External bus logic unit
Contents
1. JITK Putting the O Activating a FLASH memory out Part 2 Agenda e Processors need to send out conti signals high low 1 0 true false General purpose input output GPIO oH processor chip 16 FLASH memory chip has additional o ports connected to Ez Lite KIT LED s e Making the FLASH memory I O port control the Ez KIT LED s e The new Blackfin assembly language instructions needed l pe Blackfin 1 0 pins REVIEW L ma He AND CONTROLLER eS Sora WATCHDOG TIMER ON CORE TIMER f wis UARTPORT k rH eration eH hia er H a lt a CORE SYSTEM BUS INTERFACE oe aoe gt me EE SERIAL PORTS 2 k gt Boor ow ROM EXTERNAL PORT FLASH SDRAM CONTROL Figure 1 1 Processor Block Diagram Radio controlled car IN PRINCIPLE we could e Connect LED1 control signal to turn rigi signal line of radio transmitter e Connect LED2 control signal to forware signal line of radio transmitter e Connect LED3 control signal to left signal line of radio transmitter IN PRINCIPLE means we might start off this way wh tee W initially explore ideas to control the car However we may or may not finish the project a different way In actually fact we will use both PF1 PF5 PF6 PF7 as output to control car during the labs IN ae _ During Lab 4 we could use SPI interface so we can c control car and put LCD screen Sam S gt2. e The new Blackfin assembly language instructions needed
3. 1 to 15 eveles this memory bank General Control Register e Reset value leaves CLKOUT disabled is that important Asynchronous Memory Global Control Register EBIU_AMGCTL InitFlashCPP REVIEV e Get the FLASH to work correctly e May be many processes running on the Blackfin All these processes may want to use InitFlashCPP 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 OxFFCO0A00 fo jo Jo fo Jo Jo jo fo fia 1 Jt jo Reset 0x00F2 InitFlashCPP Core has priority over DMA 0 Disable CLKOUT for lf FLASH memory is already configured 1 DMA has priority over core Prka i ee return without re initializing sis era er aalony recs bii E aac est to avoid destroying existing code Chapter 7 Chip Bus Hierarchy region accesses AMBEN 2 0 Else Enable asynchronous memory banks 000 All banks disabled 001 Banko enabled 010 Banko and Bank1 enabled 011 Banko Bank1 and Bank2 enabled 1xx All banks Banko Bank1 Bank2 Bank3 enabled Figure 17 3 Asynchronous Memory Global Control Register 11 configure Memory Bank control register THEN configure Global control turns on the FLASH Look in EZ Kit documente Don t start from scratch Look Tor recommended settings These settings are specific for FLAS memory used on the EZ Kit Lite Table 2 4 Asynchronous Memory Control Registers Settings Example C EBIU_AMBCTLO Ox7BRO7B
4. Error in instruc l do define PO OxFFCOOA04 Operands don t fit instruction template REG ASSIGN expr and then use Check for an out of range immediate value or an illegal register double click Previous errors prevent assembly cut and paste Assembler totals 1 error s and 0 warning s Tool failed with exit exception code 1 the label Build was unsuccessful AMA oe double clic What to look for in the following Detailed look at the WriteLED and ReadLED code you will USE rather the write during the familiarization laboratory and assignment 1 e Look at how the Blackfin assembly language syntax is used KEY ELEMENT TO USE IN LABS AND QUIZZES Must do our coding without destroying the operation of existing code functionality When using hardware this normally means the extensive use of bitwise AND and OR operations WriteFlashLEDASM long inV USER CASE STUDY TASK Write on or 0 off to the Port to activate LEDs connected to pins PB5 gt PBOF leavina other pins unchanaed 4 Table 2 9 Flash A Port B Controls CC WriteFlashLEDASM long in 1 Read 8 bit LED data register into 32 bit processe data register R1 makes a copy 2 Keep top 2 bits AND operation on bits 7 and 6 of copied value in R1 3 Keep bottom 6 bits of in par 32 bit in_value ROJ OR the two processor data registers 5 Write modified copy back int
5. Keep top 2 bits AND PERE ous of copy define TOP2BITS MASKVALUE O0xC define TOP2BITS MASKVALUE OxC unsigned long top2BitMask TOP2BITS_MASKVALUE define top2BitMask_R2 R2 top2BitMask_R2 TOP2BITS MASKVALUE ledDataCopy ledDataCopy amp top2BitMask ledDataCopy_R1 LedDataCopy_R1l amp top2BitMask_R2 f R2 is now dead could re use Keep bottom 6 bits in par 32 bit in_value define BOTTOMEBITS MASKVALUE axa define ROTTOMGBITS__ MASKVALUE Ox3F f unsigned long bottom6BitMask BOTTOM6BITS MASKVALUE define bottom6BitMask_R3 bottom6BitMask_R3 BOTTOM6BITS_ aa la R3 in_value invalue amp bottom2BT sk in_value_RO in_value_RO amp bobeewGa tue R3 Fixed typo R3 is now dead could reuse OR the two processor data nen auars ledDataCopy ledDataCopy in_value Still another ledDataCopy_R1 ledDataCopy_R1 in_ Seige RO syntax Write modified co back ane LED data register a 239927992 problem WriteFlashLEDASM END RTS 8 bit and 32 bit writes Chapter 6 of instruction user manual PO RO 32 bit write 4 bytes Places all 32 bits of processor data register into long word 32 bit address starting at memory location BO If PO 0x1000 then place 32 bit val at memory location 0x1000 B PO RO 8 bit write Places bottom 8 bits of 32 bit processor data register into byte 8 bit address starting at memory location
6. PO to point to EBIU_AMBCTLO PO BIU_AMBCTLO NEW VIP BLACKFIN INSTRUCTION SSYNC Finish all pipelined operations as this processor can delay doing writes until convenient before continuing SSYNc SSYNC Programming manual page 16 q I a 1 Then RO 0x7BB07BB0 RO Ox BBO 7BBO Then P0 RO P0 RO Then make sure write occurs NOW FlashlUltiltiesAS Obvious probiem value neei EBIU_AMBCTLO e LOOK IN THE MANUAL CHAPTER Asynchronous Memory Bank Control 0 Register EBIU_AMBCTLO 31 30 29 28 27 26 25 24 2 21 20 19 18 IZ BiRDYEN moi a ammar OxFFCO 0A04 Reset OxFFC2 FFC2 able void InitFlashASM void for accesses to section program global _InitFlashaASn InitFlashaASH it FLASH memory already configured return without initializing Else Order configure Memory Bank control Set PO to point to EBIU_AMBCTLO define EBIU_AMBCTLO O0xFFCO OA04 PO BIU_AMBCTLO Is the following the correct code to use in C Then RO Ox 7BBO7BBO RO Ox BBO 7BB0 errors Then P0 RO define pBIU_AMBCTLO int OxFFCO 0A04 P0 R0 FIND TH Then make sure write occurs NOW aa this processor can delay doing writes until convenient SSYNC SSYNC Programming manual page 16 8 roject Group 1 project FlashMemory Corrected code still fal Get equivalen
7. We don t access this memory Enable asynchronous memory location using an pointer register P0 banks with value 0xFFC0 0A00 2g aa aa Instead we include lt blackfin h gt and use a pointer value EBIU_AMGTCL Software engineering abstraction concept igure 17 3 Asynchronous Memory Global Control Register PERIPHERAL r VALUE XFFCO 0A00 o jo fo jo o Jo fo fo SERA gama Reset 0x00F2 0 Disable CLKOUT for asynchronous memory 001 Banko enabled 010 Banko and Bank1 enabled USE ALL _ 911 Banko Bank1 and Bank2 enabled 1xx All banks Banko Bank1 Bank2 Bank3 enabled gi ASK ME HOW DO YOU CODE 1XX CODING VALUE 001 IS EASY 16 Key issues REVIEW InitFlashCPP Register Value Function S O EBIU_AMBCTLO Ox7BBO7BB0 Timing tvnlintnicieds i for Banks and 0 EBIU_AMBCTLI bits 15 0 Ox7BB0 Timing control for Bank 2 Bank 3 is not used EBIU_AMGCTL bits 3 0 Enable all banks Does not sound too big a deal IN PRINCIPLE 1 Set pointerto EBJU_AMBCTLO address 2 Then set value 0x7BB0O7BBO 3 Then store value at EBIU_AMBCTLO pt value 4 Then make sure write occurs NOW as this processor ci delay doing writes until convenient This processor is designed to do writes when it is not busy doing MAN reads e Do the same for the other 32 bit FLASH registers Build and Test Stub RE What we want to do pseudo code 74 woi
8. d duri ring TV flashing ship lab LEDs connectec IAFFE 33 4 i ee es A A ee LE Ada ee ogg ve ae ce E gg la le le le la l lal l Te eee ee ee eases wh O TETEE amp z a J rT ET rT rT mh rJ ra ra F r3 ra r3 Tra w a a a z z a i a fa fa fa fa o 5 5 mh r g AS F a a PH a a a a a a e a aa aa a n S BACK DONE POWER ON These pins might be connected to iw other things m WPS A DON T CHANGE THEIR EPEE EHAVIOUR Activating LEDs REVIE e Get the FLASH to work correctly Performed by nitFlashCPP e Get the Port to work correctly as output pins PB5 gt PBO leaving other pins unchanged in behaviour Performed by nitFlashPortCPP e Write the value we want to LEDS WriteFlashLEDASM int value WriteFlashLEDCPP int value e Read back the value the LEDs show int ReadFlashLEDASM void int ReadFlashLEDCPP void EBIU External BUS Intertac Unit REVIEW How does EBIU know whether to execute your c riting the data to FLASH LEDs live there or SDRAM memory Large arrays live there TK Just In Time Knowledge WAIN rather than WAI EXTERNAL BUS CONTROLLER ae FLASH DATA 15 0 ANSWER Blackfin Memory Map fp e McVASH control ADSP BF533 MEMORY MAP D a i mm logic ideas again oxeFE0 ooo ORE eS e LDF file controll
9. pointed to by pointer register PO 8 bit and 32 bit reads e RO P0 32 bit read 4 bytes Places all 32 bits of long word 32 DE address starting at memory location PU into processor data register F If PO 0x1000 then place 32 bit at memory location 0x1000 RO B P0 Z 8 bit read Places byte 8 bit address starting at memory location PO into bottom 8 bits of processor data register and puts 0 into the top 24 bits of register Must convert 8 bit read operation into a 32 bit store in register operation o D d Add byte read and write ope section progr global _WriteF lashLEDASM Zr define in_value_RO RO WriteFlashLEDASH PROBLEM byte read and writes void WriteFlashLEDASM long in_value in RO Is this correct for keeping top 2 bits of an 8 es Sel sae horse aA aes processor data register makes a copy bit value Con ned long so ve can co the sath E define LED DATA REGISTER ADDRESS 0 2027 ooog PO L LED DATA_ eae ADDRESS PO H hi LED DATA REGISTER ADDRESS ledDataCopy_R1 B P0 Z f unsigned long ledDataCopy define ledDataCopy_R1 R1 DEFECT if K top 2 bite AND ie ya of copy w define TOP2BITS_MASKVALUE 0xC not corrected define TOP2BITS_MASKVALUE OxC signed long top2BitMask TOP2BITS_N AMW define top2BitMask_R2 R2 top2BitMask_R2 TOP2BITS MASKVAL
10. BO Timing Ttmettiivimiadh for Banks 1 and 0 EBIU_AMBCTL1 bits 15 0 0x7BB0 Timing control for Bank 2 Bank 3 is not used EBIU_AMGCTL bits 3 0 Enable all banks Turns on clock Each Flash chip is initially configured with the memory sectors mapped into the processor s address space as shown in able 2 5 13 Set the Bank control reg Kit documentation recommends 0x7BBO What does this setting da PERIPHERAL REGISTER ADDRESS PERIPHERAL REGISTER RESET VALUE Memory Bank Control 0 Registr EBIU_AMBCTLO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 aoe Herp peee eee Reset 0xFFC2 FFC2 BiWAT 3 0 Bank 1 write access time number of 7 cycles cycles AWE is held asserted 0000 Not supported not 15 0001 to 1111 1 to 15 cycles BiRAT 3 0 Bank 1 read access time number of cycles ARE is held asserted 0000 Not supported 0001 to 1111 1 to 15 cycles B1HT 1 0 Bank 1 hold time number of cycles between AWE or ARE deasserted and AOE deasserted 00 0 cycles 01 1 cycle 10 2 cycles 2 cycles 11 3 cycles BiST 1 0 Bank 1 setup time number of cycles after AOE asserted before AWE or ARE asserted 11 not 15 B 1011 01 1 le for bank t iti 3 cycles 90 4 aces 4 10 2 oycles for bank transition 10 2 cycles cycles 11 3 cycles for bank transition 11 3 cycles 15 14 13 12 1110 9 8 76 5 4 83 210 ttt th fs fs ft eo o flo Jo Jo BOWAT 3 0 Bank 0 write access ti
11. UE ledDataCopy ledDataCopy amp top2BitMas ledDataCopy_R1 LedDataCopy_R1 amp top2 BitMask_R2 Still syntax R2 is now dead could re use problems Keep bottom 6 bits of in par 32 bit in_value ERRORS define BOTTOMSBITS MASKVALUE Ox3F define BOTTOM6BITS_MASKVALUE 0x3F unsigned long bottom6BitMask BOTTOM6 define bottom6BitMask_R3 R3 bottom6BitMask_R3 BOTTOM6BITS _ ae eat be Fix as in_value invalue amp bottom2BitMask in_value_RO in_value_RO amp EA cee R3 exercise 7 7 R3 is now dead could reuse OR the two processor data registers ledDataCopy ledDataCopy in_value Test by using ledDataCopy_R1 ledDataCopy_R1 in_value_RO 5 instead of my Write modified copy back into LED data register z BIPO ledDataCopy_R1 code in Labs WriteFlashLEDASM END RTS 32 1 InitFlashPortCPP to comp e Set direction to 1 on lower pins leaving othe direction values unchanged Read direction byte register into process data register makes a copy Set another processor data register to Ox3k OR the two data registers HOW Agenda e Processors need to send out coni signals high low 1 0 true falsi General purpose input output GPIOGn processor chip 16 FLASH memory chip has additionali O ports connected to Ez Lite KIT LED s e Making the FLASH memory I O port control the Ez KIT LED s
12. d InitFlashASM void CHANGED TO InitFlashCPP fe It FLASH menory already configured ae return without initializing ee Else Ae Order is inportant ee configure Memory Bank control register oe THEN configure Global control fe turna on the FLASH ee fe t wold InitFlashaAsSW void section program global _InitFlashasH Inite hASH fe FLASH memory already configured ee return without initializing ee Else AA Ordera important Ta coni igirs Memory Bank contro egister EF THEN config pa Global cp ol F dafis on the FLASH fe oe al When stub is tested add co The System Synchronize SSYNC instruction forces all speculative tran sient states in the core and system to complete before processing continues Until SSYNC completes no further instructions can be issued to the pipeline The SSYNC instruction performs the same function as Core Synchronize CSYNC In addition SSYNC flushes any write buffers between the L1 memory and the system interface and generates a Synch request signal to the external system The operation requires an acknowledgement ignal b s ore completi instructio void InitFlashASM void section program global _InitFlash SH I A taiias en ERROR WHEN WRITING A E If FLASH 1 d 3 d __ ae 7 7 lt en rotura without iait ate tas AVOID SAME PROBLEM II ZZ Z2 configure Memory Bank control register Order is important Set
13. ed i 0000 et 15 If PO pointer oran soo e scraTcHpab sea ES npo orraa maoo e RESERVED SSS g o register is set to ap pi lt 13 address 0x20001000 DFF A0 C00 ea then leer INTERNAL RO W PO Z oxFF90 2000 RESERVED MEMORY reads a 32 bit value en from FLASH BANK 0 OxFF90 0000 plein e If RO is 6 and oxFFe0 0000 s DATA BANKA SRAM Reservo PO is 0x0000 1000 oxEFO 0o00 then aes RO B P0 ROR o vamo taseen pe Ze places an 8 bit value in NC BANK 0 SDRAM memory A FLASH registers REVIE Bank control register RE How does Blackfin match itself for Reset value will probably work as is bt fastest FLASH operation not efficient slow reads Depends on which FLASH is used in the Efficiency not normally a problem if op not doneo EZ Lite KIT from a specific manufacturgi Asynchronous Memory Bank Control 0 Register EBIU_AMBCTLO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OCUN a Ea a BiRDYEN Bank 1 ARDY enable 0 Ignore ARDY for accesses to this memory bank 1 After access time countdown OxFFCO 0A04 Reset 0xFFC2 FFC2 BiWAT 3 0 Bank 1 write access time number of cycles AWE is held asserted 0000 Not supported 0001 to 1111 1 to 15 cy EBIU Programming Model B1RAT 3 0 use state of ARDY to deter This section describes the programming model of the EBIU This model is Bank 1 read acc
14. ess time number of mine completion of access cycles ARE is held asserted BiRDYPOL Bank 1 ARDY polarity 0 Transaction completes if ARDY sampled low 1 Transition completes if ARDY based on system memory mapped registers used to program the EBIU rt BINT 1 to 15 cycles There are six control registers and one status register in the EBIU They Bank 1 hold time number of cycles between AWE or ARE deasserted and AOE deasserted sampled high 00 0 cycles B1iTT 1 0 are 01 1 cycle Bank 1 memory transition time 10 2 cycles number of cycles inserted after a E gt 11 3 cycles read access to this bank and a BiST 1 0 before a write access to this bank Asynchronous Memory Glo bal Control register E BI U_AMG CT L Bank 1 setup time number of cycles after AOE or a read access to another bank lt gt _ gt asserted before AWE or ARE asserted re adore dlc br ene 00 4 cycles 1 cycle for bank transition Asynchronous Memory Bank Control 0 register EBIU_AMBCT LO 01 1 cycle 10 2 cycles for bank transition 10 2 cycles 11 3 cycles for bank transition 11 3 cycles 15 14 13 12 1110 9 8 76 543 210 Asynchronous Memory Bank Control 1 register EBIU_AMBCTL1 gggg gpggg ECC CRG ceca ne BORDYEN Bank 0 write access time number of e SDRAM Memory Global Control register EBIU_SDGCTL cycles AWE is held asserted Bank 0 ARDY enable 9 0000 Not supported 0 Ignore ARDY for accesses to 10 0001 ta 1111
15. me number of cycles AWE is held asserted 0000 Not supported 0001 ta 1111 1 ta 15 eveles TT BiRDYPOL BiTT 1 0 BiRDYEN Bank 1 ARDY enable Ignore ARDY for accesses to this memory bank 1 After access time countdown use state of ARDY to deter mine completion of access Bank 1 ARDY polarity 0 Transaction completes if ARDY sampled low 1 Transition completes if ARDY sampled high Bank 1 memory transition time number of cycles inserted after a read access to this bank and before a write access to this bank or a read access to another bank 00 4 cycles for bank transition BORDYEN Bank 0 ARDY enable 0 Ignore ARDY for accesses to this memory bank 14 Control access speed RE DATA LATCHED TRANSITION SETUP READ ACCESS HOLD TIME i _ 2 CYCLES 2CYCLES 1 CYCLE 1 CYCLE AMS X ABEI1 0 l L i f ADDR 19 1 DATA 15 0 Figure 17 6 Asynchronous Read Bus Cycles 15 Set General Control Re Documentation says set to OxF ft this particular FLASH chip Asynchronous Memory Global Control Regi DRESS 15 141312 11 10 9 8 EBIU_AMGCTL CDPRIO Lee 0 Core has priority over DMA for external accesses 1 DMA has priority over core ENA LE region accesses for external accesses 1 Enable CLKOUT for For more information please see asynchronous memory Chapter 7 Chip Bus Hierarchy region accesses 3 AMBEN 2 0 Note
16. o LED data reg gt those Table 2 6 Flash A Configuration Registers for port A B 0x2027 0007 26 Standard ENCM36Y assembly problem but using different synt Start with the stub and pseudo code of user case study Use the real C as psuedo code when we know what to Use a description otherwise section progra global _firiteF lashLEDASM f void WriteFlashLEDASM long in_value EA in RO WriteFlashLEDASH PROBLEM byte read and writes unsigned long ledDataCopy Read LED data register into processor data register makes a copy Convert byte into unsigned long so we can do the math SF TIECTT Keep top 2 bits AND operation of cop define PTOP2BITS__ MASKVALUE OxC unsigned long top2BitMask TOP2BITS_MASKVALUE lJedDataCopy ledDataCopy amp top2BitMask Keep bottom 6 bits of in par 32 bit in_value define BOTTOM6BITS MASKVALUE Ox3F f unsigned long bottom2BitMask BOTTOM6BITS MASKVALUE f in_value invalue amp bottom2BitMask OR the two processor data Bi rial ledDataCopy ledDataCopy in_value 4f Write modified copy back ay LED data register 5 7 222227222 Typo bottom6bitmask WriteFlashLEDASM END RTS 27 WriteFlashLEDASM END RTS Now identify the registers t e Input value In_par come in RO e We can use R1 R2 and R3 without saving section prog
17. r global _firiteF lashLEDASN void WriteFlashLEDASM long in_value 7 in RO define in_value_RO RO WriteFlashLEDASM PROBLEM byte read and writes f unsigned long ledDataCopy define ledDataCopy_R1 Ri Read LED data register into processor data register makes a copy f Convert byte into RSDR g so we can do the math Keep top 2 bits AND a acl of cop d Bae TOP2BITS_ MASKVALUE OxC ey unsigned long top2BitMask TOP2BITS_MASKVALUE define top2BitMask_R2 R2 ledDataCopy ledDataCopy amp top2BitMask R2 is now dead could re use Keep bottom 6 bits of in par 32 bit in_value define BOTTOM6BITS_MASKVALUE 0x3F unsigned long bottom2BitMask BOTTOM6BITS_MASKVALUE define bottom2BitMask_R3 R3 in_value invalue amp bottom2BitMask R3 is now dead could reuse OR the two processor data registers ledDataCopy ledDataCopy in_value Write modified copy back into LED data register 77 121020707 Typo bottom6bitmask Add in the code we understa section progra global _HriteF lashLEDASH void WriteFlashLEDASM long in_value Ved in RO define in_value_RO RO WriteF lashLEDASH PROBLEM byte read and writes unsigned long ledDataCopy define ledDataCopy_R1 Ri Read LED data register into processor data register makes a copy Convert byte into unsigned long so we can do the math SF TAITI f
18. s into 32 b registers You can t load a 32 bit register with a 32 bit immediate value using one instruction WRONG RO 0x7BB07BB0 e Must load low 16 bit of register RO L 0x7BBO e Then load high 16 bits of register RO H 0x7BO00 e You must load addresses into PO the same way You write the code to replace PO OxFFCOOA04 In C code a similar error is using unsigned int value 32 bits when you meant to use unsigned short value 16 bits 7 Dypropet FlashUtitiesas code D FlashMemory More readable ASM code ex include macros h Project Group 1 project void InitFlashASM void section progr B a Source Files global _Ini PF lachaSi InitFlashASh E FlashUtilties4SM asm Se If FLASH memory already configured fo a Linker Files 7 return without initializing hanas an Header Files a4 Else Order is important ef configure Memory Bank control register Set PO to point to EBIU_AMBCTLO define EBIU_AMBCTLO OxFFCOOA04 PO EBIU_AMBCTLO YOU FIX THIS COD Then RO Ox BBO07BB0 RO L Ox BBO RO H Ox BBO More readable code define FLASH_ CONTROLO_ RESET_VYALUE 0x7BB07BB0 RO L lofFLASH_CONTROLO_RESET_VALUE RO H hifFLASH CONTROLO_RESET_VALUE Then P0 RO P0 RO s Self documenting Configuration FlashMemory Debug SF hUtilitiesaASM asm 66 Erfor ea5003 FlashUtilitiesASM asm 26 Semantic
19. t errors in a GG 7 Old nite ashSe vod No in a define statement section program global _InitFlashASM J InitFlash SH i 2 7 If FLASH memory already configured Linker Files SA aR range FlashMenory Debug FlashUtilitiesaASH a Error ea5003 FlashUtilitiesASM asm 25 Semantic Error in instruction PO OxFFCOOA04 E Header Files EA return without initializi PEA Else fT r is 7z configure Memory Bank c registi ag J5 a No spaces in Set PO to point to EBIU_AMBCTLO b define EBIU_AMBCTLO OxFFCOOA04 PO EBIU_AMBCTLO aad Then RO Ox BBO 7BBO RO Ox BBO 7BBO Then P0 RO P0 RO Spell check GG 59 GG 59 as this processor can delay doing writes until con 0 not O SSYNC SSYNC Programming manual page 1 DEFECTS in code _FlashUtitiesAS process Pair programming cost if not caught Then make sure write occurs NOW Operands don t fit instruction template REG ASSIGN expr Check for an out of range immediate value or an illegal register by partner Error ea5003 FlashUtilitiesASM asm 28 Semantic Error in instruction 3 5 RO 0x7BB07BB0 Operands don t fit instruction template REG ASSIGN expr Check for an out of range immediate value or an illegal register Previous errors prevent assembly e a MIPS and Blackfin behave sam putting 32 bit number
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