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Errata Sheet

1. n lowest 4 bit hex number Example V21 V23 V3A V3F etc TC1736 EES AA ES AA AA 53 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Application Hints HYS TC H001 Effective Hysteresis in Application Environment Pad hysteresis values are specified for a noise free environment The methodology of measuring the hysteresis on product level comprises noise due to clock signals program execution and device activity etc This can lead toa measurable hysteresis that is smaller than it really is Therefore hysteresis should be checked again in the real target application at system level The measured hysteresis in a noise free environment is within the specified product limits MSC_TC H007 Start Condition for Upstream Channel The reception of the upstream frame is started when a falling edge 1 to 0 transition is detected on the SDI line In addition reception is also started when a low level is detected on the SDI line while the upstream channel was in idle state i e when the upstream channel is switched on bit field URR in register USR is set to a value different from 000 and the SDI line is already on a low level or after a frame has been received and the SDI line is on a low level at the end of the last stop bit time slot e g when the SDI line is permanently held low Therefore make sure that the SDI line is pulled high e g with an internal or external pull up while no transmission is performed
2. MultiCAN AI H005 TxD Pulse upon short disable request If a CAN disable request is set and then canceled in a very short time one bit time or less then a dominant transmit pulse may be generated by MultiCAN module even if the CAN bus is in the idle state Example for setup of the CAN disable request CAN CLC DISR 1 and then CAN CLC DISR 0 TC1736 EES AA ES AA AA 54 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Application Hints Workaround Set all INIT bits to 1 before requesting module disable MultiCAN AI HO06 Time stamp influenced by resynchronization The time stamp measurement feature is not based on an absolute time measurement but on actual CAN bit times which are subject to the CAN resynchronization during CAN bus operation The time stamp value merely indicates the number of elapsed actual bit times Those actual bit times can be shorter or longer than nominal bit time length due to the CAN resynchronization events Workaround None MultiCAN TC H002 Double Synchronization of receive input The MultiCAN module has a double synchronization stage on the CAN receive inputs This double synchronization delays the receive data by 2 module clock cycles If the MultiCAN is operating at a low module clock frequency and high CAN baudrate this delay may become significant and has to be taken into account when calculating the overall physical delay on the CAN bus transceiver delay etc MultiCAN _TC H003 Message may
3. SSC _AI 024 SLSO output gets stuck if a reconfig from slave to master mode happens The slave select output SLSO gets stuck if the SSC will be re configured from slave to master mode The SLSO will not be deactivated and therefore not correct for the 1st transmission in master mode After this 1st transmission the chip select will be deactivated and working correctly for the following transmissions TC1736 EES AA ES AA AA 47 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations Workaround Ignore the 1st data transmission of the SSC when changed from slave to master mode SSC _AI 025 First shift clock period will be one PLL clock too short be cause not syncronized to baudrate The first shift clock signal duration of the master is one PLL clock cycle shorter than it should be after a new transmit request happens at the end of the previous transmission In this case the previous transmission had a trailing delay and an inactive delay Workaround Use at least one leading delay in order to avoid this problem SSC _AI 026 Master with highest baud rate set generates erroneous phase error If the SSC is in master mode the highest baud rate is initialized and CON PO 1 and CON PH 0 there will be a phase error on the MRST line already on the shift edge and not on the latching edge of the shift clock e Phase error already at shift edge The master runs with baud rate zero The internal clock is derived from t
4. i 1 Timer_2 DECR 0 R DECR Of R DECR OJR DECR O R DECR Of R Start_chan2 _ gt gt Start shifted progr timer rate progr timer rate 2 Spec comform feature Timer_2 1 i 1 i i DECR O R DECR 0 R i DECR Of R DECR OIR i gt gt gt Start shifted prog timer rate prog timer rate Note the programmed timer rate is much longer than the conversion time this means that the fault is much smaller than in the picture Figure 1 Timing concerning equidistant multiple timers Workaround Use one timer base in combination with neighboring trigger and selection by software which result has to be taken into account FIRM_TC 010 Data Flash Erase Suspend Function This problem affects devices with microcode version V11 see FIRM_TC H000 for identification of the microcode version A sector DFx in the Data Flash may not be correctly erased when two successive erase operations are executed without any programming between TC1736 EES AA ES AA AA 33 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations the erase operations as described in the following sequence x y 0 or 1 x y 1 A Program Flash sector or a Data Flash sector DFy or DFx has been erased 2 An erase command on Data Flash sector DFx is issued 3 While the erase ope
5. made to the LMB bus by all other LMB Masters e g LFl LMB Master Hint Do not perform a DMA channel MLI Cerberus or DMA FPI Slave access to a reserved address all areas specified as reserved in the Memory Map Chapter LMB Address Map Table must not be accessed by the DMA ME MLI Cerberus TC1736 EES AA ES AA AA 27 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations Workaround The LMB Bus Control Unit can recognise a DMA LMB Master access to an unrecognised slave It can be programmed to raise an interrupt and then generate a Class 3 Application Reset to clear the lock up state DMI_TC 014 Problems with Parity Handling in TriCore Data Memories A small number of cases exist in which the handling of parity errors in the TriCore data memories LDRAM DCache and Data Cache Tag does not function correctly potentially leading to data corruption for accesses to these memories This data corruption may occur whether the access to one of these memories is from the TriCore CPU or in the case of LDRAM from another bus master access via the LMB Workaround In systems where the Data Memory parity handling must be enabled the following is required to guarantee correct behaviour e Compatibility mode must be selected for the TriCore Data side memories by setting COMPAT DIE 1g In this case parity errors are signalled to the SCU and returned to the CPU as an NMI trap rather than as a DIE trap directly
6. request data dan H loss of arbitration Y Iset Iselu data Set data MultiC AN pee object poise object P object f ae clear clear set clear NEWDAT NEWDAT NEWDAT by HW by HW by HW Figure 2 Loss of Arbitration TC1736 EES AA ES AA AA 56 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Application Hints OCDS TC H001 IOADDR may increment after aborted O_ READ BLOCK If an O_READ_BLOCK instruction is aborted by the host switching the TAP controller to the update DR state before enough data bits have been shifted out it may happen under certain clock ratios that the IOADDR register is incremented nevertheless This will result in an access to the wrong data in the succeeding O_READ_ or O_WRITE_ instruction Workaround As the host is actively causing the abort it should be fully aware of the situation The workaround now simply is to rewrite the IOADDR register using the IO_SET_ADDRESS instruction after each aborted block transfer Note This usually is done anyway at the beginning of the next transaction OCDS TC H002 Setting IOSR CRSYNC during Application Reset If the host is shifting in a Communication Mode IO READ_WORD instruction in the very moment an Application Reset happens the read request flag CBS_IOSR CRSYNC may be already set after the execution of the startup software A monitor program may be confused by this and drop out of the higher level communication protocol especially if the h
7. Deviations Workaround Do not issue an IO READ TRIG instruction after an IO READ_ WORD returned a set dirty bit OCDS TC 018 Startup to Bypass Mode requires more than five clocks with TMS 1 If the DAP state machine is brought to Enabled state by Power On Reset the TAP controller is fed 0 bits on its TMS input When the special sequence for Startup in Bypass Mode is detected by DAP the TAP controller already has left the Test Logic Reset state Workaround Shifting in more than five 1 bits recommendation 10 will securely bring the TAP state machine back to Test Logic Reset OCDS TC 020 ICTTA not used by Triggered Transfer to External Address In Triggered Transfer to External Address Mode bits 24 0 of the target address are fixed to the reset value of ICTTA Only the most significant byte can by changed by O_SET_TRADDR or by writing to ICTTA Note This is the behavior of the Cerberus implemented prior to AudoNG It is therefore not possible to use Cerberus as DMA work alike to move trace data to the outside world via an interface like ASC Workaround No workaround in Triggered Transfer to External Address mode possible only the fixed address xx10F068 can be used In Internal Mode however ICTTA is working as specified so for certain use cases the intended DMA functionality can be activated by a code snippet executed by the TriCore or PCP as long as the Debug Interface is not needed concur
8. LS based branch loop is mispredicted but resolution is overridden by HALT e Problem sequence 2 e 1 User code MTCR instruction to DBGSR sets HALT Mode e 2 LS based branch loop instruction e 3 LS based branch loop is mispredicted but resolution is overridden by HALT Workaround External agents should halt the CPU using the BRKIN pin instead of using CPS injected writes to the CSFR register Alternatively the CPU can always be halted by using the debug breakpoints Any user software write to the DBGSR CSFR should be followed by a dsync OCDS_TC 026 PSW PRS updated too late after a RFM instruction When a breakpoint with an associated TRAP action occurs the Tricore will enter a special trap called a debug monitor The RFM instruction return from monitor is used to return from the debug monitor trap After the RFM the CPU should resume execution at the point where it left it when the breakpoint happened On execution of the RFM instruction a light weight debug context is restored and the PSW CSFR is loaded with its new value The updated value of the PSW PRS field should then be used to select the appropriate protection register set for all subsequently fetched instructions Because PSW PRS can be updated too late after an RFM instruction the instruction following an RFM potentially sees the old value of the PSW PRS field as opposed to the new one This can be problematic since the PSW PRS field is crucial in terms of code protectio
9. all user manual versions If the version number found in this register CBS_JDPID 7 0 is less than 0x50 no CBS_JTAGID register is provided The original software algorithm shall be employed by the reused software If the version number found in this register CBS_JDPID 7 0 is 0x50 or higher the content of the CBS_JTAGID register shall be used to select the proper algorithm PORTS _TC H005 Pad Input Registers do not capture Boundary Scan data when BSD mode signal is set to high The principle of Boundary Scan is that the BSD cells can overrule the input and output data for all functional system components including port input registers In current implementation the peripheral port input registers P lt n gt _IN are however capturing the direct pad input data even when the BSD mode signal is set to high This limits the usage of INTEST Work around In case of INTEST do not read port input registers PWR_TC HO05 Current Peak on Vppp during Power up During power up a current peak may be observed on Vppp It is caused by internal cross currents generated by level shifters whose state is undefined until the core voltage reaches at least 0 5V This effect is statistical and may vary TC1736 EES AA ES AA AA 59 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Application Hints from one device to the other upon operating conditions etc This effect may only occur during power up It can not happen during power dow
10. any influence on the transaction width only word wide transfer 32 bit is implemented Workaround No workaround possible Choose source IOADDR and destination ICTTA addresses in word wide areas only OCDS_TC 015 IOCONF register bits affected by Application Reset The IOCONF register is erroneously cleared by each Application Reset Therefore Communication Mode is entered whenever the TriCore is reset As the interaction with the tool is suspended anyway due to Error State of the lOClient no immediate damage is done To resume interaction after leaving the Error State IO_SUPERVISOR instruction however the required mode must be restored by rewriting the IOCOMF register IO_CONFIG instruction Workaround After detecting an Application Reset IOINFO BUS_RST set the IOCONF register should be rewritten by the tool after the Error State is left OCDS _TC 016 Triggered Transfer dirty bit repeated by O_READ_TRIG The dirty bit appended to the data of an IO_READ_WORD instruction during Triggered Transfer mode indicates that there was at least one extra trigger event missed prior to capturing the transmitted data The dirty bit is therefore cleared after each IO READ_ WORD A consecutive IO READ TRIG instruction however will erroneously undo the clear The next IO_READ_WORD will then again see a set dirty bit even if no trigger was missed TC1736 EES AA ES AA AA 39 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional
11. be discarded before transmission in STT mode If MOFCRn STT 1 Single Transmit Trial enabled bit TXRQ is cleared TXRQ 0 as soon as the message object has been selected for transmission and in case of error no retransmission takes places Therefore if the error occurs between the selection for transmission and the real start of frame transmission the message is actually never sent TC1736 EES AA ES AA AA 55 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Application Hints Workaround In case the transmission shall be guaranteed it is not suitable to use the STT mode In this case MOFCRn STT shall be 0 MultiCAN TC H004 Double remote request Assume the following scenario A first remote frame dedicated to a message object has been received It performs a transmit setup TXRQ is set with clearing NEWDAT MultiCAN starts to send the receiver message object data frame but loses arbitration against a second remote request received by the same message object as the first one NEWDAT will be set When the appropriate message object data frame triggered by the first remote frame wins the arbitration it will be sent out and NEWDAT is not reset This leads to an additional data frame that will be sent by this message object clearing NEWDAT There will however not be more data frames than there are corresponding remote requests remote remote CAN Bus request
12. c d0O dl Circular Buffer wrap 32 32 CPU_TC 109 Circular Addressing Load can overtake conflicting Store in Store Buffer In a specific set of circumstances a load instruction using circular addressing mode may overtake a conflicting store held in the TriCore1 CPU store buffer The problem occurs in the following situation The CPU store buffer contains a byte store instruction st b targeting the base address 0x1 of a circular buffer A word load instruction Id w is executed using circular addressing mode targetting the same circular buffer as the buffered byte store This word load is only half word aligned and encounters the circular buffer wrap around condition such that the second wrapped access of the load instruction to the bottom of the circular buffer targets the same address as the byte store held in the store buffer Additionally one of the following further conditions must also be present for the problem to occur The circular buffer base address for the word load is double word but not quad word 128 bit aligned i e the base address has bits 3 0 0x8 with the conflicting byte store having address bits 3 0 0x9 OR The circular buffer base address for the word load is quad word 128 bit aligned and the circular buffer size is an odd number of words i e the base TC1736 EES AA ES AA AA 15 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations address has bits 3 0 0x0 w
13. effect ERROR Response The DMA LMB Master will treat this error response as its own It will clear the lock up state and return an error to the DMA access requester Normal operation will then continue Halted DMA access requests will resume There is no corruption of the data flow e NSC No Special Condition Acknowledge The DMA LMB Master will treat this response as its own and again clear the lock up state The correct response to an unrecognised slave is an ERROR Therefore the DMA LMB Master has signalled an invalid response back to the DMA access requester resulting in a corruption of the data flow e RETRY Response The DMA LMB Master will treat the retry response as its own and again clear the lock up state The access will be repeated to the same reserved address location again resulting in a lock up condition The sequence is broken by the first ERROR response or NSC acknowledge The effect of a DMA LMB Master Write accesses to an unrecognised slave is the same as above with one exception Ifthe next access is a Read access from the EBU LMB Slave then the DMA LMB Master will clear the lock up state and respond as above The EBU read completes but the data read by the Originator e g TriCore will be the write data of the DMA LMB Master Write access The following should be noted e Atall times the DMA FPI Master and DMA FPI Slave remain accessible e If the LMB DMA Master is in the lock up state then accesses can still be
14. frequency of the analog part fang Or fana respectively near the maximum value specified in the Data Sheet and 2 to switch the ADC to a power saving state via ANON while no conversions are performed Note that a certain wake up time is required before the next set of conversions when the power saving state is left Note The selected internal operating frequency of the analog part that determines the conversion time will also influence the sample time ts The sample time t can individually be adapted for the analog input channels via bit field STC CPU_TC H004 PCXI Handling Differences in TriCore1 3 1 The TriCore1 3 1 core implements the improved architecture definition detailed in the TriCore Architecture Manual V1 3 8 This architecture manual version continues the process of removing ambiguities in the description of context save and restore operations a process started in Architecture Manual V1 3 6 released October 2005 1 Symbol used depends on product family e g fana is used in the documentation of devices of the AUDO NextGeneration family TC1736 EES AA ES AA AA 51 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Application Hints Several previous inconsistencies regarding the updating of the PCXI and the storing of PCXI fields in the first word of a CSA are now removed e CALL has always placed the full PCXI into the CSA e BISR has always placed the full PCXI into the CSA e SVLCX has always placed the fu
15. sensitive the interrupt handler can simply complete and it s terminating RFE will correctly TC1736 EES AA ES AA AA 22 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations return execution to the first instruction of the trap handler where it will now execute to completion without undesired interruption If the interrupted traps are considered recoverable but are time sensitive and need to be executed immediately then some method of deferring the interrupt processing is required If the test of the situation e g checking the PCXI PIE bit is clear is at the start of the Interrupt handler then there are two simple methods to consider The first method would be to re request the interrupt by writing the appropriate Service Request Control Register with the SETR bit set to one and then executing an RFE which will be taken back to the trap handler The interrupt will now be pending again but will not be taken until the trap handler executes its RFE to re enable interrupts This method is simple if the device and hence it s SRC register address generating the interrupt is known If this is not easy to determine statically or dynamically the second method might be preferred The second method would be to jump to the trap handler after setting the trap identification number TIN and the return address which the trap handler will use to be the next instruction in the interrupt handler This relies on the f
16. the end of a transmission This requires some special considerations e g when polling for the end of a transmission In master mode when register TB has been written while no transfer was in progress flag STAT BSy is set to 1 after a constant delay of 5 FPI bus clock cycles When software is polling STAT BSy after TB was written and it finds that STAT BSY 0p this may have two different meanings either the transfer has not yet started or it is already completed Recommendations In order to poll for the end of an SSC transfer the following alternative methods may be used e either test flag RSRC SRR receive interrupt request flag instead of STAT BSY e or use a software semaphore that is set when TB is written and which is cleared e g in the SSC receive interrupt service routine TC1736 EES AA ES AA AA 62 62 Rel 1 2 26 02 2010
17. the remaining 7 bits are shifted right one bit position and the incoming bit becomes the new MSB Upon entry to the Update IR state the content of the internal shift register is copied into the INSTRUCTION register unconditionally If the final state of the shift register happens to be a valid but unintended instruction the device may enter a state very detrimental to the application An extreme example is the INTEST instruction which turns off all outputs of the device and is activated by instruction 01 i e if no bit at all is shifted in by the host Recommendations e Always shift in at least as many bits as the INSTRUCTION register holds This means 8 bit for Infineon devices e Check the bits returned via TDO Must be 01 followed by any data shifted in excluding the last eight bits This allows to check the pipe by shifting in more than the required 8 bits e Use the protection offered by IOPATH Keeping lIOPATH different from 00 whenever possible will block all Boundary Scan functions e Do not use the DAP telegrams jtag_setIR and jtag_swapIR with n less than eight e Use the CRC protected DAP interface if the application environment may cause transmission errors on the JTAG signals TC1736 EES AA ES AA AA 38 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations OCDS TC 014 Triggered Transfer does not support half word bus trans actions The register bit CBS_IOCONF EX_BUS_HW does not have
18. to the CPU AND e Ifthe system has a data cache the data cache must be used to cache read only data only such as Flash contents Writes to cacheable locations must not be used with the Data Cache enabled Note that this does not concern the program side which works as expected DMI_TC 016 CPU Deadlock possible when Cacheable access encounters Flash Double Bit Error A problem exists whereby the TriCore CPU may become deadlocked when attempting a mis aligned load access to a cacheable address The problem will be triggered in the following situation TC1736 EES AA ES AA AA 28 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations The TriCore CPU executes a load instruction whose target address is not naturally aligned a data word access which targets an address which is not word aligned or a data address double word access which is not double word aligned e The mis aligned load access targets a cacheable address whether the device is configured with a data cache or not e The mis aligned load access spans two halves of the same 128 bit cache line For instance a data word access with address offset 6 e The mis aligned load access results in a cache miss which will refill the 128 bit cache line Data Line Buffer DLB via a Block Transfer 2 BTR2 read transaction on the LMB and this LMB read encounters a bus error condition in the second beat of the block transfer It should be noted
19. trap types FCD DAE DIE CAE or NMI In each of these circumstances the return address may be invalid Workaround None CPU_TC 113 Interrupt may be taken during Trap entry sequence A problem exists whereby interrupts are not correctly disabled at the very beginning of a trap entry sequence and under certain circumstances an interrupt may be taken at the start of a trap handler The problem occurs when an interrupt request is received by the TriCore CPU within a window spanning a single clock cycle either side of a trap condition being detected and where interrupts are enabled and the interrupt priority number is higher than the current CPU priority number CCPN In this case the trap entry sequence begins and the upper context registers are stored to the appropriate CSA However before the first instruction of the trap handler is executed the interrupt condition is detected and the interrupt handler entered at a time when interrupts should be disabled This problem affects all trap types but does not affect TC1736 EES AA ES AA AA 20 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations interrupts an interrupt cannot be taken during the entry sequence of another interrupt It should be noted that no state information is lost when this issue occurs When the interrupt handler completes and the RFE instruction is executed program execution restarts with the first instruction of the interrupted trap handler a
20. 10 Register Banks may be out of sync after FCU Trap In order to improve the performance of Upper Context Save and Restore operations Call Interrupt etc the current TriCore1 CPU implementation contains shadow registers for the upper context General Purpose Registers GPRs D8 D15 and A10 A15 forming a foreground and a background bank In normal operation read and write accesses to the upper context registers target the same bank with read and write accesses targetting different banks just during upper context save and restore operations However in a certain corner case where an FCU trap is taken read and write accesses to the register banks remain out of synchronisation in the FCU trap handler and cannot be easily re synchronised Since FCU traps are non recoverable system errors with some system state already lost maintaining correct behaviour is not critical However due to the bug it is no longer straight forward to discriminate FCU traps from other context management Class 3 traps Since the read and write pointers to the register banks are incorrect in the bug situation the update of D15 with the Trap Identification Number TIN will write to one bank whilst the read of D15 in the trap handler will read the other incorrect bank returning an invalid TIN For similar reasons the upper context GPRs are unusable in an FCU trap handler since register read and write operations may target different banks The problem occurs in th
21. A ES AA AA 34 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations 1 Erase DFx 2 Additional step Wait gt 250 ms 3 Concurrent programming of DFy may be triggered Workaround 3 Issue a reset in case of two consecutive erase operations without intermediate programming e g Erase DFx Erase DFy Additional step Reset Erase DFx if needed Concurrent programming of DFy may be triggered akwWON gt Workaround 4 After a concurrent erase on Data Flash sector DFx has been triggered verify the state of DFx In case of weak programming re erase DFx Additional step Workaround 5 Do not use concurrent erase program operations on Data Flash FLASH TC 027 Flash erase time out of specification As per specification following are the flash erase timings Table 6 Flash erase timings as per spec Flash Micro Erase Time code version P Flash 1 MByte V11 20s at cold and room temperature D Flash 32 Kbyte Both V11 1 25s at cold temperature Data Flash TC1736 EES AA ES AA AA 35 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations Flash erase timings measured on actual device are as below Table 7 Actual Flash erase timings Flash Micro Erase Time code version P Flash 1 MByte V11 26s at cold temperature 22 5s at room and above temperature D Flash 32 Kbyte Both V11 1 6s at all temperature Data Flash Maxi
22. C 026 PSW PRS updated too late after a RFM 43 instruction OCDS_TC 027 BAM breakpoints with associated halt 44 action can potentially corrupt the PC TC1736 EES AA ES AA AA 5 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet History List Change Summary Table 3 Functional Deviations cont d Functional Short Description Cha Pa Deviation nge ge RESET_TC 001 SCU_RSTSTAT PORST not set by a 45 combined Debug System Application Reset SCU_TC 016 Reset Value of Registers ESRCFG0 1 New 46 SSC_AI 022 Phase error detection switched off too 47 early at the end of a transmission SSC_AI 023 Clock phase control causes failing data 47 transmission in slave mode SSC_AI 024 SLSO output gets stuck if a reconfig from 47 slave to master mode happens SSC_AI 025 First shift clock period will be one PLL 48 clock too short because not syncronized to baudrate SSC_AI 026 Master with highest baud rate set 48 generates erroneous phase error Table 4 Deviations from Electrical and Timing Specification AC DC ADC Short Description Cha Pa Deviation nge ge DTS_TC P001 Test Conditions for Sensor Accuracy T s5 New 50 FADC_TC P003 Incorrect test condition specified in 50 datasheet for FADC parameter Input leakage current at Veagnp PLL_TC P005 PLL Parameters for fyco gt 780 MHz 50 TC1736 EES AA ES AA AA 6 62 Rel 1 2 26 02 2010 Errata Sheet Cinfineo
23. C and hence resume code execution from an erroneous location Reading the PC CSFR whilst in HALT mode will also yield a faulty value TC1736 EES AA ES AA AA 44 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations Workaround In order to avoid PC corruption the user should avoid placing BAM breakpoints with HALT action on random code which could contain conditional jumps The simplest thing to do is to avoid BAM breakpoints with HALT action altogether A combination of BBM breakpoints and other types of breakpoint actions can be used to achieve the desired functionality Workaround for single stepping An intuitive way of implementing single stepping mode is to place a halt action BAM breakpoint on the address range from 0x00000000 to OxFFFFFFFF Every time the CPU is woken up via the CERBERUS it will execute the next instruction and go back to HALT mode Unfortunately this will trigger the bug described by the current ERRATA The solution is to implement single stepping using BBM breakpoints e 1 Create two debug trigger ranges First range 0x00000000 to current_instruction_pc not included e Second range current_instuction_pc not included to OxFFFFFFFF e 2 Associate the two debug ranges with BBM breakpoints e 3 Associate the BBM breakpoints with a HALT action e 4 Wake up the CPU via CERBERUS e 5 CPU will execute the next instruction update the PC and go to HALT mode e 6 Start agai
24. Cinfineon Errata Sheet Rel 1 2 26 02 2010 Device TC1736 Marking Step EES AA ES AA AA Package PG LQFP 144 10 01708AERRA This Errata Sheet describes the deviations from the current user documentation Table 1 Current Documentation TC1736 User s Manual V1 1 October 2009 TC1736 Data Sheet V1 1 August 2009 TriCore 1 Architecture V1 3 8 January 2008 Make sure you always use the corresponding documentation for this device User s Manual Data Sheet Documentation Addendum if applicable TriCore Architecture Manual Errata Sheet available in category Documents at www infineon com TC1736 Each erratum identifier follows the pattern Module_Arch TypeNumber e Module subsystem peripheral or function affected by the erratum Arch microcontroller architecture where the erratum was firstly detected Al Architecture Independent CIC Companion ICs TC TriCore X XC166 XE166 XC2000 Family XC8 XC800 Family none C166 Family e Type category of deviation none Functional Deviation P Parametric Deviation H Application Hint TC1736 EES AA ES AA AA 1 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet D Documentation Update e Number ascending sequential number within the three previous fields As this sequence is used over several derivatives including already solved deviations gaps inside this enumeration can occur Note Devices marked with EES or ES are engi
25. Devices of the Audo Future family allow tool access via dedicated pins in two basic protocol modes DAP and JTAG To avoid changes to the application environment the tool selects the protocol to be used by signalling over the same pins later used for communication Default startup mode is two pin DAP Other modes JTAG or three pin DAP are selected by specific telegrams which need to be sent to the device TC1736 EES AA ES AA AA 41 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations One of the major advantages of DAP versus JTAG within a harsh automotive environment is its robustness regarding bit errors in the telegram transmission This is achieved by adding checksums CRC to all telegrams The only exception is the telegram to switch from DAP to JTAG see jtag_mode telegram as this telegram is potentially sent by legacy JTAG only tools not able to generate properly formatted DAP telegrams A method has been implemented to prevent the following safety hole If bit errors e g caused by EMC change another DAP telegram to the telegram meaning switch to JTAG mode a tool using DAP pins only would loose connection in an unrecoverable manner Therefore the DAP module can be configured by the tool via SFR CBS_ OSTATE DJMODE to ignore the switch to JTAG mode also called BYPASS telegram Due to an imperfection within the design the intended protection via CBS_OSTATE DJMODE does not become effective in th
26. act that the CSA saved away by the preemption of the trap handler is equally valid as an execution context for the interrupt handler The code for this method is as follows interruptN mfcr dl PCXI jnz t dl5 23 interruptReal force CSA into memory dsync sh h dl4 d15 12 insert d15 d14 d15 6 16 mov a al5 d15 load trap value of d15 from CSA ld w di5 al5 0x3Cc mov a al5 all movh a all his interuptReal lea all all los interruptReal jump to trap handler will return to interruptReal ji al5 TC1736 EES AA ES AA AA 23 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations the remaining part of the interrupt handler interruptReal Again it is preferred that this method be used immediately at the beginning of the interrupt handler since this approach works straightforwardly provided there is no state in the Upper Context registers or on the interrupt stack that is required by the interrupt handler when it returned to Although it is possible to adapt this approach to operate later during interrupt handling additional steps need to be taken to ensure the correct state is maintained when returning to the interrupt handler CPU _TC 114 CAE Trap may be generated by UPDFL instruction UPDFL is a User mode instruction implemented as part of the TriCore1 Floating Point Unit FPU which allows individual bits of the Psw user status bits PSW 31 24 to be set or cleared Contrary to early
27. alue of register SCU_ESRCFG1 is Ox00000080 instead of 0x00000090 This means that bit DFEN Ox i e the digital 3 stage median filter is disabled after a System Reset Note The 3 stage median filter operates on the FPI Bus frequency All input spikes lasting less than one FPI Bus cycle are reliably suppressed Any request lasting at least 2 FPI Bus cycles is reliably recognized Workaround In case the digital 3 stage median filter shall be enabled bit DFEN must be set to 1 by software TC1736 EES AA ES AA AA 46 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations SSC AI 022 Phase error detection switched off too early at the end of a transmission The phase error detection will be switched off too early at the end of a transmission If the phase error occurs at the last bit to be transmitted the phase error is lost Workaround Don t use the phase error detection SSC _AI 023 Clock phase control causes failing data transmission in slave mode If SSC_CON PH 1 and no leading delay is issued by the master the data output of the slave will be corrupted The reason is that the chip select of the master enables the data output of the slave As long as the chip is inactive the slave data output is also inactive Workaround A leading delay should be used by the master A second possibility would be to initialize the first bit to be sent to the same value as the content of PISEL STIP
28. ar buffer base address is quad word aligned but the buffer size is an odd number of words 0x14 5 words The byte store to address 0xD0001001 is immediately followed by a load operation and is placed in the CPU store buffer The word load instruction encounters the circular buffer wrap condition and is split into 2 half word accesses to the top 0xD0001012 and bottom 0xD0001000 of the circular buffer The first load access completes correctly but due to the bug the second access overtakes the store operation and returns the previous half word from 0xD0001000 Workaround For any circular buffer data structure if byte store operations st b are not used targeting the circular buffer or if the circular buffer has a quad word aligned base address and is an even number of words in depth then this problem cannot occur If these restrictions and the other conditions required to trigger the problem cannot be ruled out then any load word instruction Id w targeting the buffer using circular addressing mode and which may encounter the circular buffer wrap condition must be preceded by a single NOP instruction TC1736 EES AA ES AA AA 17 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations LDA al2 OxDO001000 Circular Buffer Base LDA al3 0x00140012 Circular Buffer Limit and Index st b al2 0x1l d2 Store to byte offset 0x1 nop Workaround ld w d6 al2 al3 c Circular Buffer wrap 16 16 CPU _TC 1
29. cts debugging only primarily the debugger single stepping functionality The problem may or may not be visible whilst debugging dependent upon the implementation of single stepping by the debugger If single stepping is implemented by the debugger setting Break Before Make BBM breakpoints on all instructions except the next to be executed then if this problem occurs the next instruction when single stepping will be the first instruction of the interrupt handler However if single stepping is implemented TC1736 EES AA ES AA AA 25 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations by setting a Break After Make BAM breakpoint on the next instruction to be executed or a BBM breakpoint on the next but one instruction the problem will not be visible In this case when single stepping the interrupt handler will be executed in its entirety before returning to the interrupted program flow and the breakpoint being taken after the next instruction to be single stepped Workaround As described previously this problem affects debug only and in this case the taking of the interrupt immediately upon exit from Halt mode cannot be avoided if the conditions to trigger the problem occur However the debugger single stepping functionality may be implemented in such a way that this problem does not directly affect the user as follows Upon first hitting a breakpoint the debugger should read and hold the current inter
30. cycle after BSy has returned to Ox After reset the Transmit Buffer may be written at any time SSC _AI H003 Transmit Buffer Update in Slave Mode during Transmission After reset data written to the Transmit Buffer register TB are directly copied into the shift register Further data written to TB are stored in the Transmit Buffer while the shift register is not yet empty i e transmission has not yet started or is in progress If the Transmit Buffer is written in slave mode during the first phase of the shift clock SCLK supplied by the master the contents of the shift register are overwritten with the data written to TB and the first bit currently transmitted on line MRST may be corrupted No Transmit Error is detected in this case TC1736 EES AA ES AA AA 61 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Application Hints It is therefore recommended to update the Transmit Buffer in slave mode after the transmit interrupt TIR has been generated i e after the first SCLK phase After reset the Transmit Buffer may be written at any time SSC _ TC H003 Handling of Flag STAT BSyY in Master Mode In register STAT of the High Speed Synchronous Serial Interface SSC some flags have been made available that reflect module status information e g error busy closely coupled to internal state transitions In particular flag STAT BSY will change twice during data transmission from 0 to 1 at the start and from 1 to Og at
31. d trap handler Dealing with this changed circumstance is easy provided it is considered whenever CSA s are examined or manipulated Workaround As described previously the main problem associated with this erratum is the delay that may be incurred before the servicing of certain critical trap types such as NMI if no additional action is taken If this is an issue for a system then in order to minimize the impact of this erratum it is necessary to adapt the interrupt handlers to check for the occurrence of this issue and react accordingly TC1736 EES AA ES AA AA 21 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations The occurrence of this issue may be checked for by one of two methods dependent upon whether all trap classes or just a limited set are considered timing critical If it is required to check for the occurrence of this issue for all trap classes then this may be performed by checking the value of the PCXI PIE register bit within the interrupt handlers before any further context operations such as BISR are performed If PCXI PIE is clear such that no interrupt should have been taken then this indicates the occurrence of this issue Although when this method is used then it is preferred to check the value of PCXI PIE before any further context operations are performed it is possible to use this method after additional context operations have been performed In this case it is necessary to tra
32. e following situation e FCX Free Context Pointer points to an invalid location Null End of CSA list Invalid Segment Virtual or Peripheral segment e CALL CALLA CALLI instruction is in the decode pipeline stage and would generate an FCU trap due to the invalid FCX pointer TC1736 EES AA ES AA AA 18 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations e Instruction in the Load Store pipeline execute stage encounters a synchronous trap condition VAF D VAP D MPR MPW MPP MPN ALN MEM DSE SOVF OVF which would also be converted into an FCU trap Workaround The LCX Free Context List Limit pointer should be initialised in order to trap impending context list overflow before the FCU condition is encountered However in order to maintain some system function in the case of an FCU trap the following workaround is required split into two parts Firstly the Context Management Class 3 trap handler must be modified to discriminate FCU traps that incorrectly appear to have a TIN pertaining to another Class 3 trap due to the bug This is done by checking for the correct behaviour of the upper context registers and jumping to the FCU trap handler if the register file behaviour is found to be in error _Cclass3 handler mov dl2 7 nop nop jne dl2 7 _feu handler mov di2 8 nop nop jne dl2 8 _feu handler Now read valid D15 to obtain TIN Since the initial contents of the upper c
33. ecution of the BISR instruction mfcr d15 0xFEOO bisr lt New Priority Number gt TC1736 EES AA ES AA AA 52 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Application Hints Method 2 For applications where the time prior to execution of the BISR instruction is critical the priority number of the interrupted task may be read from the CSA pointed to by the PCXI after execution of the BISR instruction bisr lt New Priority Number gt mfcr d15 0xFE00 Copy PCXI to d15 sh h di4 dl5 12 Extract PCX seg to dl14 insert d15 d14 d15 6 16 Merge PCX offset to d15 mov a ar15 als Copy to address reg ld bu di5 a15 0x3 Load byte containing PCPN Note that contrary to the TriCore architecture specification no DSYNC instruction is stricly necessary after the BISR or SVLCX instruction in either the TriCore1 3 or TriCore1 3 1 to ensure the previous CSA contents are flushed to memory In both TriCore1 3 and TriCore1 3 1 any lower context save operation BISR or SVLCX will automatically flush any cached upper context to memory before the lower context is saved FIRM _TC H000 Reading the Flash Microcode Version The 1 byte Flash microcode version number is stored at the bit locations 103 96 of the LDRAM address D000 000C after each reset and subject to be overwritten by user data at any time The version number is defined as Vsn contained in the byte as e s highest 4 bit hex number
34. en a store transaction is outstanding e g held in the CPU store buffer and the PSW is modified to switch from Supervisor to User 0 or User 1 mode In this case the outstanding store transaction executed in Supervisor mode may be transferred to the bus in User mode the bus systems do not discriminate between User O0 and User 1 modes Due to the blocking nature of load transactions and the fact that User mode code cannot modify the Psw neither of these other situations can cause a problem Example TC1736 EES AA ES AA AA 9 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations st w aX dX Store to Supervisor mode protected SFR mtcr PSW dY Modify PSW IO to switch to User mode Workaround Any MTCR instruction targeting the Psw which may change the PSW IO bit field must be preceded by a DSYNC instruction unless it can be guaranteed that no store transaction is outstanding st w aX dX Store to Supervisor mode protected SFR dsync mtcr PSW dY Modify PSW IO to switch to User mode CPU_TC 106 Incorrect PSW update for certain IP instructions dual issued with MTCR PSW In certain situations where an Integer Pipeline IP instruction which updates the PSW user status bits e g PSW V Overflow is followed immediately by an MTCR instruction targetting the Psw with the instructions being dual issued the update priority is incorrect In this case the PSw user status bits are updated with the val
35. fter a loss of connection the DAP module can be forced back to the Enabled not yet Active state by a control signal restart driven by the on chip debug logic e g CBS_OSTATE and actuated by higher level on chip tool firmware In the current design this feature is implemented as synchronous reset i e it requires clock edges inside the DAP module to work properly As DAPO is the only clock source used by DAP the reset is not sensed if DAPO is not toggled by the host at least once while restart is asserted Workaround There is no workaround available Attention Do not assert restart for longer periods of time unless the interface shall be functionally locked The bug fixed version of future devices will also reset DAP as long as restart is asserted but will additionally store the rising edge until at least two DAPO clock edges have been seen TC1736 EES AA ES AA AA 37 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations OCDS Al 002 JTAG Instruction must be 8 bit long The JTAG TAP controller implemented in all Infineon devices strictly adheres to the standard IEEE 1149 1 2001 One side effect of this standard requires special awareness as it can cause severe errors Upon entry to the Capture IR state the internal shift register is preloaded with a constant namely 01 In the Shift IR state the bits from the host are prepended i e for each incoming bit the old LSB is dropped
36. he rising and the falling edge If the baud rate is different from zero there is a gap between these pulses of these internal generated clocks However if the baud rate is zero there is no gap which causes that the edge detection is to slow for the fast changing input signal This means that the input data is already in the first delay stage of the phase detection when the delayed shift clock reaches the condition for a phase error check Therefore the phase error signal appears e Phase error pulse at the end of transmission The reason for this is the combination of point 1 and the fact that the end of the transmission is reached Thus the bit counter SSCBC reaches zero and the phase error detection will be switched off TC1736 EES AA ES AA AA 48 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations Workaround Don t use a phase error in master mode if the baud rate register is programmed to zero SSCBR 0 which means that only the fractional divider is used Or program the baud rate register to a value different from zero SSCBR gt 0 when the phase error should be used in master mode TC1736 EES AA ES AA AA 49 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Deviations from Electrical and Timing Specification 3 Deviations from Electrical and Timing Specification DTS_TC P001 Test Conditions for Sensor Accuracy Trsa Parameter Sensor Accuracy symbol Tys is not subject to production
37. ies DMI_TC 016 CPU Deadlock possible when Cacheable Upd 28 access encounters Flash Double Bit Error ate DMI_TC 017 DMI line buffer is not invalidated by a write 30 to OVC_OCON DCINVAL if cache off TC1736 EES AA ES AA AA 4 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet History List Change Summary Table 3 Functional Deviations cont d Functional Short Description Cha Pa Deviation nge jge FADC_TC 005 Equidistant multiple channel timers 32 FIRM_TC 010 Data Flash Erase Suspend Function New 33 FLASH_TC 027 Flash erase time out of specification Upd 35 ate FLASH_TC 035 Flash programing time out of specification 36 FLASH_TC 036 DFLASH Margin Control Register MARD 36 OCDS _AI 001 DAP restart lost when DAPO inactive 37 OCDS_AI 002 JTAG Instruction must be 8 bit long 38 OCDS_TC 014 Triggered Transfer does not support half 39 word bus transactions OCDS_TC 015 IOCONF register bits affected by 39 Application Reset OCDS_TC 016 Triggered Transfer dirty bit repeated by 39 IO_READ_TRIG OCDS_TC 018 Startup to Bypass Mode requires more 40 than five clocks with TMS 1 OCDS_TC 020 ICTTA not used by Triggered Transfer to 40 External Address OCDS_TC 021 TriCore breaks on de assertion instead of 41 assertion of break bus OCDS_TC 024 Loss of Connection in DAP three pin Mode 41 OCDS_TC 025 PC corruption when entering Halt mode 42 after a MTCR to DBGSR OCDS_T
38. ith the conflicting byte store having address bits 3 0 0x1 In these very specific circumstances the conflict between the load instruction and store buffer contents is not detected and the load instruction overtakes the store returning the data value prior to the store operation Note In the current TriCore1 CPU implementation load accesses are initiated from the DEC pipeline stage whilst store accesses are initiated from the following EXE pipeline stage To avoid memory port contention problems when a load follows a store instruction the CPU contains a single store buffer In the case where a store instruction in EXE is immediately followed by a load instruction in DEC the store is directed to the CPU store buffer and the load operation overtakes the store The store is then committed to memory from the store buffer on the next store instruction or non memory access cycle The store buffer is only used for store accesses to local memories LDRAM or DCache Store instructions to bus based memories are always executed immediately in order A store buffer conflict is detected when a load instruction is encountered which targets an address for which at least part of the requested data is currently held in the CPU store buffer In this store buffer conflict scenario the load instruction is cancelled the store committed to memory from the store buffer and then the load re started In systems with an enabled MMU and where either the st
39. ll PCXI into the CSA e RET has always restored the full PCXI from the CSA e RFE has always restored the full PCXI from the CSA From the TriCore V1 3 8 architecture manuals onwards it is also made explicit that e CALL BISR and SVLCX now explicitly update the PCXI PCPN PCXI PIE PCXI UL PCXI PCXS and PCXI PCXO fields after storing the previous PCXI contents to memory e RSLCX now restores the full PCXI from the CSA However prior to the TriCore V1 3 6 architecture manual and as implemented by the TriCore1 3 core the following behaviour was present BISR and SVLCX previously only updated the PCXI UL PCXI PCXS and PCXI PCXO fields after storing the previous PCXI contents to memory PCXI PCPN and PCXI PIE were not updated e RSLCX previously restored only the PCXI UL PCXI PCXS and PCXI PCXO fields of the PCXI The main implication of this change is that the value held in the PCXI PCPN and PCXI PIE fields following a BISR SVLCX or RSLCX instruction may be different between the TriCore1 3 1 and TriCore1 3 cores If it is necessary to determine the priority number of an interrupted task after performing a BISR or SVLCX instruction and before the corresponding RSLCX instruction then either of the following access methods may be used Method 1 For applications where the time prior to execution of the BISR instruction is not critical the priority number of the interrupted task may be read from the PCXI before ex
40. ll other cases where FPU traps are enabled some other method of manipulating the PSW user status bits must be used in order to avoid extraneous CAE trap generation For instance if in Supervisor mode the PSW may be read using the MFCR instruction the high order PSW bits modified and written back using the MTCR instruction CPU _TC 115 Interrupt may be taken on exit from Halt mode with Inter rupts disabled A problem exists whereby an interrupt may be taken by the TriCore CPU upon exiting Halt mode even if interrupts are disabled at that point The problem occurs when an interrupt request is received by the TriCore CPU with the pending interrupt priority number PIPN higher than the current CPU priority number CCPN and interrupts are enabled In this case where only the CPU pipeline status is preventing the interrupt from being taken immediately the interrupt is latched and taken as soon as the pipeline can accept an interrupt This may cause unexpected behavior whilst debugging where interrupts are enabled before entry to Halt mode or where interrupts are temporarily enabled during Halt mode In this case an interrupt may be latched whilst the CPU is in Halt mode and subsequently disabling interrupts during Halt mode by setting ICR IE 0g will not prevent the interrupt from being serviced immediately upon exit from Halt mode It should be noted that no corruption of the program flow is associated with this issue and that it affe
41. mum erase time at various CPU operating frequencies can be calculated according to the following table Table 8 Relative erase time increments Frequency MHz Increment 40 5 66 1 80 0 FLASH_TC 035 Flash programing time out of specification As per specification flash programing time specified is per page 5msec Where as actual programing time measured on the device is per page 5 5msec FLASH TC 036 DFLASH Margin Control Register MARD The margin for the two banks of the Data Flash module DFLASH can only be selected for the complete DFLASH and not separately for each DFLASH bank Therefore the correct description representing the actual behavior of bit BNKSEL in register MARD is as follows TC1736 EES AA ES AA AA 36 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations BNKSEL Qp The active read margin for both DFLASH banks is determined by bit fields MARGINO and MARGIN1 BNKSEL 1g Both DFLASH banks are read with standard default margin independently of bit fields MARGINO and MARGIN1 Workaround According to the above description e inorder to allow reading from DFLASH bank 1 with high margin bit BNKSEL must be set to Op e in order to read different DFLASH banks with different read margins standard high reconfiguration of register MARD is required in between OCDS AI 001 DAP restart lost when DAPO inactive To speed up the resynchronization a
42. must be half word aligned and st a instructions must be word aligned they cannot trigger the circular buffer wrap around condition As such this case only affects the following instructions using circular addressing mode st w st d st da Example LDA a8 0xD000000E Address of un aligned load LDA al2 0xD0000820 Circular Buffer Base LDA al3 0x00180014 Circular Buffer Limit and Index ld w d6 a8 Un aligned load split 16 16 add d4 d3 d2 Optional IP instruction st d al2 al3 c dO d1l Circular Buffer wrap 32 32 In this example the word load from address OxDOOOOOOE is split into 2 half word accesses since it spans a 128 bit boundary in LDRAM The double word store encounters the circular buffer wrap condition and should be split into 2 TC1736 EES AA ES AA AA 12 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations word accesses to the top and bottom of the circular buffer However due to the bug the first access takes the transfer data size from the second part of the un aligned load and only 16 bits of data are written Note that the presence of an optional IP instruction between the load and store transactions does not prevent the problem since the load and store transactions are back to back in the LS pipeline Case 2 Case 2 is similar to case 1 and occurs where a load instruction using circular addressing mode encounters the circular buffer wrap around condition and is
43. n History List Change Summary Table 5 Application Hints Hint Short Description Cha Pa nge ge ADC_AI H002 Minimizing Power Consumption of an New 51 ADC Module CPU_TC H004 PCXI Handling Differences in 51 TriCore1 3 1 FIRM_TC H000 Reading the Flash Microcode Version New 53 HYS_TC H001 Effective Hysteresis in Application 54 Environment MSC_TC H007 Start Condition for Upstream Channel 54 MultiCAN_AI H005 TxD Pulse upon short disable request 54 MultiCAN_AI H006 Time stamp influenced by 55 resynchronization MultiCAN_TC H002 Double Synchronization of receive input 55 MultiCAN_TC H003 Message may be discarded before 55 transmission in STT mode MultiCAN_TC H004 Double remote request 56 OCDS_TC H001 IOADDR may increment after aborted 57 10_READ_BLOCK OCDS_TC H002 Setting IOSR CRSYNC during Application 57 Reset OCDS_TC H003 Application Reset during host 58 communication OCDS_TC H004 Device Identification by Application 58 Software PORTS_TC H005_ Pad Input Registers do not capture 59 Boundary Scan data when BSD mode signal is set to high PWR_TC H005 Current Peak on Vppp during Power up 59 SSC_AI H001 Transmit Buffer Update in Slave Mode 60 after Transmission TC1736 EES AA ES AA AA 7 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet History List Change Summary Table 5 Application Hints cont d Hint Short Descri
44. n go back to 1 RESET TC 001 SCU_RSTSTAT PORST not set by a combined Debug System Application Reset Causing simultaneously a System Application and Debug Reset via CBS_OSTATE RSTCLO 3 in most cases does not leave the SCU_RSTSTAT PORST bit set as specified Bit SCU_RSTSTAT PORST stays set only if reset source ESRO was configured not to generate any reset SCU_RSTCON ESRO 00 If the ESRO reset source is configured to generate a reset bit SCU_RSTSTAT PORST is cleared and bit SCU_RSTSTAT ESR0O is set instead TC1736 EES AA ES AA AA 45 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations Bits CBS _OSTATE RSTCLO 3 are either set by setting bits CBS_OCNTRL OJC4 7 or CBS_OJCONF OJC4 7 Debugging of PORST only application software under debugger control is therefore not working if the ESRO reset source generates a reset Workaround Before triggering a simultaneous System Application and Debug Reset by the OCDS system bit field SCU_RSTSTAT ESRO should be cleared In addition it should be checked that bit field SCU_RSTSTAT ESR1 is also cleared If bit field SCU_RSTSTAT ESRO needs to contain a value different from 00 instead of checking bit SCU_RSTSTAT PORST the three bits SCU_RSTSTATCBO SCU_RSTSTATCB1 and SCU_RSTSTATCB3 should be checked to be set SCU_TC 016 Reset Value of Registers ESRCFG0 1 The reset value of register SCU_ESRCFGO is 0x00000100 instead of 0x000001 10 The reset v
45. n and debug Indeed there is a possibility that the instruction TC1736 EES AA ES AA AA 43 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations immediately following the RFM be submitted to inadequate protection rules as defined by the old PSW PRS field e Problem sequence e instr monitor e instr monitor e instr monitor e RFM monitor e Instruction Uses debug monitor s PSW PRS field as opposed to newly restored one e instruction2 Workaround To fix this the user needs to do the following before exiting the monitor using RFM e gt Retrieve the old value of PSW from location DCX 4 e gt Do a MFCR and a MTCR to copy the old value of PSW PRS into PSW without changing other PSW fields gt DSYNC e gt RFM This sequence will guarantee that all instructions fetched subsequently to the RFM will be submitted to the new PSW PRS field OCDS_TC 027 BAM breakpoints with associated halt action can poten tially corrupt the PC BAM breakpoints can be programmed to trigger a halt action When such a breakpoint is taken the CPU will go into HALT mode immediately after the instruction is executed This mechanism is broken in the case of conditional jumps When a BAM breakpoint with halt action is triggered on a conditional jump the PC for the next instruction will potentially be corrupted before the CPU goes into HALT mode On exiting HALT mode the CPU will see the corrupted value of the P
46. n or power fail The following table classifies the Vpp Vppp ranges with respect to peak severity Table 9 Worst Case Power up Cross Current Vop Vopp Comment gt 0 5V don t care normal operation lt 0 5V lt 0 8V lppp lt 1 MA lt 0 5V 0 8 V lt Vbpr lt 1 0 V Ippp lt 3 MA lt 0 5V 3 6 V lppp lt 112 mA Even under worst case conditions this effect has no impact on lifetime nor reliability SSC_AI H001 Transmit Buffer Update in Slave Mode after Transmission If the Transmit Buffer register TB is written in slave mode in a time window of one SCLK cycle after the last SCLK edge i e after the last data bit of a transmission the first bit to be transmitted may not appear correctly on line MRST Note This effect only occurs if a configuration with PH 1 shift data on trailing edge is selected It is therefore recommended to update the Transmit Buffer in slave mode after the transmit interrupt TIR has been generated after first SCLK phase of first bit and before the current transmission is completed before last SCLK phase of last bit As this may be difficult to achieve in systems with high baud rates and long interrupt latencies alternatively the receive interrupt at the end of a transmission may be used A delay of 1 5 SCLK cycles bit times after the receive interrupt last SCLK edge of transmission should be provided before updating the Transmit Buffer of the slave The master must pr
47. nd the trap handler then continues as normal The main issue associated with this problem is that the handling of the interrupt will delay the start of the trap handler For the majority of trap types associated with the program flow this is not a problem However where the interrupted trap type denotes a serious system problem such as an NMI trap the delay in servicing the trap may be of concern In addition if interrupts are re enabled within the interrupt handler then the delay in returning to the trap handler will be further extended by the handling of any additional higher priority interrupt requests which may occur However once processing of the initial interrupt handler is complete and the RFE instruction executed to return to the trap handler interrupts are correctly disabled immediately and the trap handler will continue even if further interrupts are pending when the RFE instruction is executed Another point to note is that this issue can cause some assumptions made in system software to be invalid For example ifa system does not allow interrupts or traps to re enable interrupts then it would have been safe to assume that whenever a trap or interrupt is entered that the code that has been suspended and hence the state information saved in the CSA is for a user task and typically non privileged Unfortunately with this issue that premise no longer holds the code interrupted and state saved in a CSA can be that of a privilege
48. neering samples which may not be completely tested in all functional and electrical characteristics therefore they should be used for evaluation only Note This device is equipped with a TriCore TC 1 3 1 Core Some of the errata have workarounds which are possibly supported by the tool vendors Some corresponding compiler switches need possibly to be set Please see the respective documentation of your compiler For effects of issues related to the on chip debug system see also the documentation of the debug tool vendor The specific test conditions for EES and ES are documented in a separate Status Sheet TC1736 EES AA ES AA AA 2 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet History List Change Summary 1 History List Change Summary Table 2 History List Version Date Remark 1 0 28 11 2008 1 1 28 08 2009 Updated Documentation Reference TC1736 User s Manual V1 0 2008 11 TC1736 Data Sheet V1 1 2009 08 Removed BROM_TC H001 Frequency Ratio fSYS fOSC 2 for Bootstrap Loaders see p 7 3 in TC1736 User s Manual V1 0 Removed DMI_TC 015 LDRAM Access Limitations for 2KByte Data Cache Configurations no data cache in TC1736 1 2 26 02 2010 Updated Documentation Reference TC1736 User s Manual V1 1 2009 10 Removed MSC_TC H008 The LVDS pads require a settling time when coming up from pad power down state TC 1736 has no LVDS functionality Removed PORTS_TC H004 Using LVDS Por
49. nstruc tions with wrap around In certain situations where a Load or Store instruction using circular addressing mode encounters the circular buffer wrap around condition the first access to the circular buffer may be performed using an incorrect data size causing too many or too few data bytes to be transferred The circular buffer wrap around TC1736 EES AA ES AA AA 11 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations condition occurs when a load or store instruction using circular addressing mode addresses a data item which spans the boundary of a circular buffer such that part of the data item is located at the top of the buffer with the remainder at the base The problem may occur in one of two cases Case 1 Where a store instruction using circular addressing mode encounters the circular buffer wrap around condition and is preceded in the LS pipeline by a multi access load instruction the first access of the store instruction using circular addressing mode may incorrectly use the transfer data size from the second part of the multi access load instruction A multi access load instruction occurs in one of the following circumstances e Unaligned access to LDRAM or cacheable address which spans a 128 bit boundary e Unaligned access to a non cacheable non LDRAM address e Circular addressing mode access which encounters the circular buffer wrap around condition Since half word store instructions
50. on with an operand register containing a random non protected cacheable address The DMI line buffer will respond to cachei wi instructions regardless of the content of its operand provided that the operand contains a cacheable address which is not protected On execution of cachei wi the DMI line buffer will flush and invalidate itself For example executing the following two instructions should flush and invalidate the DMI line buffer in any circumstance Note that the current workaround always invalidates the entry regardless of whether it was dirty or not movh a a0 0x8000 Cachei operand is random non protected cacheable address cachei wi a0 The DLB gets invalidated regardless of the value in a0 If the user is not concerned in invalidating the DMI line buffer but simply guaranteeing its coherency with external memory then there is another simple workaround This consists in issueing a read to a dummy cacheable address pointing outside the 16 byte block containing the next required data Access to the next required data will then necessarily result in a refill and the resulting data will be coherent This is what the following code does a0 contains a dummy address and a1 contains the address for the user s required data movh a a0 0x8000 Dummy address is 0x80000000 ld w d0 a0 7 a0 has to point to different 16 byte block than al TC1736 EES AA ES AA AA 31 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Func
51. ontext registers are unknown it is necessary to check one of the upper context registers twice with different values in case the initial contents match the first value to be checked Note The NOP instructions in the above code are mandatory to ensure that reads from the GPRs target the register file directly rather than the forwarding paths which always function correctly Secondly within the FCU trap handler itself only the global and lower context registers may be used D0 D7 and A0 4A9 Since the upper context information TC1736 EES AA ES AA AA 19 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations is already lost in an FCU trap condition usage of the global and lower context registers without previously saving this information is acceptable CPU _TC 111 Imprecise Return Address for FCU Trap The FCU trap is taken when a context save operation is attempted but the free context list is found to be empty or when an error is encountered during a context save or restore operation In failing to complete the context operation architectural state is lost so the occurrence of an FCU trap is a non recoverable system error Since FCU traps are non recoverable system errors having a precise return address is not important but can be useful in establishing the cause of the FCU trap The TriCore1 CPU does not generate a precise return address for an FCU trap if the cause of the FCU trap was one of the following
52. ore buffer or load instruction targets an address undergoing PTE based translation the conflict detection is just performed on address bits 9 0 since higher order bits may be modified by translation and a conflict cannot be ruled out In other systems no MMU MMU disabled conflict detection is performed on the complete address Example Case 1 LDA al2 0xD0001008 Circular Buffer Base LDA al3 0x00180016 Circular Buffer Limit and Index st b a12 0x1 d2 Store to byte offset 0x9 ld w d6 al2 al3 c Circular Buffer wrap 16 16 TC1736 EES AA ES AA AA 16 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations In this example the circular buffer base address is double word but not quad word aligned The byte store to address 0xD0001009 is immediately followed by a load operation and is placed in the CPU store buffer The word load instruction encounters the circular buffer wrap condition and is split into 2 half word accesses to the top 0xD0001016 and bottom 0xD0001008 of the circular buffer The first load access completes correctly but due to the bug the second access overtakes the store operation and returns the previous half word from 0xD0001008 Example Case 2 LDA al2 OxDO001000 Circular Buffer Base LDA al3 0x00140012 Circular Buffer Limit and Index st b a12 0x1 d2 Store to byte offset 0x1 ld w d6 al2 al3 c Circular Buffer wrap 16 16 In this example the circul
53. ost posts an instruction with the O_WRITE_WORD instruction after detecting the reset Workaround Two correlated activities should be incorporated in the tool software After each reset the host should explicitly use CBS_IOCONF COM_RST to reset any erroneously pending requests The higher level protocol should require a specific answer to the very first command sent from the host to the device Erroneous read requests then can be detected and skipped TC1736 EES AA ES AA AA 57 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Application Hints OCDS TC H003 Application Reset during host communication Not only the host is able to cause resets of the device External pins driven by the application the internal watchdog and even the application program itself can trigger the reset generation process The only way to communicate reset events to the host is for Cerberus to reject the next instruction with never ending busy which should lead to communication time out on the host side The decision to accept or reject an instruction is done very early in the bit stream of the instruction If an Application Reset happens after this point of time the instruction will complete in most cases and only the next one will be rejected As the temporal distance from reset event and instruction rejection is not fixed apart from being sequential it is highly recommended to check the IOINFO register using the O_SUPERVISOR inst
54. ovide a pause that is sufficient to allow updating of the slave Transmit Buffer before starting the next transmission TC1736 EES AA ES AA AA 60 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Application Hints SSC _AI H002 Transmit Buffer Update in Master Mode during Trailing or Inactive Delay Phase When the Transmit Buffer register TB is written in master mode after a previous transmission has been completed the start of the next transmission generation of SCLK pulses may be delayed in the worst case by up to 6 SCLK cycles bit times under the following conditions e atrailing delay SSOTC TRAIL gt 0 and or an inactive delay SSOTC INACT gt 0 is configured e the Transmit Buffer is written in the last module clock cycle fssc or foc of the inactive delay phase if INACT gt 0 or of the trailing delay phase if INACT 0 No extended leading delay will occur when both TRAIL 0 and INACT 0 This behaviour has no functional impact on data transmission neither on master nor slave side only the data throughput determined by the master may be slightly reduced To avoid the extended leading delay it is recommended to update the Transmit Buffer after the transmit interrupt has been generated i e after the first SCLK phase and before the end of the trailing or inactive delay respectively Alternatively bit BSY may be polled and the Transmit Buffer may be written after a waiting time corresponding to 1 SCLK
55. preceded in the LS pipeline by a multi access load instruction However for case 2 to be a problem it is necessary that the first access of the load instruction encountering the circular buffer wrap around condition the access to the top of the circular buffer also encounters a conflict condition with the contents of the CPU store buffer Again in this case the first access of the load instruction using circular addressing mode may incorrectly use the transfer data size from the second part of the multi access load instruction Since half word load instructions must be half word aligned and lId a instructions must be word aligned they cannot trigger the circular buffer wrap around condition As such this case only affects the following instructions using circular addressing mode Id w Id d Id da Note In the current TriCore1 CPU implementation load accesses are initiated from the DEC pipeline stage whilst store accesses are initiated from the following EXE pipeline stage To avoid memory port contention problems when a load follows a store instruction the CPU contains a single store buffer In the case where a store instruction in EXE is immediately followed by a load instruction in DEC the store is directed to the CPU store buffer and the load operation overtakes the store The store is then committed to memory from the store buffer on the next store instruction or non memory access cycle The store buffer is only used for store accesse
56. ption Cha Pa nge ge SSC_AI H002 Transmit Buffer Update in Master Mode 61 during Trailing or Inactive Delay Phase SSC_AI H003 Transmit Buffer Update in Slave Mode 61 during Transmission SSC_TC H003 Handling of Flag STAT BSY in Master 62 Mode TC1736 EES AA ES AA AA 8 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations 2 Functional Deviations BCU _TC 006 Polarity of Bit SvM in Register ECON The polarity of bit svm State of FPI Bus Supervisor Mode Signal in the SBCU Error Control Capture register SBCU ECON is inverted compared to its description in the User s Manual Actually it is implemented as follows e SVM Qx Transfer was initiated in user modes e SVM 1 Transfer was initiated in supervisor mode CPU _TC 105 User Supervisor mode not staged correctly for Store In structions Bus transactions initiated by TriCore load or store instructions have a number of associated attributes such as address data size etc derived from the load or store instruction itself In addition bus transactions also have an IO privilege level status flag User Supervisor mode derived from the PSW 1IO bit field Unlike attributes derived from the instruction the User Supervisor mode status of TriCore initiated bus transactions is not staged correctly in the TriCore pipeline and is derived directly from the PSW IO bit field This issue can only cause a problem in certain circumstances specifically wh
57. ration on sector DFx is in progress during a certain critical time window a programming command on sector DFy is issued i e the erase operation on sector DFx is suspended In other words potentially critical sequences are e Erase PFLASH gt erase DFx gt program DFy suspend erase DFx or e Erase DFy gt erase DFx gt program DFy suspend erase DFx or e Erase DFx gt erase DFx gt program DFy suspend erase DF x As a consequence sector DFx may not be correctly erased after the suspended erase has been completed i e DFx may be weakly programmed The effect is non permanent i e erasing DFx again will solve the issue Note Sector DFy is always correctly programmed Therefore both Data Flash sectors or a Program and a Data Flash sector must not be erased one after the other if the second erase operation might be suspended Workaround 1 Additionally program a page of Data Flash sector DFx or DFy before starting the erase of DFx e g 1 Erase PFLASH or DFx or DFy 2 Additional step Program DFx or DFy specified rules for Data Flash page programming must remain valid check for completion of programming busy 3 any operation except erase of DFx DFy or PFLASH Erase DFx 5 Concurrent programming of DFy may be triggered gt A Workaround 2 After starting the erase of Data Flash sector DFx delay the start of the programing of sector DFy by at least 250 ms e g TC1736 EES A
58. ree pin DAP mode CBS_OSTATE DJMODE 11 Note Two pin DAP mode is not affected Workaround None for three pin DAP mode It is recommended to select the protected two pin DAP mode CBS_OSTATE DJMODE 01 instead if unintentional and non recoverable loss of the tool connection e g due to EMC shall be prevented safely OCDS _TC 025 PC corruption when entering Halt mode after a MTCR to DBGSR In cases where the CPU is forced into HALT mode by a MTCR instruction to the DBGSR register there is a possibility of PC corruption just before HALT mode is entered This can happen for MTCR instructions injected via the CPS as well as for user program MTCR instructions being fetched by the CPU In both cases the PC is potentially corrupted before entering HALT mode Any subsequent read of the PC during HALT will yield an erroneous value Moreover on exiting HALT mode the CPU will resume execution from an erroneous location TC1736 EES AA ES AA AA 42 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations The corruption occurs when the MTCR instruction is immediately followed by a mis predicted LS branch or loop instruction The forcing of the CPU into HALT takes priority over the branch resolution and the PC will erroneously be assigned the mispredicted target address before going into HALT e Problem sequence 1 e 1 CPS injected MTCR instruction to DBGSR sets HALT Mode e 2 LS based branch loop instruction e 3
59. rently TC1736 EES AA ES AA AA 40 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations OCDS TC 021 TriCore breaks on de assertion instead of assertion of break bus The central OCDS building block Cerberus provides two Break Buses All break sources can be individually enabled to assert one of these buses while all break targets can be programmed to react on the assertion of one of the break buses The break target TriCore however does not react on the assertion transition 0 to 1 of the break bus as seen in the associated status bit MCDBBSS BBSx like all the other break targets but on the deassertion transition 1 to 0 of the status bit It is therefore not possible to Stop the TriCore together with another core e g PCP at the same instant e Use a single transition of an external signal connected to any BRKIN pin to cleanly break the whole SoC Workaround e All internal break sources can be programmed in a manner so that the break event is encoded as a pulse For simple sources e g SBCU this is trivial for complex sources e g MCDS a different trigger logic may be required The temporal distance of the break requests to different targets can thus be kept low relative to the intrinsic core specific delays e g caused by pipeline flushing e External break sources may be redesigned to deliver an active low pulse also OCDS TC 024 Loss of Connection in DAP three pin Mode
60. revisions of the TriCore1 3 1 architecture manual and in contrast to most other FPU instructions the UPDFL instruction should not generate Co Processor Asynchronous Error CAE traps However in certain circumstances the TriCore1 3 1 FPU will generate CAE traps for UPDFL instructions The TriCore1 3 1 FPU will generate a CAE trap upon execution of the UPDFL instruction in the following situation e After execution of the UPDFL instruction one or more of the PSW 31 26 bits are set either the PSW bit s are set by UPDFL or were set prior to execution and not cleared by the UPDFL instruction e FPU traps are enabled for one of the asserted PSW 31 26 bits via the corresponding FPU_TRAP_CON FxE bit being set e The FPU_TRAP_CON TST CSFR bit is clear no previous FPU trap has been generated without the subsequent clearing of FPU_TRAP_CON TST Workaround The UPDFL instruction is normally used in one of two situations e Clearing the FPU sticky flags held in PSW 30 26 Setting the FPU rounding mode bits in PSW 25 24 TC1736 EES AA ES AA AA 24 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations In the first case if all the PSW 31 26 bits are cleared by UPDFL no CAE trap will be generated In the second case UPDFL may still be used to set the FPU rounding mode but in this case the remaining PSW bits 81 26 must be cleared by UPDFL in order to avoid generation of an unexpected CAE trap In a
61. ruction each time an abnormally long busy period is experienced by the host Especially a repetition of the rejected instruction should only be attempted if the possibility of Cerberus being in Error State has been excluded Workaround Use l O_SUPERVISOR whenever a too long busy bit is observed OCDS_TC H004 Device Identification by Application Software While each device type can easily be recognized by test equipment using the JTAG ID over the years each device family has had a proprietary way to provide the same information to application software running on the device When reusing software for another device family the algorithm had to be adapted To worsen things using the wrong algorithm may cause fatal errors e g traps when accessing illegal addresses Starting with the Audo Future family the JTAG ID as available as a standard SFR CBS_JTAGID at a fixed address namely in the address space of the main Cerberus The value found in this register unambiguously defines where additional information e g CHIPID can be found in the device on hand TC1736 EES AA ES AA AA 58 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Application Hints Older devices obviously do not have the CBS _JTAGID so accessing its address may cause problems Workaround Each Cerberus module ever implemented has a version number mapped into a register CBS_JDPID at a fixed address OxF0000408 Note This register is not published in
62. rupt enable status from ICR IE Interrupts should then be disabled by setting ICR IE 0p If the next debugger action is to single step a BAM breakpoint should be placed on the next instruction to be executed and the CPU re started In this case a previously latched interrupt may be serviced but will not result in a further breakpoint being flagged until the interrupt handler returns and the next instruction intended to be single stepped is executed Subsequent single step operations may be implemented using any appropriate method since interrupts will be disabled before Halt mode is entered If the debugger action is to re start normal execution the interrupt enable status should be restored from the value read upon hitting the initial breakpoint and the CPU re started DMA_TC 013 DMA LMB Master Access to Reserved Address Location DMA LMB Master goes into an unintentional lock up state when a Read or Write access is made to a reserved memory location with an unrecognised slave Subsequent Read Write accesses from a DMA Channel MLI Cerberus or the DMA FPI Slave to all memory locations mapped to the DMA LMB Master TC1736 EES AA ES AA AA 26 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations 80000000 to DFFFFFFF will be halted until control of the DMA LMB Master is regained In the case of a lock up DMA LMB Master Read access the next LMB access and associated response will have the following
63. s to local memories LDRAM or DCache Store instructions to bus based memories are always executed immediately in order A store buffer conflict is detected when a load instruction is encountered which targets an address for which at least part of the requested data is currently held in the CPU store buffer In this store buffer conflict scenario the load instruction is cancelled the store committed to memory from the store TC1736 EES AA ES AA AA 13 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations buffer and then the load re started In systems with an enabled MMU and where either the store buffer or load instruction targets an address undergoing PTE based translation the conflict detection is just performed on address bits 9 0 since higher order bits may be modified by translation and a conflict cannot be ruled out In other systems no MMU MMU disabled conflict detection is performed on the complete address Example LDA a8 0xD000000E Address of un aligned load LDA al2 0xD0000820 Circular Buffer Base LDA al3 0x00180014 Circular Buffer Limit and Index st h al2 0x14 d7 Store causing conflict ld w d6 a8 Un aligned load split 16 16 add d4 d3 d2 Optional IP instruction ld d al2 al3 c d0 d1 Circular Buffer wrap 32 32 conflict with st h In this example the half word store is to address 0xD0000834 and is immediately followed by a load instruction so is direc
64. ted that this problem is not encountered when the D cache is turned on When the D cache is turned on writing a one to OVC_OCON DCINVAL will correctly invalidate all clean cache entries and invalidate the DMI line buffer The problem only concerns systems with no cache or systems where the cache is turned off Detailed description D Cache turned on When D cache is turned on the DMI line buffer is only used as a performance enhancement mechanism with no logical existence to the user It is therefore not operating as a micro cache and the current issue does not apply When the TC1736 EES AA ES AA AA 30 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations dcache is turned on writing to OVC_OCON DCINVAL will always invalidate all clean lines in the dcache No stale data will subsist in the DMI line buffer D Cache turned off The problem occurs when the dcache is turned off When the dcache is turned off or non existent the DMI line buffer operates as a 16 byte cache Writing a one to the OVC_OCON DCINVAL register should invalidate the data inside the DMI line buffer as long as the data is not dirty This invalidation mechanism does not work on AUDO Future devices Writing to OVC_OCON DCINVAL will have no effect at all Any cache line which was previously loaded into the DMI line buffer will not be invalidated whether it was dirty or not Workaround The workaround consists in executing a cachei wi instructi
65. ted to the store buffer The word load from address OxDOOOOOOE is split into 2 half word accesses since it spans a 128 bit boundary in LDRAM The double word load encounters the circular buffer wrap condition and should be split into 2 word accesses to the top and bottom of the circular buffer In addition the first circular buffer access conflicts with the store to address 0xD0000834 Due to the bug after the store buffer is flushed the first access takes the transfer data size from the second part of the un aligned load and only 16 bits of data are read Note that the presence of an optional IP instruction between the two load transactions does not prevent the problem since the load transactions are back to back in the LS pipeline Workaround Where it cannot be guaranteed that a word or double word load or store instruction using circular addressing mode will not encounter one of the corner TC1736 EES AA ES AA AA 14 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations cases detailed above which may lead to incorrect behaviour one NOP instruction should be inserted prior to the load or store instruction using circular addressing mode LDA a8 0xD000000E Address of un aligned load LDA al2 0xD0000820 Circular Buffer Base LDA al3 0x00180014 Circular Buffer Limit and Index ld w d6 a8 Un aligned load split 16 16 add d4 d3 d2 Optional IP instruction nop Bug workaround st d al2 al3
66. test it is verified by design characterization The corresponding note will be added in the next revisions of the Data Sheet FADC TC P003 Incorrect test condition specified in datasheet for FADC parameter Input leakage current at Veagnp In datasheet the test condition for FADC parameter Input leakage current at Veacnp iS specified as OV lt Vin lt Vopwe The actual test condition is Vin OV It is not allowed to raise Veagnp above 1 5V when the FADC is in power down mode in order not to damage the device PLL_TC P005 PLL Parameters for fyco gt 780 MHz When the PLL is configured for VCO frequencies fyco gt 780 MHz the specified PLL parameters may be exceeded Workaround Select the values for the P N and K2 dividers such that the desired target frequency fp is achieved with fyco lt 780 MHz TC1736 EES AA ES AA AA 50 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Application Hints 4 Application Hints ADC _AI H002 Minimizing Power Consumption of an ADC Module For a given number of A D conversions during a defined period of time the total energy power over time required by the ADC analog part during these conversions via supply Vppy is approximately proportional to the converter active time Recommendation for Minimum Power Consumption In order to minimize the contribution of A D conversions to the total power consumption it is recommended 1 to select the internal operating
67. that under normal operation LMB block transfers will not result in a bus error condition being flagged on the second beat of a block transfer However such a condition may be encountered when accessing the on chip Flash if the second double word of data accessed from the Flash for the second half of the cache line contains an uncorrectable double bit error When this condition is triggered the first part of the requested data is obtained from the valid first beat of the BTR2 transfer and the second part is required from the errored second beat In this case no error is flagged to the TriCore CPU and the transaction is incorrectly re started on the LMB In the case of a Flash double bit error this transaction will be re tried continuously on the LMB by the DMI LMB master and the CPU become deadlocked This situation would then only be recoverable by a Watchdog reset The problem exists within the DMI DLB which is used as a single cache line when no data cache is configured and as a streaming buffer when data cache is present As such the problem affects all load accesses to cacheable locations whether data cache is configured or not since the DLB is used in both cases Note This problem affects load accesses to the on chip Flash only Instruction fetches which encounter a similar condition bus error on later beat of block transfer behave as expected and will return a PSE trap upon any attempt to execute an instruction from a Flash loca
68. tion containing a double bit error TC1736 EES AA ES AA AA 29 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations Workaround As described previously this problem should not be encountered during normal operation and will only be triggered in the case of a double bit error being detected in an access to the on chip Flash However in order to remove the possibility of encountering this issue all load accesses to cacheable addresses within the on chip Flash should be made using natural alignment word transfers should be word aligned double word transfers double word aligned It is also possible to check for the occurrence of this problem by having some other master such as the PCP periodically poll the LBCU LEATT register to check for the occurrence of LMB error conditions specifically if one is detected during a BTR2 read transfer from the DMI as reported by LEATT OPC and LEATT TAG DMI TC 017 DMI line buffer is not invalidated by a write to OVC_OCON DCINVAL if cache off A problem exists whereby the DMI line buffer is not invalidated by a write to OVC_OCON DCINVAL when operating with the D cache turned off This means that the user cannot rely on a write to OVC_OCON DCINVAL to make sure that any stale data in the DMI line buffer is invalidated This can be a problem for users who want to use the OVC_OCON DCINVAL bit to ensure coherency between the DMI and background memory It should be no
69. tional Deviations ld w d0 al This load will b xecuted fresh from memory with a refill 7 Read data will be coherent with rest of memory FADC _TC 005 Equidistant multiple channel timers The description is an example for timer_1 and timer_2 but can also affect all other combinations of timers Timer_1 and Timer_2 are running with different reload values Both timers should start conversions with the requirement of equidistant timing Problem description Timer_1 becomes zero and starts a conversion Timer_2 becomes zero during this conversion is running and sets the conversion request bit of channel_2 At the end of the conversion for channel_1 this request initiates a start for channel_2 But the Timer_2 is reloaded only when setting the request bit for channel_2 and is decremented during the conversion of channel_1 The correct behavior would be a reload when the requested conversion of channel_2 is started Therefore the start of conversion for channel_2 is delayed by maximum one conversion time After this delay it will be continued with equidistant conversion starts Please refer to the following figure TC1736 EES AA ES AA AA 32 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations R Timer loaded with Reload value 0 Timer becomes zero Timer_1 DECR OR DECR Start_chan1 Busy1 conversion time 1 In hardware implemented feature 1 i
70. ts in CMOS Mode TC1736 has no LVDS functionality Removed FPI_TC H001 FPI bus may be monopolized despite starvation protection TC1736 has no PCP Note Changes to the previous errata sheet version are particularly marked in column Change in the following tables TC1736 EES AA ES AA AA 3 62 Rel 1 2 26 02 2010 Errata Sheet Cinfineon History List Change Summary Table 3 Functional Deviations Functional Short Description Cha Pa Deviation nge jge BCU_TC 006 Polarity of Bit SVM in Register ECON New 9 CPU_TC 105 User Supervisor mode not staged 9 correctly for Store Instructions CPU_TC 106 Incorrect PSW update for certain IP 10 instructions dual issued with MTCR PSW CPU_TC 107 SYSCON FCDSF may not be set after FCD 11 Trap CPU_TC 108 Incorrect Data Size for Circular 11 Addressing mode instructions with wrap around CPU_TC 109 Circular Addressing Load can overtake 15 conflicting Store in Store Buffer CPU_TC 110 Register Banks may be out of sync after 18 FCU Trap CPU_TC 111 Imprecise Return Address for FCU Trap 20 CPU_TC 113 Interrupt may be taken during Trap entry 20 sequence CPU_TC 114 CAE Trap may be generated by UPDFL 24 instruction CPU_TC 115 Interrupt may be taken on exit from Halt 25 mode with Interrupts disabled DMA_TC 013 DMA LMB Master Access to Reserved 26 Address Location DMI_TC 014 Problems with Parity Handling in TriCore 28 Data Memor
71. ue from the IP instruction rather than the later MTCR instruction This situation only occurs in 2 cases e MUL MADD MSUB instruction followed by MTCR Psw e RSTV instruction followed by MTCR Psw Example rstv mtcr PSW dY Modify PSW TC1736 EES AA ES AA AA 10 62 Rel 1 2 26 02 2010 Cinfineon Errata Sheet Functional Deviations Workaround Insert one NOP instruction between the MUL MADD MSUB RSTV instruction and the MTCR instruction updating the PSW rstv nop mtcr PSW dY Modify PSW CPU_TC 107 SYSCON FCDSF may not be set after FCD Trap Under certain conditions the SYSCON FCDSF flag may not be set after an FCD trap is entered This situation may occur when the CSA Context Save Area list is located in cacheable memory or dependent upon the state of the upper context shadow registers when the CSA list is located in LDRAM The SYSCON FCDSF flag may be used by other trap handlers typically those for asynchronous traps to determine if an FCD trap handler was in progress when the another trap was taken Workaround In the case where the CSA list is statically located in memory asynchronous trap handlers may detect that an FCD trap was in progress by comparing the current values of FCX and LCX thus achieving similar functionality to the SYSCON FCDSF flag In the case where the CSA list is dynamically managed no reliable workaround is possible CPU _TC 108 Incorrect Data Size for Circular Addressing mode i
72. verse the CSA list to check the required PCXI PIE value from the appropriate saved context If it is necessary within a system to check for the occurrence of this issue just for specific timing critical trap classes then this may be performed by examination of the return address held in the A11 register within the interrupt handler and comparing this return address against the trap vector address es For example if only the NMI trap is a system issue requiring immediate action the following code may be added to the interrupt handler to determine if the interrupt was taken at the start of the NMI handler lt Timing critical section of Interrupt Handler gt movh a al2 his NMITrapAddress BTV OR OxEO lea al2 al2 los NMITrapAddress BTV OR OxEO eq a di3 al2 all Compare with All result in d13 lt Call Branch to NMI handler based on d13 result gt Note that this code segment assumes that the BTV CSFR is static during runtime If this is not the case then it would be necessary to determine the trap offset address during runtime by reading the BTV CSFR and ORing with the TCN offset of the trap of interest If more than one trap class is considered timing critical within a system it is possible to adapt the previous code to check the return address of the interrupt handler against a number or range of trap class entry addresses If the interrupted traps are considered recoverable and are not time

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