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Operation - Astronics Test Systems

1. J200 68 GND 34 GND 67 100 33 GND 66 1D1 32 GND 65 1D2 31 GND 64 1D3 30 GND 63 1D4 29 GND 62 105 28 GND 61 1D6 27 GND 60 1D7 26 GND 59 2DO 25 GND 58 2D1 24 GND 57 2D2 23 GND 56 2D3 22 GND 55 204 21 GND 54 2D5 20 GND 53 2D6 19 GND 52 2D7 18 GND 51 3DO 17 GND 50 3D1 16 GND 49 302 15 GND 48 303 14 GND 47 304 13 GND 46 3D5 12 GND 45 3D6 11 GND 44 3D7 10 GND 43 4DO 9 GND 42 4D1 8 GND 41 4D2 7 GND 40 4D3 6 GND 39 404 5 GND 38 4D5 4 GND 37 4D6 3 GND 36 4D7 2 GND 35 GND 1 GND Astronics Test Systems Publication 980900 Rev 3352 User Manual J201 1 GND 35 GND 2 GND 36 500 3 GND 37 5D1 4 GND 38 5D2 5 GND 39 5D3 6 GND 40 504 7 GND 41 5D5 8 GND 42 5D6 9 GND 43 5D7 10 GND 44 600 11 GND 45 6D1 12 GND 46 602 13 GND 47 603 14 GND 48 6D4 15 GND 49 605 16 GND 50 606 17 GND 51 6D7 18 GND 52 7DO 19 GND 53 7D1 20 GND 54 7D2 21 GND 55 703 22 GND 56 704 23 GND 57 7D5 24 GND 58 7D6 25 GND 59 7D7 26 GND 60 800 27 GND 61 8D1 28 GND 62 8D2 29 GND 63 8D3 30 GND 64 804 31 GND 65 8D5 32 GND 66 8D6 33 GND 67 8D7 34 GND 68 GND Astronics Test Systems M1721 7 7 3352 User Manual M1721 7 8 Publication No 980900 Rev B
2. 4 14 Rubidium Oscillator Commthi altior 4 14 4 14 Run Mode Data Format Customer 4 14 P WANT CNN c HH 4 18 X12 PPS Operation dos oet e Eee a DER 4 19 Changing the Coefficients 4 19 The y Coefficients Factory Default 4 20 deserere RE TM 4 20 4 21 I 4 21 Floating Point Number Representation 4 22 Interr piS 4 25 4 25 TSE o NEC 5 1 0 5 1 General d er otis sd a 5 1 Interfacing to the M1708 5 2 Accessing the Module eoe 5 2 EEPROM ld ntificatiorn e Cr 5 3 Address Decoding mcd a alec es Salo 5 4 GIONS TP Ps 5 4 Specifications ete EET ERR 5 4 Electrical Specifications 5 5 Environmen
3. 3 8 Figure 3 5 ID PROM ACCESS FOULING ERAS ed pr 3 11 Figure 4 1 M MODULE Installation iir ttt bee eere 4 6 Figure 4 2 M212 Functional Block 4 7 Figure 4 3 M212 Physical ayoul ues tus 4 8 Figure 4 4 Interface Connector Configuration seen 4 9 Figure 4 5 M212 Front Panel coe hoe epe e tede 4 10 Figure 4 6 M212 as iu enar etti ere ORBE etae tx e 4 12 Figure 4 7 ID PROM Access Routine 4 26 Figure 5 1 M1708 Front panel et epit daa ma Eid 5 1 Figure 5 2 M1708 PWA COMpPONGNL 5106 Hori 5 2 Figure 6 1 Functional Block Diagram 6 5 Figure 6 2 M210 Hardware Configuration 6 7 Figure 6 3 M210 Front 6 10 Figure 6 4 M210 RSOISIGIS co er e or ek en 6 12 Figure 6 5 Potentiometer Serial 6 15 Figure 6 6 ID PROM Access Routine 6 17 Astronics Test Systems Publication 980900 Rev 3352 User Manual Figure 7 1 M1714 Block Diagram 7 4 Figure 7 2 M1714 Front Panel Conmectors ti
4. 1 2 3 4 5 6 7 8 Publication No 980900 Rev Care should be taken to ensure that none of the modules have the same logical address as another module in the system Position 1 on the switch is the most significant bit and has a weighted value of 128 when the switch is in the OPEN position Position 5 on the switch is the least significant bit and has a weighted value of 8 when the switch is in the OPEN position It is important to note that if the modulo select switch is set to 8 the DOWN position only logical address switch settings of 64 128 192 are valid The sum of the weighted values of all the switches in the OPEN position along with the values in the table below give the M MAs logical address Example of Modulo 8 addressing STARTING LOGICAL ADDRESS NOT USED 128 64 32 16 8 OPEN 123 4 5 6 7 8 MODULO SELECT DOWN 8 With the above switch settings the starting logical address is 64 16 80 and the logical addresses would be assigned as follows With the above switch settings the starting logical address is 64 and the logical addresses would be assigned as follows Assigned M MA Location Logical Location Enabled Address A Yes 80 B Yes 81 C Yes 82 D No unassigned E No unassigned F Yes 85 VX405 2 18 Astronics Test
5. File Directory Description ri3352 32 dll VXIpnpWinNT bin 32 bit Windows DLL ri3352 lib VXIpnp WinNT VibW oc Borland compatible C library ri3352 lib VXlpnp WinNT lib msc Microsoft compatible C library ri3352 h VXlpnp WinNT include ANSI C header file 13352 VXIpnp WinNT i3352 Soft front panel Executable ri3352 c VXIpnp WinNT ri3352 Driver source code ri3352sfp c VXIpnp WinNT ri3352 Soft front panel source code ri3352 fp VXIpnp WinNT ri3352 LabWindows CVI interactive function panels ri3352 doc VXIpnp WinNT ri3352 Driver documentation ri3352 hlp VXIpnp WinNT ri3352 Driver help file ri3352sfp help hlp VXlpnp WinNT i3352 Soft front panel help file ri3352uir uir VXIpnp WinNT ri3352 Soft front panel user interface file for LabWindows CVI ri3352uir h VXIpnp WinNT ri3352 Header file for the soft front panel user interface Astronics Test Systems Introduction 1 3 3352 User Manual Publication No 980900 Rev B For details on the specific driver functions or on operating the soft front panel application refer to the installed help files If low level i e register level programming details are needed for any of the modules that make up the 3352 M212 M213 M1708 M210 M1714 M1721 refer to documentation for the specific module which is contained in separate chapters of this manual The 3352 requests four VXI logical addresses from the resource manager Each logical address refers to one of the fo
6. 1 1 e 1 1 tou Mt tti 1 1 1 1 nuo Muti E 1 2 1 2 Chapter A 2 1 Pci pc 2 1 General Description e 2 1 Egulpimigribs oe ee uen pete a eese ieget ni dno 2 1 Po IN 2 1 Key Feat reS 2 1 lee tM 2 2 t 2 2 2 2 Bus Gomplia C E 2 3 Applicable 2 3 a AAE 2 3 Unpacking and ISIS CHO seca em oe 2 3 Handling adap a m 2 4 Installation of Modules ree eet reete 2 4 Installation of VX405C Carrier 3352 2 5 Functional cr
7. CLOUT pesi DUAL ECL ECLOUTIG DRIVER ECLOUT1 TTL OUT A CONFIG SW M MODULE mm gt INTERFACE NE DRIVER B ME ECLOUT2 kx of ECLOUT2G ECLOUT2 TTL OUT B CONFIG SW mW TTLOUTS5 TTL TTLOUT6 DRIVERS TTLOUT7 NB gt TRGOUT1 Notes TRGIN P 1 PRG Software Pro grammable Level PAN 2 Threshold levels are switch selectable to 5 TRGOUT2 factory default levels no programming required 50 5V Figure 6 1 Functional Block Diagram Astronics Test Systems M210 6 5 3352 User Manual M Module Interface Input Comparators TTL Drivers ECL Drivers M210 6 6 Publication No 980900 Rev B The M Module Interface allows communication between the M210 and the carrier module The interface is an asynchronous 16 bit data bus The interface adheres to the ANSI VITA 12 1996 Standard for The Mezzanine Concept M Module Specification for MA modules The interface also permits the mapping of M module triggers as sources for the two standard inputs or as a destination for the TRGIN input signal Input comparators provide high speed analog to digital conversion with programmable high and low levels The comparators are confi
8. cet cased M 6 8 TR 6 8 INA LEVEL 6 8 ss aded 6 8 TROGJEEVEL S WICIT 6 8 ECLI SWIIED db 6 8 ECZ SWO M 6 8 OUT CFO 6 8 INPUT OUTPUT Signals near eoe Fari 6 9 ECbODUTI d and 8 OUT coded er aided ane aet 6 9 EGLOUT2 and 2 6 9 ECLOUT1G and CLOWN fidet ttl etia 6 9 ptm 6 9 llc 6 10 6 10 EN NS 6 10 TRODUTT and 2 EP Peto nig acide 6 10 Identification and Configuration 6 11 6 11 Module Idenuli dil qe ae 6 13 Operation NT NM ERR 6 15 Programming Threshold L8vels pear tnnt e 6 15 ID PROM 6 16 vi Astronics Test Systems Publication 980900 Rev 3352 User Manual Chapter T cC 7 1
9. iaa 2 5 E CIC 2 5 2 7 Astronics Test Systems i 3352 User Manual Publication No 980900 Rev B Memory Add 4 sessi as unc 2 7 EC 2 8 Interrupis Rd 2 8 Hardware Configuration rr 2 8 Logical Addres Mt ER 2 8 WOO SS CLS 2 8 2 8 Module Enable ren ER ERE Ser taped soe ib aor Mp 2 8 2 10 CRON S 2 11 bront AS CITC LOR eus euet beo pieds ature Rade 2 11 CONN OC OS 2 11 Contig ralon RESISIOIS 2 12 VXI Configuration Registers ane dude 2 12 VXI Identification ID 2 12 VXI Device Type 2 12 VXI Status Control err dus 2 13 ute sedulo 2 13 Spe
10. Eg 14 16 015 A15 Note Signals parentheses not used on this module Figure E 2 M210 M Module Interface M210 Connectors E 2 Astronics Test Systems Publication 980900 Rev 3352 User Manual Appendix F M1721 CONNECTORS GROUND 5 2 4 6 8 10 RFSG2PTRG RFSG3PTRG RFSG1ATRG RFSG2ATRG RFSG3ATRG HPSATRG S TRG1A1 SLOTRG2A1 SLOTRG1A3 SYSTRG1 GROUND 15 21 2 4 6 26 15 RFSGS3PLS 2 GROUND 5 8 13 1 Figure 1 M1721 Front Panel Connectors Astronics Test Systems M1721 Connectors F 1 3352 User Manual Publication No 980900 Rev B ES ees Su Km E 14 16 015 A15 Note Signals parentheses not used on this module Figure F 2 M1721 M Module Interface M1721 Connectors F 2 Astronics Test Systems
11. 1 m LT1394 1 7 gt 3 MOD TRG2 gt DAC 4 72 3 3V LDO ACE M Module Interface FPGA Figure 8 1 Functional Block Diagram DSOn DS1n NRN M Module Connector M1721 8 5 3352 User Manual M Module Interface Analog Inputs TTL Inputs Differential Inputs M1721 8 6 Publication No 980900 Rev B The M Module Interface allows communication between the M1721 and the VX405C carrier module The interface is an asynchronous 16 bit data bus The interface adheres to the ANSI VITA 12 1996 Standard for The Mezzanine Concept M Module Specification for MA modules For the Analog Inputs comparators provide high speed analog to digital conversion with programmable threshold levels comparators are configured to provide a fixed hysteresis window for the input signal As an input signal transitions from low to high it must exceed the programmed threshold level plus the hysteresis range to produce a high at the comparator output As an input signal transitions from high to low it must fall below the programmed threshold level minus the Hysteresis range to produce a low at the comparator output The comparator threshold levels are programmable between 2 Volts and 2 Volts The programmable threshold levels are set by programming the DAC Control Register 0 The Input impedance of the Analog Inputs is 50 Ohms
12. J202 68 GND 34 GND 67 9DO 33 GND 66 9D1 32 GND 65 9D2 31 GND 64 9D3 30 GND 63 904 29 GND 62 9D5 28 GND 61 9D6 27 GND 60 9D7 26 GND 59 10DO 25 GND 58 10D1 24 GND 57 10D2 23 GND 56 10D3 22 GND 55 10D4 21 GND 54 10D5 20 GND 53 10D6 19 GND 52 10D7 18 GND 51 1100 17 GND 50 11D1 16 GND 49 11D2 15 GND 48 11D3 14 GND 47 1104 13 GND 46 11D5 12 GND 45 11D6 11 GND 44 11D7 10 GND 43 1200 9 GND 42 12D1 8 GND 41 12D2 7 GND 40 12D3 6 GND 39 1204 5 GND 38 12D5 4 GND 37 12D6 3 GND 36 12D7 2 GND 35 GND 1 GND Astronics Test Systems Publication 980900 Rev 3352 User Manual J203 1 GND 35 GND 2 GND 36 1300 3 GND 37 13D1 4 GND 38 13D2 5 GND 39 1303 6 GND 40 1304 7 GND 41 1305 8 GND 42 13D6 9 GND 43 1307 10 GND 44 1400 11 GND 45 14D1 12 GND 46 14D2 13 GND 47 14D3 14 GND 48 1404 15 GND 49 14D5 16 GND 50 14D6 17 GND 51 14D7 18 GND 52 1500 19 GND 53 15D1 20 GND 54 15D2 21 GND 55 15D3 22 GND 56 15D4 23 GND 57 15D5 24 GND 58 15D6 25 GND 59 15D7 26 GND 60 16DO 27 GND 61 16D1 28 GND 62 16D2 29 GND 63 16D3 30 GND 64 1604 31 GND 65 16D5 32 GND 66 16D6 33 GND 67 16D7 34 GND 68 GND Astronics Test Systems M1721 7 9 3352 User Manual Mating Connectors OPERATING MODE M1721 7 10 Publication No 980900 Rev B The front panel connectors are a double VHDCI SCSI type
13. 201 Shielded 9826 Controlled 982424 Series SCI Cable Impedance 5 202 748364 1 Housing Amplimite 22 1658670 4 M1721 8 12 Astronics Test Systems Publication 980900 Rev Operation Astronics Test Systems 3352 User Manual The M1721 is a register based instrument that is controlled through the registers The CHVX405C carrier maps the registers of the M1721 into the A24 or A32 memory space depending on the switch settings of the carrier As shipped the registers of the M1721 are mapped to the A24 memory space The I O registers described in the previous section are located in the first 20 16 bit words of the A24 memory that is assigned to the module by the slot 0 resource manager The offsets from the base A24 memory address are shown in Table 1 1 Note that all access of the registers should be performed on even addresses and 16 bit wide reads and writes are recommended for proper performance of the module VXIplug amp play style driver and soft front panel are provided with the module This driver provides complete control of the routing and DAC voltage levels provided by the module The driver function rimal721_init must be the first function used in the application program This driver takes the VISA resource descriptor to identify which VXI resource is used by the driver The 1721 function determines whic
14. 8 6 TTE 8 7 ec cT ces 8 7 8 8 STA SYSTRGA tand STA SYSTRG 8 8 STA SYSTRG A and STA SYSTRG B ute 8 8 GATEWAYTRG1 2 8 8 GATEWAYTRG1 GATEWAYTRP 8 8 PULSE HESGS ee 8 8 SYSTRGI S YS TOS oit 8 8 RESOGXATRIG APSA SLOT e ques 8 8 RESG2 PTRIG S 8 8 MODEIRGTarnd MODTRGS 8 8 GROUND 8 8 Identification and Configuration 8 9 Oi TTE ME 8 9 Mod le Identification eae 8 12 Mating is 8 12 RST ANON 8 13 viii Astronics Test Systems Publication 980900 Rev 3352 User Manual mer cc 1 VX405C P1 amp P2 CONNECTORS ai
15. insure cs is initially low write word addr 0x0004 initialize write eebit addr 0x0001 start bit temp value for 1 0 1 lt 7 1 4 write eebit addr temp 5 0 80 7 temp temp lt lt 1 int write eebit unsigned long addr unsigned short value temp 0x0004 value amp 0x0001 set data bit before clock write word addr temp Delay 000005 temp 0x0006 value amp 0x0001 set data bit amp clock write word addr temp Delay 000005 int read eebyte unsigned short addr unsigned short value for 1 7 1 gt 0 1 1 1 4 read eebit addr amp rdval temp temp rdval amp 0x01 lt lt i temp int read eebit unsigned short addr unsigned short value write word addr 0x4 lower clock bit Delay 000005 write word addr 0x6 raise clock bit Delay 000005 read word NOTE 1 write word and read word are low level memory access routines 2 NOT actual code and should be treated as a modeling tool only Figure 4 7 ID PROM Access Routine M212 4 26 Astronics Test Systems Publication 980900 Rev 3352 User Manual Chapter 5 M1708 General The M1708 is a dual clock distribution amplifier housed in a standard BEN single wide register based VXI M module The module will accept one Description 10 MHz square wave signal and or one 10 MHz sine wave input The 10 MHz square wave signal is
16. t eese uices LA ed pd tas 7 1 GENERAL DESCRIPTIO N bites heo t het baa tpa 7 1 Specitications of EgUIDITiBri oo eese rete frd lat ail ob e ues 7 1 ydus 7 1 7 1 752 eo rol eme E 7 2 Applicable 7 3 Ordering Information es 7 3 FUNCTIONAL DESCRIPTION inca terc att a ated eee ata atl atem dete 7 3 hg M EP 7 8 M Module Interface ue Eee eimi 7 4 oid eu tu Db ductae the 7 4 7 5 7 6 M M 7 7 dens etes tier Rt eu it En tuit AL m es 7 8 7 9 Mating 7 10 OPERATING 7 10 Register Definition S roodo deci 7 12 MTZ TAI Hegister 7 12 Revision ID Register O20 e Em 7 12 BIST Command Register pe
17. the RS232 communications 4 command j command displays the difference between the 1PPS input and the 1PPS generated internally by the X72 The 4 command produces number representing the number of TICS in a delta register If the X72 has a 60MHz crystal each TIC is 16 7ns 1 67E 8 Note that this number is in hex format Astronics Test Systems Publication 980900 Rev X72 1PPS Algorithm Operation bhag Changing the y Coefficients Astronics Test Systems 3352 User Manual There are two parameters that can be modified by the user for 1PPS synchronization using the command Damping Factor and Tau Damping factor determines the relative response time and ringing in response to each step Values should be between 0 25 and 4 Values less than 0 25 will default to 0 25 while values over 4 will default to 4 Tau or time constant expressed in seconds and determines the time constant of the PLL for following a step in phase for the reference The range of Tau is 5 100 000 seconds Values outside this range will cause both the Damping Factor and Tau to change to the factory default settings Factory Default The factory default requires no inputs to the rubidium oscillator from the user The default value for Damping Factor is 1 and the default Tau is 400 These values are a good starting point and will work well for most GPS applications At the gt pr
18. DAC ADDRESS 00 MOD TRG 1 Threshold 01 MOD TRG 2 Threshold 10 GATEWAY 1 Threshold Int Threshold Must be set to 1V to 2V 1 5V nominal 11 GATEWAY 2 Threshold Int Threshold Must be set to 1V to 2V 1 5V nominal DAC DATA 000h FFFh Notes 1 MOD TRG Thresholds Ranges are 2 048Volts to 2 047Volts where 000h 2 048V FFFh 2047V 800 OV GATEWAY Thresholds Ranges are 0 Volts to 4 094Volts where 800h 0 Volts FFFh 4 094V M1721 Status Register RSVD Reserved for Future Use DAC Busy gt 0 1 Busy Figure 8 2 M1721 I O Registers continued Astronics Test Systems M1721 8 11 3352 User Manual Module Identification Publication No 980900 Rev B The M1721 has a thirty two word deep 64 byte serial non volatile FRAM to keep information about the module Access is accomplished with normal M module read write operations Data can not be written to the FRAM by user Table 8 2 M Module FRAM Words Word Description Value hex a 2 Module Number 1721 1 31 Matin The front panel connectors are two row right angle headers type of 9 connector Table 8 3 contains manufacture s numbers for the Connectors connectors used to mate to the M1721 Table 8 3 Mating Connectors Connector Manufacture Mating Connector P N Model J200 Shielded 9810 PLMO Housing Controlled 982424 Series SCI Cable Impedance 5
19. ID This front panel LED illuminates whenever the host processor applies the MODID signal to the slot the module is occupying A B C D E F These front panel LEDs illuminate whenever that M MA is properly accessed by the host processor Indicators VX405 2 10 Astronics Test Systems Publication No 980900 Rev 3352 User Manual Connectors VX405C front panel connectors come Front Panel directly from the M MAs them selves therefore they are hd dependent Front panel covers are provided to close front panel openings on any unused M MA locations The covers should be used to control airflow and EMI leakage when there is module installed re The P1 and P2 connectors are configured in accordance with the VXI specification See Figure 2 5 Rear Connectors CARRIER Figure 2 5 3352 Front Panel lt ex Astronics Test Systems VX405 2 11 3352 User Manual Publication No 980900 Rev B Configuration There are a variety of registers used to configure and control the Registers VX405C module The VXI configuration registers provide for control and status as required by the VXIbus specification An address map of the registers is shown in Table 2 1 Table 2 1 VXI Register Address Map A16 Address Register Description VXI ID VXI Device Type The VXI configuration registers contain basic informati
20. Receivers Synergy Systems LLC P N STRMM12 Rev A 24 Nov 03 Box 262250 San Diego CA 92196 www synergy gps com User s Guide GPS Oncore Revision 5 0 Motorola GPS Products 08 30 02 www motorola com M213 3 4 Astronics Test Systems Publication 980900 Rev 3352 User Manual Functional Description Overview M MODULE INTERFACE The 213 utilizes control logic to interface the M Module bus to a Motorola Oncore 12 Timing Receiver The 12 is controlled internally through a serial interface See applicable documents in Chapter 3 section Applicable Documents for details on the 12 A simplified block diagram is shown in Figure 3 1 FRONT PANEL EXTPWR 10 95V PASS EXTPWR THROUG POWER 12 CONVERSION amp PPS OUT Cece toc M Module Interface Control Logic Microcontroller UART Astronics Test Systems DISTRIBUTION INTERNAL Ex PPS OUT CONTRO uC UART Oncore 12 NE S PPS ACTIVE L LOGIC Timing Receiver ANTENNA Figure 3 1 Functional Block Diagram The Interface allows communication between the 213 the carrier module The interface is an asynchronous 16 bit data bus with interrupt and trigger capabilities The interface adheres to the ANSI VITA 12 1996 Standard for The Mezzanine Concept M Module Specification for M modules The control logic provides t
21. ignored The new setting is stored in non volatile memory and will remain the set value until it is changed again When the required memory bits are written the VX405C must be powered off and a resource manager re ran before the change will take effect Due to the required memory setting being stored in non volatile memory a short amount of time is required before the VXI Device Type Register can be accessed again after a write During this time the VXI Heady Bit is cleared in the VXI Status Control Register 0x04 and then set back to 1 when access to the Device Type Register is permitted NOTE If the installed M MA Module supports the VXI IDENT extension non standard to the optional M Module IDENT function the required memory is automatically set according to the M MA Module requirements Refer to M MA Module Identification for details on the VXI IDENT Extension Triggers 405 2 20 If the TRIGI or TRIGO functions are supported by an M MA any of the eight VXI TTL Trigger lines can be connected as either an input or output to TRIGA or TRIGB of the M MA A software programmable register or 0x22 is provided for each to connect TRIGA and TRIGB individually to a VXI TTL Trigger line Both TRIGA and TRIGB can be individually enabled and set as input or output as described in Figure 2 7 An inversion bit is also provided to allow the user to configure the trigger for a rising or falling edge M M
22. of 2 3 or 4 wide modules Supports extended M Module functions MA such as extended 24 bit addressing for up to 16 Mbytes of memory 32 bit data bus and trigger signals for synchronization of MA Modules VXI A16 A24 and A32 addressing supported e 08 016 and 032 accesses supported e Individual Logical Addressing of M MA modules e Isolated filtered and fused 45V 12V and 12V supplies for each M module 24V Auxiliary Power Connector Rev C or higher assemblies only e Separate Software Programmable Interrupt Levels e MA Module TRIGA and TRIGB can be connected to any VXI TTL Trigger Line through software control VX405 2 1 3352 User Manual Publication No 980900 Rev B M MA Module data access time lt 800ns e Front panel EMI shielding e Interactive Mezzanine Control software available The VX405C only requires the 5V power from the VXI back Electrical plane however 12V may be required by installed M modules and 24 may be required if the auxiliary power connection is used The carrier s peak module current for the 5V supply is 1 2 amps A total of 7 2A of 5V is available for the VXI backplane For electrical information on individual M MA s please reference each M MA s documentation The power requirements for each M MA installed must be added to the VX405C s requirements for the total module s requiremen
23. 0 dTempHi 4 dVoltLo 4 41381AF5 Lmp 3FAA43C6 Res 3FA10F45 39500000 B9DD8000 LVolt 3 327288 94005 0000000 2928000 34DC6A dVoltHi 41 C1CA16 iFpgaCtl dCurTemp dLVoutC 3 dRVoutC 3 029E 42690000 E25B538 E19A67E dmv2 demAvg 3F337D72 Astronics Test Systems 212 4 17 3352 User Manual X72 1PPS Functions M212 4 18 Publication No 980900 Rev B The following print out shows how entering letter followed by an integer sets the enable disable feature of FC mode Integer zero followed by disables FC mode nonzero integer followed by cr enables the FC mode r gt a lt nonzero integer gt lt cr gt FC mode enabled r gt a o lt cr gt FC mode disabled The following print out shows the control register contents by entering the letter p r gt p Control Reg 029E The X72 can be configured to e Generate a rubidium controlled 1PPS signal e Measure the difference between an incoming 1PPS signal and the X72 1PPS e Synchronize X72 s frequency 1PPS output to the incoming 1PPS and provide very long holdover times When an externally generated 1PPS signal is applied to pin 19 of the J1 26 pin connector on a properly configured X72 the unit can provide the time interval error difference between the 1PPS input and the 1PPS generated inside of the X72 The difference is read
24. 8 TTL outputs Input High and Low levels are individually programmed for each input e Trigger input with software programmable threshold Non volatile potentiometers retain setting when power is off Switch settings allow full operation at factory set levels no software programming required M Triggers supported source for input channels or trigger output Input B can drive either four TTL outputs or all TTL outputs If Input is configured to drive eight TTL outputs then Input B drives no TTL outputs and vice versa The ECL output of each input signal is not affected Astronics Test Systems M210 6 1 3352 User Manual Publication No 980900 Rev B Specifications MAXIMUM RATINGS Parameter Condition Rating Units Operating Temperature 0 to 50 Non Operating Temperature 40 to 70 C Humidity non condensing 5 to 95 Power Consumption power is 45V 1200 mA shared by both M module connectors 12V 50 mA 12V 400 mA Input Voltage INA INB no damage 10 Vrms TRIGIN M210 6 2 Astronics Test Systems Publication No 980900 Rev AC CHARACTERISTICS 3352 User Manual Limit Parameter Conditions Min Typ Max Units Common Input Characteristics Voltage Range 5 0 5 0 Input Impedance Switch 500 48 50 52 Q Switch Hi Z 10K 10 3K 106 0 Level Adjust Re
25. Altitude 0 C to 50 096 to 9096 3 000 meters non condensing 9 843 feet 40 to 70 0 to 90 non condensing Transportation 40 to 70 C 0 to 90 non condensing Physical Specifications Specification idth Standard single width M module m Height Standard single width M module Depth Standard single width M module eight Approximately 0 2 kg 1708 5 6 Astronics Test Systems Publication 980900 Rev 3352 User Manual General Description Purpose of Equipment Specifications of Equipment Key Features Chapter 6 M210 The M210 provides distribution of clock signals to other devices The module accepts two analog input signals and provides TTL and ECL distribution input signals are passed through high speed comparators that convert the analog level to a digital signal The digital signals are individually buffered to provide the TTL and ECL outputs The module is physically implemented on a double wide M Module adhering to the ANSI VITA 12 1996 specification for M Modules The M210 can be used in a wide variety of applications including functional verification of digital systems signal simulation design verification and research and development that require the distribution of clock and timing signals Two Input Channels 100MHz Maximum Frequency Each input channel supports 1 ECL output and 4 TTL outputs e Input A or B be configured to support
26. GND 45V 12V 12V GND DREQ GND D00 A08 001 D02 A10 0 11 D04 A12 DO5 A13 06 414 D07 A15 DSO WRITE m S m e 2 Publication No 980900 Rev B 022 023 g 0 Y Note Signals in parentheses not used on this module Figure B 2 M213 M MA Interface Connector Configuration M213 Connectors B 2 Astronics Test Systems Publication 980900 Rev 3352 User Manual Appendix C M212 CONNECTORS PIN 1 EXTPWR PIN 2 GND PIN 4 GND PIN 5 GND PIN 6 EXTPWR PIN 7 GND PIN 8 SERVICE PIN 9 LOCK 1PPSIN 1PPSOUT SINEOUT LOCK SQUOUT M212 Figure C 1 M212 Front Panel I O Signals Astronics Test Systems M212 Connectors C 1 3352 User Manual Publication No 980900 Rev B Rows ES Sud Eg 14 16 015 A15 Note Signals parentheses are not used on this module Figure C 2 M212 M MA Interface Connector Configuration M213 Connectors C 2 Astronics Test Systems Appendix D M1708 CONNECTORS A high density DB15 female output connector suppli
27. IEEE STD 1014 1987 IEC 821 Manufacturer ID Model Code VXI Access Type VXI Addressing VXI Data Transfer VXI Sysfail VXI Interrupts VXI Local Bus TTL Triggers Memory Requirements M MA Module Compliance ANSI VITA 12 1996 American FC146 or VXI IDENT value 216 VXI IDENT value Register Based A16 A24 A32 D8 D16 D32 supported ROAK or RORA programmable levels not used SYNC trigger protocol supported M MA dependent up to 16Mbytes VXI 32Mbytes M Module MA Module 08 A24 008 D16 032 INTA INTB INTC TRIGI TRIGO IDENT National Standard for The Mezzanine Concept M Module Specification Approved May 20 1997 VMEbus International Trade Association 7825 E Gelding Dr Suite 104 Scottsdale AZ 85260 3415 E mail info vita com URL http www vita com Remove the 3352 module and inspect it for damage If any damage is apparent inform the carrier immediately Retain shipping carton and packing material for the carrier s inspection Verify that the pieces in the package you received contain the correct 3352 module option and the 3352 Users Manual Notify Customer Support if the module appears damaged in any way Do not attempt to install a damaged module into a VXI chassis The 3352 module is shipped in an anti static bag to prevent electrostatic damage to the module Do not remove the module from the anti static bag unless it is in a static controlled area VX405 2 3 335
28. No 980900 Rev B Specifications MAXIMUM RATINGS Parameter Condition Rating Units Operating Temperature 0 to 50 Non Operating Temperature 40 to 70 Humidity non condensing 5 to 95 96 Power Consumption power is 45V 500 mA shared by both M module connectors 12V 700 mA 12V 150 mA Input Voltage Differential no damage 10 5 Vrms Input Voltage TTL Digital no damage 7 2 Vrms Input Voltage Analog no damage 8 Vrms M1721 8 2 Astronics Test Systems Publication 980900 Rev 3352 User Manual AC CHARACTERISTICS Limit Parameter Conditions Min Typ Max Units Analog Input Characteristics Voltage Range 5 0 45 0 V Input Impedance 49 50 51 Q Level Adjust Resolution 12 bit 1 mV Threshold Level Range 2 0 2 0 V Threshold Level Input Impedance 509 2 50mV Accuracy Setpoint Hysteresis 15 30 45 mV Frequency 2N p p Input 0 50 MHz Width 2V p p Input 10 ns Differential Input Characteristics Voltage Range 0 45 0 Input Impedance Pull up to 5V 90 95 1 0 Threshold Level Range Differential Input 100 100 mV Hysteresis Differential Input 65 mV Frequency 2N Differential Input 0 50 MHz Width 2V Differential Input 10 ns Digital TTL Input Characteristics Voltage Range 0 45 0 IV Input Imp
29. an individual interrupt level and is handled separately during interrupt acknowledge cycles hardware priority for each interrupt programmed to the same level begins with M MA slot A s interrupt being the highest priority and M MA slot F s Interrupt being the lowest priority For further detail refer to Chapter 2 section Interrupts below The logical address address space and positions of the occupied M MA module locations must be configured prior to installing the carrier into the chassis The configuration is done using the switches described below and shown in Figure 2 4 Each M MA location has its own logical address based on a five position address switch The selected logical address establishes the address for position A The other positions follow in sequential or modulo 8 order depending on the Modulo Select switch See Chapter 2 section Logical Address Selection for more details This switch allows the user to set the desired numbering sequential or modulo 8 of the logical addresses assigned to each M MA location on the VX405C The switch is located at position 7 of the logical address switch For further details referto Chapter 2 section Logical Address Selection This switch selects either A24 or A32 addressing The switch is located at position 8 of the logical address switch For A24 addressing the switch should be set in the OPEN or 1 position Six switches are provided to enable the individual M MA locations E
30. by Hewlett Packard This optional function is not part of the approved ANSI VITA 12 1996 standard This extension to the M module IDENT function increases the size of the EEPROM to at least 64 words 128 bytes and includes VXI compatible ID and Device Type registers Details are shown in Table 2 2 Table 2 2 the VX405C automatically checks the M MA Module for support of this optional function during power up If the VX405C detects support then the VXI Manufacturer ID in the VXI ID register and the Required Memory and Model Code in the VXI Device Type register are changed to reflect the settings provided by the M MA Module Table 2 2 Module EEPROM IDENT Words 0 56 Reserved L 5 73 lt 2 p coco cs cer Note VXI Device contains two fields bits 0 11 are the Model Code and bits 12 15 are the Regu 297 ir ed Memory where where m is the value of the four bits Model Code manufacturer specified model number Built in Test and Diagnostics Trouble Analysis Guide 405 2 22 During power up initialization a basic built in test function is performed an initialization failure is detected the SYSFAIL lamp will light indicating a failure Sysfail Inhibit can be used to help isolate the cause of the failure The Sysfail Inhibit is a VXI slot inhibit therefore setting the inhibit bit on any M MA module
31. current state of the output read the port to get any failures since the last read Read again to get any current failures Bits7 3 not used read 0 Bit2 Out2 Status 1 fault Outi Status 1 fault Serial EEPROM Data ignore Connectors Refer to Appendix D for connector and pin assignments Specifications 1708 5 4 Astronics Test Systems Publication 980900 Rev 3352 User Manual Electrical Specifications Item Specification Module Current 5 V 0 01 12 12V 0A 24 V 0A 24 V 0A 5 2V 0A 2V 0A Impedance 50 Nominal input 3 V peak 5 V Maximum Input 2 MMCX Female Output 2 SMB Female 1 high density DB15 Female Standard M module carrier board connector A8 D16 Register based M Module Circuitry Sine wave output parameters Gain 3 5 dB Level Maximum 15dBm into 50 Isolation between outputs 90 dB output parameters Rise and Fall times 3 0 ns Skew channel to channel 500 ps Jitter 50 ps rms High level 3 V minimum into 50 Isolation between outputs 80 dB Spectral Purity sine outputs Harmonics lt 40 Spurious 80 dBc Phase Noise 10 Hz offset 90 dBc Hz 100 Hz offset 128 dBc Hz 1 kHz offset 140 dBc Hz 10 kHz offset 147 dBc Hz Astronics Test Systems 1708 5 5 3352 User Manual Publication No 980900 Rev B Environment Specifications Item Temperature Relative Humidity
32. employees subsidiaries affiliates and distributors harmless against all claims arising out of a claim for personal injury or death associated with such unintended use Before undertaking any troubleshooting maintenance or exploratory procedure read carefully the WARNINGS and CAUTION notices RISK OF ELECTRICAL SHOCK human lite and safety and is capable of inflicting DO NOT OPEN personal injury CAUTION This equipment contains voltage hazardous to If this instrument is to be powered from the AC line mains through an autotransformer ensure the common connector is connected to the neutral earth pole of the power supply Before operating the unit ensure the conductor green wire is connected to the ground earth conductor of the power outlet Do not use a two conductor extension cord or a three prong two prong adapter This will defeat the protective feature of the third conductor in the power cord Maintenance and calibration procedures sometimes for operation of the unit with power applied and protective covers removed Read the procedures and heed warnings to avoid live circuit points SENSITIVE ELECTRONIC DEVICES Before operating this instrument 1 Ensure the proper fuse is in place for the power source to operate 2 Ensure all other devices connected to or in proximity to this instrument are properly grounded or connected to the protective third wire earth
33. enabled A URTI interrupt only occurs when it becomes active 4 j UART Data Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write Not Used Data Read Not Used Data Note A write to Data transmits the byte to the 12 timing receiver module read of Data receives one byte of data from the 12 receive FIFO A Special Character OxFF indicates that the FIFO is empty Figure 3 4 M213 I O Registers M213 3 8 Astronics Test Systems Publication 980900 Rev M Module Identification PROM 3352 User Manual The M213 supports the identification function called IDENT This IDENT function provides information about the module and is stored in a sixteen word deep 32 byte serial EEPROM Access is accomplished with read write operations on the last address in hex FE and the data is read one bit at a time Figure 3 5 provides an example of how to read from the serial EEPROM The modules also support the VXI IDENT function introduced by Hewlett Packard This function is not part of the approved ANSI VITA 12 1996 standard This extension to the M module IDENT function increases the size of the EEPROM to at least 64 words 128 bytes and includes VXI compatible ID and Device Type Registers Details are shown in Table 3 2 Table 3 2 M Module EEPROM IDENT Words 0 SyncCode Reserved Reserved Notes 1 The Revision Number is the functional revis correspond to the hardware assembly leve
34. for future use and are set to 0 Figure 7 4 and Table 7 5 describe these bits Figure 7 4 BIST Status Register Bit Assignment for the M1714 BIST Status Register Bit 7 Bit 0 Bi Bi Bit 4 Bi Bit 2 Bit 1 MSB it 6 it5 it it3 it it LSB BIST BIST X X X X X X Fail Busy Table 7 5 BIST Status Register Bit Definitions Bit Function BIST Busy 0 A value of 1 indicates that the M1714 is performing a BIST cycle This flag will be set to 0 upon the completion of the BIST cycle Set to 0 after reset BIST Fail 1 A value of 1 indicates that a failure has been detected during the BIST cycle This bit is reset by writing 1 to bit 1 of the Command register Set to 0 after reset 7 2 Reserved Direction Control This is a read write register that controls the direction of the corresponding byte octet All eight channels within the octet will for Octets 1 8 have the same direction Writing a 1 to this register will set the appropriate octet to an output stimulus A 0 value will set the octet to an input response This register is set to 0 after reset Figure 7 5 describes this register Figure 7 5 Direction Control for Octets 1 8 Direction Control Reg for Octets 1 8 Bit 7 Bit 0 Bi Bi Bit 4 Bi Bit 2 Bit 1 MSB it 6 it5 it it3 it it LSB Octet Octet Octet Octet Oct
35. must be done only while the power to the module is OFF Logical Address Selection Astronics Test Systems The logical address is set for each M MA module by selecting the starting logical address and the desired sequencing sequential or multiple of 8 of addressing using the toggle switches provided on the carrier With sequential logical addressing Modulo Select switch in the Up position the starting logical address can be selected as any multiple of 8 i e 8 16 or 248 The M MA in location A is assigned the starting logical address and the remaining locations enabled or disabled are assigned logical addresses in sequential order i e 8 9 10 With Modulo 8 logical addressing Modulo Select switch in the Down position the starting logical address can be selected as any multiple of 64 i e 64 128 or 192 The M MA in location A is assigned the starting logical address and the remaining locations enable or disabled are assigned logical addresses in multiples of eight i e 64 72 80 etc disabled M MA location is still counted when determining the logical address of the enabled locations however the disabled location will not respond when queried by the resource manager and the logical address can be used elsewhere in the system VX405 2 17 3352 User Manual Example of sequential addressing STARTING LOGICAL ADDRESS 1 28 64 32 16 MODULO SELECT UP 1 OPEN
36. oscillator Serial data received from the X72 is converted into 8 bit data bytes and stored in a FIFO to be read by the user The FIFO can store approximately 512 bytes Use the Datum Serial Interface Protocol in the X72 Designer s Reference for command details X72 outputs are all decimal DATA as ASCII Coded Hex except for echoed characters The following example shows how data are encoded Do not convert data to decimal when transmitting to the X72 data are sent to the X72 and received back as ASCII Coded The following example shows how data are encoded NOTE Flow control is not permitted in Mode Data sent to the X72 in run mode should not be encoded M212 4 14 Astronics Test Systems Publication 980900 Rev 3352 User Manual Data sent to the X72 in run mode should not be encoded Example of output from unit Example 1 actual unit output Example of output from X72 after power applied to the unit X72 by Symmetricom Inc Copyright 2001 SDCP Version 3 75 of 3 2001 Loader Version 2 Mode CNN1 Flag 0004 822F ok Unit serial code is 0009AB001B h current tuning state is 6 Crystal 60000000hz ACMOS 10000000 0hz Sine 10000000 0hz Ctl Reg 029C Res temp off 1 5410 Lamp Temp off 2 1142 FC Enabled Srvc high Enter Run Mode FC Mode is enabled f The following print out is an example of the response one gets by entering the letter i to get serial number and oth
37. outputs of the Differential Receivers at high frequencies to valid TTL levels The trigger levels of these comparators needs to be programmed in order for the Differential Input channels to work properly Typically Astronics Test Systems Publication 980900 Rev TTL Outputs ECL Outputs Astronics Test Systems 3352 User Manual the levels are between 1 0Volts and 2 0Volts Refer to the DAC Control Register for further details The comparator trigger levels can be Factory set to fixed voltage levels as an option Up to Nine TTL outputs provide TTL compatible signal distribution of the input signals Some inputs can be distributed to up to as many as five TTL outputs or the module can be configured to distribute a single input to all five TTL outputs The Sources of the TTL Outputs are selected through the Control Register 0 Each TTL output consists of four output buffers in parallel The output source impedance of each individual driver is 750 thus providing an overall output source impedance of 18 75 O that can drive TTL compatible logic levels into a 500 load Two ECL outputs provide differential ECL compatible signal distribution of the inputs The sources SYSTRG 1 and SYSTRG 2 of the ECL signals are fixed and dedicated to the STA SYSTRGA and STA SYSTRGB ECL outputs respectively The differential ECL outputs are terminated through 4990 resistors to 5 2V High speed ECL outputs need to be terminated with a sma
38. resolution is 39mV per bit 2 The TRG LEVEL switch must be set to PRG for the programmed threshold to take affect Figure 6 4 M210 I O Register continued The M210 supports the identification function called IDENT This IDENT function provides information about the module and is stored in a sixteen word deep 32 byte serial PROM Access is accomplished with read write operations on the last address in lOSpace hex FE and the data is read one bit at a time Instructions for reading the IDENT PROM are given in Chapter 6 section ID PROM Data can not be written to the PROM Module Identification The module also supports the VXI IDENT function This function is not part of the approved ANSI VITA 12 1996 standard This extension to the M module IDENT function increases the size of the PROM to 64 words and includes VXI compatible ID and Device Type Registers Details are shown in Table 6 2 Astronics Test Systems 210 6 13 3352 User Manual Publication No 980900 Rev B Table 6 2 M Module PROM IDENT Words 0 536 M Module Specific 0000 _____ Notes 1 The Revision Number is the functional revision level of the module It does not necessarily correspond to the hardware assembly level 2 The Module Characteristics bit definitions are Bit s Description 15 0 no burst access 14 13 unused 12 1 needs 12V 11 1 needs 5V 10 1 trigger
39. the ECL output positive signals ECLOUT1 ECLOUT2 ECLOUT2 These signal contacts are the ECL output negative signals ECLOUT1G and These signal contacts are the ECL output ground signals ECLOUT2G TRG This MMCX connector is the TRGIN signal input TRGIN can be input through this connector or through the internal PCB MMCX connector Astronics Test Systems M210 6 9 3352 User Manual Publication No 980900 Rev B INB This MMCX connector is the INB signal INB can be input through this connector or through the internal PCB MMCX connector INA This MMCX connector is the INA signal INA can be input through this connector or through the internal PCB MMCX connector TTLOUT1 8 These MMCX connectors are the TTL output signals TRGOUT1 and TRGOUT2 These internal PCB mounted MMCX connectors are the distributed TRGOUT signals 1 ECLOUT1 2 ECLOUT1 6 ECLOUT1G 3 GND 4 ECLOUT2 2 5 ECLOUT2 9 ECLOUT2G o OOO0000 TTLOUT A 6 3 210 210 6 10 Astronics Test Systems Publication 980900 Rev 3352 User Manual Identification and Configuration Registers There a variety of registers used to configure Registers control the M210 module These registers are located in the lOSpace The address map of the registers is shown in Table 6 1 Details of the registers are provided in Figur
40. will inhibit SYSFAIL on all M MA modules The following is a general guide of the most common problems that may be encountered with the VX405C along with a suggestion of the possible causes Astronics Test Systems Publication 980900 Rev SYMPTOMS Bus time out on A16 Access Unable to access M MA space Astronics Test Systems 3352 User Manual POSSIBLE CAUSES Be SE IS Logical address incorrectly set Card incorrectly installed M MA enable switch not enabled Logical address Modulo Select switch not set expected Attempting to access an improper address VXI memory setting for that M MA not set to 2 x M MA s required memory AAA bit in the Status Control register not set to allow A32 A24 addressing A24 A32 switch set improperly Offset register not set correctly VX405 2 23 3352 User Manual Publication No 980900 Rev B This page was left intentionally blank 405 2 24 Astronics Test Systems Publication 980900 Rev 3352 User Manual Chapter 3 M213 General The M213 provide GPS timing in a single wide M Module format D ipti adhering to the ANSI VITA 12 1996 specification for M Modules escription Purpose of The M213 can be used in a wide variety of applications where a Equipment precision timing control is required Specifications of Equipment e ANSI Standard M Module single wide Module Key Features e Motorola Oncore M12 GPS Timing
41. write register sets the interrupt level and provides the upper byte of vector for M MA interrupt types INTA and INTB Trigger Control Register base 0 16 or base 22 5 This read write register selects a VXI TTL Trigger line for the TRIGA and TRIGB functions and sets them as input or output using the VXI TTLTRG Synchronous SYNC Trigger Protocol Astronics Test Systems 405 2 15 3352 User Manual Publication No 980900 Rev B 08 Interrupt Control Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write Interrupt Vector LI Interrupt Level Read InteruptVector IT IVE Interrupt Interrupt Vector gt Upper 8 bits of the interrupt vector for type INTA and INTB interrupts Default 0 Interrupt 0 follows interrupt type used by installed M Module 1 ROAK regardless of M Module interrupt type Interrupt Level gt Interrupt Level for the M MA interrupt Level of 0 disables the interrupt Default disabled Interrupt vector enable 0 returns the M module vector if supported by the M Module 1 returns the interrupt vector programmed in this register Default 1 0A Trigger Control Register Bit 15 14 11 1 13 12 0 9 8 7 6 5 4 3 2 1 0 Write BNV Trig TTL Sel AENDA AN T Trig A TTL Sel Read BEN Trig B TTL Sel AEN ADIR AW Trig A TTL Sel AEN gt Trigger enable for Trig 1 en
42. 05C has no logical address or programmable registers associated with it thus allowing the carrier to be completely transparent in the VXI system VX405 2 5 3352 User Manual 405 2 6 VXI I F M MA Module E Publication No 980900 Rev B amp VXI Registers M MA Module A amp VXI Registers amp VXI Registers M MA Module B amp VXI Registers Figure 2 2 VX405C Functional Block Diagram amp Registers amp VXI Registers Astronics Test Systems Publication 980900 Rev Interfaces I O and Memory Addressing 3352 User Manual The six M MA locations interface electrically and mechanically with industry standard M MA modules meeting the ANSI VITA 12 1996 M Module Specification approved May 20 1997 Each M MA has its own I O connector and is accessible through the front panel of the VX405C via the connector or a user provided cable The VX405C supports 08 016 and 032 data access as well as A16 A24 and A32 addressing The VXI registers of the M MAs are accessible in the A16 address space The VXI Offset Register is used to map the I O Space and MA Memory if applicable into the A24 or A32 addressing space For MA s that support memory the memory begins at the mid point of the total memory required
43. 12 satellites and includes automatic site survey for accurate antenna position location An external power input keeps the Rubidium very stable over time and keeps the GPS settings in memory from becoming corrupt during the absence of VXI test station power Using ANSI Standard M module building blocks the 3352 integrates a Rubidium oscillator a GPS timing receiver and clock and trigger distribution into a single slot package The module is an integration of several standard products as shown below The M210 and M1721 Trigger Distribution boards and GPS antenna are optional The GPS antenna option includes a Motorola Oncore Timing2000 antenna and 15 meters of coaxial cable The 3352 comes in five different configurations The versions are differentiated by the amount of M module population The following lists the different versions of the 3352 along with a table of M module population for each 1 407919 3352 with GPS 2 407919 001 3352 w o GPS 3 407919 002 3352 with GPS and Trigger Distribution RTCASS version 4 407919 003 3352 with Digital GPS 5 407919 004 3352 with GPS and Trigger Distribution Upgrade 3352 VX405C M212 M213 M1708 M210 M1714 M1721 Version 407919 X X x x 407919 001 X X X 407919 002 X X X X X 407919 003 X X X X 407919 004 X X X X X Astronics Test Systems Introduction 1 1 3352 User Manual Publication No 980900 Rev B This manual covers all five
44. 2 User Manual Handling Precautions Installation of MMMA Modules WARNING Publication No 980900 Rev B The VX405C 3352 contains components that are sensitive to electrostatic discharge When handling the module for any reason do so at a static controlled workstation whenever possible At a minimum avoid work areas that are potential static Sources such as carpeted areas Avoid unnecessary contact with the components on the module M MA modules must be installed before the VX405C 3352 is installed into the VXI system To install modules remove the 405 5 top shield and front panel covers as needed There is never a need to remove the VX405C s bottom shield Install M MASs by firmly pressing the connector on the M MA together with the connector on the carrier Secure the M MA through the holes in the bottom shield using screws provided with the M MA For installing M MA modules in locations E or F longer screws are provided if necessary to accommodate the standoffs required on the 405 in those locations The VX405C supports MA Modules that use three row interface connectors M Modules use only two rows connectors and must be correctly positioned to use rows A and B on the carrier When using M Modules row C on the VX405C is left unconnected TRIGGER DISTRIBUTION M MODULE PRECISION RUBIDIUM B OSCILL
45. 4k 9 16K 16K F 64K 8 32K 32K F 64K 7 64K 64K E 128K 6 128K 128K D 256K 5 256K 256 512 4 512 512 1M 3 1 1M A 2M 2 2M 2M 9 AM 1 4M 4M 8 8M 0 8M 8M 7 16M 16M 6 32M Figure 2 6 VXI Configuration Registers VX405 2 14 Astronics Test Systems Publication 980900 Rev 3352 User Manual 04 VXI Status Control Bit 15 14 13 12 11 10 9 8 7 6 5 4 write DANA e qoo qs og pop i 5 A24 A32 Access 0 disabled Module ID Status 0 P2 MODID line is selected CSE Check Sum Error 0 error reading non volatile memory during power up Reset on read 1 OK RDY Ready 1 ready Pass Pass fail indicator 0 executing or failed 1 passed 51 5 Inhibit 1 inhibit see note RST gt Reset writing a 1 to this bit resets the M module after a minimum of 100 us 0 must be written to resume normal operation Note Sysfail Inhibit is a VXI slot inhibit therefore setting the inhibit bit on any M MA module will inhibit SYSFAIL on all M MA modules T VXI Offset Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write Offset Value Read Offset Value Offset Value gt Offset to M MA s I O Space and Memory if applicable Figure 2 6 VXI Configuration Registers continued Special Function Register Interrupt Control Registers base 0816 or base 2016 This read
46. 8 bit read only register contains a value that defines the revision number of the M1714 Initially this value is set to 01 h If a revision change has been made to either the M1714 PCB or CPLD this value will be incremented This register provides basic control over the device s BIST functions Only bits 1 and 0 are currently defined in this 8 bit register Bits 7 through 2 are reserved for future use After reset all bits in this register are set to zero Figure 7 2 and Table 7 4 describe these bits and how they should be set for operation of the M1714 Figure 7 3 Command Register Bit Assignment for the M1714 BIST Command Register Bit 7 Bit 0 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Reset Initiate X X X X X X BIST BIST Fail Cycle Table 7 4 BIST Command Register Bit Definitions Bit Function Initiate BIST Cycle 0 When set to 1 initiates a BIST cycle The BIST Busy flag will be set in the status register Set to 0 after reset 1 Reset BIST Fail A value of 1 resets the BIST Fail flag in the status register Set to 0 after reset 7 2 Reserved M1721 7 12 Astronics Test Systems Publication 980900 Rev 3352 User Manual Status Register This register tracks the status of the M1714 BIST Only bits 1 and 0 04h are currently defined in this 8 bit register Bits 7 through 2 are reserved
47. ASTRONICS TEST SYSTEMS Racal Instruments 3352 VXI Rubidium User Manual Publication No 980900 Rev B Astronics Test Systems Inc 4 Goodyear Irvine CA 92618 Tel 800 722 2528 949 859 8999 Fax 949 859 7139 atsinfo astronics com atssales astronics com atshelodesk astronics com _http Awww astronicstestsystems com Copyright 2004 by Astronics Test Systems Inc Printed in the United States of America All rights reserved This book or parts thereof may not be reproduced in any form without written permission of the publisher YOU FOR PURCHASING THIS ASTRONICS TEST SYSTEMS PRODUCT For this product or any other Astronics Test Systems product that incorporates software drivers you may access our web site to verify and or download the latest driver versions The web address for driver downloads is http www astronicstestsystems com support downloads If you have any questions about software driver downloads or our privacy policy please contact us at atsinfo astronics com WARRANTY STATEMENT All Astronics Test Systems products are designed to exacting standards and manufactured in full compliance to our AS9100 Quality Management System processes This warranty does not apply to defects resulting from any modification s of any product or part without Astronics Test Systems express written consent or misuse of any product or part The warranty also does not apply to fuses software non rechargeable ba
48. ATOR M MODULE GPS TIMING RECEIVER M MODULE CLOCK DISTRIBUTION M MODULE VX405C M MODULE CARRIER VX405 2 4 Figure 2 1 3352 M MA Configuration Diagram Astronics Test Systems Publication 980900 Rev Installation of VX405C Carrier 3352 Functional Description General Astronics Test Systems 3352 User Manual Set the module s logical address and addressing mode as described in Chapter 2 sections Logical Address Selection and Address Space Selection Insert the module into the appropriate slot according to the desired priority Apply power If no obvious problems exist proceed to communicate with the module as outlined in Chapter 2 section Operating Instructions The VX405C carrier provides a mechanical and electrical interface between VXlbus system and up to six ANSI VITA 12 1996 standard M MA modules The carrier provides VXI register configuration and access to the M MA module s I O Space and Memory if present Each M MA is controlled separately and appears as a different logical address in the VXI environment A simplified block diagram of the module is shown in Figure 2 2 The VX4
49. As on the carrier can be connected to the same VXI TTL Trigger line to synchronize the M MAs Astronics Test Systems Publication 980900 Rev Interrupts M MA Module Identification Astronics Test Systems 3352 User Manual The ANSI VITA 12 1996 M Module Specification specifies that an M MA module may generate an interrupt The VXI interrupt level is programmed by writing the desired level into the Interrupt Level field of the Interrupt Control Register 0x08 or 0x20 Writing a zero to the Interrupt Level field disables the interrupt for that M MA M MA modules can support Type A B or C interrupts A Type A interrupter requires software to access the module to release the interrupt request sometimes referred to as release on register access RORA A Type B interrupter releases the interrupt request during the hardware interrupt acknowledge cycle sometimes referred to as release on acknowledge ROAK A Type C interrupter is the same as a Type B interrupter except the M MA module also supplies an interrupt vector during the interrupt acknowledge cycle Type A and B interrupters must use the software programmable Interrupt Vector field of the Interrupt Control Register 0x08 for the upper byte of the VXI interrupt vector VXI Status ID during the interrupt acknowledge cycle To enable this action set the IVE bit to 0 in the Interrupt Control Register The lower byte of the interrupt vector is the logical address of the
50. CRIPTION Overview Astronics Test Systems 3352 User Manual ANSI VITA 12 1996 Standard for The Mezzanine Concept M Module Specification Approved May 20 1997 American National Standards Institute and VMEbus International Trade Association 7825 E Gelding Dr Suite 104 Scottsdale AZ 85260 3415 WWW Vita com Listed below are part numbers for the M1714 Digital I O M Module ITEM DESCRIPTION PART M1714 M Module 128 Channel 405262 Digital Additional Manual 980900 The M1714 utilizes control logic to interface the M Module bus to a series of digital I O ports The l O ports are driven and received via four 68 pin connectors mounted on the front panel A simplified block diagram is shown in Figure 7 1 M1721 7 3 3352 User Manual M Module Interface Control Logic M1721 7 4 Publication No 980900 Rev B M1714 Block Diagram s tM MODULE INTERFACE Figure 7 1 M1714 Block Diagram The M Module Interface allows communication between the M1714 and the carrier module The interface is an asynchronous 8 bit data bus The interface adheres to the ANSI VITA 12 1996 Standard for The Mezzanine Concept M Module Specification for M modules The control logic provides the electrical interface between the M module bus and the module The control registers are contained within this logic The control logic also monitors the
51. Data Register Octet 8 Stimulus Data Register Octet 9 Stimulus Data Register Octet 10 Stimulus Data Register Octet 11 Stimulus Data Register Octet 12 Stimulus Data Register Octet 13 Stimulus Data Register Octet 14 Stimulus Data Register Octet 15 Stimulus Data Register Octet 16 Stimulus Data Register Read M1714 Identity M1714 Revision BIST Status Register Reserved Reserved Direction Control Reg for Octets 1 8 Direction Control Reg for Octets 9 16 Master Read Strobe for Response Data Octet 1 Response Data Register Octet 2 Response Data Register Octet 3 Response Data Register Octet 4 Response Data Register Octet 5 Response Data Register Octet 6 Response Data Register Octet 7 Response Data Register Octet 8 Response Data Register Octet 9 Response Data Register Octet 10 Response Data Register Octet 11 Response Data Register Octet 12 Response Data Register Octet 13 Response Data Register Octet 14 Response Data Register Octet 15 Response Data Register Octet 16 Response Data Register M1721 7 11 3352 User Manual Register Definitions M1714 ID Register 00h Revision ID Register 02h BIST Command Register 04h Publication No 980900 Rev B The following sections described the register and bit definitions that are contained within the M1714 This 8 bit read only register identifies the M module as a M1714 module The value assigned to M1714 is 9 and is hard wired inside the CPLD core This
52. Delta Register as well as the 1PPS state See the following Table 4 3 The output format will appear similar to the following r j Delta Reg 39386F5 lppsState 6 Table 4 3 1PPS States Returned with the j Command Description Expected Values Action Being Performed INITIALIZEOSTATE 0 Start up initialization INITIALIZE1STATE 1 Start up initialization INITIALIZE2STATE 2 Start up initialization HOLDOVERSTATE 3 Seeking useable 1PPS JAMSYNC1STATE 4 Synch X72 output 1 PPS to input JAMSYNC2STATE 5 Synch X72 output 1PPS to input DISCIPLINESTATE 6 Keep X72 output 1PPS aligned to input by controlling X72 frequency PIDCALCSTATE 7 Calculations for disciplining algorithm PDATEDDSSTATE Update X72 DDS based on PIDCALSTATE output ALCSLOPESTATE 9 Calculate slope of incoming 1PPS vs X72 1PPS during holdover M212 4 20 Astronics Test Systems Publication 980900 Rev 3352 User Manual The Command _ With the g command the user can change the X72 to operate in any of three modes which affect the output of the Lock Pin pin 21 Note that this 1PPS mode can be changed by the user but cannot be saved If power is cycled to the unit it will revert to the factory default The modes are 0 1PPS Disciplining Disabled Normal Rb Lock Pin functionality Only the Rb loop needs to be locked to indicate a locked condition on pin 21 1 1PPS Disciplining Enabled Normal Lock Pin functionalit
53. Electrical Characteristics Front panel Output Level High into high impedance _ _ V min load mE V max Low into high impedance load Output Impedance 3 7 Q typ Output Source Sink cae mA Current External Power Supply Input Voltage 10 to 30 Vdc Notes 1 1PPS or 100PPS with position hold active 2 As measured at receiver the M12 RF connector Astronics Test Systems M213 3 3 3352 User Manual Publication No 980900 Rev B The mechanical dimensions of the module are in conformance with ANSI VITA 12 1996 for single wide M Module modules The nominal dimensions are 5 687 144 5 mm long x 2 082 106 2 mm wide Mechanical The module complies with the ANSI VITA 12 1996 Specification for double wide M Modules and the MA Module trigger signal extension The module also supports the optional IDENT and VXI Bus Compliance IDENT functions Module Type MA Module Addressing A08 Data D8 Interrupts INTA amp INTC DMA not supported Triggers not supported Identification IDENT and VXI IDENT Manufacturer ID Model Number 0004 212 dec VXI Model Code OFDE M212 Applicable ANSI VITA 12 1996 Standard for The Mezzanine Concept M Module Specification Approved May 20 1997 American National Documents Standards Institute and VMEbus International Trade Association 7825 E Gelding Dr Suite 104 Scottsdale AZ 85260 3415 www vita com Users Guide Motorola M12 GPS Positioning And Timing
54. M MA module Type C interrupters provide their own upper byte of the interrupt vector during the interrupt acknowledge cycle The VXI specification recommends that modules use the ROAK interrupt protocol This recommendation can be supported by using an module the uses B or Type C interrupts or by simply setting the interrupt type IT bit to a 1 in the Interrupt Control register Setting the IT bit to 1 causes the VX405C to release the interrupt request during the hardware acknowledge cycle regardless of the interrupt type used by M MA module For Type A interrupters the VX405C will release the interrupt request to the VXI during the interrupt acknowledge cycle but the interrupt from the M MA will still be pending until the appropriate IO register is accessed The VX405C will not issue another interrupt to the VXI from that M MA until the M MA s interrupt is cleared The ANSI VITA 12 1996 M Module Specification allows for an optional identification function called IDENT This IDENT function provides information about the M MA module and is stored in sixteen word deep 32 byte serial EEPROM Access is accomplished with read write operations on the last address in I O space and the data is read one bit at a time Access to the IDENT is only guaranteed after a reset is performed VX405 2 21 3352 User Manual Publication No 980900 Rev B The 405 also supports the optional VXI IDENT function introduced
55. M Module The M212 supports the identification function called IDENT 7 This IDENT function provides information about the module Identification PROM and is stored in a sixteen word deep 32 byte serial EEPROM Access is accomplished with read write operations on the last address in lOSpace hex FE and the data is read one bit at a time The modules also support the VXI IDENT function introduced by Hewlett Packard This function is not part of the approved ANSI VITA 12 1996 standard This extension to the M module IDENT function increases the size of the EEPROM to at least 64 words 128 bytes and includes VXI compatible ID and Device Type Registers Details are shown in Table 4 2 Table 4 2 M MA Module EEPROM IDENT Words 0 4 534 Notes 1 The Revision Number is the functional revision level of the module It does not necessarily correspond to the hardware assembly level 2 The Module Characteristics bit definitions are Bit s Description 15 0 no burst access 14 13 unused 12 1 needs 12V 11 1 needs 5V 10 1 trigger outputs 9 1 trigger inputs 8 7 00 no requestor 6 5 11 interrupt type C 4 3 01 16 bit data 2 1 00 8 bit address 0 no memory access 3 The VXI Device Type word contains the following information Bits Description 15 12 256 bytes of required memory 11 0 FDEie Astronics Test Systems specified VXI model code for M212 Astronics Test Syste
56. PPS output and indicates when a valid 1PPS or 100PPS output signal is available PPSACT Status is directly is available through an M module register and an interrupt can be generated on any change Astronics Test Systems Publication 980900 Rev 3352 User Manual Front Panel The es four 68 pin front panel connectors labeled J200 and J203 See Figure 7 2 for front panel connector locations Connectors Table 7 1 shows the signal assignments to connector pins _ 68 34 1 35 o a 4 25 25 EM a a eus us s qs 4200 4201 os e s 4 5 4275 47 ao eis e 5 4 gt 3 e v 4 o 35 1 68 _ 68 34 13 J202 J203 99999999999 9999 pb m to e Figure 7 2 1714 Front Panel Connectors Astronics Test Systems M1721 7 5 3352 User Manual M1721 7 6 Publication No 980900 Rev B Table 7 1 M1714 Front Panel Pin outs
57. Receiver M module interface allows complete communication with M12 e Active monitoring of PPS output indicates when a valid 1PPS output signal is available e PPS output control always off always on on when certain conditions met e Antenna bias power is switch selectable for 3V or 5V operation e External power pass through for integration with other M modules 12 channel parallel receiver design tracks up to 12 satellites Oncore 12 simultaneously Specific Features e Code plus carrier tracking carrier aided tracking e Position filtering e Antenna current sense circuitry e 3 dimensional positioning within 25 meters SEP with Selective Availability SA disabled e Extensive control and status e Satellite tracking e PPS output control Astronics Test Systems M213 3 1 3352 User Manual Specifications MAXIMUM RATINGS Publication No 980900 Rev B e Latitude and longitude e Height e Time e Selectable 1 or 100PPS output Autonomous Integrity Monitoring algorithm for checking timing solution integrity e Automatic site survey M213 3 2 Parameter Condition Rating Units Operating Temperature 0 to 50 C Non Operating 40 to 70 C Temperature Humidity non condensing 5 to 95 Power Consumption 45V 0 mA 12 or EXTPWR DE mA 12V 0 mA Input Voltage EXTPWR 40 V Supply Current EXTPWR Pass Through 2 0 A Astr
58. Systems Assigned M MA Location Logical Location Enabled Address A Yes 64 B Yes 72 C Yes 80 D No unassigned E No unassigned F Yes 104 Publication 980900 Rev Address Space Selection M MA Module Enable Software Configuration Required Memory Setting 3352 User Manual A single switch is provided that selects either A16 A24 or A16 A32 addressing for the entire carrier This switch is located in position 8 of the logical address switch The UP OPEN position of this switch corresponds to A16 A24 and the DOWN position to A16 A32 Six switches are provided to enable the individual M MA locations Each switch represents an M MA location and must be enabled before the carrier will recognize a module as present These switches are positions 1 6 of the M MA switch and correspond to M MA locations A F respectively With the switch in the UP OPEN position the M MA in that location is disabled Conversely with the switch is in the DOWN position the M MA in that location is enabled Switch positions 7 amp 8 are reserved for test purposes and must be in the DOWN position for normal operation The amount of memory space allocated for a module by the system resource manager or control module is specified in the Required Memory field of the Device Type register 0x04 The default Required Memory setting is the minimum amount allowed by the address space selected A24 addressing allows a minimum
59. TRG INA INB TRG IMP LEVEL INA IMP INB IMP LEVEL HLZ DEF HI Z DEF gt Ws Mec M MODUE A ECLOUT1 5 LEVEL INASRC INB SRC E INT ECLOUT2 ECL2 PRG EXT EXT c mE LJ COMPONENT SIDE VIEW Figure 6 2 M210 Hardware Configuration Switches Astronics Test Systems M210 6 7 3352 User Manual INA IMP Switch INB IMP Switch TRG IMP Switch INA SRC Switch INB SRC Switch INA LEVEL Switch INB LEVEL Switch TRG LEVEL Switch ECL1 Switch ECL2 Switch OUT CFG Switch M210 6 8 Publication No 980900 Rev B This switch selects the input impedance of the input A signal to be 500 or high impedance 10 This switch selects the input impedance of the input B signal to be 500 or high impedance 10 This switch selects the input impedance of the trigger input signal to be 500 or high impedance 10 This switch selects whether the INA signal come from the internal M module trigger input or from the external front panel connector This switch selects whether the INB signal come from the internal M module trigger input or from the external front panel connector This switch selects whether the input A threshold levels are software programmable or set to the fixed factory default levels of high 2 15V low 1 85V no programming required This switch selects whether the input B threshold levels are software programmable o
60. TS UE 4 6 ent 4 7 47 M Module 4 7 OPPO 4 7 Microcontroller aed onus 4 7 Rubidium ee P er 4 8 ont decis iae du 4 8 Iriput Output Signal 4 10 EXTPW 4 10 eg du DE M 4 10 SS dc on M EL 4 10 4 10 TPPSORBT a trinus ada 4 10 Cr 4 10 da c odd Mode te 4 10 Identification and Configuration 4 11 e tats 4 11 M Module Identification fe epe tee Bake 4 13 DSTA ON D pts Lem Red t LESE 4 14 iv Astronics Test Systems Publication 980900 Rev 3352 User Manual PV OG EATING dace A e es ree see 4 14
61. The source to the input comparators can also be either disconnected or connected to the comparators inputs via isolation relays using the Control Register 0 For the TTL Inputs Digital Bus Receivers provide high speed buffering with fixed TTL threshold levels The Digital Receivers provide a fixed hysteresis window for the input signal As an input signal transitions from low to high it must exceed the TTL threshold level plus the hysteresis range to produce a high at the receiver output As an input signal transitions from high to low it must fall below the TTL threshold level minus the Hysteresis range to produce a low at the receiver output The threshold levels are fixed TTL levels and can not be changed The Input impedance of the TTL Inputs is 50 Ohms For the Differential Inputs Differential Receivers provide high speed buffering with fixed threshold levels The Differential Receivers provide a fixed hysteresis range for the input signal As an input signal transitions from low to high on the plus input it must exceed the minus input level plus the hysteresis range to produce a high at the receiver output As an input signal transitions from high to low on the plus input it must fall below the minus input level minus 1 2 the Hysteresis range to produce a low at the receiver output The outputs of the Differential Receivers are routed to high speed comparators which are used to the low signal level
62. a pied ER irs 7 5 Figure 7 3 Command Register Assignment for the 1714 7 12 Figure 7 4 BIST Status Register Bit Assignment for the 1714 7 13 Figure 7 5 Direction Control for Octets 18 7 13 Figure 7 6 Direction Control for Octets 9 16 22 tr ne ie re ERR Dr 7 14 Figure 8 1 Functional Block DISSE ATE 8 5 Figure P1 Pin 1 Figure A 2 Config N 2 Figure B 1 M213 Front Panel 1 Figure 2 M213 Interface Connector Configuration esee B 2 Figure C 1 M212 Front Panel Signals aire Ine teer tente Ee SER Pe Rn C 1 Figure C 2 M212 M MA Interface Connector Configuration C 2 Figure E 1 M210 Front Panel eoi ot ntn E 1 Figure E 2 M210 M ModuleInterfabe uo aro ne aerae nti ester t pitt o a E 2 Figure F 1 M1721 Front Panel Connectors F 1 Figure F 2 M1721 M Module Interface oen reet anas F 2 Astronics Test Systems xi 3352 User Manual Publication No 980900 Rev B List of Table
63. able 02 disable Default disable ADIR Trigger direction for Trig A 0 input VXI to M Module 1 output M Module to Default input AINV gt Trig A invert bit 1 invert logical level of input or output trigger A Default 0 non inverting Trig TTL Sel gt Trigger A Mapping to VXI TTL Trigger lines 0 7 Default 0 BEN gt Trigger enable for Trig B 1 enable 02 disable Default disable BDIR gt Trigger direction for Trig B 0 input VXI to M Module 1 output M Module to Default input BINV gt Trig B invert bit 1 invert logical level of input or output trigger B Default 0 non inverting Trig B TTL Sel gt Trigger B Mapping to VXI TTL Trigger lines 0 7 Default 0 Figure 2 7 Special Function Registers VX405 2 16 Astronics Test Systems Publication 980900 Rev Operating Instructions General Hardware Configuration 3352 User Manual The VX405C 3352 is configured through a series of hardware switches and software controlled registers as below The switches enable the M MA slots and configure the logical addresses of the M MAs The VX405C has software controlled registers for each module These registers provide configuration of interrupts triggers A24 A32 addressing and required memory All other controls are dependent on a specific M MA and reside that module in I O and memory space CAUTION All hardware configurations
64. ach switch corresponds to an location and must be enabled before the carrier will recognize an M MA present The following is the switch settings for each of the 3352 configurations SW2 1 thru 6 A B C D E F FOR P N 407919 06 EN EN EN 016 FOR P N 407919 001 DIS DIS DIS EN DIS FOR P N 407919 002 DIS EN DIS FOR P N 407919 003 EN DIS DIS EN DIS FOR P N 407919 004 EN DIS EN DIS Astronics Test Systems Publication 980900 Rev 3352 User Manual 1 i _ e 3 9 MODULE D gt MODULE C if MODULEE MODULEF db LOGICAL ADDRESS Modulo Select Up 1 Down 8 ENABLE DISABLE Address Space Select amp Diac il TE 1 2345918 not Used DISABLE ENABLE 412345678 Figure 2 4 VX405C Hardware Configurable Controls Astronics Test Systems VX405 2 9 3352 User Manual Publication No 980900 Rev B Eight LED indicators are provided on the front panel Their functions are FAIL This front panel LED indicates the PASS SYSFAIL status The LED illuminates during reset initialization or if there is a failure on the VX405C Carrier itself
65. addr unsigned short value for 1 7 1 gt 0 1 1 1 4 read eebit addr amp rdval temp temp rdval amp 0x01 lt lt i int read eebit unsigned short addr unsigned short value write word addr 0x4 lower clock bit Delay 000005 write word addr 0x6 raise clock bit Delay 000005 read word addr value NOTE 1 write word and read word are low level memory access routines 2 NOT actual code and should be treated as a modeling tool only Figure 3 5 ID PROM Access Routine Astronics Test Systems M213 3 11 3352 User Manual Publication No 980900 Rev B This page was left intentionally blank M213 3 12 Astronics Test Systems Publication 980900 Rev General Description Astronics Test Systems 3352 User Manual Chapter 4 M212 The M212 provides a precision Rubidium oscillator in a double wide M Module format adhering to the ANSI VITA 12 1996 specification for M Modules see exception below A 1 pps output is an integral part of the design An optional 1 pps input allows the unit to track a GPS or other external reference and display the difference between the input and the 1 pps generated by the Rubidium module X72 The M212 may be installed on any carrier board supporting the M Module specification Carriers are available that allow the M212 to be used in VXI VME PCI cPCI PXI and many other system architectures Note Due to
66. as shown in Figure 2 3 A16 ADDRESS A24 A32 ADDRESS 15 REGISTERS ID STAT CNTL CONTROL REGISTERS INTERRUPT TRIGGER UNUSED BASE ADDRESS A24 VXI OFFSET VXI ADDR 15 BASE ADDRESS 00 0000 02 04 06 UNUSED HALF OF VXI REQ D MEM SETTING M MA MEMORY BASE ADDRESS A32 OFFSET 0 0 0 VXI REQUIRED MEM SETTING Notes 1 Referto Device register 02 for details on Req d Memory Setting 2 AAA bit of the VXI STAT CNTL register must set to 1 to access memory or I O space 3 Byte Addressing is referenced above Astronics Test Systems Figure 2 3 Memory Organization VX405 2 7 3352 User Manual Triggers Interrupts Hardware Configuration Logical Address Modulo Select Address Space M MA Module Enable VX405 2 8 Publication No 980900 Rev B Each M MA is allowed two trigger lines TRIGA and TRIGB Triggers may be input or output The VX405C Carrier provides software programmable connection to any VXI TTL Trigger line SYNC Protocol Each M MA trigger can be enabled logically inverted configured as input or output and mapped to any of the eight VXI TTL Trigger lines Each M MA can support one interrupt request as specified in the ANSI VITA 12 1996 Specification Each interrupt can be programmed to
67. ation converted to X72 coding before being sent to the X72 Table 4 4 Floating Point Number Representation for DSIP Floating Point Format Single Precision 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 7 5 4 E1 M22 M21 M20 M19 M18 M17 M16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M15 M14 M12 M11 M10 9 M8 7 6 MS 4 M3 M2 Single precision floating point format is 32 bit format consisting of a 1 bit sign field an 8 bit exponent field and a 23 bit mantissa field The fields are defined as follows Sign S 0 positive values 1 negative value Exponent lt E7 E0 gt offset binary format 00 special cases i e zero 01 exponent value 127 126 FE exponent value 127 127 FF special cases not implemented Mantissa 22 fractional magnitude format with implied 1 1 22 21 1 0 Range 1 9999998 127 to 1 0000000 126 1 0000000 126 10 1 9999998 127 where represents 2 to power of M212 4 22 Astronics Test Systems Publication 980900 Rev 3352 User Manual Table 4 5 X72 Run Mode Commands USER OUTPUT TO X72 RESPONSE TO NAME amp DESCRIPTION OF COMMAND HOST Command Data a Set FC mode To be Specified Set Analog Frequency Control Mode This command toggles the analog input pi
68. ational Standards Institute and VMEbus International Trade Association 7825 E Gelding Dr Suite 104 Scottsdale AZ 85260 3415 http www vita com Astronics Test Systems Publication 980900 Rev Functional Description Overview Mating J202 AMPMODU 1 487937 6 AMPMODU 1 104069 1 4201 x t amp 5 2 1761607 9 26 pin Tyco 200 3M 9810 PLMO 2 1761607 3 10 pin Tyco Astronics Test Systems 3352 User Manual The M1721 uses comparators differential receivers and TTL receivers to buffer the input signals Each input signal is buffered and distributed to either TTL or ECL outputs The standard multiplexer configurations are shown below but the module can be configured to handle various custom multiplexing and distribution requirements A simplified block diagram is shown in Figure 1 1 LS GATEWAY TRG1 GATEWAY TRG1 TRG2 TRG2 gt 9 STA SYSTRG A lt SYSTRG A lt SYSTRG 4 SYSTRG B RH SLOT 0 TRIG IN lt E RFSG1 ATRI lt RFSG3 4 EI R RFSG2 4 7_ TRIG IN 4 1 i 11 SLOT 0 TRIG IN 2A1 4 213 SLOT 0 TRIG IN 143 lt 17 svs TRG1 3 svs TRG2 zz NAT _ ni L 25RFsG2 PULSE SYNC OUT 25RFSG3 PULSE SYNC OUT Z RFSG2 PTRI lt H h 11 a St 9 EI RFSG3 PTRI lt 1 ex
69. cial Function FIBSOISIBI 2 15 Interrupt Control Registers cce pepe 2 15 Trigger Control 2 15 2 17 Cg cM 2 17 Hardware Pu Pen ab ec b eR pe cents 2 17 Logical Address Selection aig oto dae tetendit ee a ee dus tige im 2 17 Address Space Selection foes cise ant daca e t a acti utc 2 19 MMA Mod le Ertable ie bre ie te adu ee ore nce 2 19 Software GorfiguratlOn i eer re Pre rE 2 19 Required er 2 19 rr 2 20 2 21 Module Identification UR I bk 2 21 Built in Test and p een 2 22 Trouble cee audet onc lame 2 22 Astronics Test Systems Publication 980900 Rev 3352 User Manual scu P C 3 1 es sah etos s tl pst 3 1 General Pise gerer P 3 1 P rpose of EQUIDITeriL 3 1 Spe ifications of EquipIient
70. de edite e ae pe Rae 7 12 Status Register 04h os scorso it 7 13 Direction Control Tor Octets 1 8 DATI 7 13 Direction Control for Octets 9 16 OC hyundai isto 7 14 Master Write Strobe for Stimulus Data 0 7 14 Master Read Strobe for Response Data 7 14 Octet Stimulus Response Data Register 10h 2 7 14 Astronics Test Systems vii 3352 User Manual Publication No 980900 Rev B Chapter ble 8 1 cedet ed Lt E t MALE Uta 8 1 General Descriptio N end ute edo ss 8 1 Purpose or Equiprtfierit oae Siete etr oe eee ripae ode babel aunt 8 1 Specifications of ei eere er 8 1 Key Features ox 8 1 ru tle ad rd 8 2 Muere ccm 8 4 BUS compliant e 8 4 Applicable Documents es scat sath ER 8 4 Functional Descriptio 8 5 8 5 M Module Interfaces 8 6 a e LC 8 6 UM 8 6 Differential Inputs 2
71. distributed to 8 outputs on a high density 15 pin D Sub connector The 10 MHz sine wave signal is distributed to two SMB connectors on the front panel The module can be monitored through the register based interface The M module interface is compliant with ANSI VITA standard 12 1996 Figure 5 1 M1708 Front panel Astronics Test Systems 1708 5 1 3352 User Manual Publication No 980900 Rev B Figure 5 2 M1708 PWA component side 10 MHz Sinewave Input 10 MHz TTL Input Manufacturer use only Interfacing to the M1708 Accessing the Module 1708 5 2 Astronics Test Systems Publication 980900 Rev B 3352 User Manual Tepon This module supports the M Module serial EEPROM identification EEPROM function at 0 80 Identification Word Description Value hex 0 Sync Code 5346 1 Module Number 06AC 2 Revision Number 0000 3 Module Characteristics 1800 4 7 Reserved 0000 8 M Module Specific 5757 9 M Module Specific 572 10 Specific 5459 11 M Module Specific 4D49 12 M Module Specific 4 47 13 M Module Specific 2E43 14 M Module Specific 4F4D 15 M Module Specific 2020 16 VXI Sync Code ACBA 17 RACAL INSRUMENTS OFFB VXI Code 18 VXI Device F6AC 19 31 Reserved 0000 32 63 M Module Specific not used Notes 1 The Revision Number is the functional revision level of the module does not necessarily correspond to the hardware assembly level 2 The Module Charac
72. double wide M Module modules The nominal dimensions are 5 687 144 5 mm long x 4 183 106 2 mm wide The module complies with the ANSI VITA 12 1996 Specification for double wide M Modules and the MA Module trigger signal extension The module also supports the optional IDENT and VXI IDENT functions Module Type MA Module Addressing A08 Data D8 Interrupts INTA amp INTC DMA not supported Triggers not supported Identification IDENT and VXIHDENT Manufacturer ID 0004 6 212 VXI Model Code OFDE M212 ANSI VITA 12 1996 Standard for The Mezzanine Concept M Module Specification Approved May 20 1997 American National Standards Institute and VMEbus International Trade Association 7825 E Gelding Dr Suite 104 Scottsdale AZ 85260 3415 http www vita com X72 Precision Rubidium Oscillator Designers Reference Symmetricom formerly Datum Document Number C O 106031H Remove the 3352 module and inspect it for damage If any damage is apparent inform the carrier immediately Retain shipping carton and packing material for the carrier s inspection 2 Verify that the pieces in the package you received contain the correct 3352 module option and the 3352 Users Manual Notify Customer Support if the module appears damaged in any way Do not attempt to install a damaged module into a VXI chassis 3 The 3352 module is shipped in an anti static bag to prevent electro
73. dule are in conformance with ANSI VITA 12 1996 for double wide M Module modules The nominal dimensions are 5 687 144 5 mm long x 2 082 52 9 mm wide The module complies with the ANSI VITA 12 1996 Specification for double wide M Modules and the MA Module trigger signal extension The module also supports the optional IDENT and VXI IDENT functions Module Type MA Module Addressing A08 Data D16 Interrupts not supported DMA not supported Triggers not supported Identification IDENT and VXIHDENT Manufacturer ID 0002 6 210 dec ANSI VITA 12 1996 Standard for The Mezzanine Concept Module Specification Approved May 20 1997 American National Standards Institute and VMEbus International Trade Association 7825 E Gelding Dr Suite 104 Scottsdale AZ 85260 3415 http www vita com Astronics Test Systems Publication 980900 Rev 3352 User Manual Functional Description Overview The M210 uses high speed comparator and ECL logic to provide low propagation delay signal distribution of two input signals Each input signal is buffered and distributed to TTL and ECL outputs A TRGIN function provides limited distribution for a third input The module can be configured to handle a variety of input signals A simplified block diagram is shown in Figure 6 1 INA w TTLOUT2 aite DRIVERS W TTLOUT3 nh L W TTLOUT4
74. e 6 4 Table 6 1 Address Map Command Summary IO REG REGISTER DESCRIPTION HEX 77 TragerThreshokiLevel Conti Astronics Test Systems M210 6 11 3352 User Manual Publication No 980900 Rev B M210 Configuration Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write ei TRGO 5 Read TRGO SRCB SRCA Input A Source 00 Front Panel 01 A 10 M Trigger B 11 notused SRCB Input B Source 00 Front Panel 01 M TriggerA 10 M Trigger B 11 notused TRGO Input Trigger Output 00 none internal SMA connectors only M Trigger A M Trigger B Both M Trigger A amp B Note The INA SRCA and or INB SRC switches must be configured to INT to use the M Triggers as inputs Input A Threshold Level Control Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write a J T FS DIA Read T J DIA SELA gt Select Input A Threshold Level potentiometer 1 active 0 inactive DIA gt Data input signal to Input A Threshold Level potentiometer CLKA gt Clock signal to Input A Threshold Level potentiometer Notes 1 These bits directly control the 3 wire serial interface to the potentiometer See Chapter 6 section Programming Threshold Levels for programming details A programmed value 0046 5 0V 5 0V The resolution is 39mV per bit 2 The INA LEVEL switch must be set to PRG for the programmed t
75. edance 49 50 51 Q Threshold Level 1 25 1 60 V Hysteresis 160 mV Frequency 2V p p Input Level 0 100 Width 2V p p Input Level 5 ns TTL Output Characteristics Impedance 18 75 Output Levels Load 500 VoL 0 5 IV 3 0 V Propagation Delay ANALOG to TTLOUT 16 21 ns DIFF to TTLOUT 38 48 ns TTLIN to TTLOUT 10 15 ns ECL Output Characteristics Type 10K Series Differential ECL Termination 4990 pull downs 5 2V on both lines Propagation Delay TTLIN to ECLOUT 7 12 ns Rise Fall Time Terminated 75 O to 2V 1 0 ns Notes 1 Includes Hysteresis 2 Four output drivers with 750 source impedance each are used in parallel Astronics Test Systems M1721 8 3 3352 User Manual Mechanical Bus compliance Applicable Documents M1721 8 4 Publication No 980900 Rev B The mechanical dimensions of the module are in conformance with ANSI VITA 12 1996 for double wide M Module modules The nominal dimensions are 5 687 144 5 mm long x 2 082 52 9 mm wide The module complies with the ANSI VITA 12 1996 Specification for double wide M Modules and the MA Module trigger signal extension Module Type MA Module Addressing A08 Data D16 Interrupts not supported DMA not supported Triggers not supported Identification FRAM access Manufacturer ID 0002 6 210 dec ANSI VITA 12 1996 Standard for The Mezzanine Concept Module Specification Approved May 20 1997 American N
76. efore writing a 1 to the CLKx bit The bits are written by sequentially writing to the control registers according to Figure 6 5 Channel Input Programming Bits are written in this direction Bit 0 is first bit written Bit 16 is last bit written 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X MSB Input X Low Threshold Level LSB MSB Input X High Threshold Level LSB X gt Don t Care Trigger Input Programming Bits are written in this direction Bit O is first bit written Bit 16 is last bit written 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X X X X X X X X X MSB Trigger Input Threshold Level LSB X gt Don t Care NON Figure 6 5 Potentiometer Serial Programming Astronics Test Systems M210 6 15 3352 User Manual Publication No 980900 Rev B ID PROM Refer to Chapter 4 section M Module Identification PROM for a description of the ID PROM s function and contents Reading data from the ID PROM involves writing and reading a register in a sequential manner Data cannot be written to the PROM Figure 6 6 provides a general description of the code sequence necessary to read the information from the PROM The PROM is compatible with a standard IC 9603 type PROM For specific timing information refer to the 9603 or compatible PROM data s
77. el This MMCX connector is the 10MHz sine wave output from the Rubidium oscillator This MMCX connector is the 10MHz square wave output from the Rubidium oscillator 3 3 ACMOS logic level Astronics Test Systems Publication 980900 Rev 3352 User Manual Identification and Configuration Registers There are variety of registers used to configure and control the Registers M212 module These registers are located in the lOSpace The address map of the registers is shown in Table 4 1 Details of the registers are provided in Figure 4 6 Table 4 1 I O Address Map Command Summary M212 IO REG HEX REGISTER DESCRIPTION Control Status Interrupt Control UART Data Registers Astronics Test Systems M212 4 11 3352 User Manual Publication No 980900 Rev B M212 Control Status Reg 00 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Wie Service 0 normal operation 1 indicates that the Rubidium unit is nearing limits of frequency control and that service is required within several months LOK Locked 0 not locked 1 indicates that the output frequency is locked to the atomic resonance of rubidium Note The SRV bit is only valid when LOK 1 M212 Reg 02 Interrupt Control Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write mT SIEN LIEN Read IT I
78. ential input negative signals The outputs of these signals can be routed up to five of the TTL Outputs SLOTO 1A1 RFSG 1 3 ATRG HPSA These J201 signal contacts are 50 Ohm TTL Inputs These signals can be routed to either the RGSG2 PTRIG and RFSG3 PTRIG Outputs These J201 signal contacts are 50 Ohm TTL Inputs These signals can be routed to the RFSG 1 3 JATRG HPSA TTL outputs and are also routed to the STA SYSTRG A B ECL Outputs and Slot0 2A1 and Slot0 1A3 TTL outputs These J201 signal contacts are the TTL Outputs These are designed to drive 50 Ohm loads These J200 signal contacts are the TTL Outputs These are designed to drive 50 Ohm loads These J200 signal contacts are the 50 Ohm Analog Inputs These signals can be routed to the RGSG2 PTRIG and RFSG3 PTRIG Outputs These J200 J202 signal contacts are the common Ground reference for all Input and Output signals Astronics Test Systems Publication 980900 Rev 3352 User Manual Identification and Configuration Registers There are a variety of registers used to configure and control the M1721 module These registers are located in the Space The address map of the registers is shown in Table 1 1 Details of the registers are provided in Figure 1 3 Registers Table 8 1 Address Map Command Summary IO REG REGISTER DESCRIPTION HEX 00 1F Board ID Information Card Revision Code MUX Control DAC Control Status Signals Astronics T
79. er facts of information on the X72 r i X 72 by Symmetricom Inc Copyright 2004 SDCP Version 5 02 of 4 2004 Loader Version 2 Mode 1 Flag 0005 Unit serial code is 0009AB0018 h current tuning state is 6 Crystal 3938700hz ACMOS 989680 00000000hz Sine 989680 00000000hz Ctl Reg 0204 Res temp off BFC53F7D lamp temp off c003B7E9 FC enabled Srvc low Astronics Test Systems M212 4 15 3352 User Manual Publication No 980900 Rev B The following print out is an example of entering the letter h to get the help menu from the X72 H V Set FC Mode Setting the Lock Pin Functionality Adjust DDS Frequency delta e 11 Info show program info Display lpps Delta Reg Set lpps TIC Set Service Pin Sense Set ACMOS Output Frequency N Display Control Reg Set Control Reg Dave Tuning Data Display Health Data Exit Run Mode Setting the Damping Factor and Tau Coefficients X 9 OF FU FH H V M212 4 16 Astronics Test Systems Publication 980900 Rev 3352 User Manual The following print out shows the response to the command for w for X72 Health Data wellness r gt w AData SCont 6012 SerNum 18C PwrHrs 18A PwrTicks 11A6848 LHHrs 17E LHTicks 83DBDO RHHrs 17E RHTicks 83D2E3 dMP17 41883621 dMP5 40A158E9 HtrVolt RVthermC d dLVthermC d d d MVoutC 4 dTempLo
80. er than 12V To maintain GPS tracking when the M module interface is not powered an external power supply must be provided To support integration with other M modules an external power pass through connector is provided that simply passes the external supply voltage through if it exists The physical layout of the module is shown in Figure 3 2 A notch in the PCB is provided for the external power pass through and the internal PPS output to allow cable access when the module is installed A switch is provided to set the antenna bias voltage to either or 5V EXTPWR LED PPSOUT PPSACT LED EXT POWER PASS THROUGH 12 MIFE TIMING RECEIVER LOGIC UC UART ANT PWR INTERNAL I3 5V 213 3 6 Figure 3 2 M213 Physical Layout Astronics Test Systems Publication 980900 Rev 3352 User Manual Input Output Signals ANT EXTPWR PPSACT 2 5 Astronics Test Systems The front panel input output signals are as shown in Figure 3 3 and are briefly described below The connector shield of each of the connector is tied to chassis ground This MMCX connector provides the PPS output signal from the timing receiver The signal is buffered through 500 clock distribution driver Under software control of the timing receiver the output may be always ON alway
81. es eight Square Wave copies of the 10 MHz TTL input labeled PPS Following is the pin out for this connector Pin 1 Out1 Pin 2 Out2 Pin 3 Out3 Pin 4 Out4 Pin 5 Out5 Pin 6 Gnd Pin 7 Gnd Pin 8 Gnd Pin 9 Gnd Pin 10 Gnd Pin 11 Out6 Pin 12 Out7 Pin 13 Out8 Pin 14 Gnd Pin 15 Gnd Two front panel SMB female connectors supply copies of the 10 MHz sine wave input Astronics Test Systems M1708 Connectors D 1 3352 User Manual Publication No 980900 Rev B Connector JA1 provides the connections for all signals between the 1708 M Module and the host M Module carrier board The following signals are connected and used Pin Signal Pin Signal JA1 A1 Chip select JA1 B1 GND JA1 A8 Addr7 JA1 B2 VCC JA1 A18 DTACK JA1 B3 12V JA1 A20 RESET JA1 B4 12V JA1 B8 GND JA1 B9 000 1 10 001 JA1 B11 002 1 12 003 1 13 004 1 14 005 1 15 006 1 16 007 1 17 DSO JA1 B18 ANRITE JA1 B20 SYSCLOCK Figure D 1 M1708 Connecto M1708 Connectors D 2 Astronics Test Systems Publication 980900 Rev 3352 User Manual Appendix E M210 CONNECTORS 1 ECLOUT1 2 ECLOUT1 6 ECLOUT1G 3 GND 4 ECLOUT2 5 ECLOUT2 9 ECLOUT2G 00000000 amp Figure E 1 M210 Front Panel Connector Astronics Test Systems M210 Connectors E 1 3352 User Manual Publication No 980900 Rev B Rows ES Sud
82. est Systems M1721 8 9 3352 User Manual Publication No 980900 Rev B pe FW Revision Register 20 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write T ee ze p 5E Read CPLD FPGA FPGA gt FPGA Logic FW Revision CPLD gt CPLD Logic FW Revision M1721 MUX Control Register RFSG2 PTRIG RFSG3 HPSA TRIG ATRG RFSG2 5 PTRIG ATRG RSVD Reserved for Future Use MOD 2 enable 0 disable MOD TRG 1 EN gt T enable 0 disable SLOT 0 1A1 0 GATEWAY1 47 GATEWAY2 RFSG3 PTRIG 00 PULSE SYNC 2 01 PULSE SYNC 3 10 MODTRG1 11 MODTRG2 RFSG2 PTRIG 00 PULSE SYNC 2 01 PULSE SYNC 3 10 MODTRG1 11 MODTRG2 HPSA TRIG gt 00 GATEWAY1 01 GATEWAY2 10 SYSTRG1 11 SYSTRG2 RFSG3 ATRG 00 GATEWAY1 01 GATEWAY 1925 SYSTRG1 11 SYSTRG2 RFSG2 ATRG gt 00 GATEWAY1 01 GATEWAY2 10 SYSTRG1 41 SYSTRG2 RFSG1 ATRG gt 00 GATEWAY1 01 GATEWAY2 10 SYSTRG1 11 SYSTRG2 5 3 Default Value at Reset is 0 Figure 8 2 M1721 Registers M1721 8 10 Astronics Test Systems Publication 980900 Rev 3352 User Manual pen DAC Control Register 24 Bit 7 6 ADDRESS ADDRESS
83. et Octet Octet Octet 8 7 6 5 4 3 2 1 Astronics Test Systems M1721 7 13 3352 User Manual Direction Control for Octets 9 16 Publication No 980900 Rev B This is a read write register that controls the direction of the corresponding byte octet All eight channels within the octet will have the same direction Writing a 1 to this register will set the appropriate octet to an output stimulus A 0 value will set the octet to an input response This register is set to O after reset Figure 7 6 describes this register Figure 7 6 Direction Control for Octets 9 16 Direction Control Reg for Octets 1 8 Bit 7 Bit 0 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Octet Octet Octet Octet Octet Octet Octet Octet 16 15 14 13 12 11 10 9 Master Write Strobe write to this address location causes a master write strobe to occur master write strobe loads the data in each octet stimulus for Stimulus Data holding register into the main output registers This allows all 128 0 channels to change at once Only octets have been previously defined as outputs get written into the main output registers The master write strobe is prohibited for main output registers whose octets have been programmed as inputs Before a master write is issued the octet stimulus holding registers that are defined as outputs need to be loaded with the data
84. finitions 7 12 Table 7 5 BIST Status Register Bit 7 13 Table 8 1 I O Address Map Command 8 9 Table 8 2 M Module FRAM 5 1 0 8 12 Tabl8 8 5 Connectors ein av 8 12 xii Astronics Test Systems Publication No 980900 Rev B 3352 User Manual DOCUMENT CHANGE HISTORY Revision Date Description of Change 02 04 09 Revised per EO 29550 Revised format to current standards Company name revised throughout manual Manual now revision letter controlled Added Document Change History Page xv 04 11 11 Revised per EO 30439 Revised Document to include assembly option 407919 004 Added information pertaining to M1721 module Astronics Test Systems xiii 3352 User Manual Publication No 980900 Rev B This page was left intentionally blank xiv Astronics Test Systems Publication 980900 Rev General Description Product Configuration 3352 User Manual Chapter 1 INTRODUCTION The 3352 is single slot C size VXI module that provides a GPS disciplined 10MHz Rubidium frequency standard The module provides two 1V rms sinewave and eight TTL level outputs The GPS timing receiver is capable of tracking up to
85. g Heat seal or tape the bag to insure a moisture proof closure When sealing the bag keep trapped air volume to a minimum The shipping container should be a rigid box of sufficient size and strength to protect the equipment from damage If the module was received separately and not part of a system then the original module shipping container and packing material may be re used if itis stillin good condition M212 4 6 Astronics Test Systems Publication 980900 Rev 3352 User Manual Functional Description Overview The M212 utilizes control logic to interface the M Module bus to the Rubidium oscillator The Rubidium oscillator is controlled internally through a serial interface A simplified block diagram is shown in Figure 4 2 FRONT ft EXTPWR BEN LOCK ED SERVICE po SINE OUT M MODULE CONTRO RUBIDIUM SQU OUT INTERFACE PART OSCILLATOR 2 aper 1PPS IN Figure 4 2 M212 Functional Block Diagram M Module Interface Control Logic Microcontroller UART Astronics Test Systems The M Module Interface allows communication between the M212 and the carrier module The interface is an asynchronous 16 bit data bus with interrupt and trigger capabilities The interface adheres to the ANSI VITA 12 1996 Standard for The Mezzanine Concept M Module Specification for MA modules The control logic provides the electrical interface between the M module bu
86. ground If the instrument fails to operate satisfactorily shows visible damage has been stored under unfavorable conditions has sustained stress Do not operate until performance is checked by qualified personnel CE Declaration of Conformity Astronics Test Systems 4 Goodyear Irvine CA 92618 declare under sole responsibility that the 3352 GPS VXI RUBIDIUM P N 407919 001 002 conforms to the following Product Specifications EMC EN61326 1998 1 1998 2 2001 FCC CFR 47 PART 18 SUBPART B CLASS A ICES 003 ISSUE 4 February 2004 CLASS A Supplementary Information The above specifications are met when the product is installed in an Astronics Test Systems certified mainframe with faceplates installed over all unused slots as applicable The product herewith complies with the requirements of the Low Voltage Directive 73 23 EEC and the EMC Directive 89 336 EEC modified by 93 68 EEC Irvine CA April 13 2005 VP of Engineering Karen Evensen This page was left intentionally blank Publication 980900 Rev 3352 User Manual Table of Contents Chapter RUN 1 1 INTRO DUCTION 2 1 1 Descriptio eM e 1 1 1 1 1 1 1 1
87. gured to provide a hysteresis window for the input signal As an input signal transitions from low to high it must exceed the high threshold level to produce a high at the window comparator output As an input signal transitions from high to low it must fall below the low threshold level to produce a low at the window comparator output The comparator threshold levels can be either programmable or set to a factory default value A hardware configuration switch provides this selection The programmable threshold levels are set by programming a group of digitally programmable potentiometers These potentiometers are non volatile so they retain their setting even when power to the module is off The source of the input comparators is switch selectable as either the front panel input connectors or the internal M module trigger lines Input impedance is also switch selectable as either 50 Ohms or HI Z Eight TTL outputs provide TTL compatible signal distribution of the input signals Each input can be distributed to four TTL outputs or the module can be configured to distribute a single input to all eight TTL outputs Each TTL output consists of four output buffers in parallel The output source impedance of each individual driver is 500 thus providing an overall output source impedance of 12 50 that can drive TTL compatible logic levels into a 500 load Two ECL outputs provide ECL compatible signal distribution of the inputs The source INA
88. h memory space A24 or A32 is assigned to the module by reading the ID Logical Address register of the VXI module It then reads the first 16 bit word the A24 or A32 memory checks that the value at this location is 1721 hex This is used to ensure that the module being controlled is M1721 module All of the other functions in the driver access the registers in the A24 or A32 memory space to control the module M1721 8 13 3352 User Manual Publication No 980900 Rev B This page was left intentionally blank M1721 8 14 Astronics Test Systems VX405C P1 P2 CONNECTORS BGOIN BGOOUT BGSOUT SYSRESET LWORD AM5 A23 IACKIN IACKOUT 4 07 06 Figure 1 P1 Pin Configuration Astronics Test Systems VX405C P1 amp P2 Connectors 1 3352 User Manual GND TTLTRG1 TTLTRG3 GND TTLTRG5 TTLTRG7 Publication No 980900 Rev B GND TTLTRGO TTLTRG2 5V TTLTRG4 TTLTRG6 GND MODID Figure A 2 P2 Pin Configuration VX405C P1 8 P2 Connectors 2 Astronics Test Systems Publication 980900 Rev 3352 User Manual Appendix B M213 CONNECTORS PIN 1 EXTPWR PIN 7 GND PIN 9 PPSACT Figure B 1 M213 Front Panel I O Signals Astronics Test Systems M213 Connectors B 1 3352 User Manual EUM CS A01 A02 EN A03 15 04 6 A5 EA A06 Av 9 008
89. he electrical interface between the M module bus and the module The control registers are contained within this logic The control logic also monitors the PPS output and indicates when a valid 1PPS or 100PPS output signal is available PPSACT Status is directly is available through an M module register and an interrupt can be generated on any change The microcontroller UART provides the communication to and from the 12 Timing module internal FIFO facilitates the software communication M213 3 5 3352 User Manual Oncore 12 Timing Receiver Power Conversion and Distribution Physical Layout Publication No 980900 Rev B The 12 is GPS Timing Receiver module from Motorola The M12 internally provides extensive control and status of the GPS timing receiver including antenna connection feedback satellite tracking status output quality indication 1PPS output control and a host of other position almanac and timing status and control functions Detail information on this module can be found in the applicable documents shown in Chapter 3 Applicable Documents The main power for the module is obtained from either the M module interface 12 or from an external supply through the front panel connector Power is converted to appropriate levels and distributed to the individual components on the M213 The module uses the 12V supply from the M module interface unless an external supply is provided that is great
90. heet M210 6 16 Astronics Test Systems Publication 980900 Rev 3352 User Manual int read idword unsigned short id addr unsigned short value addr OxFE id addr 0x80 id write prbyte addr id addr read prbyte addr amp rdval tmpval rdval 8 read prbyte addr amp rdval tmpval tmpval rdval value tmpval write word addr 0x0000 M MA address for IDPROM 80 is the read opcode for the PROM returns first byte of IDPROM upper byte of sync code word returns first byte of IDPROM combine bytes of sync code lower cs int write prbyte unsigned long addr unsigned short value write word addr 0x0000 write word addr 0x0004 write_prbit addr 0x0001 temp value for 1 0 1 lt 7 1 4 write_prbit addr temp 8 0 80 gt gt 7 temp temp lt lt 1 insure cs is initially low initialize start bit int write_prbit unsigned long addr unsigned short value temp 0x0004 value amp 0x0001 write word addr temp Delay 000005 temp 0x0006 value amp 0x0001 write word addr temp Delay 000005 set data bit before clock data bit clock int read prbyte unsigned short addr unsigned short value for i 7 i 0 i i 1 read prbit addr amp rdval temp temp rdval amp 0x01 lt lt i value temp int read prbit u
91. hreshold to take affect Input Threshold Level Control eg 04 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write Read SELBY CLKB SELB Select Input Threshold Level potentiometer 1 active 0 inactive DIB Data input signal to Input B Threshold Level potentiometer CLKB Clock signal to Input B Threshold Level potentiometer Notes 1 These bits directly control the 3 wire serial interface to the potentiometer Chapter 6 section Programming Threshold Levels for programming details A programmed value 0046 5 0V 5 0 The resolution is 39mV per bit 2 The INB LEVEL switch must be set to PRG for the programmed threshold to take affect Figure 6 4 M210 I O Registers M210 6 12 Astronics Test Systems Publication 980900 Rev 3352 User Manual Trigger Threshold Level Control Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write To fsetf f DT eLkKT Read SET YT SELT Select Trigger Threshold Level potentiometer 1 active 0 inactive DIT gt Data input signal to Trigger Threshold Level potentiometer Clock signal to Trigger Threshold Level potentiometer Notes 1 These bits directly control the 3 wire serial interface to the potentiometer Chapter 6 section Programming Threshold Levels for programming details A programmed value 0046 5 0V and 5 0 The
92. i ada ee oon A 1 Append CL 1 CONNECTORS B 1 C oda uH bien dde uus C 1 M212 CONNECTORS uunc oci otc us C 1 A aa D 1 M1708 CONNECTORS D 1 E 1 M210 CONNECTORS E 1 a aa eer F 1 1 Astronics Test Systems ix 3352 User Manual Publication No 980900 Rev B List of Figures Figure 2 1 3352 Configuration 2 4 Figure 2 2 VX405C Functional Block 2 6 Figure 2 3 Memory Organization 2 7 Figure 2 4 VX405C Hardware Configurable Controls 2 9 Figure 2 5 Front Panel s a II util ic ati cec 2 11 Figure 2 6 VXI ConfiguratiorHHeglsters dodo o etre eror innate En uaque 2 14 Figure 2 7 Special Function Registers 2 16 Figure 3 1 Functional Block Dia rain bre 3 5 Figure 3 2 M213 Physical Layout s oos ete adus 3 6 Figure 3 3 M213 Frorit pendisse Fr o a PAS Dd Kus 3 7 Figure 3 4 M213 VO Registers ooo
93. iei te iet ven cest esie tu ua 3 1 Module Key dte na attuli 3 1 Oncore M12 Specific Features sni e de i e ann er ED eee 3 1 NN Rc PC cR 3 2 c 3 4 EUS ompliarib ir ues 3 4 Applicable ded setae teats 3 4 Functional DescripliOr sse ore teure Fo 3 5 OVGIVIOW iue e e BM tus 3 5 M Module e sip noe pee pa e ae o a Sese lena 3 5 MONON Bero sc EET 3 5 Microcontroller Pate terio eb dede 3 5 Oncore M12 Timing Re66lVver uu petiere 3 6 Power Conversion and tan penes e ttn uS pnt ee ax tente ates 3 6 Physical m 3 6 TPE OUTPUT SIGN AS a e ou 3 7 Et 3 7 ANI Iu DIM M E M M ME 3 7 EXIPWR 3 7 3 7 CIND a at E 3 7 Identification Conf
94. iguration Registers 00000000 3 8 ON Il T 3 8 M Module Identification P ROM eios luit 3 9 md 3 10 Rubidium Oscillator Communication 3 10 Interrupts i acre ameti e i LUE 3 10 EE 3 10 Astronics Test Systems 3352 User Manual Publication No 980900 Rev B Chapter MR ee 4 1 IM irc cR edo M ALIM A t p 4 1 General Descriptio N ensi cime 4 1 Purpose or Equiprtfierit o oerte etr efe eee ipai te ode tab el aunt Ioue peat 4 2 Specifications of ei erre e Ha ene Ru 4 2 C 4 2 POPS CRG AOS inc ss cats Sak 4 3 Mechanical o CN 4 5 BUS Compliance I 4 5 Applicable Documents et M onal 4 5 4 5 Unpacking eels 4 5 Handling Precautions 4 6 Installation of M MA IVIDOUles 2 ques 4 6 Preparation for RSS FIS
95. isabling of outputs immediately follows the command example Displays Health Monitor data Astronics Test Systems M212 4 23 3352 User Manual Publication No 980900 Rev B NOTE To save changes to default settings for next power up Enter t command followed by 5987717 to save The output control status register OSR bit structure control features and controlling factors are defined as shown below Table 4 6 X72 Output Control Status Register Structure Bit 4 Control Description Controller 0 Lamp Switch Power 0 Lamp Switch off Controlled by firmware Automated Boost RT Function 1 Lamp Switch is on internal unit function 1 BIST Output 0 Unit is locked Controlled by firmware Automated Function 1 Unit is not locked 2 FXO Enable 0 Enable FXO output Default is set at Factory 1 Disable FXO output 3 1PPS Output Enable 0 Enables 1PPS Output Default is set to 1pps enabled at 1 Disables 1PPS Output Factory Configuration 4 ACMOS Output Enable 0 Enable Output Default is set to ACMOS enabled at 1 Disables Output Factory Configuration 5 C field Boost 0 Low C field Controlled by firmware Automated 1 High C field 6 SINE Output Enable 0 Enables Output to Default is set to sine output enabled at Factory Configuration SINE PSEUD enable will not p
96. ivity and BIST Fail front panel indicators e Built in Self Test BIST RT gt Digital 5V Bus Specifications Min Max Vin V 2 0 5 5 0 5 0 8 2 4 0 45 Channel To Channel skew 20 ns Max across all 128 pins Astronics Test Systems M1721 7 1 3352 User Manual Mechanical Bus Compliance M1721 7 2 Drivers Receivers resistor Shock Vibration Temperature Relative Humidity Altitude MTBF Dimensions Publication No 980900 Rev B 74 244 with a 22 ohm series with 10K pull up connected to 5V 74ACT373 with 820 ohm series 15g 11 ms sine wave 0 33 mm P P 5 55 Hz Operating 0 C to 55 Non operating 40 to 75 8596 non condensing at lt 30 Operating 10 000 feet Non operating 15 000 feet 765 387 hours MIL HDBK 217E double wide M Module 4 183 X 5 837 The mechanical dimensions of the module are in conformance with ANSI VITA 12 1996 for double wide M Module modules The nominal dimensions are 5 837 X 4 183 The module complies with the ANSI VITA 12 1996 Specification for M Modules Module Type Addressing A08 Data D8 Interrupts not supported DMA not supported Triggers not supported Identification not supported Model Number 9C h Revision Number 01 h Astronics Test Systems Publication No 980900 Rev Applicable Documents Ordering Information FUNCTIONAL DES
97. l 000 0000 0000 ion level of the module It does not necessarily 2 The Module Characteristics bit definitions are Bits Description 15 0 no burst access 14 13 unused 12 1 module needs 12V 11 0 module does not need 5V 10 0 trigger outputs not supported 9 0 trigger inputs not supported 8 7 00 requestor 6 5 11 interrupt type C 4 3 01 16 2 1 00 8 bit address bus 0 0 no memory access 3 The VXI Device Type word contains the following information Bit s Description 15 12 Fig 256 bytes of required memory 11 0 Astronics Test Systems Astronics Test Systems specified VXI model code for M213 M213 3 9 3352 User Manual Publication No 980900 Rev B i The M213 is a register based instrument that is controlled through Operation a series of I O registers The exact method of accessing and addressing the I O registers is dependent on the M Module carrier used to interface the module to your data acquisition or test system Rubidium Oscillator The UART Data Register is used to communicate with the 12 Timing Receiver module Data written to the register is serially Communication transmitted to the 12 Serial data received from the M12 is converted into 8 bit data bytes and stored in a FIFO to be read by the user The FIFO can store approximately 512 bytes See Chapter 5 COMMANDS in the Motorola 12 GPS Positioning And Timing Recei
98. ll value resistor i e 75 Ohms to 2 Volts for optimum performance M1721 8 7 3352 User Manual INPUT OUTPUT Signals STA SYSTRG and STA SYSTRG STA SYSTRG A and STA SYSTRGB GATEWAYTRG1 and GATEWAYTRG2 GATEWAYTRG1 and GATEWAYTR2 RFSG2 PULSE and RFSG3 PULSE SYSTRG1 and SYSTRG2 RFSGxATRIG and HPSA and SLOTO RFSG2 PTRIG and RFSG3 PTRIG MODTRG1 and MODTRG2 GROUND M1721 8 8 Publication No 980900 Rev B The front panel input output signals are as shown in Appendix F in Figure F 1 and are briefly described below Right Angle Latched Box Headers are used for the MODTRG 1 2 RFSG 2 3 PTRG RFSG 1 3 ATRG HPSA TRG SLOTOTRG SYSTRG 1 2 and RFSG 2 3 PLS signals and a 15 pin HD DSUB plug provides connection to the GATEWAY 1 2 and STA SYSTRG A B signals In addition to the front panel connectors 2 optional connectors are provided on the internal side of the PCB for the SYSTRG1 and SYSTRG 2 signal inputs These connectors facilitate integration with other internal M modules Cable access is provided through a notch on one side the board These J202 signal contacts are the ECL output positive signals These J202 signal contacts are the ECL output negative signals These J202 signal contacts are the Differential input positive signals The outputs of these signals can be routed up to five of the TTL Outputs SLOTO 1A1 RFSG 1 3 ATRG HPSA These J202 signal contacts are the Differ
99. ms M212 4 13 3352 User Manual Operation Programming Writing Registers Rubidium Oscillator Communication Data Format Run Mode Data Format Customer Mode Publication No 980900 Rev B The 212 is a register based instrument that is controlled through a series of I O registers The exact method of accessing and addressing the registers is dependent the M Module carrier used to interface the module to your data acquisition or test system Refer to the carrier s documentation for information on the address mapping of an M Module s I O registers and to your system software documentation for details on data access A high level driver may also be available for control Normal 16 bit wide register values can be written in one write operation using 16 bit register access However some pulse parameters such as the pulse period pulse width and pulse delay require more than 16 bits Special attention must be given when programming these values To prevent a pulse parameter from changing until the entire value is written the order of the write operations is important The internal logic is configured to only accept the change when the high order bits are written Therefore the application software must write the low bits first then the middle bits and lastly the high bits The UART Data Register is used to communicate with the Rubidium oscillator Data written to the register is serially transmitted to the X72
100. n to 51 2 Ornon the unit Freq between enable and disable cr In Factory mode the default is enabled During factory test the default is set to disable for shipping unless the customer ordered the default to be set enabled f Desired frequency change To be Specified Adjust Frequency from free running center Adjust Unit output frequency Used to discipline the unit The smallest incremental frequency in parts to 11 frequency change is 2E 12 or 4 2 Any Example for a 100E 11 value less than this will still be used No illegal change 100 lt cr gt Example values Unit always powers up at free running for a 100E 11 change factory set frequency This command is 100 lt cr gt always relative to the free running frequency h None To be Specified HELP command Displays menu i None To be Specified Outputs Unit information While dumping data Clock outputs are not guaranteed to meet specifications during the use of this command o N example of command and To be Specified Loads the value of N to set the ACMOS data to give 10MHz for a output frequency VCXO of 60MHz is 03 N is 1 to 65536 Output FACMOS is equal to crystal frequency divided by 2N For values outside range unit sends an illegal notice E uses the previous valid setting p None To be Specified Displays Control Register q Hex data to set or reset bits To be Specified Set Control Register in the Control Register Allows enabling or d
101. ndition Rating Units Operating Temperature 0 to 50 Non Operating 40 to 70 Temperature Humidity non condensing 5 to 95 96 Power Consumption 45V 100 mA 12 0 12 0 10 25 17 W Astronics Test Systems M212 4 3 3352 User Manual AC CHARACTERISTICS Publication No 980900 Rev B Dynamic Performance Sine wave Output Frequency 10 MHz Power Into 500 7 8 10 dBm Phase Noise 1Hz offset 72 10Hz offset 90 100Hz offset 128 dBc Hz 1KHz offset 140 10KHz offset 148 Spurious Harmonic 60 dBc max Non harmonic 60 dBc max Stability Allan 1 second 3x10 sec max vaanga t 10 seconds 1x10 sec max t 100 seconds 3x 10 Initial Accuracy 25 5 10 2 Frequency Drift 25 5 107 on off on 24 hr 48 hr 12 hr 2x 10 Hz 25 Control Range 1 x 10 Hz Granularity 1 1072 Hz Warm up Time Time to lock 5 x 10 4 minutes Time to lt 1 x 10 7 5 minutes Square wave Output Level ACMOS 5 V typ Jitter RMS 10 ps max MTBF Ground benign 600 000 hrs M212 4 4 Astronics Test Systems Publication 980900 Rev Mechanical Bus Compliance Applicable Documents Installation Unpacking and Inspection 3352 User Manual The mechanical dimensions of the module are in conformance with ANSI VITA 12 1996 for
102. neral description of the code sequence necessary to read the information from the PROM The standard IC 9603 type PROM For specific timing information refer to the 9603 or compatible PROM data sheet M213 3 10 Astronics Test Systems Publication 980900 Rev 3352 User Manual int read idword unsigned short id addr unsigned short value addr OxFE M MA address for IDPROM id addr 0x80 id 80 is the read opcode for the PROM write eebyte addr id addr read eebyte addr amp rdval returns first byte of IDPROM tmpval rdval lt lt 8 upper byte of sync code word read eebyte addr amp rdval returns first byte of IDPROM tmpval tmpval rdval combine bytes of sync code value tmpval write word addr lower cs int write eebyte unsigned long addr unsigned short value write word addr 0x0000 insure cs is initially low write word addr 0x0004 initialize write eebit addr 0x0001 start bit temp value for 1 0 1 lt 7 1 4 write eebit addr temp 5 0 80 7 temp temp lt lt 1 int write eebit unsigned long addr unsigned short value temp 0x0004 value amp 0x0001 set data bit before clock write word addr temp Delay 000005 temp 0x0006 value amp 0x0001 set data bit amp clock write word addr temp Delay 000005 int read eebyte unsigned short
103. nsigned short addr unsigned short value write word addr 0x4 Delay 000005 write word addr 0x6 Delay 000005 read word addr value NOTE 1 lower clock bit raise clock bit write word and read word are low level memory access routines 2 gt actual code and should be treated as a modeling tool only Figure 6 6 ID PROM Access Routine Astronics Test Systems M210 6 17 3352 User Manual Publication No 980900 Rev B This page was left intentionally blank M210 6 18 Astronics Test Systems Publication 980900 Rev 3352 User Manual Chapter 7 M1714 GENERAL The M1714 provides 128 channels of digital I O double wide M Module format adhering to the ANSI VITA 12 1996 specification DESCRIPTION for M Modules This M Module resides in a VX405C carrier for installation into chassis Specifications of Use the original packing material when returning the 3352 to Astronics Test Systems for calibration or servicing The original Equipment shipping container and associated packaging material will provide the necessary protection for safe reshipment If the original packing material is unavailable contact Customer Support for information 128channels broken up into 16 groups of 8 bits each e Directional Programming each group 8 bits can be programmed as either an input or output Four 68 pin VHDCI front panel connectors Power Act
104. nterrupt Type 0 Type A software end of interrupt default 1 Type C hardware end of interrupt gt Service Interrupt Pending 1 a Service interrupt is pending write 1 to this bit to clear LOKI Lock Interrupt Pending 1 a Lock interrupt is pending write a 1 to this bit to clear URTI UART Interrupt Pending 1 UART interrupt is pending write a 1 to this bit to clear MIEN Master Interrupt Enable 0 disabled default 1 enable Service Interrupt Enable 0 disabled default 1 enabled gt Lock Interrupt Enable 0 disabled default 1 enabled UART Interrupt Enable 0 disabled default 1 enabled Note When using Type C interrupts IT 1 the interrupt pending bits 7 0 are presented as the interrupt vector during the interrupt acknowledge cycle The MIEN bit is also cleared and must be re enabled during the interrupt service routine SRVI and LOKI interrupts occur on any change if enabled URTI interrupts only occur when it becomes active M212 04 UART Data Register Bt 15 14 13 240 9 8 7 6 5 4 3 2 1 0 Write Read Note A write to Data transmits the byte to the X72 oscillator A read of Data receives one byte of data from the X72 receive FIFO A Special Character OxFF indicates that the FIFO is empty Figure 4 6 M212 I O Registers M212 4 12 Astronics Test Systems Publication 980900 Rev 3352 User Manual
105. of connector Table 7 2 contains manufacture s part numbers for the cable connector assemblies used by the M1714 Table 7 2 Mating Connectors Manufacture 68 Pin Mating Cable DDK Cable DFG HA2 XXX Assembly Molex 73796 3005 Connector Molex Cable 92904 0001 Assembly Note XXX represents length of cable The M1714 is a register based module that is controlled through a series of I O registers The exact method of accessing and addressing the I O registers is dependent on the M Module carrier There are a variety of registers used to configure and control the M1714 module These registers are located in the I O addressing space The address map of the registers is shown in Table 7 3 Details of the registers are provided in the register definition section Astronics Test Systems Publication 980900 Rev 3352 User Manual Table 7 3 M1714 Register Address Offset Assignments Address Offset Hex 00 02 04 06 08 0A 0C 10 12 14 16 18 1 1 1 20 22 24 26 28 2 2 2 Astronics Test Systems Write BIST Command Register Reserved Reserved Direction Control Reg for Octets 1 8 Direction Control Reg for Octets 9 16 Master Write Strobe for Stimulus Data Octet 1 Stimulus Data Register Octet 2 Stimulus Data Register Octet 3 Stimulus Data Register Octet 4 Stimulus Data Register Octet 5 Stimulus Data Register Octet 6 Stimulus Data Register Octet 7 Stimulus
106. of 512 bytes and A32 addressing allows a minimum of 64Kbytes NOTE In order to access the M MA Module IO Space and memory the AAA bit in the VXI Status Control register 0x04 must be set high This is usually done by the resource manager after allocating memory Astronics Test Systems For M Modules that have only IO Space 256 bytes the default Required Memory setting is sufficient and no changes to this field are required VX405 2 19 3352 User Manual Publication No 980900 Rev B For MA Modules that have on board memory the Required Memory field must be changed to cause the resource manager to allocate enough memory space for the IO Space and memory contained on the MA Module Since the VX405C maps a MA Module s IO Space into the lowers 256 bytes of the allocated memory space and the MA Module s memory into the upper half of the allocated memory space the VXI Required Memory must be set to twice the MA Modules required memory For example if an MA Module has 512Kbytes of on board memory then 1Mbyte of VXI memory space must be allocated The modules 256 bytes of Space is mapped starting at the Offset 0x000000 A24 and the 512Kbytes of memory begins at the Offset 0x080000 A24 Proper settings are given in the table provided under the VXI Device Type register description in Figure 2 6 To change the Require Memory field simply write the new value to Device Type register The Model Code bits are
107. og input signals are passed through high speed comparators that convert the analog level to a digital signal The input differential signals are routed to differential receivers that convert the differential inputs to single ended digital signals The TTL inputs are buffered and provide buffered digital signals These digital signals are then routed via the internal digital multiplexers to the TTL and ECL outputs The module is physically implemented on a double wide M Module adhering to the ANSI VITA 12 1996 specification for M Modules The M1721 can be used in a wide variety of applications including functional verification of digital systems signal simulation design verification and research and development that require the distribution of clock and timing signals e Eight Input Channels 2 Analog 2 Differential 4 Digital e Digital Inputs 100MHz Maximum Frequency e Differential and Analog Inputs 50MHz Maximum Frequency e Eleven Output Channels 2 Diff ECL outputs 9 TTL outputs e Trigger levels individually software programmable for each Analog input Analog Inputs can support up to 2 TTL outputs e Differential Inputs can support up to 5 TTL outputs Two Digital TTL Inputs can support up to 2 TTL outputs Two Digital TTL Inputs can support up to 4 TTL outputs and 2 Differential ECL Outputs e Custom Trigger Distribution Configurations are easily configured through on board FPGA M1721 8 1 3352 User Manual Publication
108. ompt press the y key then the 1 key then press Enter the 1 indicates that you wish to input the Damping Factor Input a value between 0 25 and 4 and then press Enter At the gt prompt press the y key then press the 2 key then press Enter the 2 indicates that you wish to input the Time Constant Input a value between 5 and 100 000 and then press Enter At the gt prompt press the 2 key This saves the 1PPS configuration data to non volatile memory the coefficients are not saved with the z command the X72 will revert to the previously saved configuration upon restart The X72 will respond with the following output gt 7 Saving Tdata 2 serial number 1 5 Coefs saved M212 4 19 3352 User Manual The Coefficients Factory Default The j Command Publication No 980900 Rev B If the factory default values of Damping Factor 1 Tau 400 are acceptable for your application no modifications to the y coefficients are required The X72 1PPS disciplining is enabled at the factory allowing the unit to work right out of the box If the user wishes to return the y coefficients to the factory defaults enter the value 0 for both the Damping Factor and Tau in the process described above This will cause the X72 to operate at the factory default Damping Factor of 1 and Tau of 400 The j key can be pressed at any time to return the current value in hex format from the
109. on needed VXI Configuration to configure a VXlbus system The configuration information Registers includes manufacturer identification product model code device type memory requirements device status and device control The registers are briefly described below and are detailed in Figure 2 6 VXI Identification ID Base 0046 This read only register provides the manufacturer Register identification device classification i e register based and the addressing mode i e A32 VXI Device Type Register Base 0216 This read write register provides the model code see note identifier and allows the user to set the M MA s required memory NOTE The manufacturer and model code identification depends on the installed M MA Module s support of the VXI extension to the optional M Module IDENT function For modules that support the VXI IDENT extension non standard the manufacturer and model code of the M MA Module is reported and the required memory is automatically set according to the M MA Module requirements For all other modules amp Technologies 116 is reported as the manufacturer and the VX405C 216 as the model code Additionally the user may have to set the required memory Refer to M MA Module Identification for details on the VXI INDENT Extension VX405 2 12 Astronics Test Systems Publication 980900 Rev 3352 User Manual VXI Status Control Base 0416 A read of this register pr
110. onics Test Systems Publication 980900 Rev AC CHARACTERISTICS 3352 User Manual Parameter Conditions Specification Units GPS Timing General Characteristics Receiver 12 channels Tracking capability simultaneous vehicles 12 satellites Operating Frequency L1 1575 42 MHz GPS Timing Performance Characteristics Acquisition Time Time Hot almanac position time 25 sec to First Fix TTFF ephemeris 50 sec Warm almanac position time lt 200 sec Cold no stored information lt 1 sec Internal Reacquisition after blockage Positioning accuracy selective availability disabled lt 25 meters SEP Timing accuracy using clock granularity message 1s average lt 2 ns 6s average lt 6 ns without clock granularity message lt 10 ns 1s average lt 20 ns 6s average Antenna requirements Active antenna module with external gain 18 36 dBm Required gain 5 V Bias Power 80 ma max Current draw PPS Output Electrical Characteristics Front panel and internal connector Output Level High into 500 load 2 0 V min Low into 500 load 0 4 V max Output Impedance 50 3 Q Output Source Sink 50 mA Current Propagation delay from M12 output 3 5 min 9 0 max ns Skew front panel output to internal 300 ps max connector output common edge variation Rise Fall Time from 0 8V to 2 0V 2 0V to 0 8V 1 5 ns max PPSACT Output
111. or INB of the ECL signals can be selected for each ECL output The differential ECL outputs are terminated through 4990 resistors to 5 2V Astronics Test Systems Publication 980900 Rev 3352 User Manual Trigger Input Comparator and The TRGIN function provides limited distribution for a third input The TRGIN signal is distributed to two TRGOUT connectors internal PCB mounted and can programmatically be distributed to the M Module Distribution trigger lines The input comparator logic is similar to the standard inputs however a hysteresis window in not provided Instead a single threshold level can be programmed or set to a factory default level as selected by a hardware configuration switch Hardware The M210 contains a variety switches that select the various Configuration configurations of the module including input impedance of the inputs the output configuration of the inputs the threshold levels of inputs and the source of the inputs The switches are only accessible with the module removed from the carrier and are located as shown in Figure 6 2 TTLOUT1 TTLOUT2 TTLOUT3 TTLOUT4 TTLOUTS TTLOUT6 TTLOUT7 TTLOUT8 c L TRGOUT2 ccc C INA NB INB
112. ource must be enabled SIEN LIEN or UIEN and the master interrupt enable MIEN must be enabled in the Interrupt Control Register For Type C interrupts the interrupt vector is equal to the lower byte of the interrupt control register NOTE When using Type C interrupts the MIEN bit is cleared during the interrupt acknowledge cycle must be re enabled to receive another interrupt ID PPROM Astronics Test Systems The ID PROM is a serial device and accessing it involves writing and reading a register in a sequential manner to acquire data Figure 4 7 provides a general description of the code sequence necessary to read the information from the PROM The PROM is a standard IC 9603 type PROM For specific timing information refer to the 9603 or compatible PROM data sheet M212 4 25 3352 User Manual Publication No 980900 Rev B int read idword unsigned short id addr unsigned short value addr OxFE M MA address for IDPROM id addr 0x80 80 is the read opcode for the PROM write eebyte addr id addr read eebyte addr amp rdval returns first byte of IDPROM tmpval rdval lt lt 8 upper byte of sync code word read eebyte addr amp rdval returns first byte of IDPROM tmpval tmpval rdval combine bytes of sync code Ay value tmpval write word addr 0x0000 lower cs int write eebyte unsigned long addr unsigned short value write word addr 0x0000
113. outputs 9 1 trigger inputs 8 7 00 no DMA requestor 6 5 11 interrupt type C 4 3 01 16 bit data 2 1 00 8 bit address 0 0 55 3 The VXI Device Type word contains the following information Bits Description 15 12 256 bytes of required memory 11 0 116 Astronics Test Systems specified VXI model code for M210 M210 6 14 Astronics Test Systems Publication 980900 Rev 3352 User Manual 1 The 210 is a register based instrument that is controlled Operation through the I O registers The module can also be operated without any software control if the default input levels are acceptable see Chapter 6 section Hardware Configuration for switch details The exact method of accessing and addressing the I O registers is dependent on the M Module carrier used to interface the module to your data acquisition or test system Refer to the carriers documentation for information on the address mapping of an M Module s registers and to your system software documentation for details on data access Programming to the Input Threshold Level Control registers Reg 00 and 02 Threshold Levels A programmed value 0046 5 0V and FFig 5 0V The resolution is 39mV per bit The CLKx and bits directly control the serial bus signals connected to the digital potentiometer The SELx bit must be set to 1 atleast one write cycle b
114. ovides the state of the P2 Register MODID line and the SYSFAIL inhibit ready and self test status write to this register allows disabling of the SYSFAIL function and individual reset of the associated M MA module VXI Offset Register Base 0616 This read write register controls the offset value for addressing the M MA I O space and memory The VXI system resource manager or control module sets this value according to the memory requirements specified for this module and the memory requirements of the other instruments in the system Astronics Test Systems 405 2 13 3352 User Manual Publication No 980900 Rev B 00 VXI ID Bt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read Device Address Only Class Space Manufacturer ID Device Class Device Class 11 Register Based Address Space Address Space 00 A16 A24 01 16 32 10 reserved 11 A16 Only Manuf ID Manufacturer Identification see text for details 02 VXI Device Type Bit 15 14 13 12 11 10 9 8 7 6 Witte Read Model Code Model Code Model code see text for details Required Memory Required memory value depends on memory required by M MA module and VXI address space setting see table below 5 4 3 2 1 0 Mem Rq d by A32 Address Space A24 Address Space M MA 0 bytes F 64K E 512 bytes 128 bytes 64K E 512 bytes 256 bytes F 64K E 512 bytes 512 bytes F 64k D 1k 1K F 64k C 2k 2K F 64k B 4k 4K F 64k A 8K 8K F 6
115. ows CVI and LabView The driver is provided with source code as well as help files to assist the developer with programming the module Various minimum system requirements must be met for use of the VXIplug amp play driver These minimum requirements are specified in the Plug and Play specification document VPP 2 general the minimum hardware requirements for the Windows framework are e Must 100 IBM PC compatible Introduction 1 2 Astronics Test Systems Publication 980900 Rev 3352 User Manual Must have an 80486 33 MHz or greater CPU with floating point Must have at least a 120 MB hard disk Must have a or higher compatible monitor Must have at least 8 RAM 16 MB recommended Must have a Windows compatible mouse Must have the capability to control a VXI system In addition the following are minimum software requirements must also be met Microsoft Windows 95 98 ME NT 2000 XP or higher VISA Library Version 2 0 of higher most recent version is recommended Minimum VXI Resource Manager software needed to configure VXI system To install the VXlp lug amp play driver run Setup exe from the installation disks or from the downloaded files Follow the instructions on the installation wizard to complete the installation The recommended installation directory is the system directory The driver files will be installed on your system as follows
116. r set to the fixed factory default levels of high 2 15V low 1 85V no programming required This switch selects whether the trigger input threshold level is software programmable or set to the fixed factory default level of 2 00 no programming required This switch selects whether the ECL1 signals are from INA or INB This switch selects whether the ECL2 signals are from INA or INB These switches configure the source of the TTL outputs and select the operational mode of the logic Astronics Test Systems Publication 980900 Rev 3352 User Manual OUT CFG Switch TTL Output 1 4 A Input A Drives Outputs OFF Normal Input B Drives Outputs OUT CFG Switch TTL Output 5 8 B Input B Drives Outputs OFF Normal Input A Drives Outputs OUT CFG Switch Operational Mode D Note Switch C is not used INPUT OUTPUT The front panel input output signals are as shown in Figure 5 1 Si gn als and are briefly described below jack receptacles are used for the TRG INB INA and TTLOUT signals and a 9 pin DSUB plug provides connection to the ECLOUT1 and ECLOUT 2 signals In addition to the front panel connectors MMCX connectors are provided on the internal side of the PCB for the INA INB TRG TRGOUT1 TRGOUT2 signals These connectors facilitate integration with other M modules Cable access is provided through a notch on one side the board See Figure 6 3 ECLOUT1 and These signal contacts are
117. rovide an output 1 Disables Output 7 SINE Output Level 0 Zero Level Controlled by firmware set at factory 1 Adds 30 of max Output 8 SINE Output Level 0 Zero Level Controlled by firmware set at factory Agusta 1 Adds 20 of max Output 9 SINE Output Level 0 Zero Level Controlled by firmware set at factory Adust 1 Adds 10 of max Output 10 SERVICE 0 Unit is OK Controlled by firmware Automated Function 1 Unit requires Service 11 15 Reserved Not Used When altering the Control Register these bits are masked out by firmware the Host will consider these bits as DON T CARE M212 4 24 Astronics Test Systems Publication 980900 Rev Interrupts 3352 User Manual The M212 supports Type A and Type C interrupts as specified in the M module specification A Type A interrupt releases the interrupt request only after the pending interrupt is cleared by software software end of interrupt interrupt releases the interrupt request during the interrupt acknowledge cycle hardware end of interrupt with vector i e ROAK Type C interrupts provide an interrupt vector during an interrupt acknowledge cycle Use the IT bit in the Interrupt Control Register to configure the desired type of interrupt NOTE For any interrupt to occur the MIEN bit in the Interrupt Control Register must be set to a one For an interrupt to occur the desired interrupt s
118. s Table 2 1 VXI Register Address 2 12 Table 2 2 Module EEPROM IDENT Wolds 2 22 Table 3 1 Address Map Command 3 8 Table 3 2 M Module EEPROM IDENT Wolds rn nena 3 9 Table 4 1 I O Address Map Command Summary 4 11 Table 4 2 Module EEPROM IDENT Wolds 4 13 Table 4 3 1PPS States Returned with the 4 20 Table 4 4 Floating Point Number Representation for DSIP 4 22 Table 4 5 X72 Run Mode 4 23 Table 4 6 X72 Output Control Status Register Structure 4 24 Table 6 1 I O Address Map Command 6 11 Table 6 2 M Module PROM IDENT 6 14 Table 7 1 M1714 Front Panel 6 2 2 7 6 Table 7 2 Mating Connectors 7 10 Table 7 3 M1714 Register Address Offset 7 11 Table 7 4 BIST Command Register Bit De
119. s OFF or only ON if certain conditions are met The LED indicates the ON OFF status of the signal The LED is visual indicator of the PPSACT signal see below 5V CMOS logic levels 500 output impedance This SMA jack is for the antenna input bias voltage may selected for 3V or 5V operation PPS Cx These two DSUB pins provide power to M213 to external power pass through connector PIN 1 EXTPWR Module power can provided PIN 5 GND through these front connectors or 2 through the M module 12V PIN 9 PPSAGT interface The EXTPWR LED d illuminates when external power above 8 to 10 volts is applied to the DSUB connector pins 70 to 30Vdc Figure 3 3 M213 Front Panel This DSUB pin indicates the status of the PPS output signal The signal is high when the PPS signal is active The PPS output from the GPS timing receiver is continuously monitored by the control logic If the PPS output does not pulse within 1 3 seconds the PPSACT signal will indicate inactive active high TTL output low output impedance These DSUB pins are the return paths for the EXTPWR and the PPSACT signals The pins are connected to the logic ground on the module M213 3 7 3352 User Manual Publication No 980900 Rev B Identification and Configuration Registers There are variety of registers used to configure and control the Registers M213 module These regis
120. s and the module The control registers are contained within this logic The microcontroller UART provides the communication to and from the Rubidium oscillator An internal FIFO facilitates the software communication 212 4 7 3352 User Manual Rubidium Oscillator Physical Layout 1PPS IN Oo Publication No 980900 Rev B The Rubidium oscillator is a X72 Precision Rubidium Oscillator from Symmetricom formerly Datum See the designers reference guide C O 106031H or latest for more information The physical layout of the module is shown in Figure 4 3 A notch in the PCB is provided for the EXTPWR connector to allow cable access when the module is installed The CPLD and MICRO connectors are for factory use only There are no configuration switches on the M212 Reference Figure 4 4 for Connector configuration ee EXTPWR CONNECTOR SYMMETRICOM X72 PRECISION RUBIDIUM OSCILLATOR M I F CONTROL LOGIC 5 uC UART 9 2 2 CPLD FOR FACTORY USE ONLY D M212 4 8 Figure 4 3 M212 Physical Layout Astronics Test Systems Publication 980900 Rev 3352 User Manual em mn KENNEN N Note Signals in parentheses are not used on this module Figure 4 4 M MA Interface Connector Configuration Astronics Test Sy
121. solution 8 bit 39 mV Threshold Level Input Impedance 500 7 150mV mV Input Impedance Hi Z 10 150mV mV Input Impedance 500 0 100 2 Input Impedance Hi Z 0 50 MHz Width 3 ns INA INB Input Characteristics High Threshold Level Software programmable 5 0 45 0 IV Range Low Threshold Level Software programmable 5 0 5 0 Range Fixed Factory Default High Level 2 15 V Levels Low Level 41 85 V Trigger Input Characteristics Input Threshold Software programmable 5 0 45 0 IV Fixed Factory Default 2 0 V Level TTL Output Characteristics Impedance 12 5 Output Levels Load 500 VoL 0 5 V Vou 3 0 V Propagation Delay INA or INB to TTLOUT 14 21 ns MTRIG to TTLOUT 24 30 ns ECL Output Characteristics Type 10K Series ECL Termination 4990 pull downs 5 2V both lines Propagation Delay INA or INB to ECLOUT 5 7 ns MTRIG to ECLOUT 14 21 ns Trigger Output Characteristics Impedance 50 Q Output Levels Load 500 VoL 0 4 V Vou 25 V Width 3 5 Propagation Delay TRIGIN to TRGOUT 14 21 ns Skew between TRGOUT1 and 1 0 ns TRGOUT2 Notes 1 The high level must be higher than the low level for proper operation 2 Four output drivers with 50Q source impedance each are used in parallel Astronics Test Systems M210 6 3 3352 User Manual Mechanical Bus compliance Applicable Documents M210 6 4 Publication No 980900 Rev B The mechanical dimensions of the mo
122. static damage to the module Do not remove the module from the anti static bag unless it is in a static controlled area Astronics Test Systems M212 4 5 3352 User Manual Publication No 980900 Rev B Handling The M212 contains components that are sensitive to electrostatic discharge When handling the module for any reason do so at a Precautions static controlled workstation whenever possible At a minimum avoid work areas that are potential static sources such as carpeted areas Avoid unnecessary contact with the components on the module All M Modules must be installed into the carrier before the carrier Installation of is installed into the host system To install a module firmly press Modules the connector on the M MA Module together with the connector on the carrier as shown in Figure 4 1 Secure the module through the holes in the bottom shield using the original screws CAUTION M MA Module connectors are NOT keyed Use extra caution to avoid misalignment Applying power to a misaligned module can damage the M MA Module and carrier M MA Module ABC Carrier Figure 4 1 M MODULE Installation Contact Customer Support for a Return Material Authorization Preparation for RMA number If the module is to be shipped separately it should Reshipment be enclosed in a suitable water and vapor proof anti static ba
123. stems M212 4 9 3352 User Manual Input Output Signals EXTPWR LOCK SERVICE 1 PPSIN 1PPSOUT SINEOUT SQUOUT M212 4 10 Publication No 980900 Rev B The front panel input output signals are as shown in Figure 4 5 and are briefly described below The connector shield of each of the connector is tied to chassis ground These two DSUB pins provide power to the Rubidium oscillator Power can either be provided through these front connectors or through the EXTPWR connector located on the PCB Power can be supplied to the Rubidium oscillator even when the M module is not powered 10 to 25Vdc This DSUB pin indicates the lock status of the Rubidium oscillator An LED also provided a direct visual indication of the lock status When illuminated it indicates that the LOCK signal is active active low TTL output This DSUB pin when active indicates that service on the Rubidium oscillator is required active low TTL output This MMCX connector is the 1PPS input signal to the Rubidium oscillator positive edge triggered ACMOS logic and 5V TTL logic compatible This MMCX connector is the 1PPS output signal from the Rubidium oscillator The output may be enabled disabled through the Rubidium communication interface 3 3 ACMOS logic level PIN 1 EXTPWR PIN 2 GND PIN4 GND O 1PPSIN 1PPSOUT SINEOUT LOCK SQUOUT M212 Figure 4 5 M212 Front Pan
124. t Specification Sinn E e 5 6 Physical SpecifIGatiOns 5 6 Chapter on ten 6 1 TE Piel 6 1 General Description a a 6 1 Purpose of 6 1 Specifications of Equipment 6 1 Key Feat reS n e E E 6 1 Specificato 6 2 Mechanical 6 4 Astronics Test Systems 3352 User Manual Publication No 980900 Rev B BUS OO IIIS mM D Me TEE 6 4 Applicable DOC VSS 6 4 Functional den decns 6 5 OVEIVIOW 6 5 TT 6 6 Comparators 6 6 QNID c E 6 6 z5 0p 6 6 Trigger Input Comparator and 6 7 Hardware ContIgurallOlr cedet aei add Ter 6 7 6 8 6 8 TRG IMP ub 6 8 INA SRC
125. tations from a competitive source or used for manufacture by anyone other than Astronics Test Systems The information herein has been developed at private expense and may only be used for operation and maintenance reference purposes or for purposes of engineering evaluation and incorporation into technical specifications and other documents which specify procurement of products from Astronics Test Systems TRADEMARKS AND SERVICE MARKS All trademarks and service marks used in this document are the property of their respective owners Racal Instruments Talon Instruments Trig Tek ActivATE Adapt A Switch N GEN and PAWS are trademarks of Astronics Test Systems in the United States DISCLAIMER Buyer acknowledges and agrees that it is responsible for the operation of the goods purchased and should ensure that they are used properly and in accordance with this document and any other instructions provided by Seller Astronics Test Systems products are not specifically designed manufactured or intended to be used as parts assemblies or components in planning construction maintenance or operation of a nuclear facility or in life support or safety critical applications in which the failure of the Astronics Test Systems product could create a situation where personal injury or death could occur Should Buyer purchase Astronics Test Systems product for such unintended application Buyer shall indemnify and hold Astronics Test Systems its officers
126. teristics bit definitions are Bits Description 15 0 no burst access 14 13 unused 12 1 module needs 12V 11 1 module needs 5V 10 0 trigger outputs not supported 9 0 trigger inputs not supported 8 7 00 no requestor 6 5 00 interrupter 4 3 00 8 data 2 1 00 8 55 0 0 55 3 The VXI Device word contains the following information Bit s Description 15 12 Fig 256 bytes of required memory 11 0 6ACis Astronics Test Systems specified VXI model code for 1708 Astronics Test Systems M1708 5 3 3352 User Manual Publication No 980900 Rev B Address Decoding Address A7 is the only decoded address bit Address 0x00 is reflected up to address Ox7f Address 0x80 is reflected up to address Oxff Address 0x00 reads the latched status of the 10MHz Square Wave TTL Outputs The latched outputs are cleared at the end of each read To obtain the current state of the output read the port to get any failures since the last read Read again to get any current failures Bits7 0 correspond to TTL outputs 8 1 where a 1 in a bit position indicates a failure and a indicates no failure Address 0x80 controls the serial EEPROM and contains the latched output status of the 10MHz sine wave The output status is reported as fault if the output level is less than approximately 2 dBm The latched outputs are cleared at the end of each read To obtain the
127. ters are located in the lOSpace address map of the registers is shown in Table 3 1 Details of the registers are provided in Figure 3 4 Table 3 1 Address Map Command Summary M213 IO REG HEX Mets Control Status eg 00 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write LE oosa series o Tsj S PPS gt PPS Active 0 PPS output is not active 1 PPS output is active M213 Interrupt Control Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write Nosed UIN Red 1 PPSI URT UIEN Interrupt Type 0 Type A software end of interrupt default 1 Type C hardware end of interrupt PPSI gt PPS Interrupt Pending 1 a PPS interrupt is pending write a 1 to this bit to clear URTI UART Interrupt Pending 1 UART interrupt is pending write a 1 to this bit to clear MIEN Master Interrupt Enable 0 disabled default 1 enable gt PPS Interrupt Enable 0 disabled default 1 enabled UART Interrupt Enable 0 disabled default 1 enabled Note When using Type C interrupts IT 1 the interrupt pending bits 7 0 are presented as the interrupt vector during the interrupt acknowledge cycle The MIEN bit is also cleared and must be re enabled during the interrupt service routine A PPSI interrupt occurs on any change if
128. that is to be written to the main output registers A read from this address location causes a master read strobe to occur A master read strobe loads the data from all 128 channels into each octet response holding register Data is written into the octet response holding register even if it has been previously defined as an output It is up to software to determine which octet has valid input data For octets that have been defined as outputs the octet response holding register contains the output data Master Read Strobe for Response Data OEh A write to this register loads the stimulus data into the octet stimulus holding register All octets that have been defined as outputs should have stimulus data loaded into their corresponding stimulus holding registers before a master write is performed A read from this register reads the response data that was captured into the corresponding octet response holding register by a master read strobe Octet Stimulus Response Data Register 10h 2Eh M1721 7 14 Astronics Test Systems Publication 980900 Rev B 3352 User Manual General Description Purpose of Equipment Specifications of Equipment Key Features Astronics Test Systems Chapter 8 M1721 The M1721 provides distribution of clock signals to other devices The module accepts two analog input signals two differential input signals and four TTL input signals and provides TTL and ECL distribution The anal
129. the physical height of the Rubidium oscillator the height on the back side of the module exceeds the allowable height specified in the M Module specification The height above the back of the PCB is approximately 0 25 inches The user must ensure that this height will not interfere with other installed modules or shield assemblies for the specific carrier that is being used 212 4 1 3352 User Manual Purpose of Equipment Specifications of Equipment Key Features M212 4 2 Publication No 980900 Rev B The M212 can be used in a wide variety of applications where a precision oscillator source is required e 10MHz frequency e Initial accuracy 5 x 107 9 25 e Frequency Drift Stability 5 x 107 per month without optional 1PPS disciplining e 1PPS input for long term stability with optional 1pps disciplining e 1PPS output ANSI Standard Double wide Full control of the Rubidium oscillator available Astronics Test Systems Publication 980900 Rev Specifications MAXIMUM RATINGS 3352 User Manual Query serial number operating hours operating temperature and event history Perform Self test Front panel service and lock signals Operates from 10 to 25V power source from the front panel or internal connector Front panel lock indicator indicates Rubidium lock or 1PPS input lock Sine wave and square wave output Parameter Co
130. ts 0001 0002 Power off Standard replaceable resetting fuses fuses Hold Trip Current Current Total Max Current 5 5A 10A 10A Total Max Current 12V 2 5A 5A Total Max Current 12V 2 5A 5A 45V 12 12V 24 24 Total Available from VXI Slot 7 2 1 0 1 0 1 0 1 0 Used by VX405C internal logic 1 2A 0A 0A 0A 0A 0001 fused level 5 0A 2 5A 2 5A 1A 1A 0002 fused level 5 0A 2 5A 2 5A 1A 1A 5V 12V 12V Allowed by specification per M Module 1A 0 2A 0 2A position 0001 fused level per position 1 25A 0 3A 0 3A 0002 fused level per position 2A 1A 1A The mechanical dimensions of the module in conformance Mechanical with the VXIbus specification Rev 1 4 for single slot C size modules The nominal dimensions are 233 35 mm 9 187 in high x 340 mm 13 386 in deep The environmental specifications of the module are Environmental Operating Temperature 0 to 55 Storage Temperature 40 C to 75 Humidity lt 95 without condensation Installed M MAs may differ in environmental specification Refer to each individual M MA s documentation for information VX405 2 2 Astronics Test Systems Publication 980900 Rev Bus Compliance Applicable Documents Installation Unpacking and Inspection Astronics Test Systems 3352 User Manual The module complies with the VXlbus Specification Revision 1 4 for C size register based modules and with VMEbus Specification ANSI
131. tteries damage from battery leakage or problems arising from normal wear such as mechanical relay life or failure to follow instructions This warranty is in lieu of all other warranties expressed or implied including any implied warranty of merchantability or fitness for a particular use The remedies provided herein are buyer s sole and exclusive remedies For the specific terms of your standard warranty contact Customer Support Please have the following information available to facilitate service 1 Product serial number 2 Product model number 3 Your company and contact information You may contact Customer Support by E Mail atshelpdesk astronics com Telephone 1 800 722 3262 USA Fax 1 949 859 7139 USA RETURN OF PRODUCT Authorization is required from Astronics Test Systems before you send us your product or sub assembly for service or calibration Call or contact Customer Support at 1 800 722 3262 or 1 949 859 8999 or via fax at 1 949 859 7139 We can also be reached at atshelodesk astronics com If the original packing material is unavailable ship the product or sub assembly in an ESD shielding bag and use appropriate packing materials to surround and protect the product PROPRIETARY NOTICE This document and the technical data herein disclosed are proprietary to Astronics Test Systems and shall not without express written permission of Astronics Test Systems be used in whole or in part to solicit quo
132. ur modules that make up the integrated unit When accessing the VXI Plug and Play driver only the base address position A of the VX405C should be used NOTE The M210 Trigger Distribution Module is configured with the input thresholds set to fixed factory default levels No programming is required for this module and thus the software driver does not refer to it Introduction 1 4 Astronics Test Systems Publication 980900 Rev General Description Purpose of Equipment Specifications of Equipment Key Features Astronics Test Systems 3352 User Manual Chapter 2 VX405 The 405 is a single slot register based C size VXlbus compatible carrier module that provides electrical and mechanical support for up to six single M or MA modules M MAs Of these six M modules connections four are used for a fully populated 3352 This is because the M210 M1714 M1721 and the M212 are double wide M modules and only one of the two connections is enabled The connections that are enabled are C D and fora fully populated 3352 Each installed M MA module appears as an independent VXI instrument to the VXI resource manager Full VXI and MA Module triggering and addressing is supported This module provides a carrier function for the plug in modules that make up the 3352 Rubidium system Supports up to six 6 ANSI VITA 12 1996 compliant single wide M or MA modules or any valid combination
133. vers User s Guide for command details Interrupts The M213 supports Type A and Type C interrupts as specified in the M module specification A Type A interrupt releases the interrupt request only after the pending interrupt is cleared by software software end of interrupt RORA Type interrupt releases the interrupt request during the interrupt acknowledge cycle hardware end of interrupt with vector i e ROAK Type C interrupts provide an interrupt vector during an interrupt acknowledge cycle Use the IT bit in the Interrupt Control Register to configure the desired type of interrupt NOTE For any interrupt to occur the MIEN bit in the Interrupt Control Register must be set to a one For an interrupt to occur the desired interrupt source must be enabled PIEN or UIEN and the master interrupt enable MIEN must be enabled in the Interrupt Control Register For Type C interrupts the interrupt vector is equal to the lower byte of the interrupt control register NOTE When using Type C interrupts the MIEN bit is cleared during the interrupt acknowledge cycle must be re enabled to receive another interrupt ID Prom Refer to Chapter 4 section M Module Identification PROM for a description of the ID PROM s function and contents The ID PROM is a serial device and accessing it involves writing and reading a register in a sequential manner to acquire data Figure 3 5 provides a ge
134. versions of the 3352 For a version that does not have a particular M module associated with it skip the corresponding section in the manual MTBF The following is the MTBF calculations for each of the modules that make up the 3352 followed by the MTBF for each 3352 version The MTBF was obtained using the Relex software with calculations configured for MIL HDBK 217 FN2 1 VX405C Carrier 62 622 hrs 2 M1708 150 000 hrs 3 M210 199 508 hrs 4 M213 M213 board 264 879 hrs b M12 GPS receiver 1 600 1000 hrs 5 M212 a M212 board 926 476 hrs b Rubidium Module 174 720 hrs 6 M1714 765 387 hrs 7 M1721 663 695 hrs The following is the calculated values for each of the 3352 variants 1 3352 w GPS training 407919 29 551 hrs 2 3352 w o GPS training 407919 001 33 967 hrs 3 3352 w GPS training and PG dist 407919 002 25 740 hrs 4 3352 w o GPS training and Dig 1 0 407919 003 32 526 hrs 5 3353 w GPS training and Trig Dist 407919 004 28 453 hrs Programming A VXlplug amp play driver is available that provides high level functions to configure operate and get status of the 3352 The driver includes an interactive soft front panel application that allows the user to interactively control the 3352 from any Windows based VXI host Also included are 32 bit Windows DLL and LIB files that allow the user to call the VXI Plug and Play driver from almost any programming environment including C Visual Basic LabWind
135. y Only the Rb loop needs to be locked to indicate a locked condition on pin 21 2 1PPS Disciplining Enabled Requires both Rb loop to belocked AND 1PPS synchronization lock to indicate a locked condition on pin 21 Notes These numbers are in Hex format 1ppsStates 0 2 Initialize 3 9 Holdover 6 8 Disciplining When connecting to a GPS receiver the factory default mode is recommended Start with y1 1 DF and 2 400 TC in seconds These values work well for most GPS receivers Use z command to save your settings X72 Rubidium system will lock approx 5 minutes after startup X72 initial frequency must be less than 3PPB for 1PPS to lock Initial 1PPS lock will occur between 3 5 minutes after both lock and valid 1PPS are present Confirm the firmware version by issuing the i command Xxis a value returned which is the hex equivalent of the number of times the table has been written to Tdata can be either 1 or 2 Calibration The X72 is designed to stay within 8 for 20 years without calibration At the end of this period the X72 should be returned to the factory for service Astronics Test Systems 212 4 21 3352 User Manual Publication No 980900 Rev B Floating Point The host PC must convert Floating Point numbers output by the Number X72 to the host s own floating point using the definition shown in Table 4 4 Likewise the host s floating point numbers must be Represent

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