XEM5010 User`s Manual
Contents
1. NAO edo om om 14 327 9 827 All dimensions in mm www opalkelly com 22 23 001 O O vecasa O vacas O uca 38 30 O Q JP JC L6 O O O O O O O O O O O O 0 O O O0 O O O O O O O O O O O O O O O O O O e20 O O O O O O O O O O O O O O O O O O Omg O O O O O O O O O O O O O O j 010 O O O O O O O O O O O O O O O O O Ojvs eio O O O O O O O O O O O O O O O O O O Os 68 XEMS5010 User s Manual All dimensions in mm 135 BRK5010 Mechanical Drawing be p0000000000000000000 QO000000000000000000 QOUU00U0000000000000 DM 0S LL pes le EE m q a i cse O kn cc c Cem 68 9 o gt DOQ00000000000000000 Minii mnn o o8 83 WM MW LO O aN gt e B 6 8 P g Jen x SR c aja 3 9u bei bada THIS p EE mo e HOH 0000000 0000000000400 000000000 00000000000 y em TZ LZ IC q 0 L I L EL 1L X du I T E 00 DEND EA O P0g00 00000 00000000000 gt 0000000000 0000000002. www opalkelly com pins IMPORTANT NOTE 3 3v I O Operation JP2 JP3 As process technology shrinks I O voltages tend lower The Xilinx Virtex 5 FPGA is no excep tion and has limited 3 3v I O operation Before using the XEM5010 to interface to any 3 3v de sign please review the Xilinx Virtex 5 FPGA User Guide Chapter 6 3 3V I O Design Guidelines JP2 is a 120 pin high density connector providing access to FPGA Banks 13 17 and 21 Pin mappings for JP2 are listed at the end of this document in the Quick Reference section For each JP2 pin the corresponding board connection is listed For pins connected to the FPGA the corresponding FPGA pin number is also shown Finally for pins routed to differential pair Os on the FPGA the FPGA signal names and routed track lengths have been provided to help you equalize lengths on differential pairs JP3 is a 120 pin high density connector providing access to FPGA Banks 14 18 and 3 Bank 3 is primarily a clock input bank providing up to 10 differential clock inputs or 20 single ended inputs Pin mappings for JP3 are listed at the end of this document in the Quick Reference section For each JP3 pin the corresponding board connection is listed For pins connected to the FPGA the corresponding FPGA pin number is also shown Finally for pins routed to differential pair Os on the FPGA the FPGA signal names and routed track lengths have been provided to help you equalize lengths o
3. 3 3VDD and the cathodes wired directly to the FPGA To turn ON an LED the FPGA pin should be brought low To turn OFF an LED the FPGA pin should be brought high The external LED connector is wired a bit differently JP4 1 is attached to 3 3VDD JP4 2 through JP4 5 are each attached through a 330 0 resistor to an FPGA pin Externally you should connect the four LED anodes to JP4 1 3 3VDD The four cathode should be attached to the other pins on JP4 Clock Oscillator Connections JTAG The LVDS clock oscillator produces a 100 MHz LVDS signal which is presented on FPGA pins AD8 and ACT These are LAP GC 4 and LAN GCA inputs respectively An on board 100 ohm termination resistor is present On the XEM5010 the FPGA is the only device on the JTAG chain The JTAG pins connecting to the FPGA are available on the expansion connector JP2 so that you can attach a suitable JTAG chain or programmer on your boart SPI Flash Connections The on board SPI flash device is attached to the FPGA according to the following table FPGA Configuration via SPI Flash The Virtex 5 on the XEM5010 may be configured by USB or SPI Flash When using USB the FPGA may be configured at any time When booting by SPI Flash configuration takes place at power on To boot to the configuration file loaded into the SPI Flash remove the jumper at J1 To load the SPI Flash with your configuration data we have provided a sample FlashLoader which is located in th
4. HLINOUTIS ACTS Cam Le H NOUTI ACS HLINOUTIB HLINOUTI HLINOUTII0 AMS HLINOUTIM Ten HLINOUTIt2 AA12 HLINOUT IS ABA i va iP veui 30810 m ara EC Jee ss aen hena 32881 2 0 lt lt X N www opalkelly com 25 XEMS5010 User s Manual XEMS5010 Quick Reference P comes ives o Jl Pin Connection LVDS mm s o tu smee 1s 18878 s H L2N SMeN 1S 19238 i voco gt a vecor Jl eo vzo hmo 15965 ss Aczi LP cc 17 17567 os as mn cear 17766 so faco fuma 27 884 m Wee T m vocon T feo ae Lipzi 27294 os Apos fona 25941 ss Apo isP2i forsor 26 P comes os jl Pin Connection LVDS mm mire v NE p Fi eem e ma Jura to me stas rms AcE erp pzo ExrPRoG 1 1 www opalkelly com XEMS5010 User s Manual XEMS5010 Quick Reference Pi comecton Des Jl Pin Connection LVDS mm s ee poca set coa a vccoa Sid m y uei farao m vccos s eco ss vr Lie GC 18 29 55 foo ass tran VREF 18 80881 P comeston J tm Pin Connection LVDS mm pof A E E A s ma uss ser 15 eveseat ju eov m9 rovo www opalkelly com 27 XEMS5010 User s Manual e XEMS5010 Quick Reference ELLE me ie JS Pin Connection LVDS mm Pin Connection LVDS mm Geo Pa a
5. a small memory on the FPGA to support bitstream encryption Please see the Xilinx Virtex 5 documentation for details Supply Currents The on board regulators provide the following supplies and respective current 3 3v 1 0A USB microcontroller clock oscillator and default FPGA I O 2 5v 2 0A FPGA VCCAUX 1 8v 1 0A DDR2 SDRAM and SSRAM 1 0v 6 0A FPGA VCCINT 3 3v is available on JP2 and 1 0v is available on JP3 Designers should note the current limi tations before deciding to use these supplies USB Bus Power The USB 2 0 specification allows for up to 2 5 W 500mA at 5v to be provided to external pe ripherals over the USB cable Due to the potentially high power requirements of the XEM5010 USB power has not been connected However the XEM firmware reports to the USB hub as a 500 mA device USB 2 0 Interface The XEM5010 uses a Cypress CY7C68013A FX2LP USB microcontroller to make the XEM a USB 2 0 peripheral As a USB peripheral the XEM is instantly recognized as a plug and play peripheral on millions of PCs More importantly FPGA downloads to the XEM happen blazingly fast virtual instruments under FrontPanel update quickly and data transfers are much faster than the parallel port interfaces common on many FPGA experimentation boards On board Peripherals The XEM5010 is designed to compactly support a large number of applications with a small num ber of on board peripherals These periphera
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7. 0000000000 0000000000 4 O ES OS CC K O DEND JPB IPSC 9 06006660666660666606066 DEE mo 0000000000000000 OO Domigo SOOOOODOOOOOOOOOO Oi P goooooooooooooodOo0loo0Jjs nooooO0o000000000000090090 es dO D O OO OO 0 0 0 OO OO OO OO Ofc c fl JU vos O U66682 O UGGORG VBE O CN rd O st st r NOOO N CO O N cN O Som s m c XEMS5010 User s Manual BRK5010 Schematic 20100226 s OBS UTE NAH TOTO SSC a p E x Amex edo a ro OLOSMAT 1 owe 1a vir DOL OVIN BANGAT SIL DV1r daxec Taf 3103347 DEED n oan 1020 1022A ar HO aav re IdaAo L AH aao ES Koart Ka CT Vas as egen ul E ES KC GL on on Ds gs LIMBAH liroooA s022 s002 er000A 10024 1000A SEI 1 009 Ae L1009 www opalkelly com 24 XEMS5010 User s Manual XEMS5010 Quick Refe JP2 FPGA Length JP2 FPGA Length Host Interface FPGA Pin Connection LVDS mm Pin Connection LVDS mm Pin Pin VA A RN p wcon Pros JP Pr A s o up sus s Jam w o OT pr m me _ ms maemo 1 N mevo hom Act mopso om act FI INQUTIO AD18 HLINOUT ACTS HLINOUTZ ABO HI INOUTIS Les HLINOUTHM Jaen
8. 010 You should read and become familiar with the DDR2 SDRAM datasheet as well as MIG and the core datasheet Although MIG can save a tremendous amount of devel opment time understanding all this information is critical to building a working DDR2 memory interface www opalkelly com 15 XEMS5010 User s Manual MIG Settings The following are the settings used to generate the MIG core for our RAMTester sample using Xilinx Core Generator These settings were used with ISE 10 2 and MIG 2 3 Note that settings may be slightly different for different versions of ISE or MIG Frequency 266 MHz Memory Type Component Memory Part MT47H64M16XX 3 1Gb x16 Data Width 16 Data Mask Checked Burst Length 4 010 default Burst Type Sequential 0 default CAS Latency 4 100 default Output drive strength Reducedstrength 1 RTT nominal 75ohms 01 default Additive latency AL 0 000 default Use DCM Your option DCI for DQ DQS CHECKED DCI for address control CHECKED Class for address control Class Debug signals Your option Limit to 2 bytes per bank No System clock Differential MIG Pin Selection To help MIG select the proper pins for the constraints UCF you can direct it to reserve non DDR2 banks and tell it where to map controllers for the others The selection process is e Reserve banks 1 2 3 13 14 17 18 21 MIG will not use these e For controller CO check all in banks 4 12 16 Uncheck all others e Forcontroll
9. 7 Opal Kelly XEM5010 User s Manual A compact 85mm x 61mm integration board featur ing the Xilinx Virtex 5 FPGA and on board DDR2 SDRAM SSRAM and SPI Flash The XEM5010 is a compact USB based FPGA integration board featuring the Xilinx Virtex 5 FPGA 256 MB 2x16 bit wide DDR2 SDRAM 1Mx36 SyncSRAM 32 Mb non volatile flash high efficiency switching power supplies and two high density 0 8 mm expansion connectors The USB 2 0 interface provides fast configuration downloads and FPGA PC communication as well as easy access with our popular FrontPanel software and developer s API An on board low jitter LVDS clock oscillator provides a 100 MHz clock source to the FPGA Software documentation samples and related materials are Copyright O 2006 2014 Opal Kelly Incorporated Opal Kelly Incorporated Portland Oregon http www opalkelly com All rights reserved Unauthorized duplication in whole or part of this document by any means except for brief excerpts in published reviews is prohibited without the express written permission of Opal Kelly Incorporated Opal Kelly the Opal Kelly Logo and FrontPanel are trademarks of Opal Kelly Incorporated Linux is a registered trademark of Linus Torvalds Microsoft and Windows are both registered trademarks of Microsoft Corporation All other trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed Revision History 20090
10. 721 20090730 20090908 20091105 Updated documentation to include VDC input voltage range and proper location of 3 3v and 1 0v outputs on JP2 JP3 20091227 Added BRK5010 schematic and mechanical drawing 20100226 20101101 20101104 20110926 2014093 20140812 Contents Introducing the XEM5010 5 EES 1222209 ipt b mat een tot b ak Bk 5 Functional Block Diagram 6 Power SUDO e Kn aga a a ES be PPS E ESSA 6 Supply Heat Dissipation IMPORTANT 6 DG Power COTnteclof oom p ted ag pa a a 6 WBATT aus ks m ar e mn ae 7 SUpply CUES uisto ta bro GO RV PE Eee T USB BUS POWER ee sia naar aa Raw pa RO IC UR A 7 USB 2 0 Interface doppie ihre TOUT ETRAS l On board Peripherals 7 Glock e EE 7 Serial EEPROM suis aaa RR SOR e 7 256 MByte Synchronous DDR2 DRAM 2x 128 MByte 8 36 Mb Word Wide Synchronous SRAM 8 32 Mb SPI Serial Flash sopor dr iaa 8 LEDs and External LED Connections 8 Expansion COnlecltors 2e ne dete SE Re uk ai 8 FrontPanel Support iss ses sau se RR ERR RSS 8 Programmer s Interface 8 Applying the XEM5010 11 FlostIDIeki aC see acsi acide Cod EE 11 MUXASEL anaa sac Pope P dun dace bd a ardor BA aes 12 PEL DECIDE 12 Clock Oscillator Connections 13 Np ciem P 13 SPI Flash Conn ectionS L jana nain aa can jr aja
11. DARD LVCMOS33 hi_in lt 4 gt LOC Y8 IOSTANDARD LVCMOS3 3 hi_in lt 5 gt LOC AA8 IOSTANDARD LVCMOS3 3 hi_in lt 6 gt LOC AA17 IOSTANDARD LVCMOS33 hi_in lt 7 gt LOC AB17 IOSTANDARD LVCMOS33 hi_out lt 0 gt LOC AC14 IOSTANDARD LVCMOS33 hi_out lt 1 gt Loc AC11 IOSTANDARD LVCMOS33 hi_inout lt gt LOC AD18 IOSTANDARD LVCMOS33 hi_inout lt 1 gt LOC AC18 IOSTANDARD LVCMOS33 hi_inout lt 2 gt LOC AB10 IOSTANDARD LVCMOS33 hi_inout lt 3 gt LOC AB9 IOSTANDARD LVCMOS33 hi_inout lt 4 gt LOC AC17 IOSTANDARD LVCMOS33 hi_inout lt 5 gt LOC AC16 IOSTANDARD LVCMOS33 hi_inout lt 6 gt LOC AC8 IOSTANDARD LVCMOS33 hi_inout lt 7 gt LOC AC9 IOSTANDARD LVCMOS33 hi_inout lt 8 gt LOC Y12 IOSTANDARD LVCMOS33 hi_inout lt 9 gt LOC Y13 IOSTANDARD LVCMOS33 hi inout 10 LOC AA15 IOSTANDARD LVCMOS33 hi inout 11 LOC AB14 IOSTANDARD LVCMOS33 hi inout 12 LOC AA12 IOSTANDARD LVCMOS33 hi inout 13 LOC AB11 IOSTANDARD LVCMOS33 hi inout 14 LOC AA13 IOSTANDARD LVCMOS33 hi inout 15 LOC AA14 IOSTANDARD LVCMOS33 hi_muxsel LOC AB15 IOSTANDARD LVCMOS33 Each of the
12. Virtex 5 FPGA Designed as a full featured integration system the XEM5010 provides access to 200 I O pins on its 676 pin Virtex 5 device and has 256 MByte of DDR2 SDRAM 36 Mb of SSRAM and 4 MByte of Flash memory available to the FPGA PCB Footprint A mechanical drawing of the XEM5010 is shown at the end of this manual The PCB is 85mm x 61mm with four mounting holes spaced as shown in the figure These mounting holes are electrically isolated from all signals on the XEM5010 The two connectors USB and DC power overhang the PCB by approximately 4mm in order to accomodate mounting within an enclosure The XEM5010 has two high density 120 pin connectors on the bottom side which provide access to many FPGA pins power JTAG and the microcontroller s 12C interface www opalkelly com 5 XEMS5010 User s Manual Functional Block Diagram 100 MHz 2x DDR2 667 LVDS OSC 64Mx16 SSRAM lt 1Mx36 Host Interface Virtex 5 FPGA x Bus XC5VLX50 1 FGG676 lt Flash 32Mb E 1 0 80 1 0 EN LEDs USB JTAG 20 GCLK XBUS JP2 YBUS JP3 Power Supply The XEM5010 has four high efficiency switching regulators to provide clean well regulated pow er to the FPGA and peripherals on the board These are Enpirion power modules and configured to supply 3 3v 2 5v 1 8v and 1 0v P1 is the DC power connector on the board and sources VDC to all four regulators Alternative ly VDC can be provided through the expansion
13. connector JP3 VDC must be sourced from a well regulated power supply in the range of 4 5v to 5 5v Supply Heat Dissipation IMPORTANT Due to the limited area available on the small form factor of the XEM5010 and the density of logic provided heat dissipation should be a concern This depends entirely on the end application and cannot be predicted in advance by Opal Kelly Heat sinks may be required on any of the devices on the XEM5010 Of primary focus should be the FPGA U12 Although the switching supplies are high efficiency they are very compact and consume a small amount of PCB area for the cur rent they can provide The FPGA will require additional passive or active cooling for even simple designs One such passive heatsink would be the INM27002 12PCU 2 6 available from Radian www radi anheatinks com The blue clip version BU T710 fits the Virtex 5 on the XEM5010 Of course this specific heatsink may not be suitable for all designs DC Power Connector The DC power connector on the XEM5010 is part number PJ 102AH from CUI Inc It is a stan dard 2 1mm 5 5mm power jack The outer ring is attached to DGND The center pin is attached to VDC on expansion connector JP3 as well as the inputs to the switching regulators on the XEM5010 6 www opalkelly com XEMS010 User s Manual VBATT VBATT is connected to the JP3 expansion connector and can be powered by a daughterboard to the FPGA This voltage is used to maintain
14. directly attached to the mating JP2 connector on the XEM5010 JP3A B C are directly attached to the mating JP3 connector on the XEM5010 The connections are straightforward Pin 1 of JP2 JP2 1 connects to JP2A 1 JP2 2 connects to JP2A 2 JP2 120 connects to JP2A 120 www opalkelly com 19 XEMS5010 User s Manual Errata Datecode 20091013 BRK5010 boards with PCB datecode 20091013 have the XEM5010 mounting holes incorrectly inset by 0 5mm The Samtec connectors JP2 and JP3 are correctly placed This error is cor rected with PCB datecode 20091209 as shown in the mechanical drawing Errata Datecode 20091013 and 20091209 BRK5010 boards with PCB datecode 20091013 and 20091209 have incorrect routing as follows Two pins were mis routed causing subsequent pins to be disjoint 20 www opalkelly com XEMS5010 User s Manual www opalkelly com 21 XEMS5010 User s Manual XEMS5010 Mechanical Drawing Mm 00 st Oo e E m LO o Sg O 18 B O c8 V9S LL I ERN i m mm ER Bl B Zen LT Sie 0 0 886 00 ive 29 713 15 925
15. e Samples directory of your installation This is a simple command line utility that can be used to transfer a configuration bitfile to SPI Flash The source code to the software is included so you can include this utility in your own application if required DDR2 SDRAM FPGA Connections The DDR2 SDRAMs are connected exclusively to the 1 8v I O on Banks 11 12 15 and 16 of the FPGA The tables below list these connections DDR2A is U15 on the PCB DDR2B is U14 www opalkelly com 13 XEMS5010 User s Manual 14 tk ps pas p UDM oor IR o Er M B o pu D a D A2 pp e p s o eo pa Be www opalkelly com XEMS5010 User s Manual o c ps oe p le D Mr Cascaded DCI The FPGA interface to the DDR2 SDRAM utilizes the digitally controlled impedance DCI feature of the Virtex 5 VRN and VRP pads on banks 15 and 16 are attached through 1 49 90 resistors to 1 8VDD and DGND respectively Banks 11 and 12 use references that are cas caded from banks 15 and 16 Cascade configuration must be specified in your constraints file UCF For example CONFIG DCI CASCADE CONFIG DCI CASCADE 16 1225 15 117 Memory Interface Generator MIG MIG is part of the Xilinx Core Generator and can be used to create a DDR2 memory controller for the XEM5
16. er C1 check all in banks 4 11 15 Uncheck all others Synchronous SRAM 16 The SSRAM has a full 36 bit wide data bus 4 bytes 4 parity pits The CLK pin is attached directly to the FPGA with the intent that the FPGA provide a synchronous clock in the so called source synchronous manner This helps align clock and data between the FPGA and SSRAM The redundant chip enable pins of the SSRAM have been tied to enable as appropriate E2 is tied to 1 8VDD and E3 is tied to DGND ZQ has been left as a no connect LBO is tied to DGND enabling linear byte order operation Finally all four byte enables BA BB BC and BD are tied to DGND High Performance Operation The SSRAM can achieve operation to 200 MHz but requires careful consideration of all FPGA timing parameters We provide the following as suggestions based on our development of test code but recommend a thorough timing analysis to achieve high performance reliable opera tion A good understanding of the SSRAM and FPGA timing datasheets is critical to this analy sis www opalkelly com XEMS010 User s Manual The SSRAM has a 0 5 ns hold time By setting the SSRAM CLK output from the FPGA to FAST this can advance the timing of the CLK in comparison to the address control lines Ac cording to the FPGA timings Toop this achieves approximately 0 6 ns hold time Delays from FPGA pads to the internal fabric can be significant and cause problems at high clock rat
17. es You must consider all delays when determining timing The following illustrates the timings considered for SSRAM reads Note that parts will differ depending on manufacturing process corners and operating techniques Adaptive techniques using the IDELAY elements help achieve optimal results Tocka QLOGIC CLK to OQ 0 62 ns Toop Delay from O pin to the IOB pad for CLOCK output 1 93 ns Tos SSRAM clock to Q read timing 5 00 ns T obi Delay from IOB pad to the pin of the IOB 0 89 ns T ILOGIC D pin setup with respect to CLK without delay 0 39 ns Total 8 83 ns This table indicates that for clock frequencies exceeding approximately 113 MHz SSRAM data reads may not be available to the FPGA fabric until the next clock cycle Therefore there is a single cycle read delay inherent in the design routing that must be accounted for in your design SSRAM FPGA Connections SSRAMPin FPGAPin SSRAMPin FPGA Pin UJU SE QG lt N SJS z N U oO U N www opalkelly com SSRAMPin FPGA Pin 17 XEMS5010 User s Manual Expansion Connectors 18 Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules It provides additional information on pin capabilities pin character istics and PCB routing Additionally Pins provides a tool for generating constraint files for place and route tools Pins can be found at the URL below http
18. ion above entitled Setting I O Voltages for details Characteristic Impedance The characteristic impedance of all routes from the FPGA to the expansion connector is 50 O Differential Pair Lengths In many cases it is desirable that the route lengths of a differential pair be matched within some specification Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible We have also included the lengths of the board routes for these connections to help you equalize lengths in your final application Due to space con straints some pairs are better matched than others Digitally Controlled Impedance DCI The Xilinx Virtex 5 supports digitally controlled impedance This functionality is supported when precision resistors are connected externally between the FPGA VRN VRP lines and VCCO DGND respectively These FPGA pins have been routed to the expansion connectors so that you may add resistors as appropriate on your daughterboard BRK5010 Breakout Board The BRK5010 is a simple breakout board for the XEM5010 that conducts the high density JP2 and JP3 signals to 2 mm headers for probing and simple prototyping The board also serves as a reference design for boards to attach to the module The mechanical drawing for this board is shown at the end of this document JP1 on the BRK5010 is a JTAG header compatible with the 2 mm Xilinx JTAG programming cables JP2A B C are
19. library available to Windows and Linux programmers allowing you to easily interface your own software to the XEM 8 www opalkelly com XEMS5010 User s Manual In addition to the C library wrappers have been written for C Java Python and Ruby making the API available under those languages as well Sample wrappers are also provided for Matlab and LabVIEW Complete documentation and several sample programs are installed with FrontPanel www opalkelly com XEMS5010 User s Manual 10 www opalkelly com XEM3050 User s Manual Applying tbe XEM5010 Host Interface There are 26 pins that connect the on board USB microcontroller to the FPGA These pins com prise the host interface on the FPGA and are used for configuration downloads After configura tion these pins are used to allow FrontPanel communication with the FPGA If the FrontPanel okHost module is instantiated in your design you must map the interface pins to specific pin locations using Xilinx LOC constraints This may be done using the Xilinx constraints editor or specifying the constraints manually in a text file An example is shown below Xilinx constraints for okHost pin mappings www opalkelly com 11 XEMS5010 User s Manual LEDs 12 hi in 0 LOC AD13 IOSTANDARD LVCMOS33 hi_in lt 1 gt LOC AD15 IOSTANDARD LVCMOS33 hi_in lt 2 gt Loc AD14 IOSTANDARD LVCMOS33 hi_in lt 3 gt LOC AB12 IOSTAN
20. ls are listed below Clock Oscillator The clock oscillator produces a 100 MHz 50ppm LVDS signal with 45 5596 symmetry and 0 5 ps typical phase jitter 1 0 ps RMS max measured from 12 kHz 80 MHz Serial EEPROM A small serial EEPROM is attached to the USB microcontroller on the XEM5010 but not directly available to the FPGA The EEPROM is used to store boot code for the microcontroller as well as a device identifier string The device identifier string may be changed at any time using FrontPanel The string serves only a cosmetic purpose and is used when multiple XEM devices are attached to the same computer so you may select the proper active device www opalkelly com 7 XEMS5010 User s Manual 256 MByte Synchronous DDR2 DRAM 2x 128 MByte The XEM also includes two 128 MByte DDR2 SDRAM with fully independent 16 bit word wide interfaces to the FPGA This SDRAMs are attached exclusively to the FPGA and do not share any pins with the expansion connector The maximum clock rate of the SDRAM is 266 MHz None of the pins control address or data are shared between the two SDRAM busses The SDRAM is a Micron MT47H64M16HR 3 G or compatible 36 Mb Word Wide Synchronous SRAM One synchronous SRAM 1M x 36 configuration is included with dedicated address data and control lines routed to the FPGA The SSRAM is a GSI Technology GS8322Z36GB 200V or equivalent 32 Mb SPI Serial Flash One Numonyx M25P32 or equivalent SPI se
21. n a sar aa ANA a 13 FPGA Configuration via SPI Flash 13 DDR2 SDRAM 4422329 c ox P RRRE A RI RITE es 13 FPGA CONNECUONS xod Gandia manda budini gon rate odds 13 Cascaded DGl 122a nature rd RES ERR XP 15 Memory Interface Generator MIG 15 MIG Settings esae gerer a ede Sox e gres 16 MIG Pin Selection ubicar oci tA caia ties ds 16 Synchronous SRAM 16 High Performance Operation 16 SSRAM FPGA Connections 17 Expansion COmnmeCtOns iue at gum a deem rk dnas a dba 18 IMPORTANT NOTE 3 3v I O Operation 18 dE Zr Ne bg oh Ge en ea a ee eee TE 18 Jo oS Ske T a a etn S tee te oe 18 Setting VO ee 0 4 gm did 18 Considerations for Differential Signals 19 BRK5010 Breakout Board 19 Errata Datecode 20091013 20 Errata Datecode 20091013 and 20091209 20 XEMS5010 User s Manual XEM5010 Mechanical Drawing 22 BRK5010 Mechanical Drawing 23 BRK5010 Schematic 20100226 24 XEM5010 Quick Reference 25 XEM5010 Quick Reference 26 XEM5010 Quick Reference 27 XEM5010 Quick Reference 28 4 www opalkelly com XEM3050 User s Manual Introducing the XEM5010 The XEM5010 is a compact 85mm x 61mm 3 35 x 2 40 FPGA board featuring the Xilinx
22. n differential pairs Setting I O Voltages The Virtex 5 FPGA allows users to set I O bank voltages in order to support several different I O signalling standards This functionality is supported by the XEM5010 by allowing the user to con nect independent supplies to the FPGA VCCO pins on six of the FPGA banks By default ferrite beads have been installed which attach each VCCO bank to the 3 3VDD supply If you intend to supply power to a particular IJO bank you MUST remove the appropriate ferrite beads Power can then be supplied through the expansion connectors The table below lists details for user supplied I O bank voltages VO Bank FPGA Pins Ferrite Bead JP32 JP34 E14 D17 www opalkelly com XEMS5010 User s Manual VO Bank FPGA Pins Ferrite Bead 921 923 N20 M23 ROA JP3 41 JP3 43 W2 R4 V5 JP2 42 JP2 44 T21 W22 V25 JP3 85 JP3 87 AB3 AA6 AD7 JP2 86 JP2 88 AC20 AB23 AE24 Considerations for Differential Signals The XEM5010 PCB layout and routing has been designed with several applications in mind including applications requiring the use of differential LVDS pairs Please refer to the Xilinx Virtex 5 datasheet for details on using differential I O standards with the Virtex 5 FPGA FPGA I O Bank Voltages In order to use differential I O standards with the Virtex 5 you must set the VCCO voltages for the appropriate banks to 2 5v according to the Xilinx Virtex 5 datasheet Please see the sect
23. rial flash is connected to the FPGA for non volatile storage LEDs and External LED Connections Four on board LEDs are provided for general use In addition a 5 pin expansion connector JP4 allows the connection of a external LEDs Four pins of this connector are wired to FPGA pins via series 330 0 resistors Expansion Connectors Two high density 120 pin expansion connectors are available on the bottom side of the XEM5010 PCB These expansion connectors provide user access to several power rails on the XEM5010 several FPGA clock inputs the JTAG chain and 200 non shared I O pins on the FPGA The connectors on the XEM5010 are Samtec part number QSE 060 01 F D A The table below lists the appropriate Samtec mating connectors along with the total mated height Samtec Part Number Mated Height QTE 060 01 F D A 5 00mm 0 198 QTE 060 02 F D A 8 00mm 0 316 FrontPanel Support The XEM5010 is fully supported by Opal Kelly s FrontPanel software FrontPanel augments the limited peripheral support with a host of PC based virtual instruments such as LEDs hex displays pushbuttons toggle buttons and so on Essentially this makes your PC a reconfigu rable I O board and adds enormous value to the XEM5010 as an experimentation or prototyping system Programmers Interface In addition to complete support within FrontPanel the XEM5010 is also fully supported by the FrontPanel programmer s interface API a powerful C class
24. samples installed with FrontPanel includes a copy of a template constraints file that lists all the XEM5010 pins and maps them to the appropriate FPGA pins using LOC location constraints You can use this template to quickly get the pin locations correct on a new design MUXSEL MUXSEL is a signal on the XEM5010 which selects the signal path to the FPGA programming signals DO and CCLK When low deasserted the FPGA and USB microcontroller are connect ed When high asserted the FPGA and PROM are connected In normal USB programmed operation J1 pulls MUXSEL low connecting the FPGA and USB microcontroller at all times This allows USB based programming of the FPGA and subsequent USB communication with the FPGA design after configuration In order to allow the PROM to configure the FPGA J1 must be removed However if the USB is to communicate with the FPGA post configuration MUXSEL must be deasserted Therefore the FPGA outputs MUXSEL so that post configuration the FPGA can deassert MUXSEL and com municate over USB even after the PROM has configured it The end result is that your FPGA design should tie HI_MUXSEL to 0 For example in Verilog assign hi muxsel 1 b0 There are four LEDs and four external LED pins on the XEM5010 Each is wired directly to the FPGA according to the pin mapping tables at the end of this document www opalkelly com XEMS010 User s Manual The LED anodes are connected to a pull up resistor to
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