2 PCIe to ISA Bus controller Core
Contents
1. Ke app PIO0 la o Signals DEV 1 UNIT 0 fapp PI0 sa_o 00046 o Data Port la fappiPlOa_o fappiPIO PIO_EPfep_isa app PIO ior_n_o appiPlO sa_o gt fappiPlO sdout o CH 0 Japp PlOlsa_o lt 05 app PIO memr_n_o CH 1 Japp PlO sa_os15 CH 2 appiPlOisa_o lt 2 PP 20 memw_n_o H 3 fappiPlOlsa_o lt 3 gt app PIO belk_o H 4 JappiPlOlsa_os4 H 5 JappiPlOlsa_o lt 5 app PIO bale_o H 6 Japp PlO sa_o lt 6 gt H 7 JappiPlOlsa_os H 8 fappiP Sek H H H H app PIO sdout en o app PIO iow_n_o 9 lappiPlOlsa_o lt 9 10 fappiPlO sa_o lt 1 11 fapp PIO sa_o lt 1 12 fappiPlOfsa_o lt 1 13 fappiPlOfsa_o lt 1 14 JappiPlOlsa_ost H 15 fappiPlO sa_o lt 1 H 16 appiPlO sa_o lt 1 H 17 fapp PlO sa_o lt 1 H 18 fappiPlO sa_o lt 1 H 19 fapp PlO sa_o lt 1 f H 20 fapp PlOfla_o lt 1 x A c C c C C C C C c C C c Cc C c C c C fim 2 Windows Explorer WA Outlook Express Arun Si ChipScope Pro Analyz E Calculator R D I 2 38PM Figure 4 Memory Write Cycle iWave Systems Technologies Pvt Ltd Page 23 of 26 e IWave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R 2 0 e To read from the memory space of the host cpu mark the auto read memory tab select some register in the top down list To check the ISA waveform in the chipscope viewer set the trigger values in the trigger window2. 5 04 5 05 D 21 0 D 21 1 0 31 3 1 00 SOR 3 0 0 PcI ISA Bridge Device VID xlOEE Xilinx Corp DID x0007 no device name found no 0 l gt 2 2 PCIAPCI SubVID xlOEE Xilinx 0 ame o EEEE E xFF lt INTA D e o S Are you ready to perform e zen BaseClass SubClass E BAR BAR read write OxFFFFFFFF read restore mp type l xs BIST Header LatTimer BAR Host PCl1 Bridge I O gt 1l iZ PCI PCIs gt Bri Nr of ConfRegs E ZG Ae C 64 refresh dump o serial bus Dev O gt S 45 Subtractive 0 VGA PC Compati D Ethernet Netwe PCIYISA Bridge De Mass Storage Cc SMBus 00072 0010 060l oooo0 oooo0 4800 oooo oooo 1OEE 01472 oooo oo10 3001 0000 oooo oooo lt 00 lt 04 lt 08 lt 0C lt 10 KA 18 lt 1C 4 use BIOS int DID WID BAR io If not a B4Rrange of 1MByte is assumed KS Stat Cmd B R F mem Serial Bus iWave Systems Technologies Pvt Ltd Page 21 of 26 e IWave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R 2 0 e The window containing all the registers under that BAR space are listed we can access those register To write into any register of memory space select some register enter the data to be written in edit memory tab e To view the ISA waveforms for memory write first set the trigger values as in the screenshot amp trigger for these values by pressing F5 amp then press write memory tab
3. e To write into the memory space of the host cpu select memory BAR register amp double User Manual for PCIe to ISA Bus Controller R 2 0 click on that BAR regsiter amp press yes tab on the information window PciTree bus ele m direct select dev fo show INT routing Ef show Mem Map PciTree direct select dev o bus s 3 0 0 PCI ISA Bridge Device VID xlOEE Xilinx Corp DID x0007 no device name found no SubVID x1lOEE Xilinx SubID x000 no name rew x00 Host PCI Bridge I O gt 1l 2 PCI PCI Br 1 gt 2 2 PCI PCIG 0 gt 3 3 PCI PCI Br3 PCI ISA Bridge 4 PCIZPCI Br Ethernet Netwe 16550 Compatibl serial bus E xFF lt INTA edit ConfReg Gf rie x48000000 nex GG Are C 64 Write ConfReg refr after wr o gt 4 o Host Cor Host Cor Host Cor Host Cor Uni d miversa SSES Universal dump Universal Universal use BIOS int Config Space Dump DID VID Stat Cmd BaseClass SubClass E BIST Header LatTimer D type 1 xs bus Dew o serial i5 Subtractive VGA Ethernet PCI ISA Bridge De o Mass Storage Cc SMBus 0 gt 5 PC Compati Netwe Serial Bus show INT routing eal show Mem Map host CPU 0 00 0 Er o ze o 0 28 4 0 28 5 4 00 4 00 4 00 0 29 0 0 29 1 DE 0 29 3 0 29 7 0 30 0
4. LL fapp PI0 la_o Signals DEV 1 UNIT 0 fapp PI0 sa_o o Data Port JappiPlOsla_o JappiPlO PIO_EP ep_is app PIO ior_n_o JappiPlO sa_o JappiPlO sdout_o CH D appiPlO sa_os05 app PIO memr_n_o CH 1 Japp PIO sa_o lt 15 CH 2 fappiPlOisa_o lt 2 gt epp P10 memy_n_o CH 3 appiPlO sa_o lt 3 gt app PIO belk_o CH 4 app PlO sa_o lt 4 CH 5 appiPIO sa_o lt 6 app PIO bale_o CH 6 Japp PIO sa_o lt 6 gt CH 7 Japp PIO sa_o lt 75 CH 8 Japp PIO Sa_o lt 85 CH 9 fapp PIO sa_o lt 9 CH 10 Japp PlO sa_os CH 11 app PlO sa_os CH 12 fapp PlO sa_os CH 13 Japp PlO sa_o 1 CH 14 Japp PlO sa_o 1 CH 15 Japp PlO sa_os CH 16 Japp PlO sa_os CH 17 Japp PlO sa_os CH 18 app PlO sa_o lt CH 19 Japp PlO sa_o lt CH 20 JappiPlOfla_os1 Ad Aaen app PIO sdout_en_o app PIO iow_n_o DONE fm 2 Windows WA Outlook Exp Si ChipScope P E Calculator Wi isalO bmp Esjaruntias RIA v 2 43PM Figure 5 Memory Read Cycle iWave Systems Technologies Pvt Ltd Page 25 of 26 ka IWave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R 2 0 APPENDIX A Reference Documents d PClItree software usage from http www pcitree de userguide html d Spartan 3 for PCI Express starter kit board user guide UG256 http www xilinx com support documentation boards_and_kits ug256 pdf iWave Systems Technologies Pvt Lt
5. Supports a 20 bit system address lines tristate which can be latched on to the falling edge of bus address latch enable signal Supports latchable address lines these unlatched address signals give the system up to 16 MB of address ability iWave Systems Technologies Pvt Ltd Page 4 of 26 ka IWave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R 2 0 1 4 Evaluation Board and Core requirements O O O Spartan 3 PCI Express Kit Mother Board with PCIe slot with PCIe tree software installed PC laptop with ChipScope software installed Endpoint core for PCI express PIO Module from Xilinx PCIe to ISA bus controller core iWave Systems Technologies Pvt Ltd Page 5 of 26 o IWave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R 2 0 2 PCIe to ISA Bus controller Core 2 1 Block Diagram User PCI Express PCI Express ISA Bus Transaction Transaction PHY Interface c ISA Interface PIO Interface En dp oint Interface Master Module Interface Xilinx Core Figure 1 Detailed view of iW PCle to ISA controller core 2 2 Description The PCle Bridge has an endpoint PIPE v1 7 PHY Interface for PCIe 1 lane core from Xilinx Programmed I O module amp ISA controller The endpoint core from xilinx implements the physical layer PHY interface data link layer transaction layer amp configuration management layer of PCIe base specification v1 1 layering mo
6. o serial bus E Universal Host Universal Host Universal Host Universal Host Cor Cor Cor Cor SubID rev x00 redit ConfReg x00003001 hex Write ConfReg x000 no name xFF lt INTA Nr of ConfRegs is C 64 Config Space Dump refr after wr use BIOS int refresh dump type 1 xs o serial bus Dev 0 gt 5 bi Subtractive VGA PC Compati Ethernet Netwe PCI ISA Bridge De o Mass Storage Ce SMBus Serial Bus III iWave Systems Technologies Pvt Ltd DID VID BaseClass SubClass I BIST Header LatTimer BAR BAR 1 mem 32Zbit BAR Z BAR 3 BAR 4 3001 lt 10 Stat Cmd 0 io Page 14 of 26 Wave Embedding Intelligence e To write into the IO space of the host cpu select IO BAR register amp double click on that User Manual for PCle to ISA Bus Controller R 2 0 BAR regsiter amp then press yes tab on the information window PciTree direct select bus dev Ho host CPU 0 00 0 Host PCI 0 28 0 0 gt 1 2 PCI 0 28 4 0 gt 3 3 PCI 0 20 65 O gt 4 4 PCI F show INT routing show Mem Map 3 0 0 PCI ISAG Bridge I PCI Bri 1 00 0 l gt 2 2 Pcr Ppcr PCI Br 3 00 0 PcIyvyIsa Bridge PCI Bri 4 00 0 Ethernet Netwe 4 00 3 16550 Compatibl 4 00 4 o serial bus E 0 29 0 Universal 0 29 1 Universal 0 29 2 Universal 0 Za 2 Universal
7. we can observe the waveform as shown in the memory write screenshot Sl ChipScope Pro Analyzer isa_bus File View JTAG Chain Device TriggerSetup Waveform Window Help gt aT Project isa_bus Trigger Setup DEV 1 MyDevice1 XC3S1000 UNIT 0 MyiLA0 ILA ve D JTAG Chain DEV 0 MyDeviced lt CFOBSP Match Unit SBS DEI 9 DEV 1 MyDevice1 GC 291 7 MO TriggerP ono isabled e UND MALAO ILA fappiPlOlbale_o Trigger Setup fappiPlOlbelk_o HG JappiPlo memw_n_o rx Japp PlO mernr_n_o Signals DEV 1 UNIT 0 OPINN 9 Data Port fappiPlOlla_o JappiPlOfior_n_o gt appiPlO PIO_EP ep_ise JappiPlOIPIO_EPlep_isaird_data_o lt 16 gt appiPlO sa_a Japp PIOIPIO_EP ep_isafrd_data_o 14 fappiPlO sdout_o fappiPIOIPIO_EP ep_isaftd_data_o lt 13 gt CH 0 fapp PlOfsa_o lt 05 1 rte gei Japp PIO PIO_EP ep_isafrd_data_o 12 gt 2 fappiPlO sa_o lt 25 JappiPIO PIO_EPlep_isaird_data_o lt 11 gt 3 JappiPlO sa_o 3 gt Japp PIO PIO_EP ep_isalrd_data_o lt 10 gt 4 fappIPlOlsa_o lt 4 gt fappiPlOIPIO_EPtep_isaitd_data_o lt 9 gt 5 JappiPlOfsa_ox6 6 fappiPlolsa_o lt 64 Japp PIO PIO_EP ep_isaitd_data_o lt 8 gt 7 fappiPlOisa_o lt 75 JappiPIO PIO_EPiep_isa rd_data_o lt gt 8 JappiPlO sa_o 8 Japp PIO PIO_EP ep_isalrd_data_o lt 6 gt 9 fappiPlO sa_o 3 gt fappiPIOIPIO_EPtep_isaitd_data_o lt 5 gt 10 JappiPlO sa_ost 11 JappiPlOisa o1 1 Japp PIO PIO_EP ep_isaird_data_o 4 gt 12 appiPlO sa_os1 Japp PIOIPIO_EPiep_isaird_data_o lt 3 gt 13 fap
8. 0 29 7 o serial 0 30 0 O gt S 5 Sub Host Cor Host Cor Host Cor Host Cor bus Dev tractive 5 04 0 VGA PC Compati 5 05 0 Ethernet Netwc D 210 PCI sIsSA Bridge De O32 o Mass Storage Cc 0 31 3 SMBus Serial Bus PciTree direct select ES EE o Host PCI 4re you ready to perform BAR read write OxFFFFFFFF read restore If not a BARrange of 1MByte is assumed e ze o serial VID DID SubVID SubID rev Bridge Device x1lOEE Xilinx Corp xO007 no device name found no x00 edit ConfReg x0000200OL hex Write ConfReg refresh El refr after wr xlOEE Xilinx xO007 no name xFF lt INTA ES of ConftRegs Ae 64 IT use BIOS int dump 3001 show INT _show INT routing show Mem Map Bridge I O gt 1l 2 PcI sPct Bri l gt 2 2 ee bus Devi O gt S 5 Subtractive VGA PC Compati Ethernet Netwe PcIyvyisa Bridge De o Mass Storage Cc SMBus Serial Bus acoso Ppcr siIsa VID DID SubVID 0007 0010 0601 oooo0 oooo 4800 0000 0000 0000 highest busnr Config Space Dump itype l xs DID VID Stat Cmd BaseClass SubClass E BIST Header LatTimer EIE Ris CES 5 About Bridge Device xLlOEE Xilinx Corp x000 no device name found no 10EE 01472 oooo 0010 3001 oooo oooo oooo oooo iWave Sys
9. AA EER A eem Project aa es BI Waveform DEV 1 MyDevice XC3S1000 UNIT 0 MyILAO ILA ve P JTAG Chain DEV MyDeviced XCF08P Bus Signal x 64 24 16 56 96 136 176 216 256 296 336 376 416 9 DEV 1 MyDevicel C3810 e UNIT O MALA ILA amp fapp PIO PIO EP ep isa rd data 000 Trigger Setup gt Japp PIO sdout o 004 R DE E apoa o 00 AY Signals DEV 4 UNIT 0 japp PIO sa o 9 Data Port amp lapp PlOfla_o JappiPIO PIO_EPlep_isa app PI0 ior_n_o Japp PlOlsa_o JappiPlO sdout_o CH D app PlO sa_o lt 05 app PIO memr_n_o CH 1 fappiPlOlsa_os1 5 CH 2 fapp PlO sa_o lt 25 CH 3 fappiPlOlsa_o lt 3 gt app PI0 belk_o d d app PI0 sdout_en_o app PI0 iow_n_o app PI0 memw_n_o CH 4 app DEN CH 5 fappiPlOlsa_0 lt 5 CH 6 Japp PlO sa_os65 CH 7 lapp PlOlsa_os7 CH 8 fapp PlO sa_o lt 85 CH 9 Japp PlO sa_o lt 95 CH 10 Japp PlO sa_os CH 11 Japp PlO sa_o lt 1 CH 12 Japp PlO sa_o lt 1 CH 13 Japp PlOlsa_os CH 14 Japp PlO sa_o lt 1 CH 15 Japp PlO sa_o lt 1 CH 16 Japp PlO sa_os1 CH 17 Japp PlO sa_o lt 4 CH 18 Japp PlO sa_os1 CH 19 lappiPlO sa_ost CH 20 Japp PlOfla_os1 A X 0 0 amanna EE app PI0 bale_o INFO Device 1 Unit 0 Waiting for core to be armed Upload i start GR fm screenshots fm pcie_isa_bridge Wa OutlookExpress AdobeReader A chipScope Pro An Figure 2 IO Write Cycle i
10. Device O gt 1l 2 PCIYPCI gt Br Lawe 2 PcryPpcr O gt 3 3 PCI YPCI gt Br Pcrt visa Bridge i PCI PCI Br Ethernet Netwe 16550 Compatibl o serial bus E Host Cor Host Host o gt 4 Universal Universal Universal Universal Host o serial bus Dev 5 Subtractive VGA PC Compati Ethernet Netwe PcI siIsa o Mass Storage Cc SMBus Serial Bus Cor Cor Cor 0 gt 5 Bridge De iWave Systems Technologies Pvt Ltd VID x8086 Intel Corporation DID xZ2778 mo device mame found no SubVID xs0s6 Intel SubID x348D no name rev x00 no INT edit ConfReg Nr of ConftfRegs nex fie es use BIOS int Write ConfReg mi refr after wr DID VID Stat Cmd BaseClass SubClass E BIST Header LatTimer BAR BAR refresh dump Config Space Dump itype 1 xs o 1 2 3 4 5 Page 12 of 26 Wave Embedding Intelligence User Manual for PCIe to ISA Bus Controller R 2 0 e Locate the Spartan 3 PCI Express board in the PCI bus list once you locate the device PClItree software will displays bus number device number function number Vendor ID device ID amp configuration space contents in the right side of the pcitree window rciree show INT _show INT routing highest EX TT SC GE show Mem Map Host PCI Bridge I 0 gt 1 2 PCI PCI Br l gt 2 i PCI PCI 0 gt 3 3 PCI PCI Br PCI ISA Bridg O gt 4 4 PCI PCI B
11. PIO sa_o lt 1 5 CH 11 JappiPlOlsa_o Topp O_EP ep_isa rd_data_o lt 4 gt CH 12 appiPlO sa_o 1 JappiP O_EP ep_isafrd_data_o lt 3 gt CH 13 JappiPlO sa_o lt 1 CH 14 JappiPlO sa_o lt 1 CH 15 JappiPlO sa_o lt 1 CH 16 appiPlO sa_o lt 1 CH 17 JappiPlO sa_o lt 1 X PK PK gt OPK x OK OK OK OK OK OOK OK OK OK KO KOK Trigger Condition Name Trigger Condition Equation TriggerConditionO MO CH 18 JappiPlO sa_o lt 1 Type Window Windows 1 Depth Position 64 CH 19 appiPlO sa_o lt 1 CH 20 fappiPlOfla_o lt t is Storage Qualification All Data GULA andeng fm 2 Windows Expl WA Outlook Express Gi ChipScope Pro A E Calculator ii isa9 bmp Paint iWave Systems Technologies Pvt Ltd Page 24 of 26 e IWave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R 2 0 e Memory read screenshot I ChipScope Pro Analyzer isa_bus File View JTAG Chain Device TriggerSetup Waveform Window Help Or nng IPA Project isa bus 2 waveform DEV 1 MyDevice1 XC3 1000 UNIT 0 MYILAO ILA ve K JTAG Chain DEV 0 MyDevice0 CFOSP BusiSignal 64 24 16 56 96 136 176 216 256 296 336 376 416 DEV 1 MyDevice1 C3510 e UNIT 0 MyILAO ILA fapp PIO PIO EP ep isa rd data o Trigger Setup 1 Japp PIO sdout_o Waveform
12. Wave Systems Technologies Pvt Ltd Page 18 of 26 e IWave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R 2 0 e To read from the IO space of the host cpu mark the auto read memory tab select some register in the top down list To check the ISA waveform in the chipscope viewer set the trigger values in the trigger window as shown in screenshot press F5 to trigger and press the refresh view window to read the the register of IO space Si ChipScope Pro Analyzer isa_bus File View JTAG Chain Device TriggerSetup Waveform Window Help mT Project isa_bus E Trigger Setup DEV 1 MyDevice1 XC351000 UNIT 0 MYALAO ILA ee oe ve A JTAG Chain 7 7 DEV 0 MyDeviced XCFO8P Match Unit Function Value Counter e DEV 1 MyDevicet C3910 e MO TriggerPorto X_ 200 1000 _ 00 0_1 802 jisabled o UNIT 0 MyILAO ILA fapp PlOfbale_o rigger Setup jappiPlO belk_o Waveform JappiPlOfmemw_n_o AY BAEN Japp PlO memr_n_o Signals DEV 1 UNIT 0 R I A o o Data Port a e Japp PlOsla_o fappiPlOfior_n_o JappiPlOIPIO_EP ep_isa JappiPlO PIO_EPsep_isafrd_data_o 15 gt Japp PlO sa_o Japp PIOIPIO_EP ep_isafrd_data_o lt 14 gt ig RENE e fappiPIO PIO_EPfep_isa rd_data_o lt 13 gt D appiPlO sa_os05 CH 1 fappiPlOisa_o 1 JappiPlO PIO_EPiep_isafrd_data_o lt 12 gt CH 2 fappiPlOlsa_os2 Japp PIO PIO_EP ep_isafrd_data_o 11 gt CH 3 appiPlo sa_o 3 JappiPlO PIO_EPiep_isafrd_data_o lt 10 gt eh Gi SEH fappiPIOIPIO_EP ep_i
13. as shown in screenshot press F5 to trigger and press the refresh view window to read the the register of memory space i ChipScope Pro Analyzer isa_bus File View JTAG Chain Device TriggerSetup Waveform Window Help gt aT Project a bus E Trigger Setup DEV 1 MyDevice1 XC3S1000 UNIT 0 MYLAO ILA ee JTAG Chain DEV 0 MyDeviced KCFO8P Match Unit Function Courter e DEV 1 MyDevicet C3810 7 MOTriggerPortd fisabled UNIT 0 Wal An ILA JappiPlOfhale_o tigger Setup JappiPIOlbclk_o Waveform BCE EEN fappiPlomernw_n_o JappiPlO memr_n_o az Signals DEV 1 UNIT 0 A JappiPlOfiow_n_o o Data Port a AR JapplPlOlla_o fappiPlOfior_n_o JappiPIO PIO_EP ep_isa Japp O_EP ep_isaird_data_o 15 gt Japp PIOlsa_o Japp O_EP ep_isaird_data_o lt 14 gt P appiPlOfsdout_o fappiPIO PIO_EP ep_isaird_data_o lt 13 gt CH 0 appiPlOlsa_o lt 05 A CH 1 JappiPlO sa_o lt 14 Japp O_EP ep_isa rd_data_o lt 12 gt CH 2 JappiPlOisa_o lt 25 Japp O_EP ep_isa td_data_o lt 11 gt CH 3 app PlOfsa_o lt 35 Japp O_EP ep_isaird_data_o lt 10 gt CH 4 fappiPlOfsa_o 4 Japp O_EP ep_isa rd_data_o lt 9 gt CH 5 fappiPlO sa_o lt 5 A CH 6 JappiPlo sa_o lt 64 Japp O_EP ep_isa td_data_o lt 8 gt CH 7 JappiP Olsa_o lt 74 Japp O_EP ep_isa rd_data_0 lt 7 gt CH 8 app PlOfsa_o lt 8 Japp O_EP ep_isafrd_data_o lt 6 gt CH 9 JappiPlOlsa_o lt 8 gt Japp O_EP ep_isa rd_data_o lt 6 gt CH 10 app
14. cling switch off amp on the board Run the PCItree software on the host computer where the Spartan 3 PCI Express board is installed Check the software overview part to get more information regarding Pcitree software for read amp write of memory amp io space of host computer iWave Systems Technologies Pvt Ltd Page 11 of 26 Wave Embedding Intelligence 3 1 3 User Manual for PCIe to ISA Bus Controller R 2 0 Procedure for Demo Connect Spartan 3 PCI Express board to the PCIe slot of host computer also connect the Xilinx platform USB cable to the PC laptop in which chipscope software is installed Start the PCItree software installed in the host computer to which Spartan 3 PCI Express board is connected then Press OK please register x this program is distributed as shareware please register mailto info pcitree de http www pcitree de http 4 www shareit com programs 103142 htm The software will scan all the PCI bus attached to the host computer amp displays all the PCI bus as the tree structure Each PCI component has an integer number for bus device and function bdf Let eh aly GEN About bus dev ree o fumc Ka o select E host CPU 0 00 0 0 28 0 1 00 0 28 4 3 00 0 28 5 00 00 00 show INT routing ES highest Rech show Mem Map PZ Host PCI Bridge I 0 0 0 Host PCI Bridge
15. d Page 26 of 26
16. data 4 AD6 rxdata 5 AC6 rxdata 6 AE5 rxdata 7 ADS5 rxdatak 0 AF8 rxelecidle AF4 rxstatus 1 AD10 rxstatus 2 ACI1 rxvalid AD12 rxclk AE13 sys_reset_n AF4 sa_o 0 M3 sa_o 1 J7 sa_o 2 M7 sa_o 3 J6 sa_o 4 N7 sa_o 5 H5 sa_o 6 M8 sa_o 7 H2 sa_o 8 N8 sa_o 9 J5 sa_o 10 P8 sa_o 11 J4 iWave Systems Technologies Pvt Ltd Page 8 of 26 ka IWave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R20 iW PClIe ISA Bridge FPGA PINS PINS sa_o 12 p2 sa_o 13 K7 sa_o 14 P7 sa_o 15 K5 sa_o 16 R1 sa_o 17 L8 sa_o 18 P1 sa_o 19 L7 la_o 17 R2 la_o 18 HI la_o 19 R3 la_o 20 Ll la_o 21 Tl la_o 22 L2 la_o 23 T2 sbhe_n_o L4 sd_io 0 M19 sd_io 1 P20 sd_io 2 M20 sd_io 3 T20 sd_io 4 K20 sd_io 5 P21 sd_io 6 J20 iWave Systems Technologies Pvt Ltd Page 9 of 26 ka IWave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R20 iW PClIe ISA Bridge FPGA PINS PINS sd_io 7 R21 sd_io 8 H20 sd_io 9 P24 sd_io 10 J21 sd_io 11 P22 sd_io 12 H21 sd_io 13 R24 sd_io 14 H22 sd_io 15 R22 ior_n_o V6 iow_n_o U7 memr_n_o w5 memw_n_o V7 bclk_o R8 bale_o R7 iWave Systems Technologies Pvt Ltd Page 10 of 26 ka IWave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R 2 0 3 Quick Start 3 1 Connecting to a Ho
17. del The PIO design interfaces with the endpoint for PCI Express core s transaction interface amp responds with read write transaction for memory or IO transaction from the endpoint core The ISA bus controller is implemented in user interface side of the PIO design The host processor can access the unit through memory IO read and write commands The ISA bus is a 16bit interface which can be used to connect peripheral components to the host CPU through ISA bus iWave Systems Technologies Pvt Ltd Page 6 of 26 ka IWave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R 2 0 2 3 Pin outs of iW PCIe ISA Bridge core The pin outs of iW PCIe ISA Bridge is as shown in the table below Table 1 Pin outs of iW PCle ISA Bridge iW PCle ISA Bridge FPGA PINS PINS powerdown 0 AF22 powerdown 1 AD23 resetn AF24 rxpolarity AE24 txclk AE21 txcompliance AE23 txdata 0 ADI15 txdata 1 AE15 txdata 2 AF15 txdata 3 AE19 txdata 4 AF19 txdata 5 AE20 txdata 6 AF20 txdata 7 AD21 txdatak 0 AE22 txdetectrx_loopback AF21 txelecidle AF23 phystatus AF12 rxdata 0 AE8 amp rxdata 1 AC7 rxdata 2 AF6 iWave Systems Technologies Pvt Ltd Page 7 of 26 ka IWave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R20 iW PClIe ISA Bridge FPGA PINS PINS rxdata 3 AE6 rx
18. ird_data_o lt 6 gt Si 9 app PlO sa_0 9 lappiPIOIPIO_EP ep_isaird_data_o 4 gt H 10 appiPlO sa_o 1 z GH 11 fappiPlOisa_o lt 1 Japp PIO PIO_EP ep_isafrd_data_o lt 4 gt CH 12 JappiPlOisa_o lt 1 JappiP OIPIO_EP ep_isaitd_data_o lt 3 gt CH 13 appiPlO sa_o 1 fanniDIAIDIA CDian inaid dat 2 Japp PlO memw_n_o gt lt gt lt gt lt gt lt gt lt gt lt gt lt BA BA gt X gt K gt lt gt lt gt lt CH 14 fapp PIO sa_o lt 1 Sol CH 15 JappiPIO sa_o lt 1 Add Active Trigger Condition Name Trigger Condition Equation CH 16 fapp PIOfsa_o lt 1 De TriggerConditiond MO CH 17 app PlO sa_o lt 1 CH 18 fappiPIO sa_o lt 1 CH 19 app PlO sa_o lt 1 CH 20 appiPlO la_o lt 1 Type Window Windows Depth Position 64 Storage Qualification All Data sinden 4 az INFO Device 1 Unit 0 Waiting for core to be armed Upload fim 2 Windows WA Outlook Expr J Adobe Read GA ChipScope Pr isa2 bmp P E Calculator iWave Systems Technologies Pvt Ltd Page 17 of 26 e IWave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R 2 0 e IO write Screenshot amp l ChipScope Pro Analyzer isa_bus EEN File View JTAG Chain Device TriggerSetup Waveform Window Help NABRAK Fle
19. ka IWave User Manual for PCle to ISA Bus Controller Embedding Intelligence R 2 0 User Manual for PCIe ISA Bus Controller iWave Systems Technologies Pvt Ltd Page 1 of 26 ka IWave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R 2 0 Table of Contents 1 TINT ROU CT e E 4 1 1 EUR Ed ee aa aaa aa aa a aa oe ee 4 1 2 RS 6 6 EE 4 1 3 PRA E ENEE 4 1 4 EVALUATION BOARD AND CORE REQUIREMENTS 0cccccscscesscscecscscsseeeseeeseeseeesaeeneeenees 5 2 PCIE TO ISA BUS CONTROLLER CORE 66000000000000 000000000000 00000000000000 000000000000 000000000000 6 2 1 BLOCK DIAGRAM EE 6 2 2 DESCRIPTION i 22 iiicsntedceus eh ag ag a sted N E ga naa aa a a gag a aan a angga a asa gana 6 2 3 PIN OUTS OF IW PCIE ISA BRIDGE Coppi H 3 QUICK STAR VE 11 3 1 CONNECTING TO A HOST COMPUTER 11 KG WE 11 3 1 2 Board Installation amp Testing sii sena eaaa tata tess KENTANG i aaa a eg aa Kapa eben 11 K Procedur for Demo sacsiassicccsassisuniavsnctosivobaninsd seattacnaseatatueneaseiaadeatassasasaasaasasnosadsaene 12 APPENDIX A E 26 iWave Systems Technologies Pvt Ltd Page 2 of 26 ka IWave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R 2 0 List of Figures Figure 1 Detailed view of iW PCle to ISA controller core anane an nane anana een 6 e 10 Write Cycle aces toe cle ee ets a daa ga a aaa gaa E betes aad eee a a aed 18 Figur 3 IO Read E 20 Fig re 4 Memoty Write Cycles dsrin eniin aes ag asa
20. o ISA Bus Controller Embedding Intelligence R 2 0 e To view the ISA waveforms for IO write first set the trigger values as in the screenshot amp trigger for these values by pressing F5 amp then press write memory tab we can observe the waveform as shown in the IO write screenshot Si ChipScope Pro Analyzer isa_bus File View JTAG Chain Device TriggerSetup Waveform Window Help mm Project isa bus JTAG Chain T DEV 0 MyDeviced CFOSP Match Unit Value Radix Counter e DEV 1 MyDevicet C3810 7 MO TriggerPortd KOKOK 1000 KOK OGAK Hex disabled e UNIT 0 MyILAO ILA lappiP Osbale_o Trigger Setup JappiPlOfbelk_o Waveform Se ar lappiPlOimemr_n_o Signals DEV 1 UNIT 0 fappiPlOsiow_n_o g Data Port gt fappiPlOlla_o JappiPIOvior_n_o fappiPIOIPIO_EP ep_isd fappiPlO PIO_EP ep_isaird_data_o lt 15 fappiPIOisa_o fappIPIOIPIO_EPfep_isa rd_data_o lt 14 gt A SE A JappiPIO PIO_EP ep_isafrd_data_o lt 13 gt D japp Sa oss CH 1 JanpiPlosa_o lt 1 gt Japp PIO PIO_EP ep_isaird_data_o lt 12 gt CH 2 JappiPlO sa_o lt 24 fapp PIO PIO_EP ep_isa rd_data_o lt 11 gt CH 3 fappiPlO sa_o 3 gt fappiPlO PIO_EP ep_isaid_data_o lt 10 gt CH 4 Japp PlO sa_o lt 4 Japp PIO PIO_EP ep_isa rd_data_o lt 9 gt CH 5 Japp PlOlsa_o lt 5 CH 6 appiPlO sa_o lt 6 fapp PIO PIO_EP ep_isa rd_data_o lt 8 gt CH 7 fappiPlO sa_o lt __ fapp PlO PlO_EPlep_isaird_data_o lt gt CH 8 app PlO sa_o lt 8 Japp PIO PIO_EP ep_isa
21. oo00000zC xoo0000030 xoo0000034 xoo0000038 xoo000003C xoo0000040 xoo000044 xoo000004s lt xoo000004cC lt xooo0000s0 lt x00000054 lt x00000058 lt xoo00000sC lt xooo000060 xoo000064 xoo000006s8 xoo000006C xo0000000 lt xoo0000004 xoo0000008 lt xO0o000000C lt xO0o0000014 lt xO00000018 lt xoo0o00001C lt xoo00000z0 xo0o0o0000z4 lt xo0o00000z8 xo0o00000zC xo00000030 xO00000034 x00000038 xO0000003C xoo0000040 lt x00000044 lt xx00000048 lt xx0000004C lt xoo0000050 lt xooo0000s4 lt xoo00000S58 lt xoo000005C lt xoo0000060 lt xoo000064 lt xo00000068 lt xoo000006C lt xoo0000070 iWave Systems Technologies Pvt Ltd mi auto read memory Io Space base 00002000 range f fffffS0 125 Byte medit memory Data toggle Write Memory count Ka if TI loop on off IS SE 1 refresh view after write mem copy source destination mem copy OK select view range mi auto read memory IO Space base 00003000 range f fffff80 128 Byte edit memory Jx4shoo000 x00002010 1 dwords Data CT toggle Write Memory count if loop on oft l verity J refresh view after write refr view mem copy source destination mem copy select view range KB range 0 0 O SSS E15 Page 16 of 26 e IWave User Manual for PCIe t
22. piPlO sa_os A 14 fappiPlO sa_ost Active Trigger Condition Name Trigger Condition Equation 15 appiPlOisa_o lt 1 HEITT TriggerConditiond MO 16 app PlO sa_o 1 Type Window v Windows 1 Depth Position 64 17 fappiPlOfsa_ost Storage Qualification All Data 2K 2K 2 lt 2 lt 2 lt 2 gt lt 2 lt gt lt 2 lt 2 lt 2 lt gt lt gt lt a 2 lt x xXx 18 JappiPlO sa_ost 19 fappiPlO sa_o 1 20 JappiPlOfla_os1 a C c C C C C c Cc C C C C C C C C C c C C aimdesa fm 2 Windows Expl WA Outlook Express Zi ChipScope Pro A E Caleulator 1 isa9 bmp Paint SG OR iWave Systems Technologies Pvt Ltd Page 22 of 26 bal Wave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R 2 0 e Memory write Screenshot S ChipScope Pro Analyzer isa_bus File View JTAG Chain Device TriggerSetup Waveform Window Help Guna p k SE dk EERE a a R RR Project ba bus d Bi Waveform DEV 1 MyDevice1 XC3S1000 UNIT 0 MYLAO ILA ve A JTAG Chain ja 7 7 4 DEV 0 MyDeviceD XCFO8P Bus Signal Ed A UU AD Ed aoe re KA 9 DEV 1 MyDevicel C3510 f TCT e UNIT 0 MyILAO ILA app PIO PIO EP ep_isa rd_data o Trigger Setup fapp PI0 sdout o Waveform
23. r Ethernet Netwe 16550 Compatibl o serial bus E Universal Host Cor Universal Host Cor Universal Host Cor Universal Host Cor 0 serial bus Dev O gt 5 5 Subtractive VGA PC Compati Ethernet Netwe PCI ISA Bridge De o Mass Storage Cc SMBus Serial Bus 3 0 0 PCI ISA Bridge Device VID xlOEE Xilinx Corp DID x0007 no device name found no SubVID xlOEE Xilinx SubID x0007 no name rev x00 xFF lt INTA edit ConfReg of erie hex ie 64 Write ConfReg E refr after wr use BIOS int refresh dump Config Space Dump type 1 xs DID VID Stat Cmd BaseClass SubClass I BIST Header LatTimer BAR O io BAR 1 mem 3Zbit BAR Z BAR 3 BAR 4 iWave Systems Technologies Pvt Ltd Page 13 of 26 Wave Embedding Intelligence User Manual for PCIe to ISA Bus Controller R 2 0 e Select memory BAR register space to access host cpu memory space or select IO BAR register to access host cpu IO space In this screenshot IO BAR address 10h is selected PciTree select dev jo 3 0 0 PCI ISA Bridge Device VID xlOEE Xilinx Corp DID x0007 no device name found no SubVID xlOEE Xilinx Host PCI Bridge I O gt l1 Gi PCI SPCI Br l gt 2 2 PCI PCI O gt 3 3 PCI PCI Br PCI ISA Bridge O gt 4 4 PCI PCI Br Ethernet Netwe 16550 Compatibl
24. s anaa 23 Fig re 5 Memory Read e 25 List of Tables Table 1 Pin outs of iW PCIe ISA Bridge 7 iWave Systems Technologies Pvt Ltd Page 3 of 26 ka IWave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R 2 0 1 Introduction 1 1 Purpose The purpose of this document is to explain the procedure to power on and setting up working environment of the PCIe to ISA Bridge for demo purpose 1 2 Scope This document describes the Hardware connection procedure to power on the board and establishes connection with the PC LA Features PCIe Interface O O 0 0 0 00 O The Xilinx endpoint cores for PCIe follows PCI express base specification v1 1 layering model 32 bit internal data path The endpoint core implements the physical layer datalink layer transaction layer amp configuration management layer Six individually programmable BAR s amp expansion ROM BAR Supports MSI amp INTX emulation Supports removal of corrupt packets for error detection and recovery Compatible with PCI PCI Express power management functions Used in conjunction with NXP PX1011A PCI Express standalone PHY to achieve high transceiver capability 2 5 GBPS line speed automatic clock and data recovery 8b 10b encode and decode Supports a maximum transaction payload of up to 512 bytes ISA Master Interface O O O The ISA Bridge implements a 16 bit data interface Supports Bus clock of 8 MHz for ISA interface
25. saird_data_o lt gt 5 fappiPlO sa_os CH 6 fappiPlOisa_o lt 6 JappiPIO PIO_EPiep_isafrd_data_o 8 gt CH 7 fappiPlOlsa_os fapp PIO PIO_EP ep_isafrd_data_o lt 7 gt CH 8 JappiPlO sa_o lt 8 JappiPIO PIO_EPiep_isafrd_data_o lt 6 gt Ei enee fappiPIO PIO_EPfep_isa rd_data_o0 lt 5 gt 10 JappiPlOfsa_o lt CH 11 fapniPlOisa_o 1 JappiPIO PIO_EPiep_isafrd_data_o lt 4 gt CH 12 appiPlO sa_o 1 Japp PIO PIO_EP ep_isaird_data_o lt 3 gt CH 13 JappiPlO sa_o lt 1 oe CH 14 fappiPlOlsa_os1 gt z es z CH 15 appiPlO sa_ost Active Trigger Condition Name Trigger Condition Equation CH 16 appiPloisa_o lt 1 TriggerCondition Mo CH 17 fappiPlO sa_o lt 1 Type Window Windows 1 Depth Position 64 CH 18 JappiPlO sa_o lt 1 Storage Qualification All Data CH 19 fappiPlO sa_o lt 1 p PIOsla_os1 SSS ainjdeg lt DONE fm 3 Windows Explorer WA Outlook Express Arun A ChipScope Pro Analyz WA isa5 bmp Paint iWave Systems Technologies Pvt Ltd Page 19 of 26 e IWave User Manual for PCIe to ISA Bus Controller Embedding Intelligence R 2 0 e JO read screenshot Si ChipScope Pro Analyzer isa_bus File View JTAG Chain Device TriggerSetup Waveform Window Help Sr atles Fle 2A emeng A Project isa_bus OB Wa
26. st computer Follow the steps below to connect the Spartan 3 PCI Express board to the host computer through PCIe link to test the functionality of iW PCle ISA Bridge core 3 1 1 Installation Requirements The items listed below are necessary to install Spartan 3 PCI Express board to the host computer o PC laptop with Chipscope software installed o Host computer of windows NT 2000 or windows XP OS having an available PCIe slot with installed PCIe Tree software Board Installation amp Testing Before connecting Spartan 3 PCI Express Kit in the PCIe slot check all these settings are properly done for starter kit o Select the master parallel mode for FPGA configuration by installing M2 in JP3 Header o Other Jumpers position on Board JP8 2 3 JP1 2 3 JP2 2 3 JPS 1 2 JP6 2 3 JP9 J4 o Select the power source from the PCIe edge connector for this install the fuse in socket F2 position dont place separate fuse in F1 position Connect the Xilinx platform USB cable to the PC laptop USB port from JTAG socket J2 of PCle board for programming amp to check the ISA waveforms on chipscope viewer After this place the board in PCle slot of a host computer Program the MCS file pcie_isa_bridge mcs provided with user manual to the Spartan 3 PCI Express board for this first program the on board 8 Mb xilinx XCFO8P parallel Platform Flash PROM then configure the FPGA from the image stored in the Platform flash PROM by power cy
27. tems Technologies Pvt Ltd lt 00 lt 04 lt 08 DC 10 lt 14 lt 18 lt 1c lt 20 x1lOEE Xilinx ES pc KEF lt INTAS Ce 16 C 64 Nx of use BIOS int refresh dump itype 1 xs DID VID Stat Cmd BaseClass SubClass I BIST Header LatTimer BAR i BAR BAR BAR BAR Page 15 of 26 Wave Embedding Intelligence User Manual for PCIe to ISA Bus Controller R 2 0 e The window containing all the registers under that BAR space are listed we can access those register To write into any register of IO space select some register enter the data to be written in edit memory tab BAR space oooo00000 ooooo0000 oooo0o0000 ooooo0000 ooooo0000 oooo0o0000 ooooo0000 oooo0o0000 ooooo0000 ooooo0000 oooo0000 oooo00000 ooooo0000 oooo00000 oooo00000 ooooo0000 ooooo0000 ooooo0000 oooo0o0000 oooo0o0000 oooo0o0000 ooooo0000 ooooo0000 oooo00000 ooooo0000 oooo00000 oooo00000 oooo00000 oooo0o0000 BAR space oooo0o0000 ooooo0000 00000000 OO0000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 OO0000000 00000000 00000000 00000000 00000000 oooo0o0000 oooo0o0000 00000000 00000000 oooo00000 00000000 00000000 00000000 00000000 00000000 lt KOOOOOOOO xoo0000004 xooo00000s8 lt xooo0o0000Cc lt xoo0000010 lt xooo0o0o0o014 lt xooo0o0001s8 lt xooo0o0o0o01Cc lt xoo00000z2z0 lt xoo00000z4 xoo00000zs8 x
28. veform DEV 1 MyDevice1 KC3S 1000 UNIT 0 MYALAO ILA JTAG Chain DEV MyDeviceo KCFO8P Bus Signal 64 24 16 56 96 136 176 216 256 296 336 376 416 o DEV 1 MyDevice1 XC3510 e UNIT O MYALAO ILA app PI0O PI0O EP ep isa rd data Trigger Setup 1 Japp PI0 sdout_o Waveform X LE S fapp PIO 1a_o ES Signals DEV 1 UNIT 0 fapp P10 sa_o 7 Data Port app PIO sdout_en_o JappiPlOfla_o appiPlO PIO_EPiep_is app PIO ior_n_o JappiPlO sa_o JappiPlO sdout_o H 0 app PlO sa_os05 app PIO memr_n_o H 1 fapp PlO sa_os1 gt H 2 app PlO sa_o lt 25 H 3 JappiPlO sa_o lt 35 app PIO belk_o H 4 Japp PIO sa_o lt 45 H 5 JappiPlOlsa_o lt 55 fepp PI0 bale_o H 6 app PlO sa_o 6 H 7 fapp PlOfsa_os gt H 8 app PlO sa_o lt 8 gt H 9 Japp PIO sa_o lt 9 H 10 fappiPlO sa_o lt 1 H 11 fappiPlO sa_o lt H 12 fappiPIO sa_o lt 1 H 13 fappiPlO sa_o lt H 14 fappiPlO sa_o lt 1 H 15 appiPlO sa_os H 16 fapp PlO sa_o lt H 17 appiPlO sa_o lt 1 CH 18 appiPlO sa_o lt CH 19 appiPlO sa_o 1_ CH 20 appiPlOfla_os1 a gt a x o 0 app PIO iow_n_o fapp PIO memw_n_o Ci Ci Cc c Cc C Cc 0 Ci Cc C Cc C c C CI C C fim 3 Windows Explorer WA Outlook Express Arun GH ChipScope Pro Analyz Figure 3 IO Read Cycle iWave Systems Technologies Pvt Ltd Page 20 of 26 Wave Embedding Intelligence
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