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uPD75P0016 DS - Renesas Electronics

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1. Data Sheet U10328EJ3V3DS 23 NEC uPD75P0016 Memory bit manipulate 24 Mnemonic Operand mem bit Machine cycle Operation mem bit lt 1 Addressing area Skip condition fmem bit fmem bit 1 pmem L pmem7 2 L3 2 bit L1 0 lt 1 H mem bit mema o bit lt 1 mem bit mem bit 0 fmem bit fmem bit lt 0 pmem L 2 L3 2 bit L1 0 lt 0 H mem bit mema3 o bit lt 0 mem bit Skip if mem bit 1 mem bit 1 fmem bit Skip if fmem bit 1 fmem bit 1 pmem L Skip if omem7 2 L3 2 bit L1 0 1 pmem L 1 H mem bit Skip if H memsa o bit 1 H mem bit 1 mem bit mem bit 0 fmem bit Skip if fmem bit 0 pmem L Skip if omem7 2 L3 2 bit L1 0 0 fmem bit 0 pmem L 0 H mem bit Skip if H mema o bit 0 mem bit 0 SKTCLR fmem bit Skip if mem bit 0 Skip if fmem bit 1 and clear fmem bit 1 pmem L Skip if pmem 2 L3 2 bit L1 0 1 and clear pmem L 1 H mem bit Skip if H mems3 0 bit 1 and clear mem bit 1 CY fmem bit CY lt CY fmem bit CY pmem L CY H mem bit lt CY pmemz L3 2 bit L1 0 amp CY mem3 0 bi
2. Pin name Shared by Function circuit type Note 1 P13 External event pulse input to timer event counter P20 Timer event counter output P21 Timer counter output P22 Clock output P23 Outputs any frequency for buzzer or system clock trimming P01 Serial clock I O SO SBO 2 Serial data output Serial data bus I O SI SB1 Serial data input Serial data bus I O INT4 POO Edge triggered vectored interrupt input Detects both rising and falling edges INTO P10 Edge triggered vectored interrupt input With noise eliminator detected edge is selectable asynch selectable 10 can select noise elimination P11 circuit Asynch INT2 P12 Rising edge triggered testable input Asynch KRO KR3 P60 P63 Falling edge triggered testable input KR4 KR7 P70 P73 Falling edge triggered testable input X1 Ceramic crystal resonator connection for main system clock If using an external clock input it to X1 and input the X2 inverted clock to X2 XT1 Crystal resonator connection for subsystem clock If using an external clock input it to XT1 and input the invert XT2 ed clock to X2 XT1 can be used as a 1 bit test input RESET System reset input low level active MDO MD3 P30 P33 Mode selection for program memory PROM write verify DO D3 P40 P43 Data bus pin for program memory PROM write verify D4 D7 P50 P53 Note 2 Programmable voltage supply in program memory PROM write verify mode In normal operation mode
3. iii 4 2 BLOCK DIAGRAM Mc 6 3 gels 7 3 4 Port PIAS uisi u uu uu uuu UU UU AU Lud paa e ER 7 3 2 u ul uu uuu ullu u ara tic o aia C e Ao dS FIERE S Da rn Ck ERU SERA GERA 8 3 3 Circuits PINS 9 3 4 Handling Of Unused Pins u lll Uu Uu luu uu u uU UU UU nua ao co ER 11 4 SWITCHING BETWEEN MK AND MK II MODES 12 41 Differences between Mk Mode and Mk Mode 12 42 Setting of Stack Bank Selection SBS Register U uu uuu uuu uuu nnne 13 5 DIFFERENCES BETWEEN uPD75P0016 AND 750004 750006 AND 750008 14 6 MEMORY CONFIGURATION 15 7 INSTRUCTION gp 17 8 ONE TIME PROM PROGRAM MEMORY WRITE AND VERIFY 28 8 1 Operation Modes for Program Memory 28 8 2 Steps in Program Memory Write Operation 29 8 3 Steps in Program Memory Read Operation 30 8 4 One Time PROM Screening otra eu sive 31 9 ELECTRICAL S
4. HL A HL A 1 HL XA lt HL HL A HL A HL XA HL XA A mem mem lt A mem XA mem XA A reg XA rp A lt reg XA c rp reg1 A 1 XA A HL A HL HL then L L 1 A HL then Le L 1 A 1 XA HL XA HL regi lt m N N NI MH 1 lt XA A mem lt gt lt gt regi XA rp Table XA PCDE lt PC13 8 DE ROM reference XA PCXA XA lt PC13 8 XA ROM XA BCDE lt Note lt Note Note As for the B register only the lower 2 bits are valid Data Sheet U10328EJ3V3DS 21 NEC uPD75P0016 Mnemonic Operand Machine Operation Addressing Skip cycle area condition Bit transfer CY fmem bit CY lt fmem bit CY pmem L CY lt 2 L3 2 bit L1 0 CY mem bit CY lt H mems o bit fmem bit CY fmem bit lt CY pmem L CY pmem7 2 L3 2 bit L1 0 lt CY mem bit CY mems3 0 bit CY Operation A n4 AcA n4 XA n8 8 HL A
5. 7 Verify mode If write is verified go to step 8 and if write is not verified go back to steps 6 and 7 8 X number of write operations from steps 6 and 7 x 1 ms additional write 9 4 pulse inputs to the X1 pin updates increments 1 the program memory address 10 Repeat steps 6 to 9 until the last address is completed 11 Zero clear mode for program memory addresses 12 Apply 5 V to the and pins 13 Power supply OFF The following diagram illustrates steps 2 to 9 X repetitions Additional Write Verify write Address increment Ven ER VPP Vb VDD 1 KH p T v ve VDD VoD x1 04 50 07 53 MPO Macau ne MD1 P31 MD2 P32 Je a MD3 P33 Data Sheet U10328EJ3V3DS 29 NEC uPD75P0016 8 3 Steps in Program Memory Read Operation The uPD75P0016 read out the program memory contents via the following steps 1 Pull down unused pins to Vss via resistors Set the X1 pin to low 2 Apply 5 V to the and Vr pins 3 Wait 10 us 4 5 Zero clear mode for program memory addresses Apply 6 V power and 12 5 V to VPP pc Verify mode When a clock pulse is input to the X1 pin data output sequentially to one address at a time based on a cycle of four pulse inputs 3 Zero clear mode for program memory addresses Apply 5 power to the an
6. mode Voo 3 0 V 4 19 MHz Note 2 Voo 5 0 10 Note3 3 0 V 10 Note 4 Ipp2 22 pF HALT 5 0 V 10 mode 3 0 V 10 96 32 768 Low 3 0 10 96 Note 5 voltage 2 5 V 10 crystal oscillation Mode Note 6 Voo 3 0 Ta 25 G Low 3 0 10 96 dissipation mode Note Vpp 3 0 V Ta 25 1004 HALT Low Vo 3 0 V 10 96 mode voltage Von 25 V 10 mode Note 6 Voo 3 0 V Ta 25 Low current Voo 3 0 V 10 96 consumption mode Note 3 0 Ta 25 1005 XT1 oy Note8 5 0 V 10 96 STOP moda 3 0 V 10 96 Notes 1 The current flowing through the internal pull up resistor is not included 2 Including the case when the subsystem clock oscillates 3 When the device operates in high speed mode with the processor clock control register PCC set to 0011 4 When the device operates in low speed mode with PCC set to 0000 5 When the device operates on the subsystem clock with the system clock control register SCC set to 1001 and oscillation of the main system clock stopped 6 When the suboscillation circuit control register SOS is set to 0000 7 When SOS is set to 0010 8 When SOS is set to 00x1 and the suboscillation circuit feedback resistor is not used
7. Pull Up Resistor 10 P U R P ch IN OUT mo IN OUT 794 ve data 13 V output disable Input H P ch instruction P U R Nete Voltage limitation circuit 13 V Note Pull up resistor that operates only when an input instruction has been executed Current flows from to the pins when at low level Data Sheet U10328EJ3V3DS NEC uPD75P0016 3 4 Handling of Unused Pins Table 3 1 Handling of Unused Pins POO INT4 Recommended connection Connect to Vss or PO1 SCK P02 SO SBO Individually connect to Vss or via resistor POS SI SB1 Connect to Vss P10 INTO P12 INT2 P13 TIO Connect to Vss or VDD P20 PTOO P21 PTO1 P22 PCL P23 BUZ P30 MDO P33 MD3 Input mode individually connect to Vss or via resistor Output mode open P40 D0 P43 D3 P50 D4 P53 D7 Connect to Vss P60 KRO P63 KR3 P70 KR4 P73 KR7 P80 P81 Input mode individually connect Vss or via resistor Output mode open XT1 Note Connect to Vss XT 2Note Open VPP Make sure to connect directly to Note When the subsystem clock is not used set SOS 0 to 1 not to use the internal feedback resistor Data Sheet U10328EJ3V3DS 11 NEC uPD75P0016 4 SWITCHING BETWEEN AND MK II MODES Setting a stack ba
8. 5 SP lt SP 6 0 0 PC1s 12 lt SP 1 11 lt SP SP 3 SP 2 PSW lt SP 4 SP 5 SP lt SP 6 Note Shaded areas indicate support for the Mk mode only Other areas indicate support for the Mk mode only 26 Data Sheet U10328EJ3V3DS NEC uPD75P0016 Mnemonic Operand Machine Operation Addressing Skip cycle area condition Subroutine SP 1 SP 2 lt rp SP SP 2 stack control SP 1 lt MBS SP 2 RBS SP SP 2 SP 1 SP SP lt SP 2 MBS lt SP 1 RBS lt SP SP SP 2 IME IPS 3 1 Interrupt IExxx 1 IME IPS 3 0 control IExxx 0 PORTn lt PORTn PORTn PORTn PORTn 1 PORTn XA Set HALT Mode PCC 2 lt 1 Set STOP Mode PCC 3 lt 1 IN Note 1 A PORTn XA PORTn OUT Note 1 PORTn PORTn XA CPU control HALT STOP NOP SEL RBn MBn GETINote 2 taddr N m m N N NI NI No Operation 0 3 0 1 15 N 2 2 3 When using TBR instruction 1 lt taddr s o taddr 1 When using TCALL instruction SP 4 SP 1 SP 2 lt PC11 0 SP 3 lt MBE PCis 12 PC13 0 lt taddr s o taddr 1 SP 5 4 When using instruction other than Determined by TBR or TCA
9. INTCSI INTO P100 INT1 P110 INT2 P120 INT4 P00 KRO0 P60 KR7 P73 INTERRUPT CONTROL BUZ P23 0 PROGRAM MEMORY PROM 16384 x 8 BITS PCL P22 DECODE AND CONTROL 512 x 4 BITS CPU CLOCK XT1XT2 xi X2 Data Sheet U10328EJ3V3DS GENERAL REGISTER MEMORY RAM TES VPP Vss RESET BIT SEQ BUFFER 16 PORTO 4 PORT1 4 PORT2 4 4 0 PORT4 4 PORTS 4 PORT6 4 PORT7 4 8 2 PD75P0016 P10 P13 20 23 P30 MD0 P33 MD3 P40 D0 P43 D3 P50 D4 P53 D7 P60 P63 P70 P73 P80 P81 NEC uPD75P0016 3 PIN FUNCTIONS 3 1 Port Pins Pin name Shared by Function circuit type Note 1 INT4 This is a 4 bit input port PORTO lt B gt For to POS on chip pull up resistor connections P01 SCK are software specifiable in 3 bit units lt F gt A P02 SO SBO lt F gt B SI SB1 lt M gt C P10 INTO This is a 4 bit input port PORT1 lt B gt C On chip pull up resistor connections are software P11 INT1 specifiable in 4 bit units P10 INTO can select noise elimination circuit P12 INT2 P13 TIO P20 PTOO This is a 4 bit I O port PORT2 On chip pull up resistor connections are software P21 PTO1 specifiable in 4 bit units P22 PCL P23
10. P12 INT2 NC P72 KR6 1 P13 TIO P71 KR5 2 POO INT4 P70 KR4 3 1 5 P63 KR3 4 P02 SO SBO P62 KR2 5 P03 SI SB1 P61 KR1 6 P80 P60 KRO 7 P81 P53 D7 8 P30 MDO P52 D6 9 P31 MD1 P51 D5 10 P32 MD2 P50 D4 11 P33 MD3 NC 40 00 O Vss O XTi O XT2 RESET O X2 a a P42 D2 O O a Note Directly connect VPP to in the normal operation mode 4 Data Sheet U10328EJ3V3DS PIN IDENTIFICATIONS NEC uPD75P0016 SCK Serial Clock P10 P13 Port1 Sl Serial Input P20 P23 Port2 SO Serial Output P30 P33 Port3 SBO SB1 Serial Data Bus 0 1 P40 P43 Port4 RESET Reset P50 P53 Port5 TIO Timer Input 0 P60 P63 Port6 PTOO PTO1 Programmable Timer Output 0 1 P70 P73 Port7 BUZ Buzzer Clock P80 P81 Port8 PCL Programmable Clock KRO KR7 Key Return 0 7 INTO 1 4 External Vectored Interrupt 0 1 4 Positive Power Supply INT2 External Test Input 2 Vss Ground X1 X2 Main System Clock Oscillation 1 2 VPP Programming Power Supply XT1 XT2 Subsystem Clock Oscillation 1 2 NC No Connection MDO MD3 Mode Selection 0 3 00 07 Data Bus 0 7 Data Sheet U10328EJ3V3DS 5 NEC 2 BLOCK DIAGRAM BASIC INTERVAL TIMER WATCHDOG TIMER 8 BIT TIMER EVENT TIO P130 8 BIT TIMER COUNTER 1 PTO1 P210 V SB1 P03 o ns i CLOCKED 5 5 20 4 SERIAL SCK P010 INTERFACE
11. VPP supply current Cautions 1 Keep VPP to within 13 5 including overshoot 2 Apply Voo before VPP and turn it off after VPP AC Programming Characteristics Ta 25 5 C Vpp 6 0 0 25 VPP 12 5 0 3 Vss 0 Address setup time Note 2 vs MDO 1 MD1 setup time vs MDO 1 Data setup time vs MDO 1 Address hold time Note 2 vs MDO T Data hold time vs MDO T MDO gt data output float delay time VPP setup time vs MD3 1 setup time vs Initial program pulse width Additional program pulse width MDO setup time vs MD1 1 MDO gt data output delay time tov MD1 hold time vs MDO MD1 Vit tuin gt 50 us MD1 recovery time vs MDO 4 twin Program counter reset time tPcR X1 input high low level width txu tx X1 input frequency fx Initial mode set time t MD3 setup time vs MD1 1 hold time vs MD1 J MD3 setup time vs MDO 4 When program memory is read Address Note 2 _ data output delay time When program memory is read Address Note 2 _ data output hold time When program memory is read MD3 hold time vs MDO 7 When program memory is read MD3 J gt data output float delay time When program memory is read Notes 1 Symbol of corresponding uPD27C256A 2 The internal address signal is increme
12. BUZ P30 MDO This is a programmable 4 bit I O port PORTS Input and output can be specified in single bit P31 MD1 units On chip pull up resistor connections are software specifiable in 4 bit units P32 MD2 P33 MD3 P40 Note 2 DO This is an N ch open drain 4 bit I O port PORT4 High In the open drain mode withstands up to 13 V impedance P41 Note 2 D1 P42 Note 2 D2 p43 Note 2 D3 P50 Note 2 D4 This is an N ch open drain 4 bit I O port PORT5 High In the open drain mode withstands up to 13 V impedance P51 Note 2 D5 P52 Note 2 D6 P53 Note 2 D7 P60 This is a programmable 4 bit I O port PORTO Input and output can be specified in single bit units P61 On chip pull up resistor connections are software specifiable in 4 bit units P62 P63 P70 This is a 4 bit port PORT7 On chip pull up resistor connections are software P71 specifiable in 4 bit units P72 P73 P80 This is 2 bit I O PORTS On chip pull up resistor connections are software P81 specifiable in 2 bit units Notes 1 Circuit types enclosed in brackets indicate Schmitt triggered inputs 2 Low level input current leakage increases when input instructions or bit manipulation instructions are executed Data Sheet U10328EJ3V3DS 7 NEC uPD75P0016 3 2 Non port Pins
13. INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between MAX and MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between Vit MAX and MIN HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended
14. MAX 1524 0 600 T P L 13 2 0 520 M 0251808 0 01020 003 N 017 0 007 R 0 15 0 15 42 70 600 1 N EC 44 PIN PLASTIC 2210 PD75P0016 detail of lead end 5 LR Q NOTE ITEM MILLIMETERS INCHES Each lead centerline is located within 0 16 mm 0 007 inch of A 13 2 0 2 0 520 0 008 its true position T P at maximum material condition 50009 0 008 B 10 0 0 2 0 3941 7009 0 008 10 0 0 2 0 3947 0 009 0 008 D 13 2 0 2 0 520 09 009 F 1 0 0 039 G 1 0 0 039 0 08 0 003 0 371007 0 01510 004 0 16 0 007 J 0 8 T P 0 031 T P K 1 6 0 2 0 063 0 008 0 009 L 0 8 0 2 0 031 6008 0 06 0 002 0 17 19 08 0 007 75 003 N 0 10 0 004 P 2 7 0 106 Q 0 125 0 075 0 005 0 003 7 7 R 3 4 393 5 3 0 0 119 Data Sheet U10328EJ3V3DS S44GB 80 3BS 49 NEC uPD75P0016 12 RECOMMENDED SOLDERING CONDITIONS The 75 0016 should be soldered and mounted under the following recommended conditions For technical information see the following website Semiconductor Device Mount Manual http www necel com pkg en mount index html Table 12 1 Surface Mounting Type Soldering Conditions 1 uPD75P0016GB 3BS MTX 44 plastic 10 10 mm 0 8 mm pitch Recommended Soldering method
15. Soldering conditions Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max 35 00 3 at 210 C or higher Count Three times less VPS Package peak temperature 215 C Time 40 seconds max VP15 00 3 at 200 C or higher Count Three times or less Wave soldering Solder bath temperature 260 C max Time 10 seconds max Count WS60 00 1 Preheating temperature 120 C max package surface temperature Partial heating Pin temperature 350 C max Time 3 seconds max per pin row Caution Do not use different soldering methods together except for partial heating Remark Forsoldering methods and conditions other than those recommended above contact an NEC Electronics sales representative 2 uPD75P0016GB 3BS MTX A 44 pin plastic QFP 10 x 10 mm 0 8 mm pitch Recommended Soldering method Soldering conditions Condition Symbol Infrared reflow Package peak temperature 260 C Time 60 seconds max IR60 207 3 at 220 C or higher Count Three times or less Exposure limit 7 days after that prebake at 125 C for 20 to 72 hours Wave soldering For details contact an NEC Electronics sales representative Partial heating Pin temperature 350 C max Time 3 seconds max per pin row Note After opening the dry pack store it at 25 C or less and 65 RH or less for the allowable storage period Caution Do not use different soldering
16. Subsystem Clock Oscillation Circuit Characteristics Ta 40 to 85 C Recommended constants Parameter Conditions Resonator Crystal Oscillation frequency Voo 2 2 to 5 5 resonator fxr Note 1 Oscillation Voo 4 5 to 5 5 stabilization time Note 2 2 2 to 5 5 V External XT1 input frequency Voo 1 8 to 5 5 V clock fxr Note 1 XT1 input high Voo 1 8 to 5 5 V low level widths txrL Notes 1 The oscillation frequency shown above indicate characteristics of the oscillation circuit only For the instruction execution time refer to AC Characteristics 2 The oscillation stabilization time is the time required for oscillation to be stabilized after has been applied Caution When using the subsystem clock oscillation circuit wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influences due to wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with other signal lines Do not route the wiring in the vicinity of a line through which a high alternating current flows Always keep the ground point of the capacitor of the oscillation circuit at the same potential as Do not ground to a power supply pattern through which a high current flows Do not extract signals from the oscillation circuit The subsystem clock oscillation circuit has a low amplification factor to
17. connect directly to Apply 12 5 V in PROM write verify mode Positive power supply Ground potential Notes 1 Circuit types enclosed in brackets indicate Schmitt triggered inputs 2 During normal operation the VPP pin will not operate normally unless connected to Vpp pin 8 Data Sheet U10328EJ3V3DS EC PD75P0016 3 3 Circuits for Pins The I O circuits for the uPD75P0016 s pin are shown in schematic diagrams below Dat o Output H N ch disable 77 77 Push pull output that can be set to high impedance output CMOS standard input buffer with both P ch and N ch OFF P U R enable Data Type D Output disable O Schmitt trigger input with hysteresis characteristics lt P U R Pull Up Resistor P U R P U R q Meri gt I P ch Data IN OUT Type D O Output disable P U R Pull Up Resistor O lt Type B P U R Pull Up Resistor Continued Data Sheet U10328EJ3V3DS 9 NEC P U R enable H P ch output disable P e output disable N 77 P U R Pull Up Resistor pe IN OUT data 75 0016 P U R P U R enable data output disable DHE P U R
18. processing 8 bit data only even addresses can be specified Data Sheet U10328EJ3V3DS 17 NEC uPD75P0016 2 Operation legend A A register 4 bit accumulator B B register register D D register E register H H register L L register X register XA Register pair XA 8 bit accumulator BC Register pair BC DE Register pair DE HL Register pair HL XA Expansion register pair XA BC Expansion register pair BC DE Expansion register pair DE HL Expansion register pair HL PC Program counter SP Stack pointer CY Carry flag bit accumulator PSW Program status word MBE Memory bank enable flag RBE Register bank enable flag PORTn Port n 0 to 8 IME Interrupt master enable flag IPS Interrupt priority select register Interrupt enable flag RBS Register bank select register MBS Memory bank select register PCC Processor clock control register Delimiter for address and bit xx Contents of address xx xxH Hexadecimal data 18 Data Sheet U10328EJ3V3DS NEC uPD75P0016 3 Description of symbols used in addressing area MB MBE MBS MBS 0 1 15 MB 0 000 07 15 F80H FFFH Data memory addressing MBS 0 1 15 15 FFOH FFFH 15 FCOH FFFH 1 addr 0000H 3FFFH addr addr1 Cu
19. reduce current dissipation and is more susceptible to noise than the main system clock oscillation circuit Therefore exercise utmost care in wiring the subsystem clock oscillation circuit RECOMMENDED OSCILLATION CIRCUIT CONSTANT Main System Clock Ceramic Resonator Ta 40 to 85 Oscillation Circuit Oscillation Voltage Manufacturer Part Number Frequency Constant s TNI Remark MHz MIN MAX Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency If the application circuit requires accuracy of the oscillation frequency it is necessary to set the oscillation frequency of the resonator in the application circuit For this it is necessary to directly contact the manufacturer of the resonator being used 34 Data Sheet U10328EJ3V3DS NEC uPD75P0016 DC Characteristics Ta 40 to 85 C Vpp 2 2 to 5 5 Symbol Conditions Low level output current Per pin Total of all pins High level input voltage Ports 2 3 8 2 7 lt lt 5 5 V 2 2 lt Voo lt 2 7 V Ports 0 1 6 7 RESET 2 7 lt lt 5 5 V 2 2 lt Voo lt 2 7 V Ports 4 5 N ch open drain 2 7 lt lt 5 5 V 2 2 lt Voo lt 2 7 V X1 XT1 Low level input voltage Ports 2 5 8 2 7 lt Von lt 5 5 V 2 2 lt Voo lt 2 7 V
20. to Ver 6 2 Note2 3 5 2HD uS5A13IE75X IBM PC AT or compatible Refer to OS for IBM PCs 3 5 2HC uS7B13IE75X Notes 1 This is a service part provided for maintenance purpose only 2 Ver 5 00 and the upper versions of Ver 5 00 are provided with a task swapping function but it does not work with this software Remarks 1 Operation of the IE control program is guaranteed only on the above host machine and OSs 2 The 75000 subseries consists of the 750004 750006 750008 and 75P00016 56 Data Sheet U10328EJ3V3DS NEC uPD75P0016 OS for IBM PCs The following operating systems for the IBM PC are supported Version PC DOS Ver 3 1 to Ver 6 3 J6 1 VNote to J6 3 VNote MS DOS Ver 5 0 to Ver 6 22 5 0 VNote to J6 2 VNote IBM DOS J5 02 VNote Note Supports English version only Caution Ver 5 0 and above include a task swapping function but this software is not able to use that function Data Sheet U10328EJ3V3DS 57 NEC uPD75P0016 APPENDIX C RELATED DOCUMENTS Some of the following related documents are preliminary This document however is not indicated as preliminary Device Related Documents Document No Document name Japanese English 750004 750006 750008 750004 A 750006 A 750008 A U10738J U10738E Data Sheet uPD75P0016 Data Sheet U10328J This document uPD750008 User s Manual U10740J U10740E LP D750008 750108 Instruction
21. use the following coding format to describe operands corresponding to the instruction s operand representations for further description refer to the RA75X Assembler Package User s Manual EEU 1363 When there are several codes select and use just one Upper case letters and and symbols are key words that should be entered as they are For immediate data enter an appropriate numerical value or label Instead of mem fmem pmem bit etc a register flag symbol can be described as a label descriptor For further description refer to the 750008 User s Manual U10740E Labels that can be entered for and pmem are restricted Representation Coding format X D H L L XA BC DE HL BC DE HL BC DE XA BC DE HL XA BC DE HL BC DE HL XA BC DE HL HL HL DE DL DE DL 4 bit immediate data or label 8 bit immediate data or label 8 bit immediate data or label Note 2 bit immediate data or label FBOH FBFH FFOH FFFH immediate data or label FCOH FFFH immediate data or label 0000 3 immediate data or label 0000 3 immediate data or label Mk mode only 12 bit immediate data or label 11 bit immediate data or label 20H 7FH immediate data however 0 or label PORTO PORT8 IECSI IET1 IEO IE2 IE4 IEW RBO RB3 MBO MB1 MB15 Note When
22. 0016 Timing Test Points except X1 and XT1 inputs Vin MIN MIN Vi MAX Vi MAX MIN MIN MAX Vo MAX Clock timing 0 1 V X1 input 0 1V 0 1 V XT1 input 0 1V TIO timing TIO 40 Data Sheet U10328EJ3V3DS N EC PD75P0016 Serial Transfer Timing 3 wire serial I O mode SCK SI SO tkcy1 2 lt TKL1 2 gt lt TKH1 2 gt 2 wire serial I O mode SCK SBO 1 lt tkcy1 2 gt 4 151 1 2 gt 2 gt 1 tkso1 2 Data Sheet U10328EJ3V3DS 41 NEC uPD75P0016 Serial Transfer Timing Bus release signal transfer tsik3 4 lt Y SB0 1 Command signal transfer 4 KL3 4 4 tsik3 4 gt SBO 1 Interrupt input timing INTO 1 2 4 KRO 7 RESET input timing RESET 42 Data Sheet U10328EJ3V3DS NEC uPD75P0016 Data Retention Characteristics of Data Memory in STOP Mode and at Low Supply Voltage Ta 40 to 85 C Symbol Conditions Release signal setup time Oscillation stabilization Released by RESET wait time Note 1 Released by interrupt request Notes 1 The oscillation stabilization wait time is the time during which the CPU stops operating to prevent
23. 8EJ3V3DS 25 NEC uPD75P0016 Mnemonic Operand Machine Operation Addressing Skip cycle area condition Subroutine CALLA Note laddr1 SP 5 lt 0 0 PC13 12 stack control SP 6 SP 3 SP 4 lt PCi1 0 SP 2 x x MBE 1 lt SP lt SP 6 CALL Note SP 4 SP 1 SP 2 lt PC11 0 SP 3 MBE PC s 12 PC13 0 lt addr SP lt SP 4 SP 5 lt 0 0 SP 6 SP 3 SP 4 PC11 0 SP 2 x x MBE RBE 1 lt addr SP lt SP 6 CALLE Note SP 4 SP 1 SP 2 SP 3 lt MBE PCs 12 PC13 0 lt 000 faddr SP lt SP 4 SP 5 0 0 PCia 12 SP 6 SP 3 SP 4 PC11 0 SP 2 x x MBE PC13 0 lt 000 faddr SP lt SP 6 RET Note MBE 12 lt SP 1 PC11 0 SP SP 3 SP 2 SP lt SP 4 x x MBE RBE lt SP 4 0 0 lt SP 1 PC11 0 lt SP SP 3 SP 2 SP lt SP 6 RETS Note MBE PCis 12 lt SP 1 Unconditional PCi1 0 lt SP SP 3 SP 2 SP lt SP 4 then skip unconditionally x x MBE lt SP 4 0 0 PCis 12 lt SP 1 PCi1 0 lt SP SP 3 SP 2 SP lt SP 6 then skip unconditionally Note MBE PC s 12 lt SP 1 PC11 0 lt SP SP 3 SP 2 PSW lt SP 4 5
24. HL XA rp lt XA rp 1 1 lt rp 1 HL A HL CY rp lt CY 1 1 CY lt 1 CY A HL A A HL borrow XA rp lt XA borrow 1 rp lt 1 XA borrow A HL A CY A HL CY XA rp lt XA CY rp rp CY lt rp1 XA CY A n4 lt HL A A HL XA rp XA lt XA rp rp rp lt 1 XA A n4 4 A HL A A v HL XA rp XA lt XA v rp rp XA 1 lt 1 v n4 4 HL A A v HL XA rp XA lt XA v rp rp 1 lt 1 v XA 22 Data Sheet U10328EJ3V3DS NEC uPD75P0016 Mnemonic Operand Machine Operation Addressing Skip cycle area condition Accumulator CY lt Ao lt CY 1 manipulate Increment reg lt reg 1 decrement 1 lt 1 HL HL 1 lt mem 1 lt reg 1 lt 1 Skip if reg 4 Skip if HL Skip if A HL Skip if XA HL Skip if A reg Skip if XA rp Carry flag CY 1 manipulate CY 0 Skip if CY 1 CY CY
25. LL referenced Execute taddr taddr 1 instructions instruction When using TBR instruction PC13 0 lt taddr s o taddr 1 When using TCALL instruction SP 5 lt 0 0 PCis 12 SP 6 SP 3 SP 4 lt SP 2 x x MBE 1 lt taddr s o taddr 1 When using instruction other than Determined by TBR or TCALL referenced Execute taddr taddr 1 instructions instruction Notes 1 Before executing the IN or OUT instruction set MBE to 0 or 1 and set MBS to 15 2 TBR and TCALL are assembler directives for the instruction s table definitions 3 Shaded areas indicate support for the Mk II mode only Other areas indicate support for the Mk mode only Data Sheet U10328EJ3V3DS 27 NEC uPD75P0016 8 ONE TIME PROM PROGRAM MEMORY WRITE AND VERIFY The program memory in the wPD75P0016 is a 16384 x 8 bit electronic write enabled one time PROM The pins listed in the table below are used for this 5 write verify operations Clock input from the X1 pins is used instead of address input as a method for updating addresses Pin name Function VPP Pin usually Vpp where programming voltage is applied during program memory write verify X1 X2 Clock input pin for address updating during program memory write verify Input the X1 pin s inverted signal to the X2 pin 0 30 Operation mode selection pin for progra
26. List U11456J 75XL Series Selection Guide U10453J U10453E Development Tool Related Documents Document No Document name Japanese English 1 75000 R IE 75001 R User s Manual EEU 846 EEU 1416 IE 75300 R EM User s Manual U11354J U11354E Hardware EP 750008CU R User s Manual EEU 699 EEU 1317 EP 750008GB R User s Manual EEU 698 EEU 1305 PG 1500 User s Manual U11940J U11940E RA75X Assembler Package Operation U12622J U12622E User s Manual Language U12385J U12385E Software PG 1500 Controller User s Manual PC 9800 Series EEU 704 EEU 1291 MS DOS Base IBM PC Series EEU 5008 U10540E PC DOS Base Other Documents Document No Document name Japanese English SEMICONDUCTOR SELECTION GUIDE Products amp Package CD ROM X13769X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices Electrostatic C11892J C11892E Discharge ESD Guide for Products Related to Microcomputer Other Companies C11416J Caution The above related documents are subject to change without notice For design purpose be sure to use the latest documents 58 Data Sheet U10328EJ3V3DS NEC uPD75P0016 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT
27. PECIFICATIONS 2 32 10 CHARACTERISTIC CURVES REFERENCE VALUE J 46 11 PACKAGE DRAWINGS 48 12 RECOMMENDED SOLDERING CONDITIONS J J 50 APPENDIX A FUNCTION LIST OF uPD75008 750008 75P0016 52 APPENDIX B DEVELOPMENT TOOLS aa oca ur 54 APPENDIX C RELATED DOCUMENTS cereo icr SAN 58 Data Sheet U10328EJ3V3DS 3 NEC uPD75P0016 1 CONFIGURATION Top View e 42 pin plastic shrink DIP 600 mil 1 778 mm pitch uPD75P0016CU uPD75P0016CU A Xn o 1 O Vss XT2 o 2 o P40 D0 RESET o 3 P41 D1 X10 4 o P42 D2 X20 5 P43 D3 P33 MD3 o 6 o P50 D4 P32 MD2 o 7 P51 D5 P31 MD1 o 8 o P52 D6 P30 MDO o P53 D7 P81 o o P60 KRO P80 o o P61 KR1 P03 SI SB1 o o P62 KR2 PO2 SO SBO o o P63 KR3 1 5 o o P70 KR4 POO INT4 P71 KR5 P13 TIO o P72 KR6 P12 INT2 o o P73 KR7 P11 INT1 o o P20 PTOO P10 INTO o o P21 PTO1 VppNote o P22 PCL o P23 BUZ Note Directly connect VPP to Vpp in the normal operation mode e 44 pin plastic QFP 10 x 10 mm 0 8 mm pitch uPD75P0016GB 3BS MTX LPD75P0016GB 3BS MTX A O P73 KR7 O P20 PTOO O P21 PTO1 O P22 PCL P23 BUZ VppNote P10 INTO P11 INT1
28. Ports 0 1 6 7 RESET 2 7 lt Voo lt 5 5 V 2 2 lt lt 2 7 V X1 XT1 High level output voltage SCK SO ports 2 3 6 8 1 0 mA lt lt lt lt lt lt lt lt lt lt lt lt Low level output voltage SCK SO 15 mA Voo 4 5 to 5 5 V lt ports 2 8 lo 1 6 mA lt SBO SB1 N ch open drain Pull up resistor 2 1 High level input leakage current Vin Pins other than X1 and 1 X1 1 Vin 13 V Ports 4 5 N ch open drain Low level input leakage current Pins other than ports 4 5 X1 and 1 X1 1 Ports 4 5 N ch open drain When input instruction is not executed Ports 4 5 N ch open drain When input instruction is executed 5 0 3 0 High level output leakage current Vout SO SBO SB1 Ports 2 3 6 8 Vout 13 Ports 4 5 N ch open drain Low level output leakage current Vout 0 V Internal pull up resistor Vin OV_ Ports 0 3 6 8 except POO pin Data Sheet U10328EJ3V3DS 35 NEC PD75P0016 DC Characteristics Ta 40 to 85 C Vpp 2 2 to 5 5 Symbol Conditions Supply current Note 1 60MHzNote2 Vpp 5 0 V 10 Note 3 crystal oscillation 23 Note 4 3 0 V 10 96 1002 22 pF HALT 5 0 V
29. Sheet U10328EJ3V3DS 13 NEC uPD75P0016 5 DIFFERENCES BETWEEN uPD75P0016 AND 750004 750006 AND 750008 The uPD75P0016 replaces the internal mask ROM in the uPD750004 750006 and 750008 with a one time PROM and features expanded ROM capacity The uPD75P0016 s Mk I mode supports the Mk mode in the uPD750004 750006 and 750008 and the uPD75P0016 s Mk mode supports the Mk II mode in the uPD750004 750006 and 750008 Table 5 2 lists differences among the uPD75P0016 and the 750004 750006 and 750008 Be sure to check the differences between corresponding versions beforehand especially when a PROM version is used for debugging or prototype testing of application systems and later the corresponding mask ROM version is used for full scale production Please refer to the 750008 User s Manual U10740E for details on CPU functions and on chip hardware Table 5 1 Differences between 75 0016 and 750004 750006 and 750008 uPD750004 750006 uPD750008 1 75 0016 Program counter 12 bit 13 bit 14 bit Program memory bytes Mask ROM Mask ROM Mask ROM One time PROM 4096 6144 8192 16384 Data memory x 4 bits 512 Mask options Pull up resistor for Yes On chip not on chip can be specified No On chip not port 4 and port 5 possible Wait time when Yes 2 7 fx or 215 Note No fixed at 2 5 f Note RESET Feedback resistor Yes can select usable or unusable No usable for subsyste
30. Storage temperature 65 to 150 Caution If the absolute maximum rating of even one of the parameters is exceeded even momeniarily the quality of the product may be degraded The absolute maximum ratings are therefore values which when exceeded can cause the product to be damaged Be sure that these values are never exceeded when using the product Capacitance Ta 25 C 0 V Parameter Symbol Conditions MIN TYP MAX Unit Input capacitance f 1 MHz Output capacitance Pins other than tested pins 0 V I O capacitance 32 Data Sheet U10328EJ3V3DS NEC uPD75P0016 Main System Clock Oscillation Circuit Characteristics TA 40 to 85 C Resonator Ceramic resonator Recommended constants Parameter Oscillation frequency fx Note 1 Conditions 2 2 to 5 5 6 0 Note 2 Oscillation stabilization time Note 3 After Voo has reached MIN value of oscillation voltage range Vpp 2 2 to 5 5 V 6 0 Note 2 Crystal Oscillation frequency resonator fx Note 1 Oscillation Voo 4 5 to 5 5 V 10 stabilization time Note 3 2 2 to 5 5 V 30 External X1 input frequency 1 8 to 5 5 V 6 0 Note 4 clock fx Note 1 X1 input high low level widths tx txt 1 8 to 5 5 Notes 1 The oscillation frequency and X1 input frequency shown above indicate characteristics
31. To our customers Old Company Name in Catalogs and Other Documents On April 15 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 15 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 24 NC S AS 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is gra
32. a Sheet U10328EJ3V3DS 37 Serial Transfer Operation 2 wire and 3 wire serial I O modes internal clock output Ta 40 to 85 C Voo 2 2 to 5 5 V Parameter SCK cycle time Symbol Conditions 2 7 to 5 5 V NEC uPD75P0016 1300 3800 SCK high low level widths Voo 2 7 to 5 5 V 1 2 50 1 2 150 SINote 1 setup time vs SCK 1 Vpp 2 7 to 5 5 V 150 500 SINote 1 hold time vs SCK Vpp 2 7 to 5 5 V 400 SCK gt SONete 1 output delay time Notes 1 2 respectively indicate the load resistance and load capacitance of the SO output line 2 wire and 3 wire serial I O modes SCK external clock input Ta 40 to 85 Vpp 2 2 to 5 5 Parameter SCK cycle time Symbol Ri 1 kQNote 2 2 7 to 5 5 V Cu 100 pF Read as SBO or SB1 when using the 2 wire serial I O mode Conditions 2 7 to 5 5 V SCK high low level widths 2 7 to 5 5 V SINote 1 setup time vs SCK T Vpp 2 7 to 5 5 V SINote 1 hold time vs SCK 1 2 7 to 5 5 V SCK SONote 1 output delay time Notes 1 2 respectively indicate the load resistance and load capacitance of the SO output line 38 Ri 1 2 2 7 to 5 5 V Cu 100 pF Read as SBO SB1 when using the 2 wire se
33. age V 46 Data Sheet U10328EJ3V3DS NEC uPD75P0016 vs Main system clock 4 19 MHz crystal resonator Ta 25 C 5 0 PCC 0011 0010 0001 PCC 0000 Main system clock HALT mode 32 kHz oscillation 0 5 5 0 1 Subsystem clock operation mode SOS 1 0 o m o o 0 05 Subsystem clock HALT mode SOS 1 0 and main system clock STOP mode 32 kHz oscillation SOS 1 0 Subsystem clock HALT mode SOS 1 1 and main system clock STOP mode 32 kHz oscillation SOS 1 1 0 01 0 005 0 001 0 Supply Voltage Vpp Data Sheet U10328EJ3V3DS 47 NEC uPD75P0016 11 PACKAGE DRAWINGS 42 PLASTIC SHRINK DIP 600 mil NOTES 1 Each lead centerline is located within 0 17 mm 0 007 inch of its true position T P at maximum material condition 2 Item K to center of leads when formed parallel 48 Data Sheet U10328EJ3V3DS ITEM MILLIMETERS INCHES 39 13 1 541 MAX B 78 0 070 MAX C 1 778 T P 0 070 D 0 50 0 10 0 020 0 004 F 0 9 MIN 0 035 MIN G 3 2 03 0 126 0 012 H 0 51 MIN 0 020 MIN I 4 31 0 170 J 5 08 MAX 0 200
34. an be used when connected to a PG 1500 PA 75P0016GB PG 1500 controller Establishes serial and parallel connections between the PG 1500 and a host machine for host machine control of the PG 1500 Software Host machine OS Supply medium Part number product name PC 9800 Series MS DOS Ver 3 30 to Ver 6 2 Note 3 5 2HD uS5A13PG1500 IBM PC AT or compatible Refer to OS for IBM PCs 3 5 2HD uS7B13PG1500 Note Ver 5 00 and the upper versions of 5 00 are provided with a task swapping function but it does not work with this software Remark Operation of the PG 1500 controller is guaranteed only on the above host machine and OSs Data Sheet U10328EJ3V3DS 55 Debugging Tools In circuit emulators IE 75000 R and IE 75001 R are provided as program debugging tools for the 75 0016 Various system configurations using these in circuit emulators are listed below Hardware IE 75000 RNete 1 NEC uPD75P0016 The IE 75000 R is an in circuit emulator to be used for hardware and software debugging during development of application systems that use 75X or 75XL Series products For development ofthe 750008 subseries the IE 75000 R is used with a separately sold emulation board IE 75300 R EM and emulation probe EP 75008CU R or EP 75008GB R These products can be applied for highly efficient debugging when connected to a host machine and PROM p
35. aw of that country is prohibited The information in this document is current as of August 2005 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information e No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document e NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others e Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full res
36. bits i 000CH INTT1 start address higher 6 bits 2 Eu INTT1 start address lower 8 bits CALL addr laddri ete Branch call 0020H address Reference table for GETI instruction by GETI 007FH ee 0080H BR addr instruction relative branch address O7FFH 2222 Y 715 to 1 0800H 2 to 16 Y 1000H BRCB Icaddr instruction branch address 1FFFH 2000H BRCB Icaddr instruction branch address 3000H BRICB Icaddr instruction branch address 3FFFH Note be used only at Mk mode Remark For instructions other than those noted above the BR PCDE and instructions can be used to branch to addresses with changes in the PC s lower 8 bits only Data Sheet U10328EJ3V3DS 15 NEC uPD75P0016 Figure 6 2 Data Memory Map Data memory Memory bank 1 1 General 000H register area 32 x 4 020H Stack areaNete 256 x4 0 224 x 4 Data area static RAM 512 x 4 OFFH y 100H 1 256 4 1 Unimplemented F80H Peripheral hardware area 128 x 4 15 FFFH Note For the stack area one memory bank can be selected from memory bank 0 or 1 16 Data Sheet U10328EJ3V3DS NEC uPD75P0016 7 INSTRUCTION SET 1 Representation and coding formats for operands In the instruction s operand area
37. ction of on chip pull up resistor specifiable by software 18 N ch open drain I O Direct LED drive capability 13 V withstand voltage Total 34 4 channels 8 bit timer event counter 1 channel 8 bit timer counter 1 channel Basic interval timer watchdog timer 1 channel Watch timer 1 channel Serial interface 3 wire serial I O mode Switching of MSB LSB first 2 wire serial I O mode SBI mode Bit sequential buffer BSB 16 bits Clock output PCL 524 262 65 5 kHz main system clock at 4 19 MHz operation 750 375 93 8 kHz main system clock at 6 0 MHz operation Buzzer output BUZ 2 4 32 kHz main system clock at 4 19 MHz operation or subsystem clock at 32 768 kHz operation 2 93 5 86 46 9 kHz main system clock at 6 0 MHz operation Vectored interrupt External 3 Internal 4 Test input External 1 Internal 1 System clock oscillation circuit Main system clock oscillation ceramic crystal oscillation circuit Subsystem clock oscillation crystal oscillation circuit Standby function STOP HALT mode Operating ambient temperature Ta 40 to 85 C Supply voltage 2 2 to 5 5 Package 42 pin plastic shrink DIP 600 mil 1 778 mm pitch 44 pin plastic QFP 10 x 10 mm 0 8 mm pitch Data Sheet U10328EJ3V3DS NEC uPD75P0016 TABLE OF CONTENTS 1 PIN
38. d VPP pins 5 Power supply OFF The following diagram illustrates steps 2 to 7 Ho Aw WWW D4 P50 D7 P53 MDO P30 lt MD1 P31 4 D r_ A O l MD2 P32 MD3 P33 _ _ 30 Data Sheet U10328EJ3V3DS NEC uPD75P0016 8 4 One Time PROM Screening Due to its structure the one time PROM cannot be fully tested before shipment by NEC Electronics Therefore NEC Electronics recommends the screening process that is after the required data is written to the PROM and the PROM is stored under the high temperature conditions shown below the PROM should be verified Storage temperature Storage time 125 C 24 hours At present a fee is charged by NEC Electronics for one time PROM after programming imprinting screening and verify service for the QTOP Microcontroller For details contact an NEC Electronics sales representative Data Sheet U10328EJ3V3DS 31 NEC uPD75P0016 9 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Ta 25 C Symbol Conditions Ratings Supply voltage 0 3 to 7 0 PROM supply voltage 0 3 to 13 5 Input voltage Other than port 4 5 0 3 to 0 3 Port 4 5 N ch open drain 0 3 to 14 Output voltage 0 3 to 0 3 High level output current Per pin 10 Total of all pins 30 Low level output current Per pin 30 Total of all pins 220 Operating ambient 40 to 85 temperature
39. e equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under c
40. e matching each machine RA75X relocatable assembler Device file Host machine PC 9800 series MS DOS Ver 3 30 to Ver 6 2 Note Supply medium 3 5 2HD Part number product name LS5A13RA75X IBM PC AT or compatible Host machine PC 9800 series Refer to OS for IBM PCs 3 5 2HC MS DOS Ver 3 30 to Ver 6 2 Note Supply medium 3 5 2HD uS7B13RA75X Part number product name 95 130 750008 IBM PC AT or compatible Refer to OS for IBM PCs 3 5 2HC uS7B13DF750008 Note Ver 5 00 and the upper versions of Ver 5 00 are provided with a task swap function but it does not work with this software Remark The operation of the assembler and device file is guaranteed only on the above host machines and OSs 54 Data Sheet U10328EJ3V3DS NEC uPD75P0016 PROM Write Tools PG 1500 A stand alone system can be configured of a single chip microcomputer with on chip PROM when connected to an auxiliary board companion product and a programmer adapter separately sold Alternatively a PROM programmer can be operated on a host machine for programming In addition typical PROMs in capacities ranging from 256 K to 4 M bits can be programmed Hardware PA 75P008CU This is a PROM programmer adapter for the u PD75PO0016CU GB It can be used when connected to a PG 1500 This is a PROM programmer adapter for the uPD75P0016GB 3BS MTX It c
41. ecution of a subroutine call instruction increases by 1 per stack for the usable area compared to the Mk mode Furthermore when a CALL addr or CALLF faddr instruction is used each instruction takes another machine cycle Therefore when more importance is attached to RAM utilization or throughput than software compatibility use the Mk mode 12 Data Sheet U10328EJ3V3DS NEC uPD75P0016 4 2 Seiting of Stack Bank Selection SBS Register Use the stack bank selection register to switch between the Mk mode and the Mk Il mode Figure 4 1 shows the format for doing this The stack bank selection register is set using a 4 bit memory manipulation instruction When using the mode be sure to initialize the stack bank selection register to 100xB Note at the beginning of the program When using the Mk II mode be sure to initialize it to 000 Note Note Set the desired value for Figure 4 1 Format of Stack Bank Selection Register Address 3 2 1 0 Symbol F84H SBS3 SBS2 SBS1 SBSO SBS Stack area specification Memory bank 0 Memory bank 1 Setting prohibited 0 Be sure to set 0 for bit 2 Mode selection specification Mk mode Mk mode Caution SBS3is setto 1 after RESET input and consequently the CPU operates in the Mk mode When using instructions for the Mk mode set SBS3 to 0 to enter the Mk Il mode before using the instructions Data
42. ents due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an pull up power supply while the device is not powered The current injection that results from input of such a signal or pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device Data Sheet U10328EJ3V3DS 59 NEC uPD75P0016 Regional Information Some information contained in this document may vary from country to country Before using any NEC Electronics product in your application please contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors They will verify Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also
43. ertain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electro
44. lock at 4 19 MHz operation 750 375 93 8 kHz main system clock at 6 0 MHz operation BUZ output BUZ 52 2 kHz 2 4 32 kHz main system clock at 4 19 MHz operation 2 93 5 86 46 9 kHz main system clock at 6 0 MHz operation Data Sheet U10328EJ3V3DS NEC uPD75P0016 2 2 Item 75008 uPD750008 uPD75P0016 Serial interface Compatible with 3 kinds of mode 3 wire serial mode MSB LSB first can be switched 2 wire serial 1 mode SBI mode SOS register Feedback resistor On chip feedback resistor On chip cut flag SOS 0 specifiable by mask option Sub oscillator current None On chip cut flag SOS 1 Register bank selection register None Yes RBS Standby release by INTO Not possible Possible Vectored interrupt External 3 Internal 3 External 3 Internal 4 Processor clock control register PCC 0 2 can be used PCC 0 to can be used PCC Supply voltage Vpp 2 7 to 6 0 V 2 2 to 5 5 V Operating ambient temperature Ta 40 to 85 C Package 42 pin plastic shrink DIP 600 mil 1 778 mm pitch 44 pin plastic 10 x 10 mm 0 8 mm pitch Data Sheet U10328EJ3V3DS 53 NEC uPD75P0016 APPENDIX B DEVELOPMENT TOOLS The following development tools are provided for system development using the uPD75P0016 The 75XL series uses a common relocatable assembler in combination with a device fil
45. m clock Pin connection Pins 6 9 CU P33 P30 P33 MD3 P30 MDO Pins 23 26 GB Pin 20 CU Pin 38 GB Pins 34 37 CU P53 P50 P53 D7 P50 D4 Pins 8 11 GB Pins 38 41 CU P43 P40 43 03 40 00 Pins 13 16 GB Noise resistance and noise radiation may differ due to the different circuit complexities and mask layouts Note 275 21 8 ms 6 0 MHz 31 3 ms 4 19 MHz 25 5 46 ms 6 0 MHz 7 81 ms 4 19 MHz Caution Noise resistance and noise radiation are different in PROM version and mask ROM versions If using a mask ROM version instead of the PROM version for processes between prototype development and full production be sure to fully evaluate the CS of the mask ROM version not ES 14 Data Sheet U10328EJ3V3DS NEC uPD75P0016 6 MEMORY CONFIGURATION Figure 6 1 Program Memory Map 0000H Internal reset start address higher 6 bits Internal reset start address lower 8 bits 0002H INTBT INT4 start address higher 6 bits INTBT INT4 start address lower 8 bits CALLF faddr instruction 0004H INTO start address higher 6 bits entry address INTO start address lower 8 bits 0006H INT1 start address higher 6 bits INT1 start address lower 8 bits BRCB 0008H INTCSI start address higher 6 bits INTCSI start address lower 8 bits 000 INTTO start address higher 6 bits Branch address for INTTO start address lower 8
46. m memory write verify 00 40 03 43 lower 4 8 bit data pin for program memory write verify D4 P50 D7 P53 higher 4 VDD Pin where power supply voltage is applied Power voltage range for normal operation is 2 2 to 5 5 V Apply 6 0 V for program memory write verify Caution Pins not used for program memory write verify should be processed as follows All unused pins except XT2 Connect to Vss via a pull down resistor XT2 pin Leave open 8 1 Operation Modes for Program Memory Write Verify When 6 V is applied to the wPD75P0016 s pin and 12 5 V is applied to its VPP pin program write verify modes are in effect Furthermore the following detailed operation modes can be specified by setting pins MDO to MD3 as shown below Operation mode specification Operation mode MDO MD1 MD3 L Zero clear program memory address Write mode Verify mode Program inhibit mode Remark x L or H 28 Data Sheet U10328EJ3V3DS NEC uPD75P0016 8 2 Steps in Program Memory Write Operation High speed program memory write can be executed via the following steps 1 Pull down unused pins to Vss via resistors Set the X1 pin to low 2 Apply 5 V to and pins 3 Wait 10 us 4 Zero clear mode for program memory addresses 5 Apply 6 V to and 12 5 V power to VPP 6 Write data using 1 ms write mode
47. methods together except for partial heating Remarks 1 Products with A at the end of the part number are lead free products 2 For soldering methods and conditions other than those recommended above contact an NEC Electronics sales representative 50 Data Sheet U10328EJ3V3DS NEC uPD75P0016 Table 12 2 Insertion Type Soldering Conditions UPD75P0016CU 42 pin plastic shrink DIP 600 mil 1 778 mm pitch 75 0016 42 pin plastic shrink DIP 600 mil 1 778 mm pitch Soldering Method Soldering Conditions Wave soldering pin only Solder bath temperature 260 C max Time 10 seconds max Partial heating Pin temperature 300 C max Time 3 seconds max for each pin Caution Apply wave soldering to pins only See to it that the jet solder does contact with the chip directly Remarks 1 Products with at the end of the part number are lead free products 2 For soldering methods and conditions other than those recommended above contact an NEC Electronics sales representative Data Sheet U10328EJ3V3DS 51 NEC uPD75P0016 APPENDIX A FUNCTION LIST OF 75008 750008 75P0016 Program memory 75008 0000H 1F7FH 8064 x 8 bits 1 2 One time PROM 0000H 3FFFH 16384 x 8 bits 750008 Mask ROM 0000 1FFFH 8192 x 8 bits Data memory 000H 1FFH 512 x 4 bits CPU 75X Standard CPU 75XL CPU General register 4 bit
48. mil 1 778 mm pitch 16384 uPD75P0016CU A 42 pin plastic shrink DIP 600 mil 1 778 mm pitch 16384 uPD75P0016GB 3BS MTX 44 pin plastic QFP 10 x 10 mm 0 8 mm pitch 16384 uPD75P0016GB 3BS MTX A 44 pin plastic QFP 10 x 10 mm 0 8 mm pitch 16384 Caution On chip pull up resistors by mask option cannot be provided Remark Products with A at the end of the part number are lead free products The information in this document is subject to change without notice Before using this document please confirm that this is the latest version Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information Document No U10328EJ3V3DS00 3rd edition The mark shows major revised points Date Published August 2005 CP K Printed in Japan NEC Electronics Corporation 1995 FUNCTION LIST Item Function Instruction execution time NEC uPD75P0016 0 95 1 91 3 81 15 3 us main system clock at 4 19 MHz operation 0 67 1 33 2 67 10 7 main system clock at 6 0 MHz operation 122 us subsystem clock at 32 768 kHz operation On chip memory 16384 x 8 bits 512 x 4 bits General register In 4 bit operation 8 x 4 banks n 8 bit operation 4 x 4 banks port CMOS input 8 Connection of on chip pull up resistor specifiable by software 7 CMOS I O 18 Direct LED drive capability Conne
49. nics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics PANSER _ O MOS INTEGRATED CIRCUIT uPD75P0016 4 BIT SINGLE CHIP MICROCONTROLLER The uPD75P0016 replaces the uPD750008 s internal mask ROM with a one time PROM and features expanded ROM capacity Because the 75 0016 supports programming by users it is suitable for use in prototype testing for system development using the 750004 750006 or 750008 products and for use in small lot production Detailed information about product features and specifications can be found in the following document 1 0750008 User s Manual U10740E FEATURES Compatible with 750008 e Memory capacity PROM 16384 x 8 bits 512 x 4 bits Can operate in same power supply voltage as the mask ROM version 750008 Vpp 2 2 to 5 5 V e Supports QTOP microcontroller Remark QTOP Microcontroller is the general name for a total support service that includes imprinting marking screening and verifying one time PROM single chip microcontrollers offered by NEC Electronics ORDERING INFORMATION Part number Package ROM x 8 bits uPD75P0016CU 42 pin plastic shrink DIP 600
50. nk selection SBS register for the 75 0016 enables the program memory to be switched between the Mk mode and the Mk II mode This capability enables the evaluation of the 750004 750006 or 750008 using the uPD75P0016 When the SBS bit 3 is set to 1 sets Mk mode corresponds to Mk mode of uPD750004 750006 and 750008 When the SBS bit is set to 0 sets Mk Il mode corresponds to Mk II mode of 750004 750006 and 750008 4 1 Differences between Mk I Mode and Mk II Mode Table 4 1 lists the differences between the Mk mode and the Mk mode of the 75 0016 Table 4 1 Differences between Mk Mode and Mk II Mode Item Mk mode Mk mode Program counter PC13 0 Program memory bytes 16384 Data memory bits 512x4 Stack Stack bank Selectable from memory banks 0 and 1 Stack bytes 2 bytes 3 bytes Instruction BRA addr1 None Provided CALLA addr1 Instruction CALL addr 3 machine cycles 4 machine cycles execution time CALLF faddr 2 machine cycles 3 machine cycles Supported mask ROM versions and Mk mode of 750004 750006 and Mk mode of 750004 750006 and mode 750008 750008 Caution Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series This mode enhances the software compatibility with products which have more than 16K bytes When the Mk II mode is selected the number of stack bytes used in ex
51. nted by one at the rising edge of the fourth X1 input and is not connected to a pin 44 Data Sheet U10328EJ3V3DS NEC uPD75P0016 Program Memory Write Timing tves VPP 5 V Vop 1 us X1 D0 P40 D3 P43 D4 P50 D7 P53 Data input Data output t MD1 P31 MD2 P32 MD3 P33 Program Memory Read Timing tves Vi PP 00 40 03 43 D4 P50 D7 P53 MD1 P31 2 asB gt B T gt lt MD2 P32 r tussr s MD3 P33 Data Sheet U10328EJ3V3DS 45 NEC PD75P0016 10 CHARACTERISTICS CURVES REFERENCE VALUE loo vs Main system clock 6 0 MHz crystal resonator Ta 25 10 Ta 25 C 5 0 PCC 0011 PCC 0010 0001 0000 1 0 Main system clock HALT mode 32 kHz oscillation 0 5 2 01 Subsystem clock operation mode 8 SOS 1 0 gt 0 05 i Subsystem clock HALT mode SOS 1 0 and main system clock STOP mode 32 kHz oscillation SOS 1 0 Subsystem clock HALT mode SOS 1 1 and main system clock STOP mode 32 kHz oscillation SOS 1 1 0 01 0 005 0 001 0 Supply Volt
52. nted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document bu
53. of the oscillation circuit only For the instruction execution time refer to AC Characteristics 2 Ifthe oscillation frequency is 4 7 MHz lt fx lt 6 0 MHz at 2 2 V lt lt 2 7 V of the supply voltage please do not set processor clock control register PCC 0011 If PCC 0011 one machine cycle is less than 0 85 us falling short of the rated value of 0 85 us 3 The oscillation stablilization time is the time required for oscillation to be stabilized after has been applied or STOP mode has been released 4 If the X1 input frequency is 4 19 MHz lt fx lt 6 0 MHz at 1 8 V lt lt 2 7 V of the supply voltage please do not set PCC 0011 If PCC 0011 one machine cycle time is less than 0 95 us falling short of the rated value of 0 95 us Caution When using the main system clock oscillation circuit wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influences due to wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with other signal lines Do not route the wiring in the vicinity of a line through which a high alternating current flows Always keep the ground point of the capacitor of the oscillation circuit at the same potential as Do not ground to a power supply pattern through which a high current flows Do not extract signals from the oscillation circuit Data Sheet U10328EJ3V3DS 33 NEC PD75P0016
54. ponsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features e NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of an NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc
55. rial I O mode Data Sheet U10328EJ3V3DS NEC uPD75P0016 SBI mode internal clock output master Ta 40 to 85 C Voo 2 2 to 5 5 Symbol Conditions SCK cycle time Voo 2 7 to 5 5 V 1300 3800 SCK high low level widths Vpp 2 7 to 5 5 V 2 50 2 150 SBO 1 setup time Voo 2 7 to 5 5 V 150 vs SCK 500 SBO 1 hold time vs SCK 7 2 J gt SBO 1 output 1 Vpp2271055V 0 delay time 100 pF 0 SCK T gt SB0 11 SBO 1 1L gt SCK 1 SBO 1 low level width SBO 1 high level width Note Ri and respectively indicate the load resistance and load capacitance of the SBO and 1 output lines SBI mode SCK external clock input slave Ta 40 to 85 C 2 2 to 5 5 V Symbol Conditions SCK cycle time Voo 2 7 to 5 5 800 3200 SCK high low level widths Vpp 2 7 to 5 5 400 1600 SBO 1 setup time Voo 2 7 to 5 5 V 100 vs SCK 150 SBO 1 hold time SCK 1 tkcv4 2 SCK gt SBO 1 output R 21kQNete Vpp 271055V 0 delay time 100 pF 0 SCK T gt SBo 11 SB0 1 1 gt SCK 1 SBO 1 low level width SBO 1 high level width Note Ri and respectively indicate the load resistance and load capacitance of the SBO and 1 output lines Data Sheet U10328EJ3V3DS 39 NEC uPD75P
56. rogrammer The IE 75000 R can include a connected emulation board IE 75000 R EM IE 75001 R The IE 75001 R is an in circuit emulator to be used for hardware and software debugging during development of application systems that use 75X or 75XL Series products The IE 75001 R is used with a separately sold emulation board IE 75300 R EM and emulation probe EP 75008CU R or EP 75008GB R These products can be applied for highly efficient debugging when connected to a host machine and PROM programmer IE 75300 R EM This is an emulation board for evaluating application systems that use the 750008 subseries It is used in combination with the IE 75000 R or IE 75001 R in circuit emulator EP 75008CU R This is an emulation probe for the uPD75P0016CU When being used it is connected with the IE 75000 R or IE 75001 R and the IE 75300 R EM EP 75008GB R EV 9200G 44 This is an emulation probe for the uPD75P0016GB When being used it is connected with the IE 75000 R or IE 75001 R and the IE 75300 R EM It includes a 44 pin conversion socket EV 9200G 44 to facilitate connections with various target systems Software IE control program This program can control the IE 75000 R or IE 75001 R on a host machine when connected to the IE 75000 R or IE 75001 R via an RS 232 C or Centronics Host machine OS Supply medium Part number product name PC 9800 series MS DOS Ver 3 30
57. rrent PC 15 to Current PC 1 Current PC 2 to Current PC 16 caddr 0000 PC13 12 008 1000H 1FFFH PC13 12 018 or Program memory addressing 2000H 2FFFH PC13 12 10B or 3000 PC13 12 118 faddr 0000 07 taddr 0020H 007FH 0000 Mk mode only Remarks 1 MB indicates access enabled memory banks 2 In area 2 MB 0 for both MBE and MBS 3 In areas 4 and 5 MB 15 for both MBE and MBS 4 Areas 6 to 11 indicate corresponding address enabled areas Data Sheet U10328EJ3V3DS 19 NEC uPD75P0016 4 Description of machine cycles S indicates the number of machine cycles required for skipping of skip specified instructions The value of S varies as shown below s 8 0 e Skipped instruction is 1 byte or 2 byte instruction 5 1 e Skipped instruction is 3 byte instruction Note 5 2 Note 3 byie instructions BR addr addr1 CALL addr CALLA addr1 Caution The GETI instruction is skipped for one machine cycle One machine cycle equals one cycle of the CPU clock Use the PCC setting to select among four cycle times 20 Data Sheet U10328EJ3V3DS NEC uPD75P0016 Mnemonic Operand Machine Operation Addressing Skip cycle area condition A n4 String effect A regi n4 8 String effect A HL 8 String effect 2 8
58. s x 8 or 8 bits x 4 4 bits x 8 or 8 bits x 4 x 4 banks Instruction execution When main system clock is selected 0 95 1 91 15 3 us at 4 19 MHz operation 0 95 1 91 3 81 15 3 us at 4 19 MHz operation 0 67 1 33 2 67 10 7 us at 6 0 MHz operation time When subsystem clock is selected 122 us at 32 768 kHz operation Stack SBS register None SBS 3 1 Mk mode selected SBS 3 0 Mk II mode selected Yes Stack area 000H OFFH n00H nFFH n 0 1 Stack operation of subroutine call instruction 2 byte stack In Mk mode 2 byte stack In Mk mode 3 byte stack BRA addr1 CALLA addr1 Instructions MOVT XA BCDE MOVT XA BCXA BR BCDE BR BCXA Unusable Mk mode Unusable In Mk mode Usable Usable CALL 3 machine cycles Mk mode machine cycles Mk mode 4 machine cycles CALLF 2 machine cycles Mk mode 2 machine cycles Mk mode 3 machine cycles 3 channels Basic interval timer 1 channel 8 bit timer event counter 1 channel Watch timer 1 channel 4 channels Basic interval timer watchdog timer 1 channel 8 bit timer event counter 1 channel 8 bit timer counter 1 channel Watch timer 1 channel Clock output PCL 524 262 65 5 kHz main system clock at 4 19 MHz operation 524 262 65 5 kHz main system c
59. t CY fmem bit CY lt CY v fmem bit CY pmem L CY lt CY v 2 L3 2 bit L1 0 CY H mem bit CY lt CY v H mema o bit CY fmem bit CY lt CY v fmem bit CY pmem L CY CY v 2 L3 2 bit L1 0 CY H mem bit N N N N N NI NIN 1 CY CY v mems o bit Data Sheet U10328EJ3V3DS NEC uPD75P0016 Mnemonic Operand Machine Operation Addressing Skip cycle area condition PC13 0 addr Assembler selects the most appropriate instruction among the following BR addr BRCB caddr BR addr PC13 0 lt Assembler selects the most appropriate instruction among the following BRA addr1 BR addr BRCB caddr BR addr1 PC13 0 lt addr PC13 0 addr 13 0 lt addr1 PC13 0 PC13 8 DE PC13 0 PC13 8 XA PC13 0 lt BCDE Note 2 PC13 0 lt BCXA Note 2 PC13 0 lt laddr addr addr1 PCDE PCXA BCDE BCXA BRANote1 laggr1 BRCB vl NN IN wo PC13 0 lt PC13 12 caddr11 0 Notes 1 Shaded areas indicate support for the Mk II mode only Other areas indicate support for the Mk mode only 2 As for the B register only the lower 2 bits are valid Data Sheet U1032
60. t Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers offic
61. to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices 4 STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elem
62. traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life Support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above M8E 02 11 1
63. unstable operation when oscillation is started 2 Set by the basic interval timer mode register BTM Refer to the table below Wait Time fx 4 19 MHz 2 0 f approx 250 ms 2201 approx 175 ms 217 2151 213 f approx 1 95 ms 213 approx 1 37 ms approx 31 3 ms 217 fx approx 21 8 ms approx 7 81 ms 215 approx 5 46 ms Data retention timing when STOP mode released by RESET Internal reset operation HALT mode STOP mode e a Operation mode lt Data retention mode STOP instruction execution RESET Data retention timing standby release signal when STOP mode released by interrupt signal HALT mode STOP mode gt Operation mode lt Data retention mode STOP instruction execution Standby release signal interrupt request Data Sheet U10328EJ3V3DS 43 NEC uPD75P0016 DC Programming Characteristics TA 25 5 C 6 0 0 25 VPP 12 5 0 3 V Vss OV Symbol Conditions Input voltage high Other than X1 X2 pins X1 X2 Other than X1 X2 pins X1 X2 Vin Vit or Vin lou 2 1 mA Input voltage low Input leakage current Output voltage high Output voltage low lo 1 6 mA supply current MDO MD1 Vin
64. vary from country to country GLOBAL SUPPORT http www necel com en support support html NEC Electronics America Inc U S NEC Electronics Europe GmbH NEC Electronics Hong Kong Ltd Santa Clara California Duesseldorf Germany Hong Kong Tel 408 588 6000 Tel 0211 65030 Tel 2886 9318 800 366 9782 Sucursal en Espa a NEC Electronics Hong Kong Ltd Madrid Spain Seoul Branch Tel 091 504 27 87 Seoul Korea Tel 02 558 3737 Succursale Francaise V lizy Villacoublay France NEC Electronics Shanghai Ltd Tel 01 30 67 5800 Shanghai P R China 22 Tel 021 5888 5400 Filiale Italiana Milano Italy NEC Electronics Taiwan Ltd Tel 02 66 75 41 Taipei Taiwan Branch The Netherlands dels 022719 2977 Eindhoven The Netherlands Tel 040 265 40 10 NEC Electronics Singapore Pte Ltd Novena Square Singapore e Tyskland Filial Tel 6253 8311 Taeby Sweden Tel 08 63 87 200 e United Kingdom Branch Milton Keynes UK Tel 01908 691 133 J05 6 60 Data Sheet U10328EJ3V3DS NEC uPD75P0016 QTOP is a trademark of NEC Corporation MS DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and or other countries IBM DOS PC AT and PC DOS are trademarks of International Business Machines Corporation These commodities technology or software must be exported in accordance with the export administration regulations of the exporting country Diversion contrary to the l
65. x don t care 36 Data Sheet U10328EJ3V3DS NEC uPD75P0016 AC Characteristics Ta 40 to 85 C 2 2 to 5 5 Parameter Symbol Conditions CPU clock cycle Operates with with ceramic Voo 2 7 to 5 5 V main system oscillator or timeNote 1 clock crystal resonator ini i with external minimum instruction clock Vpp 2 7 to 5 5 V execution time 1 Voo 1 8 to 5 5 V machine cycle Operates with subsystem clock TIO input frequency fr 2 7 5 5 V TIO high low level tru 2 7 to 5 5 V widths Interrupt input high tint INTO low level widths tINTL INT1 2 4 KRO KR7 RESET low level width Notes 1 Thecycle time of the CPU clock is determined by the oscillation frequency of the connected resonator and external clock the system clock control register SCC and processor clock control register PCC The figure on the right shows the supply voltage vs cycle time tcy characteristics when the device operates with the main system clock 2 2tcy or 128 fx depending on the setting of the interrupt mode register IMO tcv vs with main system clock Cycle time tcy us 0 95 0 85 0 67 0 5 0 1 18222 273 4 5 5 5 6 Supply voltage V Remark Shaded area indicates operation when external clock is used Dat

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