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USER`S MANUAL

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1. 8 7 8 4 6 Two Channel DMA 8 7 8 4 7 Baud Rate Generator 8 7 8 4 8 Digital Phase Locked Loop 8 9 8 4 9 Clock Usage s enint 8 9 8 5 HDLC Operational Description sss 8 11 8 5 1 HDLC 8 11 8 5 2 HDLC Data Encoding Decoding 8 12 8 5 3 HDLC Data Setup and Hold Timing with 8 13 8 5 4 HDLC Transmitter 8 14 8 5 5 HDLC Receiver 8 16 8 5 6 Hardware Flow Control 8 17 8 5 7 Memory Data 8 19 8 5 8 Data Buffer Descriptor 8 20 8 6 Buffer Descriptor 8 21 8 6 1 Transmit Buffer 8 21 8 6 2 Receive Buffer 8 22 8 7 HDLC Special 2 8 24 8 7 1 HDLC Global Mode Register 00
2. 16 2Mx8 a AP mxs 22 21 22 2 Fass ee far zs 2 Fee fee far asm 22 2 22 2 Geel ja mm Peeper o gr 36 15 4 32 10 par 36 18 canon w 17 16 ss 14 se 1 2 19 1 15 14 eps ps 2 21 ve ve 7 6 15 1 1 10 1 20 9 17 15 1 zo 9 1 15 14 2 22 21 9 17 ss 14 1 r Fw pr 35 9 2 Fw 7 9 5 42 ELECTRONICS S3C2500B MEMORY CONTROLLER Table 5 22 SDRAM address mapping of 16 bit external bus SoRAM 7 4 21 mum ze ae ewm
3. 5 42 5 22 SDRAM address mapping of 16 bit external 5 43 5 23 Em 5 44 5 24 SDRAM Special 4 4 5 47 5 25 SDRAM Configuration 5 47 5 26 SDRAM Command Register a 5 50 5 27 SDRAM Refresh Timer 5 52 5 28 SDRAM Write Buffer Time out 5 53 6 1 Control Status Register 6 9 6 2 IICCON Register 6 9 6 3 NG BU BBgISIOI E 6 11 6 4 Register 6 11 6 5 dre pret 6 11 6 6 IICPS Register 6 11 6 7 6 12 6 8 IICCNT Register nennen 6 12 6 9 6 12 6 10 IICPND Register 7 nnne 6 12 S3C2500B RISC MICROCONTROLLER xxvii List of Tables continued Table Title Page Number Number 7 1 MAC Function Block 7 3 7 2 ETHERNET 0 Special 7 13 7 3 ETHERNET 1 Special
4. 21 Face xs e e s 7 s s 4 s 2 Face mew rla SDRAM Row Address AddrOut 14 0 Technology 2Mx8 20 19 18 i7 16 15 14 13 12 10 9 mmx 20 t9 18 i7 16 15 14 13 12111110 9 64M bit paras zz o fie par s e a o D 9 9 18 17 16 15 14 13 12 11 10 9 16 7 16 15 14 t3 t2 10 9 256M bit 21 20 23 22 19 16 17 16 15 14 13 12 11 10 9 Few ie par o De D n 12 11 10 9 NOTE AP Auto precharge enable and disable auto precharge function are controlled by this bit At precharge command this bit controls the all bank or specified bank to be precharged Shaded numbers leaf selection bits unused bits Pate far 2 z 5 zs 21 20 zz s 1 fe fot ELECTRONICS 5 43 MEMORY CONTROLLER S3C2500B 5 7 4 SDRAM COMMANDS The SDRAM controller issues specific commands to the SDRAM devices by encoding the nSDCS nSDRAS nSDCAS and nSDWE outputs Table 5 23 Lists all of the SDRAM commands understood by SDRA
5. Infra Red Receive Mode Frame Timing Diagram I O Port Mode Registers 1 2 Function Control Register 1 2 Function Control Register 2 Port Control Register for Port Control Register for External Port External Interrupt Clear Register Internal Interrupt Mode Register External Interrupt Mode Internal Interrupt Mask External Interrupt Mask Register Interrupt Priority 0024 Timer Output Signal 32 Bit Timer Block Diagram 000022 Timer Mode Timer Data Register S ienis naaa E AAEE EA Timer Counter Timer Interrupt Clear Watchdog Timer 2 272 BGA 2727 AN Package S3C2500B RISC MICROCONTROLLER Page Number xxiii List of Tables Table Title Page Number Number 1 1 S3C2500B
6. 3 7 3 4 2 Instruction Cycle 3 7 3 4 3 Assembler 3 8 S Data Pr ceSsSiNg MERE NCC p 3 9 ME cence 3 11 SIS Ac accu ex 3 12 3 5 3 Immediate Operand 5 3 16 3 0 Silicon cR cc DC 3 16 3 5 5 Using R15 as an 2 3 16 3 5 6 Tst and CMN 3 16 3 5 7 Instruction Cycle 3 17 3 6 8 Assembler 3 17 3 6 PSR Transfer MRS 1 nns 3 19 3 6 1 Operand 3 19 3 6 2 Reserved Bits 3 21 3 6 3 Instruction Cycle 3 21 3 6 4 Assembler 3 22 3 7 Multiply and Multiply Accumulate MUL MLA 3 23 cT 3 24 3 7 2 Instruction Cycle 3 24 3 7 3 Assembler Syntax 7 4 3 24 3 8 Multiply Long and Multiply Accumulate Long MULL 3 25 3
7. 12 2 Programmable Priority 12 5 Control nennen nennen nnns 12 11 Source Destination Address 12 12 Transfer Count Register nennen 12 13 Run Enable 12 14 Interrupt Pending nns 12 15 External Requests Single 12 18 External Requests Block 12 18 External Requests Detailed 12 19 Single and One Data Burst Mode 12 20 Single and Four Data Burst Mode Timing 22200 0000 12 21 Block and One Data Burst Mode 12 22 Block and Four Data Burst 0 2 12 23 Console UART Block 13 2 Console UART Control Register 13 6 Console UART Control 13 7 Console UART Status 13 10 Console UART Interrupt Enable 13 12 Console UART Transmit Data 13 13 Console UART Receive Data
8. nennen 3 41 3 20 Pre Increment 3 42 3 21 Post Decrement 0 3 42 3 22 Pre Decrement 0 3 43 3 23 Swap 3 47 3 24 Software Interrupt Instruction nnne 3 49 3 25 Coprocessor Data Operation Instruction 3 51 3 26 Coprocessor Data Transfer 3 53 3 27 Coprocessor Register Transfer 3 56 3 28 Undefined Instruction iio teen Rss rn 3 58 3 29 THUMB Instruction Set 3 64 S3C2500B RISC MICROCONTROLLER xvii List of Figures continued Figure Title Page Number Number 3 30 FORMAL Tugu a iii 3 67 3 31 genti 3 68 3 32 3 70 3 33 FORMAL HC 3 71 3 34 415 P Q 3 73 3 35 EM 3 76 3 36 ua M 3 77 3 37 FORMAL M 3 79 3 38 Formal uuu M 3 81 3 39 Foma mL 3 83 3 40 genre M 3 84 3 41 FORMAL 12 c EE
9. High speed UART nDSRO HUARTnDSROJ GPIO 31 High speed UART nDTRO HUARTnDTROJ GPIO 30 27 26 25 24 Timer Output TOUT 2 GPIO 24 23 Timer Output TOUT 1 GPIO 23 22 21 20 19 18 17 16 15 14 13 12 11 10 7 0 See Note on 15 1 Timer Output TOUT 0 GPIO 22 PIO 22 xGDMA Ack 3 GPIO 21 PIO 21 2 86 2 24 23 22 21 19 xGDMAAckit GPiofig 18 xGDMA Ack o GPIO 18 GPIOH8 17 xGDMAReq3 GPIOJIZ GPIO I7 16 xGDMAReq GPlO e 1 15 xGDMAReqi GPIO iS 1 14 j xGDMAReqo GPO4 1 13 External Interrupt xINT 5 GPIO 13 12 xINT 4 GPIO 12 11 jExemalinterruptxINT 3 GPIO 13 GPIO f 10 External Interrupt xINT 2 GPIO O GPIO t0 9 Exemallnterupt xINT 1 GPIO 8 ExtemalinemuptxINTJO GPlO S 70 Reseved External Interrupt SS eee a 0 2 G G G G G G G G G G G 1 G 1 G 1 G massa Figure 15 2 Function Control Register 1 IOPCON1 ELECTRONICS 15 5 VO PORTS S3C2500B 31 30 29 28 27 26 25 24 23 22 21 2019 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 PPD PPD PPD P EEE PP lt aout vat HDLC ch 2 TXC HTXC
10. sss nennen 3 4 3 3 ARM Data Processing 3 11 3 4 Incremental Cycle 3 17 3 5 Assembler Syntax Descriptions a 3 27 3 6 Addressing Mode 3 45 3 7 THUMB Instruction Set 3 65 3 8 Summary of Format 1 3 67 3 9 Summary of Format 2 3 68 3 10 Summary of Format 3 70 3 11 Summary of Format 4 3 71 3 12 Summary of Format 5 3 74 3 13 Summary of PC Relative Load 2 3 76 3 14 Summary of Format 7 nnns 3 77 3 15 Summary of format 8 nnns 3 79 3 16 Summary of Format 9 5 5 3 81 3 17 Half word Data Transfer Instructions 3 83 3 18 SP Relative Load Store Instructions 3 84 3 19 Load 3 85 3 20 The ADD SP 5 3 87 3 21 PUSH 3
11. 7 6 7 3 6 Flow Control BlOCK EP 7 7 7 3 7 Buffered DMA BDMA 7 7 7 4 Ethernet Controller Special 7 13 7 4 1 BDMA Relative Special Register 7 15 7 4 2 MAC Relative Special 2 7 24 7 5 Ethernet 5 7 37 7 5 1 Frame 7 37 7 5 2 The MII Station 7 45 7 5 3 Full Duplex Pause Operations 7 46 7 5 4 Error 7 48 7 5 5 Timing Parameters for 7 50 S3C2500B RISC MICROCONTROLLER Table of Contents Continued Chapter 8 HDLC Controller 8 1 SPA MI 8 2 8 3 Function 8 3 8 3 1 HDLC Frame nsns snnt 8 4 8 4 Protocol 5 8 6 8 4 1 Invalid 8 6 8 4 2 Zero Insertion and Zero 8 6 Su Me lero TER T A EA 8 6 8 4 4 Idle and Time Fill 8 8 6 6 25 FIFOs
12. Ic 5 3 5 4 Bus Interface Signals ctr ee tete Der epe epe e pee 5 5 NL LL HET 5 7 5 6 Ext Bank Controller 5 13 D631 uus m m 5 13 5 6 2 External Device 5 14 5 6 3 Ext I O Bank Controller Special 5 21 5 64 EET 5 29 5 38 5 ELEM 5 38 5 7 2 SDRAM Size and 5 39 5 5 Address Mapping MeL 5 42 5 7 4 SDRAM 5 44 5 7 5 External Data Bus 5 45 5 7 6 Merging Write 5 45 Df ef DL 5 45 5 78 Basic ma um as a 5 46 5 7 9 SDRAM Special nnn 5 47 5 7 10 SDRAM Controller 5 54 viii S3C2500B RISC MICROCONTROLLER Table of Contents Continued Chapter 6 2 Controller OOV CW or M LE LEE 6 1 21 ENDE Xr S 6 1 6 3 Functional Description
13. 4 3 4 5 External Address Translation 2 uu uuu la usus aknas qhasa ins Eae 4 3 4 6 Arbitration PEE 4 4 4 6 1 Problem Solvings with Programmable 4 7 4 7 Clock Conf Ura O riri a gt 4 9 4 8 ExternaliBus Masteris u i refe 4 14 4 9 System Configuration Special nnne nnns 4 15 4 9 1 System Configuration 4 16 4 9 2 Product Code and Revision Number 4 18 4 9 3 Clock Control Beglster m u eS Re E 4 19 4 9 4 Peripheral Clock Disable eene 4 20 4 9 5 Clock Stat s Register etre cdnnacdbneenaigusdanddeaqumnahguasanaadanensaaamiandienanannns 4 21 4 9 6 AHB Bus Master Priority 4 21 4 9 7 Core PLL Control 2 4 22 4 9 8 System Bus PLL Control 4 23 4 9 9 USB PLL Control Register 2 4 24 4 9 10 PHY PLL Control en nns 4 24 Chapter 5 Memory Controller SNO CC 5 1 SPACE Im 5 2 5 3
14. 10 20 10 14 USBDISCONN Register Description 10 20 10 15 USBEPOGSR REGISTE m 10 22 10 16 USBEPOCSR Register Description 10 22 10 17 10 25 10 18 USBEP1CSR Register 10 25 10 19 USBEP2CSR ESOISIOL 10 30 10 20 USBEP2CSR Register Description 10 30 S3C2500B RISC MICROCONTROLLER Table Number List of Tables continued Title Page Number USBEP3GSR R gisleru E i 10 35 USBEPSCSR Register 10 35 WSBEPACSR LL A A 10 40 USBEP4CSR Register n 10 40 USBWGEPO R6QISIGL irpo eere ERR 10 45 USBWCEPO Register 07 10 45 USBWGEPT R69OlSIet saa RR ERR 10 47 USBWCEP 1 Register Description 7 10 47 USBWGEPJ2 Re69lSIet Run 10 49 USBWCEP2 Register 0 10 49 WSBWCEPS REGISTE u s a e HE 10 51 USBWCEP3 Register 77 10 51 USBWGEPA RGOISIGL otro
15. 14 18 14 14 Typical Baud Rates Examples of High Speed 14 19 14 15 Beglslets S ua 14 20 14 16 HUGHAR2 REGISTOS 14 21 14 17 HUABB H69glSle s 14 22 14 18 HUAB T RBgISIGIS SC SED S ret ERR E 14 23 i S3C2500B RISC MICROCONTROLLER List of Tables Concluded Table Title Page Number Number 15 1 Port Special Registers 0 2202440445000000 0 0 nennen nnne 15 2 152 IOPMODET 2 HedglSte s eere 15 3 15 3 IOPGONA 2 ee pet Rota tee EHE EX E EA 15 5 15 4 IOPGDMA E 15 8 15 5 IOPEXTINI 15 9 15 6 Register esses 15 11 15 7 IOPDATAT 2 BeglSlBr e RR 3 7272222 15 12 15 8 IOPDEVI2SBIOgISIEIE S oret ce Een UH EUH 15 12 16 1 53 2500 Internal Interrupt Sources 16 2 16 2 S3C2500B External Interrupt 16 3 16 3 INTMOD EXTMOD 16 3 16 4 EXTMASK Register 002 16 5 16 5 Interrupt Priority 9 16 8 16 6 INTOFFSET FI
16. 13 14 Console UART Baud Rate Divisor Register 13 15 Console UART Baud Rate Generator 13 16 Console UART Control Character 1 13 17 Console UART Control Character 2 13 17 Interrupt Based Serial Transmit and Receive Timing Diagram 13 18 Serial Frame Timing Diagram Normal Console UART 13 19 Infra Red Transmit Mode Frame Timing 13 19 Infra Red Receive Mode Frame Timing 13 20 High Speed UART Block 14 2 High Speed UART Control 14 7 High Speed UART Status 14 12 High Speed UART Interrupt Enable 14 15 High Speed UART Transmit Buffer 14 16 High Speed UART Receive Buffer 14 17 High Speed UART Baud Rate Divisor
17. 10 4 10 3 4 Bit Stuffing NRZI 10 5 10 3 5 Bulk r 10 5 10 3 6 Control 10 6 10 3 7 Isochronous nnt 10 6 10 3 8 Interrupt 10 6 10 4 USB Block 10 7 10 4 1 USB Block Overview 10 7 10 4 2 SIE Serial Interface Engine nennen 10 7 10 5 USB Special 10 9 10 5 1 USB Function Address 10 10 10 5 2 USB Power Management 10 12 10 5 3 USB Interrupt 10 14 10 5 4 USB Interrupt Enable 10 17 10 5 5 USB Frame Number 10 19 10 5 6 USB Disconnect Timer 10 20 10 5 7 USB Endpoint 0 Common Status Register 001 00 10 22 10 5 8 USB Endpoint 1 Common Status Register 222244000000 10 25 10 5 9 USB Endpoint 2 Common Status 10 30 10 5 10 USB Endpoint 3 Co
18. 7 14 7 4 BDMATXCON 7 15 7 5 BDMA Transmit Control Register Description 7 15 7 6 BDMA RXCON 7 16 f BDMA Receive Control Register 7 16 7 8 BDMATXDBTR B69glSteT teer eir erase tee Rage ER P RR aad E 7 17 7 9 BDMA Transmit Buffer descriptor Start Address Register Description 7 17 7 10 BDMARXDPTR 2 7 17 7 11 BDMA Receive Buffer Descriptor Start Address Register Description 7 17 7 12 us orte tr ERR de RR E RENE NE Pe RUE 7 18 7 13 BDMA Transmit Buffer descriptor 7 18 7 14 BBXBEDONT BeglSIels s au s p ree EE INNEN rS 7 18 7 15 BDMA Receive Buffer descriptor 20020000 7 18 7 16 BMTXINTEN B6glsSter terrent negat E 7 19 7 17 BDMA MAC Transmit Interrupt Enable Register Description 7 19 7 18 BMTXSTAT ZBOgISI T metre ten sube e yy FERRE 7 20 7 19 BDMA MAC Transmit Interrupt Status Register Description 7 20 7 20 Register 7 21 7 21 BDMA MAC Receive Interrupt Enable Register
19. 7 21 7 22 BMRXSTAT RBO6 lSIQI rrr epe tee ERR Regu 7 22 7 23 BDMA MAC Receive Interrupt Status Register Description 7 22 7 24 BBMARBXLEN BGISIOE rore ed rri be eH RP HER 7 23 7 25 BDMA Receive Frame Size Register 7 23 7 26 CERIXSTA uu kus n RE TENERE E E MEE 7 24 7 27 Transmit Control Frame Register 7 24 7 28 MAGGON RBOUGISIGI rote Rpe RE 7 25 7 29 MAC Control Register Description 7 25 7 30 R e P rene E I E E MEE 7 26 7 31 CAM Control Register Description 7 26 7 32 EE 7 27 7 33 MAC Transmit Control Register Description 7 27 7 34 MACTXSTAT 7 28 7 35 MAC Transmit Status Register 7 28 7 36 MACRXCON 7 29 7 37 Receive Control Register 4 6 7 29 7 38 MACRXSTAT Register 7 30 7 39 Rec
20. 13 14 13 12 13 15 13 13 Typical Baud Rates Examples of Console 13 16 13 14 2 Beglsters e re Ep TOAN EANET xy Rp 13 17 14 1 High Speed UART 0 Special Registers 14 3 14 2 High Speed UART 1 Special Registers 14 3 14 3 High Speed UART Control Registers esses 14 4 14 4 High Speed UART Control Register Description 14 4 14 5 High Speed UART Status Registers 14 9 14 6 High Speed UART Status Register 14 9 14 7 Interrupt Enable 14 14 14 8 High Speed UART Interrupt Enable Register Description 14 14 14 9 PIDTEABUE RSgISLISr SZ 70 MN REPE 14 16 14 10 High Speed UART Transmit Register Description 14 16 14 11 HURXBU E R6GGISIGES 777727277222 14 17 14 12 High Speed UART Receive Register 14 17 14 13 HUBRDO and HUBRDO
21. 2 15 21 3 Interr pt dtencles 2 16 NAI C EE ER 2 16 2 13 Introduction for 9407 2 17 2 14 940 Block 2 18 2 15 About The ARM940T Programmer s 2 19 2 15 1 Data Abort oe e DO E RAM eat tau Sak 2 20 2 15 2 Instruction Set Extension 2 20 2 16 ARM940T CP15 2 21 2 16 1 CP15 Register Map 2 21 S3C2500B RISC MICROCONTROLLER Chapter 3 Instruction Set 3 1 Instruction Set 3 1 3 1 1 Format 3 1 3 1 2 Instruction 3 2 3 2 The Condition rnt 3 4 3 3 Branch and Exchange BX 3 5 3 3 1 Instruction Cycle 5 3 5 3 3 2 Assembler 3 5 3 3 3 Using R15 Operand enint 3 5 3 4 Branch and Branch with Link B nnne nnn nnn nnns 3 7 The Rink
22. 14 18 High Speed UART Baud Rate Generator 14 19 High Speed UART Control Character 1 14 20 High Speed UART Control Character 2 14 21 S3C2500B RISC MICROCONTROLLER Figure Number 16 1 16 5 17 1 17 7 19 1 List of Figures Concluded Title AutoBaud Boundary Regsiter High Speed UART AutoBaud Boundary Example AutoBaud Table Register Setting High Speed UART AutoBaud Boundary When Signal is Asserted During Transmit Operation When CTS Signal is Deasserted During Transmit Operation Normal Received Rx 220222 00 DCD Lost During Rx Data Interrupt Based Serial Transmit and Receive Timing Diagram DMA Based Serial I O Timing Diagram Tx Only DMA Based Serial I O Timing Diagram Rx Only Serial I O Frame Timing Diagram Normal High Speed UART Infra Red Transmit Mode Frame Timing
23. 3 90 3 35 Format 16 Conditional 3 91 3 3951 Operation AMNEM 3 91 3 35 2 Instruction Cycle Times 3 92 3 36 Format 17 Software 3 93 3 96 1 0 K en IT 3 93 3 36 2 Instruction Cycle Times 3 93 3 37 Format 18 Unconditional Branch 3 94 3 37 Operation 3 94 3 38 Format 19 Long Branch With 3 95 3 38 Oe zioni 3 95 3 38 2 Instruction Cycle 3 96 3 39 Instruction Set Examples 3 97 3 39 1 Multiplication by a Constant Using Shifts and 5 2 0 1 3 97 3 39 2 General Purpose Signed 3 98 3 39 3 Division by Constant a s 3 100 S3C2500B RISC MICROCONTROLLER vii Table of Contents Continued Chapter 4 System Configuration C MOI Ee ua au aaa Sasu aaa M 4 1 42 Eeat reS rus s n 4 1 4 3 Address EE 4 2 4 4 Remap of Memory 5
24. 9 17 2 TIC Bus Address 9 18 IOM2 Channel Transmit Data 9 19 IOM2 IC Channel Receive Data 9 19 S3C2500B RISC MICROCONTROLLER List of Figures continued Figure Title Page Number Number 9 13 2 Channel Transmit Data 9 20 9 14 IOM2 Channel Receive Data 9 20 9 15 IOM2 1 Channel Transmit Data 9 21 9 16 IOM2 1 Channel Receive Data 9 21 9 17 2 Monitor Channel Transmit Data 9 22 9 18 2 Monitor Channel Receive Data Register 9 22 9 19 TSA A Control 9 23 9 20 TSA Control 0422 nnn nnns nnns 9 24 9 21 TSA G Control 9 25 9 22 2 Strobe RegiSter iS 9 26 10 1 10 3 10 2 USB 00 10 4 10 3 VSB Frame Format E 10 5 10 4 USB Core Block 10 7 10 5 SIE BIOCKBIaQral
25. O wi vos Apps o jm Pow appre no i vpo o em ow o X es wwe 7 o ws powwe wo M go 1 wo xw m o W mos wes X o M e ez X o xaxo A 1 8 ELECTRONICS S3C2500B PRODUCT OVERVIEW 1 5 PIN ASSIGNMENT Continued Direction Pin Name Direction wea x o Ji eos 0 sep Jujur sep s Jujo w m bonm ur wwas ws pow wo mennenm o soxs o psoms O o w wsa e ws O1 o Jwuljvr 9 1 Ww eo 1 1 o 1 pss 1 9 Xs sos o 1 o xe psowemwes o ana os o o ELECTRONICS 1 9 PRODUCT OVERVIEW S3C2500B 1 5 PIN ASSIGNMENT Continued Dieeton
26. 11 8 3 0 Operand Registers 19 16 15 12 Source Destination Registers 20 Set Condition Code 0 Do not alter condition codes 1 Set condition codes 21 Accumulate 0 Multiply only 1 Multiply and accumulate 22 Unsigned 0 Unsigned 1 Signed 31 28 Condition Field Figure 3 13 Multiply Long Instructions The multiply forms UMULL and SMULL take two 32 bit numbers and multiply them to produce a 64 bit result of the form RdHi RdLo Rm Rs The lower 32 bits of the 64 bit result are written to RdLo the upper 32 bits of the result are written to RdHi The multiply accumulate forms UMLAL and SMLAL take two 32 bit numbers multiply them and add a 64 bit number to produce a 64 bit result of the form RdHi RdLo Rm Rs RdHi RdLo The lower 32 bits of the 64 bit number to add is read from RdLo The upper 32 bits of the 64 bit number to add is read from RdHi The lower 32 bits of the 64 bit result are written to RdLo The upper 32 bits of the 64 bit result are written to RdHi The UMULL and UMLAL instructions treat all of their operands as unsigned binary numbers and write an unsigned 64 bit result The SMULL and SMLAL instructions treat all of their operands as two s complement signed numbers and write a two s complement signed 64 bit result 3 8 1 OPERAND RESTRICTIONS R15 must not be used as an operand or as a destination register RdLo and Rm must all specify different register
27. neris aene nnn 6 2 DEO ufu elato ulace tu Gua M latu m ect 6 3 6 4 1 Basic 6 3 6 4 2 General Characteristics 6 4 54 Qha 6 4 6 44 Data ALLE Utt LE rcd d 6 5 6 4 5 Start And Stop 6 5 6 4 6 Data Trsansfer 6 6 G Sil Gr Special mam ta A sunu E a A ru Et a cU Ee cd 6 9 6 5 1 Control Status 6 9 6 5 2 Shift Buffer 6 11 6 5 3 Prescaler 6 11 6 5 4 Prescaler Counter 6 12 6 5 5 Interrupt Pending Register 6 12 Chapter 7 Ethernet Controller Vno I II REFERRED NEEDED CP E 7 1 VE ERE cuml mE RE 7 2 7 3 MAC Function 7 3 7 3 1 Media Independent Interface 7 3 7 3 2 Physical Layer Entity PHY 7 4 7 3 3 Buffered Interface 7 4 7 3 4 The MAC Transmitter 7 4 7 3 5 The MAC Receiver
28. 5 TIMERS clock disable TIMER4 clock disable 9 6 S 19 18 17 16 14 13 12 11 10 GDMA2 GDMA channel 2 clock disable GDMA1 GDMA channel 1 clock disable GDMAO 0 GDMA channel 0 clock disable 0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 V 4 20 ELECTRONICS S3C2500B SYSTEM CONFIGURATION 4 9 5 CLOCK STATUS REGISTER CLKST The operating frequency of the S3C2500B can be obtained by reading the CLKST register The CPU Freq field in CLKST 11 0 decodes the CPU FREQ 2 0 settings and the BUS Freq in CLKST 23 12 decodes the BUS FREQ 2 0 settings There clock modes in the S3C2500B fast mode sync mode and async mode In async mode there is no misinformation about the frequency But Care must be taken for the fastbus mode and sync mode In the fastbus mode the BUS frequency in the CLKST 23 12 should be ignored and the CPU frequency in the CLKST 11 0 should be taken for the BUS frequency because the CPU clock and system bus clock is the same In the sync mode the BUS frequency in the CLKST 23 12 should also be ignored and the half of the CPU frequency should be taken for the BUS frequency CLKST OxF00000010 R Clock Status register Read Only 4 Clock Mode 31 30 00 FastBus mode 01 Reserved 10 Reserved 11 Asynchronous BUS 23 12 System Bus Clock frequency CPU Freq 11 0 CPU C
29. 5 55 5 29 Single Write Operation 5 56 5 30 Burst Read Operation CAS Latency 2 5 57 5 31 Burst Read Operation CAS Latency 3 5 58 5 32 Burst Write Operation rrt ib ts e Rad ree x dade eua dS 5 59 6 1 6 1 6 2 Master Transmitter and Slave 6 3 6 3 Master Receiver and Slave 2 6 4 6 4 Start and Stop 6 5 6 5 Data Transfer 6 7 6 6 12 Control Status Register Gu a 6 10 7 1 Ethernet DIagrar Sau iiie a ua 7 1 7 2 Data Structure of Tx Buffer 0 7 10 7 3 Data Structure of Rx Buffer 7 11 7 4 Data Structure of the Receive 01 10 7 12 7 5 Fields of IEEE802 3 Ethernet 2 2 02 7 38 7 6 CSMA CD Transmit 7 40 7 7 Timing for Transmission without 7 41 7 8 Timing for Transmission with Collision in 7 42 7 9 Receiving Frame without 7 43 7 10 Receiving Frame with 2 9 7 43 7 11 CSMA CD Receive
30. Decoder Figure 13 1 Console UART Block Diagram 13 2 ELECTRONICS S3C2500B SERIAL CONSOLE UART 13 3 CONSOLE UART SPECIAL REGISTERS Table 13 1 Console UART Special Registers Overview Register Address RW Description Sie Reset Valu LCUTXBUF OxFO06000C W ConsoleUARTtransmidataregister B LCURXBUF OxFO060010 _R__ Console UART receive data register B ELECTRONICS 13 3 SERIAL CONSOLE UART S3C2500B 13 3 1 CONSOLE UART CONTROL REGISTERS Table 13 2 CUCON Registers I Register RW Desonpion Size Reset Vas CUCON OxF0060000 Console UART control register 0x00000000 Table 13 3 Console UART Control Register Description 1 0 Transmit mode This two bit value determines which function is currently able to TMODE write TX data to the Console UART transmit data register CUTXBUF 00 Disable TX mode 01 CPU request 10 Reserved 11 Reserved 3 2 Receive mode RMODE This two bit value determines which function is currently able to read RX data from the Console UART receive data register CURXBUF NOTE Changing these bits TMODE RMODE while transmitting receiving cause abnormal UART operation To prevent Tx Rx data from being lost changing these bits while transmitting receiving is strictly prohibited 00 Disable RX mode 01 CPU request 10 Reserved 11 Reserved 4 Send Break SBR Set this bit to one to cau
31. Rx Buffer Descriptor Pointer OxFFFFFFFF 31 30 29 28 27 26 25 0 l j U U 25 0 DMA Rx buffer descriptor pointer Figure 8 24 DMA Rx Buffer Descriptor Pointer 8 7 13 MAXIMUM FRAME LENGTH REGISTER The HDLC controller checks the length of an incoming frame against the user defined value in DMA mode If the frame received exceeds this register value the frame is discarded and FLV Frame Length Violated bit is set in the buffer descriptor belonging to that frame Table 8 21 HDMATXCNT and HDMARXCNT Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 15 0 Maximum frame length Figure 8 25 Maximum Frame Length Register 8 50 ELECTRONICS S3C2500B HDLC CONTROLLER 8 7 14 RECEIVE BUFFER SIZE REGISTER The Rx buffer size register contains the 16 bit user defined value This user defined count value determines the buffer size for one Buffer Descriptor If incoming HDLC frame is longer than the Rx buffer size register value the next buffer descriptor having the Rx buffer size value will be used Table 8 22 DMA Rx Buffer Size Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 15 0 Receive buffer size register Figure 8 26 DMA Receive Buffer Size Register 8 7 15 SYNCHRONIZATION REGISTER The HDLC synchronous register content will be sent during flag idle in HDLC mode In mark idle mode this register content can not used However in transparent mo
32. usu o 1 ve wmemon wo vr mo w Goo wo ve w 1 1 vo Go A o w sr i 1 12 ELECTRONICS S3C2500B PRODUCT OVERVIEW 1 6 SIGNAL DESCRIPTION Table 1 1 S3C2500B Signal Descriptions Group Pin Type PadType Description XCLK 1 Phic S3C2500B PLL Clock Source If CLKSEL is Low PLL output clock is used as the system clock If CLKSEL is high XCLK is used as the system clock HCLKO 1 phbst24 System clock output The internal system clock is monitored via HCLKO If SDRAM is used this clock should be used SDRAM clock CLKSEL 1 Phic Clock Select for CPU PLL and system PLL If CLKSEL is low CPU PLL clock is used as ARM940T source clock and system PLL clock is used system clock source depending on CLKMODf 1 0 If CLKSEL is high XCLK is used both clock sources See Figure 4 5 BUS FILTER 1 50 abb PLL filter pin for System PLL If the PLL is used 320pF capacitor should be connected between the pin and ground PHY FREQ 1 Phic PHY clock frequency select for PHY PLL 0 20MHz 1 25 2 PHY_CLKSEL 1 Phic Clock Select for PHY PLL If this pin is set to low the PHY PLL generates clock depending on PHY FREQ state The PHY PLL goes into power down mode with PHY CLKSEL set to high See Figure 4 5 PHY FILTER 1 50 abb PLL filter pin for PHY PLL If the PLL is used 320pF
33. 7 44 7 12 Control Frame enne nnne nnns 7 46 7 13 Timing Relationship of Transmission Signals at Mll 7 50 7 14 Timing Relationship of Reception Signals at 7 50 7 15 Sourced Q Su s a t RR sap enia 7 50 7 16 MDIO Sourced by 7 50 S3C2500B RISC MICROCONTROLLER xix Figure Number 8 1 8 2 8 3 O O O N List of Figures continued Title Page Number HDLC Module Block 8 3 Baud Rate Generator Block 8 7 DPLE Block DIagrarm eR ERR SER sasa saa 0 8 9 Clock Usage Method Diagram semen 8 9 Data Encoding Methods and Timing Diagrams 8 12 HDLC Data Setup and Timing 8 13 nCTS Already 8 17 CTS Lost During Transmission 8 17 CTS om 8 18 Transmit Buffer 8 21 Receive Buffer 8 22 Data Structure of the Receive Data 2 4 8 23 FIM DE EE 8 29 HADES Control REGISTE riss ann a E E A 8 34
34. Add lmm to base address in Rb Load bits 0 15 from the resulting address into Rd and set bits 16 31 to zero NOTE is a full 6 bit address but must be half word aligned ie with bit 0 set to 0 since the assembler places lmm gt gt 1 in the Offset5 field 3 29 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 17 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples STRH R6 R1 56 Store the lower 16 bits of R4 at the address formed by adding 56 R1 Note that the THUMB opcode will contain 28asthe Offset5 value LDRH 7 4 Load into the half word found at the address formed by adding 4 to R7 Note that the THUMB opcode will contain 2 as the Offset5 value ELECTRONICS 3 83 INSTRUCTION SET S3C2500B 3 30 FORMAT 11 SP RELATIVE LOAD STORE 15 14 13 7 0 12 11 10 8 po o s e O 7 0 Immediate Value 10 8 Destination Register 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 3 40 Format 11 3 30 1 OPERATION The instructions in this group perform an SP relative load or store The THUMB assembler syntax is shown in the following table Table 3 18 SP Relative Load Store Instructions THUMB Assembler ARM Equivalent Action STR Rd SP STR Rd R13 Imm Add unsigned offset 255 words 1020 byte
35. 8 13 8 4 HDLC Channel A Special 8 24 8 5 HDLC Channel B Special 8 25 8 6 HDLC Channel C Special 8 26 8 7 HMODEA HMODEB and HMODEC 8 27 8 8 HMODE Register 8 27 8 9 HCONA HCONB and HCONC 8 30 8 10 HCON Register 8 30 8 11 HSTATA HSTATB HSTATC 8 36 8 12 HSTAT Register 8 37 8 13 HINTENA HINTENB and HINTENC 8 42 8 14 HINTEN Register 8 42 8 15 HBRGTCA and HBRGTCB 8 46 8 16 HPRMBA HPRMBB Register 8 47 8 17 Preamble Reference 2 8 47 8 18 HSADR and HMASK 8 48 8 19 DMA Tx Buffer Descriptor Pointer 8 49 8 20 DMA Rx Buffer Descriptor Pointer Registers 8 50 8 21 HDMATXCNT and HDMARXONT 8 50 8 22 DMA Rx Buffer Size Register 8 51 8 23 Synchronizat
36. 3 85 3 42 FORMAL u 3 87 3 43 Pormal uuu L 3 88 3 44 3 90 3 45 3 91 3 46 AA 3 93 3 47 FOMMAL 18 r 3 94 3 48 72 3 95 4 1 S3C2500B Address map after 4 2 4 2 External Address Bus 4 4 4 3 Priority Groups of 53 2500 4 5 4 4 AHB Programmable Priority 4 6 4 5 Shows the Clock Generation Logic of the 53 25008 4 14 4 6 Divided System Clock Timing 4 19 5 1 Memory Bank Address 5 4 5 2 Memory Controller Bus 5 6 5 3 8 bit ROM SRAM and Flash Basic Connection 5 14 5 4 8 bit ROM SRAM and Flash Basic Connection 8 bit Memory 2 5 15 5 5 16 bit SRAM Basic 5 16 5 6 16 bit ROM and Flash Basic Connection 5 17 5 7 16 bit ROM Basic Connection 2 5 18 5 8 16 bit SRAM Basic Connection 2 5 19 5 9 ROM amp SRAM with Muxed Address amp Data Bus 5 20 5
37. Long enable MLongEn Set this bit to receive frames with lengths greater than 1518 bytes Short enable MShortEn Set this bit to receive frames with lengths less than 64 bytes 4 Strip CRC value MStripCRC Set this bit to check the CRC and then strip it from the message 5 Pass control frame Set this bit to enable the passing of control frames to a MAC MPassCtl client 6 Ignore CRC value Set this bit to disable CRC value checking 817 Not applicable ELECTRONICS 7 29 ETHERNET CONTROLLER S3C2500B 7 4 2 7 MAC Receive Status Register A receive status flag is set in the MAC receive status register MACRXSTAT whenever the corresponding event occurs When a status flag is set it remains set until another packet arrives or until software writes a 1 to the flag to clear the status bit If the corresponding interrupt enable bit in the receive control register is set an interrupt is generated whenever a status flag is set A MAC receive parity error sets RxParErr and also clears the MRxEn bit if an interrupt is enabled Table 7 38 MACRXSTAT Register MACRXSTATB 0xF00D0014 0 00000000 Table 7 39 MAC Receive Status Register Description 7 0 s o These bits are equal to the BMRXSTAT 7 0 Short Frame Error MRxShort This bit is set if the frame was received with short frame 9 Receive 10 Mb s status This bit is set to 1 if the frame was received over the 7 wire MRx10S
38. 18 Enable BDMA Rx maximum This bit enables BRxMSO interrupt size over interrupt BRxMSOIE 19 Enable BDMA Rx This bit enables BRxFull interrupt buffer BRxBUFF Overflow Interrupt BRxFulllE 20 Enable BDMA Rx early This bit enables BRxEarly interrupt notification interrupt BRxEarlylE 81 21 Not applicable ELECTRONICS 7 21 ETHERNET CONTROLLER S3C2500B 7 4 1 10 BDMA MAC Receive Interrupt Status Register Table 7 22 BMRXSTAT Register BMRXSTATA OxF00A0024 BDMA MAC Rx Interrupt Status register 0x00000000 BMRXSTATB 0 00 0024 BDMA MAC Rx Interrupt Status register 0x00000000 Table 7 23 BDMA MAC Receive Interrupt Status Register Description Missed roll MissRoll This bit is set when the missed error counter rolls over Whenever this bit is set the MISSCNT register should be read to clear this bit Writing by ARM doesn t affect the Rx interrupt Alignment error AlignErr This bit is set if the frame length in bits is not a multiple of eight and the CRC is invalid For the MAC Rx control mode of MlgnoreCRC this bit is not set CRC error CRCErr This bit is set if the CRC at the end of frame did not match the computed value or else the PHY asserted RX_ER during frame reception Overflow error Overflow This bit is set if the MAC RxFIFO was full when it needed to store a received byte Long error LongErr This bit is set if the MAC received a frame longer than 1518 bytes It is not set if the
39. COL 0 phis Collision Detected Collision Detected for 10M COL is asserted asynchronously with minimum delay from the start of a collision on the medium in mode COL 10M is asserted when a 10 Mbit s PHY detects a collision S3C2500B PRODUCT OVERVIEW Table 1 1 S3C2500B Signal Descriptions Continue Group PinName Pin Type PadType 7 Deseripion Ethernet TX EN 1 phob4 Transmit Enable Transmit Enable for 10M ControllerO TX EN provides precise framing for the data 18 carried on TXD 3 0 This pin is active during the clock periods in which TXD 3 0 contains valid data to be transmitted from the preamble stage through CRC When the controller is ready to transfer data it asserts TXEN 10M TX ERR 0 1 phob4 Transmit Error Packet Compression Enable PCOMP 10M for 10M TX ERR is driven synchronously to TX CLK and sampled continuously by the Physical Layer Entity PHY If asserted for one or more TX CLK periods TX ERR causes the PHY to emit one or more symbols which are not part of the valid data or delimiter set located somewhere in the frame that is being transmitted PCOMP 10M is asserted immediately after the packet s DA field is received PCOMP 10M is used with the Management Bus of the DP83950 Repeater Interface Controller from National Semiconductor The MAC can be programmed to assert PCOMP if there is a CAM match or if there is not a match The RIC Repeater Interface Controller uses this s
40. Devco ONTO onti owre Deven s o o oo e o o 402955 o7 e oo 599415 o s e o erm os took o 500 OO 95340 47 16 o o 8353 29 5 o 4096000 24 ook 10 6000000 OO o 614400 24 7 o 500 31 2 o 8192000 24 tooook o 942859 57 1 12288000 229 8 8 ELECTRONICS S3C2500B HDLC CONTROLLER 8 4 8 DIGITAL PHASE LOCKED LOOP DPLL The HDLC module contains a digital phase locked loop DPLL function to recover clock information from a data stream with NRZI or FM encoding The DPLL is driven by a clock that is normally 32 NRZI or 16 FM times the data rate The DPLL uses this clock along with the data stream to construct the clock This clock may then be used as the receive clock the transmit clock or both Figure 8 3 shows a block diagram of the digital phase locked loop It consists of a 5 bit counter an edge detector and a pair of output decoders Receive Clock Count Modifier Decoder dplloutR Detector Transmit clock 5 Counter Decoder dplloutT BRGOUT1 BRGOUT2 gt HMODE 18 16 8 4 9 CLOCK USAGE METHOD Figure 8 3 DPLL Block Diagram BRGOUT1 DPLLOUTT RxC gt Baud Rate DPLL MCLK2 Generator DPLLORTR
41. Note effect of PC offset B jimmy Branch to jimmy m Note that the THUMB opcode will contain the number of half words to offset Jimmy Must be half word aligned 3 94 ELECTRONICS S3C2500B INSTRUCTION SET 3 38 FORMAT 19 LONG BRANCH WITH LINK 15 14 13 10 0 12 11 10 0 Long Branch and Link Offset High Low 11 Low High Offset Bit 0 Offset high 1 Offset low Figure 3 48 Format 19 3 38 1 OPERATION This format specifies a long branch with link The assembler splits the 23 bit two s complement half word offset specified by the label into two 11 bit halves ignoring bit 0 which must be 0 and creates two THUMB instructions 3 38 1 1 Instruction 1 H 0 In the first instruction the Offset field contains the upper 11 bits of the target address This is shifted left by 12 bits and added to the current PC address The resulting address is placed in LR 3 38 1 2 Instruction 2 1 In the second instruction the Offset field contains an 11 bit representation lower half of the target address This is shifted left by 1 bit and added to LR LR which now contains the full 23 bit address is placed in PC the address of the instruction following the BL is placed in LR and bit of LR is set The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction ELECTRONICS 3 95 INSTRUCTION SET S3C2500B 3 38 2
42. Oses Load store halfword 4 5 2 SP relative load store 1 Word8 Load address 1 0 1 1 0 0 0 0 6 Add offset to stack pointer Push pop register 20000 0 Multiple load store 111901 Sotses Conditionat branch 11 Software interrupt Offset1 1 Unconditional branch DIEN Long branch with link 15 14 13 12 11 109 8 7 6 5 4 3 Figure 3 29 THUMB Instruction Set Formats 3 64 ELECTRONICS S3C2500B INSTRUCTION SET 3 19 2 OPCODE SUMMARY The following table summarises the THUMB instruction set For further information about a particular instruction please refer to the sections listed in the right most column Table 3 7 THUMB Instruction Set Opcodes mM Dno pp wer Operand Operand Codes Set me J v AND AND V _ v B QUnond olbranh y Bo 7 Cond ondbranh y v v Branch and exchange lt lt lt lt BL BX MN 5 MVN NEG lt BS PUSH POR Rei Move negative register ELECTRONICS 3 65 INSTRUCTION SET S3C2500B Table 3 7 THUMB Instruction Set Opcodes Continued per puer Operand Operand Codes Set SC Subtractwitheary sma Swempe v Store word Store half word Software interrupt
43. 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset bofore transfer 31 28 Condition Field Figure 3 26 Coprocessor Data Transfer Instructions 3 15 1 THE COPROCESSOR FIELDS The CP field is used to identify the coprocessor which is required to supply or accept the data and a coprocessor will only respond if its number matches the contents of this field The CRd field and the N bit contain information for the coprocessor which may be interpreted in different ways by different coprocessors but by convention CRd is the register to be transferred or the first register where more than is to be transferred and the bit is used to choose of two transfer length options For instance 0 could select the transfer of a single register and 1 could select the transfer of all the registers for context switching ELECTRONICS 3 53 INSTRUCTION SET S3C2500B 3 15 2 ADDRESSING MODES ARM9TDMI is responsible for providing the address used by the memory system for the transfer and the addressing modes available are a subset of those used in single data transfer instructions Note however that the immediate offsets are 8 bits wide and specify word offsets for coprocessor data transfers whereas they are 12 bits wide and specify byte offsets for single data transfers The 8 bit unsigned immediate offset is shifted left 2 bits and either added to U 1 or subtracted from U 0 the base
44. 7 5 Reserved 8 SUSpend Interrupt SUSI 0 No suspend interrupt 1 Suspend interrupt generated 9 RESume Interrupt RESI 0 No resume interrupt 1 Resume interrupt generated 10 ReSeT Interrupt RSTI 0 No reset interrupt 1 Reset interrupt generated 11 DISConnect Interrput DISCI 0 No interrupt 1 Interrupt generated after disconnect operation 31 12 Reserved Figure 10 8 USBINTR Register 10 16 ELECTRONICS S3C2500B USB CONTROLLER 10 5 4 USB INTERRUPT ENABLE REGISTER Corresponding to each USB Interrupt Register USBINTR there is an interrupt enable bit at USB Interrupt Enable Register USBINTRE By default all interrupts are disbled Table 10 8 USBINTRE Register USBINTRE USB interrupt enable register 0x0000041f Table 10 9 USBINTRE Register Description EPO Interrupt If bit 0 the corresponding interrupt is disabled ENable EP4 If bit 1 the corresponding interrupt is enabled Interrupt ENable EPOIEN EPAIEN SUSpend Interrupt If bit 0 the corresponding interrupt is disabled ENable SUSIEN If bit 1 the corresponding interrupt is enabled Reserved 10 ReSeT Interrupt R W If bit 0 the corresponding interrupt is disabled ENable RSTIEN If bit 1 the corresponding interrupt is enabled 11 DISConnect R W If bit 0 the corresponding interrupt is disabled Interrupt ENable If bit 1 the corresp
45. CONSOLE UART 13 3 6 UART BAUD RATE DIVISOR REGISTER The values stored in the baud rate divisor registers CUBRD let you determine the serial TX RX clock rate baud rate as follows PCLK 2 or EXT UCLK BRGOUT CNT0 1 x 160NT x 16 Table 13 12 CUBRD Registers Register Address RW Description Sie Reset Value CUBRD OxF0060014 Console UART baud rate divisor register 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 3 0 Baud rate divisor value CNT1 xxx0 Divide by 1 xxx1 Divide by 16 15 4 Time constant value for CNTO Figure 13 8 Console UART Baud Rate Divisor Register ELECTRONICS 13 15 SERIAL CONSOLE UART S3C2500B 13 3 7 CONSOLE UART BAUD RATE EXAMPLES If the system clock frequency is 133 MHz and PCLK is selected the maximum BRGOUT output clock rate is PCLK2 16 4 156 250 Hz EXT UCLK is the external clock input pin for Console UART PCLK2 and EXT UCLK can be selected by 5 register PCLK2 P 271 BRGOUT EXT UCLK Divide by 1 or 16 Divide by 16 Sample Clock Select Clock NOTE CNTO CUBRD 15 4 CNT1 CUBRD 3 0 Select Clock CUCON 5 Figure 13 9 Console UART Baud Rate Generator BRG Table 13 13 Typical Baud Rates Examples of Console UART Baud Rates PCLK2 66 5 MHz EXT UCLK 29 4912 MHz BRGOUT CNTO CNT1 CNTO CNT1 DEC HEX DEC HEX 1200 3463 87 0 119984 001 16365 0 120000
46. Figure 8 28 Data Sampling Method 8 52 ELECTRONICS S3C2500B HDLC CONTROLLER 8 7 17 TX BUFFER DESCRIPTOR COUNT REGISTER Tx Buffer Descriptor count register which shows how many Tx buffer descriptor is used Table 8 25 HTXBDCNTA HTXBDCNTB and HTXBDCNTC Register RW HTXBDCNTA R Tx buffer descriptor count register 0xXXXXX000 HTXBDCNTB 0xF01100C0 R Tx buffer descriptor count register 0xXXXXX000 HTXBDCNTC 0xF01200C0 R Tx buffer descriptor count register 0xXXXXX000 8 7 18 RX BUFFER DESCRIPTOR COUNT REGISTER Rx Buffer Descriptor count register which shows how many Rx buffer descriptor is used Table 8 26 HRXBDCNTA HRXBDCNTB and HRXBDCNTC Register HRXBDCNTA oxFo1000c4 R Rx buffer descriptor count register 0xXXXXX000 HRXBDCNTB 0xF01100C4 R Rx buffer descriptor count register 0xXXXXX000 HRXBDCNTC 0 01200 4 R Rx buffer descriptor count register 0xXXXXX000 ELECTRONICS 8 53 HDLC CONTROLLER S3C2500B 8 7 19 TX BUFFER DESCRIPTOR MAXIMUM COUNT REGISTER Tx Buffer Descriptor maximum count register sets tx buffer descriptor maximum counts For example if you set the HTXBDMAXCNT register to OxFFF then you can use 1 2 buffer descriptor If you set the HTXBDMAXCNT register to OxFFE OXFFC OxFF8 OxFEO then you can use 2 2 4 22 8 23 16 24 32 25 buffer descriptor for each buffer descriptor maximum count register setting You can set the
47. 1 the CPU PLL output is not filtered to be provided to the system SPLLFD 26 SPLL filter disable This bit determines whether the BUS PLL output is filtered or not during the configuration When this bit is set to 0 the BUS PLL output is filtered to be provided to the system during the configuration In this case the glitch output from PLL can be masked When this bit is set to 1 the BUS PLL output is not filtered to be provided to the system DPP 4 16 ELECTRONICS S3C2500B SYSTEM CONFIGURATION UPLLFD 25 UPLL filter disable This bit determines whether the USB PLL output is filtered or not during the configuration When this bit is set to 0 the USB PLL output is filtered to be provided to the USB during the configuration In this case the glitch output from PLL can be masked When this bit is set to 1 the USB PLL output is not filtered to be provided to the USB PPLLFD 24 PPLL filter disable This bit determines whether the PHY PLL output is filtered or not during the configuration When this bit is set to 0 the PHY output is filtered to be provided to the PHY during the configuration In this case the glitch output from PLL can be masked When this bit is set to 1 the PHY PLL output is not filtered to be provided to the PHY BIG 16 Little Big endian information Read only 0 Little endian 1 Big endian REMAP 8 External memory address remapping enable 0 Remap disable 1 Rema
48. 10 53 USBWCEP4 Register nnn 10 53 1 2 3 4 5 9 10 55 DES 3DES Special Registers Overview 22 2 11 3 DES 3DES Control Register lt 11 4 DES 3DES Status Register 11 5 DES 3DES Interrupt Enable Register Description 11 6 DES 3DES Run Enable Register Description sss 11 6 DES 3DES 1 Left Side Register Description 11 6 DES 3DES Key 1 Right Side Register Description 11 6 DES 3DES Key 2 Left Side Register Description 11 7 DES 3DES Key 2 Right Side Register Description 11 7 DES 3DES Key Left Side Register Description 11 7 DES 3DES Key Right Side Register Description 11 7 DES 3DES IV Left Side Register Description 11 7 DES 3DES IV Right Side Register Description 11 7 DES 3DES Input Data FIFO 11 8 DES 3DES Output Da
49. 128 and set condition codes CMP R2 62 Setcondition codes on R2 62 ADD R1 255 R1 255 and set condition codes SUB R6 145 R6 145 and set condition codes 3 70 ELECTRONICS S3C2500B INSTRUCTION SET 3 23 FORMAT 4 ALU OPERATIONS 15 14 13 12 11 10 9 6 5 3 2 0 2 0 Source Destination Register 5 3 Source Register 2 9 6 Opcode Figure 3 33 Format 4 3 23 1 OPERATION The following instructions perform ALU operations on a Lo register pair NOTE All instructions in this group set the CPSR condition codes Table 3 11 Summary of Format 4 Instructions THUMB Assembler ARM Equivale ww necra ns rsss ns a ELECTRONICS 3 71 INSTRUCTION SET 3 23 2 INSTRUCTION CYCLE TIMES S3C2500B All instructions in this format have an equivalent ARM instruction as shown in Table 3 11 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples EOR ROR NEG CMP MUL 3 72 R3 R4 R1 RO R5 R3 R2 R6 R7 R8 R8 EOR R4 and set condition codes Rotate right R1 by the value in RO store the result in R1 and set condition codes Subtract the contents of R3 from zero store the result in R5 Set condition codes ie R5 Set the condition codes on the result of R2 R6 RO R7 RO and set condition codes ELECTRONICS S3C2500B INSTRUCTION SET 3 24 FORMAT
50. 15 Timer 5 enable TE5 0 Disable timer 5 1 Enable timer 5 16 Timer 5 mode selection TMD5 0 Interval mode 1 Toggle mode 17 Timer 5 initial TOUT5 value TCLR5 0 Initial is 0 in toggle mode 1 Initial TOUTS is 1 in toggle mode Figure 17 3 Timer Mode Register TMOD ELECTRONICS 17 5 32 BIT TIMERS S3C2500B 17 6 2 TIMER DATA REGISTERS The timer data registers TDATAO TDATAS contain a value that specifies the time out duration for each timer The formula for calculating the time out duration is Timer data cycles The timer is dependent on the system bus clock When the system bus is 133 MHz the minimum value 0x1 for TDATA generates interrupt at every 7 5n sec It takes about 32 2 sec for TDATA to go from 0 0 to OxFFFFFFFF Although TOUT signal is designed to come out whenever time out occurs it is possible for TOUT signal not to work properly for some TDATA values when interrupt is enabled The reason is that ARM940T spends the specific time to reach interrupt service routine after time out takes place The elapsed time from time out to interrupt service routine is approximately 27 cycles 200n sec at 133 MHz Therefore TDATA should be set to the bigger value than Ox1A to avoid another time out while it is carrying out the process between time out and interrupt routine Table 17 2 TDATAO 5 Registers 31 0 31 0 Timer 0 5 data value Figure 17 4 Timer Data
51. 19 Receive FIFO reset RFRST 21 20 Transmit FIFO trigger level TFTL up ELECTRONICS S3C2500B High Speed UART block support 32 byte FIFO If this bit set to one transmit data moved to Tx FIFO and then sent S3C2500B High Speed UART block support 32 byte FIFO If this bit set to one receive data moved to Rx FIFO NOTE Changing these bits TFEN RFEN while transmitting receiving cause sending receiving unexpected data To prevent this changing these bits while transmitting receiving is strictly prohibited You set this bit to 1 transmit FIFO will be reset In this case if there is data in transmit shift register it will be sent NOTE This bit will not cleared automatically You set this bit to 1 receive FIFO will be reset In this case if there is data in receive shift register it will be received NOTE This bit will not cleared automatically This two bit trigger level value determines when the transmitter start to transmit data in 32 byte transmit FIFO 00 30 byte empty 32 byte 01 24 32 10 16 32 11 8 32 14 5 SERIAL I O HIGH SPEED UART S3C2500B Table 14 4 High Speed UART Control Register Description Continued Receive FIFO trigger This two bit trigger level value determines when the receiver start to 23 22 level RFTL move the received data in 32 byte receive FIFO 00 1 byte valid 32 byte 01 8 32 10 18 32 11 28 32 24 Data Terminal Ready to This bit directly co
52. 5 2 ELECTRONICS S3C2500B MEMORY CONTROLLER 5 3 MEMORY MAP After a power on or system reset all bank address pointer registers are initialized to their default values And the base address of all banks are fixed The initial system memory map following system start up is shown in Figure 5 1 Table 5 1 Base Address of Each Bank Bak Address ELECTRONICS 5 3 MEMORY CONTROLLER S3C2500B OxFFFFFFFF Internal Register 0x88000000 RE 0x48000000 0x40000000 0x08000000 0x07000000 0x06000000 0x05000000 0x04000000 0x03000000 0x02000000 0x01000000 0x00000000 NOTES 1 ROM SRAM Flash and External I O Bank have the same operation in internal logic Therefore you may connect a SRAM or a Flash Memory with a External I O Bank 2 Each EXT I O bank address is fixed with maximum address range S3C2500 has 24 address pins which restrict to 16M byte address 3 Each SDRAM bank supports up to 128M byte in size OxF0000000 Figure 5 1 Memory Bank Address map 5 4 ELECTRONICS S3C2500B MEMORY CONTROLLER 5 4 BUS INTERFACE SIGNALS The bus interface signals transfer information between the S3C2500B and external memory device These divide into address and data which used commonly SDRAM interface signals for SDRAM and memory device interface for ROM SRAM etc For detail description for the bus interface signals refer to the table below Table 5 2 Bus Interface Signals ACTIVE DESCRIPT
53. After an abort the following example code is difficult to unwind as the base register Rn gets updated before the abort handler starts Sometimes it may be impossible to calculate the initial value Example LDR RO R1 R1 Therefore a post indexed LDR or STR where Rm is the same register as Rn should not be used 3 9 6 DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system For instance in a system which uses virtual memory the required data may be absent from main memory The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the data abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued 3 9 7 INSTRUCTION CYCLE TIMES Normal LDR instructions take 15 1N 11 and LDR PC take 25 2N 11 incremental cycles where S N and I are defined as sequential S cycle non sequential N cycle and internal I cycle respectively STR instructions take 2N incremental cycles to execute ELECTRONICS 3 31 INSTRUCTION SET S3C2500B 3 9 8 ASSEMBLER SYNTAX LDR STR cond BT Rd Address where LDR STR B Address can be 1 shift 19 3 32 Load from memory into a register Store from a register into memory Two character condition mnemonic See Table 3 2
54. Assemble MAC frame Carrier sense ON Wait for interframe gap 96 bit time start Tx with preamble SFD Connie transmission Collision detected reamble and SFD Done Complete Tx transmitted Yes Stop transmission send 32 bit jam Attemp count Wait for back off time slot time x minimum n back off limit 10 0 lt Max attempt 216 0 lt random integer lt 2k Yes Report attempt limit exceeded error pp y Figure 7 6 CSMA CD Transmit Operation Attempt count Max attempt 7 40 ELECTRONICS S3C2500B ETHERNET CONTROLLER The main transmission state machine The main transmission state machine implements the remaining MAC layer protocols If there is data to be transferred if the inter frame gap is valid and if the MII is ready that is if there are no collisions and no CRS in full duplex mode the transmitter block then transmits the preamble followed by the SFD After the SFD and preamble are transmitted the block transmits 64 byte data regardless of the frame length unless short transmission is enabled This means that if the frame is less than 64 byte it will pad the LLC data field with zeros It will also append the CRC to the end of the frame if CRC generation is enabled If there is any collision during this first 72 byte time 8 byte preamble and SFD and 64 byte frame the main transmission state machine stops the transmis
55. EN was asserted the timeout counter in watchdog timer is cleared as 0 Following this cycle WDT 29 RST is automatically de asserted Watchdog Timer Timeout Value WDTVAL can be set as shown in Table 17 6 If the user set two or more bits of WDTVAL the lowest significant bit of those let the watch dog timer time out Table 17 5 WDT Register RW OxF0040008 R W Watchdog Timer Register 0x00000000 31 30 29 28 Watchdog Timer Timeout Value WDTVAL 17 0 Watchdog Timer Timeout Value WDTVAL 29 Watchdog Timer Counter Reset RST When set to 1 Watchdog Timer Counter is reset 30 Watchdog Timer Mode MODE 0 Interrupt Mode 1 Reset Mode 31 Watchdog Timer Enable EN 0 Disable 1 Enable Figure 17 7 Watchdog Timer Register WDT ELECTRONICS 17 9 32 BIT TIMERS S3C2500B Table 17 6 Watchdog Timer Timeout Value WDTVAL X Don t Care When watchdog timer operates at 133 MHz RE o d femi 910 0 0 0 0 0 0 0 0 0 0 0 Nooperation SENE X X x x x x x x x x x x x x x x 1 o X X X x x x x x x x x X x x x 1 o o 25045889 X X x x x x x x x x x x x x 7 X X x x x x X x x x x X X 1 0 0 0 0 270830 x x x x x x x x x x x x eme x X x x x x x x x x x 0 X X x x x x x x x x o o o o ojo 2G86m X X x x x x x x x t o o oj o o ojo o X X x x x x x
56. NOTES 1 The condition codes are unaffected by the format 5 12 and 13 versions of this instruction 2 The condition codes are unaffected by the format 5 version of this instruction 3 66 ELECTRONICS S3C2500B INSTRUCTION SET 3 20 FORMAT 1 MOVE SHIFTED REGISTER 15 14 13 12 11 10 6 5 3 2 0 2 0 Destination Register 5 3 Source Register 10 6 Immediate Vale 12 11 Opcode 0 LSL 1 LSR 2 ASR Figure 3 30 Format 1 3 20 1 OPERATION These instructions move a shifted value between Lo registers The THUMB assembler syntax is shown in Table 3 8 NOTE All instructions in this group set the CPSR condition codes Table 3 8 Summary of Format 1 Instructions OP THUMB Assembler ARM Equivalent O LSL Rd Rs Offset5 MOVS Rd Rs LSL Offset5 Shift Rs left by 5 bit immediate value and store the result in Rd 01 LSR Rd Rs Offset5 MOVS Rd Rs LSR Offset5 Perform logical shift right Rs by a 5 bit immediate value and store the result in Rd 10 ASR Rd Rs OffsetS MOVS Rd Rs ASR Offset5 Perform arithmetic shift right on Rs by 5 bit immediate value and store the result in Rd 3 20 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 8 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples LSR R2 R5 27 Logical shift right the contents of R5 by
57. TXC 4 RxCLK TxCLK 0 Muilt Frame in in Operation 0 Single frame in 1 Multi frame in TxFIFO 16 15 14 Ar OOmU Qo 33352142 1 Reserved 2 Rx Clock Inversion RxCINV 0 Rx clock rising 1 Rx clock falling 3 Tx Clock Inversion TxCINV 0 Tx clock falling 1 Tx clock rising 4 Rx Little Endian Mode RxLittle 0 The Rx data on the system bus is in Big Endian format 1 The Rx data on the system bus is in Little Endian format 5 Tx Little Endian Mode TxLittle 0 The Tx data on the system bus is in Big Endian format 1 The Tx data on the system bus is in Little Endian format 6 Rx Transparent Mode RXTRANS 0 The Rx operates HDLC mode 1 The Rx operates transparent mode 7 Tx Transparent Mode 5 0 The Tx operates HDLC mode 1 The Tx operates transparent mode 10 8 Tx Preamble Length TxPL 000 1 byte 100 5 byte 001 2 byte 101 6 byte 010 3 byte 110 7 byte 011 4 byte 111 8 byte 11 Reserved 14 12 Data Format DF 000 NRZ data format 010 FMO 100 Manchester 001 NRZI 001 HDLC CONTROLLER 12 11 10 2 gt 20 2 15 RTRnRTS 0 Request to send 1 Receive to ready 18 16 DPLL Clock Select DPLLCLK 000 TXC pin 001 RXC pin 010 MCLK2 011 BRGOUT1 100 BRGOUT2 19 BRG Clock Select BRGCLK 0 RXC pin is selected 1 2 is s
58. Table 10 18 USBEP1CSR Register Description Continued 20 Out mode This bit is valid only when endpoint 1 is set to OUT Fifo FLUSH The MCU writes a 1 to flush the FIFO OFFLUSH This bit can be set only when OORDY is set The packet due to be unloaded by the MCU will be flushed 21 Out mode This bit is valid only when endpoint 1 is set to OUT SenD STALL The MCU writes 1 to this bit to issue STALL OSDSTALL handshake to the USB The MCU clears this bit to end the STALL condition 22 Out mode This bit is valid only when endpoint 1 is set to OUT SenT STALL The USB sets this bit when an OUT token is ended OSTSTALL with a STALL handshake The USB issues a stall handshake to the host if it sends more than MAXP data for the OUT token 23 Out mode This bit is valid only when endpoint 1 is set to OUT CLear data TOGgle When the MCU writes a 1 to this bit the data OCLTOG toggle sequence bit is reset to DATAO 24 In mode IN packet This bit is valid only when endpoint 1 is set to IN ReaDY IINRDY The MCU sets this bit after writing a packet of data into the FIFO The USB clears this bit once the packet has been successfully sent to the host An interrupt is generated when the USB clears this bit so the MCU can load the next packet While this bit is set the MCU will not be able to write to the FIFO If the SEND STALL bit is set by the MCU this bit can not be set 25 In mode fifo
59. gt go to number 1 0 Number 6 No GDMA go to number 1 GDMA 0 12 6 ELECTRONICS S3C2500B GDMA CONTROLLER The following is the problem solving with software 1 Method 1 DPRIR Channel Expected Real Bus System Bus Occupancy Occupancy DPRIR Channel Occupancy gt Problem Problem Solving by Method 1 Writing 0x000330 instead of 0x0 will give each channel of three with the same amount of bus occupancy 2 Method 2 DPRIR Channel Expected Real Bus System Bus Occupancy Occupancy DPRIR Channel Occupancy Problem Problem Solving by Method 2 With leaving DPRIR as 0x0 and using every other channel each channel of three GDMA gets the same bus occupancy as seen above ELECTRONICS 12 7 GDMA CONTROLLER S3C2500B GDMA Channel Needed Recommended Problem Solving Recommended GDMA Channel Used when S W 2 Method 2 0 1 2 3 4 0r 5 Method 2 0 3 or 1 4 or 2 5 This method works when 1 2 4 or 6 channels are needed but there is no solution when 4 or 5 channels are needed So we recommend that when you need 1 2 3 or 6 GDMA channels use Method 2 and when you need 4 or 5 GDMA channels use Method 1 12 8 ELECTRONICS S3C2500B GDMA CONTROLLER 12 3 2 GDMA CONTROL REGISTERS Table 12 3 1 2 3 4 5 Registers DCONO 0 0050000 GDMA channel 0 control register 0x00000000 DCON1 0 0050020 GDMA channel 1 control register 0x00000000 T
60. 10 in out MODE setting MODE 0 Indexed endpoint set to OUT 1 2 Indexed endpoint set to IN 11 IN ISO mode 5 0 Bulk interrupt mode 1 ISO mode 12 IN AuTo SET IATSET 0 No operation 1 Auto setting IINRDY when MAXP sized packet loaded 14 13 Reserved 15 CSR2 SETting enable CSR2SET 0 USBEPSCSR 12 8 isn t changed 1 USBEPSCSR 12 8 is changed 16 OUT Out packet ReaDY OORDY 0 Not received data packet 1 Received packet from host 17 OUT Fifo FULL OFFULL 0 Normal operation 1 FIFO full state 18 OUT OVER run OOVER 0 Normal operation 1 Data received at FIFO full state ISO USB CONTROLLER 16 15 14 13 12 11 10 9 8 ropo 2 19 OUT Data ERRor ODERR 0 Normal operation 1 Data error ISO 20 OUT Fifo FLUSH OFFLUSH 0 No operation 1 FIFO flush 21 OUT SenD STALL OSDSTALL 0 No operation 1 Stall handshake transmit state 22 OUT SenT STALL OSTSTALL 0 No operation 1 Stall handshake transmitted 23 OUT CLear data TOGgle OCLTOG 0 No operation 1 Data toggle flag set to 0 24 IN IN packet ReaDY IINRDY 0 Not ready for IN operation 1 Ready for IN operation 25 IN fifo Not EMPty INEMP 0 No data packet in FIFO 1 There is at least one packet of data in FIFO 26 IN UNDER run IUNDER 0 No operation 1 Received IN token but not ready ISO 27 IN Fifo FLUSH IFF
61. 11 LDR H SH SB PC take 2S 2N 11 incremental cycles S N and are defined as sequential S cycle non sequential N cycle and internal I cycle respectively STRH instructions take 2N incremental cycles to execute ELECTRONICS 3 37 INSTRUCTION SET S3C2500B 3 10 8 ASSEMBLER SYNTAX lt LDR STR gt cond lt H SH SB gt Rd lt address gt LDR STR cond H SB SH Rd lt address gt can be 1 3 38 Load from memory into a register Store from a register into memory Two character condition mnemonic See Table 3 2 Transfer half word quantity Load sign extended byte Only valid for LDR Load sign extended half word Only valid for LDR An expression evaluating to a valid register number An expression which generates an address The assembler will attempt to generate an instruction using the PC as a base and a corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated A pre indexed addressing specification Rn offset of zero Rn lt expression gt offset of lt expression gt bytes Rn Rm offset of contents of index register A post indexed addressing specification Rn lt expression gt offset of lt expression gt bytes Rn Rm offset of contents of index register Rn and Rm are expressions evaluating to a register number If Rn
62. 12 3 1 GDMA PROGRAMMABLE PRIORITY REGISTERS The GDMA can support the fixed priority and the round robin priority for the local arbitration of six GDMA channels by register setting Especially the GDMA can program the priority order in the fixed priority mode as well as the ratio of the bus occupancy in the round robin priority mode The local priority of six channels of GDMA can be programmed by the fixed priority or the round robin priority in similar manner to the AHB bus priority Please refer to Chapter 4 The System Configuration The GDMA programmable priority registers are DPRIC Programmable Priority Register for Configuration DPRIF Programmable Priority Register for Fixed and DPRIR Programmable Priority Register for Round Robin If the priority configuration register 0 0051000 DPRIC 0 1 the programmable fixed priority is run by DPRIF register Each GDMA channel has its own fixed priority index For example the GDMA channel 0 has the index 0 The reset value of DPRIF register is 0x00543210 The first field of DPRIF 3 0 indicates the highest priority So the channel 0 has the highest priority in local arbitration when DPRIC 0x1 and the DPRIF has the reset value For example DPRIC 0x1 and the DPRIF is 0x00431520 the fixed priority order from the highest to the lowest is GDMA channel 0 channel 2 channel 5 channel 1 channel 3 and channel 4 If the priority configuration register 0
63. 2 IC Channel Transmit Data Register Table 9 8 IOM2ICRD 2 IC Channel Receive Data Register IOM2ICRD 0 0130014 IC Channel Receive Data 0x00000000 wap 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 7 0 IC Channel Receive Data Figure 9 12 2 IC Channel Receive Data Register ELECTRONICS 9 19 IOM2 CONTROLLER S3C2500B 9 5 6 2 10 CHANNEL TRANSMIT DATA REGISTER Table 9 9 IOM2CITDO IOM2 Channel Transmit Data Register IOM2CITDO OxF0130018 Channel Transmit Data 0x0000000F Bit Number Description 3 0 CITDO This field includes the data to be transmitted on the channel The data is continuously transmitted until a new code is loaded Bia 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11109876543 3 0 Channel Transmit Data Figure 9 13 2 Channel Transmit Data Register Table 9 10 IOM2CIRDO 2 Channel Receive Data Register IOM2CIRDO 0xF013001C Channel Receive Data 0x00000000 Bit Number Description 3 0 CIRDO This field includes the data received on the channel This data is sure to be valid by double last look criterion valid during two successive frames Bia Reseved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 3 0 Channel Receive Data Figure 9 14 IOM2 Channel Receive Data
64. 2 cycles TCOS 0x1 1 cycle TMA 0 2 0x4 4 cycles 0 1 1 cycle o 5 c E I LLI m gt TCOH Figure 5 19 Read Timing Diagram Muxed Bus ELECTRONICS 5 34 MEMORY CONTROLLER S3C2500B Data Fetch 0 1 1 cycle 0x2 2 cycles TCOS TMA 9 8 gt IE TCOH MBE 1 Enable Figure 5 20 Write Timing Diagram Muxed Bus 5 35 ELECTRONICS S3C2500B MEMORY CONTROLLER nEWAIT tnWAITd 0 1 1 cycle 0 1 1 cycle TCOS TACS 5 cycles Enable T gt o e z gt 0 5 EWAITEN 1 Figure 5 21 Write Timing Diagram nEWAIT ELECTRONICS 5 36 MEMORY CONTROLLER tnWAITh Ox1 1 cycle Ox1 1 cycle tnWAITd NREADY 1 nReady TCOS TACS 9 gt 6 2x 5 5 u 2 E lt z ul TACC TCOH 5 37 S3C2500B Figure 5 22 Write Timing Diagram nREADY ELECTRONICS MEMORY CONTROLLER S3C2500B 5 7 SDRAM CONTROLLER 5 7 1 FEATURES The SDRAM controller provides the following features e Provides merging write buffer to improve system performance e Supports for 16M bit 64M bit 128M bit 256M bit SDRAM devices with two or four leaves e Allows a direct interface to up to two banks of SDRAM e Each bank supports 16 32 bits wide and up to 128M byte in size e Support
65. CRC generation and checking Token and Data e Packet ID generation and checking decoding e Serial Parallel Parallel Serial Conversion ELECTRONICS 10 7 USB CONTROLLER fun sync detect RXD fun rxd x 2 L fun eop detect syn VPIN rxd fun rst detect VPIN VMIN 10 8 fun bit stuff VPOUT VMOUT data in fun crc crc out nrzi dec out fun shiftreg nrzi dec out rxd tx mux out 7 0 shiftreg out 7 0 fun pid dec shiftreg out 7 0 fun tx mux tx mux out 7 0 TX DATA tx buf out 7 0 DATA 7 0 Figure 10 5 SIE Block Diagram S3C2500B ELECTRONICS S3C2500B USB CONTROLLER 10 5 USB SPECIAL REGISTERS The USB special registers are defined as read write or read only or write only registers according to the direction of information flow The addresses of these registers are shown in Table 10 1 Table 10 1 USB Registers Resev 1 a e OxFOOE007C NOTE The Mark of R W column means that each register can be set in read or write mode but once it is set to one mode it cannot operate the other mode For example USBEP1 is set to R in setup time it can be read but not be written So if you want to write something in USBEP1 after it is set to mode you must re setup the register to W mode ELECTRONICS 10 9 USB CONTROLLER S3C2500B 10 5 1 USB FUNCTION ADDRESS REGISTER
66. If this bit is a zero the device will not enter suspend mode This bit is set by the USB when it enters suspend mode It is cleared under the following conditions The MCU clears the USB RESUme bit to end resume signaling The MCU reads USB Interrupt Register for the USB Resume Interrupt The MCU sets this bit for a duration of 10ms maximum of 15ms to initiate a resume signaling The USB generates resume signaling while this bit is set in suspend mode The USB set this bit if reset signaling is received from the host This bit remains set as long as reset signaling persists on the bus 0 Disable Tx Data Swap from USB to SIE 1 Enable Tx Data Swap If this bit is a one the device will swap transmitted data 0 Disable Rx Data Swap from SIE to USB 1 Enable Rx Data Swap If this bit is a one the device will swap received data Used for ISO Mode only If set GFI waits for a SOF token from the time USBINRDY was set to send the packet If an IN token is received before a SOF token then a zero length data packet will be sent em ELECTRONICS S3C2500B ELECTRONICS 0 SUSpend Enable SUSE Suspend mode disable 1 Suspend mode enable 1 SUSpend Mode SUSM 0 Normal operation 1 Suspend state 2 ResUme RU Normal or suspend state 1 Resume signal generation in suspend state 3 ReSeT RST 0 Normal operation 1 Reset received state 4 Tx Data Swap TDS
67. NOTE Each of the 32 bits in the interrupt mode enable register INTMOD corresponds to an interrupt source When the source interrupt mode bit is set to 1 the interrupt is processed by the ARM940T core fast interrupt mode Otherwise it is processed in IRQ mode normal interrupt The 32 interrupt sources are mapped as follows 31 Watchdog Timer interrupt 0 IRQ interrupt mode 1 FIQ interrupt mode 30 32 bit Timer 5 interrupt 29 32 bit Timer 4 interrupt 28 32 bit Timer 3 interrupt 27 32 bit Timer 2 interrupt 26 32 bit Timer 1 interrupt 25 32 bit Timer 0 interrupt 24 GDMA channel 5 interrupt 23 GDMA channel 4 interrupt 22 GDMA channel 3 interrupt 21 GDMA channel 2 interrupt 20 GDMA channel 1 interrupt 19 GDMA channel 0 interrupt 18 DES interrupt 17 Ethernet 1 RX interrupt 16 Ethernet 1 TX interrupt 15 Ethernet 0 RX interrupt 14 Ethernet 0 TX interrupt 13 HDLC 2 RX interrupt 12 HDLC 2 TX interrupt 11 HDLC 1 RX interrupt 10 HDLC 1 TX interrupt 9 HDLC 0 RX interrupt 8 HDLC 0 TX interrupt 7 USB interrupt 6 CUART RX interrupt 5 CUART TX interrupt 4 HUART 1 RX interrupt 3 HUART 1 TX interrupt 2 HUART 0 RX interrupt 1 HUART 0 TX interrupt 0 interrupt Figure 16 1 Internal Interrupt Mode Register INTMOD 16 4 ELECTRONICS S3C2500B INTERRUPT CONTROLLER 31 30 29 28 27 26 25 24 23 22 21 2019 18 17 16 15 14 131211
68. Reading the HDLC status register is a non destructive process The method used to clear a High level status condition depends on the bit s function and operation mode DMA or interrupt For details please see the description of each status register Table 8 11 HSTATA HSTATB and HSTATC Register HSTATA 0 0100008 R W HDLC Channel A Status Register 0X00000000 HSTATB OxF0110008 R W HDLC Channel B Status Register 0X00000000 HSTATC OxF0120008 R W HDLC Channel C Status Register 0X00000000 8 7 4 SUMMARY There are two kinds of bits in a status register 1 TxCTS RxFA RxDCD RxFV RxCRCE RxNO RxIERR and RxOV bits are show each bit s status These bits are set or cleared automatically according to the each bit status 2 All other bits are cleared by the CPU writing 1 to each bit 8 36 ELECTRONICS S3C2500B HDLC CONTROLLER Table 8 12 HSTAT Register Description Bit Bit Name Description Number 3 0 Rx remaining bytes RxRB Tx frame complete TxFC Tx FIFO available TxFA Tx clear to send TxCTS Tx stored clear to send TxSCTS Tx under run TxU Rx FIFO available RxFA RxRB 1 indicates how many data bytes are valid in a 1 word or 4 word boundary when the receiver has received a complete frame In 1 word transfer mode the RxRB value is either 0 1 2 or 3 In 4 word mode it is 0 1 14 or 15 This status bit is automatically set to 1 when the two conditions are
69. Register Address RW Description Size Reset Valu RW High Speed UART contol register W 0x00000000 HUSTAT oxFo080004 RW High Speed UART status register ur oxFo080008 RA High Speed UART iterupt enable register W 000000000 HUTXBUF bwrocenooc High Speed UART tansmtdetaregister HURXBUF High Speed UART receive data register ELECTRONICS 14 3 SERIAL I O HIGH SPEED UART S3C2500B 14 3 1 HIGH SPEED UART CONTROL REGISTERS Table 14 3 High Speed UART Control Registers HUCON 0 0070000 R W High Speed UART control register 0x00000000 OxF0080000 Table 14 4 High Speed UART Control Register Description Transmit mode TMODE This two bit value determine which function is currently able to write Tx data to the High Speed UART transmit buffer register HUTXBUF 00 Disable Tx mode 01 Interrupt request 10 request 11 Reserved High speed UART 0 can use only 0 1 2 channel and High speed UART 1 can use only GDMA 3 4 5 channel Receive mode RMODE This two bit value determine which function is currently able to read Rx data to the High Speed UART receive buffer register HURXBUF NOTE Changing these bits TMODE RMODE while transmitting receiving cause abnormal high speed UART operation To prevent Tx Rx data from being lost changing these bits while transmitting
70. This register maintains the USB device address assigned by the host The MCU writes the value received through a SET ADDRESS descriptor to this register This address is used for the next token Table 10 2 USBFA Register USBFA 0 00 0000 USB function address register 0 00000000 Table 10 3 USBFA Register Description USB Function R W The MCU write the address to these bits Address Field USBFAF transfer which is signaled by the clearing of the DATA END bit in the Endpoint 0 CSR reves 080000 USB Address S R C The MCU sets this bit whenever it updates the USB UPdate Function Address Field USBFAF in this register The USBAUP USBFAF is used after the Status phase of a Control 10 10 ELECTRONICS S3C2500B USB CONTROLLER 6 0 Function Address Field FAF 7 Address UPdate AUP 31 8 Reserved Figure 10 6 USBFA Register ELECTRONICS 10 11 USB CONTROLLER S3C2500B 10 5 2 USB POWER MANAGEMENT REGISTER This register is used for suspend resume reset and data swapping signaling The different bits in this register are explained below Table 10 4 USBPM Register USBPM OxFOOE0004 USB power management register Table 10 5 USBPM Register Description 0x00000000 0 SUSpend Enable SUSE SUSpend Mode SUSM 4 Tx Data Swap R W 5 Rx Data Swap Reserved ISO Update ISOU 81 8 10 12 0 Disable Suspend mode Default 1 Enable Suspend mode
71. e Level Sensitive Interrupt Sources e Supports 33 Internal Interrupt Sources e Supports 6 External Interrupt Sources e Supports Interrupt Sources Programmable to Different Priorities e Supports Global Interrupt Masking ELECTRONICS 16 1 INTERRUPT CONTROLLER S3C2500B 16 3 INTERRUPT SOURCES The 39 interrupt sources in the S3C2500B interrupt structure are listed in brief as follows Table 16 1 S3C2500B Internal Interrupt Sources 29 28 27 26 25 24 23 22 21 20 119 18 17 t6 15 14 13 12 11 10 9 8 7 6 5 S 2 0 16 2 ELECTRONICS S3C2500B INTERRUPT CONTROLLER Table 16 2 S3C2500B External Interrupt Sources External interrupt 3 External interrupt 2 External interrupt 1 External interrupt 0 16 4 INTERRUPT CONTROLLER SPECIAL REGISTERS 16 4 1 INTERRUPT MODE REGISTERS Bit settings in the interrupt mode registers INTMOD and EXTMOD specify if an interrupt is to be serviced as a fast interrupt FIQ or a normal interrupt IRQ Table 16 3 INTMOD EXTMOD Register RW INTMOD 0xF0140000 R Intemal interrupt mode register 0x00000000 EXTMOD OxF0140004 External interrupt mode register 0x00000000 ELECTRONICS 16 3 INTERRUPT CONTROLLER S3C2500B 31 30 29 28 27 26 25 24 23 22 21 2019 18 17 16 15 14 131211109 8 7 6 5 4 3 2 1 0 rmon x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 31 0 Internal interrupt mode bits
72. equivalent to the BMTXSTAT 7 0 11 8 Transmission collision count This 4 bit value is the count of collisions that occurred while MCollCnt successfully transmitting the frame 12 Transmission deferred This bit is set if transmission of a frame was deferred because MTxDefer of a delay during transmission 13 Signal quality error SQEErr According to the IEEE802 3 specification the SQE signal reports the status of the PMA MAU or transceiver operation to the MAC layer After transmission is complete and 1 6 ms has elapsed a collision detection signal is issued for 1 5 ms to the MAC layer This signal is called the SQE test signal The MAC sets this bit if this signal is not reported within the IFG time of 6 4ms 14 Transmission halted This bit is set if the MTxEn bit is cleared or the MHaltlmm bit MTxHalted is set 15 Paused MPaused This bit is set if transmission of frame was delayed due to a Pause being received 91 16 Not applicable 7 28 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 4 2 6 MAC Receive Control Register Table 7 36 MACRXCON Register MACRXCONA 0xF00B0010 0 00000000 MACRXCONB 0xF00D0010 0 00000000 Table 7 37 MAC Receive Control Register Description 0 Receive enable MRxEn Set this bit to 1 to enable MAC receive operation If 0 stop reception immediately Receive halt request Set this bit to halt reception after completing the reception of MRxHalt any current frame
73. to the RxEN or bit respectively You can disable the receiver and HRXFIFO or the transmitter and HTxFIFO by writing 1 to the RxRS or TxRS bit respectively ELECTRONICS 8 11 HDLC CONTROLLER S3C2500B 8 5 2 HDLC DATA ENCODING DECODING Data encoding is utilized to allow the transmission of clock and data information over the same medium This saves the need to transmit clocks and data over a separate medium as would normally be required for synchronous data The HDLC provides four different data encoding methods selected by bits in HCON1 18 16 An example of these four encoding methods is shown in figure 8 5 Bit Cell Level High 1 Low 0 No Change 1 Change 0 Bit Center Transition Transition 1 Biphase Mark No Transition 0 FMO No Transition 1 Biphase Space Transition 0 I I 1 1 High 3 Low 1 Manchester FL p Low gt High 0 I NRZ NRZI Type TxClock 1 I I I I I RxClock FM0 FM1 Manchester type TxClock Data I I I I I I I I RxClock Figure 8 5 Data Encoding Methods and Timing Diagrams 8 12 ELECTRONICS S3C2500B HDLC CONTROLLER 8 5 3 HDLC DATA SETUP AND HOLD TIMING WITH CLOCK You can see the timing of and RxD in terms of TxC and RxC HDLC clock in Figure 8 6 Table 8 3 HDLC Data Setup and Hold Timing TxD tating edge delay ime wo
74. 0 Do not store LR Load PC 1 Store LR Load PC 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 3 43 Format 14 3 33 1 OPERATION The instructions in this group allow registers 0 7 and optionally LR to be pushed onto the stack and registers 0 7 and optionally PC to be popped off the stack The THUMB assembler syntax is shown in Table 3 21 NOTE The stack is always assumed to be full descending Table 3 21 PUSH and POP Instructions L THUMB ARM Equivalent Assembler PUSH Rlist STMDB R13 Rlist Push the registers specified by Rlist onto the stack Update the stack pointer 1 PUSH Rlist LR STMDB R13 Rlist R14 Push the Link Register and the registers specified by Rlist if any onto the stack Update the stack pointer 1 POP RIist LDMIA R13 Rlist Pop values off the stack into the registers specified by Rlist Update the stack pointer 1 1 POP Rlist LDMIA R13 Rlist R15 Pop values off the stack and load into the registers specified by Rlist Pop the PC off the stack Update the stack pointer 3 88 ELECTRONICS S3C2500B INSTRUCTION SET 3 33 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 21 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples PUSH RO R4 LR Store RO R1 R2 R3 R4 and R14 LR at the st
75. 0 Normal operation 1 Transmit data swap 5 Rx Data Swap RDS 0 Normal operation 1 Receive data swap 6 Reserved 7 ISO Update ISOU 0 ISO data updated zero data packet send 1 ISO data updated 31 8 Reserved Figure 10 7 USBPM Register USB CONTROLLER 10 13 USB CONTROLLER S3C2500B 10 5 3 USB INTERRUPT REGISTER There re five endpoints EPO EP4 Each bit in this register corresponds to the respective endpoint number All interrupts corresponding to endpoints whose direction is programmable Mode IN OUT are mapped to this register This register maintains interrupt status of bus signaling condition viz e Suspend Resume e Reset e Disconnect Table 10 6 USBINTR Register USBINTR OxFO0EO008 R W interrupt register 0x00000000 10 14 ELECTRONICS S3C2500B USB CONTROLLER Table 10 7 USBINTR Register Description EPOInterrupt This bit corresponds to endpoint 0 interrupt EPOI The USB sets this bit under the following conditions 1 ORDY bit is set 2 INRDY bit is cleared 3 STSTALL bit is set 4 SETEND bit is set 5 DEND bit is cleared Indicates End of control transfer 4 1 EP1 Interrupt For Bulk Endpoints EPAInterrupt The USB sets this bit under the following conditions EPAI 1 IINRDY bit is cleared 2 FIFO is flushed 3 OSTSTALL ISTSTALL is set For ISO Endpoints The USB sets this bit under the following conditions 1 IUNDER bit is s
76. 1 Load from memory 21 Write back 0 No write back 1 Write address into base 23 Up Down 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing 0 Post add subtract offset after transfer 1 Pre add subtract offset bofore transfer 31 28 Condition Field Figure 3 16 Half word and Signed Data Transfer with Register Offset 3 34 ELECTRONICS S3C2500B INSTRUCTION SET 31 2827 25 24 23 22 21 20 19 16 15 12 11 876543 Lu PPTPLPI m Dow Dee PIF DD 3 0 Immediate Offset Low Nibble 6 5 S H 0 0 SWP instruction 0 1 Unsigned halfwords 1 1 Signed byte 1 1 Signed half words 11 8 Immediate Offset High Nibble 15 12 Source Destination Register 19 16 Base Register 20 Load Store 0 Store to memory 1 Load from memory 21 Write back 0 No write back 1 Write address into base 23 Up Down 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing 0 Post add subtract offset after transfer 1 Pre add subtract offset bofore transfer 31 28 Condition Field Figure 3 17 Half word and Signed Data Transfer with Immediate Offset and Auto Indexing 3 10 1 OFFSETS AND AUTO INDEXING The offset from the base may be either a 8 bit unsigned binary immediate value in the instruction or a second register The 8 bit offset is formed by concatenating bits 11 to 8 and bits 3 to 0 of the instruction word such tha
77. 1 1 Hd Hs CMP Hd Hs Compare two registers in the range 8 15 Set the condition code flags on the result 10 1 MOV Rd Hs MOV Rd Hs Move a value from a register in the range 8 15 to a register in the range 0 7 10 1 MOV Hd Rs MOV Hd Rs Move a value from a register in the range 0 7 to a register in the range 8 15 MOV Hd Hs MOV Hd Hs Move value between two registers in the range 8 15 BX Rs BX Rs Perform branch plus optional state change to address in a register in the range 0 7 BX Hs BX Hs Perform branch plus optional state change to address in a register in the range 8 15 3 24 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 12 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction 3 24 3 THE BX INSTRUCTION BX performs a branch to a routine whose start address is specified in a Lo or Hi register Bit 0 of the address determines the processor state on entry to the routine Bit0 0 Causes the processor to enter ARM state Bit 0 1 Causes the processor to enter THUMB state NOTE The action of H1 1 for this instruction is undefined and should not be used 3 74 ELECTRONICS S3C2500B Examples Hi Register Operations ADD PC R5 R4 R12 MOV R15 R14 Branch and Exchange ADR R1 0utof THUMB MOV R11 R1 BX R11 ALIGN CODE32 outof THUMB 3 24 4 USING R15 AS AN OPERAND INS
78. 2 3 2 LITTLE ENDIAN FORMAT In Little Endian format the lowest numbered byte in a word is considered the word s least significant byte and the highest numbered byte the most significant Byte 0 of the memory system is therefore connected to data lines 7 through 0 Higher Address Word Address Lower Address Least significant byte is at lowest address Word is addressed by byte address of least significant byte Figure 2 2 Little Endian Addresses of Bytes Words 2 2 ELECTRONICS S3C2500B PROGRAMMER S MODEL 2 4 INSTRUCTION LENGTH Instructions are either 32 bits long in ARM state or 16 bits long in THUMB state 2 5 DATA TYPES ARMSTDMI supports byte 8 bit half word 16 bit and word 32 bit data types Words must be aligned to four byte boundaries and half words to two byte boundaries 2 6 OPERATING MODES ARMSTDMI supports seven modes of operation User usr The normal ARM program execution state Designed to support a data transfer or channel process IRQ irq Used for general purpose interrupt handling Supervisor svc Protected mode for the operating system Abort mode abt Entered after a data or instruction prefetch abort System sys A privileged user mode for the operating system Undefined und Entered when an undefined instruction is executed Mode changes may be made under software control or may be brought about by external interrupts or exception processing Most application prog
79. 2 cycles 0110 6 cycles 1010 10 cycles 1110 14 cycles 0010 2 cycles 0110 6 cycles 1010 10 cycles 1110 14 cycles 15 12 Page address access cycle TPA 0000 0 cycle 0100 4 cycles 1000 8 cycles 1100 12 cycles 0001 1 cycle 0101 5 cycles 1001 9 cycles 1101 13 cycles 0010 2 cycles 0110 6 cycles 1010 10 cycles 1110 14 cycles 20 16 Access cycles nOE low time TACC 00000 reserved 00100 4 cycles 01000 8 cycles 01100 12 cycles 10000 16 cycles 10100 20 cycles 11000 24 cycles 11100 28 cycles 22 21 Reserved 00001 reserved 00101 5 cycles 01001 9 cycles 01101 13 cycles 10001 17 cycles 10101 21 cycles 11001 25 cycles 11101 29 cycles 00010 reserved 00110 6 cycles 01010 10 cycles 01110 14 cycles 10010 18 cycles 10110 22 cycles 11010 26 cycles 11110 2 30 cycles 0011 3 cycles 0111 7 cycles 1011 11 cycles 1111 2 15 cycles 0011 3 cycles 0111 7 cycles 1011 11 cycles 1111 2 15 cycles 0011 3 cycles 0111 7 cycles 1011 11 cycles 1111 2 15 cycles 0011 3 cycles 0111 7 cycles 1011 11 cycles 1111 2 15 cycles 00011 cycles 00111 7 cycles 01011 11 cycles 01111 2 15 cycles 10011 19 cycles 10111 23 cycles 11011 27 cycles 11111 2 31 cycles 23 nWBE or nBE DQM selection IS 0 nWBE function 1 nBE function NOTE nWBE signal is operated at only coriting operation
80. 21 TCOH disable for bank 5 COHDIS5 20 TCOH disable for bank 4 COHDISA 19 TCOH disable for bank 3 COHDIS3 18 TCOH disable for bank 2 COHDIS2 17 TCOH disable for bank 1 COHDIS1 16 TCOH disable for bank 0 COHDISO 15 External wait enable for bank 7 EWAITEN7 0 disable 1 enable 14 External wait enable for bank 6 EWAITEN6 13 External wait enable for bank 5 EWAITEN5 12 External wait enable for bank 4 EWAITEN4 11 External wait enable for bank 3 EWAITEN3 10 External wait enable for bank 2 EWAITEN2 9 External wait enable for bank 1 EWAITEN1 8 External wait enable for bank 0 EWAITENO 7 nWait nReady select for bank 7 NREADY7 0 nWait 1 nReady 6 nWait nReady select for bank 6 NREADY6 5 nWait nReady select for bank 5 NREADY5 4 nWait nReady select for bank 4 NREADY4 3 nWait nReady select for bank 3 NREADY3 2 nWait nReady select for bank 2 NREADY2 1 nWait nReady select for bank 1 NREADY1 0 nWait nReady select for bank 0 NREADYO Figure 5 13 Wait Control WAITCON Register Configuration oO lt OPmIZz wo 0 N S3C2500B lt gt 22 o ELECTRONICS MEMORY CONTROLLER S3C2500B 5 6 4 TIMING DIAGRAM Data Fetch 0 0 0 cycle 0x0 0 cycle TCOS TACS gt eo o 0x8 TACC TCOH Figure 5 14 Read Timing Diagram 1 5 29 ELECTRONICS S3C250
81. 24 DMA Rx frame done every received frame interrupt enable DRxFDIE 25 Reserved 26 Rx not owner interrupt enable 27 DMA Tx frame done every received frame interrupt enable DTxFDIE 28 Reserved 29 DMA Tx not owner interrupt enable DTxNOIE 30 DPLL one missing interrupt enable DPLLOMIE 31 DPLL two missing interrupt enable DPLLTMIE Figure 8 16 HDLC Interrupt Enable Register ELECTRONICS 8 43 HDLC CONTROLLER S3C2500B 8 7 6 HDLC TX FIFO HTXFIFO The Tx FIFO consists of eight 32 bit registers that are used for buffer storage of data to be transmitted Data is always transferred from a full register to an empty adjacent register The Tx FIFO can be addressed at two different register addresses the continue address and the frame terminate address Each register has four pointers data valid pointer bit 4 bits last pointer bit NoCRC pointer bit Preamble pointer bit The data valid pointer bit indicates whether each byte is valid or not The last byte pointer bit indicates whether the frame to be sent has the frame last byte or not The NoCRC pointer bit determines whether the CRC data is to be appended or not by hardware When valid data byte is written to the frame continue address the data valid pointer is set but the last byte pointer is not set When a valid data byte is written to the frame terminate address the data valid pointer and last byte pointer
82. 802 3 Section 22 3 Signal Characteristics TX CLK N N 1 4 9ns MIN 28ns MIN TXD 3 0 I Figure 7 13 Timing Relationship of Transmission Signals at MII RX CLK N N I I Ts 3ns Th 5ns I I RXD 3 0 Input V RX_DV Valid Figure 7 14 Timing Relationship of Reception Signals at MII Th 1305 MDIO Output Valid Figure 7 16 MDIO Sourced by STA 7 50 ELECTRONICS S3C2500B HDLC CONTROLLER HDLC CONTROLLER 8 1 OVERVIEW The S3C2500B has three high level data link controllers HDLCs to support three channel serial communica tions The HDLC module supports a CPU data link interface that conforms to the synchronous data link control SDLC and high level data link control HDLC standards In addition the following function blocks are integrated into the HDLC module Three channel DMA engine for Tx Rx Support buffer descriptors per frame Digital phase locked loop DPLL block Baud rate generator BRG ELECTRONICS 8 1 HDLC CONTROLLER S3C2500B 8 2 FEATURES Important features of the S3C2500B HDLC block are as follows e Protocol features Flag detection and synchronization Zero insertion and deletion Idle detection and transmission FCS encoding and detection 16 bit Abort detection and transmission e Four address station registers and one mask register for address search mode e Selecta
83. B BRGOUT2 BRGOUT2 RxCLK RE gt T it xC gt Recei Transmitter DPLLOUTR gt EEV Receiver Data BRGOUT1 Clock TE BRGOUT2 BRGOUT2 NOTE BRGCLK HMODE 19 DPLLCLK HMODE 18 16 TxCLK HMODE 22 20 RxCLK HMODE 26 24 Figure 8 4 Clock Usage Method Diagram ELECTRONICS 8 9 HDLC CONTROLLER S3C2500B In the NRZ NRZI mode the DPLL source clock must be 32 times the data rates In this mode the transmit and receive clock outputs of the DPLL are identical and the clocks are phased so that the receiver samples the data in the middle of the bit cell The DPLL counts the 32x clock using an internal 5 bit counter As the 32x clock is counted the DPLL searches the incoming data stream for edges either positive or negative transition The output of DPLL is High while the DPLL is waiting for an edge in the incoming data stream When it detects a transition the DPLL starts the clock recovery operation The first sampling edge of the DPLL occurs at the counter value of 16 after the first edge is detected in the incoming data stream The second sampling edge occurs following the next 16 When the transition of incoming data occurs at a count value other than 16 the DPLL adjusts its clock outputs during the next 0 to 31 counting cycle by extending or shortening its count by one which effectively moves the edge of the clock sampling the receive data closer to the center of t
84. F X Don t care Table 5 5 External 16 bit Datawidth Store Operation with Big Endian Transfer Width STORE CPU Reg External Memory Bit Num 31 0 31 0 31 0 31 0 CPU Register Data abcd xxab xxxb CPU Address EN EMEN Bit Num 31 31 31 CPU Data Bus D TE aaaa External Address ADDR EA EA TA Bit Num 15 0 15 0 15 0 15 0 15 0 External Data ba dc ba xa bx Timing Sequence as md 2 Table 5 6 External 16 bit Datawidth Load Operation with Big Endian Transfer Width LOAD CPU Reg lt External Memory Bit Num 31 0 31 0 31 0 31 0 CPU Register Data abcd xxab xxxb CPU Address EM EMEN s s Bit Num 31 31 CPU Data Bus p pe TM External Address ADDR EA Ea i Ea TA Bit Num 15 0 15 0 15 0 15 0 External Data ba dc ba ba Timing Sequence Las md 5 8 ELECTRONICS S3C2500B MEMORY CONTROLLER Table 5 7 and 5 8 Using big endian and byte access Program Data path between register and external memory WA Address whose LSB is 0 4 8 C EA External Address HA Address whose LSB is 0 2 4 6 8 C E BA Address whose LSB is 0 1 2 3 4 5 6 7 8 9 A B C D E F X Don t care Table 5 7 External 8 bit Datawidth Store Operation with Big Endian Transfer Width STORE CPU Reg External Memory Bit Num 31 0 15 0 7 0 CPU Register Data abcd xxab CPU Address 31 0 Bit Num 31 0 CPU Data Bus abcd abab External Addr
85. Figure 12 2 GDMA Programmable Priority Registers ELECTRONICS 12 5 GDMA CONTROLLER S3C2500B 12 3 1 1 Problem Solving with Programmable Round Robin S3C2500B has stuff to thing about with arbiter This only applies to arbiter with Round Robin priority Assuming all 0 are set for programmable priority register for Round Robin HPRIR all same bus occupancy in Round Robin and only three of six channels of GDMA are used the problem arises as follows DPRIR Channel Expected Bus Actual GDMA Real System Occupancy Channel Bus Occupancy 0 GDMAO 1 3 GDMA 0 1 6 1 3 GDMA 1 1 6 18 1 6 16 MAD 16 When DPRIR is 0 0 and only GDMA channel 0 1 and 2 are used the expected bus occupancy for each channel is 1 3 However S3C2500B does not work in that way instead GDMA channel 0 gets 4 6 of the bus occupancy GDMA 1 1 6 and 2 1 6 In short 0 is run four times more than 1 and 2 This is because S3C2500B is designed to turn the bus occupancy to the next channel when there is non used channel For instance Number 1 GDMA 0 Number 2 GDMA 1 Number 3 GDMA 2 Number 4 gt to number 5 gt go to number 6 to number 1 0 Number 5 gt to number 6
86. PHY address MPHYaddr The 5 bit address of the PHY device to be read or written 10 Write MPHYwrite To initiate a write operation set this bit to 1 For a read operation clear it to O Busy bit MPHYbusy To start a read or write operation set this bit to 1 The controller clears the Busy bit automatically when the operation is completed 12 Not applicable 15 13 MDC clock rate MMDCrate Controls the MDC period The default value is 011 MDC period MMDCrate x 4 32 Example MMDCrate 011 MDC period 44 x 1 system clock 91 16 Not applicable 7 32 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 4 2 10 CAM Enable Register The CAMEN register indicates which CAM entries are valid using a direct comparison mode Up to 21 entries numbered 0 through 20 may be active depending on the CAM size If the CAM is smaller than 21 entries the higher bits are ignored Table 7 44 CAMEN Register OxF00B0028 CAM enable 0x00000000 CAMENB 0 0000028 CAM enable 0x00000000 Table 7 45 CAM Enable Register Description 20 0 CAM enable Set the bits in this 21 bit value to selectively enable CAM locations 20 through 0 To disable a CAM location clear the appropriate bit 81 21 Not applicable ELECTRONICS 7 33 ETHERNET CONTROLLER S3C2500B 7 4 2 11 MAC Missed Error Count Register The value in the missed error count register MISSCNT indicates the number of frames that
87. RSB Ra Rb Rb LSL n SUB Ra Rt Rb 4 Multiplication by 24n 2 4 8 LSL Ra Rb n MOV Ra Rb LSL n MVN Ra Ra RSB Ra Ra 0 5 Multiplication by 24n 1 3 7 15 LSL Rt Rb n SUB Ra Rb Rb LSL n SUB Ra Rb Rt Multiplication by any C 2 1 2 n 1 2 n or 2 n 1 2 n Effectively this is any of the multiplications in 2 to 5 followed by a final shift This allows the following additional constants to be multiplied 6 10 12 14 18 20 24 28 30 34 36 40 48 56 60 62 2 5 2 5 LSL Ra Ra MOV Ra Ra LSL n ELECTRONICS 3 97 INSTRUCTION SET S3C2500B 3 39 2 GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and remainder routine in both Thumb and ARM code 3 39 2 1 Thumb code signed divide Signed divide of R1 by RO returns quotient in RO remainder in R1 Get abs value of RO into R3 ASR R2 RO 31 Get 0 or 1 in R2 depending on sign of RO EOR RO R2 EOR with 1 OXFFFFFFFF if negative SUB RO R2 and ADD 1 SUB 1 to get abs value always sets flag so go amp report division by 0 if necessary BEQ divide by zero Get abs value of R1 by xoring with OXFFFFFFFF and adding 1 if negative ASR RO R1 31 Get 0 or 1 R3 depending on sign of EOR R1 RO EOR with 1 OxFFFFFFFF if negative SUB R1 RO and ADD 1 SUB 1 to get abs value Save signs 0 or 1 amp for later u
88. Rd 0 1 Instruction memory region 0 MCR MRC p15 0 Rd c6 c3 1 Instruction memory region 3 ELECTRONICS 2 27 PROGRAMMER S MODEL S3C2500B Each protection region register has the format shown in Table 2 16 Table 2 16 CP15 Protection Region Register Format Register bit Function 31 12 Area size See Table 2 17 ERE Region enable Reset to disable 0 The region base must be aligned to an area size boundary where the area size is defined in its respective protection region register The behavior is undefined if this is not the case Area sizes are given in Table 2 17 Table 2 17 Area Size Encoding 4MB 01011 4KB 8MB 10011 2GB 10100 2MB 4GB 01111 64KB 11010 128MB 2 16 1 7 1 Example Base Setting An 8KB size region aligned to the 8KB boundary at 0x00002000 covering the address range 0 00002000 0 00003 would be programmed to 0x00002019 2 28 ELECTRONICS S3C2500B PROGRAMMER S MODEL 2 16 1 8 Register 7 Cache operations A write to this register can be used to perform the following operations e Flush ICache and Dcache e Prefetch an ICache line e Wait for interrupt e Drain the write buffer e Clean and flush the DCache The ARM940T uses a subset of the architecture V4 functions defined in the ARM Architecture Reference Manual The available operations are summarized in Table 2 18 and described below Table 2 18 Cache Operations Writing to Register 7 Baa P
89. S3C2500B DES 3DES 11 3 2 DES 3DES STATUS REGISTER Table 11 3 DES 3DES Status Register Description dp de This bit indicates whether DES 3DES is running or not E These bits have 0 value Available DESINFIFO DESINFIFO is vacant 4 or 2 depends on DESCON 7 words or more this bit is set to 1 Empty DESINFIFO DESINFIFO is vacant all Full DESINFIFO DESINFIFO has 8 words valid data CPU can write in any more This bit has 0 value 8 Valid DESOUTFIFO DESOUTFIFO has 4 2 depends DESCON 7 valid words or more this bit is set to 1 Empty DESOUTFIFO DESOUTFIFO is vacant all 10 Full DESOUTFIFO DESOUTFIFO has 8 words valid data CPU have to read data immediately 11 3 3 DES 3DES INTERRUPT ENABLE REGISTER Table 11 4 DES 3DES Interrupt Enable Register Description 0 Int Idle Interrupt enable register for DES 3DES engine operation 0 Disable 1 Interrupt signal is generated when the status register 0 Idle bit goes to high which means the end of the current DES 3DES operation Int Available Interrupt enable register for input FIFO DESINFIFO DESINFIFO 0 Disable 1 Interrupt signal is generated when the status register 4 E Int Valid DESOUTFIFO Interrupt enable register for output FIFO DESOUTFIFO 0 Disable 1 Interrupt signal is generated when the status register 8 Valid DESOUTFIFO bit goes to high ELECTRONICS 11 5 DES 3DES S3C2500B 11 3 4 DES 3DES
90. Setting this bit TxDTR forces the nDTR pin to Low level When you clear the TxDTR bit nDTR goes High 25 Rx frame discontinue When this bit is set the frame currently received is ignored and the data RxDISCON in this frame is discarded Only the last frame received is affected There is no effect on subsequent frames even if the next frame enters the receiver when the discontinue bit is set This bit is automatically cleared after a cycle 26 Tx no CRC TXNOCRO When this bit is set to 1 the CRC is not appended to the end of a frame by hardware It is used only by the Transmitter Interrupt Mode not by the Transmitter DMA Mode see 8 14 27 Rx CRC When this bit is set to 1 the receiver does not check for CRC by hardware CRC data is always moved to the HRXFIFO 28 Auto enable AutoEN This bit programs the function of both nDCD and nCTS However and RxEN must be set before the nCTS and nDCD pins can be used When this bit is 0 if the nCTS becomes high the transmitter sends mark idle pattern However though the nDCD becomes high the receiver can receive the data When this bit is 1 if the nCTS becomes high the transmitter send mark idle but clears the HTxFIFO and the Tx block If becomes high the receiver can t operate and the HRXFIFO and Rx blocks are cleared this bit set to one in HDLC mode RxFIFO cleared except for receiver So the data in receiver c
91. The System BUS PLL generates system bus clock only The USB PLL generates USB clock The PHY PLL generates clock for external devices Each PLL clock output frequency can be programmed by either the pin setting or software setting In pin configurable mode the CPU FREQ 2 0 pins determine the frequency of the CPU PLL clock output and the BUS FREQ 2 0 pins determine the frequency of the System BUS PLL clock output The USB PLL always generates 4 8 times the input clock i e if the 10MHz input clock is provided the USB clock output is always 48 MHz The PHY FREQ pin determines the frequency of the PHY PLL output The PHY PLL generates 2 times the input clock if the PHY FREQ is 0 and 2 5 times the input clock if the PHY FREQ is 1 The CLKMOD 1 0 pins determine the relation of the ARM940T clock and the system clock If the CLKMOD 1 0 is 00 the fastbus clock mode is defined In this mode the ARM940T clock and the system bus clock is the same clock and the clock is from the CPU PLL output The two clocks are of the same phase and of the same frequency If the CLKMOD 1 0 is 11 the async clock mode is defined In this mode the ARM940T clock is out of the CPU PLL and the system bus clock is out of the System BUS PLL The frequency of the two clocks could be set to any frequency so long as the the frequency of the ARM940T clock is faster than that of the system bus clock The table 4 3 shows the clock configuration of the external pin setti
92. To support future uses of MAC control frames these values are fully programmable in the flow control 100 10M bps Ethernet MAC When the remote Pause operation is completed the transmit status is written to the transmit control frame status register The BDMA engine is responsible for providing an interrupt enable control ELECTRONICS 7 47 ETHERNET CONTROLLER S3C2500B 7 5 4 ERROR SIGNALLING The error abnormal operation flags asserted by the MAC are arranged into transmit and receive groups These flag groups are located either in the transmit status register MACTXSTAT or the receive status register MACRXSTAT A missed frame error counter is included for system network management purposes Normally software does not have enough direct control to examine the status registers directly Therefore the BDMA engine must store the values in system memory so that they can be examined by software 7 5 4 1 Reporting of Transmission Errors A transmit operation terminates when the entire frame preamble SFD data and CRC has been successfully transmitted through the MII without a collision In addition the transmitter block detects and reports both the internal and the network errors Under the following conditions the transmit operation will be aborted in most cases Parity error The 8 bit of data incoming through the BDMA has an optional parity bit A parity bit also protects each byte in the MTxFIFO If a parity error occurs the t
93. TxSCTS 0 Normal operation 1 A transition occured at the nCTS input This transition can be used to trigger an interrupt 8 Tx underrun TxU 0 Normal operation 1 The transmitter ran out of data during transmission 9 Rx FIFO available RxFA 0 Normal operation 1 Data is available in the RxFIFO 10 Tx Frame Good TxFG 0 Normal operation 1 Tx Data sent well 11 Rx flag detected RxFD 0 Normal operation 1 This bit is set when the last bit of the flag sequence is received 12 Rx data carrier detected RXDCD 0 nDCD input pin is High 1 2 nDCD input pin is Low 13 Rx stored data carrier detected RXSDCD 0 Normal operation 1 When a transition of the nDCD input occurs this bit is set 14 Rx frame valid RxFV 0 Normal operation 1 The last data byte if a frame is transferred into the last location of RxFIFO 15 Rx idle RxIDLE 0 Normal operation 12A minimum 15 consecutive 1 s have been received Figure 8 15 HDLC Status Register 8 40 ELECTRONICS S3C2500B HDLC CONTROLLER moJo xzu 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 16 Rx abort R x 0 Normal operation 1 Seven or more consecutive 1s have been received in frame condition 17 Rx CRC error RXCRCE 0 Normal operation 1 A frame Rx operation is completed with a CRC error 18 Rx non octet align RXNO 0 Received
94. arbitration method and address remap function etc 4 2 FEATURES Key features of the system configuration include the following Various clock mode operation the fastbus mode sync mode and async mode Product code and revision number System clock control clock status Peripheral clock enable disable AHB bus master priority define Fixed Round Robin Core System USB PHY PLL Configuration Register Setting ELECTRONICS 4 1 SYSTEM CONFIGURATION S3C2500B 4 3 ADDRESS MAP Internal Register OxF0000000 0x88000000 SDRAM 1 0x80000000 0x48000000 SDRAM 0 0x40000000 0x08000000 EXT Bank 7 0x07000000 0x06000000 0x05000000 0x04000000 0x03000000 0x02000000 0x01000000 0x00000000 Figure 4 1 S3C2500B Address map after resest Each memory block is mapped within the fixed location of memory space As shown in the figure 4 1 the maximum size ROM SRAM Flash External IO bank is restricted to 16M bytes and the SDRAM bank can be mapped within 1G byte memory space It must be noticed that the base address of each bank is fixed and the bank size is variable Although the SDRAM bank size are up to 1G bytes in the figure 4 1 the possible maximum size is 128M bytes because the sdram controller can supports 256M bit sdram component 4 2 ELECTRONICS S3C2500B SYSTEM CONFIGURATION 4 4 REMAP OF MEMORY SPACE The S3C2500B supports the address remap function When the remap functio
95. around main memory 3 11 1 THE REGISTER LIST The instruction can cause the transfer of any registers in the current bank and non user mode programs can also transfer to and from the user bank see below The register list is a 16 bit field in the instruction with each bit corresponding to a register A 1 in bit of the register field will cause RO to be transferred a 0 will cause it not to be transferred similarly bit 1 controls the transfer of R1 and so on Any subset of the registers or all the registers may be specified The only restriction is that the register list should not be empty Whenever R15 is stored to memory the stored value is the address of the STM instruction plus 12 31 2827 25 2423 22 21 20 19 16 15 0 e v sIw L D 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 PSR amp Force User Bit 0 Do not load PSR or user mode 1 Load PSR or force user mode 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset bofore transfer 31 28 Condition Field Figure 3 18 Block Data Transfer Instructions 3 40 ELECTRONICS S3C2500B INSTRUCTION SET 3 11 2 ADDRESSING MODES The transfer addresses are determined by the contents of the base register Rn the pre p
96. frame continue address Then the transmission of the frame data starts automatically The bytes of the frame continue to be written into the Tx FIFO as long as data is written to the frame continue address The HDLC logic keeps track of the field sequence within the frame The frame is terminated when the last frame data is written to the Tx FIFO s terminate address The FCS field is automatically appended by hardware along with a closing flag Data for a new frame can be loaded into the Tx FIFO immediately after the previous frame data if TxFA is 1 The closing flag can serve as the opening flag of the next frame or separate opening and closing flags can be transmitted If a new frame is not ready to be transmitted a flag time fill or mark idle pattern is transmitted automatically If the Tx FIFO becomes empty at any time during the frame transmission an underrun occurs and the transmitter automatically terminates the frame by transmitting an abort The underrun state is indicated when the transmitter underrun status bit TxU is 1 Whenever you set the transmission abort control bit TxABT in HCON the transmitter immediately aborts the frame transmits at least eight consecutive 1s clearing the Tx FIFO If the transmission abort extension control bit TXABTEXT is set at the time an idle pattern at least 16 consecutive 1s is transmitted An abort or idle in an out of frame condition can be useful to gain 8 or 16 bi
97. incrementing the addresses for each word Write back the updated value of RO 3 90 ELECTRONICS S3C2500B INSTRUCTION SET 3 35 FORMAT 16 CONDITIONAL BRANCH 15 14 13 12 11 8 7 0 7 0 8 bit Signed Immediate 11 8 Condition Figure 3 45 Format 16 3 35 1 OPERATION The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction The THUMB assembler syntax is shown in the following table Table 3 23 The Conditional Branch Instructions kuqa i Assembler Branch if Z set equal Branch if Z clear not equal Branch if C set unsigned higher or same Branch if C clear unsigned lower Branch if N set negative Branch if N clear positive or zero Branch if V set overflow Branch if V clear no overflow Branch if C set and Z clear unsigned higher Branch if C clear or Z set unsigned lower or same 1010 BGE label BGE label Branch if N set and V set or N clear and V clear greater or equal ELECTRONICS 3 91 INSTRUCTION SET S3C2500B Table 3 23 The Conditional Branch Instructions Continued Code THUMB ARM Equivalent Assembler 1011 BLT label BLT label Branch if N set and V clear or N clear and V set less than 1100 BGT label BGT label Branch if Z clear and either N set and V set or N clea
98. or 10M b s HDX Table 7 54 STA Frame Structure Description Preamble Start of Operation PHY Register Turnaround Frame Code Address Address Write 11111111 01 write 5 bit 5 bit 0 2 bit 16 bit Command 32 bit register value Read Status 11111111 0 read 5 bit 5 bit 16 bit 32 bit register value Direction STA to PHY Direction PHY to STA ELECTRONICS 7 45 ETHERNET CONTROLLER S3C2500B 7 5 3 FULL DUPLEX PAUSE OPERATIONS Flow control can be done by the use of control frames The receive logic in the flow control block recognise a MAC control frame as follows The current specification for full duplex flow control specifies a special destination address for the Pause operation frame In order for the MAC to receive frames that contain this special destination address the address must be programmed in one of the CAM entries This CAM entry must then be enabled and the CAM activated Some CAM entries are also used when generating a flow control frame using the MSdPause bit in the MACTXCON register length type field is a 2 octet field that shall contain the hexadecimal value 88 08 The frame length must be at least 64 bytes including CRC The CRC must be valid and the frame must contain a valid pause opcode and a parameter pause period field If the length type field does not have the special value specified for MAC control frames the MAC takes no action and the frame is treated as a normal
99. since the assembler places 1 gt gt 2 the Offset5 field ELECTRONICS 3 81 INSTRUCTION SET S3C2500B 3 28 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 16 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples LDR R2 R5 116 Load into R2 the word found at the address formed by adding 116 to R5 Note that the THUMB opcode will contain 29 as the Offset5 value STRB R1 R0 13 Store the lower 8 bits of R1 at the address formed by adding 13 to RO Note that the THUMB opcode will contain 13 as the Offset5 value 3 82 ELECTRONICS S3C2500B INSTRUCTION SET 3 29 FORMAT 10 LOAD STORE HALF WORD 10 6 5 3 2 0 14 2 0 Source Destination Register 5 3 Base Register 10 6 Immediate Value 11 Load Store Flag 0 Store to memory 1 Load from memory Figure 3 39 Format 10 3 29 1 OPERATION These instructions transfer half word values between a Lo register and memory Addresses are pre indexed using a 6 bit immediate value The THUMB assembler syntax is shown in Table 3 17 Table 3 17 Half word Data Transfer Instructions THUMB Assembler ARM Equivalent STRH Rb lmm STRH Rb 1 lmm to base address in Rb and store bits 0 15 of Rd at the resulting address LDRH Rb LDRH Rd Rb
100. source data1 gt source data2 gt source data3 gt destination data0 gt destination data1 gt destination data2 gt destination data3 Figure 12 12 Single and Four Data Burst Mode Timing ELECTRONICS 12 21 GDMA CONTROLLER S3C2500B 12 6 3 BLOCK AND ONE DATA BURST MODE DCON 3 1 001 4 1 5 0 xGDMA Req and xGDMA Ack signals are active high transfers data from single Req signal till Transfer Count Register DTCR consumes to 0 Recommand deasserted time xGDMA Req xGDMA Ack EE EE Programmable b rogrammable b DCON 16 13 DCON 16 13 Address SAO DAO SA1 DA1 C NOTE is in the block mode starts to operate with first signal So in the ideal case does not the number of xGDMA Req signal pulse But recommand that xGDMA siganl is deasserted when xGDMA signal is active state Figure 12 13 Block and One Data Burst Mode Timing 12 22 ELECTRONICS S3C2500B GDMA CONTROLLER 12 6 4 BLOCK AND FOUR DATA BURST DCON 3 1 001 4 1 5 1 This timing diagram is the same with block and one data burst except that it is four data burst Recommand deasserted time xGDMA Req XGDMA Ack 9 Programmable b DCON 16 13 NOTE is in the block mode starts to operate with first Req signal So the ideal case GDMA does not care the number of xGDMA signal pulse But
101. ti u u OY s 12 3 14 GDMA Programmable Priority Registers 12 3 2 GDMA Control teta ates telo assit tk atta daba atender 12 3 3 GDMA Source Destination Address Registers 12 3 4 GDMA Transfer Count Registers 12 3 5 Run Enable 12 3 6 GDMA Interrupt Pending Register 12 4 GDMA Mode Operation 12 4 50 Mode scu s s s t D L D D DS D D D D SSS 12 4 2 External GDMA Request Mode 12 4 3 HUART Mode 12 4 DES ModE Mm 12 5 GDMA Function Description Te Sa ODMA un 12 5 2 Starting Ending GDMA Transfers 12 5 3 Data Transfer Modes 12 6 GDMA Transfer Timing Datan a datis caisse br tex patate tete eia us asas 12 6 1 Single and One Data Burst 12 6 2 Single and Four Data Burst Mode 12 6 3 Block and One Data Burst Mode 12 6 4 Block and Four Data Burst S3C2500B RISC MICROCONTROLLER L lobos xiii Table of Contents Continued Chapter 13 Serial I O Console UART IRSE 13 1 19 2 Features e ie bes 13 1 13 3 Console UART Special 13 3 13 3 1 Console UART Control Registers nennen nennen nennen nnns 13 4 13 3 2 Console UART S
102. 0 Frame Number W Frame Number from SOF packet FN 81 11 Reserved 1 1 10 0 Frame Number FN 31 11 Reserved Figure 10 10 USBFN Register ELECTRONICS 10 19 USB CONTROLLER S3C2500B 10 5 6 USB DISCONNECT TIMER REGISTER This register turns USB bus into disconnected state First You set the disconnect interval time in the connect register Next set the enable bit USBDISCONN 31 Then the disconnect logic keeps the line state in SEO Single Ended Zero After that interval time any hub can detect our device as just connected Finally bus reset will be started again You could calculate wait time period by below CNTVLE Table Table 10 12 CNTVLE Table 223 202 2 1 0 Disconnect Time 2 CNTVLE 7 x 20 8333ns x x x x ijo 00025509 ts SS 719191919191 IET NOTE X means don t care Table 10 13 USBDISCONN Register USBDISCONN 0 0014 R W USBDISCONNect register 0x00000001 Table 10 14 USBDISCONN Register Description M 22 0 CouNT VaLuE R Disconnect duration time value CNTVLE 80 23 31 DISconnect 0 No operation operation STaRT 1 Both D D go to 0 and all USB registers can t DISSTRT read written until USBINTR 11 is set 10 20 ELECTRONICS S3C2500B ELECTRONICS USB CONTROLLER CNTVLE 22 0 CouNT VaLuE CNTVLE 23 30 Reserved 31 DISconnet operation STaRT DISSTRT 0 No operation 1
103. 0x00000000 ELECTRONICS 15 11 VO PORTS S3C2500B NOTES 15 12 ELECTRONICS S3C2500B INTERRUPT CONTROLLER INTERRUPT CONTROLLER 16 1 OVERVIEW The S3C2500B interrupt controller has a total of 39 interrupt sources Interrupt requests can be generated by internal function blocks or external pins The 940 core recognizes two kinds of interrupts a normal interrupt request IRQ and a fast interrupt request FIQ Therefore all 53 2500 interrupts can be categorized as either IRQ or FIQ The S3C2500B interrupt controller is level sensitive to each interrupt source Three special registers are used to control interrupt generation and handling Interrupt priority registers INTPRIORn The index number of each interrupt source is written to the pre defined interrupt priority register field to obtain that priority The interrupt priorities are pre defined from 0 0 to 0x26 Interrupt mode register INTMOD EXTMOD Defines the interrupt mode IRQ or for each interrupt source Interrupt mask register INTMASK EXTMASK Indicates that the current interrupt has been disabled if the corresponding mask bit is 1 If an interrupt mask bit is the interrupt will be serviced normally If the global mask bit bit 31 of EXTMASK register is set to 1 no interrupt is serviced When the global mask bit has been set to 0 the interrupt is serviced 16 2 FEATURES e Supports IRQ and FIQ Interrupt Request
104. 1 invalid byte 1022 invalid bytes 11 3 invalid bytes 14 DMA Tx stop or skip This bit determines a DMA Tx stop or skip when DMA has not the DTxnSTSK ownership associated with the Tx buffer descriptor DMA Tx is disabled in this condition when this bit is not set 0 Not Owner Tx stop 1 Not Owner Tx BD skip 15 DMA Rx stop or skip This bit determines a DMA Rx stop or skip when DMA has not the DRxnSTSK ownership associated with the Rx buffer descriptor If this bit is not set DMA Rx is disabled 0 2 Not Owner Rx stop 1 2 Not Ower Rx BD skip 16 DMA Rx memory This bit determines whether the address is incremented or decremented address decrement If this bit is set to 1 then the address will be decremented DRxMADEC 17 Tx flag idle TxFLAG This bit selects the flag fill mode active idle or the mark idle mode inactive idle for the transmitter The selected active or inactive idle state continues until data is sent after nRESET has return to High level The flag idle pattern is 7EH the mark idle pattern is FFH 18 Tx single flag This bit controls whether separate closing and opening flags are TxSFLAG transmitted in succession to delimit frames When this bit is O independent opening and closing flags are transmitted in order to separate frame When this bit is set to 1 the closing flag of the current frame serves as the opening flag of the next frame Loop back mode nCTS and nDCD inputs ar
105. 10 BACON 5 22 5 11 Bank n Control BACON Register 5 24 5 12 Muxed Bus Control MUXBCON Register Configuration 5 26 5 13 Wait Control WAITCON Register Configuration 5 28 xvi i i S3C2500B RISC MICROCONTROLLER List of Figures continued Figure Title Page Number Number 5 14 Read Timing Diagram 1 99 5 29 5 15 Write Timing Diagram a 5 30 5 16 Read Timing Diagram 2 5 31 5 17 Write Timing 2 5 32 5 18 Read after Write at the Same Bank COHDIS 1 5 33 5 19 Read Timing Diagram Muxed Bus sse 5 34 5 20 Write Timing Diagram Muxed 5 35 5 21 Write Timing Diagram nnne 5 36 5 22 Write Timing Diagram 5 37 5 23 SDRAM Configuration Register 0 5 49 5 24 SDRAM Command 5 51 5 25 SDRAM Refresh Timer 5 52 5 26 SDRAM Write Buffer Time out 5 53 5 27 Single Read Operation CAS 2 5 54 5 28 Single Read Operation CAS 3
106. 14 29 SERIAL I O HIGH SPEED UART S3C2500B IR Transmit Frame Data Bits Bit frame T 13 16 Figure 14 24 Infra Red Receive Mode Frame Timing Diagram 14 30 ELECTRONICS S3C2500B VO PORTS PORTS 15 1 OVERVIEW S3C2500B has 64 programmable ports I O port function control registers 2 upper word IOPCON 1 lower word select either function s port or GPIO If IOPCON1 2 register is set to GPIO IOPMODE 1 2 register should be set to either input mode or output mode For example if you select IOPCON1 2 for GPIO and 1 2 for input then I O port can be used for GPIO input mode When the value is latched in IOPDATA1 2 register CPU can read IOPDATA1 2 register value If you select IOPCON1 2 for GPIO and IOPMODE 1 2 for output then CPU can write the data to IOPDATA1 2 register and the value can be transferred to the output port I O Ports Pad Ports or PP d Function s Port GPIO JE Input Mode Output Mode If you select IOPCON1 14 for xGDMA Req 0 then the port is used for Req port mode 1 0 port signal decision register is used when IOPCON 1 is selected for Req Ack IOPGDMA controls external Req Ack signals IOPEXTINTPND register is used for external interrupt status IOPEXTINTPND is set when external interrupt is generated and is cleared when IOPEXTINTPND register is re written to 1 15 2 FEATURES e 64 Programmable I O Ports e Configurab
107. 16 7 Table 16 5 Interrupt Priority Register RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 wremoro o o Pmonmvs JoJo Joo monmvi o o PRIORI tow oo mnm o o folo 5 ofo Priority 0 0 PRIORITY lolo PRIORTYi0 fofo PRioRmYe Jojo Prionns 0 0 PRIORTYI5 lolo Pmommvi4 ofo o o PRIORTYI2 0 0 lolo 0 0 7 Jofo PRIORITY16 0 0 PRIORTY23 lolo PRIORTY22 0 0 o o PRIORITY20 Pomme oo Pmonmves olo 2 o o PRIORITY24 o Pmommvs lolo ofo PnionTv2 Jojo 28 o Pmommvss oo Pmommvs ofo o o 22 Hion WremoRo o o o o o o o Pmommvss o o o o PRIORITYa6 fv High Priority Low Priority Figure 16 5 Interrupt Priority Register INTPRIORn 16 8 ELECTRONICS S3C2500B INTERRUPT CONTROLLER 16 4 4 INTERRUPT OFFSET REGISTER The interrupt offset registers INTOFFSET FIQ and INTOFFSET contain the interrupt offset address of the interrupt which has the highest priority among the pending interrupts The content of the interrupt offset address is index value of the i
108. 19 0 activelow 1 active high 18 0 filtering off 1 filtering on 17 16 00 level detection 01 rising edge detection 10 falling edge detection 15 12 Control external interrupt request3 input for port 11 xINT3 15 0 activelow 1 active high 14 0 filtering off 1 filtering on 13 12 00 level detection 01 rising edge detection 10 falling edge detection 11 8 Control external interrupt request2 input for port 10 xINT2 11 0 activelow 1 active high 10 0 filtering off 1 filtering on 9 8 00 level detection 01 rising edge detection 10 falling edge detection 7 4 Control external interrupt request1 input for port 9 xINT1 7 0 active low 1 active high 6 0 filtering off 1 filtering on 5 4 00 level detection 01 rising edge detection 10 falling edge detection 3 0 Control external interrupt requestO input for port 8 XINTO 3 0 active low 1 active high 2 0 filtering off 1 filtering on 1 0 00 level detection 01 rising edge detection 10 falling edge detection Figure 15 5 I O Port Control Register for External Interrupt IOPEXTINT ELECTRONICS 15 9 VO PORTS S3C2500B 15 3 5 PORT EXTERNAL INTERRUPT CLEAR REGISTER IOPEXTINTPND External interrupt clear register IOPEXTINTPND is set when external interrupt is generated and you can clear the interrupt status by writing the IOPEXTINTPND status register to 1 Table 15 6 IOPEXT
109. 2 Descriptor BRxNBD BDMA Rx word alignment The Rx word alignment bits determine how many bytes are BRxWA invalid in the first word of each data frame These invalid bytes are inserted when the word is assembled by the BDMA 00 No invalid bytes 01 1 invalid byte 10 2 invalid bytes and 11 3 invalid bytes Not applicable Rx Byte Swapping Use to prevent disorder of byte sequence when memory operate BRxBSWAP on big endian format and byte unit access If this bit is set the reception byte is swapped B3 B2 B1 B0 gt B0 B1 B2 B3 Not applicable BI Factoriattestbits BDMA Rx enable BRxEn When the Rx enable bit is set to 1 the BDMA Rx block is enabled Even if this bit is disabled buffer data will be moved to the BDMA RxBUFF until the MAC RxFIFO underflows This bit is automatically disabled when the BDMA is not the owner NOTE The buffer descriptor start address pointer must be assigned before this bit is set 11 BDMA Rx reset BRxRS Set this bit to 1 to reset the BDMA Rx block JReseved 7 16 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 4 1 3 BDMA Transmit Buffer Descriptor Start Address Register Table 7 8 BDMATXDPTR Register BDMATXDPTRA 0 0 0008 BDMA Tx buffer descriptor base register 0x00000000 0 00 0008 BDMA Tx buffer descriptor base register 0x00000000 Table 7 9 BDMA Transmit Buffer descr
110. 2 x Timer data value Interval Mode 4 Time out Time out Time out fTOUT Toggle Mode Initial TOUTn is 0 A A A Time out Time out Time out Figure 17 1 Timer Output Signal Timing 17 2 ELECTRONICS S3C2500B 32 BIT TIMERS 17 5 TIMER OPERATION GUIDELINES The block diagram in Figure 17 2 shows how the 32 bit timers are configured in the S3C2500B The following guidelines apply to the timer functions When timer is enabled it loads a data value TDATA to its count register TCNT and begins decrement of the count register value When the count register TCNT reaches to zero the associated interrupt is generated The base value TDATA is then reloaded to the count register TCNT and the timer continues decrement of its count register value If a timer is disabled you can write a new base value into its registers TDATA If the timer is halted while it is running the base value is not automatically re loaded 32 Bit Timer Data Register TDATAn INTMASK fSYSCLK gt 32 Bit Timer Count Register TCNTn TMOD TEn Down Counter Interrupt Request TMOD TMDn TMOD TCLRn Port 22 27 Data Out Figure 17 2 32 Bit Timer Block Diagram ELECTRONICS 17 3 32 BIT TIMERS S3C2500B 17 6 TIMER SPECIAL REGISTER 17 6 1 TIMER MODE REGISTER The timer mode register TMOD is used to control the operation of the six 32 b
111. 4 0 100 0 1000 4 0 100 0 1000 4 0x100C 0x1000 4 S3C2500B ELECTRONICS S3C2500B INSTRUCTION SET 0x100C xt 00 0x1000 0x1000 4 1 0 0x1000 4 Figure 3 22 Pre Decrement Addressing 3 11 4 USE OF THE S BIT When the S bit is set in a LDM STM instruction its meaning depends on whether or not R15 is in the transfer list and on the type of instruction The S bit should only be set if the instruction is to execute in a privileged mode 3 11 4 1 LDM with R15 in Transfer List and S Bit Set Mode Changes If the instruction is a LDM then SPSR mode is transferred to CPSR at the same time as R15 is loaded 3 11 4 2 STM with R15 in Transfer List and S Bit Set User Bank Transfer The registers transferred are taken from the user bank rather than the bank corresponding to the current mode This is useful for saving the user state on process switches Base write back should not be used when this mechanism is employed 3 11 4 3 R15 not in List and S Bit Set User Bank Transfer For both LDM and STM instructions the user bank registers are transferred rather than the register bank corresponding to the current mode This is useful for saving the user state on process switches Base write back should not be used when this mechanism is employed When the instruction is LDM care must be taken not to read from a banked regis
112. 64 The second one is the left half of data encrypted decrypted bit 1 32 The byte order in the DESOUTFIFO is LSB first That is the LSB byte is read from DESOUTFIFO 31 24 If you need to swap the byte order you can control it by using DESCON 10 If DESCON 10 is set the read data from the DESOUTFIFO is automatically byte swapped Otherwise the read data have the original byte order ELECTRONICS 11 9 DES 3DES S3C2500B 11 4 DES 3DES OPERATION The 64 bit data to be encoded should be written to DESINFIFO of DES 3DES block by CPU or DMA When the data conversion is completed the Valid DESOUTFIFO bit in DESSTA is set to 1 and the CPU DMA can read the encrypted data from the DESOUTFIFO The DESINFIFO and DESOUTFIFO consists of eight 32 bit registers that are used for data storage The DESINFIFO has two data request options for data transmission which is controlled by DESCON 7 When the DESCON T is set to 0 the Available DESINFIFO status means that DESINFIFO is empty for 4 word It is recommended when DMA mode is selected When the DESCON T is set to 1 the Available DESINFIFO status means that DESINFIFO is empty for 2 word It is recommended when CPU mode is selected Similarly the DESOUTFIFO has two data request options for data receiving which is controlled by DESCON 7 When the DESCON T is set to 0 the Valid DESOUTFIFO status means that DESOUTFIFO has at least 4 word Valid data It is recommended when DMA mode is select
113. 7 Sign Flag 0 Offset is positive 1 Offset is negative Figure 3 42 Format 13 3 32 1 OPERATION This instruction adds a 9 bit signed constant to the stack pointer The following table shows the THUMB assembler syntax Table 3 20 The ADD SP Instruction S THUMB Assembler ARMEquivalent 0 ADD SP ADD R13 R13 Imm Add Imm to the stack pointer SP ADD SP Imm SUB R13 R13 Add Imm to the stack pointer SP NOTE The offset specified by lmm can be up to 508 but must be word aligned ie with bits 1 0 set to 0 since the assembler converts lmm to 8 bit sign magnitude number before placing it in field SWord7 The condition codes are not set by this instruction 3 32 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 20 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples ADD SP 268 SP R13 SP 268 but don t set the condition codes Note that the THUMB opcode will contain 67 as the Word7 value and S 0 ADD SP 44 104 SP R13 SP 104 but don t set the condition codes Note that the THUMB opcode will contain 26asthe Word7 value and S 1 ELECTRONICS 3 87 INSTRUCTION SET S3C2500B 3 33 FORMAT 14 PUSH POP REGISTERS 15 14 13 11 10 7 0 12 9 8 pots ts te ts Jol 7 0 Register List 8 PC LR Bit
114. 7 20 Rx Buffer Descriptor Maximum Count 8 54 S3C2500B RISC MICROCONTROLLER Table of Contents Continued Chapter 9 IOM2 amp TSA Controller MM MM MM C E C MA 9 1 S MUI RIED NEC 9 1 OS BUSH 9 2 9 3 1 9 3 9 32 Cea ban rS 9 3 9 3 3 Monitor Channels 9 3 9 3 4 Command Indicate 9 3 9 3 5 Intercommunication Channels nennen nnne nnne 9 3 9 3 5 FIG Buses vacate NEA EAD EE LARA EA AE E ERA MEE 9 3 9 3 7 Channel 9 4 9 4 TSA Time Slot 9 9 Qe ANOVEIVIOW E RNC 9 9 9 4 2 TSA Block 9 9 9 4 3 HDLC External Pin Multiplexed 9 10 4 4 0 c p 9 10 9 5 2 Special 9 11 9 5 1 IOM2CON 2 2 9 12 9 5 2 IOM2 Status 9 14 9 5 3 I
115. 8 1 Operand 3 25 3 26 3 8 3 Instruction Cycle 3 26 3 8 4 Assembler 3 27 3 9 Single Data Transfer LDR 1 0 6 00 3 28 3 9 1 Offsets and 0 3 29 3 9 2 Shifted Register Offset 3 29 3 9 3 Bytes and 0 044440000004 tad 3 29 SOA Seol PIU PES 3 31 3 9 5 Restriction the Use of Base 3 31 3 9 6 3 ADOS P elec MAK 3 31 3 9 7 Instruction Cycle n 3 31 3 9 8 Assembler 3 32 iv S3C2500B RISC MICROCONTROLLER Table of Contents Continued Table of Contents Continued Chapter 3 Instruction Set Continued 3 10 Halfword and Signed Data Transfer _ 5 3 10 1 Offsets and 9 3 10 2 Half Word Load and 3 10 3 Signed Byte Half Word 3 10 4 Endi
116. 88 3 22 The Multiple Load Store 5 3 90 3 23 The Conditional Branch Instructions 3 91 3 24 3 92 3 25 Summary of Branch 10 nnns 3 93 3 26 THe BE e FREE 3 94 4 1 The Base Address of Remapped 4 3 4 2 AHB Bus Priorities for 4 4 4 3 Clock Frequencies for CLKMOD Pins CPU FREQ Pins and BUS FREQ Pins 4 9 4 4 M S values of the 53 2500 4 13 4 5 System Configuration 2 0000 4 15 S3C2500B RISC MICROCONTROLLER List of Tables continued Table Title Page Number Number 5 1 Base Address of Each nennen 5 3 5 2 5 5 5 3 External 32 bit Memory Store Operation with Big Endian 5 7 5 4 External 32 bit Memory Load Operation with Big Endian 5 7 5 5 External 16 bit Store Operation with 5 8 5 6 External 16 bit Load
117. Abort MRxABT 0 normal 1 Monitor channel transmission aborted 6 Monitor Collision MCOL 0 Normal 1 Monitor channel collision detected 7 Monitor Transmit Buffer Available MTxBA 0 Normal 1 Monitor tx buffer empty 8 Monitor Receive Buffer Available MRxBA 0 Normal 1 Monitor rx buffer data ready 9 Monitor Transmit Abort Detected MTxABT 0 Normal 1 Monitor channel Tx abort received 10 IC Buffer Available ICBA 0 Normal 1 IC buffer available 11 ALIVE ALIVE 0 IOM2 bus is in the inactive state DCL 1 1 IOM bus is in the active state DCLK is clocking 12 NEWFSC NEWFSC 0 Normal 1 fsc rising edge detected Figure 9 8 IOM2 Status Register ELECTRONICS 9 15 IOM2 CONTROLLER S3C2500B 9 5 3 2 INTERRUPT ENABLE REGISTER Table 9 5 IOM2INTEN Register Interrupt Enable Register Rw IOM2INTEN 0xF0130008 Interrupt Enable Register 0x00000000 _ C 0 2 3 4 5 6 7 8 9 9 16 ELECTRONICS S3C2500B IOM2 CONTROLLER 13 12 11 m 02 x x 2 o 0 CI 0 Buffer Available Interrupt Enable CIOBAIE 0 Disable 1 Enable 1 Reserved 2 Cl 1 Buffer Available Interrupt Enable CITBAIE 0 Disable 1 Enable 3 Reserved 4 Monitor Received End of Frame Interrupt Enable MRxEOMIE 0 Disable 1 Enable 5 Monitor Received Abort Interrupt Enable MRxABTIE 0 Disable 1 Enable 6 Moni
118. Both D D go to 0 and all USB registers R W blocked Figure 10 11 USBDISCONN Register 10 21 USB CONTROLLER S3C2500B 10 5 7 USB ENDPOINT 0 COMMON STATUS REGISTER This register includes the control bits status bits and max packet size value for endpoint 0 Table 10 15 USBEPOCSR Register USBEPOCSR 0 0018 USB Endpoint 0 Common Status Register 0x00000001 Table 10 16 USBEPOCSR Register Description 3 0 size If 3 0 is 0000 then MAXPsize is 0 byte value MAXP If MAXP 3 0 is 0001 then MAXPsize is 8 bytes If MAXP 3 0 is 0010 then MAXPsize is 16 bytes If MAXP 3 0 is 0011 then MAXPsize is 24 bytes If MAXP 3 0 is 0100 then MAXPsize is 32 bytes If MAXP 3 0 is 0101 then MAXPsize is 40 bytes If MAXP 3 0 is 0110 then MAXPsize is 48 bytes If MAXP 3 0 is 0111 then MAXPsize is 56 bytes If MAXP 3 0 is 1000 then MAXPsize is 64 bytes 7 size 0 USBEPOCSR 3 0 isn t overwritten when MCU SETtable writes a 32bit value to USBEPOCSR register MAXPSET 1 USBEPOCSR 3 0 is overwritten 23 8 24 Out packet This is a Read Only bit ReaDY The USB sets this bit once a valid token is written to the FIFO An interrupt is generated when the USB sets this bit The MCU clears this bit by writing a 1 to the SVORDY 25 IN packet The MCU sets this bit after writing a packet of data ReaDY into endpoint 0 FIFO INRDY The USB clears this bit once the packet has been successfully sent
119. CAM block accepts the destination address the MRxFIFO stores the rest of the frame Any error in reception will reset the MRxFIFO and the state machine will wait for the end of the current frame It will then be idle while it is waiting for the next preamble and SFD 7 3 5 5 BDMA Interface Receive State Machine The BDMA I F receive state machine issues the Rx rdy signal whenever data is present in the receive FIFO last byte of the packet is signaled by asserting the Rx EOF In case there are any errors during the reception or if there is CRC error at the end the BDMA I F receive state machine asserts the Rx toss signal to indicate that the received packet should be discarded 7 6 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 3 6 FLOW CONTROL BLOCK Flow control is done using the MAC control frame The receiver sends control frames to the transmitter and the transmitter pauses its operation during the time interval specified in the control frames The flow control block provides the following functions e Recognition of MAC control frames received by the receiver block e Transmission of MAC control frames even if transmitter is paused e Timers and counters for pause operation e Command and status register CSR interface e Options for passing MAC control frames through to software drivers For details refer to the full duplex pause operation section in this chapter 7 3 7 BUFFERED DMA BDMA OVERVIEW The BDMA engine co
120. CRC mode 1 CRC mode 18 Little Endian Mode E 0 Big Endian 1 Little Endian 19 Last L 0 This is not the last buffer in the frame 1 This is the last buffer int the frame 20 Buffer Data Pointer Decrement D 0 Increment 1 Decrement 22 21 Widget Alignment Control WA 00 No invalid bytes 01 1 invalid bytes 1022 invalid bytes 1123 invalid bytes Tx Status Bit These bit may be regarded as valid when the L bit in Tx control bit is set 26 Transmission completion T 0 Normal 1 One frame completed 31 Ownership 0 CPU 0 1 Figure 8 10 Transmit Buffer Descriptor ELECTRONICS 8 21 HDLC CONTROLLER S3C2500B 8 6 2 RECEIVE BUFFER DESCRIPTOR Buffer Pointer fF Rx Control Bits Buffer Length 31 0 Buffer Data Pointer 15 0 Buffer Length Rx Status Bits These bits may be regarded as valid when L bit in Rx status bit is set 16 CD Lost CD 0 Normal 1 CD lost occurs 17 CRC Error CE 0 Normal 1 CRC error occurs to the frame received 18 Non octet Aligned Frame NO 0 Normal 1 Non octet aligned frame is received 19 Overrun OV 0 Normal 1 The received frame overruns 20 DPLL Two Miss DTM 0 Normal 1 DPLL two miss clock occurs 21 Rx Abort ABT 0 Normal 1 The received frame aborted 22 First In Frame F 0 This buffer descriptor status is not the first to the frame 1 This buffer descriptor status is the fir
121. Controller ELECTRONICS 1 1 PRODUCT OVERVIEW 1 2 FEATURES ARM940T Core processor Fully 16 32 bit RISC architecture Harvard cache architecture with separate 4KB Instruction and Data cache Protection unit to partition memory and set individual protection attributes for each partition AMBA Bus architecture Up to 166MHz operating frequency Memory Controller 24 Bit External Address Pins 2 Banks for SDRAM with 16 32 bit external bus 8 Banks for Flash ROM SRAM External with 8 16 32 bit external bus One External Bus Master with Bus Request Acknowledge Pins Ethernet Controllers 1 2 Buffered DMA BDMA engine using burst mode BDMA Tx Rx buffers 256 byte 256 byte MAC Tx Rx FIFOs 80 byte 16 byte to support re transmit after collision without DMA request Data alignment logic Support for old and new media compatible with existing 10M bit s networks 10 100 Mbps operation to increase price performance options and to support phased conversions Full IEEE 802 3 compatibility for existing applications Media Independent interface MII or 7 wire interface Station management STA signaling for external physical layer configuration and link negotiation 3C2500B On chip CAM 21 addresses Full duplex mode for doubled bandwidth Pause operation hardware support for full duplex flow control Long packet mode for specialized environments Short packet mode for fast testing PAD generation fo
122. GDMA Req GDMA Ack Port 18 Data IOPCON1 18 xGDMA Ack1 Port 19 Data IOPCON1 19 xGDMA_Ack2 Port 20 Data IOPCON1 20 xGDMA_Ack3 Port 21 Data 11211 Figure 12 1 GDMA Controller Block Diagram ELECTRONICS S3C2500B GDMA CONTROLLER 12 3 GDMA SPECIAL REGISTERS Table 12 1 GDMA Special Registers Overview OxF0051000 0 0052000 0 0053000 OxF0050000 OxF0050004 OxF0050008 OxF005000C OxF0050010 OxF0050014 OxF0050020 OxF0050024 OxF0050028 OxF005002C 0 0050030 OxF0050034 OxF0050040 OxF0050044 OxF0050048 OxF005004C OxF0050050 OxF0050054 OxF0050060 OxF0050064 OxF0050068 OxF005006C 0 0050070 0 0050074 OxF0050080 OxF0050084 OxF0050088 OxF005008C OxF0050090 OxF0050094 OxF00500A0 OxF00500A4 OxF00500A8 OxF00500AC OxF00500B0 OxF00500B4 ELECTRONICS priority configuration register GDMA programmable priority register for fixed GDMA programmable priority register for round robin GDMA channel 0 control register GDMA channel 0 source address register GDMA channel 0 destination address register GDMA channel 0 transfer count register GDMA channel 0 run enable register GDMA channel 0 interrupt pending register GDMA channel 1 control register GDMA channel 1 source address register GDMA channel 1 destination address register GDMA channel 1 transfer count register GDMA channel 1 run enable register GDMA channel 1 interrupt pe
123. General I O Port phbst8 TIMERS Out General I O Port phbst8 TIMER4 Out General I O Port phbst8 TIMER5 Out General I O Port phbcd8 serial clock phbcd8 C serial data O O O O O O O O O O O NOTE Total Number of Signal Pins 217 1 30 8 ELECTRONICS S3C2500B PRODUCT OVERVIEW 1 7 PAD TYPE Table 1 2 S3C2500B Pad Type and Feature ex Drive Control 3M Phicu LVCMOS Level 3 3V Pull up resistor Phisd LVCMOS Schmitt Trigger 3 3V Pull down resister Poar50_abb Analog output with seperate bulk bias Phbcut12 12 LVCMOS Level 3 3V Tri State Buffer Pull up resistor phbsud4 45 LVCMOS Schmit trigger level 3 3 Tri State Buffer Pull up resister phbst8 8mA LVCMOS Schmit trigger level 3 3V Tri State Buffer phbst16 16mA LVCMOS Schmit trigger leve 3 3V Tri State Buffer Phbst24 24 LVCMOS Schmit trigger level 3 3V Tri State Buffer Phbsut20 20 LVCMOS Schmit trigger level 3 3V Tri State Buffer Pull up resistor phbcd8 8 LVCMOS Level 3 3V Open drain buffer 6mA 058 Butfer NOTE For the detail information about the pad type Input Output Cells of the STD130 MDL 130 0 18um 3 3V Standard Cell Library Data Book which is produced by Samsung Electronics Co Ltd ASIC Team ELECTRONICS 1 31 PRODUCT OVERVIEW S3C2500B 1 8 SPECIAL REGISTERS Ta
124. General Registers and Program Counter Supervisor Undefined THUMB State Program Status Registers CPSR CPSR CPSR CPSR CPSR CPSR SPSR fiq svc m SPSH abt SPSR SPSH und banked register Figure 2 4 Register Organization in THUMB State 2 6 ELECTRONICS S3C2500B PROGRAMMER S MODEL 2 7 3 THE RELATIONSHIP BETWEEN ARM AND THUMB STATE REGISTERS The THUNB state registers relate to the ARM state registers in the following way THUMB state R0 R7 and ARM state RO R7 are identical THUMB state CPSR and SPSRs ARM state CPSR and SPSRs are identical THUMB state SP maps onto ARM state R13 THUMB state LR maps onto ARM state R14 The THUMB state program counter maps onto the ARM state program counter R15 This relationship is shown in Figure 2 5 THUMB State ARM State Lo registers Figure 2 5 Mapping of THUMB State Registers onto ARM State Registers ELECTRONICS 2 7 PROGRAMMER S MODEL S3C2500B 2 7 4 ACCESSING HI REGISTERS IN THUMB STATE In THUMB state registers R8 R15 the Hi registers are not part of the standard register set However the assembly language programmer has limited access to them and can use them for fast temporary storage A value may be transferred from a register in the range R0 R7 a Lo register to a Hi register and from a Hi register to a Lo register using special variants of the MOV instruction Hi register values
125. If B is present then byte transfer otherwise word transfer If T is present the W bit will be set in a post indexed instruction forcing non privileged mode for the transfer cycle T is not allowed when a pre indexed addressing mode is specified or implied An expression evaluating to a valid register number Expressions evaluating to a register number If Rn is R15 then the assembler will subtract 8 from the offset value to allow for ARM9TDMI pipelining In this case base write back should not be specified An expression which generates an address The assembler will attempt to generate an instruction using the PC as a base and a corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated A pre indexed addressing specification Rn offset of zero Rn x expression offset of expression bytes Rn Rm lt shift gt offset of contents of index register shifted by lt shift gt A post indexed addressing specification Rn lt expression gt Rnj Rm lt shift gt offset of lt expression gt bytes offset of contents of index register shifted as by lt shift gt General shift operation see data processing instructions but you cannot specify the shift amount by a register Writes back the base register set the W bit if is present ELECTRONICS S3C
126. Not This bit is valid only when endpoint 1 is set to IN EMPty INEMP Indicate there is at least one packet of data in FIFO if USBEP1CSR 25 24 is 10 1 packet IN FIFO 11 2 packets of lt 1 2 FIFO or 1 packet of gt FIFO size ELECTRONICS 10 27 USB CONTROLLER S3C2500B Table 10 18 USBEP1CSR Register Description Continued 26 In mode UNDER This bit is valid only when endpoint 1 is set to IN run IUNDER ISO The USB sets this bit when in ISO mode an IN token is received and the IINRDY bit is not set The USB sends a zero length data packet for such conditions and the next packet that is loaded into the FIFO is flushed 27 In mode Fifo This bit is valid only when endpoint 1 is set to IN FLUSH IFFLUSH The MCU sets this bit if it intends to flush the IN FIFO This bit is cleared by the USB when the FIFO is flushed The MCU is interrupted when this happens If a token is in progress the USB waits until the transmission is complete before the FIFO is flushed If two packets are loaded into the FIFO only the top most packet one that was intended to be sent to the host is flushed and the corresponding IINRDY bit for that packet is cleared 28 In mode SenD This bit is valid only when endpoint 1 is set to IN STALL ISDSTALL The MCU writes a 1 to this register to issue a STALL handshake to the USB The MCU clears this bit to end the STALL condition 29 In mode SenT This bit is valid only
127. Operation with 5 8 5 7 External 8 bit Store Operation with 5 9 5 8 External 8 bit Load Operation with 0 5 9 5 9 External 32 bit Memory Store Operation with Little Endian 5 10 5 10 External 32 bit Memory Load Operation with 5 10 5 11 External 16 bit Store Operation with 5 11 5 12 External 16 bit Load Operation with Little Endian 5 11 5 13 External 8 bit Store Operation with 5 12 5 14 External 8 bit Load Operation with Little Endian 5 12 5 15 Ext I O Bank Controller Special Registers 4 0 5 21 5 16 Bank n Control BnCON Register 22 00 5 23 5 17 Muxed Bus Control 5 25 5 18 WAIT Control RR RR 5 27 5 19 Supported SDRAM Configuration of 32 bit External 5 40 5 20 Supported SDRAM Configuration of 16 bit External 5 41 5 21 SDRAM Address Mapping of 32 bit External Bus
128. Pin Name Direction DA T tmo xw promo 1 w sere o eus erea 1 GD wr wo mcs o moje 9 o 9 wo ms S o i 1 m wmc o w e m ci w sexw 1 1 m moruoo xw o vos EZE _ me mco o Juj 1 o moms A o vuo wws m xax 10 m u us wws ms msuo 1 1 1 ur mo S 1 n o ute feus 1 mms o jujur 1 10 ELECTRONICS S3C2500B PRODUCT OVERVIEW 1 5 PIN ASSIGNMENT Continued Fns PmName Direction Pin Name Direction wma _ 00 w ws 1 moa w men i ws 1 w joo 9 wu we w xk we w wo curma ELECTRONICS 1 11 PRODUCT OVERVIEW S3C2500B 1 5 PIN ASSIGNMENT Continued Direction Pin Name Direction vum o
129. RUN ENABLE REGISTER Table 11 5 DES 3DES Run Enable Register Description 0 Run Enable If you set this bit to 1 DES 3DES engine begin to run This bit is the same register as the Run Enable bit of the DES 3DES Control Register You can read this bit by addressing 0 00 too 11 3 5 DES 3DES KEY1 LEFT RIGHT SIDE REGISTER Table 11 6 DES 3DES Key1 Left Side Register Description EX 32 1 Left Half The left half of the Key1 should be stored to this register The 8 bit of each byte is parity bit and it isn t used for encryption decryption If users need to byte swapped key value they can control it by using DESCON 12 If DESCON 12 is set byte swapped key is written to DESKEY1L Otherwise original key is written to DESKEY1L Table 11 7 DES 3DES Key 1 Right Side Register Description 33 64 Key 1 Right Half The right half of the Key1 should be stored to this register The 8 bit of each byte is parity bit and it isn t used for encryption decryption If users need to byte swapped key value they can control it by using DESCON 12 If DESCON 12 is set byte swapped key is written to DESKEY1R Otherwise original key is written to DESKEY1R 11 3 6 DES 3DES KEY 2 LEFT RIGHT SIDE REGISTER Table 11 8 DES 3DES Key 2 Left Side Register Description 1 32 Key 2 Left Half The left half of the Key2 should be stored to this register The 8 bit of each byte is parity bit and it isn t used for encryption decryption If
130. Registers u atate aaa aa a Cuotas 17 6 17 6 3 Timer Gount Beglsters i t uu S uwa aus a a aa 17 7 17 6 4 Timer Interrupt Clear Registers 17 8 17 6 5 Watchdog Timer 17 9 Chapter 18Electrical Data 19 1 OVENI Wanane semet E EE 18 1 18 2 Absolute Maximum 18 1 18 3 Recommended Operating 18 1 18 4 DC Electrical 18 2 18 5 Power Consumption 18 4 18 6 Electrical 18 5 Chapter 19Mechanical Data 19 1 OVOIVIOW ne aed t d e dettes 19 1 S3C2500B RISC MICROCONTROLLER List of Figures Figure Title Page Number Number 1 1 S3C2500B Block 1 5 1 2 S3C2500B Pin Assignment Diagram 4 000 1 6 2 1 Big Endian Addresses of Bytes within 2 2 2 2 Little Endian Addresses of Bytes 2 2 2 3 Register Organization in ARM 2 5 2 4 Register Organization in THUMB 2 6 2 5 Mapping of THUM
131. Registers DRER5 OxF00500B0 GDMA channel 5 run enable register OxXXXXXXXO 31 1 0 0 Figure 12 6 Run Enable Register 12 14 ELECTRONICS S3C2500B GDMA CONTROLLER 12 3 6 GDMA INTERRUPT PENDING REGISTER The GDMA interrupt pending register DIPR indicates the pending state of GDMA interrupt by the pending bit 0 of the DIPR register The is active high The DIPR 0 can be asserted after the operation completes successfully when the Interrupt Enable field of DCON 12 is 1 Once the GDMA interrupt service routine is called the DIPR 0 should be de asserted by writing 1 DIPR 0 in the beginning of the interrupt service routine Table 12 8 DIPRO 1 2 3 Registers 31 1 0 0 Interrupt Pending Figure 12 7 GDMA Interrupt Pending Register ELECTRONICS 12 15 GDMA CONTROLLER S3C2500B 12 4 GDMA MODE OPERATION 12 4 1 SOFTWARE MODE It is the mode that operates without specific request signal with just setting the enable bit of control register by software When we want to enable the operation the data transmission is started by setting 3 1 of mode selection bit of DCON register to 000 and 0 bit of the same register to 1 This mode can transmit data between the memories by sending the data which is designated by the source address register to the destination address register The data transmission size
132. SDRAM memory devices 10 128 Mbit SDRAM memory devices 11 2 256 Mbit SDRAM memory devices 7 6 SDRAM device Density of bank 0 DO 00 16 Mbit SDRAM memory devices 01 64 Mbit SDRAM memory devices 10 2 128 Mbit SDRAM memory devices 11 2 256 Mbit SDRAM memory devices 9 8 Row Pre charge time RP 00 1 cycle 01 2 cycles 10 3 cycles 1124 cycles 11 10 RAS to CAS delay RCD 00 1 cycle 01 2 cycles 10 3 cycles 1124 cycles 15 12 Row Cycle RC 0000 1 cycle 0001 2 cycles 0010 3 cycles 0011 4 cycles 0100 5 cycles 0101 6 cycles 0110 7 cycles 0111 8 cycles 1000 9 cycles 1001 10 cycles 1010 11 cycle 1011 12 cycles 1100 13cycles 1101 14 cycles 1110 15 cycles 1111 16 cycles 19 16 Row Active time RAS 0000 1 cycle 0001 2 cycles 0010 3 cycles 0011 4 cycles 0100 5 cycles 0101 6 cycles 0110 7 cycles 0111 8 cycles 1000 9 cycles 1001 10 cycles 1010 11 cycle 1011 12 cycles 1100 13cycles 1101 14 cycles 1110 15 cycles 1111 16 cycles 31 20 Reserved Figure 5 23 SDRAM Configuration Register ELECTRONICS 5 49 MEMORY CONTROLLER S3C2500B 5 7 9 2 Command Register The configuration register 1 is 32 bit read write some bits are read only register The SDRAM initialization command write buffer operation can be controlled by this register Table 5 26 SDRAM Command Register CMDREG 0 0020004 SDRAM command register 0x00000000 INIT 1 0 Control
133. This bit is only valid only when endpoint 2 is set to SET IATSET IN If set whenever the MCU writes MAXP data IINRDY will be automatically be set without any intervention from MCU If the MCU writes less than MAXP data then IINRDY bit has to be set by the MCU Default 0 14 13 15 CSR2 SETtable 0 USBEP2CSR 12 8 isn t overwritten when MCU CSR2SET writes a 32bit value to USBEP2CSR register 1 USBEP2CSR 12 8 is overwritten 16 Out mode Out This bit is valid only when endpoint 2 is set to OUT packet ReaDY The USB sets this bit once it has loaded a packet of OORDY data into the FIFO Once the MCU reads the FIFO for the entire packet this bit should be cleared by MCU 17 Out mode Fifo This bit is valid only when endpoint 2 is set to OUT FULL OFFULL Indicates no more packets can be accepted if USBEP2CSR 17 16 is 00 No packet in FIFO 01 1 packet in FIFO 11 2 packet of MAXP lt 1 2 FIFO size or 1 packet of MAXP gt FIFO size 18 Out mode fifo This bit is valid only when endpoint 2 is set to OUT OVER run ISO OOVER This bit is set if the core is not able to load an OUT ISO packet into the FIFO 19 Out mode Data This bit is valid only when endpoint 2 is set to OUT ERRor ODERR ISO This bit should be sampled with OORDY When set it indicates the data packet due to be unloaded by the MCU has an error either bit stuffing or CRC If two packets are loaded into the FIFO and the second pack
134. V 50 C 737 1 mW 3 3 V Idle 25 C 664 2 mW The output can differ under other circumstances 18 4 ELECTRONICS S3C2500B ELECTRICAL DATA 18 6 AC ELECTRICAL CHARACTERISTICS Table 18 4 Operating Frequency System bus frequency MHz USB Frequency MHz Table 18 5 Clock AC timing specification Characteristic Mn Wax Internal PLL lock time Frequency of operation XCLK Lec 133 MHz 75 nns O Frequency of operation HCLKO 13 2 IMdKOgdeTme ELECTRONICS 18 5 ELECTRICAL DATA S3C2500B Table 18 6 AC Electrical Characteristics for S3C2500B Signal Name Min Mex Unit inRCSd inOEd ROM SRAM output enable holdtime 069 inSDWEd tADDRd tADDRh IDATAd DATA tALEh tMADDRd tMADDRh tnWAITd tnWAITh cc CH CL CASh RASC Row Address Strobe Delay Time 20 48 ps LRASh Row Address Strobe Hold Time 20 47 ps SDRAM Chip Select Delay Time 20 48 SDRAM Chip Select Hod Time 20 47 ps Wed SDRAM Write Enable DelayTime 17 40 WEh SDRAM Write Enable Hold Time 17 39 WDd SDRAM Write DataDelayTime 723 53 WDh SDRAM Write Data Hold Time 116 35 ps SDRAM Read Data Delay Time 60 70 ps SDRAM Read Data Hold Time 7760 70 ps
135. a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24 This means that half words accessed at these offsets will be correctly loaded into bits 16 through 31 of the register A shift operation is then required to move and optionally sign extend the data into the bottom 16 bits An address offset of 1 or 3 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 15 through 8 A word store STR should generate a word aligned address The word presented to the data bus is not affected if the address is not word aligned That is bit 31 of the register being stored always appears on data bus output 31 3 30 ELECTRONICS S3C2500B INSTRUCTION SET 3 9 4 USE OF R15 Write back must not be specified if R15 is specified as the base register Rn When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction R15 must not be specified as the register offset Rm When R15 is the source register of a register store STR instruction the stored value will be address of the instruction plus 12 3 9 5 RESTRICTION ON THE USE OF BASE REGISTER When configured for late aborts the following example code is difficult to unwind as the base register Rn gets updated before the abort handler starts Sometimes it may be impossible to calculate the initial value
136. and MLA 15 1 cycles to execute where S and are defined as sequential S cycle and internal I cycle respectively m The number of 8 bit multiplier array cycles is required to complete the multiply which is controlled by the value of the multiplier operand specified by Rs Its possible values are as follows 1 If bits 32 8 of the multiplier operand are all zero or all one 2 If bits 32 16 of the multiplier operand are all zero or all one 3 If bits 32 24 of the multiplier operand are all zero or all one 4 In all other cases 3 7 8 ASSEMBLER SYNTAX MUL cond S Rd Rm Rs MLA cond S Rd Rm Rs Rn cond Two character condition mnemonic See Table 3 2 S Set condition codes if S present Rd Rm Rs and Rn Expressions evaluating to a register number other than R15 Examples MUL R1 R2 R3 1 MLAEQS R1 R2 R3 R4 Conditionally R1 R2 R3 R4 setting condition codes 3 24 ELECTRONICS S3C2500B INSTRUCTION SET 3 8 MULTIPLY LONG AND MULTIPLY ACCUMULATE LONG MULL MLAL The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 13 The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results Signed and unsigned multiplication each with optional accumulate give rise to four variations 28 27 23 22 21 20 19 16 15 12 11 Lu ooo os ules me D m
137. bit SRAM Basic Connection 5 16 ELECTRONICS S3C2500B MEMORY CONTROLLER Figure 5 6 illustrates a connection between 16 bit ROM Flash and S3C2500B ADDED ABE in _ 1641 we n S3C2500B Figure 5 6 16 bit ROM and Flash Basic Connection ELECTRONICS 5 17 MEMORY CONTROLLER S3C2500B Figure 5 7 illustrates a connection between 16 bit ROM and S3C2500B ADDR 23 0 DATAI31 DATA 15 HR 81 0 TI pea Ed nOE 16 bit ROM ws TT E nSDWE nWE16 nWE S3C2500B ADDR DATA nOE 16 bit ROM nCS nWE DATA 31 16 Figure 5 7 16 bit ROM Basic Connection 2 5 18 ELECTRONICS S3C2500B MEMORY CONTROLLER Figure 5 8 illustrates a connection between 16 bit SRAM and S3C2500B ADDR 23 0 ADDR DATA 0 DATA 15 0 pon nOE d S us nRCS a 16 bit ROM J o y nWBE 1 Upper byt nWBE O Lower byte S3C2500B ADDR DATA nOE nCS nWBE 2 Upper byte Lower byte DATA 31 16 16 bit ROM Figure 5 8 16 bit SRAM Basic Connection 2 ELECTRONICS 5 19 MEMORY CONTROLLER S3C2500B Figure 5 9 illustrates a connection between S3C2500B and muxed bus ROM amp SRAM ADDR 23 ALE ALE DATA 7 0 DATA 7 0 nOE nOE nRCS S nWBE S3C2500B nREADY nREADY Figure 5 9 ROM amp SRAM with Muxed Address amp Data Bus Connection NOTE If the external I O use nReady signal insteady of nWait you must select nReady in
138. bit to 1 To inhibit counting clear the bit to 0 Tx 4 word mode When this bit is 0 and TxFA bit in status register is 1 it is indicated that Tx4WD Tx FIFO is empty for 1 word It means that 1 word data can be loaded to Tx FIFO Similarly when this bit is 1 the same status register bit indicate that 4 words of data can be loaded to Tx FIFO without reading the status bit for a second time Specifically the status register bit affected by the 1 word or 4 word transfer setting are the transmit data available TxFA bit Rx 4 word mode When this bit is 0 and the RxFA bit in the status register is 1 it is Rx4WD indicated that Rx FIFO has 1 word data It means that 1 word data can be moved to memory Similarly when this bit is 1 the same status register bit indicates that 4 words of data can be moved in the memory without reading the status bit for a second time Specifically the status register bit affected by the 1 word or 4 word transfer setting are the receive data available RxFA bit and the residue bytes status bits RxRB 3 0 up ELECTRONICS 8 31 HDLC CONTROLLER S3C2500B Table 8 10 HCON Register Description Continued Bit Bit Name Description Number 13 12 Rx widget alignment These bits determine how many bytes are invalid in the first memory RxWA word of the frame to be received The invalid bytes are inserted when the word is assembled in the HRXFIFO 00 No Invalid byte 01
139. bits for SDRAM device initialization R W 00 Normal operation 01 Automatically issue a PALL to the SDRAM 10 Automatically issue a MRS to the SDRAM 11 reserved WBUF 2 Write buffer enable R W 0 Disable merging write buffer 1 Enable merging write buffer NOTE Disabling the write buffer will flush any stored value s to the external SDRAM memory BUSY 3 SDRAM controller status bit 0 SDRAM controller is idle 1 SDRAM controller is busy Ba 1 NOTE WBUF field of configuration register is a read only bit if write buffers are not included an AHB interface sub block 5 50 ELECTRONICS S3C2500B ELECTRONICS MEMORY CONTROLLER RESERVED 1 0 Control bits for SDRAM device initialization 00 Normal operation 01 Automatically issue a PALL to the SDRAM 10 Automatically issue a MRS to the SDRAM 11 reserved 2 Write buffer enable 0 Disable merging write buffer 1 Enable merging write buffer 3 SDRAM controller status bit 0 SDRAM controller is idle 1 SDRAM controller is busy 31 4 Reserved Figure 5 24 SDRAM Command Register MEMORY CONTROLLER S3C2500B 5 7 9 3 Refresh Timer Register The Refresh timer register is 32 bit read write some bits are read only register This register sets the SDRAM refresh cycle The refresh timer register is programmed with the number of system bus clock that should be counted between SDRAM refresh cycles Table 5 27 SDRAM Ref
140. can be byte half word or word It is determined by setting 7 6 bit of DCON register Without special USB mode setting of endpoint read write are possible That is by writing an address of USB endpoint into source address register or destination address register read write is possible Also it is possible to read and write any function registers or buffer FIFO by GDMA controller 12 4 2 EXTERNAL GDMA REQUEST MODE of S3C2500B has four external request Req sources xGDMA signal xGDMA signal can be shared with port signals So it is used by setting I O Ports register 1 Refer to Chapter 15 Ports External device sending xGDMA transmits the data by during receiving xGDMA signal Also external request mode is used by setting mode selection bit 3 1 of DCON register to 001 It is similar to the basic operation mode of software but it is different that GDMA transmits the data only after receiving xGDMA signal The first external request xGDMA can be serviced by channel 0 and 4 The second external request xGDMA Redl can be serviced by channel 1 and 5 The third external request xGDMA Reg can be serviced by channel 2 The fourth external request xGDMA 3 can be serviced by channel If the slow external devices need the GDMA service the slo
141. cannot be updated You should check BTXBDONT register to detect how many frames were handled ELECTRONICS 7 9 ETHERNET CONTROLLER 7 10 S3C2500B 18 17 16 15 Buffer Pointer 31 0 31 30 18 17 16 15 0 TxStatus Buffer pointer Ownership bit O TxStatus 30 Reserved 29 Paused 28 Halted 27 SQEErr 26 Defer 25 Coll 24 Comp 23 ParErr 22 LateColl 21 NoCarr 20 DeferErr 19 Underflow 18 ExColl TxWidget TxLength TxWidget TxLength Address of the data be transmitted 0 CPU 1 BDMA Writing in this field don t have any mean Transmission of frame was paused due to the reception of a Pause control frame The transmission of the next frame is halted when MACCON 1 MHaltlmm is set or when 0 MTxEn is clear Signal Quality Error The transmission of frame was deferred The collision is occured in half duplex The current frame is retried to send The transmition is finished Parity Error The Collision occured after 64 byte times No Carrier sense is detected when MAC Tx transmits a frame MAC doesn t run the transmission process until 6071 nibble or 24284 bit times The current frame is aborted MTxFIFO underflow The excessive collision is occured 16 times consecutively The current frame is aborted The transmission widget alignment of the current frame The size of the transmission data by using the BDMA The U
142. capacitor should be connected between the pin and ground PHY CLKO 1 phob8 PHY clock Out PHY PLL clock output can be monitored by PHY CLKO This clock is used as the external phy source clock However some switches may cause a link failure when S3C2500 s PHY source clock PHY CLKO is used CPU FILTER 1 50 abb PLL filter pin for System PLL If the PLL is used 320pF capacitor should be connected between the pin and ground ELECTRONICS 1 13 PRODUCT OVERVIEW S3C2500B Table 1 1 S3C2500B Signal Descriptions Continue Group PinName Pin Type PadType Description CLKMOD 1 0 2 Phic The CLKMOD pin determines internal clock scheme of S3C2500B When CLKMOD is 00 the nfast clock mode is defined In this mode the same clock is used as CPU clock and system clock When CLKMOD is 11 the async clock mode is defined In this mode the CPU clock and system clock can operate independently as long as the CPU clock is faster than system clock CPU FREQ 2 0 3 phic CPU Clock Frequency Selection BUS FREQ 2 0 3 phic System Bus Clock Frequency Selection nRESET 1 phis Not Reset NRESET is the global reset input for the 53 2500 and nRESET must be held to low for at least 64 clock cycles for digital filtering TMODE 1 phicd Test Mode The TMODE pin setting is interpreted as follows 0 normal operating mode 1 chip test mode BIG 1 phicd BIG endian mode select pin When this pi
143. case of occasional delivery failure due to error on the bus An interrupt pipe is a stream pipe and is therefore always uni directional An endpoint description identifies whether a given interrupt pipe s communication flow is into or out of the host 10 6 ELECTRONICS S3C2500B USB CONTROLLER 10 4 USB BLOCK DESCRIPTIONS 10 4 1 USB BLOCK OVERVIEW USB block is compatible with USB spec 1 1 There re 5 EPs Endpoint with EPO for control transfer This block uses two input clocks 133MHz and 48MHz 133MHz clock is used to special registers access and USB to system bus interfacing 48MHz clock is used for SIE 12MHz clock is generated from 48MHz and used for transmitting data throughout physical cable FIQ IRQ interrupt routine should be used for USB service Max packet size is programmable with special registers E Hesse General Function Interface Special Registers APB BUS or LLI 2 LLI 2 lt or Figure 10 4 USB Core Block Diagram 10 4 2 SIE SERIAL INTERFACE ENGINE BLOCK The SIE is the front end of this hardware and handles most of the protocol described in chapter 8 of the USB specification The SIE typically comprehends signaling up to the transaction level The functions that it handles could include e Packet recognition transaction sequencing e SOP EOP RESET RESUME signal detection generation e Clock Data separation e NRZI Data encoding decoding and bit stuffing
144. clocks Reading is driven by either a 25MHz or a 2 5MHz TX Writing is driven by system clock which is asynchronous to CLK After a reset the MTxFIFO is empty To enable the transmission the system must set the transmit enable bit in the MACTXCON register In addition eight bytes of data must be present in the MTxFIFO The BDMA engine can start stuffing data into the MTxFIFO and then enable the transmit bit or it can enable the transmit bit first and then start stuffing data into the MTxFIFO The transmitting operation can only start if both of these conditions are met 7 5 1 4 Receiving a Frame The receiver block when enabled constantly monitors a data stream coming either from the MII or if in loop back mode from the transmitter block The MII supplies from zero to seven bytes of preamble followed by the start frame delimiter SFD The receiver block checks that the first nibbles received are preamble and then looks for the SFD 10101011 in the first 8 byte If it does not detect the SFD by then it treats the frame as a fragment and discards it The first nibble of destination address follows the SFD LSB first When it has received a byte the receiver block generates parity stores the byte with its parity in the MRxFIFO It combines subsequent nibbles into bytes and stores them in the FIFO 7 42 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 5 1 4 1 Receive Frame Timing With Without Error If during frame rece
145. contain interrupt pending bits which are re ordered by the INTPRIORn register settings IPRIORLO 14 is mapped to the interrupt source of whichever bit index is written into the priority 14 field of the INTPRIORn registers This register is useful for testing To validate the interrupt pending by priority value you can obtain the highest priority pending interrupt from the interrupt offset register INTOFFSET Table 16 8 IPRIORHI IPRIORLO Register IPRIORHI OxF0140010 R High bits 38 32 bit Interrupt by priority register 0x00000000 IPRIORLO OxF0140014 R Low bits 31 0 bit Interrupt by priority register 0x00000000 16 4 6 INTERRUPT TEST REGISTER The interrupt test registers INTTSTHI and INTTSTLO are used to monitor a interrupt pending status The interrupt pending test registers INTTSTHI and INTTSTLO are also useful for testing Table 16 9 INTTSTHI INTTSTLO Register INTTSTHI OxF0140048 High bits 38 7 bit Interrupt test register 0x00000000 INTTSTLO OxF014004C R Low bits 6 0 bit Interrupt test register 0 00000000 16 12 ELECTRONICS S3C2500B 32 BIT TIMERS 32 BIT TIMERS 17 1 OVERVIEW The timer has six 32 bit timers and one watchdog timer Six 32 bit timers have Timer Mode register TMOD which is used to control the operation of the six 32 bit timers Timer Data registers TDATAn which are data registers for counting Timer Counts registers TCNTn which are count value registers and Timer Inte
146. content 32 word Undefined OxFOOBOOFC CAMB 0 0000080 R W CAM content 32 word Undefined OxFOODOOFC Table 7 55 Content Address Memory CAM Register Description 31 0 CAM content The CPU uses the CAM content register as data for destination address To activate the CAM function you must set the appropriate enable bits in CAM enable register 7 36 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 5 ETHERNET OPERATIONS 7 5 1 MAC FRAME FORMAT Table 7 2 lists the eight fields in a standard IEEE 802 3 Ethernet frame Table 7 53 MAC Frame Format Description Preamble 7 byte The bits in each preamble byte are 10101010 transmitted from left to right Start frame delimiter 1 byte The SFD bits are 10101011 transmitted from left to right SFD Destination address 6 byte The destination address can be an individual address or a multicast or broadcast address Source address 6 byte The MAC does not interpret the source address bytes However to qualify as a valid station address the first bit transmitted the LSB of the first byte must be a 0 Length or type 2 byte The MAC treats length fields greater than 1500 byte as type fields Byte values less than or equal to 1500 indicate the number of logical link control LLC data bytes in the data field The MAC transmits the high order byte first Logical link control 46 to 1500 byte Data bytes used for logical link control LLC data PAD 0 to 46 byte If the LLC
147. data OCLTOG toggle sequence bit is reset to DATAO 24 In mode IN packet This bit is valid only when endpoint 3 is set to IN ReaDY IINRDY The MCU sets this bit after writing a packet of data into the FIFO The USB clears this bit once the packet has been successfully sent to the host An interrupt is generated when the USB clears this bit so the MCU can load the next packet While this bit is set the MCU will not be able to write to the FIFO If the SEND STALL bit is set by the MCU this bit can not be set 25 In mode fifo Not This bit is valid only when endpoint 3 is set to IN EMPty INEMP Indicate there is at least one packet of data in FIFO if USBEP3CSR 25 24 is 10 1 packet IN FIFO 11 2 packets of MAXP lt 1 2 FIFO or 1 packet of MAXP gt FIFO size 26 In mode UNDER This bit is valid only when endpoint 3 is set to IN run IUNDER ISO The USB sets this bit when in ISO mode an IN token is received and the IINRDY bit is not set The USB sends a zero length data packet for such conditions and the next packet that is loaded into the FIFO is flushed ELECTRONICS 10 37 USB CONTROLLER S3C2500B Table 10 22 USBEP3CSR Register Description Continued 27 In mode Fifo This bit is valid only when endpoint 3 is set to IN FLUSH IFFLUSH The MCU sets this bit if it intends to flush the IN FIFO This bit is cleared by the USB when the FIFO is flushed The MCU is interrupted when this happens If a token
148. data will be decrypted 0 DES algorithm is selected 1 Triple DES algorithm is selected Encryption Mode 0 DES 3DES will be running ECB Electronic Code Book mode 7 ECB or CBC 1 DES SDES will be running CBC Cipher Block Chaining mode 2word req 0 DES 3DES engine generates Available DESINFIFO bit in the status register to 1 when DESINFIFO is vacant more than 4 words and Valid DESOUTFIFO bit in the status register to 1 when DESOUTFIFO has more than 4 words valid data 1 DES SDES engine generates Available DESINFIFO bit in the status register to 1 when DESINFIFO is vacant more than 2 words and Valid DESOUTFIFO bit in the status register to 1 when DESOUTFIFO has more than 2 words valid data 8 FIFO Test 0 Normal operation 1 DESINFIFO and DESOUTFIFO test If this bit sets to 1 user can scan DESINFIFO and DESOUTFIFO 9 FIFO Reset 0 Normal operation 1 The data in the DESINFIFO and DESOUTFIFO have been invalid data 10 SwapEn data 0 no byte swapping for DESINFIFO and DESOUTFIFO 1 cpu write byte swapped data to DESINFIFO and read byte swapped data from the DESOUTFIFO 11 SwapEn iv 0 no byte swapping for DESIVL R 1 cpu writes byte swapped value to the DESIVL R and reads byte swapped data from the DESIVL R 12 SwapEn keys 0 no byte swapping for DESKEY L R 1 cpu writes byte swapped data to the DESKEY L R and reads byte swapped data from DESKEY L R 11 4 ELECTRONICS
149. entity STA The STA controls and reads the current operating status of the PHY layer The speed of transmit and receive operations is determined by the management data clock MDC The frame structure of the STA that writes command to control registers or which reads the status register of a PHY device is shown Table 7 54 The PHY address is defined as the identification ID value of the various PHY devices that may be connected to a single MAC Register addresses can contain the ID value for up to 32 types of PHY registers Turn around bits are used to regulate the turn around time of the transmit receive direction between the STA and a PHY device So that the STA can read the set value of a PHY device register it must transmit the frame data up to a specific register address to the PHY device During the write time which is an undirected transmission the STA transmits a stream of turn around bits As a result by transmitting a write or read message to a PHY device through the MDIO the STA can issue a request to set the operation or to read the operation status As its response this message the PHY device resets itself sets loop back mode selects active non active auto negotiation process separates the PHY and MII electrically and determines whether or not to activate the collision detection process When it receives a read command the PHY reports the type of PHY device such as 100 base T4 FDX 100 base X HDX 100Base X 10M b s FDX
150. execute the following irrespective of the state ARM or Thumb SUBS PC R14_abt 4 fora prefetch abort SUBS PC R14_abt 8 for a data abort This restores both the PC and the CPSR and retries the aborted instruction ELECTRONICS 2 13 PROGRAMMER S MODEL S3C2500B 2 9 7 SOFTWARE INTERRUPT The software interrupt instruction SWI is used for entering Supervisor mode usually to request a particular supervisor function A SWI handler should return by executing the following irrespective of the state ARM or Thumb MOV PC R14 svc This restores the PC and CPSR and returns to the instruction following the SWI NOTE nFIQ nIRQ ISYNC LOCK BIGEND and ABORT pins exist only in the ARM9TDMI CPU core 2 9 8 UNDEFINED INSTRUCTION When ARM9TDMI comes across an instruction which it cannot handle it takes the undefined instruction trap This mechanism may be used to extend either the THUMB or ARM instruction set by software emulation After emulating the failed instruction the trap handler should execute the following irrespective of the state ARM or Thumb MOVS PC R14 und This restores the CPSR and returns to the instruction following the undefined instruction 2 10 EXCEPTION VECTORS The following table shows the exception vector addresses Table 2 3 Exception Vectors Exeon Abort prefetch Abort data 0000018 2 14 ELECTRONICS S3C2500B PROGRAMMER S
151. flushed 10 42 ELECTRONICS S3C2500B USB CONTROLLER Table 10 24 USBEPACSR Register Description Continued 27 In mode Fifo This bit is valid only when endpoint 4 is set to IN FLUSH IFFLUSH The MCU sets this bit if it intends to flush the IN FIFO This bit is cleared by the USB when the FIFO is flushed The MCU is interrupted when this happens If a token is in progress the USB waits until the transmission is complete before the FIFO is flushed If two packets are loaded into the FIFO only the top most packet one that was intended to be sent to the host is flushed and the corresponding IINRDY bit for that packet is cleared 28 In mode This bit is valid only when endpoint 4 is set to IN SenD STALL The MCU writes a 1 to this register to issue a ISDSTALL STALL handshake to the USB The MCU clears this bit to end the STALL condition 29 In mode This bit is valid only when endpoint 4 is set to IN SenT STALL The USB sets this bit when a STALL handshake is ISTSTALL issued to an IN token due to the MCU setting SEND STALL bit When the USB issues a STALL handshake IINRDY is cleared 30 In mode CLear This bit is valid only when endpoint 4 is set to IN data TOGgle When the MCU writes a 1 to this bit the data toggle ICLTOG bit is cleared This is a write only register Reserved PP ELECTRONICS 10 43 USB CONTROLLER S3C2500B 31 30 29 28 27 26 25 24 23 22 e 16 15 14 13 12 11 10 9 8
152. frame If the frame is marked as a MAC control frame and pass through is enabled it is passed to the software drivers User can set the control bit in the MAC control register to generate a Full Duplex pause operation or other MAC control functions even if the transmitter itself is paused The command and status registers initiate the sending of a MAC control frame enable and disable MAC control functions and read the values of the flow control counters Destination 6 Octet Source 6 Octets 2 Octets Length Type Octers within Frame Transmitted Top to Bottom 2 Octets MAC Control Opcode MAC Control Parameters minFrameSize 160 8 Octets Bits within Frame Transmitted Left to Right Figure 7 12 MAC Control Frame Format 7 46 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 5 8 1 Transmit Pause Operation To enable a full duplex Pause operation the special broadcast address for MAC control frames must be programmed into the CAM and the corresponding CAM enable bit set The special broadcast address can be a CAM location To optimize the utilization CAM entries you can specify a preference for specific CAM locations This feature is described below The MAC receive circuit recognizes a full duplex Pause operation when the following conditions are met The length type field has the special value for MAC control frames 0x8808 CAM detects the correcting destination address
153. frame based on their destination address Flow control block Recognizes MAC control frame and supports the pause operation for full duplex links The flow control block also supports generation of pause frame and provides timers and counters for pause control MAC control command Controls programmable options including the enabling or disabling of signals that and status registers notify the system when conditions occur The status registers hold information for error handling software and the error counters accumulate statistical information for network management software Loop back circuit Provides for MAC layer testing in isolation from the MII and physical layer 7 3 1 MEDIA INDEPENDENT INTERFACE MII Both transmitter and receiver blocks operate using the MII which was developed by the IEEE802 3 task force on 100 Mbps Ethernet This interface has the following characteristics e Media independence e Multi vendor points of interoperability e Supports connection of MAC layer and physical layer entity PHY devices e Capable of supporting both 100M bps 10M bps and 1M bps data rates e Data and delimiters are synchronous to clock references e Provides independent 4 bit wide transmit and receive data paths e Uses TTL signal levels that are compatible with common digital CMOS ASIC processes e Supports connection of PHY layer and station management STA devices e Provides a simple management interface e Capable of driv
154. host a a 17 OUT Fifo FULL OFFULL 1 Stall handshake transmit state Ionia perator 29 IN SenT STALL ISTSTALL 1 FIFO full state 0 No operation 18 OUT OVER run OOVER 1 Stall handshake transmitted 0 Normal operation 1 Data received at FIFO full state ISO ICLTOG 1 Data toggle flag set to 0 31 Reserved 10 in out MODE setting MODE 0 Indexed endpoint set to OUT 1 Indexed endpoint set to IN 11 IN ISO mode IISO 0 Bulk interrupt mode 1 2 ISO mode 12 IN AuTo SET IATSET 0 No operation Figure 10 16 USBEPACSR Register 10 44 ELECTRONICS S3C2500B USB CONTROLLER 10 5 12 USB WRITE COUNT FOR ENDPOINT 0 REGISTER When OORDY is set for OUT endpoints USBWCEPO 22 16 maintains the byte count number of data in FIFO due to be unloaded by the MCU In case of IN mode MCU first writes the byte count number of data to be loaded into FIFO then write data into FIFO Table 10 25 USBWCEPO Register USBWCEPO 0xF00E0030 USB Write Count for Endpoint 0 Register 0x00000000 Table 10 26 USBWCEPO Register Description CPU WRiTe R W the byte count number of data to be loaded into CouNT FIFO CPUWRTONT 57 Reewed 22 16 WRiTe CouNT W the byte count number of data in FIFO due to be WRTONT unloaded by the MCU jReseved ELECTRONICS 10 45 USB CONTROLLER S3C2500B 31 23 22 16 15 7 6 0 6 0 ep0 CPU WRiTe CouNT
155. in HUART control register If hardware flow control bit set to one HUARTO can receive the receiving data only when this pin state is active General I O Port Receive Data See HURXDO description General I O Port HUART1 Transmit Data See HUTXDO description General I O Port PRODUCT OVERVIEW S3C2500B Table 1 1 S3C2500B Signal Descriptions Continue HUART1 HUnDTR1 7 GPIO37 HUnDSR1 GPIO38 HUnRTS1 9 HUnCTS1 GPIO40 HUnDCD1 GPIO41 GPIO Included XINT 5 0 GPIO 13 8 XGDMA Ack 3 0 GPIO 21 18 _ 22 Ss p p TIMER1 GPIO 23 TIMER2 GPIO 24 TIMER3 GPIO 25 TIMER4 GPIO 26 TIMER5 GPIO 27 EI GPIO 7 0 xINT xGDMA Req xGDMA Ack Timer XGDMA Req 3 0 GPIO 17 14 phbst8 Not HUART1 Data Terminal Ready See HUnDTROdescription General I O Port phbst8 Not HUART1 Data Set Ready See HUnDSRO description General I O Port phbst8 Not Request to send See HUnRTSO description General I O Port phbst8 Not Clear to send See HUnCTSO description General I O Port phbst8 Not Data carrier detected See HUnDCDO description General I O Port phbst8 General Ports phbst8 External interrupt requests General Ports phbst8 External DMA requests for GDMA General Ports phbst8 External DMA acknowledge from GDMA General I O Ports phbst8 TIMERO Out General I O Port phbst8 TIMER1 Out General I O Port phbst8 TIMER2 Out
156. input mode bit value 0 is output mode 9 sama Sup Fesrm 30 28 27 HE HUNE 26 0 25 S 0 24 L 8 Lue 28 21 S O 19 L Oo 18 NER 16 15 14 EBENE 8 7 5 Figure 15 1 Port Mode Registers 1 2 IOPMODE1 2 15 3 VO PORTS S3C2500B 15 3 2 PORT FUNCTION CONTROL REGISTER IOPCON1 2 The I O port function select registers 1 2 are used for function select 1 2 are used to configure external interrupt signals signals timer signals UART Tx Rx signals and HDLC Tx Rx signals For example if you set IOPCON 1 14 to 0 then port14 is used for Req port If you set the IOPGDMA 14 to 1 then port14 is used for GPIO NOTE If the port is used for a function s port such as an external interrupt request or an external GDMA Req Ack signal its signal function is determined by IOPGDMA IOPEXTINT register Table 15 3 IOPCON1 2 Register IOPCON1 OxF0030008 port function control register for port 0 to 31 IOPCON2 OxFO003000C port function control register for port 32 to 63 0x00000000 15 4 ELECTRONICS S3C2500B VO PORTS 31 30 29 28 27 26 25 24 23 22 21 2019 18 17 16 15 14 13 12 1110 9 8 7 0 ETT NN
157. input output mask signal for SDRAM 1 16 ELECTRONICS S3C2500B PRODUCT OVERVIEW Table 1 1 S3C2500B Signal Descriptions Continue Group Pin Type PadType Memory XBMREQ 1 phicd External Master bus request Interface An external bus master uses this pin to 80 request the external bus When it activates the XBMREQ the S3C2500B drives the state of external bus pins to high impedance This lets the external bus master take control of the external bus When it has control the external bus master assumes responsibity for SDRAM refresh operation The XBMREQ is deactivated when the external bus master releases the external bus When this occurs the S3C2500B can get the control of the bus and the XBMACK goes low XBMACK 4 9 phob8 External bus Acknowledge TAP 1 Test Clock Control The JTAG test clock shifts state information 5 and test data into and out of the S3C2500B during JTAG test operations TMS 1 phicu JTAG Test Mode Select This pin controls JTAG test operations in the S3C2500B This pin is internally connected pull up TDI 1 phicu JTAG Test Data In The TDI level is used to serially shift test data and instructions into the S3C2500B during JTAG test operations This pin is internally connected pull up TDO 1 phot12 JTAG Test Data Out The TDO level is used to serially shift test data and instructions out of the S3C2500B during JTA
158. instruction the PC will be 8 bytes ahead If a register is used to specify the shift amount the PC will be 12 bytes ahead 3 5 6 TEQ TST CMP AND CMN OPCODES NOTE TEQ TST CMP and CMN do not write the result of their operation but do set flags in the CPSR An assembler should always set the S flag for these instructions even if this is not specified in the mnemonic The TEQP form of the TEQ instruction used in earlier ARM processors must not be used the PSR transfer operations should be used instead The action of TEQP in the ARM9TDMI is to move SPSR mode to the CPSR if the processor is in a privileged mode and to do nothing if in User mode 3 16 ELECTRONICS S3C2500B INSTRUCTION SET 3 5 7 INSTRUCTION CYCLE TIMES Data processing instructions vary in the number of incremental cycles taken as follows Table 3 4 Incremental Cycle Times Data processing with register specified shift 15 11 Data processing with PC written 25 1 Data processing with register specified shift and PC written 25 1 1I NOTE 5 as defined sequential S cycle non sequential N cycle and internal I cycle respectively 3 6 8 ASSEMBLER SYNTAX single operand instructions lt opcode gt cond S Rd lt Op2 gt CMP CMN TEQ TST instructions which do not produce a result lt opcode gt cond Rn lt Op2 gt AND EOR SUB RSB ADD ADC SBC RSC ORR BIC lt opcode gt cond S Rd Rn lt
159. into memory at the address specified by the DMA Rx data buffer pointer If a frame is longer than the value of the RxBuf Size register then the next buffer descriptors are fetched to receive the frame That is to handle a frame one or more buffer descriptors could be used Please note that no configurable offset or page boundary calculation is required The received frame is moved to the buffer memory whose address is pointed to by the buffer data pointer until the end of frame or until the length exceeds the maximum frame length configured If the length exceeds the maximum frame length configured the frame length violated bit is set During transmission the two byte frame length at the Tx buffer descriptor is moved to the DMA internal Tx register After transmission the Tx status is saved in the Tx buffer descriptor After stores the status the BDMA controller fetches the next buffer descriptor and the Owner bit and the control bits of the next word When the DMA Tx buffer descriptor register points to the first buffer descriptor the transmitter starts transmitting the frame data from the buffer memory to Tx FIFO 8 20 ELECTRONICS S3C2500B HDLC CONTROLLER 8 6 BUFFER DESCRIPTOR 8 6 1 TRANSMIT BUFFER DESCRIPTOR 272625 2322 Buffer Pointer Tx Control Bits Buffer Length 31 0 Buffer Data Pointer 15 0 Buffer Length Tx Control Bits 16 Preamble P 0 No Preamble 1 Preamble 17 TxNoCRC Mode N 0
160. is forced to send an End of Message EOM 8 Bus Request for BREQ 0 The TIC bus is released 1 The 2 controller starts to access the TIC bus for channel 9 Monitor Channel Select MSEL 0 Monitor channel 0 is selected 1 Monitor channel 1 is selected IC Channel Select ICSEL 0 is selected 1 is selected 11 Awake Request AWAKE 0 Normal 1 The 2 controller pulls DU to low which requests the transceiver to deliver DCLK 12 Test Loop Back LOOP 0 normal 1 The DD and DU are internally connected together The Data from the transceiver will not be forwarded to the IOM2 controller 13 TSA Enable 0 TSA disabled 1 TSA enable 14 Transceiver Type Select TTSEL 0 Transceiver that transmit DCL rising edge after FSC rising edge 1 Transceiver that transmit DCL rising edge before FSC rising edge 9 12 ELECTRONICS Message MTxEOM S3C2500B IOM2 CONTROLLER 15 14 13 12 11 10 mugcj 0 2 Enable IOM2EN 0 Disable 1 Enable 1 Data Bus Reverse DBREV 0 DU upstream DD downstream 1 DU downstream DD upstream 2 Monitor Enable MEN 0 Disable 1 Enable 3 TIC Bus Enable TICEN 0 Disable 1 Enable 4 D channel Collision Enable DCOLEN 0 Disable 1 Enable 5 Monitor Abort Request MAR 0 Normal 1 Abort request asserted 6 Monitor Address Valid MAV 0 Address received is not valid 1 Address receiv
161. it has loaded a packet of data into the FIFO Once the MCU reads the FIFO for the entire packet this bit should be cleared by MCU This bit is valid only when endpoint 4 is set to OUT Indicates no more packets can be accepted if USBEPACSR 17 16 is 00 No packet in FIFO 01 1 packet in FIFO 11 2 packet of lt 1 2 FIFO size or 1 packet of MAXP FIFO size This bit is valid only when endpoint 4 is set to OUT ISO This bit is set if the core is not able to load an OUT ISO packet into the FIFO This bit is valid only when endpoint 4 is set to OUT ISO This bit should be sampled with OORDY When set it indicates the data packet due to be unloaded by the MCU has an error either bit stuffing or CRC If two packets are loaded into the FIFO and the second packet has an error then this bit gets set only after the first packet is unloaded This is automatically cleared when OORDY gets cleared This bit is valid only when endpoint 4 is set to OUT The MCU writes a 1 to flush the FIFO This bit can be set only when OORDY is set The packet due to be unloaded by the MCU will be flushed 10 41 USB CONTROLLER S3C2500B Table 10 24 USBEPACSR Register Description Continued 21 Out mode This bit is valid only when endpoint 4 is set to OUT SenD STALL The MCU writes 1 to this bit to issue STALL OSDSTALL handshake to the USB The MCU clears this bit to end the STALL condition 22 Out mo
162. length of preamble is determined by TxPL bit in HMODE 10 8 It is noticed that the frequency of the receive clock RxC should be slower than half of the internal system clock i e MCLK 2 Otherwise the data transfer from receive FIFO to memory could be lost 8 10 ELECTRONICS S3C2500B HDLC CONTROLLER 8 5 HDLC OPERATIONAL DESCRIPTION The following sections describe the operation of the HDLC module 8 5 1 HDLC INITIALIZATION A power on or reset operation initializes the HDLC module and forces it into the reset state After a reset the CPU must write a minimum set of registers as well as any options set based on the features and operating modes required First the configuration of the serial port and the clock mode must be defined These settings include the following Data format select BRG clock select clock select Transmit clock select Receive clock select BRG DPLL enable to use internal clock You must also set the clock for various components before each component is enabled Additional registers may also have to be programmed depending on the features you select All settings for the HDLC mode register HMODE and the HDLC control register HCON must be programmed before the HDLC is enabled To enable the HDLC module you must write a 1 to the receiver enable bit and or the transmitter enable bit During normal operation you can disable the receiver or the transmitter by writing a
163. long enable bit in the receive control register MACRXCON is set Parity error RxParErr This bit is set if a parity error is detected in the MAC RxFIFO Factorial test bit 15 7 Not applicable 16 BDMA Rx done in every This bit is set each time the BDMA receiver moves one received frames BRxDone received data frame to memory This bit must be cleared for the next frame interrupt generation 17 BDMA Rx not owner BRxNO This bit is set when BDMA is not the owner and the reception process is stop 18 BDMA Rx maximum size over This bit is set when the value of received frame size is larger BRxMSO than one of the Rx frame maximum size 19 BDMA RxBUFF Full BRxFull This bit is set when the BDMA RxBUFF is in the full flag state 20 Early notification BRxEarly This bit is set when the BDMA moves the Length Ether type field of the current frame to the external memory 21 One more frame data in BDMA This bit is set whenever an additional data frame is received in RxBUFF BRxFRF read only the BDMA receive buffer 26 22 Number of frames BRxBUFF These bits appear number of frames in BRXBUFF read only 81 27 Not applicable emp 7 22 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 4 1 11 BDMA Receive Frame Size Register Table 7 24 BDMARXLEN Register BDMARXLENB 0xF00C0028 Undefined Table 7 25 BDMA Receive Frame Size Register Description BDMA Rx Buffer Size T
164. master IC generates the timing and terminates the transfer The master IC is always responsible for generating the clock signals on the C Bus clock signals from a master can only be altered by 1 a slow slave IC which stretches the signal by temporarily holding the clock line Low or 2 by another master IC during arbitration 6 4 2 GENERAL CHARACTERISTICS Both SDA and SCL are bi directional lines which are connected to a positive supply voltage through a pull up resistor When the is free the SDA and SCL lines are both high level The output stages of interfaces connected to the bus have an open drain or open collector to perform the wired AND function Data on the be transferred at a rate up to 100K bits s The number of interfaces that can be connected to the bus is solely dependent on the limiting bus capacitance of 400 pF 6 4 3 BIT TRANSFERS Due to the variety of different ICs CMOS NMOS I2L for example which can be connected to the the levels of logic zero low and logic one high are not fixed and depend on the associated level of Vpp One clock pulse is generated for each data bit that is transferred 6 4 ELECTRONICS S3C2500B 2 CONTROLLER 6 4 4 DATA VALIDITY The data on the SDA line must be stable during the high period of the clock The high or low state of the data line can only change when clock signal on the SCL line is low 6 4 5 START AND STOP CONDITIONS Start and s
165. monitoring internal clock such as the transmitter clock receiver clock and baud rate generator output clocks General I O Port 1 26 ELECTRONICS HTXCO FSC GPIO47 HRXCO DCL 1 46 S3C2500B PRODUCT OVERVIEW Table 1 1 S3C2500B Signal Descriptions Continue Group PinName Pin Type PadType Description HDLC1 HTXD1 GPIO48 1 phbst16 HDLC Ch 1 Transmit Data 8 See the HTXDO description General I O Port HRXD1 GPIO49 phbst8 HDLC Ch 1 Receive Data See the HRXDO description General I O Port phbst16 HDLC Ch 1 Data Terminal Ready See the HnDTRO description General I O Port phbst16 HDLC Ch 1 Request To Send See the HnRTSO description General I O Port phbst8 HDLC Ch 1 Clear To Send See the HnCTSO description General I O Port phbst8 HDLC Ch 1 Data Carrier Detected See the HnDCDO description General I O Port HnDTR1 GPIO50 HnRTS1 GPIO51 HnCTS1 GPIO52 HnDCD1 GPIO53 HTXC1 GPIO55 HnDTR2 GPIO58 HnRTS2 GPIO59 HnCTS2 GPIO60 aD ELECTRONICS 1 27 phbst8 HDLC Ch 1 Transmitter Clock See the HTXCO description General I O Port phbst8 HDLC Ch 2 Transmit Data See the HTXDO description General I O Port phbst8 HDLC Ch 2 Receive Data See the HRXDO description General I O Port phbst8 HDLC Ch 2 Data Terminal Ready See the HnDTRO description General I O Port phbst8 HDLC Ch 2 Request To Send See the HnRTSO description General I O Port phbst8 HDLC Ch 2 Clear To Send See
166. offset from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 0 to 7 This means that half words accessed at offsets 0 and 2 from the word boundary will be correctly loaded into bits O through 15 of the register Two shift operations are then required to clear or to sign extend the upper 16 bits A word store STR should generate a word aligned address The word presented to the data bus is not affected if the address is not word aligned That is bit 31 of the register being stored always appears on data bus output 31 ELECTRONICS 3 29 INSTRUCTION SET S3C2500B Register LDR from word aligned address Memory Register LDR from address offset by 2 Figure 3 15 Little Endian Offset Addressing 3 9 3 2 Big Endian Configuration A byte load LDRB expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary on data bus inputs 23 through 16 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros Please see Figure 2 1 A byte store STRB repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0 The external memory system should activate the appropriate byte subsystem to store the data A word load LDR should generate a word aligned address An address offset of 0 or 2 from
167. performance options and to support phased conversions Full IEEE 802 3 compatibility for existing applications Media Independent interface MII or 7 wire interface Station management STA signaling for external physical layer configuration and link negotiation On chip CAM 21 MAC addresses Full duplex mode for doubled bandwidth Hardware support of pause operation for full duplex flow control Long frame mode for specialized environment Short frame mode for fast testing PAD generation for easy processing and reduced processing time ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 3 MAC FUNCTION BLOCKS The major function blocks of each Ethernet of MAC layer are described in Table 7 1 and Figure 7 1 Table 7 1 MAC Function Block Descriptions Media Independent The interface between the physical layer and the transmit receiver blocks Interface MII Transmitter block Moves the outgoing data from the transmit buffer to the MII This includes circuits for generating the CRC checking parity and generating preamble or jam Also has timers for back off after collision and the inter frame gap follows a transmission Receiver block Accepts incoming data from the and stores it in the MRxFIFO The receiver block has logic for computing and checking the CRC value generating parity for data from the and checking minimum and maximum frame lengths Also has a CAM that provides for address lookup and for acceptance or rejection for
168. register Rn this calculation may be performed either before P 1 or after P 0 the base is used as the transfer address The modified base value may be overwritten back into the base register if W 1 or the old value of the base may be preserved W 0 Note that post indexed addressing modes require explicit setting of the W bit unlike LDR and STR which always write back when post indexed The value of the base register modified by the offset in a pre indexed instruction is used as the address for the transfer of the first word The second word if more than one is transferred will go to or come from an address one word 4 bytes higher than the first transfer and the address will be incremented by one word for each subsequent transfer 3 15 3 ADDRESS ALIGNMENT The base address should normally be a word aligned quantity The bottom 2 bits of the address will appear on A 1 0 and might be interpreted by the memory system 3 15 4 USE OF R15 If Rn is R15 the value used will be the address of the instruction plus 8 bytes Base write back to R15 must not be specified 3 15 5 DATA ABORTS If the address is legal but the memory manager generates an abort the data trap will be taken The write back of the modified base will take place but all other processor state will be preserved The coprocessor is partly responsible for ensuring that the data transfer can be restarted after the cause of the abort has been resolved and must e
169. register 0x00000000 USBPM 0 00 0004 USB power management register 0x00000000 USBFN USBframenumberregister 0 00000000 USBINTR 0 00 0008 USB interrupt register 0 00000000 USBINTRE 0 00 000 USB interrupt enable register 0x00000000 Reserved 4 J me Pe 0xF00E007C RIW W ELECTRONICS 1 39 PRODUCT OVERVIEW S3C2500B Table 1 14 S3C2500B DES Controller DESSTA 600904 DESGDESsusregster oX00000251 DESOUTFIFO OxF0090034 FIFO 7 00000000QX 1 40 ELECTRONICS S3C2500B PRODUCT OVERVIEW Table 1 15 S3C2500B GDMA Controller DPRIC OxF0051000 priority configuration register 0x00000000 DPRIF 0xF0052000 programmable priority register for fixed 0 00543210 DPRIR 0 0053000 GDMA programmable priority register for round 0 00000000 robin DCONO 0 00000000 DSARO 0 00000000 DDARO 000000000 DTCRO 000000000 DRERO 000000000 DIPRO 000000000 DCON 0 00000000 DSAR 0 00000000 DDAR 0x00000000 DTCR 000000000 0 00000000 0 00000000 DCON2 000000000 DSAR 000000000 DAR 0 00000000 DTCR 0 00000000 DRER 0 00000000 DIPR2 000000000 000000000 DSARS 0 00000000 DDARS 000000000 DTCRS 0 00000000 DRERS 0 00000000 DIPRS 0 00000000 DCON4 000000000 DSAR4 000000000 DDAR4 0x00000000 DTCR4 0x00000000 ELECTRONICS 1 41 PRO
170. signal is asserted during Transmit operation High Speed UART transmits TX DATA to TX line normally When CTS signal is deasserted during Transmit operation If CTS signal is deasserted when High Speed UART transmits TX DATA to TX line High Speed UART stops data transmission immediately In this case transmitting TX data will be lost Hardware Flow Control for Receive Operation In the hardware flow control during High Speed UART receive data from Rx pin DCD level have to be low If DCD level goes high received data will be pull up by High Speed UART Rx block from that time 14 24 ELECTRONICS S3C2500B SERIAL HIGH SPEED UART lt 4 Data Size Start Bit Figure 14 15 When Signal is Asserted During Transmit Operation lt 4 Data Region Start Bit Stop Bit Figure 14 16 When CTS Signal is De asserted During Transmit Operation ELECTRONICS 14 25 SERIAL HIGH SPEED UART S3C2500B 4 4 Data Region Start Bit Stop Bit Figure 14 17 Normal Received Rx Data 4 Data Region RXD Pin Signal Start Bit Stop Bit DCD RXD Internal Start Bit Signal Figure 14 18 DCD Lost During Rx Data Receive 14 4 3 SOFTWARE FLOW CONTROL Software can control High Speed UART by control characters High Speed UART compares received data with control characters if they are identical it sets 1 at state bit CCD HUSTAT 5 and generates interrupt which maske
171. so that it remains stable low during the high period of this clock pulse Usually a receiver which has been addressed is obliged to generate an acknowledge after each byte is received When a slave receiver does not acknowledge from the slave address the slave must leave the data line high The master can then generate a stop condition to abort the transfer If a slave receiver acknowledges the slave address but later in the transfer cannot receive any more data bytes the master must again abort the transfer This is indicated by the slave not generating the acknowledge on the first byte to follow The slave leaves the data line high and the master generates the stop condition If a master receiver is involved in a transfer it must signal the end of data to the slave transmitter by not generating an acknowledge on the last byte that was clocked out of the slave The slave transmitter must then release the data line to let the master generate the stop condition 6 6 ELECTRONICS S3C2500B 2 CONTROLLER 6 4 6 3 Data Transfer Format Data transfers uses the format shown in Figure 6 5 After the start condition has been generated a 7 bit slave address is sent The eighth bit is a data direction bit R W A 0 direction bit indicates a transmission Write and a 1 indicates a request for data Read A data transfer is always terminated by a stop condition which is generated by the master However if a master still wishes to communic
172. specified use suitable mnemonics will be added to the assembler Until such time this instruction must not be used 3 58 ELECTRONICS S3C2500B 3 18 INSTRUCTION SET EXAMPLES INSTRUCTION SET The following examples show ways in which the basic ARM9TDMI instructions can combine to give efficient code None of these methods saves a great deal of execution time although they may save some mostly they just save code 3 18 1 USING THE CONDITIONAL INSTRUCTIONS Using Conditionals for Logical OR CMP Label CMP Rm q BEQ Label This can be replaced by CMP Rn p CMPNE Rm q BEQ Label Absolute Value TEQ Rn 0 RSBMI Rn Rn 0 Multiplication by 4 5 or 6 Run Time MOV Rc Ra LSL 2 CMP Rb 5 ADDCS Rc Rc Ra ADDHI Combining Discrete and Range Tests TEQ 127 CMPNE 1 MOVLS ELECTRONICS If Rn p OR Rm q THEN GOTO Label If condition not satisfied try other test Test sign and 2 s complement if necessary Multiply by 4 Test value Complete multiply by 5 Complete multiply by 6 Discrete test Range test IF lt Rc ASCII 127 THEN 3 59 INSTRUCTION SET Division and Remainder S3C2500B A number of divide routines for specific applications are provided in source form as part of the ANSI C library provided with the ARM Cross development toolkit available from your supplier A short general purpose divi
173. state of RxDATA 14 10 ELECTRONICS S3C2500B SERIAL HIGH SPEED UART Table 14 6 High Speed UART Status Register Description Continued 12 Receive Event time out E RXTO 13 AutoBaud Rate Detection AUBDDN 14 Data Set ready DSR 15 Clear To Send CTS 16 CTS Event occurred E CTS 17 Transmitter Idle TI 18 Transmit Holding Register Empty THE 19 Transmit FIFO Empty TFEMT 20 Transmit FIFO full TFFUL 31 21 Not applicable up ELECTRONICS During Receive FIFO mode if there is a valid data in URXFIFO or Receive FIFO within a promised time internal which is determined according to Length this bit is set to 1 URXFIFO is for non FIFO mode and Receive FIFO is for FIFO mode If the E RxTO interrupt enable bit HUINT 12 is 1 an interrupt is generated when a receive event time out is detected and valid data reside in HURXBUF or Receive FIFO You can clear this bit by writing 1 to this bit NOTE Event time WL 4 12 This bit set to one when the Rx data resides in RxFIFO This bit is automatically set to 1 when high speed UART finishes AutoBaud Rate Detection procedure You can clear this bit by writing 1 to this bit This bit is only for CPU to monitor High Speed UART When HUnDSRO HUnDSR1 level is low this bit is set And HUnDSRO0 HUnDSR1 high this bit is cleared This bit is only for CPU to monitor High Speed UART When HUnCTSO H
174. such as a coding violation by asserting the input pin RX ER When the MAC sees RX ER asserted it sets CRCErr bit of the BMRXSTAT register Frame too long The receiver block checks the length of the incoming frame at the end of reception including CRC but excluding preamble and SFD If the length is longer than the maximum frame size of 1518 bytes the receiver block reports receiving a long frame unless long frame mode is enabled The receiver can detect network related errors such as CRC frame alignment and length errors It can also detect these types of errors in the following combinations CRC errors only Frame alignment and CRC errors only Length and CRC errors only Frame alignment length and CRC errors MRxFIFO full During the reception the incoming data are put into the MRxFIFO temporarily before they are transferred to the system memory If the MRxFIFO is filled up because of excessive system latency or for other reasons the receiver block sets the overrun bit in the BMRXSTAT register MII error The PHY informs the MAC if it detects a medium error such as a coding violation by asserting the input pin Rx er When the MAC sees Rx er asserted it sets CRCErr bit of the receive status register ELECTRONICS 7 49 ETHERNET CONTROLLER S3C2500B 7 5 5 TIMING PARAMETERS FOR MII TRANSACTIONS The timing diagrams in this section conform to the guidelines described in the Draft Supplement to ANSI IEEE Std
175. targeted at a wide range of embedded control applications where high performance low system cost small die size and low power are key considerations The ARM940T processor macrocell provides a complete high performance CPU subsystem including ARM9TDMI RISC integer CPU caches write buffer and protection unit with an AMBA ASB bus interface Providing a complete high frequency CPU subsystem frees the system on a chip designer to concentrate on design issues unique to their system The ARM9TDMI core within the ARM940T macrocell executes both the 32 bit ARM and 16 bit Thumb instruction sets allowing the user to trade off between high performance and high code density It is binary compatible with ARM7TDMI ARM10TDMI and StrongARM processors and is supported by a wide range of tools operating systems and application software The 940 processor macrocell is designed to be integrated into larger chips It supports EmbeddedICE software and hardware debug and efficient production test when embedded in larger devices The Advanced Microcontroller Bus Architecture AMBA provides a high performance 32 bit System Bus ASB and a low power peripheral bus APB The ASB is re used to provide a channel for production test vectors with low silicon and pin overhead The ASB is a multi master on chip bus interface designed specifically to address the needs of system on a chip designs The EmbeddedICE software and hardware debug features of the ARM9
176. that it has entered an idle state in one of the following two ways 1 by transmitting a continuous series of flag patterns time fill or 2 by transmitting a stream of consecutive 1s mark idle The flags and mark idle are not transferred to the HRXFIFO The flag or mark idle selection bit TXFLAG in HCON controls this function when TxFLAG is 0 mark idle is selected when TxFLAGIDLE is 1 the time fill method is selected 8 6 ELECTRONICS S3C2500B HDLC CONTROLLER 8 4 5 FIFO STRUCTURE In both transmit and receive directions 32 byte 8 word deep FIFOs are provided for the intermediate storage of data between the serial interface and the CPU Interface 8 4 6 TWO CHANNEL DMA ENGINE The HDLC module has two channel engine for FIFOs The TX channel programming and the RX channel programming are described in the transmitter and receiver operation sections respectively 8 4 7 BAUD RATE GENERATOR The HDLC module contains a programmable baud rate generator BRG The BRG register contains a 16 bit time constant register a 12 bit down counter for time constant value two control bit to divide 16 and another two control bits to divide 16 or 32 A clock diagram of the BRG is shown in Figure 8 2 At a start up the flip flop on the output is set in a High state the value in the time constant register is loaded into the counter and the counter starts counting down The output of the baud rate generator may
177. that of the equivalent ARM instruction Examples ADD RO R3 R4 R4 and set condition codes on the result SUB R6 R2 6 R2 6 set condition codes ELECTRONICS 3 69 INSTRUCTION SET S3C2500B 3 22 FORMAT 3 MOVE COMPARE ADD SUBTRACT IMMEDIATE 15 14 13 7 0 12 11 10 8 opel SSS 7 0 Immediate Value 10 8 Source Destination Register 12 11 Opcode 0 MOV 1 2 ADD 3 SUB Figure 3 32 Format 3 3 22 1 OPERATIONS The instructions in this group perform operations between a Lo register and an 8 bit immediate value The THUMB assembler syntax is shown in Table 3 10 NOTE All instructions in this group set the CPSR condition codes Table 3 10 Summary of Format 3 Instructions 00 MOV Rd 4Offset8 5 Rd Offset8 8 bit immediate value into Rd Rd Offset8 Rd Offset8 Compare contents of Rd with 8 bit immediate value 10 ADD Rd Offset8 ADDS Rd Offset8 Add 8 bit immediate value to contents of Rd and place the result in Rd 11 SUB Rd Offset8 SUBS Rd Offset8 Subtract 8 bit immediate value from contents of Rd and place the result in Rd 3 22 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 10 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples MOV RO 128
178. the Broadcast address For example 01 00 00 00 00 00 CAM comparison mode 1 MNegCAM 0 The CAM controller compares the destination address of the incoming frame with the CAM addresses enabled by the CAM Enable CAMEN register The controller accepts only the frames with the matched destination addresses Negative CAM comparison mode MCompEn 1 MNegCAM 1 The address comparison is same as the CAM comparison mode But the CAM controller rejects the frames with the matched destination addresses and accepts frames with the address outside the CAM address enabled No CAM comparison mode MCompEn 0 The CAM controller accepts frames with all types of destination addresses Table 7 30 CAMCON Register OxF00BO004 CAM control 0x00000000 CAMCONB OxF00D0004 CAM control 0x00000000 Table 7 31 CAM Control Register Description Station accept MStation Set this bit to accept unicast i e station frames Group accept MGroup Set this bit to accept multicast i e group frames 7 26 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 4 2 4 MAC Transmit Control Register Table 7 32 MACTXCON Register MACTXCONA 0xF00B0008 0 00000000 MACTXCONB OxF00D0008 0 00000000 Table 7 33 MAC Transmit Control Register Description Transmit enable MTxEn Set this bit to enable transmission To stop transmission immediately clear the transmit enable bit to 0 Transmit halt reques
179. the HnCTSO description General I O Port HRXC1 GPIO54 phbst8 HDLC Ch 1 Receiver Clock See the HRXCO description General Port PRODUCT OVERVIEW S3C2500B Table 1 1 S3C2500B Signal Descriptions Continue Group PinName Pin PadType Description HDLC2 HnDCD2 1 phbst8 HDLC Ch 2 Data Carrier Detected 8 GPIO61 See the HnDCDO description General I O Port HRXC2 1 phbst8 HDLC Ch 2 Receiver Clock GPIO62 See the HRXCO description General I O Port HTXC2 1 phbst8 HDLC Ch 2 Transmitter Clock GPIO63 See the HTXCO description General I O Port 6 USB_FILTER B pbusbfs Internal USB transceiver differential I O pbusbfs Internal USB transceiver differential I O phic USB clock source input phic USB Clock Select When USB CLKSEL is 0 USB PLL output is used as the USB clock When USB_CLKSEL is 17 the USB XCLK is usedas the USB clock See Figure 4 5 poar50_abb Filter for USB PLL If the PLL is used 320pF capacitor should be connected between the pin and ground phis Console UART Receive Data phob8 Console UART Transmit Data Phi F HUART External Clock for HUARTO HUARTI phbst8 HUARTO Receive Data HURXDO is the HUARTO input signal for receiving serial data General Port phbst8 HUARTO Transmit Data HUTXDO is the HUARTO output signal for transmitting serial data General I O Port phbst8 Not HUARTO Data Terminal Ready This output signals the
180. the corresponding interrupt request is generated If the mask bit is 0 the interrupt is serviced upon request The 32 interrupt sources are mapped as follows 31 Watchdog Timer interrupt 0 non Masking 1 Masking 30 32 bit Timer 5 interrupt 29 32 bit Timer 4 interrupt 28 32 bit Timer 3 interrupt 27 32 bit Timer 2 interrupt 26 32 bit Timer 1 interrupt 25 32 bit Timer 0 interrupt 24 GDMA channel 5 interrupt 23 GDMA channel 4 interrupt 22 GDMA channel 3 interrupt 21 GDMA channel 2 interrupt 20 GDMA channel 1 interrupt 19 GDMA channel 0 interrupt 18 DES interrupt 17 Ethernet 1 RX interrupt 16 Ethernet 1 TX interrupt 15 Ethernet 0 RX interrupt 14 Ethernet 0 TX interrupt 13 HDLC 2 RX interrupt 12 HDLC 2 TX interrupt 11 HDLC 1 RX interrupt 10 HDLC 1 TX interrupt 9 HDLC 0 RX interrupt 8 HDLC 0 TX interrupt 7 USB interrupt 6 CUART RX interrupt 5 CUART TX interrupt 4 HUART 1 RX interrupt 3 HUART 1 TX interrupt 2 HUART 0 RX interrupt 1 HUART 0 TX interrupt 0 interrupt Figure 16 3 Internal Interrupt Mask Register INTMASK 16 6 ELECTRONICS S3C2500B INTERRUPT CONTROLLER 31 30 29 28 27 26 25 24 23 22 21 2019 18 17 16 15 14 13 1211109 8 7 6 5 4 3 2 4 EXTMASK 6 0 Individual external interrupt mask bits NOTE Eachofthe 7 bits in the external interrupt mask register EXTMASK except for the globa
181. to facilitate connecting components that do not directly support IOM2 These are 1x Bit rate Clock BCL and two Serial Data Strobes that identify the location of the B channels SDS1 5052 The S3C2500B includes two optional signals BCL and 8051 5051 is called STRB 53 2500 In S3C2500B the terminal mode operation is supported but line card mode is not supported Figure9 1 shows the IOM2 channel structure in terminal mode 2 MR MX MR MX BAC TAD Figure 9 1 IOM2 Channel Structure in Terminal DU DD 768 kbit s DU data upstream output DD data downstream input DCL 1536 kHz input Double Data Rate FSC 8 kHz input BCL 768 kHz output STRB strobe signal for non IOM2 device 9 2 ELECTRONICS S3C2500B IOM2 CONTROLLER 9 3 1 B CHANNELS The B1 and B2 provide two clear 64 Kbit s user data channels to from the network 9 3 2 D CHANNEL The 16 Kbit s D channel provides a connection between the layer 2 and layer 1 components 9 3 3 MONITOR CHANNELS There are two programming channels monitors 0 and 1 Each channel has an associated pair of MX and MR handshake bits that control data flow 9 3 4 COMMAND AND INDICATE CHANNELS Three Command and Indicate channels C I1 C I2 provide real time status between devices connected via the IOM2 bus 9 3 5 INTERCOMMUNICATION CHANNELS Two intercommunication data channels IC1 and IC2 provide 64 Kbit s data paths betwee
182. to send an acknowledge automatically after each byte This bit must be when the controller is operating in receiver mode and requires no further data to be received from the slave transmitter This causes a negative acknowledge on the which halts further reception from the slave device 5 4 COND1 CONDO These bits control the generation of the start stop and repeat start conditions 00 no effect 01 start 10 stop and 11 repeat start When start condition BF bit should be set simultaneously When repeat start condition ACK bit should be set simultaneously 6 Bus busy BUSY This bit is a read only flag that indicates when the I C is in use indicates that the bus is busy This bit is set or cleared by a start or stop condition respectively 7 Reset If 1 is written to the reset bit the controller is reset to its initial state emp ELECTRONICS 6 9 2 CONTROLLER S3C2500B Reserved 0 Buffer Flag BF 0 Automatically cleared when the IICBUF register is written or read To manually clear the BF write 0 1 Automatically set when the buffer is empty in transmit mode or when the buffer is full in receive mode 1 Interrupt enable IEN 0 Disable 1 Enable an interrupt is generated if the BF bit is 1 2 Last received bit LRB Use this read only status bit to check for ACK signals from the receiver slave or to monitor SDA operation of SDA when writing 1
183. to the host An interrupt is generated when the USB clears this bit so the MCU can load the next packet For a zero length data phase the MCU sets INRDY and DEND at the same time 26 SenT STALL The USB sets this bit if a control transaction is ended STSTALL due to a protocol violation An interrupt is generated when this bit is set 10 22 ELECTRONICS S3C2500B USB CONTROLLER Table 10 16 USBEPOCSR Register Description Continued 27 Data END R S C The MCU sets this bit DEND After loading the last packet of data into the FIFO at the same time INRDY is set While it clears ORDY after unloading the last packet of data For azero length data phase when it clears ORDY and sets INRDY 28 SETup END This is a read only bit SETEND The USB sets this bit when a control transfer ends before DEND is set The MCU clears this bit by writing a 1 to the SVSET bit When the USB sets this bit an interrupt is generated to the MCU When such a condition occurs the USB flushes the FIFO and invalidates MCU access to the FIFO When MCU access to the FIFO is invalidated this bit is cleared 29 SenD STALL The MCU writes a 1 to this bit at the same time it SDSTALL clears ORDY if it decodes a invalid token The USB issues a STALL handshake to the current control transfer The MCU writes a 0 to end the STALL condition 30 SerViced Out The MCU writes a 1 to this bit to clear ORDY ReaDY SVORDY 31 SerViced SETup The
184. transfer data it asserts TXEN 10M 1 22 ELECTRONICS S3C2500B PRODUCT OVERVIEW Table 1 1 S3C2500B Signal Descriptions Continue Group PinName Pin Type PadType Ethernet TX ERR 1 1 phob4 Controller1 PCOMP 10M 18 I ELECTRONICS Transmit Error Packet Compression Enable for 10M TX ERR is driven synchronously to TX and sampled continuously by the Physical Layer Entity PHY If asserted for one or more TX CLK periods TX ERR causes the PHY to emit one or more symbols which are not part of the valid data or delimiter set located somewhere in the frame that is being transmitted PCOMP 10M is asserted immediately after the packet s DA field is received PCOMP 10M is used with the Management Bus of the DP83950 Repeater Interface Controller from National Semiconductor The MAC can be programmed to assert PCOMP if there is a CAM match or if there is not a match The RIC Repeater Interface Controller uses this signal to compress shorten the packet received for management purposes and to reduce memory usage See the DP83950 Data Sheet published by National Semiconductor for details on the RIC Management Bus This pin is controlled by a special register with which you can define the polarity and assertion method CAM match active or not match active of the PCOMP signal Carrier Sense Carrier Sense for 10M CRS is asserted asynchronously with minimum delay from the
185. were discarded due to various type of errors Together with status information on frames transmitted and received the missed error count register and the two pause count registers provide the information required for station management Reading the missed error counter register clears the register It is then the responsibility of software to maintain a global count with more bits of precision The counter rolls over from Ox7FFF to 0x8000 and sets the corresponding bit in the MAC control register It also generates an interrupt if the corresponding interrupt enable bit is set If station management software wants more frequent interrupts you can set the missed error count register to a value closer to the rollover value of OX7FFF For example setting a register to 0 7 00 would generate an interrupt when the count value reaches 256 occurrences Table 7 46 MISSCNT Register MISSCNTA 0xF00B003C R CI W Missed error count 0 00000000 MISSCNTB 0xF00D003C R CI W Missed error count 0 00000000 Table 7 47 Missed Error Count Register Description Missed error count The number of valid packets rejected by the MAC unit MissErrCnt because of MAC RxFIFO overflows parity errors or because the MRxEn bit was cleared This count does not include the number of packets rejected by the CAM 91 16 Not applicable 7 34 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 4 2 12 MAC Received Pause Count Register The
186. when endpoint 1 is set to IN STALL ISTSTALL The USB sets this bit when a STALL handshake is issued to an IN token due to the MCU setting SEND STALL bit When the USB issues a STALL handshake IINRDY is cleared 30 In mode CLear This bit is valid only when endpoint 1 is set to IN data TOGgle When the MCU writes a 1 to this bit the data toggle ICLTOG bit is cleared This is a write only register jReseved 10 28 ELECTRONICS S3C2500B 31 30 29 28 27 26 25 24 23 22 e gt 1000 C r T TI lt ON2 gt gt 10 10 rr 4o0o000 rocrmmo 1 S T S T A L L 2 0 MAXP value MAXP 2 0 value x 8 2 max packet size 6 3 Reserved 7 MAXP value SETting enable MAXPSET value isn t changed 1 value is changed 8 OUT ISO mode OISO 0 Bulk interrupt mode 1 2 ISO mode 9 OUT AuTo CLeaR OATCLR 0 No operation 1 Auto clearing ORDY when FIFO data unloaded 10 in out MODE setting MODE 0 Indexed endpoint set to OUT 1 Indexed endpoint set to IN 11 IN ISO mode IISO 0 Bulk interrupt mode 1 2 ISO mode 12 IN AuTo SET IATSET 0 No operation 1 Auto setting IINRDY when MAXP sized packet loaded 14 13 Reserved 15 CSR2 SETting enable CSR2SET 0 USBEP1CSR 12 8 isn t changed 1 USBEP1CSR 12 8 is changed 16 OUT Out packet ReaDY OORDY 0 Not received data packet 1 Received packet from hos
187. width is determined by the signal at the BOSIZE pins When BOSIZE 1 0 01 the external bus width for ROM SRAM Flash bank 0 is 8 bits When BOSIZE 1 0 10 the external bus width for ROM SRAM Flash bank 0 is 16 bits When BOSIZE 1 0 11 the external bus width for ROM SRAM Flash bank 0 is 32 bits BnCON register configuration is described in Figure 5 11 5 22 ELECTRONICS S3C2500B MEMORY CONTROLLER Table 5 16 Bank n Control BnCON Register BOCON OxF0010000 R W Bank 0 control register 0xC514E488 BOSIZE 3 0x8514E488 BOSIZE 2 0x4514E488 BOSIZE 1 1 0 0010004 Bank 1 control register 0xC514E488 BACON OxF0010008 Bank 2 control register 0xC514E488 ELECTRONICS 5 23 MEMORY CONTROLLER 31 30 29 28 27 24 23 22 21 20 16 15 12 11 S3C2500B Tow ruc wee see D ee 3 0 Chip selection hold time on nOE TCOH 0000 0 cycle 0100 4 cycles 1000 8 cycles 1100 12 cycles 7 4 Chip selection setup time on nOE 0000 0 cycle 0100 4 cycles 1000 8 cycles 1100 12 cycles 0001 1 cycle 0101 5 cycles 1001 9 cycles 1101 13 cycles 0001 1 cycle 0101 5 cycles 1001 9 cycles 1101 13 cycles 11 8 Address setup time TACS 0000 0 cycle 0100 4 cycles 1000 8 cycles 1100 12 cycles 0001 1 cycle 0101 5 cycles 1001 9 cycles 1101 13 cycles 0010 2 cycles 0110 6 cycles 1010 10 cycles 1110 14 cycles TCOS 0010
188. will also occur automatically on return from an exception IRQ FIQ UNDEF ABORT SWI etc if the exception was entered with the processor in THUMB state 2 2 2 ENTERING ARM STATE Entry into ARM state happens 1 On execution of the BX instruction with the state bit clear in the operand register 2 On the processor taking an exception IRQ FIQ RESET UNDEF ABORT SWI etc In this case the PC is placed in the exception mode s link register and execution commences at the exception s vector address ELECTRONICS 2 1 PROGRAMMER S MODEL S3C2500B 2 3 MEMORY FORMATS ARM9TDMI views memory as a linear collection of bytes numbered upwards from zero Bytes 0 to hold the first stored word bytes 4 to 7 the second so ARM9TDMI can treat words in memory as being stored either in Big Endian or Little Endian format 2 3 1 BIG ENDIAN FORMAT In Big Endian format the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte Byte 0 of the memory system is therefore connected to data lines 31 through 24 Higher Address Word Address Lower Address Most significant byte is at lowest address Word is addressed by byte address of most significant byte Figure 2 1 Big Endian Addresses of Bytes within Words NOTE The data locations in the external memory are different with Figure 2 1 in the S3C2500B Please refer to the chapter 4 system manager
189. with Immediate 3 81 3 281 pcc 3 81 3 28 2 Instruction Cycle TIMES 3 82 3 29 Format 10 Load Store 3 83 B29 merce Mp xc S 3 83 3 29 2 Instruction Cycle 3 83 3 30 Format 11 SP Relative Load Store 3 84 EO or eco MR ern 3 84 3 30 2 Instruction Cycle nnns 3 84 3 31 Format 12 Load 3 85 Operatori sanie nx cR 3 85 3 31 2 Instruction Cycle Times 3 86 3 32 Format 13 Add Offset to Stack 3 87 3 32 1 Operatora Rc c cs 3 87 3 32 2 Instruction Cycle Times 3 87 3 33 Format 14 Push Pop 3 88 3 33 OPSFAUCM 3 88 3 33 2 Instruction Cycle 3 89 3 34 Format 15 Multiple 2 3 90 3 94 ashen 3 90 3 34 2 Instruction Cycle 0 22 0000
190. x 22 46 X X x x x x x 1 o o o o ojo o o o o 22 29m X X x x x x 1 o o o o o oj o o o o o 2 qa25sms x x x x x o o o o o o ojo o o o o z5estesms x x x x 1 ojo o o o o ojo o o o o 2 603m x x x o o ojojo oj o o aos x x i o ojo jo o o o o ojojo oj o o 22209 x rjojo ojo ojojoj o ojo ojo o ojo o 2 2600 17 10 ELECTRONICS S3C2500B ELECTRICAL DATA ELECTRICAL DATA 18 1 OVERVIEW This chapter describes the S3C2500B electrical data 18 2 ABSOLUTE MAXIMUM RATINGS Table 18 1 Absolute Maximum Ratings UM DC supply voltage V m 330 mA Tes Sempetmpemue L 6 18 3 RECOMMENDED OPERATING CONDITIONS Table 18 2 Recommended Operating Conditions Sm Parameter raig UM ViN DC input voltage 3 3V input buffer 3 0 3 6 DC output voltage 3 3V output buffer 3 0 3 6 Commercial temperature range 40 to 85 ELECTRONICS 18 1 ELECTRICAL DATA S3C2500B 18 4 DC ELECTRICAL SPECIFICATIONS Table 18 3 D C Electric Characteristics Vpp 3 3 V 5 T4 40 to 85 C Symbol PARAMETER Condition min Wax Umi Vin High level input voltage tvomosintetace Vi Low level input voltage LVCMos
191. 0 29040 o 23040000 000 soso 46080000 000 821600 44 0 O 92160000 up ELECTRONICS 14 19 SERIAL HIGH SPEED UART S3C2500B 14 3 8 HIGH SPEED UART CONTROL CHARACTER 1 REGISTER This Control Character registers can be used for Software Flow control In Software Flow Control mode you should write control characters into this registers If not the reset value will be used as control character For example even if you want to use one control character all control characters will have same value with it Table 14 15 HUCHAR1 Registers 0xF0070018 R W High Speed UART control character1 register 0x00 0080018 31 24 23 16 15 8 7 0 2 CONCHAR1 CONCHARO 7 0 Control Character 0 15 8 X Control Character 1 23 16 Control Character 2 31 24 Control Character 3 Figure 14 9 High Speed UART Control Character 1 Register 14 20 ELECTRONICS S3C2500B SERIAL HIGH SPEED UART 14 3 9 HIGH SPEED UART CONTROL CHARACTER 2 REGISTER This Control Character registers can be used for Software Flow control In Software Flow Control mode you should write control characters into this registers If not the reset value will be used as control character For example even if you want to use one control character all control characters will have same value with it Table 14 16 HUCHAR2 Registers HUCHAR2 OxF00700
192. 0000 8 27 8 7 2 HDLC Control Register s 8 30 8 7 3 HDLC Status Register 22 0 0 8 36 9 74 8 36 8 7 5 HDLC Interrupt Enable 7 8 42 8 Spa e c PL 8 44 ADEG RX FO aqa PM u 8 45 8 7 8 HDLC Brg Time Constant 8 46 8 7 9 HDLC Preamble Constant 8 47 8 7 10 HDLC Station Address Registers and Hmask 8 48 8 7 11 Tx Buffer Descriptor Pointer 8 49 8 7 12 Rx Buffer Descriptor Pointer 2 8 50 8 7 13 Maximum Frame Length 8 50 8 7 14 Receive Buffer Size 8 51 8 7 15 Synchronization 8 51 8 7 16 Transparent Control Register 8 52 8 7 17 Tx Buffer Descriptor Count 8 53 8 7 18 Rx Buffer Descriptor Count Register 8 53 8 7 19 Tx Buffer Descriptor Maximum Count Register 8 54 8
193. 0000 BRXBDCNTB 000000000 BMTXINTENB 000000000 BMRXINTENB 000000000 BMTXSTATB 000000000 BMRXSTATB 0x00000000 BDMARXLENB 0x00000000 CFTXSTATB 0xFO0COO30 Transmit control frame status 0 00000000 MACCONB 0x00000000 CAMCONB 0x00000000 MACTXCONB 0x00000000 MACTXSTATB 0x00000000 MACRXCONB 000000000 MACRXSTATB 000000000 STADATAB 000000000 STACONB 000006000 CAMENB 000000000 MISSCNTB OxFO0DO03C R Cir W Missed error count 1 0 00000000 PZCNTB OxFOODOO40 00000000 RMPZCNTB 0 0000044 Remotepausecount 0x00000000 CAMB 0 0000080 W CAM content 32 words Undefined OxFOODOOFC 7 14 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 4 1 BDMA RELATIVE SPECIAL REGISTER 7 4 1 1 Buffered DMA Transmit Control Register Table 7 4 BDMATXCON Register BDMATXCONA OxF00A0000 Buffered DMA transmit control register 0x00000000 BDMATXCONB OxF00C0000 Buffered DMA transmit control register 0x00000000 Table 7 5 BDMA Transmit Control Register Description 3 0 BDMA Tx Number of Buffer You can select number of buffer descriptor Descriptor BTxNBD 0000 2 0001 2 0010 22 11 2 6 4 BDMA transmit to MAC Tx These bits determine when to move the data of the new frame in start level BTxMSL the BDMA Tx Buffer to the MAC TxFIFO MTxFIFO at a new frame arrival 000 means no wait 001 means wait to fill 1 8 of the BDMA Tx Buffer 010 means wait to fil
194. 000000 WBTO 15 0 Write buffer time out delay time 0x00000000 3116 Reseved A write to merging write buffer loads the value in the timeout register into the time out down counter of the buffer When the time out counter reaches 0 the merging write buffer contents is written flushed to the external memory The down counter is clocked by system bus clock Storing a value of 0 in the timeout register disables the write buffer timeout function 31 16 15 0 RESERVED WBTO 15 0 Write buffer time out delay time 31 16 Reserved Figure 5 26 SDRAM Write Buffer Time out Register ELECTRONICS 5 53 S3C2500B MEMORY CONTROLLER 5 7 10 SDRAM CONTROLLER TIMING nSDRAS nSDCAS o gt o lt z o a Figure 5 27 Single Read Operation CAS Latency 2 ELECTRONICS 5 54 MEMORY CONTROLLER S3C2500B nSDRAS nSDCAS o gt o lt z o a 3 28 Single Read Operation CAS Latency Figure 5 5 55 ELECTRONICS S3C2500B MEMORY CONTROLLER nSDRAS nSDCAS o z lt z a Figure 5 29 Single Write Operation ELECTRONICS 5 56 MEMORY CONTROLLER S3C2500B nSDRAS nSDCAS o 2 5 lt z S a 2 Figure 5 30 Burst Read Operation CAS Latency 5 57 ELECTRONICS S3C2500B MEMORY CONTROLLER nSDRAS nSDCAS o 2 5 lt o a 3 Figure 5 31 Burst Read Operation CAS Latency ELECTRONICS 5 58 MEMORY CONTRO
195. 0008 Table 14 8 High Speed UART Interrupt Enable Register Description 2 S z i Qs j pus reeves 14 14 ELECTRONICS S3C2500B SERIAL HIGH SPEED UART 19 18 17 16 15 14 13 12 11 10 9 8 m m O 3 0 Receive Data Valid Interrupt Enable RDVIE 1 Break Signal Detected Interrupt Enable BKDIE 2 Frame Error Interrupt Enable FERIE 3 Parity Error Interrupt Enable PERIE 4 Overrun Error Interrupt Enable OERIE 5 Control Character Detect Interrupt Enable CCDIE 6 Data Carrier Detect Lost Interrupt Enable DCDLIE 7 Receive FIFO Data Trigger Level Reach Interrupt Enable RFREAIE 9 8 Reserved 10 Receive FIFO overrun Interrupt Enable OVFFIE 11 Reserved 12 Receive Event Time out Interrupt Enable E RxTOIE 13 AutoBaud Rate Detection done interrupt enable AUBDDNIE 15 14 Reserved 16 CTS event occured Interrupt Enable E CTSIE 17 Transmitter Idle TIIE 18 Transmit Holding Register Empty Interrupt Enable THEIE This bit used in FIFO mode for interrupt enable when transmit FIFO empty as much transmit data trigger level 31 19 Reserved Figure 14 4 High Speed UART Interrupt Enable Register ELECTRONICS 14 15 SERIAL I O HIGH SPEED UART S3C2500B 14 3 4 HIGH SPEED UART TRANSMIT BUFFER REGISTER S3C2500B has a 32 byte Transmit FIFO and the bottom of FIFO is HUTXBUF All data to be
196. 051000 0x0 the programmable round robin priority is run by DPRIR register All GDMA channels own their respective field position in DPRIR The ratio of the bus occupancy can be programmed by writing an arbitrary value on each field The arbitrary value can be from 0x0 to OxF The ratio of the bus occupancy of the GDMA channel in the first field is dprir0 1 dprir5 1 dprir4 1 dprir3 1 dprir2 1 dprir1 1 dprir0 1 The reset value of DPRIR register is 0x0 So each GDMA channel has the same bus occupancy ratio when DPRIC 0x0 and the DPRIR has the reset value For example DPRIC 0x0 and the DPRIR is 0 20 100 the expected ratios of the bus occupancy of the GDMA channel 0 channel 1 channel 2 channel 3 channel 4 and channel 5 are 1 24 1 24 2 24 16 24 1 24 and 3 24 respectively Table 12 2 GDMA Programmable Priority Registers DPRIC OxF0051000 priority configuration register 0x00000000 DPRIF 0 0052000 GDMA programmable priority register for fixed 0x00543210 DPRIR 0 0053000 GDMA programmable priority register for round 0x00000000 robin 12 4 ELECTRONICS S3C2500B GDMA CONTROLLER 0 Priority configuration 0 Round robin 1 Fixed priority DPRIF 31 24 23 20 19 16 15 12 11 8 7 4 3 0 dprit5 dprif4 dprif3 dprif2 dprif1 dprif0 lt Low Priority High Priority gt DPRIR 31 24 23 20 19 16 15 12 11 8 7 4 3 0 wwe omms SPRITE SPARS DUET
197. 0B MEMORY CONTROLLER 0 0 0 cycle 0x0 0 cycle TCOS TACS 9 5 c 95 TCOH Figure 5 15 Write Timing Diagram 1 ELECTRONICS 5 30 MEMORY CONTROLLER S3C2500B 0 1 1 cycle 0 1 1 cycle Data Fetch TCOS TACS P 8 gt 10 TCOH Figure 5 16 Read Timing Diagram 2 5 31 ELECTRONICS S3C2500B MEMORY CONTROLLER 0 1 1 cycle 0 1 1 cycle TCOS TACS 8 gt wr 9 TCOH ELECTRONICS 17 Write Timing Diagram 2 Figure 5 5 32 MEMORY CONTROLLER S3C2500B Uu lt tACC gt lt 1st access cycle at tACS tACC 2nd access cycle at Bank gt l l l 1 Addr at Bank n 1 l l 1 T 1 l l J Data 1 Data 1 1 l i l l 1 l l 1 l l 1 TACC 5 5 cycles TCOH 2 2 cycle COHDIS 1 Enable 1 I 1 1 1 I 1 1 1 i Addr2 at Bank n 1 2 i 1 TCOS 1 1 cycle TACS 1 1 cycle Figure 5 18 Read after Write at the Same Bank COHDIS 1 5 33 ELECTRONICS S3C2500B MEMORY CONTROLLER Data Fetch
198. 0x00432501 the fixed priority order from the highest to the lowest is Ethernet Controller 0 General DMA HDLC Controller 2 Ethernet Controller 1 HDLC Controller 0 and HDLC Controller 1 If system configuration register 000000 SYSCFG 0 0x0 the programmable round robin priority is run by HPRIR register All AHB bus masters own their respective field position in HPRIR The ratio of the bus occupancy can be programmed by writing an arbitrary value on each field The arbitrary value can be 0x0 to OxF The ratio of the bus occupancy of the bus master in the first field is 0 1 1 4 1 3 1 2 1 1 1 0 1 The reset value of HPRIR register is 0x00000000 So each master has the same bus occupancy ratio when SYSCFG 0 0x0 and the HPRIR has the reset value For example SYSCFG 0 0 0 and the HPRIR is 0x0011F001 the expected ratios of the bus occupancy of the bus masters General Ethernet Controller 0 Ethernet Controller 1 HDLC Controller 0 HDLC Controller 1 and HDLC Controller 2 are 2 24 1 24 1 24 16 24 2 24 and 2 24 respectively ELECTRONICS 4 5 SYSTEM CONFIGURATION S3C2500B SYSCFG 0 System bus arbitration method ARB 0 Round robin 1 Fixed priority NOTE See page 4 16 4 17 24 23 20 19 16 15 12 11 8 7 4 3 0 hprif5 hprif4 hprif3 hprif2 hprif1 hprif0 lt Low Priority High Priority gt 24 23
199. 1 Table 10 18 USBEP1CSR Register Description 2 0 MAXP size value If MAXP 2 0 is 000 then MAXPsize is 0 byte MAXP If MAXP 2 0 is 001 then MAXPsize is 8 bytes If MAXP 2 0 is 010 then MAXPsize is 16 bytes If MAXP 2 0 is 011 then MAXPsize is 24 bytes If MAXP 2 0 is 100 then MAXPsize is 32 bytes 6 3 7 MAXP size SET 0 USBEP1CSR 2 0 isn t overwritten when MCU table MAXPSET writes a 32bit value to USBEP1CSR register 1 USBEP1CSR 2 0 is overwritten 8 Out mode ISO This bit is valid only when endpoint 1 is set to OUT mode OISO 0 Endpoint 1 will be Bulk mode 1 Endpoint 1 will be ISO mode Default 0 Out mode AuTo This bit is valid only when endpoint 1 is set to OUT CLeaR OATCLR If set whenever the MCU unloads last data in endpoint 1 FIFO OORDY will automatically be cleared without any intervention form MCU Default 0 in out MODE 0 Transfer direction will be OUT selection MODE 1 Transfer direction will be IN Default 1 IN In mode ISO mode This bit is valid only when endpoint 1 is set to IN 5 0 Endpoint 1 will be Bulk mode 1 Endpoint 1 will be ISO mode Default 0 ELECTRONICS 10 25 USB CONTROLLER S3C2500B Table 10 18 USBEP1CSR Register Description Continued In mode AuTo R W This bit is valid only when endpoint 1 is set to IN SET IATSET If set whenever the MCU writes MAXP data IINRDY will be automatically be set without any intervention from MCU If
200. 1 IN 11 In mode ISO mode This bit is valid only when endpoint 3 is set to IN 150 0 Endpoint 3 will be Bulk mode 1 Endpoint 3 will be ISO mode Default 0 up ELECTRONICS 10 35 USB CONTROLLER S3C2500B Table 10 22 USBEP3CSR Register Description Continued In mode AuTo R W This bit is only valid only when endpoint 3 is set to SET IATSET IN If set whenever the MCU writes MAXP data IINRDY will be automatically be set without any intervention from MCU If the MCU writes less than MAXP data then IINRDY bit has to be set by the MCU Default 0 14 13 a a 15 CSR2 SETtable 0 USBEPSCSR 12 8 isn t overwritten when MCU CSR2SET writes a 32bit value to USBEP3CSR register 1 USBEPSCSR 12 8 is overwritten 16 Out mode Out This bit is valid only when endpoint 3 is set to OUT packet ReaDY The USB sets this bit once it has loaded a packet of OORDY data into the FIFO Once the MCU reads the FIFO for the entire packet this bit should be cleared by MCU 17 Out mode Fifo This bit is valid only when endpoint 3 is set to OUT FULL OFFULL Indicates no more packets can be accepted if USBEP3CSR 1 7 16 is 00 No packet in FIFO 01 1 packet in FIFO 11 2 packet of MAXP lt 1 2 FIFO size or 1 packet of MAXP gt FIFO size 18 Out mode fifo This bit is valid only when endpoint 3 is set to OUT OVER run ISO OOVER This bit is set if the core is not able to load an OUT ISO packet into th
201. 1 to IICCON 5 4 for repeated starts 0 The most recent SDA is low is received 1 The most recent SDA is high not received 3 Acknow enable ACK Controls generation of an ACK signal in receive mode 0 Do not generate an at 9th SCL No more received data is required from the slave 1 Generate an signal at 9th SCL 5 4 COND 1 and COND 0 Generate a control such as start or stop 00 No effect 01 Generate start condition BF bit should be set simultaneously 10 Generate stop condition 11 SCL will be released to high level to generate repeated start condition ACK bit should be set simultaneously 6 Bus busy BUSY Data transmission is in progress on the IIC bus 0 Bus is currently not in use not busy 1 Bus is in use busy 7 Reset 0 Normal 1 Reset the controller 31 8 Reserved Figure 6 6 I C Control Status Register 6 10 ELECTRONICS S3C2500B 2 CONTROLLER 6 5 2 SHIFT BUFFER REGISTER IICBUF The shift buffer register for the 2 described in Table 6 4 Table 6 3 IICBUF Register IICBUF 0 00 0004 Shift buffer register Undefined Table 6 4 IICBUF Register Description 7 0 Data This data field acts as serial shift register and read buffer for interfacing to the 12C All read and write operations to from the 12 are done via this register The IICBUF register is a combination of a shift register and a data buffer
202. 10 5 10 USB ENDPOINT 3 COMMON STATUS REGISTER This register includes the control bits status bits IN OUT status information and max packet size value for endpoint 3 Table 10 21 USBEP3CSR Register USBEP3CSR 0 00 0024 USB Endpoint 3 Common Status Register 0x00000401 Table 10 22 USBEP3CSR Register Description 3 0 size value If MAXP 3 0 is 0000 then MAXPsize is 0 byte If MAXP 3 0 is 0001 then MAXPsize is 8 bytes If MAXP 3 0 is 0010 then MAXPsize is 16 bytes If MAXP 3 0 is 0011 then MAXPsize is 24 bytes If MAXP 3 0 is 0100 then MAXPsize is 32 bytes If MAXP 3 0 is 0101 then MAXPsize is 40 bytes If MAXP 3 0 is 0110 then MAXPsize is 48 bytes If MAXP 3 0 is 0111 then MAXPsize is 56 bytes If MAXP 3 0 is 1000 then MAXPsize is 64 bytes 6 4 MAXP size 0 USBEP3CSR 3 0 isn t overwritten when MCU SETtable writes a 32bit value to USBEP3CSR register MAXPSET 1 USBEPSCSR 3 0 is overwritten 8 Out mode ISO This bit is valid only when endpoint 3 is set to OUT mode OISO 0 Endpoint 1 will be Bulk mode 1 Endpoint 1 will be ISO mode Default 0 9 Out mode AuTo This bit is valid only when endpoint 3 is set to OUT CLeaR OATCLR If set whenever the MCU unloads last data in endpoint 1 FIFO OORDY will automatically be cleared without any intervention form MCU Default 0 10 in out MODE 0 Transfer direction will be OUT selection MODE 1 Transfer direction will be IN Default
203. 101 these bits don t care 11 10 Destination address These bits control whether the destination address will be increased direction 00 decreased 01 or fixed 10 during a GDMA operation The fixed 10 means the destination address will not be changed during a GDMA operation You use this fixed feature when transferring data from multiple sources to a single destination When DCON MODE 3 1 is HUART TX mode HUART from memory 010 or DES IN mode DES from memory 100 these bits don t care 12 Interrupt enable If the interrupt enable bit is 1 a interrupt is generated when GDMA operation completes successfully If this bit is 0 the GDMA interrupt is not generated If you stop the GDMA operation by resetting the run enable bit the GDMA interrupt is not generated regardless of this bit 16 13 External GDMA ACK These bits control how many cycles of the external GDMA count acknowledgement signals provided If the slow external devices want GDMA service the slow external devices can sample the external GDMA ACK signal by setting these bits These bits provide the range of 1 and 16 cycles If these bits are 0000 the single cycle of the external GDMA ACK are generated If these bits are 1111 the 16 cycles of the external ACK are generated 31 Busy status When GDMA starts this read only status bit is automatically set to 1 When it is 0 GDMA is idle This bit is a rea
204. 109 8 7 6 5 4 3 2 1 EXTMOD 6 0 External interrupt mode bits NOTE Each of the 7 bits in the external interrupt mode enable register EXTMOD corresponds to an external interrupt source When the source interrupt mode bit is set to 1 the interrupt is processed by the ARM940T core in FIQ fast interrupt mode Otherwise it is processed in IRQ mode normal interrupt The 7 external interrupt sources are mapped as follows 6 IOM2 interrupt 0 IRQ interrupt mode 1 FIQ interrupt mode 5 EXT 5 interrupt 4 EXT 4 interrupt 3 EXT 3 interrupt 2 EXT 2 interrupt 1 EXT 1 interrupt 0 EXT 0 interrupt Figure 16 2 External Interrupt Mode Register EXTMOD 16 4 2 INTERRUPT MASK REGISTERS The interrupt mask registers INTMASK and EXTMASK contain interrupt mask bits for each interrupt source Table 16 4 INTMASK EXTMASK Register INTMASK 0xF0140008 Internal Interrupt mask register OxFFFFFFFF EXTMASK OxF014000C External Interrupt mask register 0x8000007F ELECTRONICS 16 5 INTERRUPT CONTROLLER S3C2500B 31 30 29 28 27 26 25 24 23 22 21 2019 18 17 16 15 14 131211109 8 7 6 5 4 3 2 1 INTMASK 31 0 Individual internal interrupt mask bits NOTE Each of the 32 bits in the interrupt mask register INTMASK corresponds to an interrupt source When a source interrupt mask bit is 1 the interrupt is not serviced by the ARM940T when
205. 1C R W High Speed UART control character2 register 0x00 0xF008001C 31 24 23 16 15 8 7 0 CONCHAR7 CONCHAR6 5 7 0 Control Character 4 15 8 X Control Character 5 23 16 Control Character 6 31 24 Control Character 7 Figure 14 10 High Speed UART Control Character 2 Register ELECTRONICS 14 21 SERIAL I O HIGH SPEED UART S3C2500B 14 3 10 HIGH SPEED UART AUTOBAND BOUNDARY REGISTER This autoband boundary register limit range of each baud rate value that is auto detected ABBO is the lowest boundary value high baud rate and ABB3 is the highest value low baud rate of autobaud boundary register actually the highest boundary value is Refer figure 14 13 for detail range Figure 14 11 AutoBaud Boundary Regsiter Range Table 14 17 HUABB Registers HUABB 0 0070020 R W High Speed UART autobaud boundary register 0 1 0 0703 OxF0080020 31 24 23 16 15 8 7 0 ABB3 ABB2 ABB1 ABBO 7 0 AutoBaud Boundary 0 15 8 AutoBaud Boundary 1 23 16 AutoBaud Boundary 2 31 24 AutoBaud Boundary 3 Figure 14 12 High Speed UART AutoBaud Boundary Register 14 22 ELECTRONICS S3C2500B SERIAL HIGH SPEED UART 14 3 11 HIGH SPEED UART AUTOBAUD TABLE REGSITER This autobaud table register corrects each baud rate divisor value that is auto detected For detail refer figure 14 15 If high speed UART uses external UCLK 29 4912 MHz and you want to use 460800 baud rate thoug
206. 2 GPIO 63 HTXC2 HDLC ch 2 RXC HRXC2 GPIO 62 HRXC2 HDLC ch 2 nDCD HnDCD2 GPIO 61 HnDCD2 HDLC ch 2 nCTS HnCTS2 GPIO 60 HDLC ch 2 nRTS HnRTS2 GPIO 59 HDLC ch 2 nDTR HnDTR2 GPIO 58 HDLC ch 2 RXD HRXD2 GPIO 57 HDLC ch 2 TXD HTXD2 GPIO 56 HDLC ch 1 RXC HRXC1 GPIO 54 HRXC1 HDLC ch 1 nDCD HnDCD1 GPIO 53 HnDCD1 HDLC ch 1 nCTS HnCTS1 GPIO 52 HDLC ch 1 nRTS HnRTS1 GPIO 51 HDLC ch 1 nDTR HnDTR1 GPIO 50 HDLC ch 1 RXD HRXD1 GPIO 49 HDLC ch 0 TXC HTXCO GPIO 47 HTXCO HDLC ch 0 GPIO 46 HRXCO HDLC ch 0 nDCD HnDCDO GPIO 45 HnDCDO HDLC ch 0 nCTS HnCTS0 GPIO 44 HnCTSO HDLC ch 0 nRTS HnRTSO GPIO 43 HnRTSO HDLC ch 0 nDTR HnDTRO GPIO 42 HnDTRO High speed UART nDTR1 HUARTnDTR1 GPIO 37 High speed UART TXD1 HUARTTXD1 GPIO 36 High speed UART RXD1 HUARTRXD1 GPIO 35 High speed UART nDCDO HUARTnDCDO GPIO 34 High speed UART nCTSO HUARTnCTSO GPIO 33 HUARTnCTSO GPIO 32 HUARTnRTSO HTXCO 9 8 5 0 High speed UART nRTSO HUARTnRTSO Figure 15 3 Function Control Register 2 2 15 6 ELECTRONICS S3C2500B VO PORTS 15 3 3 PORT CONTROL REGISTER FOR IOPGDMA If the port is used for a function s port such as an external signal its signal function is determined by the IOPGDMA register IOPGDMA register is used to configure Reqg Ack signal ports provide
207. 2 14 2 4 ARM9TDMI Implementation 2 19 2 5 GPITS Register Map onse PIDE DI DU PIE HUE 2 21 2 6 ID Gode 2 21 2 7 Cache Type Register 2 22 2 8 GPIb5Rhediieri pU UNUM e 2 23 2 9 IGIOCKING our p ER pen RS 2 23 2 10 Cacheable Register 2 24 2 11 Write Buffer Control 2 25 2 12 Protection Space Register 2 26 2 13 Permission Encodihg t en en he epe RE eub ege kk e nana Mae SER 2 26 2 14 CP15 Data Protection Region 2 27 2 15 CP15 Instruction Protection Region Registers 2 27 2 16 CP15 Protection Region Register 2 28 2 17 Area 5176 Encoding 2 28 2 18 Cache Operations Writing to Register 7 2 29 2 19 CP15 Register 7 Index Segment Data 2 30 2 20 CP15 Register 7 Prefetch Address 2 30 2 21 Lockdown Register 2 31 2 22 CP S EE EE 2 32 List of Tables continued Table Title Page Number Number 3 1 The ARM Instruction 3 2 3 2 Condition Code
208. 20 19 16 15 12 11 8 7 4 3 0 Masters Index for HPRIF Field for HPRIR General DMA GDMA S Oo HPRIR 3 0 Ethernet Contoller 0 HPRIR 7 4 Ethernet Contoller 1 HPRIR 1 1 8 HDLC Controller 0 HPRIR 15 12 HDLC Controller 1 HPRIR 19 16 HDLC Controller 2 HPRIR 23 20 Figure 4 4 AHB Programmable Priority Registers ELECTRONICS S3C2500B SYSTEM CONFIGURATION 4 6 1 PROBLEM SOLVINGS WITH PROGRAMMABLE ROUND ROBIN S3C2500B has a stuff to think about with arbiter operation This only applies to arbiter with Round Robin priority Assuming all 0 s are set for HPRIR register for Round Robin HPRIR all same bus occupancy Round Robin and only three of six masters are used the problem arises as follows Channel Expected Bus Actual Real System Occupancy Running Block Bus Occupancy GVA 1 3 GDMA 1 6 2 Ethernet 1 3 Ethernet 1 6 Controller 0 Controller 0 3 Ethernet 1 3 Ethernet 1 6 Controller 1 Controller 1 x 8 O NtUed o GDM 1 6 5 0 GDMA 1 6 6 O0 0 GMA 16 When HPRIR is 0 0 only Ethernet controller 0 and 1 used the expected bus occupancy for each channel is 1 3 However S3C2500B does not work in that way instead GDMA gets 4 6 of the bus occupancy Ethernet controller O 1 6 and Ethernet controller 1 1 6 In short GDMA is run four times more than Ethernet controller O and 1 This is because S3C2500B is designed to turn the bus occu
209. 21 20 19 18 17 16 15 14 13 azm zoouc m rcmmma 12 Receive Event Time out E RxTO 0 A promised time is not elapsed during receiving 1 Valid data in a promised time NOTE A promised time is determined according to WL Word Length Promised time 4 WL 12 13 AutoBaud Rate Detection Done AUBDDN 0 Before AutoBaud Rate Detection 1 After AutoBaud Rate Detection 14 Data Set Ready DSR 0 DSR pin goes High 1 DSR pin goes Low 15 Clear To Send CTS 0 2 CTS pin goes High 1 CTS pin goes Low 16 CTS event occured E CTS 0 2 CTS pin has changed 12 CTS pin keep it s level 17 Transmitter Idle TI 0 Transmit is in progress 1 Transmitter is in idle no data for Tx 18 Transmit Holding Register Empty THE 0 TxFIFO at trigger level or tranmit holding register is not empty 1 TxFIFO mode TxFIFO at trigger level is empty In non FIFO mode transmit holding register is empty 19 Transmit FIFO Empty TFEMT 0 Transmit FIFO is not empty 1 Transmit FIFO is empty 20 Transmit FIFO full TFFUL 0 Transmit FIFO is not full 1 Transmit FIFO is full 31 21 Reserved Figure 14 3 High Speed UART Status Register Continued ELECTRONICS 14 13 SERIAL I O HIGH SPEED UART S3C2500B 14 3 3 HIGH SPEED UART INTERRUPT ENABLE REGISTER Table 14 7 HUCON Interrupt Enable Registers HUINT 0070008 R W High Speed UART Interrupt Enable register 0x00 008
210. 21 S3C2500B 032003 USER S MANUAL 53 2500 32 Bit RISC Microprocessor Revision 1 ELECTRONICS 53 2500 32 BIT RISC MICROPROCESSOR USER S MANUAL Revision 1 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3C2500B RISC Microprocessor User s Manual Revision 1 0 Publication Number 21 0 53 2500 052003 2003 Samsung Electronics Typical parameters can and do vary in different applications All operating paramet
211. 2400 17605 0 239968 001 76722 0 240000 4800 865361 0 479936 001 0 480000 9600 959873 001 1918F 0 960000 19200 21507 o 1924190 001 9652 0 1920000 Se400 10768 3848380 O22 o 3840000 57600 57725 69 O22 o 5760000 5200 3623 1154139 022 15F 0 11520000 000 13 16 ELECTRONICS S3C2500B SERIAL CONSOLE UART 13 3 8 UART CONTROL CHARACTER REGISTER 1 AND 2 These Control Character registers can be used for Software Flow control In Software Flow Control mode you should write control characters into these registers Any character in these registers can be used as a software control flow character and you can use maximum 8 characters for it Table 13 14 CUCHAR 1 2 Registers OxF0060018 Console UART control character register 1 0x00000000 CUCHAR2 OxF006001C RW Console UART control character register 2 0x00000000 31 24 23 16 15 8 7 0 CHAR3 CHAR2 CHAR1 CHARO 7 0 Control Character 0 15 8 X Control Character 1 23 16 Control Character 2 31 24 Control Character 3 Figure 13 10 Console UART Control Character 1 Register 31 24 23 16 15 8 7 0 7 CHAR6 5 7 0 Control Character 4 15 8 X Control Character 5 23 16 Control Character 6 31 24 Control Character 7 Figure 13 11 Console UART C
212. 2500B INSTRUCTION SET Examples STR STR LDR LDR LDREQB STR PLACE ELECTRONICS R1 R2 R4 R1 R2 R4 R1 R2 16 R1 R2 R3 LSL 2 R1 R6 5 R1 PLACE Store R1 at R2 R4 both of which are registers and write back address to R2 Store R1 at R2 and write back R2 R4 to R2 Load R1 from contents of R2 16 but don t write back Load from contents of R2 4 Conditionally load byte at R6 5 into R1 bits 0 to 7 filling bits 8 to 31 with zeros Generate PC relative offset to address PLACE 3 33 INSTRUCTION SET S3C2500B 3 10 HALFWORD AND SIGNED DATA TRANSFER LDRH STRH LDRSB LDRSH The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 16 These instructions are used to load or store half words of data and also load sign extended bytes or half words of data The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register The result of this calculation may be written back into the base register if auto indexing is required 28 27 25 24 23 22 21 20 19 16 15 12 11 876543 Lu Des Do De 3 0 Offset Register 6 5 S H 0 0 SWP instruction 0 1 Unsigned halfwords 1 1 Signed byte 1 1 Signed half words 15 12 Source Destination Register 19 16 Base Register 20 Load Store 0 Store to memory
213. 2500B GDMA CONTROLLER 12 4 4 DES MODE S3C2500B has only one DES Any channel of GDMA can transmit the data of DES If GDMA mode selection bit 100 or 101 GDMA gets ready to communicate with DES If GDMA mode is 100 DES IN mode and GDMA receives the request signal transmitted from DES GDMA transfers IN data of DES in memory into IN buffer FIFO of DES If GDMA mode is 101 DES OUT mode and GDMA receives the request signal transmitted from DES GDMA transfers OUT data of OUT buffer FIFO of DES into memory NOTE When GDMA is DES mode GDMA transmits two words by single request When GDMA is DES mode and four burst mode is enabled GDMA transmits four words by single request But DTCR register only has to be a multiple of 8 2 words because GDMA can transmit the last misaligned data At this time if GDMA count register is zero the operation is ended In DES mode you should set word 10 on transfer size TS 7 6 of DCON register In DES IN mode you don t need to care the destination address direction DD 11 10 of DCON register either the DDAR register In DES OUT mode you don t need to care the source address direction SD 9 8 of DCON register either the DSAR register 12 5 GDMA FUNCTION DESCRIPTION The following sections provide a functional description of the GDMA controller operations 12 5 1 GDMA TRANSFERS The GDMA transfers data directly between a requester and a target The requester and target can be memory HUA
214. 27 and store the result in R2 Setcondition codes on the result ELECTRONICS 3 67 INSTRUCTION SET S3C2500B 3 21 FORMAT 2 ADD SUBTRACT 15 14 13 11 10 12 9 8 6 5 3 2 0 i mote 2 0 Destination Register 5 3 Source Register 8 6 Register Immediate Value 9 Opcode 10 Immediate Flag 0 Register operand 1 Immediate oerand Figure 3 31 Format 2 3 21 1 OPERATION These instructions allow the contents of a Lo register or a 3 bit immediate value to be added to or subtracted from a Lo register The THUMB assembler syntax is shown in Table 3 9 NOTE All instructions in this group set the CPSR condition codes Table 3 9 Summary of Format 2 Instructions OP 1 THUMB Assembler ARMEquivalent Action ADD Rd Rs Rn ADDS Rd Rs Rn Add contents of Rn to contents of Rs Place result in Rd 1 ADD Rd Rs Offset3 ADDS Rd Rs Offset8 Add 3 bit immediate value to contents of Rs Place result in Rd 1 SUB Rd Rs Rn SUBS Rd Rs Subtract contents of Rn from contents of Rs Place result in Rd 1 1 SUB Rd Rs SUBS Rd Rs 4Offset3 Subtract 3 bit immediate value from contents of Rs Place result in Rd 3 68 ELECTRONICS S3C2500B INSTRUCTION SET 3 21 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 9 The instruction cycle times for the THUMB instruction are identical to
215. 3 tap filtering and you can select filtering on or off External signals can be active high or low so you must set the active high or low bits for the proper operation Table 15 4 IOPGDMA Register IOPGDMA 0 0030010 port special function register for 0x00000000 31 1211109 8 7 6 5 4 3 2 1 0 PDP px 11 Control external Acknowledge3 output for port 21 XGDMA Ack3 11 0 active low 1 active high 10 Control external Acknowledge2 output for port 20 xXGDMA Ack2 10 0 activelow 1 active high 9 Control external Acknowledgel1 output for port 19 Ack1 9 0 active low 1 active high 8 Control external Acknowledge0 output for port 18 8 0 active low 1 active high 7 6 Control external Request3 input for port 17 Req3 7 0 filtering off 1 filtering on 6 0 active low 1 active high 5 4 Control external Request2 input for port 16 xXGDMA Req2 5 0 filtering off 1 filtering on 4 0 active low 1 active high 3 2 Control external Request1 input for port 15 xXGDMA 3 0 filtering off 1 filtering on 2 0 active low 1 active high 1 0 Control external 510 input for port 14 Req0 1 0 filtering off 1 filtering on 0 0 active low 1 active high Figure 15 4 Port Control Re
216. 3C2500B INSTRUCTION SET 3 13 SOFTWARE INTERRUPT SWI The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 24 below 31 28 27 24 23 0 1111 Comment Field Ignored by Processor 31 28 Condition Field Figure 3 24 Software Interrupt Instruction The software interrupt instruction is used to enter supervisor mode in a controlled manner The instruction causes the software interrupt trap to be taken which effects the mode change The PC is then forced to a fixed value 0x08 and the CPSR is saved in SPSR_sve If the SWI vector address is suitably protected by external memory management hardware from modification by the user a fully protected operating system may be constructed 3 13 1 RETURN FROM THE SUPERVISOR The PC is saved in R14 svc upon entering the software interrupt trap with the PC adjusted to point to the word after the SWI instruction MOVS PC R14_svc will return to the calling program and restore the CPSR Note that the link mechanism is not re entrant so if the supervisor code wishes to use software interrupts within itself it must first save a copy of the return address and SPSR 3 13 2 COMMENT FIELD The bottom 24 bits of the instruction are ignored by the processor and may be used to communicate information to the supervisor code For instance the supervisor may look at this field and use it to index into an arra
217. 3C2500B RISC MICROCONTROLLER Table of Contents concluded Chapter 16Interrupt Controller 16 1 Overview ace eee SAME 16 1 MANERA Dc 16 1 16 3 Interrupt 16 2 16 4 Interrupt Controller Special 16 3 16 4 1 Interrupt Mode 16 3 16 4 2 Interrupt Mask 16 5 16 4 3 Interrupt Priority 16 8 16 4 4 Interrupt Offset 16 9 16 4 5 Interrupt by Priority Register 16 12 16 4 6 Interrupt Test Register 16 12 Chapter 1732 bit Timers ME AR 17 1 su AN 17 1 17 3 Interval Mode Operation a u asua Sa ua Asas 17 2 14 4 Toggle Mode Operation 17 2 17 5 Timer Operation Guidelines u 17 3 17 6 Timer Special FiGglster s datei nas 17 4 17 6 56 ana a amas 17 4 17 6 2 Timer Data
218. 40T macrocell are accessed via standard 5 pin JTAG port and are supported by ARM s Software Development Toolkit and Multi ICE interface hardware The EmbeddedlCE features allow software download and debug of the final production system with no cost overhead there is no monitor code or other use of target resident RAM or ROM The 940 processor has a Harvard cache architecture with separate 4KB instruction and 4KB data caches each with a 4 word line length A protection unit allows 8 regions of memory to be defined each with individual cache and write buffer configurations and access permissions The cache system is software configurable to provide highest average performance or to meet the needs of real time systems Software configurable options include e Random or round robin replacement algorithm e Write through or write back cache operation independently selectable for each memory region e Cache locking with granularity 1 64 th of cache size Overall the cache and write buffers improve CPU performance and minimize accesses to the AMBA bus and to any off chip memory thus reducing overall system power consumption The 940 includes support for coprocessors allowing a floating point unit or other application specific hardware acceleration to be added To minimize die size and power consumption the 940 does not provide virtual to physical address mapping as this is not required in most embedded applications Fo
219. 5 HI REGISTER OPERATIONS BRANCH EXCHANGE 15 14 13 12 11 10 9 8 7 6 5 3 2 0 ooo o Le mm 9 2 0 Destination Register 5 3 Source Register 6 Hi Operand Flag 2 7 Hi Operand Flag 1 9 8 Opcode Figure 3 34 Format 5 3 24 1 OPERATION There are four sets of instructions in this group The first three allow ADD CMP and MOV operations to be performed between Lo and Hi registers or a pair of Hi registers The fourth BX allows a Branch to be performed which may also be used to switch processor state The THUMB assembler syntax is shown in Table 3 12 NOTE In this group only CMP Op 01 sets the CPSR condition codes The action of 0 H2 0 for Op 00 ADD Op 01 CMP and Op 10 MOV is undefined and should not be used ELECTRONICS 3 73 INSTRUCTION SET S3C2500B Table 3 12 Summary of Format 5 Instructions LOP Hi H2 THUMB Assembler ARM Equivalent Action 1 ADD Rd Hs ADD Rd Rd Hs Add a register in the range 8 15 to a register in the range 0 7 ADD Hd Rs ADD Hd Hd Rs Add a register in the range 0 7 to a register in the range 8 15 ET ADD Hd Hs ADD Hd Hd Hs Add two registers in the range 8 15 1 CMP Rd Hs CMP Rd Hs Compare a register in the range 0 7 with a register in the range 8 15 Set the condition code flags on the result CMP Hd Rs CMP Hd Rs Compare a register in the range 8 15 with a register in the range 0 7 Set the condition code flags on the result 01
220. 5 3 2 Block Mode The assertion of only one request or an internal request causes all of the data as specified by the control register settings to be transmitted in a single operation The GDMA transfer is completed when the transfer counter value reaches zero The xGDMA signal can be de asserted after checking that xGDMA has been asserted xGDMA Req xGDMA Ack Figure 12 9 External GDMA Requests Block Mode 12 18 ELECTRONICS S3C2500B GDMA CONTROLLER 12 6 GDMA TRANSFER TIMING DATA Figure 12 10 provides the detailed timing data for GDMA data transfers that are triggered by external GDMA requests Please note that read write timing depends on which memory banks are selected The S3C2500B has the internal clock HCLK as the operating clock The clock frequency of HCLK is 133MHz Internal CIk HCLK xGDMA Req 1 1 1 1 tXDAr 1 p I xGDMA_Ack I Programmable by DCON 16 13 tXDRs 6 5 nsec delay rising 7 982 nsec 3 103 nsec tXDAf delay falling 8 002 nsec 2 703 nsec Figure 12 10 External GDMA Requests Detailed Timing ELECTRONICS 12 19 GDMA CONTROLLER S3C2500B 12 6 1 SINGLE AND ONE DATA BURST MODE DCON 3 1 001 4 0 5 0 xGDMA Req and xGDMA Ack signals are active high Recommand deasserted time xGDMA xGDMA Ack Address source dest data data NOTES 1 In this region operation is independent of the numbe
221. 6 32 MOV Ra Rb LSL n Multiplication by 24n 1 3 5 9 17 ADD Ra Ra Ra LSL n Multiplication by 2 n 1 3 7 15 RSB Ra Ra Ra LSL n ELECTRONICS INSTRUCTION SET Multiplication by 6 ADD MOV S3C2500B Ra Ra Ra LSL 1 Multiply by 3 Ra Ra LSL 1 and then by 2 Multiply by 10 and add in extra number ADD ADD Ra Ra Ra LSL 2 Multiply by 5 Ra Rc Ra LSL 1 Multiply by 2 and add in next digit General recursive method for Rb Ra C C a constant 1 If C even say C 2 n D D odd D 1 MOV Rb Ra LSL n Rb Rb Rb LSL n 2 If C MOD 4 1 say 24n D 1 D odd D 1 ADD ADD Rb Ra Ra LSL n Rb Ra D Rb Ra Rb LSL 3 If C MOD 4 3 say 2 n D 1 D odd n gt 1 D 1 RSB RSB Rb Ra Ra LSL n Rb Rb Ra Rb LSL n This is not quite optimal but close An example of its non optimality is multiply by 45 which is done by RSB RSB ADD rather than by ADD ADD 3 62 Rb Ra Ra LSL 2 Multiply by 3 Rb Ra Rb LSL 2 Multiply by 4 3 1 11 Rb Ra Rb LSL 2 Multiply by 4511 11 45 Rb Ra Ra LSL 3 Multiply by 9 Rb Rb Rb LSL 2 Multiply by 5 9 45 ELECTRONICS S3C2500B INSTRUCTION SET 3 18 4 LOADING A WORD FROM AN UNKNOWN ALIGNMENT BIC LDMIA AND MOVS MOVNE RSBNE ORRNE ELECTRONICS Rb Ra 3 Rb Rd Rc Rb Ra 3 Rb Rb LSL 3 Rd Rd LSR Rb Rb Rb 32 Rd Rd Rc LSL Rb Enter w
222. 7 is automatically set to 1 when the transmit holding register has no valid data to transmit and when the TX shift register is empty The reset value is 1 18 Transmit Holding When CUTXBUF is empty without regarding TX shift register this Register Empty THE bit set to 1 An interrupt is generated when CUSTAT 18 is 1 CUCON 1 0 is 91 and CUINT 18 is 1 You can clear this bit by writing some data into CUTXBUF 139 Reserved ELECTRONICS 13 9 SERIAL CONSOLE UART S3C2500B 19 18 17 16 12 11 10 0 Receive Data Valid RDV 0 No valid data Receive FIFO top or CURXBUF 1 Valid data present Receive FIFO top or CURXBUF 1 Break Signal Deteced BKD 0 No Break Signal Receive FIFO top or CURXBUF 1 Break received 2 Frame Error FER 0 No Frame Error Receive FIFO top or CURXBUF 1 Frame Error occured 3 Parity Error PER 0 No Frame Error Receive FIFO top or CURXBUF 1 Parity Error occured 4 Overrun Error OER 0 No Overrun Error Receive FIFO top or CURXBUF 1 Overrun Error occured 5 Control Character Detect CCD 0 No Control Character Receive FIFO top or CURXBUF 1 Control character present Receive FIFO top or CURXBUF 10 6 Reserved 11 Receiver in IDLE IDLE 0 Receiver is in active state 1 Receiver is in IDLE state 16 12 Reserved 17 Transmitter Idle TI 0 Transmit is in progress 1 Transmitter is in idle no data for Tx 18
223. 8 18 HSADR and HMASK Register NOTE Recognize one 32 bit address NOTE Recognize a single 8 bit address and the 32 bit broadcast address Figure 8 21 Address Recognition 8 48 ELECTRONICS S3C2500B HDLC CONTROLLER 31 24 23 16 15 8 7 0 First byte Second byte Third byte Fourth byte Station address byte register and MASK register 31 24 First address byte 23 16 Second address byte 15 8 Third address byte 7 0 Fourth address byte Figure 8 22 HDLC Station Address and HMASK Register 8 7 11 DMA TX BUFFER DESCRIPTOR POINTER REGISTER The DMA transmit buffer descriptor pointer register contains the address of the Tx buffer data pointer on the data to be sent During a DMA operation the buffer descriptor pointer is updated by the next buffer data pointer Table 8 19 DMA Tx Buffer Descriptor Pointer Registers 31 30 29 28 27 26 25 0 l MAT Butter Descriptor Pointer 25 0 DMA Tx buffer descriptor pointer Figure 8 23 DMA Tx Buffer Descriptor Pointer ELECTRONICS 8 49 HDLC CONTROLLER S3C2500B 8 7 12 DMA RX BUFFER DESCRIPTOR POINTER REGISTER The DMA receive buffer descriptor pointer register contains the address of the Rx buffer data pointer on the data to be received During a DMA operation the buffer descriptor pointer is updated by the next buffer data pointer Table 8 20 DMA Rx Buffer Descriptor Pointer Registers HDMARXPTRA 0 010003 DMA Rx Buffer Descriptor Pointer OxFFFFFFFF
224. 8 bit parallel data is always written to the shift register and read form the data buffer 12 data is always shifted in or out of the shift register 6 5 3 PRESCALER REGISTER IICPS The prescaler register for the 12C is described in Table 6 6 Table 6 5 IICPS Register Table 6 6 IICPS Register Description Prescaler value This prescaler value is used to generate the serial I2C clock The system clock is divided by 16 x prescaler value 1 3 to make the serial IC clock If the prescaler value is zero the system clock is when divided by 19 to make the serial 2 clock Therefore when 2 is used to 100kbit s in the standard mode the prescaler value must be changed 31 16 Not applicable ELECTRONICS 6 11 2 CONTROLLER S3C2500B 6 5 4 PRESCALER COUNTER REGISTER IICCNT prescaler counter register for the 2 is described in Table 6 8 Table 6 7 IICCNT Register Table 6 8 IICCNT Register Description Bit Number Description 15 0 Counter value This 16 bit value is the value of the prescaler counter It is read in test mode only to check the counter s current value 31 16 Not applicable 6 5 5 INTERRUPT PENDING REGISTER IICPND The 12C interrupt pending register for the 12 is described in Table 6 10 Table 6 9 IICPND Register IICPND OxFO0F0010 R W Interrupt pending register 0x00000000 Table 6 10 IICPND Register Description Bit Number Description 0 Interru
225. 90020 RW Key left half 0x00000000 Key 3 is the security key for the 3 DES of 3DES in the encryption mode or 1 DES of 3DES in the decryption mode DESKEY3R 0 0090024 Key 3 right 0x00000000 DESIVL OxF0090028 R W IV left half 0x00000000 is used for CBC mode only The IV for the next block is updated automatically DESIVR 0 009002 IV right half 0x00000000 DESINFIFO 0xF0090030 W DES 3DES input FIFO 0xXXXXXXXX This FIFO depth is 8 words DESOUTFIFO 0xF0090034 DES 3DES output FIFO 0xXXXXXXXX This FIFO depth is 8 words ELECTRONICS 11 3 DES 3DES S3C2500B 11 3 1 DES 3DES CONTROL REGISTER Table 11 2 DES 3DES Control Register Description 0 Run Enable 0 DES 3DES disable 1 DES 3DES enable This bit is the same register as the Run Enable bit of the Run Enable Register That is this bit has two writing address 0x00 and 0x0C 1 Indata DMA 0 CPU transfers the data to be encrypted from the external memory to the DESINFIFO of DES 3DES 1 transfers the data to be encrypted from the external memory to the DESINFIFO of DES 3DES 2 Outdata DMA 0 CPU transfers the encrypted data from the DESOUTFIFO of DES 3DES to the external memory 1 GDMA transfers the encrypted data from the DESOUTFIFO of DES 3DES to the external memor Right Left data 0 CPU write read from left half to right half data in DESINFIFO out DESOUTFIFO 1 CPU write read from right half to left half data in 1 DES SDES
226. A 0x00000000 MISSCNTA R CI W 0x00000000 PZCNTA LOxFOOBOD40 Pausecount 0500000000 RMPZCNTA 0xFO0BO044 R Remote pause count 7 0 00000000 CAMA OxF00B0080 W CAM content 32 words Undefined OxFOOBOOFC ELECTRONICS 1 33 PRODUCT OVERVIEW S3C2500B Table 1 8 S3C2500B Ethernet Controller 1 CAMB 0 0000080 w CAM content 32 words Undefined OxFOODOOFC 1 34 ELECTRONICS S3C2500B PRODUCT OVERVIEW Table 1 9 63 2500 HDLC Controller 0 HTxFIFOC 0 0100010 w HTxFIFO frame continue register Frame Continue HTxFIFOT 0 0100014 HTxFIFO frame terminate register Frame Terminate IHIXDONT oxroroooco Tx bufer descriptor countragiser HRXBDONT oxForo00ca ELECTRONICS 1 35 PRODUCT OVERVIEW S3C2500B Table 1 10 53 2500 HDLC Controller 1 HTxFIFOC 0 0110010 w HTxFIFO frame continue register Frame Continue HTxFIFOT 0 0110014 W HTxFIFO frame terminate register Frame Terminate 1 36 ELECTRONICS S3C2500B PRODUCT OVERVIEW Table 1 11 S3C2500B HDLC Controller 2 HTxFIFOC 0 0120010 W HTxFIFO frame continue register Frame Continue HTxFIFOT 0 0120014 W HTxFIFO frame terminate register Frame Terminate ELECTRONICS 1 37 PRODUCT OVERVIEW S3C2500B Table 1 12 S3C2500B 2 Controller 1 38 ELECTRONICS S3C2500B PRODUCT OVERVIEW Table 1 13 S3C2500B USB Controller USBFA 0 00 0000 USB function address
227. ADLC Status Heglstel sno PE IU D UE 8 40 HDLC Interrupt Enable 8 43 HDLC Tx FIFO Function 8 44 HDLC Rx FIFO Function 8 45 HDLC Time Constant 8 46 HDLC Preamble Constant 8 47 8 48 HDLC Station Address and HMASK 8 49 DMA Tx Buffer Descriptor 8 49 DMA Rx Buffer Descriptor Pointer 8 50 Maximum Frame Length 22022440000001 8 50 DMA Receive Buffer Size 8 51 HDLC Synchronization 8 51 Data Sampling 8 52 IOM2 Channel Structure in 9 2 Monitor Channel Handshake 9 4 Abortion of Monitor Channel Transmission 9 5 Structure of Last Byte of Channel 2 on 9 7 Structure of Last Byte of Channel 2 on 9 8 TSABlocleDIagralic sucer 7 9 9 IOM2 Control 9 13 OMA Status Heglster tenete ER exa ko E 9 15 2 Interrupt Enable
228. AM and Address Recognition The CAM compares the destination address of the received frame to stored addresses If it finds a match the receive state machine continues to receive the frame The CAM is organized to hold six byte address entries The CAM can store 21 address entries The CAM address entries 0 1 and 18 are used to send the pause control frame To send a pause control frame you must write the destination address to the source address to 1 and length type op code and operand to the CAM18 entry You must write the MAC transmit control register to set the send pause control bit In addition CAM19 and 20 can be used to construct a user define control frame 7 3 5 3 Parallel CRC Checker The receiver block computes a CRC across the data and the transmitted CRC and then checks that the resulting syndrome is valid A parallel CRC checking scheme handles data arriving in 4 bit nibbles at 100M bps To support full duplex operation the receiver and transmitter blocks have independent CRC circuits 7 3 5 4 Receive State Machine In MII mode the receiver block receives data from the MII on the RXD 3 0 lines This data is synchronized to RX CLK at 25 MHz or 2 5MHz In 7 wire mode and at 10MHz data is received on the RXD 10M line only After it detects the preamble and SFD the receive state machine arranges data in byte configurations generates parity and stores the result in the MRxFIFO one byte at a time If the
229. Add lmm to the current value of the program counter PC and load the result into Rd 1 ADD Rd SP lmm ADD Rd R13 Imm Add to the current value of the stack pointer SP and load the result into Rd NOTE The value specified by is a full 10 bit value but this must be word aligned ie with bits 1 0 set to 0 since the assembler places 1 gt gt 2 in field Word 8 Where the PC is used as the source register SP 0 bit 1 of the PC is always read as 0 The value of the PC will be 4 bytes greater than the address of the instruction before bit 1 is forced to 0 The CPSR condition codes are unaffected by these instructions ELECTRONICS 3 85 INSTRUCTION SET S3C2500B 3 31 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 19 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples ADD R2 PC 572 R2 PC 572 but don t set the condition codes bit 1 of PC is forced to zero Note that the THUMB opcode will contain 143 as the Word8 value ADD R6 SP 212 SP R13 212 but don t set the condition codes Note that the THUMB opcode will contain 53 as the Word 8 value 3 86 ELECTRONICS S3C2500B INSTRUCTION SET 3 32 FORMAT 13 ADD OFFSET TO STACK POINTER 15 14 13 11 10 6 0 12 9 8 7 oli lol olo o s 6 0 7 bit Immediate Value
230. B State Registers onto ARM State Registers 2 7 2 6 Program Status Register Format 2 8 2 7 ARMSOAOT Block 2 18 3 1 ARM Instruction Set 3 1 3 2 Branch and Exchange Instructions 3 5 3 3 socero EEUU UE e mE tU 3 7 3 4 Data Processing nnne 3 9 3 5 ARM Shit OperatlOns isch 3 12 3 6 Logical 3 12 3 7 Logical M 3 13 3 8 ArithmetieShife RIgDIE 3 13 3 9 Rotat 3 14 3 10 Rotate Right Extended ette EE 3 14 3 11 t epa 3 20 3 12 M ltiply In StE CtlOflS u rre peter pese e E Ra Rene Eua 3 23 3 13 Multiply Long 3 25 3 14 Single Data Transfer Instructions 3 28 3 15 Little Endian Offset 2 3 30 3 16 Half word and Signed Data Transfer with Register Offset 3 34 3 17 Half word and Signed Data Transfer with Immediate Offset and Auto Indexing 3 35 3 18 Block Data Transfer 58 3 40 3 19 Post Increment
231. CPSR SPSR abt 11011 Undefined R7 RO LR_und SP_und PC CPSR SPSR_und 11111 System R7 RO LR SP PC CPSR 14 0 CPSR R7 RO 14 fiq R8 fiq PC CPSR SPSR R12 RO R14 irq R13 PC CPSR SPSR irq R12 RO R14 svc R13 sve PC CPSR SPSR_svc R12 RO R14 abt R13 abt PC CPSR SPSR abt R12 RO R14 und R13 und PC CPSR R14 RO PC CPSR Reserved bits The remaining bits in the PSRs are reserved When changing a PSR s flag or control bits you must ensure that these unused bits are not altered Also your program should not rely on them containing specific values since in future processors they may read as one or zero ELECTRONICS S3C2500B PROGRAMMER S MODEL 2 9 EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted temporarily for example to service an interrupt from a peripheral Before an exception can be handled the current processor state must be preserved so that the original program can resume when the handler routine has finished It is possible for several exceptions to arise at the same time If this happens they are dealt with in a fixed order See Exception Priorities on page 2 15 2 9 1 ACTION ON ENTERING AN EXCEPTION When handling an exception the ARM9TDMI 1 Preserves the address of the next instruction in the appropriate Link Register If the exception has been entered from ARM state then the address of the next instru
232. CPUWRTCNT 15 7 Reserved 22 16 epo WRiTe CouNT WRTCNT 31 23 Reserved Figure 10 17 USBWCEPO Register 10 46 ELECTRONICS S3C2500B USB CONTROLLER 10 5 13 USB WRITE COUNT FOR ENDPOINT 1 REGISTER When OORDY is set for OUT endpoints USBWCEP1 21 16 maintains the byte count number of data in FIFO due to be unloaded by the MCU In case of IN mode MCU first writes the byte count number of data to be loaded into FIFO then write data into FIFO Table 10 27 USBWCEP1 Register USBWCEP1 0 00 0034 USB Write Count for Endpoint 1 Register 0x00000000 Table 10 28 USBWCEP1 Register Description CPU WRiTe R W the byte count number of data to be loaded into CouNT FIFO CPUWRTONT se P 21 16 WRiTe CouNT W the byte count number of data in FIFO due to be WRTCNT unloaded by the MCU Reserved ELECTRONICS 10 47 USB CONTROLLER S3C2500B 31 22 21 16 15 6 5 0 5 0 CPU WRiTe CouNT CPUWRTCNT 15 6 Reserved 21 16 ept WRiTe CouNT WRTCNT 31 22 Reserved Figure 10 18 USBWCEP1 Register 10 48 ELECTRONICS S3C2500B USB CONTROLLER 10 5 14 USB WRITE COUNT FOR ENDPOINT 2 REGISTER When OORDY is set for OUT endpoints USBWCEP2 21 16 maintains the byte count number of data in FIFO due to be unloaded by the MCU In case of IN mode MCU first writes the byte count number of data to be loaded into FIFO then write data into FIFO Table 10 29 USBWCEP2 Register USB
233. CTRONICS SYSTEM CONFIGURATION S3C2500B 4 8 EXTERNAL BUS MASTER The S3C2500 allows the external bus master to get the external memory bus and control the external memory system When the external bus master asserts XBMREQ to get the external memory bus the S3C2500 asserts XMBACK high and drives the state of the external memory bus to high impedance after S3C2500 finishes current transfer with memory When the external bus master takes the control of external memory bus it should take care of SDRAM refresh operation S3C2500 can get the control of the memory bus 1 cycle after XBMREQ is deactivated PXBMACK Figure 4 6 External Master Request Timing 4 14 ELECTRONICS S3C2500B SYSTEM CONFIGURATION 4 9 SYSTEM CONFIGURATION SPECIAL REGISTERS The System Configuration reigisters are as follows Table 4 5 System Configuration Registers Name Reset Value oxF0000000 Syster con gwraton regse ost ELECTRONICS 4 15 SYSTEM CONFIGURATION S3C2500B 4 9 1 SYSTEM CONFIGURATION REGISTER SYSCFG You can control the system bus arbitration method PLL operation system clock output enable disable function external memory address remap function and Little Big information read function by SYSCFG SYSCFG OxF0000000 System configuration register L o CPLLREN 31 CPLLCON register enable This bit controls which value is used for the C
234. CU writes a 1 to this register to issue a ISDSTALL STALL handshake to the USB The MCU clears this bit to end the STALL condition 29 In mode SenT This bit is valid only when endpoint 2 is set to IN STALL The USB sets this bit when a STALL handshake is ISTSTALL issued to an IN token due to the MCU setting SEND STALL bit When the USB issues a STALL handshake IINRDY is cleared 30 In mode CLear This bit is valid only when endpoint 2 is set to IN data TOGgle When the MCU writes a 1 to this bit the data toggle ICLTOG bit is cleared This is a write only register Reserved PP ELECTRONICS 10 33 USB CONTROLLER S3C2500B 29 28 27 26 25 24 23 22 N 15 14 13 12 11 10 9 8 gt 10 10 gt 109 0 rocrmm lt 7 gt rr oocoo rocrmmo rrcmmo 2 2 0 value 19 OUT Data ERRor ODERR 2 0 value x 8 max packet size 0 Normal operation 6 3 Reserved 1 Data error ISO 7 MAXP value SETting enable MAXPSET 2 OFFLUSH 0 MAXP value isn t changed 1 FIFO flush 1 MAXP value is changed iso miae IS 21 OUT SenD STALL OSDSTALL 0 No operation o Bulk ninteruptmode 1 Stall handshake transmit state 1 ISO mode 9 OUT AuTo CLeaR OATCLR 5222 STALL OSTSTALL 0 No operation _ 1 Auto clearing ORDY when FIFO data unloaded t Stall nandshha
235. DE 3 1 is HUART TX mode HUART from memory 010 or DES IN mode DES from memory 100 the DDAR register doesn t care Table 12 5 1 2 3 4 5 and DDARO0 1 2 3 4 5 Registers RW 31 0 Source Destination Address 31 0 Source destination address Figure 12 4 GDMA Source Destination Address Register 12 12 ELECTRONICS S3C2500B GDMA CONTROLLER 12 3 4 GDMA TRANSFER COUNT REGISTERS The transfer count register indicates the byte transfer rate which runs at 24 bit on channels 0 1 2 3 4 and 5 Whenever GDMA transfer count register transmits the data of GDMA it will be diminished by transfer width In other words when transfer size TS is byte it will be diminished at 1 in the case of half word at 2 and word at 4 If it is set in four data burst mode each value of transfer count will be diminished at 4 times But if the value of transfer count register is not a multiple of 4 times transfer size the last misaligned data can be transferred by one transfer size Table 12 6 1 2 3 4 5 Registers 31 24 23 0 Transfer Count 23 0 Transfer count Figure 12 5 GDMA Transfer Count Register ELECTRONICS 12 13 GDMA CONTROLLER S3C2500B 12 3 5 GDMA RUN ENABLE REGISTERS The GDMA run enable register DRER can enable or disable the RUN ENABLE bit DCON 0 of the GDMA control register DCON The DRER register is write only register Table 12 7 1 2 3 4 5
236. DMA owns the Buffer Descriptor and BDMA waits until Rx frame is received If the entire frame is received successfully the status bits in the receive buffer descriptor are set to indicate the received frame status The ownership bit in the buffer descriptor pointer is cleared by the CPU which has the ownership and an interrupt may now be generated After stores the states the BDMA fetches next Buffer Data Pointer and Owner bit of the next word If the Owner bit is O when BDMA checks the Owner of the Buffer Descriptor then it has two options Skip to the next buffer descriptor when DRxnSTSK DTxnSTSK bit is Owner Skip Generate an interrupt and halt the DMA operation when DRxSTSK DTxnSTSK bit is 0 Not Owner Stop You must set HBRXBDMAXCNT HBTXBDMAXONT register which shows the maximum buffer descriptor counts And if all buffer descirptors are used by the received frames or by the transmitted frames then first Rx Tx Buffer Descritptor is fetched by the BDMA As BDMA receives the data the software sets the maximum frame length register If the received data is longer than the value of the maximum frame length register this frame is ignored and the FLV bit is set The software also sets the DMA Rx buffer descriptor pointer to point to a chain of buffer descriptors all of which have their ownership bit The DMA controller can be started to set the DMA Rx enable bit in the control register When a frame is received it is moved
237. DPLL clock select Using this setting you can configure the clock source for DPLL to one of DPLLCLk the following pins TXC RXC MCLK2 BRGOUT1 or BRGOUT2 To select one of these pins set the DPLLCLK bits to 000 001 010 011 or 100 respectively 19 BRG clock select If this bit is 1 MCLK2 is selected as the source clock for the baud rate BRGCLK generator If this bit is 0 the external clock at the RXC pin is selected as the BRG source clock 22 20 Tx clock select TxCLK Using this setting you can configure the transmit clock source to one of the following pins TXC RXC DPLLOUTT BRGOUT1 or BRGOUT2 To select one of these pins set the TxCLK bits to 000 001 010 011 or 100 respectively 26 24 Rx clock select RxCLK Using this setting you can configure the receive clock source to one of the following pins TXC RXC DPLLOUTR BRGOUT1 or BRGOUT2 To select one of these pins set the RxCLK bits to 000 001 010 011 100 respectively 30 28 TXC output pin select If you do not use the clock at TXC pin as the input clock DPLLCLK TXCOPS TxCLK RxCLK must not 000 you can use the TXC pin to monitor TxCLK RxCLK BRGOUT1 BRGOUT2 DPLLOUTT and DPLLOUTR To select the clock you want to monitory set the TXCOPS to 000 001 010 011 or 100 101 respectively 81 Not applicable 8 28 ELECTRONICS S3C2500B 3130 282726 242322 201918
238. DUCT OVERVIEW S3C2500B Table 1 15 S3C2500B Controller Continued Table 1 16 S3C2500B Console UART Controller ICurxeur ooosococ W Console UART ransmitdataregister CURKBUF ooosooo Console UART receive data register Table 1 17 53 2500 High speed UART Controller 0 mustar RW High Speed UART status regster Humeur oeoorococ W High Speed UART wansmit data regster urxeur High Speed UART receive data register HUCHAR2 OxF007001C High Speed UART control character register 2 0x00000000 HUABB 0xF0070100 High Speed UART autobaud boundary register Ox1F0F0703 HUABT 0070104 High Speed UART autobaud table register 0x170B0502 HUCHAR 1 0070018 High Speed UART control character register 1 0x00000000 mE 1 42 ELECTRONICS S3C2500B PRODUCT OVERVIEW Table 1 18 S3C2500B High speed UART Controller 1 oeoosooo RW High Speed UART status regster Humeur W High Speed UART transmit data regster urxeur ooosooo High Speed UART receive data register Table 1 19 S3C2500B Port Controller IOPMODE1 OxF0030000 port mode select lower register for port 0 OxFOO3FFFF 31 IOPMODE2 OxF0030004 port mode select upper register for port 32 to OXFFFFFFFF 63 IOPCON1 OxF0030008 port function control register for port 0 to 31 OxOF
239. ECHO 0 Disable Tx auto echo mode 1 Enable Rx echo mode 21 Tx abort extension 0 At least eight consecutive 1 s are transmitted 1 At least 16 consecutive 1 s are transmitted 22 Tx abort 0 Normal 1 Enable at least eight consecutive 1 s are transmitted 23 Tx preamble TxPRMB 0 Transmit a mark idle is time fill bit pattern 1 Transmit the content of HPRMB 24 Tx data terminology ready TxDTR 0 nDTR goes high level 1 2 nDTR goes low level 25 Rx frame discontinue TxDISCON 0 Normal 1 Ignore the currently received frame 26 Tx CRC 0 Disable 1 CRC is not appended by hardware 27 Rx No CRC RXNOCR 0 Disable 1 Receiver does not check CRC by hardware CRC is treated as data in any case 28 Auto enable AutoEN 0 Normal operation Even if the nCTS or nDCD become high the transmitter can send tx data and the receiver can receive rx data 1 2 If the nDCD or nCTS become high the transmitter can not send tx data and the receiver can not receive rx data 29 Transparent Rx Stop TRxStop 0 Normal 1 Stop receive operation 30 Tx reverse TxREV 0 Normal 1 Send Tx data reversly 31 Rx reverse RXREV 0 Normal operation 1 Receive Rx data reversly Figure 8 14 HDLC Control Register HCON Continued ELECTRONICS 8 35 HDLC CONTROLLER S3C2500B 8 7 3 HDLC STATUS REGISTER HSTAT NOTE
240. ECTRONICS 5 25 MEMORY CONTROLLER 5 26 31 30 29 28 27 26 25 24 23 21 20 18 17 1514 2 0 Muxed bus address cycle for bank 0 TMAO 001 1 cycle 010 2 cycles 011 2 3 cycles 101 5 cycles 110 6 cycles 111 7 cycles 5 3 Muxed bus address cycle for bank 1 TMA1 001 1 cycle 010 2 cycles 011 2 3 cycles 101 5 cycles 110 6 cycles 111 7 cycles 8 6 Muxed bus address cycle for bank 2 TMA2 001 1 cycle 010 2 cycles 011 2 3 cycles 101 5 cycles 110 6 cycles 111 7 cycles 11 9 Muxed bus address cycle for bank 3 TMA3 001 1 cycle 010 2 cycles 011 2 3 cycles 101 5 cycles 110 6 cycles 111 7 cycles 14 12 Muxed bus address cycle for bank 4 4 001 1 cycle 010 2 cycles 011 2 3 cycles 101 5 cycles 110 6 cycles 111 7 cycles 17 15 Muxed bus address cycle for bank 5 5 001 1 cycle 010 2 cycles 011 cycles 101 5 cycles 110 6 cycles 111 7 cycles 20 18 Muxed bus address cycle for bank 6 TMA6 001 1 cycle 010 2 cycles 011 cycles 101 5 cycles 110 6 cycles 111 7 cycles 23 21 Muxed bus address cycle for bank 7 TMA7 001 1 cycle 010 2 cycles 011 2 3 cycles 101 5 cycles 110 6 cycles 111 7 cycles 24 Address Data muxed bus enable for bank 0 0 disable 1 enable 25 Address Data muxed bus enable for bank 1 0 disable 1 enable 26 Address Data muxed bus enable for bank 2 0 disable 1 enable 27 Address Data muxed bus e
241. EGISTERS Table 13 4 CUSTAT Registers Register RW Desnpion Size Reset Vane CUSTAT OxF0060004 Console UART status register 0x00060800 Table 13 5 Console UART Status Register Description Receive Data Valid This bit is automatically set to one when CURXBUF contains a valid RDV data received over the serial port The received data can be read from CURXBUF When this bit is 0 there is no valid data If you set CUCON 3 2 to 2501 and CUINT 0 to 1 b1 the interrupt is requested You can clear this bit by reading CURXBUF Break Signal Detected This bit is automatically set to one to indicate that a break signal BKD has been received in CURXBUF If the interrupt enable bit CUINT 1 is 1 a interrupt is generated when break occurs You have to clear this bit by writing 1 to this bit If not UART may be stopped during a serial data receiving operation A frame error occurs when a zero is detected instead of the stop bit s If the FER interrupt enable bit CUINT 2 is 1 a interrupt is generated when a frame error occurs You have to clear this bit by writing 1 to this bit If not UART may be stopped Parity Error PER This bit is automatically set to 1 whenever a parity error occurs during a serial data receiving operation If the PER interrupt enable bit CUINT 3 is 1 a interrupt is generated when a parity error OCCUIS You have to clear this bit by writing 1 to this
242. FFFFOO IOPCON2 0xF003000C port select function control register for port 0 00000000 32 to 63 IOPGDMA 0 0030010 port special function register for 0x00000000 0 0030014 port special function register for external 0x00000000 interrupt ELECTRONICS 1 43 PRODUCT OVERVIEW S3C2500B Table 1 20 S3C2500B Interrupt Controller INTTSTLO oxFor40046 R Low bits 6 0 bit merupttestregster ox00060000 1 44 ELECTRONICS S3C2500B PRODUCT OVERVIEW Table 1 21 S3C2500B Timer Controller wor ELECTRONICS 1 45 PRODUCT OVERVIEW S3C2500B NOTES 1 46 ELECTRONICS S3C2500B PROGRAMMER S MODEL PROGRAMMER S MODEL 2 1 OVERVIEW S3C2500B was developed using the advanced ARM9TDMI core designed by advanced RISC machines Ltd Processor Operating States From the programmer s point of view the ARM9TDMI can be in one of two states ARM state which executes 32 bit word aligned ARM instructions THUNB state which operates with 16 bit half word aligned THUMB instructions In this state the PC uses bit 1 to select between alternate half words NOTE Transition between these two states does not affect the processor mode or the contents of the registers 2 2 SWITCHING STATE 2 2 1 ENTERING THUMB STATE Entry into THUMB state can be achieved by executing a BX instruction with the state bit bit O set in the operand register Transition to THUMB state
243. FO Function Diagram 8 44 ELECTRONICS S3C2500B HDLC CONTROLLER 8 7 7 HDLC RX FIFO HRXFIFO The Rx FIFO consists of eight 32 bit registers that are used for the buffer storage of the data received Data bytes are always transferred from a full register to an adjacent empty register Each register has pointer bits that indicate the frame status When these pointers appear at the last 1 word or 4 word FIFO location they update the LAST bit indicating the last of a frame the OVERRUN bit the CRC error bit or Non octet aligned bit The HRXFIFO data available RxFA status bits indicate the current state of the HRXFIFO When the HRXFIFO data status bit is 1 the HRXFIFO is ready to be read The HRXFIFO data status is controlled by the 4 word or 1 word transfer selection bit Rx4WD When an overrun occurs the overrun frame of the HRXFIFO is no longer valid An in frame abort or a High level on nDCD input with the AutoEN bit in HCON is set to 1 the frame is cleared in the HRXFIFO The last byte of the previous frame which is separated by the frame boundary pointer is retained Data in HRXFIFO should be read by word size The HRXFIFO is cleared by the Rx reset bit set to 1 an abort signal received or nRESET RxFIFO Data Valid OV CRCE NO Figure 8 18 HDLC Rx FIFO Function Diagram ELECTRONICS 8 45 HDLC CONTROLLER S3C2500B 8 7 8 HDLC BRG TIME CONSTANT REGISTERS HBRGTC Table 8 15 HBRGTCA and HBRGTCB Register HBR
244. G test operations nTRST 1 phicu JTAG Not Reset Asynchronous reset of the JTAG logic This pin is internally connected pull up ELECTRONICS 1 17 PRODUCT OVERVIEW S3C2500B Table 1 1 S3C2500B Signal Descriptions Continue MDIO 0 Ethernet ControllerO 18 phob12 Management Data Clock The signal level at the MDC pin is used as a timing reference for data transfers that are controlled by the MDIO signal phbcut12 Management Data I O When a read command is being executed data that is clocked out of the PHY is presented on this pin When a write command is being executed data that is clocked out of the controller is presented on this pin for the Physical Layer Entity PHY TXDO 3 0 TXD_10M LOOP_10M phis Transmit Clock Transmit Clock for 10M The controller drives TXD 3 0 and EN from the rising edge of TX CLK In MII mode the PHY samples TXD 3 0 and TX EN on the rising edge of TX CLK For data transfers TXCLK 10M is provided by the 10M bit s PHY phob12 Transmit Data Transmit Data for 10M Transmit data is aligned on nibble boundaries 0 corresponds to the first bit to be transmitted on the physical medium which is the LSB of the first byte and the fifth bit of that byte during the next clock TXD 10M is shared with TXD 0 and is a data line for transmitting to the 10M bit s PHY LOOP 10M is shared with TXD 1 and is driven by the loop back bit in the control register 1 18 ELECTRONICS
245. GTCA 0xF010001C HDLC BRG Time Constant Register 0x00000000 HBRGTCB 0 011001 HDLC BRG Time Constant Register 0x00000000 HBRGTCC 0xF012001C HDLC BRG Time Constant Register 0x00000000 The HDLC BRG time constant register value can be changed at any time but the new value does not take effect until the next time the constant is loaded into the down counter No attempt is made to synchronize the loading of the time constant into while the clock is driving the down counter For this reason you should first disable the baud rate generator before loading the new time constant into the HBRGTC register The formula for determining the appropriate time constant for a given baud rate is shown below The desired rate is shown in bits per second This formula shows how the counter decrements from N down to zero plus one cycles for reloading the time constant This value is then fed to a toggle flip flop to generate the square wave output BRGOUT1 MCLK2 or RXC CNTO 1 16CNT1 BRGOUT2 BRGOUT1 1 or 16 or 32 according to CNT2 value of the HBRGTC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Tn 1 0 Time constant value for CNT2 00 divide by 1 01 adivide by 16 10 divide by 32 3 2 Time constant value for CNT1 00 divide by 1 divide by 16 15 4 Time constant value for CNT0 Figure 8 19 HDLC BRG Time Constant Register 8 46 ELECTRONICS S3C2500B HDLC CONTROLLER 8 7 9 HDLC PREAMBLE CO
246. HADDRd SDRAM Address Delay Time 22 50 LADDRh SDRAM Address Hold Time 22 49 SDRAM Data Input Output Mask Delay Time 20 49 iDQMh SDRAM Data Input Output Mask Hold Time 18 42 ps 18 6 ELECTRONICS S3C2500B MECHANICAL DATA MECHANICAL DATA 19 1 OVERVIEW The S3C2500B is available in a 272 pin BGA package 272 BGA 2727 AN ELECTRONICS 19 1 S3C2500B MECHANICAL DATA 27 00 0 10 0 10 24 00 A1 Corner 2727 010 0072 0r0 oO vc 72 BGA 2 a 0 75 MAX 99 0 96 0 S00 L Y ile 0 0 090 272 0 76 0 015 0 38 NJ OOOO OOOO 09000000090000000000 2 25r mcazzoaeorcouunoom A1 Corner 123 45 6 7 8 9 1011121314 1516 17 18 19 20 AN Package Dimensions BGA 2727 Figure 19 1 272 ELECTRONICS 19 2
247. HTXBDMAXCNT register up to 0x800 so you can use maximum 2048 2 buffer descriptors After HTXBDMAXONT Buffer Descriptor used the Tx Buffer Descriptor Address Pointer points the start address Table 8 27 HTXBDMAXCNTA HTXBDMAXCNTB and HTXBDMAXCNTC Register HTXBDMAXCNTA 0 01000 8 Tx buffer descriptor maximum count control register HTXBDMAXCNTB 0 01100 8 R W Tx buffer descriptor maximum count control register HTXBDMAXCNTC 0 01200 8 Tx buffer descriptor maximum count control 0xXXXXXFFF register 8 7 20 RX BUFFER DESCRIPTOR MAXIMUM COUNT REGISTER Rx Buffer Descriptor maximum count register sets rx buffer descriptor maximum counts For example if you set the HRXBDMAXONT register to then you can use 1 2 buffer descriptor If you set the HRXBDMAXONT register to OxFFE OxFFC OxFF8 OxFFO then you can use 2 21 4 22 8 23 16 24 32 25 buffer descriptor for each buffer descriptor maximum count register setting You can set the HRXBDMAXONT register up to 0x8002 so you can use maximum 2048 211 buffer descriptors After HRXBDMAXONT Buffer Descriptor used the Rx Buffer Descriptor Address Pointer points the start address Table 8 28 HRXBDMAXCNTA HRXBDMAXCNTB and HRXBDMAXCNTC Register HRXBDMAXCNTA 0xF01000CC R W Rx buffer descriptor maximum count control register HRXBDMAXCNTB 0xF01100CC R W Rx buff
248. I O Bank controller supports ROM SRAM and Flash memory SDRAM controller support SDRAM The S3C2500B Memory controller has the following functions e provide the required memory control signals for external memory accesses For example if a master block such as DMA controller or CPU generates an address that corresponds to a SDRAM bank the SDRAM controller generates the required SDRAM access signals e To provide the required signals for bus traffic between the S8C2500B and ROM SRAM and the external banks e To compensate for differences in bus width for data flowing between the external memory bus and the internal data bus e S3C2500B supports both little and big endians for external memory or I O devices ELECTRONICS 5 1 MEMORY CONTROLLER S3C2500B 5 2 FEATURES The following is a list of the Memory Controller s features e 10 banks 8 banks for ROM SRAM Flash Memory External I O interface 2 banks for SDRAM interface e 16M byte maximum address range per bank 24 bit external address pins e 32 bit internal and external data bus e Various timing control options NOTE By generating an external bus request an external device can access the S8C2500B s external memory interface pins In addition the 53 2500 can access slow external devices by using a WAIT signal The WAIT signal which is generated by the external device extends the duration of the CPU s memory access cycle beyond its programmable value
249. ICS This bit automatically set to one when Receive FIFO top or HURXBUF contains a valid data received over the serial port The received data can be read from Receive FIFO top or HURXBUF When this bit is 0 there is no valid data According to the current setting of the High Speed UART receive mode bits an interrupt or DMA request is generated when HUSTATT O0 is 1 In case of HUCON 3 2 01 and HUINT 0 1 interrupt requested and HUCON 3 2 10 or 11 request occurred You can clear this bit by reading Receive FIFO or HURXBUF NOTE Whether Receive FIFO top or HURXBUF depends on the 7 This bit automatically set to one to indicate that a break signal has been received in Receive FIFO top or HURXBUF If the BKD interrupt enable bit HUINT 1 is 1 a interrupt is generated when break occurs You have to clear this bit by writing 1 to this bit If not UART may be stopped This bit automatically set to 1 whenever a frame error occurs during a serial data receiving operation A frame error occurs when a zero is detected instead of the stop bit s If the FER interrupt enable bit HUINT 2 is 1 a interrupt is generated when a frame error occurs You have to clear this bit by writing 1 to this bit If not UART may be stopped This bit automatically set to 1 whenever a parity error occurs during a serial data receiving operation If the PER interrupt enable bit HUINT 3 is 1 a interrup
250. ID Code Register 31 12 Implementor 0x41 identifies ARM 23 16 Architecture version 0x2 0x940 od ELECTRONICS 2 21 PROGRAMMER S MODEL S3C2500B 2 16 1 2 Register 0 Cache type This is a read only register which allows operating systems to establish how to perform operations such as cache cleaning and lockdown Future ARM cached processors will contain this register allowing RTOS vendors to produce future proof versions of their operating systems The cache type register is accessed by reading CP15 register with the opcode 2 field set to 1 For example MRC p15 0 rd cO c0 1 returns Cache type register The register contains information about the size and architecture of the caches The format of the register is shown in Table 2 7 Table 2 7 Cache Type Register Format Memng ma 2 22 ELECTRONICS S3C2500B PROGRAMMER S MODEL 2 16 1 3 Register 1 Control register This contains the global control bits of the ARM940T All reserved bits should either be written with zero or one as indicated or written using read modify write The reserved bits have an unpredictable value when read All defined bits in the control register are set to zero at reset Table 2 8 CP15 Register 1 RegisterBits Functions Asynchronous clocking select iA nFastBus select nF Reserved should be zero Alternate vectors select V ICache enable bit 1 Reserved should be z
251. INSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instruction Table 3 26 The BL Instruction THUMB Assembler Equivalent EN BL label LR PC OffsetHigh 12 temp next instruction address PC LR OffsetLow lt lt 1 LR temp 1 Examples BL faraway Unconditionally Branch to next 2 and place following instruction address ie next in R14 the Link register and set bit 0 of LR high Note that the THUMB opcodes will contain the number of half words to offset faraway Must be Half word aligned 3 96 ELECTRONICS S3C2500B INSTRUCTION SET 3 39 INSTRUCTION SET EXAMPLES The following examples show ways in which the THUMB instructions may be used to generate small and efficient code Each example also shows the ARM equivalent so these may be compared 3 39 1 MULTIPLICATION BY A CONSTANT USING SHIFTS AND ADDS The following shows code to multiply by various constants using 1 2 or 3 Thumb instructions alongside the ARM equivalents For other constants it is generally better to use the built in MUL instruction rather than using a sequence of 4 or more instructions Thumb ARM 1 Multiplication by 2 n 1 2 4 8 LSL Ra Rb LSL n MOV Ra Rb LSL n 2 Multiplication by 24n 1 3 5 9 17 LSL Rt Rb zin ADD Ra Rb Rb LSL n ADD Ra Rt Rb 3 Multiplication by 2 n 1 3 7 15 LSL Rt Rb zin
252. INTPND Register IOPEXTINTPND OxF0030018 port external interrupt clear register 0x00000000 31 6 5 4 3 2 1 0 oeexmwTeND es NOTE IOPEXTINTPND is set when external interrupt is generated and is cleared by writing 1 to the appropriate bit of IOPEXTINTPND register 5 EXTINTCLR5 4 EXTINTCLR4 3 EXTINTCLR3 2 EXTINTCLR2 1 EXTINTCLR1 0 EXTINTCLRO Figure 15 6 I O Port External Interrupt Clear Register IOPEXTINTPND 15 10 ELECTRONICS S3C2500B VO PORTS 15 3 6 I O PORT DATA REGISTER 2 The I O port data registers IOPDATA1 2 contain one bit read values for ports that are configured to input mode and one bit write values for ports that are configured to output mode Table 15 7 IOPDATA1 2 Register IOPDATA1 OxF003001C port data register for port 0 to 31 Undefined IOPDATA2 0 0030020 port data register for port 32 to 63 Undefined 15 3 7 PORT DRIVE CONTROL REGISTER 2 The I O port drive control registers IOPDRV 1 2 control the pad type for which is operating as a tri state output mode or an open drain output mode This register s each bit value programmed as write 1 value for open drain output mode or write 0 value for tri state output mode Table 15 8 IOPDRV1 2 Register OxF0030024 port drive control register for port 0 to 31 0x00000000 IOPDRV2 OxF0030028 port drive control register for port 32 to 63
253. ION 4 HIGH Specifies the physical address of the external device 2 32 2 Specifies data bus access size for the Bank 0 Specifies read write state from S3C2500B When S3C2500B read from ext I O device nOE s value is nRCS Specifies which ext device is selected nEWAIT nREADY Signal be controlled from ext I O slow device to delay cycles in data read and write CKE sos tow data width and SDRAM NOTES 1 O Output from the S3C2500B 2 Input to the S3C2500B 3 B Bi direction 1 1 1 PINS 32 1 ELECTRONICS 5 5 MEMORY CONTROLLER ADDR 23 0 DATA 31 0 BOSIZE 1 0 nRCS 7 0 nEWAIT nREADY XBMACK XBMREQ 3C2500B nSDWE nWE16 nWBE nBE DQN 3 0 nOE HCLKO CKE nSDCS 1 0 nSDRAS nSDCAS S3C2500B Address amp Data Adjust with pin selection ROM amp SRAM Interface signals External device interface signals ROM SRAM Flash and SDRAM common signals SDRAM Interface signals Figure 5 2 Memory Controller Bus Signals 5 6 ELECTRONICS S3C2500B MEMORY CONTROLLER 5 5 ENDIAN MODES S3C2500B supports both little endian and big endian for external memory or I O devices by setting the pin BIG Below tables 5 3 through 5 14 are show the program data path between the CPU register and the external memory using little big endian and word half word byte access Table 5 3 and 5 4 Using big endian and word acces
254. ITD1 IOM2 1 Channel Transmit Data Register 9 21 9 12 IOM2CIRD1 IOM2 1 Channel Receive Data Register 9 21 9 13 IOM2MTD 2 Monitor Channel Transmit Data Register 9 22 9 14 IOM2MRD 2 Monitor Channel Receive Data Register 9 22 9 15 TSAACON TSA A Control 9 23 9 16 TSABCON TSA B Control 9 24 9 17 TSACCON TSA Control 0004 0 0 9 25 9 18 IOM2STRB Strobe 9 26 10 1 USB 10 9 10 2 10 10 10 3 USBFA Register 10 10 10 4 USBPM Iv ERR Fete Feu Ren 10 12 10 5 USBPM Register 10 12 10 6 USBINTR BOOISIOE 10 14 10 7 USBINTR Register Description 10 15 10 8 USBINTRE e 10 17 10 9 USBINTRE Register 10 17 10 10 USBEN REGIST Em 10 19 10 11 USBFN Register 10 19 10 12 CNT VEE Table 10 20 10 13 USBDISCONN
255. LECTRONICS 10 55 USB CONTROLLER S3C2500B EPO FIFO 31 0 EndPoint 0 data FIFO EP1 FIFO 31 0 EndPoint 1 data FIFO EP2 FIFO 31 0 EndPoint 2 data FIFO FIFO 31 0 EndPoint 3 data FIFO FIFO 31 0 EndPoint 4 data FIFO Figure 10 22 05 0 1 2 3 4 FIFO Registers 10 56 ELECTRONICS S3C2500B DES 3DES DES 3DES 11 1 OVERVIEW The Data Encryption Standard DES consists of the Data Encryption Algorithm DES and Triple Data Encryption Algorithm TDEA as described in ANSI 9 52 The DES SDES accelerator of the 53 2500 is designed in such a way that they may be used in a computer system or network to provide cryptographic protection to binary coded data FIPS PUB 81 DES Modes of operation describes four different modes for using DES described in this standard Those are ECB electronic codebook CBC cipher block chaining CFB cipher feedback and OFB output feedback But the 53 2500 two modes are supported ECB and CBC The X9 52 standard Triple Data Encryption Algorithm Modes of Operation describes seven different modes for using TDEA Those are TECB TDEA electronic codebook mode of operation TCBC TDEA cipher block chaining mode of operation TDEA cipher block chaining mode of operation interleaved TCFB TDEA cipher feedback mode of operation TCFB P TDEA cipher feedback mode of operation pipelined TOFB TDEA output feedback mode of operation an
256. LLER S3C2500B nSDRAS nSDCAS o 2 o lt z o a Figure 5 32 Burst Write Operation 5 59 ELECTRONICS MEMORY CONTROLLER S3C2500B NOTES 5 60 ELECTRONICS S3C2500B 2 CONTROLLER 2 CONTROLLER 6 1 OVERVIEW The S3C2500B has internal 2 controller It requires only two bus lines a serial data line SDA and a serial clock lines SCL When the 2 is free both lines are high level It is connected to the same I C And the number of IC is limited only by the maximum bus capacitance of 400 pF 6 2 FEATURES e Supports only single master mode e Supports 8 bit bi directional serial data transfers e Supports 7 bit addressing Figure 6 1 shows a block diagram of the S3C2500B controller Data Shift buffer register IICBUF ial Serial Clock c System clock fsvscLk Line Control Prescaler Prescaler register IICPS RESET BUSY COND1 CONDO LRB Control status register IICCON Figure 6 1 2 Block Diagram ELECTRONICS 6 1 2 CONTROLLER S3C2500B 6 3 FUNCTIONAL DESCRIPTION The S3C2500B controller is the master of the serial Using a prescaler register the user can program the serial clock frequency that is supplied to the controller The serial clock frequency is calculated as follows Serial clock frequency 16 x prescaler register value 1 3 where is the system clock freq
257. LUSH 0 No operation 1 FIFO flush 28 IN SenD STALL ISDSTALL 0 No operation 1 Stall handshake transmit state 29 IN SenT STALL ISTSTALL 0 No operation 1 Stall handshake transmitted 30 IN CLear TOGgle ICLTOG 0 No operation 1 Data toggle flag set to 0 31 Reserved Figure 10 15 USBEP3CSR Register ELECTRONICS 10 39 USB CONTROLLER S3C2500B 10 5 11 USB ENDPOINT 4 COMMON STATUS REGISTER This register includes the control bits status bits IN OUT status information and max packet size value for endpoint 4 Table 10 23 USBEPACSR Register USBEP4CSR 028 USB Endpoint 4 Common Status Register 0x00000401 Table 10 24 USBEPACSR Register Description 3 0 size value If MAXP 3 0 is 0000 then MAXPsize is 0 byte If MAXP 3 0 is 0001 then MAXPsize is 8 bytes If MAXP 3 0 is 0010 then MAXPsize is 16 bytes If MAXP 3 0 is 0011 then MAXPsize is 24 bytes If MAXP 3 0 is 0100 then MAXPsize is 32 bytes If MAXP 3 0 is 0101 then MAXPsize is 40 bytes If MAXP 3 0 is 0110 then MAXPsize is 48 bytes If MAXP 3 0 is 0111 then MAXPsize is 56 bytes If MAXP 3 0 is 1000 then MAXPsize is 64 bytes 6 4 7 size 0 USBEPACSR 3 0 isn t overwritten when MCU SETtable writes a 32bit value to USBEP4CSR register MAXPSET 1 USBEPACSR 3 0 is overwritten 8 Out mode ISO This bit is valid only when endpoint 4 is set to OUT mode OISO 0 Endpoint 1 wil
258. M devices The controller supports a subset of these commands Table 5 23 SDRAM Commands Mode Register Set MRS Refresh x Self refresh H Rowadvae H L H X ACT Read with auto H precharge without auto precharge Write with auto H precharge without auto precharge H t r Precharge H NOTE Shaded boxes indicate commands not supported by SDRAM controller They are included for completeness X Don t care V Valid value or L A10 AP ADDR 10 Auto Pre charge 5 44 ELECTRONICS S3C2500B MEMORY CONTROLLER 5 7 5 EXTERNAL DATA BUS WIDTH The SDRAM controller supports not only 32 bit data bus but also 16 bit data bus External data bus width can be selected by the XW field of CFGREG 5 7 6 MERGING WRITE BUFFER A merging write buffer compacts the writes of all widths into quad word which can be efficiently transferred to the SDRAM The merging write buffer improves the data bandwidth of write operation The merging write buffer is comprised of write buffer 0 and write buffer 1 Each write buffer holds a quad word which is the size of the default SDRAM data burst length Two write buffer configuration allows a new quad word to be buffered while the contents of the other quad word buffer are transferred to memory These write buffers can also merge non contiguous writes to the same quad word address The conditions of the write buffer fl
259. MCU writes a 1 to this bit to clear SETEND end SVSET ELECTRONICS 10 23 USB CONTROLLER S3C2500B 27 26 25 24 23 lt lt 0 2 3 0 value 3 0 value x 8 max packet size 6 4 Reserved 7 MAXP value SETting enable MAXPSET 0 value isn t changed 1 value is changed 8 23 Reserved 24 Out packet ReaDY ORDY 0 Not received packet or in IN mode 1 Received packet from host 25 IN packet ReaDY INRDY 0 Not yet loaded packet to EPO FIFO or in OUT mode 1 Loading packet to EPO FIFO completed 26 SenT STALL STSTALL 0 stall token is transmitted 1 Control transaction is ended due to a protocol violation 27 Data END DEND 0 Not dataend stage 1 Dataend stage 28 SETup END SETEND 0 Normal operation state 1 Setup end stage 29 SenD STALL SDSTALL 0 Normal operation state 1 Go to stall token transmt state 30 SerViced Out ReaDY SVORDY 0 No operation 1 ORDY bit clear 31 SerViced SETup end SVSET 0 No operation 1 SETEND bit clear Figure 10 12 USBEPOCSR Register 10 24 ELECTRONICS S3C2500B USB CONTROLLER 10 5 8 USB ENDPOINT 1 COMMON STATUS REGISTER This register includes the control bits status bits IN OUT status information and max packet size value for endpoint 1 Table 10 17 USBEP1CSR Register USBEP1CSR OxF00E001C USB Endpoint 1 Common Status Register 0x0000040
260. MODEL 2 10 1 EXCEPTION PRIORITIES When multiple exceptions arise at the same time a fixed priority system determines the order in which they are handled Highest priority Reset Data abort FIQ IRQ Prefetch abort ON gt Lowest priority 6 Undefined Instruction Software interrupt 2 10 2 NOT ALL EXCEPTIONS CAN OCCUR AT ONCE Undefined Instruction and Software Interrupt are mutually exclusive since they each correspond to particular non overlapping decoding of the current instruction If a data abort occurs at the same time as a FIQ and FIQs are enabled ie the CPSR s F flag is clear ARM9TDMI enters the data abort handler and then immediately proceeds to the FIQ vector A normal return from FIQ will cause the data abort handler to resume execution Placing data abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection The time for this exception entry should be added to worst case FIQ latency calculations ELECTRONICS 2 15 PROGRAMMER S MODEL S3C2500B 2 11 INTERRUPT LATENCIES The worst case latency for FIQ assuming that it is enabled consists of the longest time the request can take to pass through the synchroniser Tsyncmax if asynchronous plus the time for the longest instruction to complete Tldm the longest instruction is an LDM which loads all the registers including the PC plus the time for the data abort entry Texc plus the time for FIQ en
261. MSR transfer register contents to PSR MSR cond lt psr gt Rm transfer register contents to PSR flag bits only MSR cond lt psrf gt Rm The most significant four bits of the register contents are written to the N Z C amp V flags respectively MSR transfer immediate value to PSR flag bits only lt psrf gt expression The expression should symbolise a 32 bit value of which the most significant four bits are written to the N Z C and V flags respectively Key Two character condition mnemonic See Table 3 2 Rd and Rm Expressions evaluating to a register number other than R15 psr CPSR CPSR all SPSR or SPSR all CPSR and CPSR all are synonyms as are SPSR and SPSR all lt psrf gt CPSR flg or SPSR flg lt expression gt Where this is used the assembler will attempt to generate a shifted immediate 8 bit field to match the expression If this is impossible it will give an error Examples In User mode the instructions behave as follows MSR CPSR_all Rm CPSR 31 28 lt Rm 31 28 MSR CPSR flg Rm CPSR 31 28 lt Rm 31 28 MSR CPSR_flg 0xA0000000 CPSR 81 28 lt set C clear Z V MRS Rd CPSR 31 0 lt 1 0 In privileged modes the instructions behave as follows MSR CPSR all Rm CPSR 31 0 lt Rm 31 0 MSR CPSR flg Rm CPSR 31 28 lt Rm 31 28 MSR CPSR_flg 0x50000000 CPSR 31 28 lt 0x5 set Z V clear C MSR S
262. N down PHY PLL PHY FREQ or PPLLCON 48MHz USB Clock Divider PHY CLKSEL XCLK PHY CLKO NOTES 1 CPUPLL block can generate eight clock frequencies between 166MHz and 33MHz according to the CPU FREQ 2 0 pins out of the 10MHz XCLK input clock frequency USB PLL block can generate only 48MHz clock frequency out of the 10MHz USB XCLK input clock frequency If CLKSEL or USB CLKSEL is 1 the CPU PLL BUS PLL or USB PLL go into the state of power down Three pins of CPU FREQ 2 0 can control the multiplication factor of the CPU PLL block The PHY FREQ pin controls the frequency of the PHY PLL The system configuration register CLKCON 15 0 can divide the ARMO clock and the system clock If all bits are 0 non divided clock is used Only one bit can be set in CLKCON 15 0 That is the clock dividing value is defined as 1 2 4 8 16 The internal clock is PLL output clock between 166 2 and 33MHz CLKCON 1 CLKCON 15 0 register CLKMOD 1 0 pins FREQ 2 0 pins can control the AMBA clock divider CLKMOD 1 0 pins and BUS FREQ 2 0 pins can generate the various AMBA bus clock frequecies referring to the Table 3 The CLKCON 15 0 register can divide the various AMBA clock frequecies of the Table 4 3 All PLL can be controlled by either pin setting or register setting Figure 4 5 Shows the Clock Generation Logic of the S3C2500B ELE
263. NRZI data to toggle each bit time A string of ones causes long periods with no transitions in the data In order to ensure adequate signal transitions the transmitting device employs bit stuffing when sending a packet on USB A zero is inserted after every six consecutive ones in the data stream before the data is NRZI encoded to force a transition in the NRZI data stream This gives the receiver logic a data transition at least once every seven bit times to guarantee the data and clock lock Bit stuffing is enabled beginning with the Sync Pattern and throughout the entire transmission The data one that ends the Sync Pattern is counted as the first one in a sequence Bit stuffing by the transmitter is always enforced without exception If required by the bit stuffing rules a zero bit will be inserted even if it is the last bit before the end of packet EOP signal 10 3 5 BULK TRANSACTIONS The bulk transfer type is designed to support devices that need to communicate relatively large amounts of data at highly variable times where the transfer can use any available bandwidth Requesting a pipe with a bulk transfer type provides the requester with the following Access to the USB a bandwidth available basis Retry of transfers in the case of occasional delivery failure due to errors on the bus Guaranteed delivery of data but no guarantee of bandwidth or latency Bulk transfers occur only on a bandwidth available basis For a
264. NSTANT REGISTER HPRMB The HPRMB register is used to meet the DPLL requirements for phase locking The preamble pattern is transmitted as many Tx preamble length bit values in HMODE 10 8 when the Tx preamble bit TxPRMB is 1 and then the Tx preamble bit is cleared automatically The opening flag follows this preamble pattern and the data will be transmitted Table 8 16 HPRMBA and HPRMBB Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 1 0 Preamble pattern Figure 8 20 HDLC Preamble Constant Register The reference for the preamble pattern of each data mode is as follows Table 8 17 Preamble Reference Pattern ELECTRONICS 8 47 HDLC CONTROLLER S3C2500B 8 7 10 HDLC STATION ADDRESS REGISTERS HSADRO 3 AND HMASK REGISTER Each HDLC controller has five 32 bit registers for address recognition four station address registers and one mask register Generally the HDLC controller reads the address of the frame from the receiver to check it against the four station address values and then masks the result with the user defined HMASK register A 1 in the HMASK register represents a bit position for which an address comparison should occur A 0 represents a masked bit position If you check the address up to four bytes the HMASK register value should be Dependent on the HMASK register value the frame s address is compared If the address is not matched this frame is discarded Table
265. NT 31 23 Reserved Figure 10 20 USBWCEP3 Register 10 52 ELECTRONICS S3C2500B USB CONTROLLER 10 5 16 USB WRITE COUNT FOR ENDPOINT 4 REGISTER When OORDY is set for OUT endpoints USBWCEP4 22 16 maintains the byte count number of data in FIFO due to be unloaded by the MCU In case of IN mode MCU first writes the byte count number of data to be loaded into FIFO then write data into FIFO Table 10 33 USBWCEP4 Register USBWCEP4 0 0 0040 USB Write Count for Endpoint 4 Register 0x00000000 Table 10 34 USBWCEP4 Register Description CPU WRiTe R W the byte count number of data to be loaded into FIFO CouNT CPUWRTONT 7 22 16 WRiTe CouNT W the byte count number of data in FIFO due to be WRTCNT unloaded by the MCU ELECTRONICS 10 53 USB CONTROLLER S3C2500B 31 23 22 16 15 7 6 0 6 0 epa CPU WRiTe CouNT CPUWRTCNT 15 7 Reserved 22 16 ep4 WRiTe CouNT WRTCNT 31 23 Reserved Figure 10 21 USBWCEP4 Register 10 54 ELECTRONICS S3C2500B USB CONTROLLER 10 5 17 USB ENDPOINT 0 1 2 3 4 FIFO REGISTER Each endpoint has his own FIFO To access to each FIFO data User must use these registers Table 10 35 USBEPO 1 2 3 4 Descriptions USBEPO OxFOOE0080 USB EPO FIFO OxXXXXXXXX USBEP1 OxFOOE0084 USB EP1 FIFO OxXXXXXXXX USBEP2 OxFOOE0088 USB EP2 FIFO OxXXXXXXXX USBEP3 OxFOOE008C USB EP3 FIFO OxXXXXXXXX USBEP4 0 00 0090 USB FIFO OxXXXXXXXX E
266. OM2 Interrupt Enable 9 16 9 5 4 IOM2 TIC Bus Address 9 18 9 5 5 IOM2 IC Channel Transmit Data 2 22 00 9 19 9 5 6 IOM2 Channel Transmit Data 9 20 9 5 7 IOM2 1 Channel Transmit Data 9 21 9 5 8 IOM2 1 Channel Receive Data 9 21 9 5 9 IOM2 Monitor Channel Transmit Data 9 22 9 5 10 IOM2 Monitor Channel Receive Data 9 22 9 5 11 TSA A Control 9 23 9 5 12 TSA B Control 9 24 9 5 13 TSA C Control Register 9 25 9 5 14 IOM2STRB Strobe 9 26 S3C2500B RISC MICROCONTROLLER Table of Contents Continued Chapter 10USB Controller xii TOZT2OVOLVIOWE ea ea chee oce T D 10 1 10 2 9 re FPES ccr 10 2 10 3 Function rnnt rn 10 3 10 3 1 USB Bus Topology and Physical 10 3 10 3 2 Frame 10 3 10 3 3 Packet
267. ON These instructions load optionally sign extended bytes or half words and store half words The THUMB assembler syntax is shown below Table 3 15 Summary of format 8 instructions B THUMB Assembler Equivalent Rd Rb Ro STRH Rd Rb Ro Store half word Add Ro to base address in Rb Store bits 0 15 of Rd at the resulting address LDRH Rd Rb Ro LDRH Rd Rb Ro Load half word Add Ro to base address in Rb Load bits 0 15 of Rd from the resulting address and set bits 16 31 of Rd to 0 LDSB Rd Rb Ro LDRSB Rb Ro Load sign extended byte Add Ro to base address in Rb Load bits 0 7 of Rd from the resulting address and set bits 8 31 of Rd to bit 7 LDSH Rd Rb Ro LDRSH Rd Rb Ro Load sign extended half word Add Ro to base address in Rb Load bits 0 15 of Rd from the resulting address and set bits 16 31 of Rd to bit 15 ELECTRONICS 3 79 INSTRUCTION SET S3C2500B 3 27 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 15 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples STRH R3 RO Store the lower 16 bits of R4 at the address formed by adding RO to R3 LDSB R2 R7 R1 Load into R2 the sign extended byte found at the address formed by adding to R7 LDSH R3 R4 R2 Loadinto R3 the
268. ONICS 1 6 S3C2500B PRODUCT OVERVIEW 1 5 PIN ASSIGNMENT Pns PmName Direction Pin Name Direction wm 9 i Puy FREQ 1 o 10 0 apo ets 1 o _ o A Can rate App j eo 1 o vo 9 oom O o cono 10 aoon 10 we O o 10 mo poma o m o 10 o s 0 m momocmos cra o s cts 1 s cu appro o cox Appi o ELECTRONICS 1 7 PRODUCT OVERVIEW S3C2500B 1 5 PIN ASSIGNMENT Continue Ping Direction Pin Name Direction Topo ttOO _ o m 1 mono 1 Fmj woco i o5 mcrssamoe 10 Fe mx ERR opoo uw Fj eus _ or mocowgmom rr vos 1 o os 10 wo
269. OV ELECTRONICS a3 al divide by zero Justification stage shifts 1 bit at a time a2 LSR 1 a3 LSL 1 NB LSL 1 is always OK if LS succeeds S loop a2 a3 a4 a4 a4 a2 a2 a3 a3 a1 a3 a3 LSR 1 S loop2 1 4 ip ip ASL 1 a1 a1 0 a2 a2 0 Ir 3 99 INSTRUCTION SET S3C2500B 3 39 3 DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts adds and subtracts Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code 3 39 3 1 Thumb Code udiv10 Take argument in a1 returns quotient in a1 remainder in a2 MOV a2 1 LSR a3 a1 2 SUB a1 a3 LSR a3 a1 4 ADD al LSR a3 a1 48 ADD al LSR a1 16 ADD al LSR a1 3 ASL a3 a1 2 ADD a3 a1 ASL 1 SUB a2 a3 CMP a2 10 BLT FTO ADD al 1 SUB a2 10 0 MOV Ir 3 39 3 2 ARM Code udiv10 Take argument in a1 returns quotient in a1 remainder in a2 SUB 82 a1 10 SUB a1 al a1 Isr 2 ADD a1 a1 a1 Isr 4 ADD a1 a1 a1 Isr 48 ADD a1 al Isr 16 MOV a1 a1 Isr 3 ADD a3 a1 a1 asl 2 SUBS a2 a2 a3 asl 1 ADDPL a1 a1 1 ADDMI a2 a2 10 MOV Ir 3 100 ELECTRONICS S3C2500B SYSTEM CONFIGURATION SYSTEM CONFIGURATION 4 1 OVERVIEW The System Configuration consists of several functions that control the clock configuration system bus
270. Op2 gt where lt Op2 gt Rm lt shift gt or lt expression gt cond A two character condition mnemonic See Table 3 2 S Set condition codes if S present implied for CMP CMN TEQ TST Rd Rn and Rm Expressions evaluating to a register number lt gt If this is used the assembler will attempt to generate a shifted immediate 8 bit field to match the expression If this is impossible it will give an error shift Shiftname register or shiftname expression or rotate right one bit with extend lt shiftname gt s ASL LSL LSR ASR ROR ASL is a synonym for LSL they assemble to the same code ELECTRONICS 3 17 INSTRUCTION SET Examples ADDEQ TEQS SUB MOV MOVS R2 R4 R5 R4 3 R4 R5 R7 LSR R2 PC R14 PC R14 3C2500B If the Z flag is set make R2 R4 R5 Test R4 for equality with 3 The S is in fact redundant as the assembler inserts it automatically Logical right shift R7 by the number in the bottom byte of R2 subtract result from R5 and put the answer into R4 Return from subroutine Return from exception and restore CPSR from SPSR mode ELECTRONICS S3C2500B INSTRUCTION SET 3 6 PSR TRANSFER MRS MSR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The MRS and MSR instructions are formed from a subset of the data processing operations and are implemented using the TEQ TS
271. PSR all Rm SPSR_ lt mode gt 31 0 lt Rm 31 0 MSR SPSR flg Rm SPSR mode 31 28 lt Rm 31 28 MSR SPSR_flg 0xC0000000 SPSR mode 31 28 lt set Z clear C MRS Rd SPSR Rd 31 0 lt SPSR mode 31 0 3 22 ELECTRONICS S3C2500B INSTRUCTION SET 3 7 MULTIPLY AND MULTIPLY ACCUMULATE MUL MLA The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 12 The multiply and multiply accumulate instructions use an 8 bit Booth s algorithm to perform integer multiplication 28 27 22 21 20 19 16 15 12 11 Dome ooo offs L gt root 15 12 11 8 3 0 Operand Registers 19 16 Destination Register 20 Set Condition Code 0 Do not alter condition codes 1 Set condition codes 21 Accumulate 0 Multiply only 1 Multiply and accumulate 31 28 Condition Field Figure 3 12 Multiply Instructions The multiply form of the instruction gives Rd Rm Rs is ignored and should be set to zero for compatibility with possible future upgrades to the instruction set The multiply accumulate form gives Rd Rm Rs Rn which can save an explicit ADD instruction in some circumstances Both forms of the instruction work on operands which may be considered as signed 2 complement or unsigned integers The results of a signed multiply nd of an unsigned multiply of 32 bit operands differ
272. PU PLL constant from the two constant values When this bit is set to 0 the CPU PLL constant is from CPU FREQ 2 0 setting When this bit is set to 1 the CPU PLL constant is from the CPLLCON register SPLLREN 30 SPLLCON register enable This bit controls which value is used for the BUS PLL constant from the two constant values When this bit is set to 0 the BUS PLL constant is from BUS FREQ 2 0 setting When this bit is set to 1 the BUS PLL constant is from the SPLLCON register UPLLREN 29 UPLLCON register enable This bit controls which value is used for the USB PLL constant from the two constant values When this bit is set to 0 the BUS PLL constant is always set to generates the clock frequency 4 8 times the input clock When this bit is set to 1 the USB PLL constant is from the UPLLCON register PPLLREN 28 PPLLCON register enable This bit controls which value is used for the PHY PLL constant from the two constant values When this bit is set to 0 the PHY PLL constant is from PHY FREQ setting When this bit is set to 1 the PHY PLL constant is from the PPLLCON register CPLLFD 27 CPLL filter disable This bit determines whether the CPU PLL output is filtered or not during the configuration When this bit is set to 0 the CPU PLL output is filtered to be provided to the system during the configuration In this case the glitch output from PLL can be masked When this bit is set to
273. PU Reg lt External Memory Bit Num 31 0 31 0 31 0 31 0 31 0 31 0 31 0 CPU Register Data abcd xxcd xxab xxxd XXXC xxxb Bhd Bit Num 31 31 31 31 31 Data Bus acd ies d t aaaa External Address ADDR Address ADDR Bit Num 31 31 31 External Data ie 6 5 10 ELECTRONICS S3C2500B MEMORY CONTROLLER Table 5 11 and 5 12 Using little endian and half word access Program Data path between register and external memory WA Address whose LSB is 0 4 8 C EA External Address HA Address whose LSB is 0 2 4 6 8 E BA Address whose LSB is 0 1 2 3 4 5 6 7 8 9 A B C D E F X Don t care Table 5 11 External 16 bit Datawidth Store Operation with Little Endian Transfer Width STORE CPU Reg External Memory Bit Num 31 0 31 0 31 0 31 0 CPU Register Data abcd xxab xxxb CPU Address EN EMEN Bit Num 31 31 31 CPU Data Bus e PM M aaaa Bit Num 15 0 15 0 15 0 15 0 15 0 External Data ab cd ab xb ax Timing Sequence as md Table 5 12 External 16 bit Datawidth Load Operation with Little Endian Transfer Width LOAD CPU Reg lt External Memory Bit Num 31 0 31 0 31 0 31 0 CPU Register Data abcd xxab xxxb CPU Address EN EMEN MM Bit Num 31 31 31 CPU Data Bus aub be aaaa Bit Num E E p 0 ps 0 0 Ex
274. Programmable baud rates e 32 byte Transmit FIFO and 32 byte Receive FIFO e High Speed UART source clock selectable Internal clock PCLK2 External clock EXT UCLK e PCLK2 PCLK 2 e Infra red IR transmit receive e Insertion of one or two Stop bits per frame e Selectable 5 bit 6 bit 7 bit or 8 bit data transfers e Parity checking SIO unit has a baud rate generator transmitter receiver and a control unit as shown in Figure 14 1 The baud rate generator can be driven by the internal system clock divided by 2 PCLK2 or by the external clock EXT_UCLK Auto Baud Rate Generator tries to get the baud rate from input data in this mode The transmitter and receiver blocks have independent data buffer registers and data shifters And 32 byte transmit FIFO and 32 byte receive FIFO is also provided which include transmit and receive buffer In non FIFO mode transmit data is written first to the transmit buffer register From there it is copied to the transmit shifter and then shifted out by the transmit data pin HUTXDO HUTXD1 Receive data is shifted in by the receive data pin HURXDO HURXD1 It is then copied from the shifter to the receive buffer register when one data byte has been received Otherwise you can select FIFO mode In FIFO mode transmitter and receiver use transmit FIFO and receive FIFO instead of Tx Rx buffer register HUTXBUF HURXBUF They are controlled by each FIFO trigger level The SIO control units provide s
275. Q INTOFFSET Register 16 9 16 7 Index Value of Interrupt 16 10 16 8 IPRIORHI IPRIORLO Register 0000 enne 16 12 16 9 INTTSTHI INTTSTLO 16 12 17 1 R 17 4 17 2 TDATAO TDATAS 17 6 17 3 5 REGISTE Sua aeaeaie eaaa 17 7 17 4 Timer Interrupt Clear 17 8 17 5 WOT E N E A E 17 9 17 6 Watchdog Timer Timeout 17 10 18 1 Absolute Maximum Ralings nnne 18 1 18 2 Recommended Operating 0 0 1204440000 0 18 1 18 3 D C Electric 18 2 18 4 Operating Erequerey nr tette gii e aa RE ERR ANUS 18 4 18 5 Clock AC timing specification 18 4 18 6 AC Electrical Characteristics for 3 2500 18 5 S3C2500B RISC MICROCONTROLLER xxxiii S3C2500B PRODUCT OVERVIEW PRODUCT OVERVIEW 1 1 OVERVIEW Samsung s S3C2500B 16 32 bit RISC microcontroller is a cost effective high performance microcontroller solution for Ethernet based systems for example SOHO router internet gat
276. RC mode transmitter does not append FCS to the end of data and the receiver also does not check FCS In this mode the data preceding the closing flag is transferred to the HRXFIFO In CRC mode the FCS field is transferred to the HRXFIFO ELECTRONICS 8 5 HDLC CONTROLLER S3C2500B 8 4 PROTOCOL FEATURES 8 4 1 INVALID FRAME A valid frame must have at least the A C and FCS fields between its opening and closing flags Even if no CRC mode is set the frame size should not be less than 32 bits There are three invalid frame conditions Short frame a frame that contains less than 25 bits between flags Short frames are ignored Invalid frame a frame with 25 bits or more having CRC compare error non byte aligned Invalid frames are transferred to the HRXFIFO then the invalid frame error flag RXCRCE RxNO in the status register is set to indicate that an invalid frame has been received Aborted frame a frame aborted by the reception of an abort sequence is handled as an invalid frame 8 4 2 ZERO INSERTION AND ZERO DELETION The zero insertion and zero deletion feature which allows the content of a frame to be transparent is handled automatically by the HDLC module While the transmitter inserts a binary 0 following any sequence of five 15 within a frame the receiver deletes a binary 0 that follows a sequence of five 1s within a frame 8 4 3 ABORT The function of early termination of a data link is called a
277. RTO HUART1 DES special function registers USB endpoints or external devices An external device requests the service by activating signal A channel is programmed by writing to registers which contain the requester address the target address the amount of data and other control contents HUARTO HUART1 DES external I O or software memory can request service HUARTO HUART1 and DES are internally connected to the GDMA 12 5 2 STARTING ENDING GDMA TRANSFERS GDMA starts to transfer data after the GDMA receives service request from xGDMA Req signal HUARTO HUART1 DES or software When the entire buffer of data has been transferred the GDMA becomes idle If you want to perform another buffer transfer the GDMA must be reprogrammed Although the same buffer transfer will be performed again the GDMA must be reprogrammed ELECTRONICS 12 17 GDMA CONTROLLER S3C2500B 12 5 3 DATA TRANSFER MODES 12 5 3 1 Single Mode request or an internal request causes one byte one half word or one word to be transmitted if four data burst mode is disabled or four times of transfer size if four data burst mode is enabled Single mode requires a request for each data transfer The signal can be de asserted after checking that xGDMA has been asserted xGDMA Req A A A N xGDMA Ack Figure 12 8 External GDMA Requests Single Mode 12
278. Reception The BDI receive operation is a simple FIFO mechanism The BDMA engine stores received data to MRxFIFO and the BDMA RxBUFF controller empties it when the BDMA RxBUFF has enough space left Note that the two time domains intersect at the FIFO controller The writing and reading of data is asynchronous and on different clocks Reading is driven by system clock which is asynchronous to Writing is driven by either a 25MHz or a 2 5MHz After a reset the MRxFIFO is empty To enable the reception the system must set the receive enable bit in the MACRXCON register If the BDMA engine cannot transfer the received data to the BRXBUFF and memory due to the disabled BDMA or the inaccessibility on the system bus the MAC RxFIFO may overflow Carrier sense on Carrier sense ON after detection SFD store byte stream in in FIFO Recognize Discard the frame address report error status Move the byte stream in the FIFO to the receive buffer memory o Frame too long Interrput CPU for handing the frame Check ethertype or length field MAC drive software Disassemble frame software jobs for typical LAN cards Signal to upper layer Figure 7 11 CSMA CD Receive Operation 7 44 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 5 2 THE MII STATION MANAGER The MDIO management data input output signal line is the transmission and reception path for control status information for the station management
279. Register 9 20 ELECTRONICS S3C2500B IOM2 CONTROLLER 9 5 7 2 1 CHANNEL TRANSMIT DATA REGISTER Table 9 11 IOM2CITD1 IOM2 C I1 Channel Transmit Data Register IOM2CITD1 0xF0130020 C I1 Channel Transmit Data 0x0000003F Bit Number Description 5 0 CITD1 This field includes the data to be transmitted on the C I1 channel The data is continuously transmitted until a new code is loaded i 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 0 5 0 1 Channel Transmit Data Figure 9 15 2 1 Channel Transmit Data Register 9 5 8 IOM2 1 CHANNEL RECEIVE DATA REGISTER Table 9 12 IOM2CIRD1 IOM2 1 Channel Receive Data Register IOM2CIRD1 0 0130024 C I1 Channel Receive Data 0x00000000 Bit Number Description 5 0 CIRD1 This field includes the data received on the C I1 channel This data is sure to be valid by double last look criterion valid during two successive frames pup feed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211109 8 7 6 5 0 cov 5 0 1 Channel Receive Data Figure 9 16 IOM2 1 Channel Receive Data Register ELECTRONICS 9 21 IOM2 CONTROLLER S3C2500B 9 5 9 2 MONITOR CHANNEL TRANSMIT DATA REGISTER Table 9 13 IOM2MTD 2 Monitor Channel Transmit Data Register IOM2MTD 0 0130028 Monitor Channel Transmit Data 0x000000FF 7 0 MTxD This field inclu
280. Registers TDATAO TDATA5 17 6 ELECTRONICS S3C2500B 32 BIT TIMERS 17 6 3 TIMER COUNT REGISTERS The timer count registers TCNTO TCNT5 contain the current timer 0 5 count value respectively during the normal operation Table 17 3 TCNTO TCNT5 Registers 31 0 31 0 Timer 0 5 count value Figure 17 5 Timer Count Registers TCNTO TCNT5 ELECTRONICS 17 7 32 BIT TIMERS S3C2500B 17 6 4 TIMER INTERRUPT CLEAR REGISTERS Timer Interrupt Clear register TIC clears the current interrupt of the six 32 bit timers and one watchdog timer Table 17 4 Timer Interrupt Clear Registers 0 0040004 RW Timer Interrupt Clear 0x00000000 0 WDT interrupt clear WDTIC 0 no interrupt clear 1 interrupt clear TimerO interrupt clear TICO 0 no interrupt clear 1 interrupt clear 2 Timer1 interrupt clear TIC1 0 no interrupt clear 1 interrupt clear 3 Timer2 interrupt clear TIC2 0 no interrupt clear 1 interrupt clear 4 Timer3 interrupt clear TIC3 0 no interrupt clear 1 interrupt clear 5 Timer4 interrupt clear 4 0 no interrupt clear 1 interrupt clear 6 Timer5 interrupt clear TIC5 0 no interrupt clear 1 interrupt clear Figure 17 6 Timer Interrupt Clear Register 17 8 ELECTRONICS S3C2500B 32 BIT TIMERS 17 6 5 WATCHDOG TIMER REGISTER WDT To use Watchdog Timer Watchdog Timer Register WDT must be set If WDT 29 RST is 1 when WDT 31
281. SB CONTROLLER S3C2500B TS T or TT see ni semel TD m sees eee s NN NN sess s H m RL s Rx Voice Interrupt Control Low Speed Figure 10 2 USB 1 1 Frame Model 10 3 3 PACKET FORMATS All packets begin with a synchronization SYNC field which is a coded sequence that generates a maximum edge transition density The SYNC field appears on the bus as IDLE followed by the binary string KJKJKJKK in its NRZI encoding It is used by the input circuitry to align incoming data with the local clock and is defined to be eight bits in length SYNC serves only as a synchronization mechanism and is not shown in the following packet diagrams The last two bits in the SYNC field are a marker that is used to identify the end of the SYNC field and by inference the start of the PID The PID indicates the type of packet and by inference the format of the packet and the type of error detection applied to the packet The host and all functions must perform a complete decoding of all received PID fields Any PID received with a failed check field or which decodes to a non defined value is assumed to be corrupted and it as well as the remainder of the packet is ignored by the packet receiver If a function receives an otherwise valid PID for a transaction type or direction that it does not support the function must not respond For example an IN only endpoint
282. SEMBLER SYNTAX LDMISTM cond FD ED FA EAIIA IBIDA DB Rn lt Rlist gt where cond Two character condition mnemonic See Table 3 2 Rn An expression evaluating to a valid register number lt Rlist gt A list of registers and register ranges enclosed in e g RO R2 R7 R10 If present requests write back W 1 otherwise W 0 If present set S bit to load the CPSR along with the PC or force transfer of user bank when in privileged mode 3 11 9 1 Addressing Mode Names There are different assembler mnemonics for each of the addressing modes depending on whether the instruction is being used to support stacks or for other purposes The equivalence between the names and the values of the bits in the instruction are shown in the following table 3 6 Table 3 6 Addressing Mode Names Postincrementioad two oma 9 9 Post Decrementioad 3 9 9 memwemmsoe smea o Postincremert sore SEA sma o o Pre Decrement sre smeo sm o 9 Post Decrement store smeo o o o FD ED FA EA define pre post indexing and the up down bit by reference to the form of stack required The F and E refer to full or empty stack i e whether a pre index has to be done full before storing to the stack The A and D refer to whether the stack is ascending or
283. SR automatically sets the T bit to the value it held immediately prior to the exception ELECTRONICS 2 11 PROGRAMMER S MODEL S3C2500B 2 9 3 EXCEPTION ENTRY EXIT SUMMARY Table 2 2 summarizes the PC value preserved in the relevant R14 on exception entry and the recommended instruction for exiting the exception handler Table 2 2 Exception Entry Exit Return Instruction Previous State ARM R14 x THUMB R14 x MOV PC R14 MOVS PC R14 svc MOVS PC R14 und SUBS R14 fiq 4 SUBS R14 irq 4 SUBS R14 abt 4 SUBS R14 abt 8 NA 1 1 1 2 2 1 3 4 NOTES 1 Where PC is the address of the BL SWI Undefined Instruction fetch which had the prefetch abort 2 Where PC is the address of the instruction which did not get executed since the FIQ or IRQ took priority 3 Where PC is the address of the Load or Store instruction which generated the data abort 4 The value saved in R14 svc upon reset is unpredictable 2 9 4 FIQ The FIQ Fast Interrupt Request exception is designed to support a data transfer or channel process and in ARM state has sufficient private registers to remove the need for register saving thus minimizing the overhead of context switching FIQ is externally generated by taking the nFIQ input LOW This input can except either synchronous or asynchronous transitions depending on the state of the ISYNC input signal When ISYNC is LOW nFIQ and nIRQ are considered asynchronous and a
284. Signal 1 13 1 2 53 2500 Pad and 2 1 31 1 3 53 2500 System 1 32 1 4 S3C2500B Memory Controller sees 1 32 1 5 S3C2500B SDRAM Controller 1 32 1 6 S3C2500B Controller 1 33 1 7 S3C2500B Ethernet Controller 0 0 1 33 1 8 S3C2500B Ethernet Controller 1 1 34 1 9 S3C2500B HDLC Controller O 1 35 1 10 S3C2500B HDLC Controller 1 1 36 1 11 S3C2500B HDLC Controller 2 1 37 1 12 S3C2500B 2 nennen 1 38 1 13 S3C2500B USB Oontroller 2 010 eene 1 39 1 14 S3C2500B DES Gorttroller a u engen nx denn 1 40 1 15 S3C2500B nnn 1 41 1 16 S3C2500B Console UART 1 42 1 17 53 2500 High speed UART Controller 0 1 42 1 18 S3C2500B High speed UART Controller 1 1 43 1 19 53 2500 I O Port 1 43 1 20 53 2500 Interrupt Controller 1 44 1 21 53 2500 Timer 1 45 2 1 PSR MOGe Bit NENEI a ET 2 10 2 2 Exception ENY EXIT ceo 2 12 2 3 Exception Vector S i EE
285. T CMN and CMP instructions without the S flag set The encoding is shown in Figure 3 11 These instructions allow access to the CPSR and SPSR registers The MRS instruction allows the contents of the or 5 5 mode to be moved to a general register The MSR instruction allows the contents of a general register to be moved to the CPSR or SPSR mode register The MSR instruction also allows an immediate value or register contents to be transferred to the condition code flags N Z C and V of CPSR or SPSR mode without affecting the control bits In this case the top four bits of the specified register contents or 32 bit immediate value are written to the top four bits of the relevant PSR 3 6 1 OPERAND RESTRICTIONS n user mode the control bits of the CPSR are protected from change so only the condition code flags of the CPSR can be changed In other privileged modes the entire CPSR can be changed Note that the software must never change the state of the T bit in the CPSR If this happens the processor will enter an unpredictable state SPSR register which is accessed depends on the mode at the time of execution For example only SPSR fiq is accessible when the processor is in FIQ mode You must not specify R15 as the source or destination register Also do not attempt to access an SPSR in User mode since no such register exists ELECTRONICS 3 19 INSTRUCTION SET S3C2500B 3 20 MRS Tran
286. T L T SIR B 1 0 SIO transmit mode selection TMODE 00 Disable 01 Interrupt request 10 GDMA request 11 Reserved 9 2 SIO receive mode selection RMODE 00 Disable 01 Interrupt request 10 GDMA request 11 Reserved 4 Send Break SBR 0 Send normal TxData 1 Send Break signal 5 Serial Clock Selection SCSEL 0 Internal systen clock divided 2 PCLK2 rmooojo 1 External UART clock UCLK 6 Auto Baud Rate Detect AUBD 0 Normal operating mode 1 Auto Baud Rate Detect mode 7 Loopback mode LOOPB 0 Normal operating mode 1 Enable Loopback mode only for test 10 8 Parity mode PMD Oxx No parity 100 Odd parity 101 Even parity 110 Parity forced checked as 1 111 Parity forced checked as 0 11 Stop Bits STB 0 1 stop bit 1 2 stop bits 13 12 Word Length WL 00 5 bit 01 6 bit 10 7 bit 11 8 bit 14 Infra red mode IR 0 normal operating mode 1 Infra red mode 15 Reserved This bit should be cleared Figure 14 2 High Speed UART Control Register ELECTRONICS 14 7 SERIAL I O HIGH SPEED UART S3C2500B 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 16 Transmit FIFO Enable TFEN 0 Disable Transmit FIFO 1 Enable Transmit FIFO 17 Receive FIFO Enable RFEN 0 Disable Receive FIFO 1 Enable Receive FIFO 18 Tranmit FIFO Reset TFRST 0 Normal operation 1 Reset Tr
287. THUMB state Branch and change to THUMB state Assemble subsequent code as THUMB instructions Generate branch target to word aligned address hence bit 0 is low and so change back to ARM state Branch and change back to ARM state Word align Assemble subsequent code as ARM instructions ELECTRONICS S3C2500B INSTRUCTION SET 3 4 BRANCH AND BRANCH WITH LINK B BL The instruction is only executed if the condition is true The various conditions are defined Table 3 2 The instruction encoding is shown in Figure 3 3 below 31 2827 252423 0 24 Link Bit 0 Branch 1 Branch with link 31 28 Condition Field Figure 3 3 Branch Instructions Branch instructions contain a signed 2 s complement 24 bit offset This is shifted left two bits sign extended to 32 bits and added to the PC The instruction can therefore specify a branch of 32Mbytes The branch offset must take account of the pre fetch operation which causes the PC to be 2 words 8 bytes ahead of the current instruction 3 4 1 THE LINK BIT Branch with Link BL writes the old PC into the link register R14 of the current bank The PC value written into R14 is adjusted to allow for the pre fetch and contains the address of the instruction following the branch and link instruction Note that the CPSR is not saved with the PC and R14 1 0 are always cleared To return from a routine called by branch with link use MOV PC R14 if the link regist
288. TRONICS 8 3 HDLC CONTROLLER S3C2500B 8 3 1 HDLC FRAME FORMAT The HDLC transmits and receives data address control information and CRC field in a standard format called a frame All frames start with an opening flag beginning of flag BOF 7EH and end with a closing flag end of flag EOF 7EH Between the opening and the closing flags a frame contains an address A field a control C field an information 1 field optional and a frame check sequence FCS field see Table 8 1 Table 8 1 HDLC Data Frame Format Opening Address Control Information Frame Check Closing Flag Field Field Field Sequence Field Flag 01111110 8 bits per byte 8 bits per byte 8 bits per byte 16 bits 01111110 variable length NOTE The address field can be extended up to four bytes using a optional software control setting 8 3 1 1 Flag F A flag is a unique binary pattern 01111110 that is used to delimit HDLC frames This pattern is generated internally by the transmitter An opening flag starts a frame and a closing flag ends the frame Opening flags and closing flags are automatically appended to frames A single flag pattern can optionally serve as both the closing flag of one frame and the opening flag of the next one This feature is controlled by the double flag FF single flag F or frame separator selection bit the TxSDFL bit in the HCON register 8 3 1 2 Order of Bit Transmission Address field control field and informatio
289. TRUCTION SET PC PC R5 but don t set the condition codes CMP Set the condition codes on the result of R4 R12 Move R14 LR into R15 PC but don t set the condition codes eg return from subroutine Switch from THUMB to ARM state Load address of outofTHUMB into R1 Transfer the contents of R11 into the PC Bit O of R11 determines whether ARM or THUMB state is entered ie ARM state here Now processing ARM instructions If R15 is used as an operand the value will be the address of the instruction 4 with bit O cleared Executing a BX PC in THUMB state from a non word aligned address will result in unpredictable execution ELECTRONICS 3 75 INSTRUCTION SET S3C2500B 3 25 FORMAT 6 PC RELATIVE LOAD 15 14 13 7 0 12 11 10 8 7 0 Immediate Value 10 8 Destination Register Figure 3 35 Format 6 3 25 1 OPERATION This instruction loads a word from an address specified as a 10 bit immediate offset from the PC The THUMB assembler syntax is shown below Table 3 13 Summary of PC Relative Load Instruction THUMB Assembler ARMEquivalent LDR PC lmm LDR Rd R15 Add unsigned offset 255 words 1020 bytes in Imm to the current value of the PC Load the word from the resulting address into Rd NOTE The value specified by lmm is a full 10 bit address but must always be word aligned ie with bits 1 0 set to 0 since the assembler place
290. The High Speed UART receive buffer registers HURXBUF contain an 8 bit data value to be received over the High Speed UART channel Table 14 11 HURXBUF Registers Offset Address HURXBUF 0xF0070010 High Speed UART receive buffer register OxF0080010 Table 14 12 High Speed UART Receive Register Description Description 7 0 Receive data This field contains the data received over the single channel High Speed UART When the High Speed UART finishes receiving a data frame the receive data ready bit in the High Speed UART status register HUSTAT 14 should be 1 This prevents reading invalid receive data that may already be present in the HURXBUF Whenever the HURXBUF is read the receive data valid bit HUSTAT 14 is automatically cleared to O 31 8 7 0 peeve Dats 7 0 Receive data for UART Figure 14 6 High Speed UART Receive Buffer Register ELECTRONICS 14 17 SERIAL I O HIGH SPEED UART S3C2500B 14 3 6 HIGH SPEED UART BAUD RATE DIVISOR REGISTER The values stored in the baud rate divisor registers HUBRD let you determine the serial Tx Rx clock rate baud rate as follows PCLK2 or EXT UCLK BRGOUT ONTO 1 x 16CNTI x 16 Table 14 13 HUBRDO and HUBRDO Registers HUBRD 0070014 R W High Speed UART baud rate divisor register 0x00 0080014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 3 0 Baud reate divisor value CNT1 xxx0 divide by 1 xxx1 divide by 16 15 4 Time consta
291. The nBE DQM signal is operated at writing and reading operation 27 24 Bank Size BS 0000 Disable 0001 1M 0100 8M 0101 16M 0010 2M 0011 4M 0110 1111 2 Reserved 29 28 Page mode configuration PMC 00 Normal ROM or External I O 01 4 word page 10 8 word page 11 16 word page 31 30 Physical memory data bus width DW 00 Reserved 01 8 bit 10 16 bit 11 32 bit Figure 5 11 Bank n Control BnCON Register Configuration 5 24 ELECTRONICS S3C2500B MEMORY CONTROLLER NOTES 1 If WAITEN of WAITCON register is enable memory controller can t finish access cycle until nEWAIT signal is high If you use slow device you can set WAITEN to 1 and control nEWAIT signal memory controller checks nEWAIT signal at the last cycle of If you set WAITEN to 0 the f nEWAIT signal is ignored 2 You can use memory control signals such as nCS nWBE nOE nEWAIT for 8 bit memory and nCS nWE16 nOE nEWAIT for 16 bit memory 3 The DW of bank 0 is the same with BOSIZE 1 0 pin That is read only value The initial value of other banks is 11 5 6 3 2 Muxed bus control register Ext I O Bank controller supports memory devices which have the muxed bus interface To use muxed bus memory device muxed bus enable MBE and muxed bus address cycle TMA for each bank in MUXBCON register must be set Table 5 17 Muxed Bus Control Register MUXBCON OxF0010020 Muxed bus control register 0x006DB6DB EL
292. Transmit Holding Register Empty THE 0 Tranmit holding register is not empty 1 Transmit holding register is empty 31 19 Reserved Figure 13 4 Console UART Status Register 13 10 ELECTRONICS S3C2500B SERIAL CONSOLE UART 13 3 3 CONSOLE UART INTERRUPT ENABLE REGISTER Table 13 6 CUINT Registers Register Address RW Description Sie Reset Value CUINT OxF0060008 RW Console UART interrupt enable register 0x00000000 Table 13 7 Console UART Interrupt Enable Register Description S 4 5 OERIE Overrun Error interrupt enable Rem pup ELECTRONICS 13 11 SERIAL CONSOLE UART S3C2500B 13 12 19 18 17 16 0 Receive Data Valid Interrupt Enable RDVIE 1 Break Signal Detected Interrupt Enable BKDIE 2 Frame Error Interrupt Enable FERIE 3 Parity Error Interrupt Enable PERIE 4 Overrun Error Interrupt Enable OERIE 5 Control Character Detect Interrupt Enable CCDIE 16 6 Reserved 17 Transmitter Idle TIIE 18 Transmit Holding Register Empty Interrupt Enable THEIE 31 19 Reserved Figure 13 5 Console UART Interrupt Enable Register ELECTRONICS S3C2500B SERIAL CONSOLE UART 13 3 4 UART TRANSMIT DATA REGISTER Table 13 8 CUTXBUF Registers Register Address RW Description Sie Reset Value CUTXBUF OxF006000C Console UART transmit data register o B Table 13 9 Console UART Transmit Regis
293. USB with large amounts of free bandwidth bulk transfers may happen relatively quickly for a USB with little bandwidth available bulk transfers may trickle out over a relatively long period of time A bulk pipe is a stream pipe and therefore always has communication flowing either into or out of the host for a given pipe If a device requires bi directional bulk communication flow two bulk pipes must be used one in each direction ELECTRONICS 10 5 USB CONTROLLER S3C2500B 10 3 6 CONTROL TRANSACTIONS Control transfers are bursty non periodic host software initiated request response communication typically used for command status operations Control transfers allow access to different parts of a device Control transfers are intended to support configuration command status type communication flows between client software and its function A control transfer is composed of a Setup bus transaction moving request information from host to function zero or more Data transactions sending data in the direction indicated by the Setup transaction and a Status transaction returning status information from function to host The Status transaction returns success when the endpoint has successfully completed processing the requested operation Control transfers are supported via bi directional communication flow over message pipes As a consequence when a control pipe is configured it uses both the input and output endpoint with the specified en
294. UnCTS1 level is low this bit is set And HUnCTSO HUnCTS 1 high this bit is cleared This bit is set to 1 whenever HUnCTSO HUnCTS 1 level changed If the E CTS interrupt enable bit HUINT 16 is 1 a interrupt is generated when a CTS event is occurred You can clear this bit by writing 1 to this bit 17 is automatically set to 1 when the transmit holding register has no valid data to transmit and when the TX shift register is empty The reset value is 1 In Transmit FIFO mode when Transmit FIFO is empty to trigger level this bit set to 1 In non FIFO mode when HUTXBUF is empty without regarding Tx shift register this bit set to 1 An interrupt or DMA request is generated when 8 is 1 In case HUCON 1 0 2 01 and HUINT 18 1 an interrupt requested and 0 10 or 11 DMA request occurred You can clear this bit by writing TxDATA into HUTXBUF or Transmit FIFO This bit is only for CPU to monitor High Speed UART When Transmit FIFO is empty this bit is set to 1 After reset default value is 1 This bit is only for CPU to monitor High Speed UART When Transmit FIFO is full this bit is set to 1 After reset default value is 0 14 11 SERIAL I O HIGH SPEED UART S3C2500B 21 20 19 18 17 16 15 14 13 12 11 10 T T E JC H T E Cis T S 0 Receive Data Valid RDV 0 No valid data Receive FIFO top or HURXBUF 1 Valid data present Re
295. Unsigned multiply long 32 x 32 64 UMLAL cond S Rm Rs Unsigned multiply amp Accumulate long 32 x 32 64 64 SMULL cond S RdLo RdHi Rm Rs Signed multiply long 32 x 32 64 SMLAL cond S Rm Rs Signed multiply amp Accumulate long 32 x 32 64 64 where cond S RdLo RdHi Rm Rs Examples UMULL UMLALS ELECTRONICS Two character condition mnemonic See Table 3 2 Set condition codes if S present Expressions evaluating to a register number other than R15 R1 R4 R2 R3 R4 R1 R2 R1 R5 R2 R3 R5 R1 R2 R5 also setting condition codes 3 27 INSTRUCTION SET S3C2500B 3 9 SINGLE DATA TRANSFER LDR STR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 14 The single data transfer instructions are used to load or store single bytes or words of data The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register The result of this calculation may be written back into the base register if auto indexing is required 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0 s 21111011 15 12 Source Destination Registers 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address i
296. WAITCON register of memory controller ADDR 23 bit is used the address latch enable ALE signal to latch an address for the ROM and SRAM which have the muxed bus structure 5 20 ELECTRONICS S3C2500B MEMORY CONTROLLER 5 6 3 EXT BANK CONTROLLER SPECIAL REGISTER To control the external memory operations the memory controller uses a dedicated set of special registers see Table 5 15 By programming the values in the memory controller special registers you can specify such things as e Memory type e External bus width selection e Control signal timing e Ext I O access cycles control e sizes of memory banks to be used for arbitrary address spacing The memory controller uses some special registers to control the generation and processing of the control signals addresses and data that are required by the external devices in a standard system configuration The special registers are also used to control access to all banks Table 5 15 Ext I O Bank Controller Special Registers BOCON OxF0010000 Bank 0 control register 0xC514E488 BOSIZE 3 0x8514E488 BOSIZE 2 0x4514E488 BOSIZE 1 B1CON OxF0010004 Bank 1 control register 0xC514E488 B2CON OxF0010008 Bank 2 control register 0xC514E488 B3CON OxF001000C Bank 3 control register 0xC514E488 NOTE BOSIZE means the size of physical data bus width in Bank 0 Refer to the next page ELECTRONICS 5 21 MEMORY CONTROLLER S3C2500B 5 6 3 1 Ext I O Bank Access Contr
297. WCEP2 0 0038 USB Write Count for Endpoint 2 Register 0x00000000 Table 10 30 USBWCEP2 Register Description CPU WRiTe R W the byte count number of data to be loaded into FIFO CouNT CPUWRTONT 57 Reevwed ooo 21 16 WRiTe CouNT W the byte count number of data in FIFO due to be WRTCNT unloaded by the MCU Reserved FP ELECTRONICS 10 49 USB CONTROLLER S3C2500B 31 22 21 16 15 6 5 0 5 0 ep2 CPU WRiTe CPUWRTCNT 15 6 Reserved 21 16 ep2 WRiTe CouNT WRTCNT 31 22 Reserved Figure 10 19 USBWCEP2 Register 10 50 ELECTRONICS S3C2500B USB CONTROLLER 10 5 15 USB WRITE COUNT FOR ENDPOINT 3 REGISTER When OORDY is set for OUT endpoints USBWCEP3 22 16 maintains the byte count number of data in FIFO due to be unloaded by the MCU In case of IN mode MCU first writes the byte count number of data to be loaded into FIFO then write data into FIFO Table 10 31 USBWCEP3 Register USBWCEP3 OxF00E003C USB Write Count for Endpoint 3 Register 0x00000000 Table 10 32 USBWCEP3 Register Description CPU WRiTe R W the byte count number of data to be loaded into FIFO CouNT CPUWRTONT 7 Reserved FP 22 16 WRiTe CouNT W the byte count number of data in FIFO due to be WRTCNT unloaded by the MCU ELECTRONICS 10 51 USB CONTROLLER S3C2500B 31 23 22 16 15 7 6 0 6 0 ep3 CPU WRiTe CouNT CPUWRTCNT 15 7 Reserved 22 16 ep3 WRiTe CouNT WRTC
298. a frame to be stored and retransmitted without further system involvement in case of a collision If no collision occurs and transmission is underway the additional 16 bytes handle system latency and avoid FIFO under run When the system interface has set the MACTXCON O bit the transmission state machine requests data from the BDI The system controller then fetches data from the system memory The data is stored in the MTxFIFO until the threshold for transmit data is satisfied When the MTxFIFO is not full a request is issued to the BDI for more data It then appends the calculated CRC to the end of the data unless the CRC truncate bit in the transmit control register is set 7 3 4 2 Preamble and Jam Generator As soon as the MACTXCON O bit is set and there are eight bytes of data in the MTxFIFO the transmission state machine starts the transmission by asserting the TX EN signal and transmitting the preamble and the start frame delimiter SFD In case there is a collision it transmits a 32 bit string of 1 s after the preamble as a jam pattern 7 3 4 3 PAD Generator If a short data frame is transmitted the MAC will normally generate pad bytes to extend the frame to a minimum of 64 bytes The pad bytes consist entirely 0 bits A control bit is also used to suppress the generation of pad bytes 7 3 4 4 Parallel CRC Generator The CRC generation of the outgoing data starts from the destination address and continues through th
299. able 12 4 GDMA Control Register Description Run enable disable Setting this bit to 1 starts GDMA operation To stop you must clear this bit to 0 You can use the DRER run enable register to manipulate this bit By using the DRER other GDMA control register values are not affected GDMA mode selection 6 GDMA modes can initiate a GDMA operation 1 software mode memory to memory or memory to from USB 000 2 an external request mode 001 3 HUART TX mode HUART from memory 010 4 HUART mode HUART to memory 011 5 DES IN mode DES from memory 100 6 DES OUT mode DES to memory 101 Single Block mode This bit determines the number of external GDMA requests XGDMA Req 0 3 that are required for a operation In Single mode when 4 0 the S3C2500B requires an external GDMA request for every GDMA operation In Block mode when 4 1 the S3C2500B requires only one external request during the entire GDMA operation An entire GDMA operation is defined as the operation of GDMA until the counter value is zero The block mode can be used only when GDMA mode is external GDMA request mode Four data burst mode If this bit is set to 1 GDMA operates under four data burst mode Four consecutive source addresses are read and then are written to the consecutive destination addresses If four data burst mode is set to 1 Transfer Count Regist
300. ack pointed to by R13 SP and update R13 Useful at start of a sub routine to Save workspace and return address POP R2 R6 PC Load R2 R6 and R15 PC from the stack pointed to by R13 SP and update R13 Useful to restore workspace and return from sub routine ELECTRONICS 3 89 INSTRUCTION SET S3C2500B 3 34 FORMAT 15 MULTIPLE LOAD STORE 15 14 13 7 0 12 11 10 8 pt totot ey m 7 0 Register List 10 8 Base Register 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 3 44 Format 15 3 34 1 OPERATION These instructions allow multiple loading and storing of Lo registers The THUMB assembler syntax is shown in the following table Table 3 22 The Multiple Load Store Instructions THUMB Assembler Equivalent STMIA Rb Rlist STMIA Rb Rlist Store the registers specified by Rlist starting at the base address in Rb Write back the new base address 1 LDMIA Rlist LDMIA Rb Rlist Load the registers specified by Rlist starting at the base address in Rb Write back the new base address 3 34 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 22 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples STMIA RO R3 R7 Store the contents of registers R3 R7 starting at the address specified in RO
301. al ARM940T and system bus clock is connect to Fout 2 66 MHz clock ELECTRONICS 4 23 SYSTEM CONFIGURATION S3C2500B 4 9 9 USB PLL CONTROL REGISTER UPLLCON If you want to use this register you should set UPLLREN SYSCFG 29 to 1 This register doesn t work with UPLLREN set to 0 UPLLCON 0 0000024 USB PLL control register 0x00010328 UPLLCON Bit Description Reserved 31 12 S 17 16 Scaler Reserved 13 8 Pre divider M 7 0 Main divider Output clock frequency is determined by following formula Fout Fin x M 8 P 2 x 2 S If Fin 10MHz P 2 3 M 40 0x28 and S 1 Fout is 48MHz 4 9 10 PHY PLL CONTROL REGISTER PPLLCON If you want to use this register you should set PPLLREN SYSCFG 28 to 1 This register doesn t work with PPLLREN set to 0 PPLLCON 0 0000028 PHY PLL control register 0x00010311 PPLLCON Description 31 12 17 16 Scaler Reserved 15 14 P 138 Pre divider 7 0 Main divider Note Some switches may cause a link failure when S3C2500 s PHY source clock PHY CLKO is used Output clock frequency is determined by following formula Fout Fin x M 8 P42 2 S If Fin 10MHz P 3 M 17 0x11 and S 1 Fout is 25MHz 4 24 ELECTRONICS S3C2500B MEMORY CONTROLLER MEMORY CONTROLLER 5 1 OVERVIEW This Memory controller consists of Ext Bank controller and SDRAM controller Ext
302. alue within the coprocessor illustrates the use of ARM9TDMI register to coprocessor transfer MCR An important use of this instruction is to communicate control information directly from the coprocessor into the ARM9TDMI CPSR flags As an example the result of a comparison of two floating point values within coprocessor can be moved to the CPSR to control the subsequent flow of execution 28 27 2423 212019 16 15 12 11 7 5 43 Du Dow De PT om 3 0 Coprocessor Operand Register 7 5 Coprocessor Information 11 8 Coprocessor Number 15 12 ARM Source Destination Register 19 16 Coprocessor Source Destination Register 20 Load Store Bit 0 Store to coprocessor 1 Load from coprocessor 21 Coprocessor Operation Mode 31 28 Condition Field Figure 3 27 Coprocessor Register Transfer Instructions 3 16 1 THE COPROCESSOR FIELDS The CP field is used as for all coprocessor instructions to specify which coprocessor is being called upon The CP Opc CRn CP and CRm fields are used only by the coprocessor and the interpretation presented here is derived from convention only Other interpretations are allowed where the coprocessor functionality is incompatible with this one The conventional interpretation is that the CP Opc and CP fields specify the operation the coprocessor is required to perform CRn is the coprocessor register which is the source or destination of the transferred information and CRm
303. ame to each successive flag If the frame is terminated because of a short frame condition frame data is less than 32 bits after an opening flag the frame is simply ignored Noise on the data input line RXD during time fill can cause this kind of invalid frame The received data which is clocked by the external TXC or RXC or by an internal DPLL or BRG source enters a 56 bit or 32 bit shift register before it is transferred into the HRXFIFO Synchronization is established when a flag is detected in the first eight locations of the shift register When synchronization has been achieved data is clocked through to the last byte location of the shift register where it is transferred into the HRXFIFO In 1 word transfer mode when the HRXFIFO available bit RxFA is 1 data is available at least in one word In 4 word transfer mode the RxFA is 1 when data is available in the last four FIFO register locations registers 4 5 6 and 7 The nDCD input is provided for a modem or other hardware interface If AutoEN bit in HCON 28 is set to 1 the receiver operation is dependent on the nDCD input level Otherwise receiver operation is free of the nDCD input level 8 5 5 1 Receiver Interrupt Mode Whenever data is available in the HRXFIFO an interrupt is generated by RxFA if the interrupt is enabled The CPU reads the HDLC status register either in response to the interrupt request or in turn during a polling sequence When the received d
304. an be moved to Rx FIFO at this time 30 Transmit reverse If this bit set to one the data will be sent MSB first If this bit set to zero TxREV LSB first 31 Receive reverse If this bit set to one the received data will be MSB first If this bit set to RxREV zero LSB first 29 Transparent Rx stop This bit reset value is zero If this bit set to one the receive operation is TRxSTOP ended in transparent mode And then the receiver start to search Sync If ELECTRONICS 8 33 HDLC CONTROLLER S3C2500B 8 34 29 28 27 26 25 24 23 2221 15 14 13 1211109 8 7 6 5 4 3 0040x221 OmOOZxZzm gt 4 gt amp AO 0 x 40 0 Tx reset 5 0 Normal 1 TxFlFOmand Tx block are reset Rx reset RxRS 0 Normal operation 1 RxFIFO and Tx block are reset 2 DMA Tx reset DTxRS 0 Normal operation 1 DMA Tx block is reset 3 DMA Rx reset DRxRS 0 Normal operation 1 Rx block is reset 4 Tx enable TxEN 0 Tx disabled 1 Tx enabled 5 Rx enable RxEN 0 Rx disabled 1 Rx enabled 6 DMA Tx enable DTxEN 0 DMA Tx disabled 1 DMA Tx enabled 7 DMA Rx enable DRxEN 0 DMA Rx disabled 1 DMA Rx enabled 8 DPLL enable DPLLEN 0 Disable 1 Enable DPLL enters search mode for a locking edge in the incoming data stream 9 BRG enable BRGEN 0 BRG counter is inbibited 1 BRG counter is enabled 10 Tx 4 wor
305. an control it by using DESCON 12 If DESCON 12 is set byte swapped key is written to DESKEY3R Otherwise original key is written to DESKEY3R 11 3 8 DES 3DES IV LEFT RIGHT SIDE REGISTER Table 11 12 DES 3DES IV Left Side Register Description 1 32 IV Left Half IV is only used for the CBC mode The left half of the 1 IV should be stored in this register The IV for the next block is updated in this register automatically If users need to byte swapped iv value they can control it by using DESCON 1 1 If DESCON 1 1 is set byte swapped iv is written to DESIVL Otherwise original key is written to DESIVL Table 11 13 DES 3DES IV Right Side Register Description 33 64 IV Right Half IV is only used for the CBC mode right half of the 1 IV should be stored in this register The IV for the next block is updated in this register automatically If users need to byte swapped iv value they can control it by using DESCON 1 1 If DESCON 1 1 is set byte swapped iv is written to DESIVR Otherwise original key is written to DESIVR 11 8 ELECTRONICS S3C2500B DES 3DES 11 3 9 DES 3DES INPUT OUTPUT DATA FIFO REGISTER Table 11 14 DES 3DES Input Data FIFO Description 31 0 DESINFIFO This FIFO can be filled by CPU or DMA depends on control register value This FIFO consists of 8 words If data are transferred by DMA the 4 word burst transaction DESCON T is zero and 5 is one is recommended Otherw
306. an eR 3 57 3 16 3 Transfers from R15 nennen 3 57 3 16 4 Instruction Cycle r 3 57 3 16 5 Assembler Syntax 3 57 3 17 Undefined Instruction 3 58 3 17 1 Instruction Cycle Times 3 58 3 17 2 Assembler Syntax e nennen nsns 3 58 3 18 Instruction Set 3 59 3 18 1 Using The Conditional 3 59 3 18 2 Pseudo Random Binary Sequence 2 3 61 3 18 3 Multiplication by Constant Using The Barrel 3 61 3 18 4 Loading a Word From an Unknown 3 63 3 19 Thumb Instruction Set 3 64 3 19 1 Format 3 64 3 19 2 Opcode nnns 3 65 3 20 Format 1 Move Shifted 3 67 320V Operatio TEES 3 67 3 20 2 Instruction Cycle 5 3 67 3 21 Format 2 Add Subtract 3 68 CC 3 68 3 21 2 Instr
307. ance with the highest quality standards and objectives Samsung Electronics Co Ltd San 24 Nongseo Ri Kiheung Eup Yongin City Kyunggi Do Korea Box 37 Suwon 449 900 TEL 82 31 209 2831 FAX 82 31 209 3262 Home Page URL http www samsungsemi com Printed in the Republic of Korea Table of Contents Chapter 1 Product Overview EST 1 1 eatur 1 2 1 3 Block Did Gramm 1 5 1 4 Package 1 6 1 5 Pin Assignment 1 7 1 6 Signal 1 13 VALER PEPPER 1 31 1 8 Special 1 32 Chapter 2 Programmer s Model OVOIVIOW crt cct np 2 1 Ze Pec ei ole QU M a 2 1 2 2 1 Entering THUMB 2 1 2 2 2 Entering ARM 1 2 1 2 3 MEMORY HI 2 2 2 31 BigeEndian Formal oie er ett e est eee ayau aaa eat Sas 2 2 2 3 2 44 Formatiu u D T 2 2 2 4 Instruction Le
308. and detach and reconfiguration and so on USB architecture is suitable for wide range of workloads and applications Various device can be attached which bandwidths ranging from a few Kbps bits per sec to several Mbps This also supports multiple connections at the same time up to 127 physical devices including USB hub USB architecture can be used for real time data transfer such as audio and video with Isochronous transfer On the other hand asynchronous transfer type is supported over the same set of wires Other merits of USB architecture are listed below Wide range of packet size Wide range of device data rates by accommodating packet buffer size and latencies Error handling fault recovery mechanism built into protocol Support for identification of faulty devices Suitable for development of low cost peripherals Low cost cables and connectors Easy architecture upgrade with multiple USB host controllers in a system ELECTRONICS 10 1 USB CONTROLLER 10 2 FEATURES Important features of the S3C2510 USB block are as follows e Fully Compliant to USB 1 1 Specification e Supports Only Full Speed Function 12Mbps e Complete Device Configuration e Compatible with both and Intel UHCI Standards e Support 5 Endpoints Control 2 Interrupt 2 Data Endpoints e EPO 64 Bytes Control Status Endpoint e 1 2 32 Bytes Interrupt Endpoint In Out e 4 64 Bytes Data Endpoints In Out e 32 64 Byte Data End
309. anness Byte Half Word Selection 310 5 USe OF RAD Ec 10 ADORNS v E 3 10 7 Instruction Cycle Times 3 10 8 Assembler 3 11 Block Data Transfer LDM 6 nsns ren nnn 3 11 1 The Register 3 11 2 Addressing 3 11 3 Address Alignment 3 11 4 Use of the S Bit 00000000 ness a nnns 3 11 5 Use of R15 as the Base n 3 11 6 Inclusion of the Base in the Register Beds PD ata ADOMS A aE 3 11 8 Instruction Cycle Times 200000000 3 11 9 Assembler SYNtax 3 12 Single Data Swap SWP 5 3 12 1 165 fcc TL CAA BRE BEIE MEM 3 12 4 Instruction Cycle 3 12 5 Assembler 0 3 13 Software Interrupt SWI n 3 13 1 Retu
310. ansmit FIFO 19 Receive FIFO Reset RFRST 0 Normal operation 1 Reset Receive FIFO 21 20 Transmit FIFO Trigger Level TFTL 00 30 32 byte data 01 24 32 byte data 10 16 32 byte data 11 8 32 byte data empty Tx data TxFIFO depth 23 22 Receive FIFO Trigger Level RFTL 00 1 32 byte data 01 8 32 byte data 10 18 32 byte data 11 28 32 byte data valid Rx data RxFIFO depth 24 Data Terminal Ready to pin DTR 0 UnDTRO UnDTR 1 goes high level 1 UnDTRO UnDTR 1 goes low level 25 Request To Send to pin RTS 0 UnRTSO UnRTS 1 goes high level 1 UnRTSO UnRTS1 goes low level 27 26 Reserved This bit should be cleared 28 Hardware Flow Control Enable HFEN 0 Disable Hardware Flow Control 1 Enable Hardware Flow Control 29 Software Flow Control Enable SFEN 0 Disable Software Flow Control 1 Enable Software Flow Control 30 Echo Mode ECHO 0 Normal 1 ECHO mode 31 RTS RTR selection RTS RTR 0 RTS 1 Figure 14 2 High Speed UART Control Register Continued 14 8 ELECTRONICS S3C2500B SERIAL HIGH SPEED UART 14 3 2 HIGH SPEED UART STATUS REGISTERS Table 14 5 High Speed UART Status Registers HUSTAT 0 0070004 R W High Speed UART status register 0080004 Table 14 6 High Speed UART Status Register Description Receive Data Valid RDV Break Signal Detected BKD Frame Error FER Parity Error PER ELECTRON
311. ansmit receive e Insertion of one or two Stop bits per frame e Selectable 5 bit 6 bit 7 bit or 8 bit data transfers e Parity checking SIO unit has a baud rate generator transmitter receiver and a control unit as shown in Figure 13 1 The baud rate generator can be driven by the internal system clock PCLK2 or by the external clock EXT_UCLK The transmitter and receiver blocks have independent data registers and shifters Transmit data is written first to the transmit data register From there it is copied to the transmit shifter and then shifted out by the transmit data pin CUTXD Receive data is shifted in by the receive data pin CURXD It is then copied from the shifter to the receive data register when one data byte has been received The SIO control unit provides software controls for mode selection and for status and interrupt generation In S3C2500B software flow control can be selected according to the application The SIO control unit supports echo mode Received data from CURXD send to not only CURXBUF but also CUTXD This mode is for test only ELECTRONICS 13 1 SERIAL CONSOLE UART S3C2500B Transmit Data Register CUTXBUF Baud Rate Divisor ED Transmit Shift Register Baud Rate Generator IR TX Encoder UART Control Register CUCON UART Interrupt Enable CUINT UART Status Register CUSTAT Control Character1 2 CUCHAR 1 2 Receive Data Register CURXBUF Receive Shift Register
312. are defined in Table 3 2 This instruction performs a branch by copying the contents of a general register Rn into the program counter PC The branch causes a pipeline flush and refill from the address specified by Rn This instruction also permits the instruction set to be exchanged When the instruction is executed the value of Rn 0 determines whether the instruction stream will be decoded as ARM or THUMB instructions 28 27 24 23 20 19 16 15 12 11 EEE KS 3 0 Operand Register If bitO of Rn 1 subsequent instructions decoded as THUMB instructions If bitO of Rn 20 subsequent instructions decoded as ARM instructions 31 28 Condition Field Figure 3 2 Branch and Exchange Instructions 3 3 1 INSTRUCTION CYCLE TIMES The BX instruction takes 2S 1N cycles to execute where 5 and are defined as sequential S cycle and non sequential N cycle respectively 3 3 2 ASSEMBLER SYNTAX BX branch and exchange BX cond Rn cond Two character condition mnemonic See Table 3 2 Hn is an expression evaluating to a valid register number 3 3 3 USING R15 AS AN OPERAND If R15 is used as an operand the behaviour is undefined ELECTRONICS 3 5 INSTRUCTION SET Examples 3 6 ADR Into THUMB 1 BX RO CODE16 Into_THUMB ADR R5 Back to ARM BX R5 ALIGN CODE32 Back to ARM S3C2500B Generate branch target address and set bit high hence arrive in
313. are set together To reset these pointers you write 1 to either the TxABT bit or the TxRS bit in the HCON register In DMA mode when the DMA controller writes data to the HTxFIFO Tx buffer descriptor Buffer Length field value must be pre set However if the Last bit is set in buffer descriptor the last byte pointer in HTxFIFO is also set This means the last byte of the frame is in HTxFIFO If the transmitted frame is longer than the Buffer Length field value the last byte pointer will not be set and the next buffer descriptor having the last byte pointer bit will be used The pointers continue shifting through the FIFO When the transmitter detects a positive transition in the data valid pointer at the last location of the FIFO it initiates a frame with an opening flag When it detects a negative transition in the last byte pointer at the last location of the FIFO it closes the frame appending the CRC and a closing flag follows The status of the Tx FIFO is indicated by the transmitter FIFO register available TxFA status bit When TxFA 1 the Tx FIFO is available for loading data data can be loaded into it This function is controlled by the Tx4WD bit The HTxFIFO is reset by writing a 1 to the Tx reset or the TxABT bit or by the nRESET During a reset operation the TxFA status bit is suppressed and data loading is inhibited TxFIFO Data Valid 4 bit Last 1 bit NoCRC Preamble Tx Data Figure 8 17 HDLC Tx FI
314. ase the transmitter block is cleared except for the HTxFIFO and the status bits associated with transmit operation are cleared Data cannot be loaded into the HTxFIFO If this bit is set to 1 the idle pattern is sent continuously In this case the data can be loaded into HTxFIFO and then sent operation are cleared Data cannot be received If this bit is set to 1 the flag pattern is detected In this case the data received can be loaded into the HRXFIFO and moved to system memory DMA Tx enable DTxEN The DTxEN bit lets the HDLC Tx operate on a bus system in DMA mode When DMA Tx is enabled an interrupt request caused by TxFA status is inhibited and the HDLC does not use the interrupt request to request a data transfer DMA Tx monitors the HTxFIFO and fills the HTxFIFO This 4 5 6 5 Rx enable RxEN When the RxEN bit is 0 the receiver enters a disabled state and can not detect the flag pattern if any In this case receiver block is cleared except for the HRXFIFO and the status bits associated with receiver bit is auto disabled when Tx underrun occurs or CTS lost or next buffer descriptor pointer reach null or the owner bit is not DMA mode when DTxSTSK bit is set If Tx underrun occurs DTxABT in HSTAT bit set and abort signal sended If CTS lost occurs DTxABT bit set and TxD output goes high state as long as CTS remains high level 8 30 ELECTRONICS S3C2500B HDLC CONTROLLER Table 8 10 HCON R
315. at reset Table 2 11 Write Buffer Control Register RegisierBns e wrebuferconrobi B de fordamarea Write buffer control bit dO for data area 0 2 16 1 6 Register 5 Instruction and data space protection registers These registers contain the access permission bits for the instruction and data protection regions The opcode 2 field determines whether the instruction or data access permissions are programmed If the opcode 2 field 0 the data space bits are programmed For example MCR p15 0 Rd c5 c0 0 Write data space access permissions MCR p15 0 Rd c5 c0 0 Read data space access permissions If the opcode 2 field 1 the instruction space bits are programmed For example MCR p15 0 Rd c5 c0 1 Write instruction space access permissions MRC p15 0 Rd c5 c0 1 Read instruction space access permissions ELECTRONICS 2 25 PROGRAMMER S MODEL S3C2500B Each register contains the access permission bits apn 1 0 for the eight areas of instruction or data memory as shown in Table 2 12 All defined bits in the control register are set to zero at reset Table 2 12 Protection Space Register Format Register Bits se The values of the lapn 1 0 and Dapn 1 0 bits define the access permission for each area of memory The encoding is shown in Table 2 13 NOTE On reset the values of the lapn 1 0 and Dapn 1 0 bits for all areas are undefined However as on reset the pro
316. ata available bit RxFA is 1 the CPU can read the data from the HRXFIFO If the CPU reads normal data or address data from the HRXFIFO the RxFA bit is automatically cleared In CRC mode the 16 bits preceding the closing flag are regarded as the FCS and checked by hardware and they are transferred to the HRXFIFO Also in no CRC mode without the hardware checking all data bits preceding the closing flag are transferred to the HRXFIFO When the closing flag is sent to the receiver the frame is terminated Whatever data is present in the most significant byte of the receiver the shift register is right justified and transferred to the HRXFIFO The frame boundary pointer which is explained in the HRXFIFO register section is set simultaneously in the HRXFIFO When the last byte of the frame appears at the 1 word or 4 word boundary location of the HRXFIFO depending on the settings of the Rx4WD control bit the frame boundary pointer sets the frame valid status bit if the frame is completed with no error or the RxCRCE status bit if the frame was completed but with a CRC error If the frame reception is completed an RxCRCE interrupt for a frame error or an RxFV interrupt for normal state is generated At this point the CPU can read the Rx remaining bytes RxRB status bits to know how many bytes of this frame still remain in the HRXFIFO When you set the frame discontinue control bit the incoming frame discard control bit to 1 the recei
317. ate on the bus it can generate another start condition and address another slaves without first generating a stop condition This feature supports the use of various combinations of read write formats for data transfers Multiple byte master receiver format afa ome s mv Multiple byte master transmitter format fafa oeren AP NOTE 5 Start W Write bit value is 0 R Read bit value is 1 P Stop A Acknowledge The ACK is first sent from the slave Afterwards the direction depends on the data transfer direction In other words if the mater reads the data it sends the ACK NAK Not Acknowledge Figure 6 5 Data Transfer Format ELECTRONICS 6 7 2 CONTROLLER S3C2500B 6 4 6 4 Addressing The addressing procedure for the is such that the first byte after the start condition determines which slave the master will select Usually this first byte immediately follows the start procedure An exception is the general call address which can address all ICs simultaneously When this address is used all ICs should in theory respond with an acknowledge However ICs can also be made to ignore this address The second byte of the general call address then defines the action to be taken 6 4 6 5 Definition of Bits in the First Data Byte The first seven bits of the first data byte make up the slave address The eighth bit is the LSB or direction bit whic
318. atus bits IN OUT status information and max packet size value for endpoint 2 Table 10 19 USBEP2CSR Register USBEP2CSR 0 0 0020 USB Endpoint 2 Common Status Register 0x00000401 Table 10 20 USBEP2CSR Register Description 2 0 MAXP size value If MAXP 2 0 is 000 then MAXPsize is 0 byte If MAXP 2 0 is 001 then MAXPsize is 8 bytes If MAXP 2 0 is 010 then MAXPsize is 16 bytes If MAXP 2 0 is 011 then MAXPsize is 24 bytes If MAXP 2 0 is 100 then MAXPsize is 32 bytes 6 7 size 0 USBEP2CSR 2 0 isn t overwritten when MCU SETtable writes a 32 bit value to USBEP2CSR register MAXPSET 1 USBEP2CSR 2 0 is overwritten 8 Out mode ISO This bit is valid only when endpoint 2 is set to OUT mode OISO 0 Endpoint 1 will be Bulk mode 1 Endpoint 1 will be ISO mode Default 0 Out mode AuTo This bit is valid only when endpoint 2 is set to OUT CLeaR OATCLR If set whenever the MCU unloads last data in endpoint 1 FIFO OORDY will automatically be cleared without any intervention form MCU Default 0 in out MODE 0 Transfer direction will be OUT selection MODE 1 Transfer direction will be IN Default 1 IN In mode ISO mode This bit is valid only when endpoint 2 is set to IN 150 0 Endpoint 2 will be Bulk mode 1 Endpoint 2 will be ISO mode Default 0 10 30 ELECTRONICS S3C2500B USB CONTROLLER Table 10 20 USBEP2CSR Register Description Continued In mode AuTo R W
319. back to the Low condition if there remains any data to be transmitted in HTxFIFO If nCTS is still High even when nRTS went back to Low not the data in HTxFIFO but a mark idle pattern is transmitted when AutoEn bit set to one ELECTRONICS 8 17 HDLC CONTROLLER S3C2500B TxClock 4 5 12 cycles RTS i CTS Figure 8 9 CTS Delayed on If nCTS remains still High for a while after nRTS enters Low to allow data transmission from HTxFIFO the data transmission starts 5 12 cycles after nCTS is shifted to Low 8 18 ELECTRONICS S3C2500B 8 5 7 MEMORY DATA STRUCTURE The flow control to the HDLC controller uses two data structures to exchange control information and data Each Tx DMA buffer descriptor has the following elements Each Rx DMA buffer descriptor has the following elements Transmit buffer descriptor Receive buffer descriptor Buffer data pointer Ownership bit Control field for transmitter Status field for Tx Transmit buffer length Buffer data pointer Ownership bit Status field for Rx Accumulated received buffer length for a frame ELECTRONICS HDLC CONTROLLER 8 19 HDLC CONTROLLER S3C2500B 8 5 8 DATA BUFFER DESCRIPTOR Rx BDMA function is enabled by DRxEN bit HCON 7 When Rx BDMA is enabled the BDMA fetches the Rx Buffer Data pointer and Owner bit of the next word Then it checks the Ownership of the Buffer Descriptor If the Owner bit is 1 then B
320. bit If not UART may be stopped Frame Error FER This bit is automatically set to 1 whenever a frame error occurs 13 8 ELECTRONICS S3C2500B SERIAL CONSOLE UART Table 13 5 Console UART Status Register Description Continued 4 Overrun Error OER This bit is automatically set to 1 whenever an overrun error occurs during a serial data receiving operation When CURXBUF has a previous valid data and a new received data is going to be written into CURXBUF 4 is set to 1 If the OER interrupt enable bit CUINT 4 is 1 a interrupt is generated when a overrun error occurs You have to clear this bit by writing 1 to this bit If not UART may be stopped Control Character Detect CUSTAT 5 is automatically set to 1 to indicate that a control character has been received If the interrupt enable bit CUINT 5 is 1 an interrupt is generated when a control character is detected You can clear this bit by writing 1 to this bit NOTE Software flow control mode does not affects Tx Rx operation this bit This bit informs only whether UART receives control character or not Namely if user want to stop Tx Rx operation User must program that routine 10441 Resewed 11 Receiver in idle This bit is only for CPU to monitor the receiver state of console RXIDLE UART The RXIDLE status bit indicates inactive state of CURXBUF Reseved 00202 17 Transmitter Idle TI CUSTATT 1
321. bit 10 7 bit 11 8 bit 14 Infra red mode IR The S3C2500B Console UART block supports infra red IR transmit and receive operations In IR mode the transmit period is pulsed at a rate of 3 16 that of the normal serial transmit rate when the transmit data value in the CUTXBUF register is zero To enable IR mode operation you set CUCON 14 to 1 Otherwise the Console UART operates in normal mode In IR receive mode the receiver must detect the 3 16 pulsed period to recognize a zero value in the receiver data register CURXBUF as the IR receive data When this bit is 0 normal Console UART mode is selected When itis 1 infra red TX RX mode is selected NOTE Changing this bit while transmitting cause one Tx data losing Because level of infra red frame start bit and idle state of normal frame are identically high 835 Reserved 29 Software Flow Control This bit determines whether Console UART select software flow Enable SFEN control or not If you set CUCON 29 to 1 Console UART will act in software flow control In this mode you have to use Control Character register 30 Echo Mode Enable If you set CUCON 30 to 1 RX data is sent not only CURXBUF ECHO but also TX port directly so CUTXBUF data will not be transmitted 81 ELECTRONICS 13 5 SERIAL CONSOLE UART S3C2500B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 L H 1 0 SIO transmit mode
322. bit is valid only when endpoint 2 is set to IN run IUNDER ISO The USB sets this bit when in ISO mode an IN token is received and the IINRDY bit is not set The USB sends a zero length data packet for such conditions and the next packet that is loaded into the FIFO is flushed 24 In mode IN packet This bit is valid only when endpoint 2 is set to IN ReaDY IINRDY The MCU sets this bit after writing a packet of data into the FIFO The USB clears this bit once the packet has been successfully sent to the host An interrupt is generated when the USB clears this bit so the MCU can load the next packet While this bit is set the MCU will not be able to write to the FIFO If the SEND STALL bit is set by the MCU this bit 10 32 ELECTRONICS S3C2500B USB CONTROLLER Table 10 20 USBEP2CSR Register Description Continued 27 In mode Fifo This bit is valid only when endpoint 2 is set to IN FLUSH IFFLUSH The MCU sets this bit if it intends to flush the IN FIFO This bit is cleared by the USB when the FIFO is flushed The MCU is interrupted when this happens If a token is in progress the USB waits until the transmission is complete before the FIFO is flushed If two packets are loaded into the FIFO only the top most packet one that was intended to be sent to the host is flushed and the corresponding IINRDY bit for that packet is cleared 28 In mode SenD This bit is valid only when endpoint 2 is set to IN STALL The M
323. ble 1 3 S3C2500B System Configuration RW System configuraionregister POCODE oxF0000004 Product code and revision number register 025000000 ooo Cock status register Table 1 4 S3C2500B Memory Controller Table 1 5 S3C2500B SDRAM Controller aii CFGREG OxF0020000 R W SDRAM Configuration register 0 00099 0 CMDREG 0020004 R W SDRAM Command register 0x00000000 REFREG 0 0020008 Refresh timer register 0x00000020 WBTOREG 0 002000 Write buffer time out register 0x00000000 mE 1 32 ELECTRONICS S3C2500B PRODUCT OVERVIEW Table 1 6 S3C2500B IIC Controller IICCON 0xF00F0000 0x00000000 IICBUF 0 00 0004 R W Shift buffer register Undefined IICPS 0xF00F0008 0x00000000 IICCNT 0xF00F000C 0x00000000 IICPND OxFO0F0010 R W Interrupt pending register 0x00000000 Table 1 7 S3C2500B Ethernet Controller 0 Registers Address Reset Value BDMATXCONA 000000000 BDMARXCONA 000000000 BDMATXDPTRA 000000000 BDMARXDPTRA 000000000 BTXBDCNTA 000000000 BRXBDCNTA 000000000 BMTXINTENA 0x00000000 BMRXINTENA 000000000 BMTXSTATA 000000000 BMRXSTATA 000000000 BDMARXLENA 000000000 CFTXSTATA _ control frame status 00000 MACCONA 000000000 CAMCONA 000000000 MACTXCONA 000000000 MACTXSTATA 000000000 MACRXCONA 000000000 MACRXSTATA 000000000 STADATAA 0x00000000 STACONA 0x00006000 CAMEN
324. ble CRC No CRC mode e Automatic CRC generator preset e Digital PLL block for clock recovery e Baud rate generator e NRZ NRZI FM Manchester data formats for Tx Rx and auto echo mode Tx and Rx clock inversion e Tx and Rx FIFOs with 8 word 8 x 32 bit depth e Selectable 1 word or 4 word data transfer mode for Tx Rx e Data alignment logic e Endian translation e Programmable interrupts e Modem interface e Hardware flow control e Buffer descriptor for Tx Rx e Three channel DMA Controller Three channels for HRXFIFO Single or 4 word 4 x 32 bit burst transfer mode Maximum frame size allows for up to 64K bytes e Upto 10 Mbps full duplex operation using an external internal clock e HDLC frame length based on octets 8 2 ELECTRONICS S3C2500B HDLC CONTROLLER 8 3 FUNCTION DESCRIPTIONS Figure 8 1 shows the HDLC module s function blocks These function blocks are described in detail in the following sections Tx FIFO FCS Generator 8 Words Address DMA Controlller Flag Abort Idle Zero Generateor and C Transmitter nsertion HDLC Control and Status poa Idle Registers etection Zero Control FCS Checker gt Delection Data Bus Arbiter Controller autoecho o lt a 3 UJ C eues Receive shift Register Rx FIFO dplloutR DPLL 8 words dplloutT brgout1 Address brgout2 BRG Figure 8 1 HDLC Module Block Diagram ELEC
325. ble Register 0X00000000 HINTENB OxF011000C HDLC Interrupt Enable Register 0X00000000 HINTENC 0xF012000C HDLC Interrupt Enable Register 0X00000000 Table 8 14 HINTEN Register Description Number te Reseved Reseved fg fe 251 Reseved DPLL clocks missing interrupt enable 8 42 ELECTRONICS S3C2500B HDLC CONTROLLER 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 m omnx UO m 02 x U m Ox m OOUO0 x 2 m GQ 4 m 0 00 x 3 0 Reserved 4 Tx frame complete interrupt enable TxFCIE 5 Tx FIFO available to write interrupt enable TxFAIE 6 Reserved 7 CTS transition has occurred interrupt enable TxSCTIE 8 Transmit underrun has occured interrupt enable TxUIE 9 RxFIFO available to read interrupt enable RxFAIE 10 Tx Frame Good Interrupt enable TxFGIE 11 Flag detected interrupt enable RxFDIE 12 Reserved 13 DCD transition interrupt enable RXSDCDIE 14 Valid frame interruopt enable 15 Idle detected interruot enable RxIDLEIE 16 Abort detected interrupt enable RxABTIE 17 CRC error frame interrupt enable RXCRCEIE 18 Non dctet aligned frame interrupt enable RXNOIE 19 Rx overrun interrupt enable RxOVIE 20 Reserved 21 Reserved 22 DMA Tx abort interrupt enable DTxABTIE 23 Rx internal error interrupt enable RXIERRIEN
326. byte half word and word transaction e CAS latency can be 1 20r 3 e Provides auto refresh and self refresh mode to sustain the contents of SDRAM memory 5 38 ELECTRONICS S3C2500B MEMORY CONTROLLER 5 7 2 SDRAM SIZE AND CONFIGURATION The SDRAM controller supports a SDRAM memory ranging from 2 to 256M byte Table 5 19 Illustrates the supported SDRAM configurations when external bus width is 32 bits Table 5 20 Illustrates the supported SDRAM configurations when external bus width is 16 bits If 16M bit device which has two leaves is used only ADDR 13 is used to select a leaf If SDRAM device which has four leaves is used both ADDR 14 and ADDR 13 are used to select a leaf Only the chip select signals nSDCS 1 0 are to select a bank The other SDRAM control signals are common to both banks ELECTRONICS 5 39 MEMORY CONTROLLER S3C2500B Table 5 19 Supported SDRAM Configuration of 32 bit External Bus Banks Address Size Leaf Select Total Technology Arrangement Memory Size Row ADDR 14 ADDR 13 Byte 16M bit 2M x8 HADDR 21 bi 1 2 1 HADDR 21 2 64M bit 8M x 8 1 pt Ls 4M x 16 1 a r 2M x 32 1 1 2 1 2 1 2 1 2 1 2 1 2 8 HADDR 22 HADDRI21 32M HADDR 22 HADDR 21 HADDR 22 HADDR 21 10 HADDR 22 HADDR 21 HADDR 22 HADDR 21 HADDR 22 HADDR 21 BENE E 10 HADDR 22 HADDR 21 HADDR 22 HADDR 21 HADDR 22 HADDR 21 4M x 32 256M bi
327. can also be compared against or added to Lo register values with the CMP and ADD instructions For more information refer to Figure 3 34 2 8 THE PROGRAM STATUS REGISTERS The ARM9TDMI contains a Current Program Status Register CPSR plus five Saved Program Status Registers SPSRs for use by exception handlers These register s functions are Hold information about the most recently performed ALU operation Control the enabling and disabling of interrupts Set the processor operating mode The arrangement of bits is shown in Figure 2 6 Condition Code Flags Reserved Control Bits 7 7 1 31 30 29 28 27 26 25 24 Mode bits Carry Borrow Extend State bit Overflow Zero FIQ disable Negative Less Than FRQ disable Figure 2 6 Program Status Register Format 2 8 ELECTRONICS S3C2500B PROGRAMMER S MODEL 2 8 1 THE CONDITION CODE FLAGS The N Z C and V bits are the condition code flags These may be changed as a result of arithmetic and logical operations and may be tested to determine whether an instruction should be executed In ARM state all instructions may be executed conditionally see Table 3 2 for details In THUMB state only the branch instruction is capable of conditional execution see Figure 3 46 for details 2 8 2 THE CONTROL BITS The bottom 8 bits of a PSR incorporating 1 F T and M 4 0 are known collectively as the control bits These will change when an exception a
328. ceive FIFO top or HURXBUF 1 Break Signal Deteced BKD 0 No Break Signal Receive FIFO top or HURXBUF 1 Break received 2 Frame Error FER 0 No Frame Error Receive FIFO top or HURXBUF 1 Frame Error occured 3 Parity Error PER 0 No Frame Error Receive FIFO top or HURXBUF 1 Frame Error occured ZOUOUcr r Tm lt 02 4 Overrun Error OER 0 No Overrun Error Receive FIFO top or HURXBUF 1 Overrun Error occured 5 Control Character Detect CCD 0 No Control Character Receive FIFO top or HURXBUF 1 Control character present Receive FIFO top HURXBUF 6 Data Carrier Detect Lost DCDL 0 DCD pin is Low at the receiver checking time 1 DCD pin is High at the receiver checking time 7 Receive FIFO Data Trigger Level Reach RFREA 0 No valid data in HURXBUF or Not reached to trigger level 1 In RxFIFO mode RxFIFO has valid data and reach trigger level In non FIFO mode HURXBUF has valid data 8 Receive FIFO Empty RFEMT 0 Receive FIFO is not empty 1 Receive FIFO is empty 9 Receive FIFO Full RFFUL Receive FIFO is not full 1 Receive FIFO is full 10 Receive FIFO Overrun RFOV Receive FIFO is not occured 1 Receive FIFO overrun occured 11 Receiver in IDLE IDLE 0 Receiver is in IDLE state 1 Receiver is in active state Figure 14 3 High Speed UART Status Register 14 12 ELECTRONICS S3C2500B SERIAL HIGH SPEED UART
329. channel is provided with half frequency clock of external clock and the tx data is shifted out every two external clock When the Divide bit in TSAxCON is 0 each HDLC channel is provided with the external clock and the tx data is shifted out every one clock 9 10 ELECTRONICS S3C2500B IOM2 CONTROLLER 9 5 IOM2 SPECIAL REGISTERS Table 9 2 IOM2 Special Registers RW ELECTRONICS 9 11 IOM2 CONTROLLER S3C2500B 9 5 1 IOM2CON REGISTER Table 9 3 IOM2CON Register Control Register RW IOM2CON 0 0130000 Control Register 0x00000000 2 Enable IOM2EN 0 Disable 1 Enable 1 Data Bus Reverse DBREV 0 DD downstream DU upstream 1 DD upstream DU downstream Monitor Channel Enable MEN 0 Monitor channel is disabled 1 Monitor channel transmission is allowed TIC Bus Enable TICEN 0 TIC bus access is disabled 1 TIC bus access is enabled D Channel Collision Control Enable 0 Ignore the echo bit DCOLEN 1 i The echo bit from the transceiver is compared to detect D channel collision 0 auto cleared after transmitting MR abort 1 The remote transmitter is forced to abort the current transmission This enforces the local receiver to set the MR bit to 1 0 cleared before the first byte is received 1 The CPU indicates the monitor receiver that the first byte address received is valid 7 Monitor Channel Sends End of 0 cleared after the EOM is sent 1 The monitor transmitter
330. character in RO bits 0 7 Restore workspace and return restoring processor mode and flags ELECTRONICS S3C2500B INSTRUCTION SET 3 14 COPROCESSOR DATA OPERATIONS CDP The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 25 This class of instruction is used to tell a coprocessor to perform some internal operation No result is communicated back to ARM9TDMI and it will not wait for the operation to complete The coprocessor could contain a queue of such instructions awaiting execution and their execution can overlap other activity allowing the coprocessor and ARM9TDMI to perform independent tasks in parallel 3 14 1 COPROCESSOR INSTRUCTIONS The S3C2500B unlike some other ARM based processors does not have an external coprocessor interface It does not have a on chip coprocessor also So then all coprocessor instructions will cause the undefined instruction trap to be taken on the S8C2500B These coprocessor instructions can be emulated by the undefined trap handler Even though external coprocessor can not be connected to the S3C2500B the coprocessor instructions are still described here in full for completeness Remember that any external coprocessor described in this section is a software emulation 28 27 24 23 20 19 16 15 12 11 7 5 4 3 Du pee om D 3 0 Coprocessor operand register 7 5 Cop
331. ction is copied into the Link Register that is current PC 4 or PC 8 depending on the exception See Table 2 2 on for details If the exception has been entered from THUMB state then the value written into the Link Register is the current PC offset by a value such that the program resumes from the correct place on return from the exception This means that the exception handler need not determine which state the exception was entered from For example in the case of SWI MOVS PC R14 svc will always return to the next instruction regardless of whether the SWI was executed in ARM or THUMB state Copies the CPSR into the appropriate SPSR Forces the CPSR mode bits to a value which depends on the exception Forces the PC to fetch the next instruction from the relevant exception vector It may also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions If the processor is in THUMB state when an exception occurs it will automatically switch into ARM state when the PC is loaded with the exception vector address 2 9 2 ACTION ON LEAVING AN EXCEPTION On completion the exception handler 1 Moves the Link Register minus an offset where appropriate to the PC The offset will vary depending on the type of exception Copies the SPSR back to the CPSR Clears the interrupt disable flags if they were set on entry NOTE An explicit switch back to THUMB state is never needed since restoring the CPSR from the SP
332. cycle delay for synchronization is incurred before the interrupt can affect the processor flow Irrespective of whether the exception was entered from ARM or Thumb state a FIQ handler should leave the interrupt by executing SUBS PC R14 10 44 FIQ may be disabled by setting the CPSR s F flag but note that this is not possible from User mode If the F flag is clear ARM9TDMI checks for a LOW level on the output of the FIQ synchroniser at the end of each instruction 2 12 ELECTRONICS S3C2500B PROGRAMMER S MODEL 2 9 5 IRQ The IRQ Interrupt Request exception is a normal interrupt caused by a LOW level on the nIRQ input IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered It may be disabled at any time by setting the bit in the CPSR though this can only be done from a privileged non User mode Irrespective of whether the exception was entered from ARM or Thumb state an IRQ handler should return from the interrupt by executing SUBS PC R14 4 2 9 6 ABORT An abort indicates that the current memory access cannot be completed It can be signalled by the external ABORT input ARM9TDMI checks for the abort exception during memory access cycles There are two types of abort Prefetch abort occurs during an instruction prefetch Data abort occurs during a data access If a prefetch abort occurs the prefetched instruction is marked as invalid but the exception will not be taken un
333. cycles 11 CL 3 cycles R 7 6 SDRAM device Density of bank 0 00 16M bit SDRAM memory devices 01 64M bit SDRAM memory devices 10 2 128M bit SDRAM memory devices 15 12 Row Cycle 0000 RC 1 cycles 1110 RC 15 cycles W P L 11 256M bit SDRAM memory devices DO 1 0 D 11 10 RAS to CAS delay 00 RCD 1 cycle 10 RCD 3 cycles C 12 RAS 19 16 Row Active time 0000 RAS 1 cycles 1110 RAS 15 cycles 01 RCD 2 cycles 11 2 RCD 4 cycles 1001 1001 0001 RC 2 cycles 1111 2 RC 16 cycles 0001 RAS 2 cycles 1111 RAS 16 cycles 08120 HEN NOTES 1 Software should not write to configuration register when the SDRAM engine is busy The SDRAM engine status bit BUSY in command register can be used to check if the control engine is idle 2 We recommend that the auto pre charge should be disabled by asserting 1 on the Reg0 when the page hit ratio is more than 50 5 48 ELECTRONICS S3C2500B MEMORY CONTROLLER 31 20 19 16 15 1211109 8 7 6 5 4 3 2 1 e R 0 eXternal data bus Width XW 0 external bus width is 32 bit 1 external bus width is 16 bit 1 Auto Pre charge control for SDRAM accesses AP 0 Auto pre charge 1 No auto pre charge 3 2 CAS Latency CL 00 Reserved 01 1 cycles 10 2 cycles 11 3 cycles 5 4 SDRAM device Density of bank 1 D1 00 16 Mbit SDRAM memory devices 01 64 Mbit
334. d Data Downstream DD In terminal mode a device may be required to transmit both upstream and downstream based on which channel is being transmitted at any one time As a result the actual data pins of the S3C2500B 2 interface need to be both inputs and outputs When the DBREV bit in IOM2CON is set the DU pin is used to receive downstream data and the DD pin is used to send upstream data 9 3 7 8 Strobe Signals The optional 2 signals BCL and STRB are used by 2 devices on the IOM2 bus BCL is 1x clock running at 768 kHz and used as the data clock STRB is used to specify a strobe of an appropriate time slot for 2 device The start and stop position of STRB is programmed by IOM2STRB register 9 8 ELECTRONICS S3C2500B IOM2 CONTROLLER 9 4 TSA TIME SLOT ASSIGNER 9 4 1 OVERVIEW The S3C2500B includes three time slot assigners TSA which provide flexible data path control between the three HDLCs and external interfaces A variety of data interface can be supported by the S3C2500B with the TSA raw Data Communication Equipment DCE Pulse Code Modulation PCM highway non multiplexed mode and multiplexed mode and ISDN Oriented Modular Interface 2 Each TSA can be programmed to select one between DCE and PCM highway non multiplexed interface Besides DCE PCM highway interface can afford IOM2 interface to multiplex data from each HDLC channel on HDLCA pad interface and interface B ca
335. d HDLC Controller 2 The S3C2500B can program the bus priority of each bus masters among Group B So the bus priority of bus masters in only Group B can be programmed Group C has the ARM940T CPU The relative priority of Group B and Group C is determined more or less in an alternating manner The local priority of six channels of general DMA can be programmed by fixed priority or round robin priority in similar manner to the AHB bus priority Please refer to the general DMA chapter Table 4 2 AHB Bus Priorities for Arbitration Function Block AHB Bus Priority Group Test Interface Controller TIC Group A highest priority 4 4 ELECTRONICS S3C2500B SYSTEM CONFIGURATION General DMA Ethernet HDLC Controller 0 Controller 2 Ethernet HDLC Controller 1 Controller 1 HDLC Controller 0 Figure 4 3 Priority Groups of S3C2500B AHB Bus Programmable Priority Register are HPRIF Programmable Priority Register for Fixed HPRIR Programmable Priority Register for Round Robin If system configuration register OxF0000000 SYSCFG 0 0x1 the programmable fixed priority is run by HPRIF register Each Master has its own fixed priority index For example has the index 0 The reset value of HPRIF register is 0x00543210 The first field of HPRIF 3 0 indicates the highest priority So the GDMA has the highest AHB master when SYSCFG 0 0x1 and the HPRIF has the reset value For example SYSCFG 0 0x1 and the HPRIF is
336. d TOFB I TDEA output feedback mode of operation interleaved But in the S3C2500B two modes are supported TECB and TCBC The DES 3DES of S3C2500B supports byte swapping function for DESINFIFO DESOUTFIFO IV and KEYs 11 2 FEATURES e DES or Triple DES Mode e ECB or CBC Mode e Encryption or Decription Support e General DMA Support ELECTRONICS 11 1 DES 3DES S3C2500B PWDATA Register key write sig PENABLE Add decode FSM state left side data machine Control in mode sig PSELx PWRITE Ges mods left side data Interrupt PRDATA enable wr indata Status lt 5 state left side data machine in mode sig PW IV indata register right side data outdata dreg64 register left side data DESOUTFI FO 20 60 DES 3DES cycle 1 2 cycle Figure 11 1 DES 3DES Block Diagram 11 2 ELECTRONICS S3C2500B DES 3DES 11 3 DES 3DES SPECIAL REGISTERS Table 11 1 DES 3DES Special Registers Overview DESSTA JoxFo0g0004 DESGDESsusregster 000000231 DESKEY1L 0xF0090010 RW Key 1 left half 0x00000000 Key 1 is the security key for DES the 1 DES of 3DES in the encryption mode or 3 DES 3DES in the decryption mode DESKEY1R OxF0090014 Key 1 right half 0x00000000 DESKEY2L OxF0090018 R W Key 2 left half 0x00000000 Key 2 is the security key for the 2 DES of 3DES DESKEY2R 0 009001 Key 2 right half 0x00000000 DESKEY3L 00
337. d burst mode Tx4WD 0 1 word mode selected 1 4 word mode selected 11 Rx 4 word burst mode Rx4WD 0 1 word mode selected 1 4 word mode selected 13 12 Rx widget algnment RxWA 00 No invalid byte 01 1 invalid byte 10 2 invalid byte 11 invalid byte 14 DMA Tx stop or skip DTxSTSK 0 Tx stops when not owner bit is set 1 Tx skips when not owner bit is set 15 DMA Rx stop or skip DRxSTSK 0 Rx stops when not owner bit is set 1 Rx skips when not owner bit is set 16 DMA Rx memory address decrement DRXMADEC 0 Address is incremented 1 Address is decremented 17 Tx flag idle TxFLAG 0 Enter mark idle mode a bit pattern of consecutive ones 1 Enter time fill mode a bit pattern of consecutive opening closing flag as in string 01111110 01111110 Figure 8 14 HDLC Control Register HCON ELECTRONICS S3C2500B HDLC CONTROLLER 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 2 m 2 4 18 Tx single flat TXSFLAG 0 Double flag mode a closing amp opening flags are used to separate frames 1 Single flag mode only one flags are used to separate frames 19 Tx loop back mode TxLOOP 0 Normal operation 12 The tramsmit data output is internally connected to the receiver data input for self testing 20 Rx echo mode RX
338. d by Interrupt enable register 14 4 4 AUTO BAUD RATE DETECTION To use Auto Baud Rate Detection Set ABB AutoBaud rate Boundary ABT AutoBaud rate Table Register and Auto Baud Detect bit AUBD HUCON 6 When level is low High Speed UART counts low level of start signal and rewrites counting value of low level by comparing ABB ABT Register This automatically corrects Baud Rate CNTO and CNT1 14 26 ELECTRONICS S3C2500B SERIAL HIGH SPEED UART TRANSMIT lt RECEIVE gt RX DATA Data Bits 5 8 Data Bits INT RXD A HURXBUF Receive Data Receive Data Figure 14 19 Interrupt Based Serial Transmit and Receive Timing Diagram ELECTRONICS 14 27 SERIAL I O HIGH SPEED UART S3C2500B lt TRANSMITTER gt Select DMA Mode TX DATA eee 12 uart_tx_req uart_tx_ack Figure 14 20 DMA Based Serial I O Timing Diagram Tx Only RECEIVER gt lt Select DMA Mode RX DATA Start Data Bits 5 8 es Start Data Bits HU RXBUF Previous Receive Data Valid Receive Data uart rx req A uart rx ack A Figure 14 21 DMA Based Serial 1 Timing Diagram Rx Only 14 28 ELECTRONICS S3C2500B SERIAL HIGH SPEED UART SIO Frame Data Bits Figure 14 22 Serial Frame Timing Diagram Normal High Speed UART IR Transmit Frame Data Bits Bit frame T 7 16 6 16 Figure 14 23 Infra Red Transmit Mode Frame Timing Diagram ELECTRONICS
339. d only bit NOTE To ensure the reliability of GDMA operations the GDMA control register bits must be configured independently and carefully If you want four bust mode DCON 5 you should set both SD DCON 9 8 DD DCON 11 10 to 00 increase But SD DCON 9 8 and DD DCON 11 10 can be 10 fixed only for USB endpoints software mode and DES IN OUT FIFO DES mode when four burst mode DCON 5 is set 12 10 ELECTRONICS S3C2500B GDMA CONTROLLER 131211109 8 7 6 5 4 3 RESERVED AZO 0 Run enable RE 0 Disable operation 1 Enable operation 3 1 Mode selection MODE 000 Software mode Memory to Memory or Momory to from USB 001 External Request mode for external devices 010 HUART TX mode HUART from memory 011 HUART RX mode HUART to memory 100 DES IN mode DES from memory 101 DES OUT mode DES to memory 110 111 Reserved 4 Single block mode SB 0 One initiates a single operation 1 Req initiates a whole operation 5 Four data burst enable FB 0 Disable 4 data burst mode 1 Enable 4 data burst mode 7 6 Transfer size TS 00 Byte 8 bit 01 Half word 16 bit 10 Word 32 bit 11 No use 9 8 Source address direction SD 00 Increase source address 01 Decrease source address 10 Do not change source address fixed 11 Reserved 11 10 Destination address directi
340. data is less than 46 byte long the MAC transmits pad bytes of all zeros Frame check 4 byte The FCS field contains a 16 bit error detection code that is sequence FCS computed as a function of all fields except the preamble the SFD and the FCS itself The FCS 32 polynomial function is as follows X32 X28 X23 4X224 X16 X12 X1 X10 X8 X7 X5 X4 X XI 1 ELECTRONICS 7 37 ETHERNET CONTROLLER Packet Encoded on the Medium Added by Data Frame sent by user Added by transmitter Transmitter Stripped by Data frame delivered to user Optionaly stripped Receiver by receiver Destination Source Length or 46 to 1500 Oto 46 7 bit 6 byte 6 byte 2 byte byte byte 4 byte LLC header LLC information field SNAP ssaP our PD 1 byte 1 byte 1 byte 3 2 byte DSAP Destination service access point SSAP Source service access point CTRL Control field SNAP Subnetwork access protocol OUI Origanizationally unique identifier PID Protocol identifier SFD Starting frame delimiter LLC Logical lick control FCS Frame check sequence Figure 7 5 Fields of an IEEE802 3 Ethernet Frame 7 5 1 1 Options that affect the Standard MAC Frame There are a number of factors and options that can affect the standard MAC frame as described in 2 Some PHYs may deliver a longer or shorter preamble 3C2500B Table 7 Short frame mode permit
341. de routine follows MOV CMP CMPCC MOVCC MOVCC BCC MOV CMP SUBCS ADDCS MOVS MOVNE BNE Div1 Div2 Rent 1 Rb 0x80000000 Rb Ra Rb Rb ASL 1 Rent Rent ASL 1 Div1 0 Ra Rb Ra Ra Rb Rc Rc Rent Rent Rent _SR 1 Rb Rb LSR 1 Div2 Overflow Detection in the ARM9TDMI 1 Overflow in unsigned multiply with a 32 bit result UMULL TEQ BNE Rd Rt Rm Rn Rt 0 overflow 2 Overflow in signed multiply with a 32 bit result SMULL TEQ BNE Rd Rt Rm Rn Rt Rd ASR 31 overflow Enter with numbers in Ra and Rb Bit to control the division Move Rb until greater than Ra Test for possible subtraction Subtract if ok Put relevant bit into result Shift control bit Halve unless finished Divide result in Rc remainder in Ra 3 to 6 cycles 1 cycle and a register 3 to 6 cycles 1 cycle and a register 3 Overflow in unsigned multiply accumulate with a 32 bit result UMLAL TEQ BNE Rd Rt Rm Rn Rt 0 overflow 4 to 7 cycles 1 cycle and a register 4 Overflow in signed multiply accumulate with a 32 bit result SMLAL TEQ BNE 3 60 Rd Rt Rm Rn Rt Rd ASR 31 overflow 5 4 to 7 cycles 1 cycle and a register ELECTRONICS S3C2500B INSTRUCTION SET 5 Overflow in unsigned multiply accumulate with a 64 bit result UMULL i ADDS RI RI Ra1 ADC Rh Rh Ra2 BCS overflow 3 to 6 cycles Lower accumulate Upper accumulate 1 cycle and 2 reg
342. de This bit is valid only when endpoint 4 is set to OUT SenT STALL The USB sets this bit when an OUT token is ended OSTSTALL with a STALL handshake The USB issues a stall handshake to the host if it sends more than MAXP data for the OUT token 23 Out mode CLear This bit is valid only when endpoint 4 is set to OUT data TOGgle When the MCU writes a 1 to this bit the data OCLTOG toggle sequence bit is reset to DATAO 24 In mode IN packet This bit is valid only when endpoint 4 is set to IN ReaDY IINRDY The MCU sets this bit after writing a packet of data into the FIFO The USB clears this bit once the packet has been successfully sent to the host An interrupt is generated when the USB clears this bit so the MCU can load the next packet While this bit is set the MCU will not be able to write to the FIFO If the SEND STALL bit is set by the MCU this bit can not be set 25 In mode fifo Not This bit is valid only when endpoint 4 is set to IN EMPty INEMP Indicate there is at least one packet of data in FIFO if USBEPACSR 25 24 is 10 1 packet IN FIFO 11 2 2 packets of MAXP z 1 2 FIFO or 1 packet of MAXP FIFO size 26 In mode UNDER This bit is valid only when endpoint 4 is set to IN run IUNDER ISO The USB sets this bit when in ISO mode an IN token is received and the IINRDY bit is not set The USB sends a zero length data packet for such conditions and the next packet that is loaded into the FIFO is
343. de with in line sync this register value used for searching sync pattern This sync pattern is used as like opening or closing flag In line sync or out line sync determined by AutoEn bit value If AutoEn bit is set to zero it is determined to in line sync in transparent mode Table 8 23 Synchronization Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 7 0 Sync pattern Figure 8 27 HDLC Synchronization Register ELECTRONICS 8 51 HDLC CONTROLLER S3C2500B 8 7 16 TRANSPARENT CONTROL REGISTER The HDLC transparent register controls the transparent data flow This is composed with Data sampling field and RTS control field Table 8 24 Transparent Control Register Registers Ades RW Description Reset Value TCONA oxFot00040 RAW Transparent Control Register 000000000 Ton RAW Transparent Control Register 000000000 Tcowc ewrotzopic Transparent Control Register 000000000 Bi Number 1 Data sampling These bit values determine which data bits are regarded as valid DS after the nDCD state active 00 the first valid bit is D4 01 the first valid bit is 10 D2 and 11 D1 See Figure 8 28 data sampling method 32 Not applicable RTS control RTS It this bit set to one the nRTS pin goes Low 81 5 Not applicable RxC XOX TX DEX EDK nDCD EER T Z Z Z Sampled here if DS value is 01
344. des the data to be transmitted on the monitor channel selected by MSEL if MEN 1 Gp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 0 7 0 Monitor Channel Transmit Data Figure 9 17 IOM2 Monitor Channel Transmit Data Register 9 5 10 IOM2 MONITOR CHANNEL RECEIVE DATA REGISTER Table 9 14 IOM2MRD 2 Monitor Channel Receive Data Register RW IOM2MRD OxF013002C Monitor Channel Receive Data 0x00000000 7 0 MRxD This field includes the data received on the monitor channel selected by MSEL if MEN 1 This data is sure to be valid by double last look criterion valid during two successive frames Gp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 7 0 Monitor Channel Receive Data Figure 9 18 IOM2 Monitor Channel Receive Data Register 9 22 ELECTRONICS S3C2500B IOM2 CONTROLLER 9 5 11 TSA A CONTROL REGISTER Table 9 15 TSAACON TSA A Control Register TSAACON 0xF0130030 TSA A Control Register 0x00000000 11 0 START The location of start bit of time slot assigned to HDLCA 23 12 STOP The location of stop bit of time slot assigned to HDLCA 25 24 MODE 00 DCE 01 PCM highway non multiplexed 10 IOM2 11 PCM highway multiplexed 26 Divide 0 HDLC clock is the same clock as the external clock 1 HDLC clock is 1 2 times the external clock 127 Peserved 31 30 29 28 27 26 25 24 23 12 11 0 l puo s
345. descending If ascending a STM will go up and LDM down if descending vice versa IA IB DA DB allow control when LDM STM are not being used for stacks and simply mean increment after increment before decrement after decrement before ELECTRONICS 3 45 INSTRUCTION SET Examples LDMFD SP RO R1 R2 STMIA RO RO R15 LDMFD SPI R15 LDMFD SP R15 STMFD R13 RO R14 S3C2500B Unstack 3 registers Save all registers R15 SP CPSR unchanged R15 SP CPSR lt SPSR mode allowed only in privileged modes Save user mode regs on stack allowed only in privileged modes These instructions may be used to save state on subroutine entry and restore it efficiently on return to the calling routine STMED SPI RO RS R14 2 BL somewhere LDMED SP RO R3 R15 3 46 Save to R3 to use as workspace and R14 for returning This nested call will overwrite R14 Restore workspace and return ELECTRONICS S3C2500B INSTRUCTION SET 3 12 SINGLE DATA SWAP SWP 28 27 23 22 21 20 19 16 15 12 11 Lus ww Bie Dow sw I 3 0 Source Register 15 12 Destination Register 19 16 Base Register 22 Byte Word Bit 0 Swap word quantity 1 Swap word quantity 31 28 Condition Field Figure 3 23 Swap Instruction The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 23 T
346. detection of a non idle medium in MII mode CRS 10M is asserted when a 10M bit s PHY has data to transfer A 10M bit s transmission also uses this signal PRODUCT OVERVIEW S3C2500B Table 1 1 S3C2500B Signal Descriptions Continue Group Pin Type PadType Description Ethernet RX CLK 1 1 phis Receive Clock Receive Clock for 10M Controller1 RX CLK is a continuous clock signal Its 18 frequency is 25 MHz for 100 Mbit s operation and 2 5 MHz for 10 Mbit s RXD 3 0 DV and RX ERR are driven by the PHY off the falling edge of and sampled on the rising edge of RX CLK To receive data the RXCLK 10 M clock comes from the 10M bit s PHY RXD1 3 0 4 phis Receive Data Receive Data for 10M RXD 10M RXD is aligned on nibble boundaries RXD 0 corresponds to the first bit received on the physical medium which is the LSB of the byte in one clock period and the fifth bit of that byte in the next clock RXD 10M is shared with RXD 0 and it is a line for receiving data from the 10M bit s PHY RX DV 1 1 phis Receive Data Valid LINK 10M PHY asserts DV synchronously holding it active during the clock periods in which RXD 3 0 contains valid data received PHY asserts RX DV no later than the clock period when it places the first nibble of the start frame delimiter SFD on RXD 3 0 If PHY asserts RX DV prior to the first nibble of the SFD then RXD 3 0 carries valid preamble symbo
347. dpoint number 10 3 7 ISOCHRONOUS TRANSACTIONS In non USB environments isochronous transfers have the general implication of constant rate error tolerant transfers In the USB environment requesting an isochronous transfer type provides the requester with the following Guaranteed access to USB bandwidth with bounded latency Guaranteed constant data rate through the pipe as long as data is provided to the pipe n the case of a delivery failure due to error retrying of the attempt to deliver the data While the USB isochronous transfer type is designed to support isochronous sources and destinations it is not required that software using this transfer type actually be isochronous in order to use the transfer type An isochronous pipe is a stream pipe and is therefore always uni directional An endpoint description identifies whether a given isochronous pipe s communication flow is into or out of the host If a device requires bi directional isochronous communication flow two isochronous pipes must be used one in each direction 10 3 8 INTERRUPT TRANSACTIONS The interrupt transfer type is designed to support those devices that need to send or receive small amounts of data infrequently but with bounded service periods Requesting a pipe with an interrupt transfer type provides the requester with the following Guaranteed maximum service period for the pipe Retry of transfer attempts at the next period in the
348. e channel carries the commands and indications between the S3C2500B and layer 1 device to control the activation deactivation procedures 10 channel access may be arbitrated via in the TIC bus access protocol The CPU have access to channel by using two registers IOM2CITDO in transmit direction and IOM2CIRDO in receive direction The data written to IOM2CITDO is continuously transmitted until new data is to be sent The 2 receiver generates interrupt whenever the receive data changes and is stable for two frames double last look criterion The 1 channel carries the real time status information between the S3C2500B and 2 devices other than layer 1 device The C I1 channel is accessed via IOM2CITD1 and IOM2CIRD1 9 6 ELECTRONICS S3C2500B IOM2 CONTROLLER 9 3 7 5 TIC Bus Access The bus capability enables more than one device to access 2 bus The arbitration mechanism is implemented in the last byte of channel2 of IOM2 interface This allows external communication controllers up to 7 to access the and D Channel in the channelO of IOM2 interface The TIC bus access is enabled by setting the TICEN to 1 An access request to the TIC bus may either be generated by the software CPU access to the C I channel or by the HDLC controller transmission of HDLC frame in the D channel A software access request to the bus is activated by setting the BREQ bit to 1 In the case of an access reque
349. e FIFO 19 Out mode Data This bit is valid only when endpoint 3 is set to OUT ERRor ODERR ISO This bit should be sampled with OORDY When set it indicates the data packet due to be unloaded by the MCU has an error either bit stuffing or CRC If two packets are loaded into the FIFO and the second packet has an error then this bit gets set only after the first packet is unloaded This is automatically cleared when OORDY gets cleared 10 36 ELECTRONICS S3C2500B USB CONTROLLER Table 10 22 USBEP3CSR Register Description Continued BitName MCU USB Desorption 20 Out mode Fifo This bit is valid only when endpoint 3 is set to OUT FLUSH The MCU writes a 1 to flush the FIFO OFFLUSH This bit can be set only when OORDY is set The packet due to be unloaded by the MCU will be flushed 21 Out mode SenD This bit is valid only when endpoint 3 is set to OUT STALL The MCU writes a 1 to this bit to issue a STALL OSDSTALL handshake to the USB The MCU clears this bit to end the STALL condition 22 Out mode SenT This bit is valid only when endpoint 3 is set to OUT STALL The USB sets this bit when an OUT token is ended OSTSTALL with a STALL handshake The USB issues a stall handshake to the host if it sends more than MAXP data for the OUT token 23 Out mode CLear This bit is valid only when endpoint 3 is set to OUT data TOGgle When the MCU writes a 1 to this bit the
350. e Table 3 2 The unique number of the required coprocessor Evaluated to a constant and placed in the CP Opc field Evaluate to the valid coprocessor register numbers CRd CRn and CRm respectively Where present is evaluated to a constant and placed in the CP field p1 10 c1 c2 c3 Request coproc 1 to do operation 10 on CR2 and and put the result in CR1 2 5 1 2 3 2 If Z flag is set request coproc 2 to do operation 5 type 2 on CR2 and and put the result in CR1 ELECTRONICS S3C2500B INSTRUCTION SET 3 15 COPROCESSOR DATA TRANSFERS LDC STC The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 26 This class of instruction is used to load LDC or store STC a subset of a coprocessor s registers directly to memory ARM9TDMI is responsible for supplying the memory address and the coprocessor supplies or accepts the data and controls the number of words transferred 2827 25 24 23 22 21 20 19 16 15 12 11 0 Lu Ds PRI De De oma 7 0 Unsigned 8 Bit Immediate Offset 11 8 Coprocessor Number 15 12 Coprocessor Source Destination Register 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 Transfer Length 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base
351. e data field You can suppress CRC generation by setting the appropriate bit in the transmit control register This is useful in testing for example to force the transmission of a bad in order to test error detection in the receiver It can also be useful in certain bridge or switch applications where end to end CRC checking is desired 7 4 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 3 4 5 Threshold Logic and Counters The transmission state machine uses a counter and logic to control the threshold of when the transmission can begin Before transmitting the MAC waits until eight bytes or a complete frame has been placed in the MTxFIFO This gives the DMA engine some latency without causing an underflow during transmission 7 3 4 6 Back Off and Retransmit Timers When a collision is detected on the network the transmitter block stops the transmission and starts a jamming pattern to ensure that all the nodes detect the collision After this the transmitter waits for a minimum of 96 bit times and then retransmits the data After 16 attempts the transmission state machine sets an error bit and generates an interrupt if enabled to signify the failure to transmit a frame due to excessive collisions It flushes the MTxFIFO and the MAC is ready for the next frame 7 3 4 7 Transmit Data Parity Checker Data in the FIFO is even parity When data is read for transmission the transmission state machine checks the parity If a parity error is de
352. e ignored For normal 19 Tx loop back mode This bit is used for self testing If this bit is set to 1 the transmit data output TxD is internally connected to the receiver data input RxD In operation this bit should always be 0 20 Rx echo mode Setting this bit to 1 selects the auto echo mode of operation In this RxECHO mode the TXD pin is connected to RXD as in local loop back mode but the receiver still monitors the RXD input 21 Tx abort extension When this bit is set to 1 the abort pattern that is initiated when TxABT TxABTEXT 1 is extended to at least 16 bits of 1s in succession and the mark idle state is entered 22 Tx abort When this bit is set to 1 an abort sequence of at least eight bits of 1s is transmitted The abort is initiated and the HTxFIFO is cleared TxABT is then cleared automatically by hardware 8 32 ELECTRONICS S3C2500B HDLC CONTROLLER Table 8 10 HCON Register Description Continued Bit Bit Name Description Number 23 Tx preamble TxPRMB When this bit is set to 1 the content of the HPRMB register is transmitted as many TxPL bit values in interrupt mode instead of mark idle or time fill mode This is useful for sending the data needed by the DPLL to lock the phase It is used only by the Transmitter Interrupt Mode not by theTransmitter DMA Mode see 8 14 24 Tx data terminal ready The TxDTR bit directly controls the nDTR output state
353. e processor will be the modification of the base register if write back was specified and this must be reversed by software and the cause of the abort resolved before the instruction may be retried 3 11 7 2 Aborts During LDM Instructions When ARM9TDMI detects a data abort during a load multiple instruction it modifies the operation of the instruction to ensure that recovery is possible Overwriting of registers stops when the abort happens The aborting load will not take place but earlier ones may have overwritten registers The PC is always the last register to be written and so will always be preserved base register is restored to its modified value if write back was requested This ensures recoverability in the case where the base register is also in the transfer list and may have been overwritten before the abort occurred The data abort trap is taken when the load multiple has completed and the system software must undo any base modification and resolve the cause of the abort before restarting the instruction 3 11 8 INSTRUCTION CYCLE TIMES Normal LDM instructions take nS 1N 11 and LDM PC takes n 1 S 2N 11 incremental cycles where S N and are defined as sequential S cycle non sequential N cycle and internal I cycle respectively STM instructions take n 1 S 2N incremental cycles to execute where nis the number of words transferred 3 44 ELECTRONICS S3C2500B INSTRUCTION SET 3 11 9 AS
354. ed When the DESCON T is set to 1 the valid DESOUTFIFO status means that DESOUTFIFO has at least 2 word Valid data It is recommended when CPU mode is selected When the Available DESINFIFO or valid DESOUTFIFO request signal interrupt or DMA signal is generated the CPU or DMA can write or read data to from the DESIN OUTFIFO Software can use DES or 3DES according to applications which is controlled by DESCON 5 When the DESCON 5 is set to 0 the DES algorithm is used the key1 value is used and the key2 and the key3 are ignored When the DESCON 5 is set to 1 the 3DES algorithm is used the key1 key2 and key3 value used The 3DES algorithm can select the number of keys 2keys or 3keys It must be noticed that when the 3DES with 2keys not 3keys is selected the key value of the key1 register and the key3 register must be the same 11 10 ELECTRONICS S3C2500B DES 3DES 11 5 PERFORMANCE CALCULATION GUIDE Supposed condition DESINFIFO has already data to be encrypting DESOUTFIFO can be written data to be encrypted Cycle Unit Reference Figure 11 1 DES 3DES Block Diagram Unit 1 from DESINFIFO to input buffer 1 1 2 cycle Unit 2 from input buffer to DES engine 1 cycle Unit 3 DES operation 20 cycles for DES 60 cycles for 3DES Unit 4 from DES engine to output buffer 1 2 cycle Unit 5 from output buffer to DESOUTFIFO 2 cycle total 25 cycles for DES 65 cycles for 3DES Explain DES engine cons
355. ed is valid 7 Monitor Transmit End Of Frame MTxEOM 0 Normal 1 Monitor sends end of frame 8 Bus Request BREQ 0 Normal 1 Request TIC bus to send data 9 Monitor Channel Select MSEL 0 Monitor 0 selected 1 Monitor 1 selected 10 IC channel Select ICSEL 0 IC 0 selected 1 IC 1 selected 11 AWAKE AWAKE 0 Normal 1 Request the transceiver to deliver DCL 12 LoopBack LOOP 0 Normal 1 Loopback mode 13 TSA Enable TSAEN 0 Disable 1 Enable 14 Transceiver Type Select TTSEL 0 Transceiver that transmit DCL rising edge after FSC rising edge 1 Transceiver that transmit DCL rising edge beforeFSC rising edge Figure 9 7 IOM2 Control Register ELECTRONICS 9 13 IOM2 CONTROLLER S3C2500B 9 5 2 2 STATUS REGISTER Table 9 4 IOM2STAT Register Status Register RW 0 Channel Buffer Available CIOBA 0 receive data is not valid 1 IOM2CIORD is valid to read Reseved 000000000000 1 Channel Buffer Available 0 1 receive data is not valid 1 IOM2CIH is valid to read 4 Monitor Channel Receive End of 0 The EOM has not arrived Message MRxEOM 1 The EOM has arrived on the monitor channel which indicates that the current message transfer has concluded Monitor Channel Receive Abort 0 Normal MRxABT 1 The remote receiver has sent abort request because of transmission errors In this case the local tran
356. egister Description Continued Bit Bit Name Description Number DMA Rx enable The DRxEN bit lets the HDLC Rx operate on a bus system in DMA mode DRxEN When Rx is enabled an interrupt request caused by the status is inhibited and the HDLC does not use the interrupt request to request a data transfer DMA Rx monitors the HRXFIFO and moves the data from the HRXFIFO to memory This bit is automatically disabled when the next buffer descriptor pointer becomes null or the owner bit is not in DMA mode when the DTxSTSK bit is set DPLL enable Setting this bit enables the DPLL causing the DPLL to enter search mode In Search mode the DPLL searches for a locking edge in the incoming data stream After DPLL is enabled in NRZI mode for example the DPLL starts sampling immediately after the first edge is detected In FM mode the DPLL examines the clock edge of every other bit to decide what correction must be made to remain in sync If the DPLL does not detect an edge during the expected window it sets the one clock missing bit If the DPLL does not detect an edge after two successive attempts it sets the two clock missing bit and the DPLL automatically enters the Search mode To reset both clocks missing latches you can disable and re enable the DPLL using the reset Rx status BRG enable BRGEN This bit controls the operation of the baud rate generator BRG To enable the counter set the BRGEN
357. egister are filled with zeros and for signed half words LDRSH the top 16 bits are filled with the sign bit bit 15 of the half word A half word store STRH repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0 The external memory system should activate the appropriate half word subsystem to store the data Note that the address must be half word aligned if bit 0 of the address is high this will cause unpredictable behaviour 3 36 ELECTRONICS S3C2500B INSTRUCTION SET 3 10 4 2 Big Endian Configuration A signed byte load LDRSB expects data on data bus inputs 31 through to 24 if the supplied address is on a word boundary on data bus inputs 23 through to 16 if itis a word address plus one byte and so on The selected byte is placed in the bottom 8 bit of the destination register and the remaining bits of the register are filled with the sign bit bit 7 of the byte Please see Figure 2 1 A half word load LDRSH or LDRH expects data on data bus inputs 31 through to 16 if the supplied address is on a word boundary and on data bus inputs 15 through to 0 if it is a half word boundary A 1 1 The supplied address should always be on a half word boundary If bit O of the supplied address is high then the ARM9TDMI will load an unpredictable value The selected half word is placed in the bottom 16 bits of the destination register For unsigned half words LDRH the top 16 bits of the register are
358. eive Status Register 484 7 30 7 40 STADATA BGOISIOF i e Pent 7 31 xxvi i i S3C2500B RISC MICROCONTROLLER List of Tables continued Table Title Page Number Number 7 41 Station Management Register Description 7 31 7 42 gg eonMeicee E 7 32 7 43 STACON Register 7 32 7 44 GAMEN 4 a RERS 7 33 7 45 CAM Enable Register 7 33 7 46 MISSGCNT Registe rtm 7 34 7 47 Missed Error Count Register Description 7 34 7 48 PZGN Mem TS 7 35 7 49 Received Pause Count Register 7 35 7 50 RNMPZCNT R egISIeRR 7 35 7 51 Remote Pause Count Register 7 35 7 52 GAM E iiir repr 7 36 7 55 Content Address Memory CAM Register Description 7 36 7 53 MAC Frame Format Description sss nennen 7 37 7 54 STA Frame Structure Description 7 45 8 1 HDLC Data Frame nnne nnn nnns 8 4 8 2 Baud Rate Example 8 8 8 3 HDLC Data Setup and Hold
359. elected 22 20 Tx Clock Select TxCLK 000 TXC pin 001 pin 010 DPLLOUTT 011 BRGOUT1 100 BRGOUT2 26 24 Rx Clock Select RxCLK 000 TXC 001 pin 010 DPLLOUTT 011 BRGOUT1 100 BRGOUT2 27 Reserved 30 28 TXC Output Pin Select TXCOPS This pin is used for output only when it is not used as an input clock for the DPLL 1 or RxCLK 000 Tx Clock 001 Rx Clock 010 BRGOUT1 011 BRGOUT2 100 DPLLOUTT 101 DPLLOUTR 31 Reserved Figure 8 13 HMODE Register ELECTRONICS 8 29 HDLC CONTROLLER S3C2500B 8 7 2 HDLC CONTROL REGISTER Table 8 9 HCONA HCONB and HCONC Register HCONA 0 0100004 RAW HDLC channel A control register 0x00000000 R W HCONB 0 01100044 HDLC channel B control register 0x00000000 HCONC 0xF0120004 HDLC channel C control register 0x00000000 Table 8 10 HCON Register Description Bit Bit Name Description Number 0 Tx reset TxRS Set this bit to 1 to reset the Tx block Tx block comprises HTxFIFO and a transmitter block 1 Rx reset RxRS Set this bit to 1 to reset the Rx block Rx block comprises HRXFIFO and a receiver block DMA Tx reset 8 Set this bit to 1 to reset the DMA Tx block Rx reset Set this bit to 1 to reset the DMA Rx block Tx enable When the TxEN bit is 0 the transmitter enters a disabled state and the line becomes high state In this c
360. else that PHY asserted RX ER during the frame reception Set if the frame length in bit is not the multiple of eight and the CRC is invalid The byte count of the received data is written in hexa decimal by the BDMA Figure 7 3 Data Structure of Rx Buffer Descriptor ELECTRONICS ETHERNET CONTROLLER S3C2500B Buffer Descriptor Start Address Register buffer pointer 1 BRXBDCNT 0 status 3 buffer 1 BRxBS of BDMARXLEN BRXBDCNT 1 buffer 42 BRxBS of BDMARXLEN not used buffer BRxBS of BDMARXLEN buffer pointer Memory for Rx bufer descriptor Memory for frame The BRxBS and BRxMFS of the BDMARXLEN register have to keep multiples of 16 in byte unit For long packet reception larger than 1518 byte the BRxBS should be at least 4 bytes larger than the BRxMFS or less than 1518 byte for the reception with a single or multiple buffer descriptors respectively Figure 7 4 Data Structure of the Receive Frame 7 12 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 4 ETHERNET CONTROLLER SPECIAL REGISTERS There are two Ethernet controllers in S3C2500B They are same each other except the base addresses for internal registers Table 7 2 ETHERNET 0 Special Registers CAMA OxF00B0080 CAM content 32 words Undefined OxFOOBOOFC ELECTRONICS 7 13 ETHERNET CONTROLLER S3C2500B Table 7 3 ETHERNET 1 Special Registers BDMATXDPTRB 000000000 BDMARXDPTRB 000000000 BTXBDCNTB 00000
361. en this COHDIS is enabled as 1 Ext I O contoller disables chip selection hold time TCOH while access the same bank except first access cycle So TCOHDIS helps you to access slow External I O devices more quickly Performance by using COHDIS in the WAITCON register when slow External I O is used could be improved If you use slow External I O you must set TCOH to a proper value because you have to prevent the data collision But when you set TCOH to a non zero value all types of data access in the selected bank have TCOH cycle time So although write to write read to read and write to read access don t have to use TCOH cycle memory controller extends chip select signal during TCOH cycle It decreases the system performance In 53 2500 to improve this operation we add TCOHDIS field If you set COHDIS 1 although TCOH isn t zero TCOH is ignored in write to write read to read and write to read access In those case memory controller operates as if TCOH is zero Table 5 18 WAIT Control Register ELECTRONICS 5 27 MEMORY CONTROLLER 5 28 Reserved Oo0 OrIr NO OI 31 24 Reserved 23 TCOH disable for bank 7 COHDIS7 ozm zm o IN O lt UPMIZ lt gt 22 This forces TCOH to 40 for read to read write to write and write to read access the bank 7 0 disable 1 enable 22 TCOH disable for bank 6 COHDIS6
362. ent addressable memory CAM for storing network addresses a number of commands status and error counter registers The MII supplies the transmission and reception clocks of 25MHz for 100M bps operation 2 5 MHz for the 10M bps speed or 1MHz for the 1M bps for Home PNA The MII conforms to the ISO IEC 802 3 standards PHYSICAL LAYER BDMA Tx Buffer Controller BDMA Tx 64 words Preamble Bus Arbiter and SFD CRC Controller Intergap PAD JAM BDMA Rx timer Generator p Buffer BDMA Rx 64 words Buffer Controller S Y S T E M CAM Contents Memory CAM CRC Preamble 32 words Checker SFD 32 32 Detector BDMA Control Flow Control Station and Satus Manager register MAC Control and Status Figure 7 1 Ethernet Diagram ELECTRONICS 7 1 ETHERNET CONTROLLER S3C2500B 7 2 FEATURES The most important features and benefits of each Ethernet controller are as follows 7 2 Cost effective connection to an external RIC Repeater Interface Controller Ethernet backbone Buffered DMA BDMA engine with burst mode BDMA Tx Rx Buffers BTXBUFF and BRxBUFF 256 bytes 256 bytes MAC Tx Rx FIFOs MTxFIFO and MRxFIFO 80 bytes 16 bytes to support re transmission after collision without DMA request and DMA latency Data alignment logic Old and new physical media support compatible with existing 10M bps networks 100M bps or 10M bps operation to allow price
363. er DTCR should be set carefully because the four data burst mode is executed during decreasing of the transfer count But the misalign of Transfer Counter Register DTCR can be supported The four data burst mode can be used only when GDMA mode is software external GDMA request or DES mode You can use four data burst mode together with block mode of the external GDMA requests ELECTRONICS 12 9 GDMA CONTROLLER S3C2500B Table 12 4 GDMA Control Register Description Continued 7 6 Transfer size These bits determine the transfer data width to be one byte one half word or one word If you select a byte transfer operation the source destination address will be increased or decreased by one with each transfer Each half word transfer increments or decrements the address by two and each word transfer by four NOTE HUART mode you should set byte 00 on transfer size TS 7 6 of DCON register In DES mode you should set word 10 on transfer size TS 7 6 of DCON register 9 8 Source address direction These bits control whether the source address will be increased 00 decreased 01 or fixed 10 during GDMA operation The fixed 10 means the source address will not be changed during a GDMA operation You use this fixed feature when transferring data from a single source to multiple destinations When DCON MODE 3 1 is HUART RX mode HUART to memory 011 or DES OUT mode DES to memory
364. er descriptor maximum count control register HRXBDMAXCNTC 0xF01200CC R W Rx buffer descriptor maximum count control register 8 54 ELECTRONICS S3C2500B IOM2 CONTROLLER 2 amp TSA CONTROLLER 9 1 OVERVIEW The IOM2 bus is an industry standard serial bus for interconnecting telecommunication ICs The S3C2500B includes the 2 controller to enable a modular interface to the terminal network such as an ISDN interface 9 2 FEATURES e OM 2 terminal mode support e Inter device communication via IC channel e bus access control e Monitor channel collision control e Optional signals such as BCL and STRB e Bus Deactivation Activation via e Reversal ELECTRONICS 9 1 IOM2 CONTROLLER S3C2500B 9 3 IOM2 BUS The 2 bus provides a symmetrical full duplex communication link containing user data control programming and status channels Both the line card and terminal portions of the IOM2 standard utilize the same basic frame and clocking structure but differ in the number and usage of the individual channels The various channels are time multiplexed over a four wire serial interface Data is clocked by a Data Rate Clock DCL that operates at twice the data rate Frames are delimited by an 8 kHz Frame Synchronization Clock FSC Data is carried over Data Upstream DU and Data Downstream DD signals Three additional signals are specified the terminal mode
365. er is still valid or LDM Rn PC if the link register has been saved onto a stack pointed to by Rn 3 4 2 INSTRUCTION CYCLE TIMES Branch and branch with link instructions take 2S 1N incremental cycles where S and are defined as sequential S cycle and internal ELECTRONICS 3 7 INSTRUCTION SET S3C2500B 3 4 3 ASSEMBLER SYNTAX Items in are optional Items in must be present expression L cond lt expression gt Examples here BAL CMP BEQ ADDS BLCC 3 8 Used to request the branch with link form of the instruction If absent R14 will not be affected by the instruction A two character mnemonic as shown in Table 3 2 If absent then AL Always will be used The destination The assembler calculates the offset here Assembles to OXEAFFFFFE note effect of PC offset there Always condition used as default R1 0 Compare R1 with zero and branch to fred if R1 was zero otherwise continue fred Continue to next instruction sub ROM Call subroutine at computed address R1 1 Add 1 to register 1 setting CPSR flags onthe result then call subroutine if sub the C flag is clear which will be the case unless R1 held OxFFFFFFFF ELECTRONICS S3C2500B INSTRUCTION SET 3 5 DATA PROCESSING The data processing instruction is only executed if the condition is true The conditions are defined in Table 3 2 The instruction encoding is sho
366. erand may be a shifted register Rm or a rotated 8 bit immediate value Imm according to the value of the bit in the instruction The condition codes in the CPSR may be preserved or updated as a result of this instruction according to the value of the S bit in the instruction Certain operations TST TEQ CMP CMN do not write the result to Rd They are used only to perform tests and to set the condition codes on the result and always have the S bit set The instructions and their effects are listed in Table 3 3 3 10 ELECTRONICS S3C2500B INSTRUCTION SET 3 5 1 CPSR FLAGS The data processing operations may be classified as logical or arithmetic The logical operations AND EOR TST TEQ ORR MOV BIC MVN perform the logical action on all corresponding bits of the operand or operands to produce the result If the S bit is set and Rd is not R15 see below the V flag in the CPSR will be unaffected the C flag will be set to the carry out from the barrel shifter or preserved when the shift operation is LSL 0 the Z flag will be set if and only if the result is all zeros and the N flag will be set to the logical value of bit 31 of the result Table 3 3 ARM Data Processing Instructions Assembler Mnemonic Opeode AND EOR SUB RSB ADD SBC TST az CMP CMN 17100 Operandi OR operand O MOV Operand2 operand1 is ignored BIC Operand1 AND NOT operand2 Bit clear MVN NOT 2 operand1 is i
367. ero Big end bit E Reserved should be one DCache enable bit D Reserved should be zero EE Protection unit enable P The bits in the control register have the following functions e Bits 31 30 Control the clocking mode of the processor as shown in Table 2 9 Clocking modes are discussed in Chapter5 Clock Modes Table 2 9 Clocking Modes Resev o Synchronous 0 1 13 Selects the location of the vector table During reset the bit is cleared and the vector table is located at address 0x00000000 When bit 13 is set the vector table is relocated to address Oxffff0000 e Bits 12 and2 Enable the caches see Chapter4 Caches and Write Buffer Bit7 Selects the endian configuration of the ARM940T Setting bit 7 selects big endian configuration Clearing bit 7 selects a little endian configuration Bit 7 is cleared during reset e Bito Enables the protection unit see Chapter4 Caches and Write Buffer ELECTRONICS 2 23 PROGRAMMER S MODEL S3C2500B 2 16 1 4 Register 2 Instruction and data cacheable registers This location provides access to two registers which contain the cacheable attributes for each of eight memory areas The two registers provide individual control for the and D address spaces The opcode 2 field determines whether the instruction or data cacheable attributes are programmed If the opcode 2 field 0 the data cacheable bits are programmed For example MCR p15 0 Rd c2 c0 0 W
368. ers including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics Microprocessor business has been awarded full ISO 14001 certification BSI Certificate No FM24653 All semiconductor products are designed and manufactured in accord
369. escribed in the section on single data transfers In particular the description of Big and Little Endian configuration applies to the SWP instruction 3 12 2 USE OF R15 Do not use R15 as an operand Rd Rn or Rs in a SWP instruction ELECTRONICS 3 47 INSTRUCTION SET S3C2500B 3 12 3 DATA ABORTS If the address used for the swap is unacceptable to a memory management system the memory manager can flag the problem by driving ABORT HIGH This can happen on either the read or the write cycle or both and in either case the data abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued 3 12 4 INSTRUCTION CYCLE TIMES Swap instructions take 1S 2N 11 incremental cycles to execute where S are defined as squential S cycle non sequential and internal I cycle respectively 3 12 5 ASSEMBLER SYNTAX lt SWP gt cond B Rn Two character condition mnemonic See Table 3 2 If B is present then byte transfer otherwise word transfer Rd Rm Rn Expressions evaluating to valid register numbers Examples SWP RO R1 R2 Load RO with the word addressed by R2 and store R1 at R2 SWPB R2 R3 R4 Load R2 with the byte addressed by R4 and store bits 0 to 7 of R3 at R4 SWPEQ RO RO R 1 Conditionally swap the contents of the word addressed by R1 with RO 3 48 ELECTRONICS S
370. ess Bit Num 7 0 7 7 7 External Data a 0 0 0 b Timing Sequence Table 5 8 External 8 bit Datawidth Load Operation with Big Endian Transfer Width LOAD CPU Reg lt External Memory Bit Num 31 0 15 0 7 0 CPU Register Data abcd xxab CPU Address Bit Num 31 0 3 31 0 3 31 0 3 31 0 CPU Data Bus abxx abcx abcd axax abab aaaa 7 7 0 7 7 0 a 10 10 Bit Num 7 0 7 0 7 0 0 External Data a b 4th 10 0 b 2nd Timing Sequence 14 24 md ELECTRONICS 5 9 MEMORY CONTROLLER S3C2500B Table 5 9 and 5 10 Using little endian and word access Program Data path between register and external memory WA Address whose LSB is 0 4 8 EA External Address HA Address whose LSB is 0 2 4 6 8 E BA Address whose LSB is 0 1 2 3 4 5 6 7 8 9 A C D E F X Don t care Table 5 9 External 32 bit Datawidth Store Operation with Little Endian Transfer Width STORE aa Reg External Memory Bit Num Data x CPU Address Address HA 2 External Address ADDR Address ADDR Bit Num 31 31 lt Data es 2 4 x p Timing Sequence Sequence Bit Num S 31 31 Data Bus is bib ddl ms aaaa Table 5 10 External 32 bit Datawidth Load Operation with Little Endian Transfer Width LOAD C
371. esses BDMA count register values indicate the number of frames to be handled by BDMA In addition users can determine how many buffer descriptors to use by controlling the BDMATXCON 3 0 BTxNBD and BDMARXCON 3 0 BRxNBD If the last buffer descriptor was used by the BDMA the next buffer is the first buffer and BDMA count register value goes to zero Finally the status and length fields in the first and the last Rx buffer descriptors are updated The length field value is same in the first and last Rx buffer descriptor The status field of the middle Rx buffer descriptors does not have any mean When the received frame size exceeds the maximum frame size BRxMFS bits of BDMARXLEN the data frame will be overwritten by the last word of maximum frame If overflow occurred this status is written to status field bit 20 in the Rx buffer descriptor When the BDMA reads a descriptor if the ownership bit is not set it has two options Skip to the next buffer descriptor or Generate an interrupt and halt the BDMA operation If CPU set to skip bit in Rx buffer descriptor s status field BDMA goes next buffer without interrupt or BDMA stop During transmission the two byte frame length at the Tx buffer descriptor is moved into the BDMA internal Tx counter After transmission Tx status is saved in the Tx buffer descriptor The BDMA points to the next buffer descriptor address register for the linked list structure However BDMATXDPTR register
372. et 2 IINRDY bit is cleared 3 FIFO is flushed 4 OSTSTALL ISTSTALL is set NOTE conditions 1 and 2 are mutually exclusive uS SUSpend The USB sets this bit when it receives suspend Interrupt SUSI signaling This bit is set whenever there is no activity for 3ms on the bus Thus if the MCU does not stop the clock after the first suspend interrupt it will be continue to be interrupted every 3ms as long as there is no activity on the USB bus By default this interrupt is disabled RESume The USB sets this bit when it receive resume Interrupt RESI signaling while in suspend mode If the resume is due to a USB reset then the MCU is first interrupted with a Resume Interrupt Once the clocks resume and the SEO condition persists for 3ms USB RESET interrupt will be asserted 10 ReSeT Interrupt The USB sets this bit when it receives reset signaling RSTI 11 DISConnect The USB sets this bit when it finishes disconnect Interrupt DISCI 81 12 ELECTRONICS 10 15 USB CONTROLLER S3C2500B 109 8 7 543210 0 EPO Interrupt 0 No EPO interrupt 1 EPO interrupt generated 1 EP1 Interrupt EP11 0 No interrupt 1 EP1 interrupt generated 2 EP2 Interrupt 2 0 No EP2 interrupt 1 EP2 interrupt generated 3 EP3 Interrupt 0 No EP3 interrupt 1 EP3 interrupt generated 4 EPA Interrupt EP4I 0 No interrupt 1 interrupt generated
373. et has an error then this bit gets set only after the first packet is unloaded This is automatically cleared when OORDY gets cleared ELECTRONICS 10 31 USB CONTROLLER S3C2500B Table 10 20 USBEP2CSR Register Description Continued 20 Out mode This bit is valid only when endpoint 2 is set to OUT Fifo FLUSH The MCU writes a 1 to flush the FIFO OFFLUSH This bit can be set only when OORDY is set The packet due to be unloaded by the MCU will be flushed 21 Out mode This bit is valid only when endpoint 2 is set to OUT SenD STALL The MCU writes a 1 to this bit to issue a STALL OSDSTALL handshake to the USB The MCU clears this bit to end the STALL condition 22 Out mode This bit is valid only when endpoint 2 is set to OUT SenT STALL The USB sets this bit when an OUT token is ended OSTSTALL with a STALL handshake The USB issues a stall handshake to the host if it sends more than MAXP data for the OUT token 23 Out mode This bit is valid only when endpoint 2 is set to OUT CLear data TOGgle When the MCU writes a 1 to this bit the data OCLTOG toggle sequence bit is reset to DATAO can not be set 25 In mode fifo Not This bit is valid only when endpoint 2 is set to IN EMPty INEMP Indicate there is at least one packet of data in FIFO if USBEP2CSR 25 24 is 10 1 packet IN FIFO 11 2 packets of lt 1 2 FIFO or 1 packet of MAXP FIFO size 26 In mode UNDER This
374. eway WLAN AP etc A variety of communication features is embedded into 53 2500 required many communication areas including two Ethernet MACs three HDLCs and three TSAs supporting IOM2 two high speed UARTS a console UART and USB A security feature is also supported by DES 3DES accelerator This highly integrated microcontroller enables customers to save system costs and increase performance over other 32 bit microcontroller The S3C2500B is built based on an outstanding CPU core The ARM940T cached processor is a member of the ARM9 Thumb family of high performance 32 bit system on a chip processor solutions It provides a complete high performance CPU subsystem including ARM9TDMI RISC integer CPU 4KB instruction data caches write buffer and protection unit with an AMBA bus interface The ARM9TDMI core within the ARM940T executes both the 32 bit ARM and 16 bit Thumb instruction sets allowing the user to trade off between high performance and high code density It is binary compatible with ARM7TDMI ARM10TDMI and Strong ARM processors and is supported by a wide range of tools operating systems and application software The following integrated on chip functions are described in detail in this user s manual e ARM940T cached processor e Ethernet Controller e HDLC Controller e Controller e Controller 1 2 Controller e USB Controller 2 Controller e Programmable I O ports e Interrupt
375. filled with zeros and for signed half words LDRSH the top 16 bits are filled with the sign bit bit 15 of the half word A half word store STRH repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0 The external memory system should activate the appropriate half word subsystem to store the data Note that the address must be half word aligned if bit of the address is HIGH this will cause unpredictable behaviour 3 10 5 USE OF R15 Write back should not be specified if R15 is specified as the base register Rn When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction R15 should not be specified as the register offset Rm When R15 is the source register Rd of Half word store STRH instruction the stored address will be address of the instruction plus 12 3 10 6 DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system For instance in a system which uses virtual memory the required data may be absent from the main memory The memory manager can signal a problem by taking the processor ABORT input high whereupon the data abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued 3 10 7 INSTRUCTION CYCLE TIMES Normal LDR H SH SB instructions take 15 1N
376. frame is octet 1 Received frame is not octet 19 Rx overrun RxOV 0 Normal operation 1 Received data is transferred into the RxFIFO when it is full 20 Reserved 21 Reserved 22 DMA Tx abort DTxABT 0 Normal operation 1 Abort signal is sended and Tx enable bit is cleared 23 Rx internal error RXIERR 0 Normal operation 1 Received frame is not stable due to receive clock is unstable 24 DMA Rx frame done every received frame DRxFD 0 Normal operation 1 Rx operation has successfully transferred a frame from RxFIFO to buffer memory 25 Reserved 26 DMA Rx not owner DRxNO 0 has the ownership 1 CPU has the ownership 27 DMA Tx frame done DTxFD 0 Normal operation 1 DMA Tx operation has successfully transferred a frame from memory to TxFIFO 28 Reserved 29 DMA Tx not owner DTxNO 0 has the ownership 1 CPU has the ownership 30 DPLL one clock missing DPLLOM 0 Normal operation 1 Set in FM Machester mode when DPLL does not detect an edge on the first entry 31 DPLL two clock missing DPLLTM 0 Normal operation 1 DPLL was not detected on two consecutive edges an search mode sas entered Figure 8 15 HDLC Status Register Continued ELECTRONICS 8 41 HDLC CONTROLLER S3C2500B 8 7 5 HDLC INTERRUPT ENABLE REGISTER HINTEN Table 8 13 HINTENA HINTENB and HINTENC Register HINTENA 0xF010000C HDLC Interrupt Ena
377. gister for GDMA IOPGDMA ELECTRONICS 15 7 VO PORTS S3C2500B 15 3 4 PORT CONTROL REGISTER FOR EXTERNAL INTERRUPT IOPEXTINT If the port is used for a function s port such as an external interrupt request its signal function is determined by the IOPEXTINT register IOPEXTINT register is used to configure external interrupt request signals ports provide 3 tap filtering and you can select filtering on or off External interrupt provides level or rising or falling edge detection If you set rising or falling edge detection rising or falling edge interrupt makes interrupt status high You can clear the interrupt by writing IOPEXTINTPND register to 1 If you set level detection then external interrupt level goes direct to interrupt controller External signals can be active high or low so you must set the active high or low bits for the proper operation Table 15 5 IOPEXTINT Register IOPEXTINT OxF0030014 port special function register for external 0x00000000 interrupt 15 8 ELECTRONICS S3C2500B VO PORTS 31 24 23 22 21 2019 18 17 16 15 14 13 121110 9 8 7 6 5 4 3 2 1 IOPEXTINT DP 23 20 Control external interrupt request5 input for port 13 5 23 0 active low 1 active high 22 0 filtering off 1 filtering on 21 20 00 level detection 01 rising edge detection 10 falling edge detection 19 16 Control external interrupt request4 input for port 12 xINT4
378. gnored The arithmetic operations SUB RSB ADD ADC SBC RSC CMP CMN treat each operand as a 32 bit integer either unsigned or 2 s complement signed the two are equivalent If the S bit is set and Rd is not R15 the V flag in the CPSR will be set if an overflow occurs into bit 31 of the result this may be ignored if the operands were considered unsigned but warns of a possible error if the operands were 2 s complement signed The C flag will be set to the carry out of bit 31 of the ALU the Z flag will be set if and only if the result was zero and the N flag will be set to the value of bit 31 of the result indicating a negative result if the operands are considered to be 2 s complement signed ELECTRONICS 3 11 INSTRUCTION SET S3C2500B 3 5 2 SHIFTS When the second operand is specified to be a shifted register the operation of the barrel shifter is controlled by the shift field in the instruction This field indicates the type of shift to be performed logical left or right arithmetic right or rotate right The amount by which the register should be shifted may be contained in an immediate field in the instruction or in the bottom byte of another register other than R15 The encoding for the different shift types is shown in Figure 3 5 11 6 5 Shift Type 6 5 Shift Type 00 logical left 01 logical right 00 logical left 01 logical right 10 arithmetic right 11 rotate right 10 arithmetic right 11 rotate r
379. h Speed UART Control Character 2 14 21 14 3 10 High Speed UART Autoband Boundary 14 22 14 3 11 High Speed UART Autobaud Table 14 23 14 4 HighsSpeed DART OperatlOn iim rrr RR a E ened 14 24 14 41 suu Ta 14 24 14 4 2 Hardware Flow Gontrol t p 14 24 14 4 3 Software FOW CONVO iesi iiiter le Yir nna 14 26 14 4 4 Auto Baud Rate 14 26 Chapter 151 0 Ports 5 15 1 Agua EE 15 1 15 3 D O Port Speclal Register etre he gt 15 2 15 3 1 Port Mode Select 15 3 15 3 2 I O Port Function Control 15 5 15 3 3 I O Port Control Register for 15 8 15 3 4 I O Port Control Register for External 15 9 15 3 5 I O Port External Interrupt Clear 15 11 15 3 6 O Port Data Beglster ott etr e ped Sauna 15 12 15 3 7 I O Port Drive Control 15 12 xiv S
380. h determines the direction R W of the message When an address is sent each IC on the bus compares the first 7 bits received following start condition with its own address If the addresses match the IC considers itself addressed by the master as a slave receiver or a slave transmitter 6 8 ELECTRONICS S3C2500B 2 CONTROLLER 6 5 SPECIAL REGISTERS The controller has three special registers a control status register IICCON a prescaler register IICPS and a shift buffer register IICBUF 6 5 1 CONTROL STATUS REGISTER IICCON The control status register for the is described in Table 6 2 Table 6 1 Control Status Register IICCON Table 6 2 IICCON Register Description Buffer flag BF The BF bit is set when the buffer is empty in transmit mode or when the buffer is full in receive mode To clear the buffer you write a O to this bit The BF bit is cleared automatically whenever the IICBUF register is written or read Interrupt enable IEN Setting the interrupt enable bit to 1 enables the interrupt An interrupt is generated if BF bit is set to 1 2 Last received bit LRB The LRB bit is read only It holds the value of the last received bit over the Normally this bit will be the value of the slave acknowledgement To check for slave acknowledgement you test the LRB Acknowledge enable The ACK bit is normally set to 1 This causes the controller
381. h high speed UART detects baud rate divisor register value CNTO CNT1 as 0x04 autobaud mechanism will correct baud rate divisor register value as 0x03 because detected value is between 0x05 ABB1 and 0x02 ABBO is lowest table value and is highest table value also ABTS is highest boundary value of total range If out of range value is detected it will be written normally without modification em If Ox1F was detected aBB2 0x0B If 0x0B was detected If 0x04 was detected Rewrite 0x03 Figure 14 13 Example of AutoBaud Table Register Setting Table 14 18 HUABT Registers HUABT 0 0070024 R W High Speed UART autobaud boundary register 0x170B0502 OxF0080024 31 24 23 16 15 8 7 0 ABT3 ABT2 ABT1 ABTO 7 0 AutoBaud Table 0 15 8 AutoBaud Table 1 23 16 AutoBaud Table 2 31 24 AutoBaud Table 3 Figure 14 14 High Speed UART AutoBaud Boundary Register ELECTRONICS 14 23 SERIAL I O HIGH SPEED UART S3C2500B 14 4 HIGH SPEED UART OPERATION Data Transmit Operation Flow If there is no data at Tx Buffer FIFO of High Speed UART in case of FIFO if data in the Tx FIFO are empty as same amount of trigger level High Speed UART generates interrupt or GDMA request signal It depends on High Speed UART mode CPU or software or GDMA controller will read data from memory where High Speed UART transmit data are stored and send them to Tx Buffer FIFO Transfer unit is byte When da
382. he bit cell The adding or subtracting of a count of 1 will produce a phase jitter of 5 63 degrees on the output Because the DPLL uses both edges of the incoming signal for its clock source comparison the mark space ratio 5096 of the incoming signal must not deviate more than 1 5 of its baud rate if proper locking is to occur In the FM mode the DPLL clock must be 16 times the data rate The 5 bit counter in the DPLL counts from 0 to 31 so the DPLL makes two sampling clocks during the 0 to 31 counting cycle The DPLL output is Low while the DPLL is waiting for an edge in the incoming data stream The first edge the DPLL detects is assumed to be a valid clock edge From this point the DPLL begins to generate output clocks In this mode the transmit clock output of the DPLL lags the receive clock outputs by 90 degrees to make the transmit and receive bit cell boundaries the same because the receiver must sample the FM data at a one quarter and three quarters bit time You can program the 32X clock for the DPLL to originate from one of the RXC input pins from the TxC pin or from the baud rate generator output You can also program the DPLL output to be echoed out of the HDLC module over the TXC pin if the TXC pin is not being used as an input During idle time you can set the TxPRMB in to send the special pattern required for a remote DPLL to lock the phase In this case the content of the HPRMB register is sent repeatedly The
383. he data swap instruction is used to swap a byte or word quantity between a register and external memory This instruction is implemented as a memory read followed by a memory write which are locked together the processor cannot be interrupted until both operations have completed and the memory manager is warned to treat them as inseparable This class of instruction is particularly useful for implementing software semaphores The swap address is determined by the contents of the base register Rn The processor first reads the contents of the swap address Then it writes the contents of the source register Rm to the swap address and stores the old memory contents in the destination register Rd The same register may be specified as both the source and destination The lock output goes HIGH for the duration of the read and write operations to signal to the external memory manager that they are locked together and should be allowed to complete without interruption This is important in multi processor systems where the swap instruction is the only indivisible instruction which may be used to implement semaphores control of the memory must not be removed from a processor while it is performing a locked operation 3 12 1 BYTES AND WORDS This instruction class may be used to swap a byte B 1 or a word B 0 between an ARM9TDMI register and memory The SWP instruction is implemented as a LDR followed by a STR and the action of these is as d
384. he functions of these addresses are discussed in detail in the FIFO section below Table 8 4 HDLC Channel A Special Registers HTxFIFOCA 0 0100010 HTxFIFO frame continue register Frame Continue Frame Terminate HSAR3A 0xF0100030 HDLC station address 3 0x00000000 HMASKA 0xF0100034 HDLC mask register 0x00000000 ES HDMATxPTRA 0 0100038 DMA Tx buffer descriptor pointer OxFFFFFFFF 0xF010003C DMA Rx buffer descriptor pointer OxFFFFFFFF HRXBDCNTA 0 01000 4 Rx buffer descriptor count register OxXXXXX000 HTXMAXBDCNTA 0 01000 8 R W Tx buffer descriptor maximum count OxXXXXXFFF register HRXMAXBDCNTA 0 01000 Rx buffer descriptor maximum count OxXXXXXFFF register 8 24 ELECTRONICS S3C2500B HDLC CONTROLLER Table 8 5 HDLC Channel B Special Registers HTxFIFOCB 0 0110010 W HTxFIFO frame continue register Frame Continue HTxFIFOTB 0 0110014 W HTxFIFO frame terminate register Frame Terminate HTXMAXBDCNTB 0 01100 8 R W Tx buffer descriptor maximum count OxXXXXXFFF register HRXMAXBDCNTB 0 01100 Rx buffer descriptor maximum count OxXXXXXFFF register ELECTRONICS 8 25 HDLC CONTROLLER S3C2500B Table 8 6 HDLC Channel C Special Registers HTxFIFOCC 0 0120010 W HTxFIFO frame continue register Frame Continue HTxFIFOTC 0 0120014 W HTxFIFO frame terminate register Frame Terminate HTXBDMAXCNTC 0 01200 8 R W Tx buffer descri
385. he last location of the Rx FIFO and is available to be read Rx idle RxIDLE The RxIDLE status bit indicates that a minimum of 15 consecutive 1s have been received The event is stored in the status register and can be used to trigger a receiver interrupt The RxIDLE bit continues to reflect the inactive idle condition until a 0 is received You can clear this bit by writing a 1 to this bit Rx abort RxABT The RxABT status bit is set to 1 when seven or more consecutive 1s abort sequence have been received When an abort is received in an in frame condition the event is stored in the status register triggering an interrupt request You can clear this bit by writing a 1 to this bit 17 Rx CRC error RXCRCE The RxCRCE status bit is set a frame is completed with a CRC error 18 Rx non octet align The RxNO bit is set to 1 if received data is non octet aligned frame Rx overrun The RxOV status bit is set to 1 if the data received is transferred into the HRXFIFO when it is full resulting in a loss of data Continued overruns destroy data in the first FIFO register 20 Not applicable Not applicable DMA Tx abort This bit is set to 1 when abort signal is sent due to the Tx underrun or DTxABT CTS lost occurred If this bit is set DTXEN in HCON bit cleared You can clear this bit by writing 1 to this bit 8 38 ELECTRONICS S3C2500B HDLC CONTROLLER Table 8 12 HSTAT Register Desc
386. his register value specifies the buffer size allocated to each BRxBS buffer descriptor Thus for an incoming frame larger than the BRxBS multiple buffer descriptors are used for the frame reception NOTE BRxBS value has to keep multiples of 16 in byte unit For long packet reception larger than 1518 bytes the BRxBS should be at least 4 bytes larger than the BRxMFS or less than 1518 bytes for the reception with a single or multiple buffer descriptor respectively 15 12 Not applicable 27 16 BDMA Maximum Rx Frame This register value controls how many bytes per frame can be Size BRxMFS saved to memory If the received frame size exceeds these values an error condition is reported NOTE BRxMFS value has to keep multiples of 16 in byte unit 51 28 Not applicable ELECTRONICS 7 23 ETHERNET CONTROLLER S3C2500B 7 4 2 MAC RELATIVE SPECIAL REGISTER 7 4 2 1 MAC Transmit Control Frame Status The transmit control frame status register CFTXSTAT provides the status of a MAC control frame as it is sent to a remote station This operation is controlled by the MSdPause bit in the transmit control register MACTXCON It is the responsibility of the BDMA engine to read this register and to generate an interrupt to notify the system that the transmission of a MAC control packet has been completed Table 7 26 CFTXSTAT Register CFTXSTATB OxFO0COO30 Transmit control frame status 0x00000000 Table 7 27 Tra
387. host or peripheral that HUARTO is ready to transmit or receive serial data General I O Port HUARTO UCLK 7 HURXDO GPIO28 HUTXDO GPIO29 HUnDTRO GPIO30 1 28 ELECTRONICS S3C2500B PRODUCT OVERVIEW Table 1 1 S3C2500B Signal Descriptions Continue Group Pad Type HUARTO HUnDSRO 7 HUnRTSO GPIO32 HUnCTSO GPIO33 HUnDCDO GPIO34 HUART1 7 HURXD1 GPIO35 HUTXD1 GPIO36 ELECTRONICS Pin phbst8 phbst8 phbst8 O phbst8 ohbst8 ohbst8 Not HUARTO Data Set Ready This input signals in the HUARTO that the peripheral or host is ready to transmit or receive serial data General I O Port Not request to send This pin output state goes Low or High according to the transmit data is in Tx buffer or Tx FIFO when hardware flow control bit value set to one in HUARTO control register If Tx buffer or Tx FIFO has data to send this pin state goes low If hardware flow control bit is zero this pin output can be controlled directly by HUARTO control register General I O Port Not Clear to send This input pin function controlled by hardware flow control bit value in HUARTO control register If hardware flow control bit set to one HUARTO can transmit the transmitting data only when this pin state is active General I O Port Not Data Carrier Detect This input pin function is determined by hardware flow control bit value
388. hown below 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211109 8 7 6 5 4 3 2 1 0 Data processing Dpppee B ow m re Ls jejeje e rae D m ppp m mmm fefe Tp per I 1090090090000000000009 000 Halfword data transfer Cond register offset ppp m m rimedio afset cw EL usted 35 P Cond HDH Offset Branch e Ga edt eee Ignored by processor Software Interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 48 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 Figure 3 1 ARM Instruction Set Format NOTE Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken for instance a Multiply instruction with bit 6 changed to a 1 These instructions should not be used as their action may change in future ARM implementations ELECTRONICS 3 1 INSTRUCTION SET S3C2500B 3 1 2 INSTRUCTION SUMMARY Table 3 1 The ARM Instruction Set memo Load coprocessor from memory Coprocessor load Load multiple registers Stack manipulation Pop Move negative register mnemonic OR op2 AND NOT Rn 3 2 ELECTRONICS S3C2500B INSTRUCTION SET Table 3 1 The ARM Instruction Se
389. ight 11 7 Shift Amount 11 8 Shift Register 5 bit unsigned integer Shift amount specified in bottom byte of Rs Figure 3 5 ARM Shift Operations 3 5 2 1 Instruction Specified Shift Amount When the shift amount is specified in the instruction it is contained in a 5 bit field which may take any value from 0 to 31 A logical shift left LSL takes the contents of Rm and moves each bit by the specified amount to a more significant position The least significant bits of the result are filled with zeros and the high bits of Rm which do not map into the result are discarded except that the least significant discarded bit becomes the shifter carry output which may be latched into the C bit of the CPSR when the ALU operation is in the logical class see above For example the effect of LSL 5 is shown in Figure 3 6 Contents of Rm Value of Operand 2 00000 Figure 3 6 Logical Shift Left NOTE LSL 0 is a special case where the shifter carry out is the old value of the CPSR C flag The contents of Rm are used directly as the second operand A logical shift right LSR is similar but the contents of Rm are moved to less significant positions in the result LSR 5 has the effect shown in Figure 3 7 3 12 ELECTRONICS S3C2500B INSTRUCTION SET 31 5 4 0 Contents of Rm carry out 00000 Value of Operand 2 Figure 3 7 Logical Shift Right The form of the shift field which might be expected to correspond to LSR 0 is used
390. ignal to compress shorten the packet received for management purposes and to reduce memory usage See the DP83950 Data Sheet published by National Semiconductor for details on the RIC Management Bus This pin is controlled by a special register with which you can define the polarity and assertion method CAM match active or not match active of the PCOMP signal ELECTRONICS 1 19 PRODUCT OVERVIEW S3C2500B Table 1 1 S3C2500B Signal Descriptions Continue Group PinName Pin PadType Description Ethernet CRS 0 1 phis Carrier Sense Carrier Sense for 10M ControllerO CRS is asserted asynchronously with 18 minimum delay from the detection of a non idle medium in MII mode CRS 10M is asserted when a 10 Mbit s PHY has data to transfer A 10 Mbit s transmission also uses this signal RX CLK 0 1 phis Receive Clock Receive Clock for 10M RX CLK is a continuous clock signal Its frequency is 25 MHz for 100 Mbit s operation and 2 5 MHz for 10 Mbit s RXD 3 0 DV and RX ERR are driven by the PHY off the falling edge of and sampled on the rising edge To receive data the RXCLK 10 M clock comes from the 10Mbit s PHY RXDO 3 0 4 phis Receive Data Receive Data for 10M RXD 10M RXD is aligned on nibble boundaries RXD 0 corresponds to the first bit received on the physical medium which is the LSB of the byte in one clock period and the fifth bit of that byte in the nex
391. ime slot assigned to HDLCC 23 12 STOP The location of stop bit of time slot assigned to HDLCC 25 24 MODE 00 DCE 01 PCM highway non multiplexed 10 IOM2 11 PCM highway multiplexed 26 Divide 0 HDLC clock is the same clock as the external clock 1 HDLC clock is 1 2 times the external clock 127 Peserved 31 30 29 28 27 26 25 24 23 12 11 0 l pej 11 0 The location of START bit of time slot 23 12 The location of STOP bit of time slot 25 24 MODE 00 01 Highway non multiplexed 10 IOM2 11 PCM Highway multiplexed 26 Divide 0 1 x Clock mode 1 0 5 x Clock mode Figure 9 21 TSA C Control Register ELECTRONICS 9 25 IOM2 CONTROLLER S3C2500B 9 5 14 IOM2STRB STROBE REGISTER Table 9 18 IOM2STRB Strobe Register mW IOM2STRB 0 013003 Strobe Register 0x00000000 mag 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 7 0 The location of START bit of time slot 15 8 The location of STOP bit of time slot Figure 9 22 2 Strobe Register 9 26 ELECTRONICS S3C2500B USB CONTROLLER USB FUNCTION CONTROLLER 10 1 OVERVIEW USB products are easy to use for end users Electrical details such as bus termination are isolated from end users and plug and play is supported There re other merits for users Self identifying peripherals automatic mapping function to driver auto configuration dynamically attach
392. ing a limited length of shielded cable ELECTRONICS 7 3 ETHERNET CONTROLLER S3C2500B 7 3 2 PHYSICAL LAYER ENTITY PHY The physical layer entity or PHY performs all of the decoding encoding on incoming and outgoing data The manner of decoding and encoding Manchester for 10BASE T 4B 5B for 100BASE X or 8B 6T for 100BASE T4 does not affect the MII The MII provides the raw data it receives starting with the preamble and ending with the CRC The MII expects raw data for transmission also starting with the preamble and ending with the CRC The MAC layer also generates jam data and transmits it to the PHY 7 3 3 BUFFERED DMA INTERFACE BDI The buffered DMA interface BDI supports read and write operations across the system bus Two eight bit buses transfer data with optional parity checking The system interface initiates data transfers The MAC layer controller responds with a ready signal to accept data for transmission or to deliver data which has been received An end of frame signal indicates the boundary between packets 7 3 4 THE MAC TRANSMITTER BLOCK The MAC transmitter block is responsible for transmitting data It complies with the IEEE802 3 standard for the carrier sense multiple access with collision detection CSMA CD protocol 7 3 4 1 MAC TxFIFO MTXxFIFO The MTxFIFO has an 80 byte depth An extra bit is associated with each data byte for parity checking This 80 byte by 9 bit size allows the first 64 bytes of a dat
393. interface 08 VT Switching threshold O sg s VT Schmitt trigger positive going CMOS 2 0 V threshold VT Schmitt trigger negative CMOS going threshold V High level input current uA Input buffer with pull down Input buffer Input buffer with pull up Type B16 16 mA Type B20 20 mA Type B24 lon 24 mA 18 2 ELECTRONICS S3C2500B ELECTRICAL DATA Table 18 3 D C Electric Characteristics Continued Sms Type Low level output voltage 24 24 la 24mA 24 la 24mA Tri state output leakage Vout Vss Or Vpp current sq Maximum operating current Vpp 3 3 V 1 8 V note mA Frequency 133MHz Input capacitance Any Input Bi directional 4 pF Buffers Lum NR NOTE Later It will be updated ELECTRONICS 18 3 ELECTRICAL DATA S3C2500B 18 5 MAX POWER CONSUMPTION Condition 1 S3C2500B ES Sample SMDK2500 Evaluation Board Rev 1 0 without LCD module HCLKout damping resister R146 480 Clock Mode Async 166MHz 133MHz Samsung Diagnostic Test All Test Remap Mode On D Cache On c RON Samsung Diagnostic Test Idle Remap Mode On D Cache Table 18 4 MAX Power Consumption Voltage MAX Power Consumption 3 3 V 95 C 760 2 mW 3 3 V 80 C 740 4 mW 3 3 V 25 C 741 3 mW 3 3 V 0 C 738 mW 3 3 V 80 C 748 5 mW 3 3
394. ion 8 51 8 24 Transparent Control 8 52 8 25 HTXBDCNTB and HTXBDCNTC 8 53 8 26 HRXBDCNTB HRXBDCNTC 22 8 53 8 27 HTXBDMAXCNTA HTXBDMAXCNTB and HTXBDMAXCNTC Register 8 54 8 28 HRXBDMAXCNTA HRXBDMAXCNTB HRXBDMAXCNTC Register 8 54 3C2500B RISC MICROCONTROLLER xxix List of Tables continued Table Title Page Number Number 9 1 HDLC External Pin Multiplexed Signals 9 10 9 2 2 Special 444 9 11 9 3 IOM2CON Register Control 9 12 9 4 IOM2STAT Register Status 9 14 9 5 IOM2INTEN Register Interrupt Enable 9 16 9 6 IOM2TBA Register TIC Bus Address 9 18 9 7 IOM2ICTD IOM2 IC Channel Transmit Data Register 9 19 9 8 IOM2ICRD 2 IC Channel Receive Data Register 9 19 9 9 IOM2CITDO IOM2 Channel Transmit Data Register 9 20 9 10 IOM2CIRDO IOM2 Channel Receive Data Register 9 20 9 11 IOM2C
395. iptor Start Address Register Description BDMA transmit buffer The BDMA transmit buffer descriptor start address register descriptor start address contains the address of the first buffer descriptor on the frame to be sent 7 4 1 4 BDMA Receive Buffer Descriptor Start Address Register Table 7 10 BDMARXDPTR Register BDMARXDPTRA 0xF00A000C BDMA Rx buffer descriptor base register 0x00000000 BDMARXDPTRB 0 00 000 BDMA Rx buffer descriptor base register 0x00000000 Table 7 11 BDMA Receive Buffer Descriptor Start Address Register Description BDMA receive buffer The BDMA receive buffer descriptor start address register descriptor start address contains the address of the first buffer descriptor on the frame to be saved ELECTRONICS 7 17 ETHERNET CONTROLLER S3C2500B 7 4 1 5 BDMA Transmit Buffer Descriptor Counter Table 7 12 BTXBDCNT Register BTXBDCNTA OxF00A0010 BDMA Tx buffer descriptor counter of Current 0x00000000 Pointer BTXBDCNTB 0 00 0010 BDMA Tx buffer descriptor counter of Current 0x00000000 Pointer Table 7 13 BDMA Transmit Buffer descriptor Counter BDMA Tx buffer descriptor The maximum counter value is dependent on the BTxNBD of the Counter BDMATXCON register Buffer descriptor current address BDMATXDPTR BTXBDCNT lt lt 3 7 4 1 6 BDMA Receive Buffer Descriptor Counter Table 7 14 BRXBDCNT Register BRXBDCNTA OxF00A0014 R W BDMA Rx buffer descriptor counter 0x00000000
396. is 1 the BDMA controller owns the descriptor When the bit is 0 the CPU owns the descriptor The owner of the descriptor always owns the associated data frame The descriptor s frame start address field always points to this frame Software sets the BDMARXLEN register to the length and also sets the BDMARXDPTR register to point to a chain of buffer descriptors all of which have their ownership bits set The BDMA engine can then be started to set the BDMARXCON 10 BRxEn When a frame is received it is copied into the external memory at the address specified by the BDMARXDPTR register Please note that no configurable offset or page boundary calculation is required The received frame is written into the buffer in the external memory until the end of frame is reached or until the length exceeds the configured maximum frame size If the entire frame is received successfully the status bits in the buffer descriptor are set to indicate this Otherwise the status bits are set to indicate that an error occurred The ownership bit in the status and length field is cleared and an interrupt may now be generated The length field in the Rx buffer descriptor is updated in summation with previous length filed of Rx buffer descriptor The BDMA points the next buffer descriptor automatically but BDMATXDPTR BDMARXDPTR is not updated to the next pointer It always has the first buffer descriptor address Because BDMA pointers are fixed as initial addr
397. is R15 then the assembler will subtract 8 from the offset value to allow for ARM9TDMI pipelining In this case base write back should not be specified Writes back the base register set the W bit if is present ELECTRONICS S3C2500B Examples LDRH STRH LDRSB LDRNESH HERE STRH FRED ELECTRONICS R1 R2 R3 R3 R4 4H 4 R8 R2 4 223 R11 RO R5 PC FRED HERE 8 INSTRUCTION SET Load R1 from the contents of the half word address contained in R2 R3 both of which are registers and write back address to R2 Store the half word at R14 14 but don t write back Load R8 with the sign extended contents of the byte address contained in R2 and write back R2 223 to R2 Conditionally load R11 with the sign extended contents of the half word address contained in RO Generate PC relative offset to address FRED Store the half word in R5 at address FRED 3 39 INSTRUCTION SET S3C2500B 3 11 BLOCK DATA TRANSFER LDM STM The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 18 Block data transfer instructions are used to load LDM or store STM any subset of the currently visible registers They support all possible stacking modes maintaining full or empty stacks which can grow up or down memory and are very efficient instructions for saving or restoring context or for moving large blocks of data
398. is a second coprocessor register which may be involved in some way which depends on the particular operation specified 3 56 ELECTRONICS S3C2500B INSTRUCTION SET 3 16 2 TRANSFERS TO R15 When a coprocessor register transfer to ARM9TDMI has 15 as the destination bits 31 30 29 and 28 of the transferred word are copied into the N Z C and V flags respectively The other bits of the transferred word are ignored and the PC and other CPSR bits are unaffected by the transfer 3 16 3 TRANSFERS FROM R15 A coprocessor register transfer from ARM9TDMI with R15 as the source register will store the PC 12 3 16 4 INSTRUCTION CYCLE TIMES MRC instructions take 1S 1 1C incremental cycles to execute where S and C are defined as sequential S cycle internal I cycle and coprocessor register transfer C cycle respectively MCR instructions take 1S bl 1C incremental cycles to execute where b is the number of cycles spent in the coprocessor busy wait loop 3 16 5 ASSEMBLER SYNTAX lt gt p lt expression1 gt Rd cn cm lt expression2 gt MRC Move from coprocessor to ARM9TDMI register L 1 MCR Move from ARM9TDMI register to coprocessor L 0 cond Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor lt expression1 gt Evaluated to a constant and placed in the CP Opc field Rd An expression evaluating to a valid ARM9TDMI register number cn and cm Expres
399. is clock enable signal for SDRAM nSDWE nWE16 1 phot20 Not Write Enable for SDRAM or 16 bit ROM SRAM This signal is always used as write enable of SDRAM and is used as write enable of only 16 bit ROM SRAM Flash That is It is not enabled for 8 bit Memory ELECTRONICS 1 15 PRODUCT OVERVIEW S3C2500B Table 1 1 S3C2500B Signal Descriptions Continue Group PinName Pin Type PadType Description Memory nEWAIT 1 phicu Not External wait signal Interface This signal is activated when an external I O 80 device or ROM SRAM Flash banks need more access cycles than those defined in the corresponding control register nRCS 7 0 phot20 Not ROM SRAM Flash External I O Chip select The S3C2500B supports upt to 8 banks of ROM SRAM Flash External I O By controlling the nRCS signals you can map CPU address into the physical memory banks BOSIZE 1 0 2 phic Bank 0 Data Bus Access Size is used for the boot program You use these pins to set the size of the bank 0 data bus as follows 01 Byte 10 Half word 11 2 Word and 00 reserved 1 phot20 Not output enable Whenever a memory read access occurs the nOE output controls the output enable port of the specific memory device nWBE 3 0 4 phot20 Not write byte enable or DQM for SDRAM 3 0 Whenever a memory write access occurs the DQN 3 0 nWBE output controls the write enable port of the specific memory device DQM is data
400. is in progress the USB waits until the transmission is complete before the FIFO is flushed If two packets are loaded into the FIFO only the top most packet one that was intended to be sent to the host is flushed and the corresponding IINRDY bit for that packet is cleared 28 In mode SenD This bit is valid only when endpoint 3 is set to IN STALL ISDSTALL The MCU writes a 1 to this register to issue a STALL handshake to the USB The MCU clears this bit to end the STALL condition 29 In mode SenT This bit is valid only when endpoint 3 is set to IN STALL ISTSTALL The USB sets this bit when a STALL handshake is issued to an IN token due to the MCU setting SEND STALL bit When the USB issues a STALL handshake IINRDY is cleared 30 In mode CLear This bit is valid only when endpoint 3 is set to IN data TOGgle When the MCU writes a 1 to this bit the data toggle ICLTOG bit is cleared This is a write only register 10 38 ELECTRONICS S3C2500B 31 30 29 28 27 26 25 24 23 22 gt 0 10 0 rrepoaonuno gt gt 100900 rocrmm 3 0 MAXP value MAXP 3 0 value x 8 max packet size 6 4 Reserved 7 MAXP value SETting enable MAXPSET 0 value isn t changed 1 2 MAXP value is changed 8 OUT ISO mode OISO 0 Bulk interrupt mode 1 2 ISO mode 9 OUT AuTo CLeaR OATCLR 0 No operation 1 Auto clearing ORDY when FIFO data unloaded
401. is on processing the SRack bit of the PCLKDIS is deasserted and if the self refresh mode change is completed the SRack bit is asserted To recover from the self refresh mode to normal operation mode the SRack bit should be checked asserted before access the SDRAM ELECTRONICS 5 45 MEMORY CONTROLLER S3C2500B 5 7 8 BASIC OPERATION SDRAM initialization sequence On power on reset software must initialize the SDRAM controller and each of the SDRAM connected to the controller Refer to the SDRAM data sheet for more detailed information on the start up procedure for the SDRAM used Typical example sequence is given below Wait 200us to allow SDRAM power and clocks to stabilize Program the INIT 1 0 of the CMDREG to 01 This automatically issues a PALL command to the SDRAM Write OxF into the refresh timer register This provides a refresh cycle every 15 clock cycles Wait for a time period equivalent to 120 clock cycles 8 refresh cycles Program the CFGREG to their normal operation values Program the INIT 1 0 to 10 This automatically issues a MRS command to the SDRAM Program the INIT 1 0 to 00 The controller enters the normal mode Program the CMDREG and WBTOREG to their normal operation values 1 2 3 4 5 Program the normal operational value into the refresh timer 6 7 8 9 10 The SDRAM is now ready for normal operation 5 46 ELECTRONICS S3C2500B MEMORY CONTROLLER 5 7 9 SDRAM SPECIAL REGISTERS The address a
402. ise if data are transferred by CPU the 2 word transaction DESCON 7 is one is recommended IF DESCON 3 is zero the 17 written data is the left half of data to be encrypted decrypted bit 1 32 The second one is the right half of data to be encrypted decrypted bit 33 64 Otherwise if DESCON 3 is one the 1 written data is the right half of data to be encrypted decrypted bit 33 64 The second one is the left half of data to be encrypted decrypted bit 1 32 The byte order in the DESINFIFO is LSB first That is the LSB byte is stored to DESINFIFO 31 24 If you need to swap the byte order you can control it by using DESCON 10 If DESCON 10 is set the written data to the DESINFIFO is automatically byte swapped Otherwise the written data have the original byte order Table 11 15 DES 3DES Output Data FIFO Description 31 0 DESOUTFIFO This FIFO can be read by CPU or DMA depends on control register value This FIFO consists of 8 words If data are transferred by DMA the 4 word burst transaction DESCON T is zero and is one is recommended Otherwise if data are transferred by CPU the 2 word transaction DESCON 7 is one is recommended If DESCON 3 is zero the 1 read data is the left half of data encrypted decrypted bit 1 32 The second one is the right half of data encrypted decrypted bit 33 64 Otherwise if DESCON 3 is one the 1 read data is the right half of data encrypted decrypted bit 33
403. isters 6 Overflow in signed multiply accumulate with a 64 bit result SMULL i ADDS RI RI Ra1 ADC Rh Rh Ra2 BVS overflow 3 to 6 cycles Lower accumulate Upper accumulate 1 cycle and 2 registers NOTE Overflow checking is not applicable to unsigned and signed multiplies with a 64 bit result since overflow does not occur in such calculations 3 18 2 PSEUDO RANDOM BINARY SEQUENCE GENERATOR It is often necessary to generate pseudo random numbers and the most efficient algorithms are based on shift generators with exclusive OR feedback rather like a cyclic redundancy check generator Unfortunately the sequence of a 32 bit generator needs more than one feedback tap to be maximal length i e 2 32 1 cycles before repetition so this example uses a 33 bit register with taps at bits 33 and 20 The basic algorithm is newbit bit 33 eor bit 20 shift left the 33 bit number and put in newbit at the bottom this operation is performed for all the newbits needed i e 32 bits The entire operation can be done in 5 S cycles TST Rb Rb LSR 1 MOVS Rc Ra RRX ADC Rb Rb Rb EOR Rc Rc Ra LSLit 2 EOR Ra Rc Re LSR3E20 Enter with seed in Ra 32 bits Rb 1 bit in Rb Isb uses Rc Top bit into carry 33 bit rotate right Carry into Isb of Rb involved similarly involved new seed in Ra Rb as before 3 18 3 MULTIPLICATION BY CONSTANT USING THE BARREL SHIFTER Multiplication by 2 n 1 2 4 8 1
404. it 30 one clock missing When operating in FM Manchester mode the DPLL sets this bit to 1 if it DPLLOM does not detect an edge in its first attempt You can clear this bit by writing a 1 to this bit 31 DPLL two clock missing When it is operating in the FM Manchester mode the DPLL sets this bit DPLLTM to 1 if it does not detect an edge in two successive attempts At the same time the DPLL enters Search mode In NRZ NRZI mode and while the DPLL is disabled this bit is always 0 You can clear this bit by writing a 1 to this bit ELECTRONICS 8 39 HDLC CONTROLLER S3C2500B 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 zZorrvo ooox 2 3 0 Rx remaining bytes RxRB At 1 word boundary At 4 word boundary 0000 Valid data byte is 1 0000 Valid data byte is 1 0001 Valid data byte is 2 0010 Valid data byte is 3 0011 Valid data byte is 4 1111 Valid data byte is 16 4 Tx frame complete TxFC 0 Normal operation 1 Automatically set if two conditions are met 1 Tx FIFO is empty 2 An abort or a closing flag is transmitted 5 Tx FIFO available TxFA 0 Tx FIFO is not available 1 Tx FIFO is available that is the data to be transmitted can now be loaded into the Tx FIFO 6 Tx clear to send TxCTS 0 Level at the nCTS input pin is High 1 Level at the nCTS input pin is Low 7 Tx stored clear to send
405. it receive e Insertion of one or two Stop bits per frame e Selectable 5 bit 6 bit 7 bit 8 bit data transfers e Parity checking DES 3DES Accelerator e DES or Triple DES mode e ECB or CBC mode e Encryption or decryption support e General DMA support ELECTRONICS PRODUCT OVERVIEW General DMA Channels e Six channels e Memory to memory data transfer e Memory to peripheral data transfer high speed UART DES and USB controller e Support for four external requests from GDMA request pins XGDMA Req0 xGDMA Six Programmable Timers e Interval or toggle mode operation Hardware Watchdog Timer e Useful for periodic reset or interrupts Programmable Interrupt Controller 39 programmable interrupt sources e 33internal sources and 6 external sources programmable priority control Programmable I O port Controller e 64 programmable ports e individually configurable to input output or I O mode for dedicated signals e 6 external interrupt request e 4 external request e 4 external acknowledge e timer outputs e 14 UART signals e 22 HDLC signals 1 3 PRODUCT OVERVIEW 1 2 FEATURES Continue 2 Controller e Master mode operation only Baud rate generator for serial clock Four PLLs for System Core USB and PHY Clock Each PLLO for ARM940T e The Input frequency is 10MHz e Provide up to 166MHz output to ARM940T PLL1 for system c
406. it timers TMOD register settings are described in Figure 17 3 Table 17 1 TMOD Register 17 4 ELECTRONICS S3C2500B 0 Timer 0 enable TEO 0 Disable timer 0 1 Enable timer 0 1 Timer 0 mode selection TMDO 0 Interval mode 1 Toggle mode 2 Timer 0 initial TOUTO value TCLRO 0 Initial TOUTO is 0 toggle mode 1 Initial TOUTO is 1 in toggle mode 3 Timer 1 enable TE1 0 Disable timer 1 1 Enable timer 1 4 Timer 1 mode selection TMD1 0 Interval mode 1 Toggle mode 5 Timer 1 initial TOUT1 value TCLR1 0 Initial TOUT1 is 0 toggle mode 1 Initial TOUT1 is 1 in toggle mode 6 Timer 2 enable TE2 0 Disable timer 2 1 Enable timer 2 7 Timer 2 mode selection TMD2 0 Interval mode 1 Toggle mode 8 Timer 2 initial TOUT2 value TCLR2 0 Initial 2 is 0 in toggle mode 1 Initial TOUT2 is 1 in toggle mode 32 BIT TIMERS M Xr 9 Timer 3 enable 0 Disable timer 3 1 Enable timer 3 10 Timer 3 mode selection TMD3 0 Interval mode 1 Toggle mode 11 Timer 3 initial TOUTS value TCLR3 0 Initial is 0 toggle mode 1 Initial TOUTS is 1 in toggle mode 12 Timer 4 enable 4 0 Disable timer 4 1 Enable timer 4 13 Timer 4 mode selection TMD4 0 Interval mode 1 Toggle mode 14 Timer 4 initial TOUT4 value TCLR4 0 Initial TOUT4 is 0 in toggle mode 1 Initial TOUT4 is 1 in toggle mode
407. ith address in Ra 32 bits uses Rb Rc result in Rd Note d must be less than c e g 0 1 Get word aligned address Get 64 bits containing answer Correction factor in bytes how in bits and test if aligned Produce bottom of result word if not aligned Get other shift amount Combine two halves to get result 3 63 INSTRUCTION SET S3C2500B 3 19 THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16 bit versions of ARM instruction sets 32 bit format The ARM instructions are reduced to 16 bit versions Thumb instructions at the cost of versatile functions of the ARM instruction sets The thumb instructions are decompressed to the ARM instructions by the Thumb decompressor inside the ARM9TDMI core As the Thumb instructions are compressed ARM instructions the Thumb instructions have the 16 bit format instructions and have some restrictions The restrictions by 16 bit format is fully notified for using the Thumb instructions 3 19 1 FORMAT SUMMARY The THUMB instruction set formats are shown in the following figure 15 14 13 12 11 O o o Op ofses Move Shite register Add subtract Offset8 Move compare add subtract immediate ALU operations H2 Hi regiter operations branch exchange Word8 PC relative load Load store with register offset 1 1 H S 1 Load store sign extended byte halfword eel eee 35 sa with immediate offset
408. ke transmitted 10 in out MODE setting MODE 23 OUT CLear data TOGgle OCLTOG 0 Indexed endpoint set to OUT 0 No operation 1 Indexed endpoint set to IN 1 Data toggle flag set to 0 11 IN ISO mode 5 24 IN IN packet ReaDY IINRDY 0 Bulk interrupt mode 0 Not ready for IN operation 1 2 ISO mode 1 Ready for IN operation 12 IN AuTo SET IATSET 25 IN fifo Not EMPty INEMP 0 No operation 0 No data packet in FIFO 1 Auto setting when MAXP sized packet loaded 1 There is at least one packet of data in FIFO 14 13 Reserved 26 IN UNDER run IUNDER 0 No operation 15 CSR2 SETting enable CSR2SET 1 Received IN token but not ready ISO 0 USBEP2CSR 12 8 isn t changed 1 USBEP2CSR 12 8 is changed 27 IN Fifo FLUSH IFFLUSH 0 No operation 16 OUT Out packet ReaDY OORDY 1 FIFO flush 0 Not received data packet 1 Received packet from host 28 IN SenD STALL ISDSTALL 0 No operation 17 OUT Fifo FULL OFFULL 1 Stall handshake transmit state 0 Normal operation 1 FIFO full state 29 IN SenT STALL ISTSTALL 0 No operation 18 OUT OVER run OOVER 1 Stall handshake transmitted 0 Normal operation 1 Data received at FIFO full state ISO 30 IN CLear TOGgle ICLTOG 0 No operation 1 Data toggle flag set to 0 31 Reserved Figure 10 14 USBEP2CSR Register 10 34 ELECTRONICS S3C2500B USB CONTROLLER
409. l 2 8 of the buffer and so on through 100 which means wait to fill 4 8 of the BDMA Tx Buffer NOTE Ifthe last data of the frame arrives in BDMA Tx Buffer the data transfer from the BDMA Tx Buffer to the MAC TxFIFO starts immediately regardless of the level of these bits Tx Byte Swapping Use to prevent disorder of byte sequence when memory operate BTxBSWAP on big endian format and byte unit access If this bit is set the transferring byte is swapped 2 1 0 B0 B1 B2 B3 7 8 Not applicable 9 j Fadorialtestbit 10 BDMA Tx enable BTxEn When the Tx enable bit is set to 1 the BDMA Tx block is enabled Even if this bit is disabled buffer data will be moved to the MAC TxFIFO until the BDMA TxBUFF underflows This bit is automatically cleared when the BDMA is not the owner NOTE The BDMATXDPTR register must be assigned before this bit is set 11 BDMA Tx reset BTxRS Set this bit to 1 to reset the BDMA Tx block 81 121 Reserved 1 emp ELECTRONICS 7 15 ETHERNET CONTROLLER S3C2500B 7 4 1 2 Buffered DMA Receive Control Register Table 7 6 BDMA RXCON Register BDMARXCONA 0xF00A0004 Buffered DMA receive control register 0x00000000 BDMARXCONB 0xF00C0004 Buffered DMA receive control register 0x00000000 Table 7 7 BDMA Receive Control Register Description BDMA Rx Number of You can select number of buffer descriptor Buffer 0000 2 0001 2 0010
410. l be Bulk mode 1 Endpoint 1 will be ISO mode Default 0 Out mode AuTo This bit is valid only when endpoint 4 is set to OUT CLeaR If set whenever the MCU unloads last data in OATCLR endpoint 1 FIFO OORDY will automatically be cleared without any intervention form MCU Default 0 in out MODE 0 Transfer direction will be OUT selection MODE 1 Transfer direction will be IN Default 1 IN In mode ISO mode This bit is valid only when endpoint 4 is set to IN 150 0 Endpoint 4 will be Bulk mode 1 Endpoint 4 will be ISO mode Default 0 10 40 ELECTRONICS S3C2500B USB CONTROLLER Table 10 24 USBEPACSR Register Description Continued In mode AuTo SET IATSET This bit is only valid only when endpoint 4 is set to IN If set whenever the MCU writes MAXP data IINRDY will be automatically be set without any intervention from MCU If the MCU writes less than MAXP data then IINRDY bit has to be set by the MCU Default 0 MN I 1 5 CSR2 SETtable CSR2SET 16 Out mode Out packet ReaDY OORDY 17 Out mode Fifo FULL OFFULL 18 Out mode fifo OVER run OOVER 19 Out mode Data ERRor ODERR 20 Fifo FLUSH OFFLUSH up ELECTRONICS 0 USBEPACSR 12 8 isn t overwritten when MCU writes a 32bit value to USBEPACSR register 1 USBEPACSR 12 8 is overwritten This bit is valid only when endpoint 4 is set to OUT The USB sets this bit once
411. l mask bit G corresponds to an external interrupt source When a source interrupt mask bit is 1 the interrupt is not serviced by the ARM940T when the corresponding interrupt request is generated If the mask bit is 0 the interrupt is serviced upon request And if global mask bit bit 31 is 1 no interrupts include internal and external interrupts are serviced After the global mask bit is cleared the interrupt is serviced The 7 interrupt sources are mapped as follows 6 IOM2 interrupt 0 non Masking 1 Masking 5 EXT 5 interrupt 4 EXT 4 interrupt 3 EXT 3 interrupt 2 EXT 2 interrupt 1 EXT 1 interrupt 0 EXT 0 interrupt 31 Global interrupt mask bit 0 Enable all interrupt requests 1 Disable all interrupt requests Figure 16 4 External Interrupt Mask Register EXTMASK ELECTRONICS 16 7 INTERRUPT CONTROLLER S3C2500B 16 4 3 INTERRUPT PRIORITY REGISTERS The interrupt priority registers INTPRIORO INTPRIORS contain information about which interrupt source is assigned to the pre defined interrupt priority field Each INTPRIORn register value determines the priority of the corresponding interrupt source The lowest priority value is 0 0 and the highest priority value is 0x26 The index value of each interrupt source is written to one of the above 39 positions see Figure 16 5 The position value then becomes the written interrupt s priority value The index value of each interrupt source is listed in Table
412. l of the 4 word transfer mode bit Tx4WD HCON When you select 1 word transfer mode not 4 word select mode one word can be loaded into the HTxFIFO assuming the TxFA bit is set to 17 When you select 4 word transfer mode four successive words can be transferred to the FIFO if the TxFA bit is set to 1 The nCTS clear to send input nRTS request to send and nDCD data carrier detect are provided for a modem or other hardware peripheral interface In auto enable mode nDCD becomes the receiver enable However the receiver enable bit must be set before the nDCD pin is used in this manner The TxFC status bit in HSTAT can cause an interrupt to be generated upon frame completion This bit is set when there is data HTxFIFO and when the closing flag or an abort is transmitted NOTE You can use Transmitter Interrupt mode or Transmitter DMA mode for transmitting the frame Transmitter Interrupt mode writes tx data to TxFIFO by CPU Transmitter DMA mode writes tx data to TxFIFO by HDMA NOTE If you use Transmitter Interrupt mode then you must set the Preamble TxNoCRC Little Endian mode to HCON 23 HCON 26 and HMODE 5 If you use Transmitter DMA mode then you must set the Preamble TxNoCRC Little Endian mode to Transmit Buffer Descriptor 8 14 ELECTRONICS S3C2500B HDLC CONTROLLER 8 5 4 1 Transmitter Interrupt Mode The first byte of a frame the address field should be written into the Tx FIFO at the
413. le to Input Output or Mode for Dedicated Signals e 6 External Interrupt Requests e 4 External GDMA Requests 4 External Acknowledges e 6 Timer Outputs e 22 HDLC Signals e 14 UART Signals NOTE PP 27 PP 18 ports support external software reset When PP 27 18 are in GPIO output mode and when nRESET or system reset including watchdog reset is asserted the external devices that are connected to PP 27 18 are also reset That is the output signals go low and rise back to high ELECTRONICS 15 1 VO PORTS S3C2500B 15 3 PORT SPECIAL REGISTER Table 15 1 I O Port Special Registers OxF0030014 port special function register for external 0x00000000 interrupt 15 3 1 PORT MODE SELECT REGISTER IOPMODE1 2 If you set 1 2 registers to GPIO then IOPMODE1 2 registers should determine whether input or output mode for each port Table 15 2 IOPMODE1 2 Registers RW IOPMODE1 0xF0030000 R W port mode select register for port 0 to 31 OxFOOSFFFF IOPMODE2 OxF0030004 R W port mode select register for port 31 to 63 OxFFFFFFFF 15 2 ELECTRONICS S3C2500B VO PORTS 31 30 29 28 27 26 25 24 23 22 21 2019 18 17 16 1514 13 1211109 8 7 6 5 4 3 2 1 xDDD DDD XP DD 31 30 29 28 27 26 25 24 23 22 21 2019 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bp e See Note on 15 1 ELECTRONICS NOTE 1 2 registers bit value 1 is
414. length of the frame is 64 bytes receiving CRC is correct operation field specifies a Pause operation When a full duplex pause operation is recognized the MAC receive circuit loads the operand value into the pause count register It then signals both the MAC and the BDMA engine that the pause should begin at the end of the current frame if any The pause circuit maintains the pause counter and decrements it to zero It does this before it signals the end of the pause operation and before allowing the transmit circuit to resume its operation If a second full duplex pause operation is recognized while the first operation is in effect the pause counter is reset with the current operand value Note that a count value of zero may cause pre mature termination of a pause operation that is already in progress 7 5 3 2 Remote Pause Operation To send a remote pause operation follow these steps Program CAM location 0 with the destination address Program CAM location 1 with the source address Program CAM location 18 with length type field opcode and operand Program the 2 bytes that follow the operand with 0000H Program the three double words that follow CAM location 18 with zeros og pwn Write the transmit control register to set the MSdPause bit The destination address and source address are commonly used as the special broadcast address for MAC control frames and the local station address respectively
415. ll sa su uu e Mae ee ie 10 8 10 6 USBFA meter teret 10 11 10 7 Ucisi Miti 10 13 10 8 m 10 16 10 9 USBINTRE 10 18 10 10 EE 10 19 10 11 USBDISCONN nnns 10 21 10 12 USBEPOGSR RECEN E 10 24 10 13 USBEPi1CSR Beglslet u l ERE RE 10 29 10 14 USBEP2GSR Registe eee ERE HERR RACER 10 34 10 15 USBEPSGSR H6glsler AUR RE E S NEE 10 39 10 16 USBEPACSR i epe poetae EE Ade n RETE 10 44 10 17 NU SBWOEPOBSOISIEE u a 10 46 10 18 Registe raras naen en See ee rp 10 48 10 19 USBWOEP2 BRSOISIBL oot tr emet P INED EET 10 50 10 20 WSBWCEPRS REGISICD aee pitt Se ee irri ma de E 10 52 10 21 Uu SBWOEPAHBSOISIOE SS EIE 10 54 10 22 05 0 1 2 3 4 Registers 2201 10 56 11 1 DES 3DES BIoCk DIAQtFalm scene EER EE RA 11 2 S3C2500B RISC MICROCONTROLLER xxi Figure Number 12 1 12 2 12 3 12 4 12 5 12 6 12 7 List of Figures continued Title Page Number Controller Block
416. lock e The Input frequency is 10MHz e Provide up to 133MHz output to system PLL2 for USB e The input frequency is 10MHz e Provide 48MHz output to USB 1 4 53 2500 PLL3 for PHY e input frequency is 10MHz e Provide 20MHz or 25MHz output to external PHY chip Operating Voltage Range e Internal Power 1 8V 5 e Power 3 3V 5 Operating temperature range 40 85 e 272 BGA ELECTRONICS S3C2500B 1 3 BLOCK DIAGRAM 10 100 Ethernet DMA MAC 10 100 Ethernet DMA MAC TSA HDLC Gi Memory Controller 8 bank Flash ROM SRAM Ext External REQ ACK Bus Master PRODUCT OVERVIEW 4KB D Cache ARM940T 166 MHz 4KB D Cache Console Interrupt UART Controller 27 GPIOs Function Timers Clock Gen amp Reset with 4 PLLs Figure 1 1 S3C2500B Block Diagram ELECTRONICS 1 5 S3C2500B PRODUCT OVERVIEW 1 4 PACKAGE DIAGRAM z gt E A1 ball pad corner 2 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 1 OOO OOO OU 9131909 910 01919 GOD DIO OOOO 91919101 91910193 919 919 oO qa a 9 60 919 s 9 01 91 0181919 649016 95 019 9 9 G 91010100 n e 01019 919 919 ele ODD OO 31678 61678 V 2 Jd M L A Figure 1 2 S3C2500B Pin Assignment Diagram ELECTR
417. lock frequency 4 9 6 AHB BUS MASTER PRIORITY REGISTER HPRIF OxF0000014 AHB bus master fixed priority register 0x00543210 HPRIR OxF0000018 AHB bus master round robin priority register 0x00000000 ELECTRONICS 4 21 SYSTEM CONFIGURATION S3C2500B 4 9 7 CORE PLL CONTROL REGISTER CPLLCON If you want to use this register you should set CPLLREN in SYSCFG 31 to 1 This register doesn t work with CPLLREN set to 0 CPLLCON OxF000001C Core PLL control register 0x0001039E ix p Output clock frequency is determined by following formula Fout Fin x M 8 2 x 2 S If Fin 10MHz P 3 M 158 0 9 and S 1 Fout is 166 MHz signal of ARM940T core is connected to Fout 166MHz clock But BCLK signal of ARM940T and system bus clock is connect to Fout 2 66 MHz clock 4 22 ELECTRONICS S3C2500B SYSTEM CONFIGURATION 4 9 8 SYSTEM BUS PLL CONTROL REGISTER SPLLCON If you want to use this register you should set SYSCFG 30 to 1 This register doesn t work with SPLLREN set to 0 SPLLCON 0xF0000020 System BUS PLL control register 0x0001037D P tres Output clock frequency is determined by following formula Fout Fin x M 8 P 2 x 2 S If Fin 10MHz P 3 M 125 0x7D and S 1 Fout is 133 MHz signal of ARM940T core is connected to Fout 133MHz clock But BCLK sign
418. ls LINK 10M is shared with RX DV and used to convey the link status of the 10 Mbit s endec The value is stored in a status register ERR 1 1 phisd Receive Error PHY asserts synchronously whenever it detects a physical medium error e g a coding violation PHY asserts RX ERR only when it asserts RX DV 1 24 ELECTRONICS S3C2500B PRODUCT OVERVIEW Table 1 1 S3C2500B Signal Descriptions Continue HDLCO HTXDO DU er 2 Data Upstream Open Drain Output and 8 schmit trigger input HDLC Ch 0 Transmit Data The serial data output from the transmitter is encoded in NRZ NRZI FM Manchester data format HRXDO DD phbsud4 2 Data Down Stream Open Drain Output and schmit trigger input HDLC Ch 0 Receive Data The serial data input should be coded in NRZ NRZI FM Manchester data form at The data should not exceed the rate of the 53 2500 internal master clock HnDTRO BCL phbst8 2 bit clock 768 KHz GPIO42 HDLC Ch 0 Data Terminal Ready output indicates that the data terminal device is ready for transmis sion and reception General I O Port HnRTSO STRB phbst8 2 Data Strobe 8 KHz programable signal GPIO43 for selecting an 8 bit timeslot or 16 bit timeslot HDLC Ch 0 Request To Send The nRTSO output is controlled by the Tx Request to send control bit When the TXRTS bit is set to 1 the nRTS output is driven log When the TxRTS bit is clear to 0 the nRTS output remain
419. met 1 there is no data in the Tx FIFO and 2 either an abort or a closing flag is transmitted You can clear this bit by writing 1 to this bit If this bit is 1 the data to be sent can be loaded into the HTxFIFO register In 1 word transfer mode the TxFA status bit is set to 1 when the first register of the HTxFIFO is empty In 4 word transfer mode TxFA 1 when the first four 32 bit registers of the HTxFIFO are empty The TxFA status condition is automatically cleared when HTxFIFO is no longer available During DMA Tx operation this bit is always 0 so not generating interrupt The nCTS input is projected to this status bit If the level at the nCTS input pin is Low this status bit is 1 If nCTS input pin is High level TxCTS is 0 This bit does not generate an interrupt This bit is set to 1 each time a transition in nCTS input occurs You can clear this bit by writing 1 to this bit When the transmitter runs out of data during a frame transmission an underrun occurs and the frame is automatically terminated by transmitting an abort sequence The underrun condition is indicated when TxU is 1 You can clear this bit by writing a 1 to this bit This status bit indicates when the data received can be read from the Rx FIFO When RxFA is 1 it indicates that data other than an address or a final data word is available in the HRXFIFO In 1 word transfer mode RxFA bit set to 1 when received data is available in
420. mmon Status 10 35 10 5 11 USB Endpoint 4 Common Status 10 40 10 5 12 USB Write Count for Endpoint 0 Register n 10 45 10 5 13 USB Write Count for Endpoint 1 10 47 10 5 14 USB Write Count for Endpoint 2 10 49 10 5 15 USB Write Count for Endpoint 2 22200400000 10 51 10 5 16 USB Write Count for Endpoint 4 02024 0001 00 10 53 10 5 17 USB Endpoint 0 1 2 3 4 FIFO 10 55 S3C2500B RISC MICROCONTROLLER Table of Contents Continued Chapter 11DES 3DES 11 1 Overview 11 2 Feature 11 3 DES 3DES Special Registers 11 3 1 DES 3DES Control Register 11 3 2 DES 3DES Status Register 11 3 3 DES 3DES Interrupt Enable Register 11 3 4 DES 3DES Run Enable Register 11 3 5 DES 3DES Key1 Left Right Side Register 11 3 6 DES 3DES Key 2 Left Right Side Register 11 3 7 DES 3DES Key 3 Left Side Register 11 3 8 DES 3DES IV Left Right Side Register 11 3 9 DES 3DES Input Output Data FIFO Register 11 4 DES 3DES 11 5 Performance Calculation Guide Chapter 12GDMA Controller 12 1 Overview 12 2 Fealife s iau rta bata fata uta 12 9 GDMA Special Heglsters
421. mount is in the range 1 to 32 and see above NOTE The zero in bit 7 of an instruction with a register controlled shift is compulsory a one in this bit will cause the instruction to be a multiply or undefined instruction ELECTRONICS 3 15 INSTRUCTION SET S3C2500B 3 5 3 IMMEDIATE OPERAND ROTATES The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value This value is zero extended to 32 bits and then subject to a rotate right by twice the value in the rotate field This enables many common constants to be generated for example all powers of 2 3 5 4 WRITING TO R15 When Rd is a register other than R15 the condition code flags in the CPSR may be updated from the ALU flags as described above When Rd is R15 and the S flag in the instruction is not set the result of the operation is placed in R15 and the CPSR is unaffected When Rd is R15 and the S flag is set the result of the operation is placed in R15 and the SPSR corresponding to the current mode is moved to the CPSR This allows state changes which atomically restore both PC and CPSR This form of instruction should not be used in User mode 3 5 5 USING R15 AS AN OPERAND If R15 the PC is used as an operand in a data processing instruction the register is used directly The PC value will be the address of the instruction plus 8 or 12 bytes due to instruction prefetching If the shift amount is specified in the
422. must ignore an OUT token Function endpoints are addressed using two fields the function address field and the endpoint field The function address ADDR field specifies the function via its address that is either the source or destination of a data packet depending on the value of the token PID Cyclic redundancy checks CRCs are used to protect all non PID fields token and data packets In this context these fields are considered to be protected fields The PID is not included in the CRC check of a packet containing a CRC All CRCs are generated over their respective fields in the transmitter before bit stuffing is performed Handshake packets are used to report the status of a data transaction and can return values indicating successful reception of data command acceptance or rejection flow control and halt conditions 10 4 ELECTRONICS S3C2500B USB CONTROLLER 7 bits 4 bits 5 bits ADDR ENDP CRC5 Token In Out 0 1023 bytes 16 bits DATA CRC16 Data Toggle Handshake Low Speed Preamble 11 bits 5 bits CRC5 Start of Frame Figure 10 3 USB Frame Format 10 3 4 BIT STUFFING AND NRZI CODING The USB employs NRZI data encoding when transmitting packets In NRZI encoding a 1 is represented by no change in level and a 0 is represented by a change in level The high level represents the J state on the data lines encoding and J state means that D is 5V and D is OV A string of zeros causes the
423. n Rn lt expression offset of lt expression gt bytes I write back the base register set the W bit if is present Rn is an expression evaluating to a valid ARM9TDMI register number NOTE If Rn is R15 the assembler will subtract 8 from the offset value to allow for ARM9TDMI pipelining Examples LDC p1 c2 table Load c2 of coproc 1 from address table using a PC relative address STCEQL p2 c3 R5 24 Conditionally store c3 of coproc 2 into an address 24 bytes up from R5 write this address back to R5 and use long transfer option probably to store multiple words NOTE Although the address offset is expressed in bytes the instruction offset field is in words The assembler will adjust the offset appropriately ELECTRONICS 3 55 INSTRUCTION SET S3C2500B 3 16 COPROCESSOR REGISTER TRANSFERS MRC MCR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 27 This class of instruction is used to communicate information directly between ARM9TDMI and a coprocessor An example of a coprocessor to ARM9TDMI register transfer MRC instruction would be a FIX of a floating point value held in a coprocessor where the floating point number is converted into a 32 bit integer within the coprocessor and the result is then transferred to ARM9TDMI register A FLOAT of a 32 bit value ARM9TDMI register into a floating point v
424. n abort The transmitter aborts a frame by sending at least eight consecutive 1s immediately after the abort transmitter control bit TXABT in HCON is set to 1 Setting this control bit automatically clears the HTxFIFO The abort sequence can be extended up to at least 16 consecutive 1s by setting the abort extend control bit in HCON to 1 This feature is useful for forcing the mark idle state The receiver interprets the reception of seven or more consecutive 1s as an abort The receiver responds the abort received as follows abort in an out of frame condition an abort has no meaning during the idle or the time fill An abort in frame after less than 25 bits are received after an opening flag under this condition no field of the aborted frame is transferred to the HRXFIFO The HDLC module clears the aborted frame data in the receiver and flag synchronization The aborted reception is indicated in the status register abort in frame after 25 bits or more are received after an opening flag in this condition some fields of the aborted frame may be transferred to the HRXFIFO The abort status is set in the status register and the data of the aborted frame in the HRXFIFO is cleared Flag synchronization is also cleared and the DMA operation for receiving is aborted too 8 4 4 IDLE AND TIME FILL When the transmitter is not transmitting a frame it is in an idle state The transmitter signals
425. n afford PCM highway multiplexed interface to multiplex data from each HDLC channel on HDLCB pad interface In DCE interface the internal HDLC can directly be connected to the external serial interface In PCM highway and 2 interface the TSA is located between the HDLC and the external serial interface By intervening in between the TSA provides the appropriate HDLC clocks during its programmed timeslot within an 8 KHz frame The TSA can support a maximum data rate of up to 10 Mbps with HDLOs In PCM highway interface up to 156 time slots can be supported with credible data transfer Although the 53 2500 can support up to 4096 bit positions 12bit programmable this requires a lower frequency of FSC or a high frequency of clock rates The 2 is pin multiplexed with HDLCA pins and the PCM highway multiplexed is pin multiplexed with HDLCB pin interface and the HDLCC pins are dedicated to DCE interface 9 4 2 TSA BLOCK DIAGRAM DCE IOM2 PCM non multiplexed interface DCE PCM multiplexed PCM non multiplexed interface DCE PCM non multiplexed interface Figure 9 6 TSA Block Diagram ELECTRONICS 9 9 IOM2 CONTROLLER S3C2500B 9 4 3 HDLC EXTERNAL PIN MULTIPLEXED SIGNALS HDLC external pins are multiplexed among the various operating modes The Mode bits in TSAxCON determines operating mode of each TSA and HDLC external pins are automatically configured according to Mode bits as follows Table 9 1 HDLC Ex
426. n and data lockdown registers These registers allow regions of the cache to be locked down The opcode 2 field determines whether the instruction or data caches are programmed e fthe opcode 2 field 0 the data lockdown bits are programmed For example MCR MRC p15 0 Rd c9 c0 0 data lockdown control e fthe opcode 2 field 1 the instruction lockdown bits are programmed For example MCR MRC p15 0 Rd c9 cO 1 instruction lockdown control The format of the registers Rd transferred during this operation is shown below All defined bits in the control register are set to zero at reset Table 2 21 Lockdown Register Format Function NOTE The segment number is not specified because cache lines are locked down across all four segments 16 word granularity ELECTRONICS 2 31 PROGRAMMER S MODEL 3C2500B 2 16 1 10 Register 15 Test debug register The DTRRobin and ITRRobin bits set the respective caches into a pseudo round robin replacement mode All defined bits in the control register are set to zero at reset Table 2 22 CP15 Register 15 Function 2 16 1 11 Reserved Registers Accessing a reserved register is unpredictable 2 32 ELECTRONICS S3C2500B INSTRUCTION SET INSTRUCTION SET 3 1 INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set and the THUMB instruction set in the ARM9TDMI core 3 1 1 FORMAT SUMMARY The ARM instruction set formats are s
427. n fetches and data loads and stores may be cached or buffered Cache and write buffer configuration and operation is described in detail in following chapters e registers defined in CP14 are accessible with MCR and MRC instructions These are described in Debug communications channel on page 8 46 e The registers defined CP15 are accessible with MCR MRC instructions These are described in ARM940T CP15 registers on page 2 5 e Registers and operations provided by coprocessors attached to the external coprocessor interface will be accessible with appropriate coprocessor instructions The ARM9TDMI processor core implements ARM Architecture v4T and so executes the ARM 32 bit instruction set and the compressed Thumb 16 bit instruction set The programmer s model is fully described in the ARM Architecture Reference Manual The ARM v4T architecture specifies a small number of implementation options The options selected the ARM9TDMI implementation are listed in Table 2 4 For comparison the options selected for the ARM9TDMI implementation are also shown Table 2 4 ARM9TDMI Implementation Option Processor Core ARM Data Abort Mode Value Stored by Direct Architecture STR STRT STM of PC ARM7TDMI v4T Base updatd Address of Inst 12 4 Address of Inst 12 The ARM9TDMI is code compatible with the ARM7TDMI with two exceptions e The ARM9TDMI implements the base restored data abort model
428. n field bytes are transferred between the CPU and the HDLC module in parallel over the data bus These bytes are transmitted and received LSB first The 16 bit frame check sequence FCS field is however transmitted and received MSB first 8 4 ELECTRONICS S3C2500B HDLC CONTROLLER 8 3 1 3 Address A Field The eight bits that follow the opening flag are called address A field The address field are expendable To extend this address byte simply user defined address write to the station address register To check address byte against the incoming data have to be used the MASK register If match occurred the frame s data including address and CRC 16 bit into the HRXFIFO and then moved to system memory If it is not matched simply discarded S3C2500B allows up to 32 bits address For instance SDLC and LAPB use an 8 bit address LAPD further divides its 16 bit address into different fields to specify various access points one piece of equipment Some HDLC type protocol allows for extended addressing beyond 16 bit 8 3 1 4 Control C Field The eight bits that follow the address field are called the control link control C field The S3C2500B HDLC module treats the control field in the same way as the information field That is it passes the eight bits to the CPU or memory during reception The CPU is responsible for how the control field is handled and what happens to it 8 3 1 5 Information 1 Field The information 1 field follow
429. n is enabled the base address of each memory bank is changed as follows Table 4 1 The Base Address of Remapped Memory Sd afore remap erem 4 5 EXTERNAL ADDRESS TRANSLATION The S3C2500B address bus is in some respects different than the bus used in other standard CPUs Based the required data bus width of each memory bank the internal system address bus is shifted out to an external address bus ADDR 23 0 Data Bus Width External Address Pins ADDR 23 0 Accessible Memory Size A23 A0 internal 16M byte 24 1 internal 8M half word ELECTRONICS 4 3 SYSTEM CONFIGURATION S3C2500B Data bus width configuration 8 16 32 bit HADDR 23 0 External address pins HADDR 24 1 ADDR 23 0 HADDR 25 2 External Internal Figure 4 2 External Address Bus Diagram 4 6 ARBITRATION SCHEME The S3C2500B can support the fixed priority and the round robin method for AHB bus arbitration by register setting Especially the S3C2500B can program the priority order in the fixed priority mode as well as the ratio of the bus occupancy in the round robin priority mode The internal function blocks or AHB bus masters are divided into three groups Group A Group B and Group C Group A has only Test Interface Controller TIC block The Group A has the highest bus priority Group B has 6 AHB bus masters General DMA Ethernet Controller 0 Ethernet Controller 1 HDLC Controller 0 HDLC Controller 1 an
430. n state is 0 the S3C2500B operates in litte endian mode When this pin state is 1 the S3C2500B operates big endian mode 1 14 ELECTRONICS S3C2500B PRODUCT OVERVIEW Table 1 1 S3C2500B Signal Descriptions Continue Group PinName Pin PadType Memory ADDR 23 0 24 Phot20 Address bus Interface ADDR 10 AP The 24 bit address bus covers the full 16 M 80 word address range of each ROM SRAM FLASH and external bank In the SDRAM interface ADDR 14 13 is always used as bank address of SDRAM devices If SDRAM devices with 2 internal bank is used ADDR 13 should be connected to the BA of SDRAM If SDRAM devices with 4 internal bank is used ADDR 14 13 should be connected to the BA 1 0 of SDRAM ADDR 10J AP is the auto precharge control pin The auto precharge command is issued at the same time as burst read or burst write by asserting high on ADDR 10 AP XDATA 31 0 32 phbsut20 External bi directional 32bit data bus The S3C2500B supports 8 bit 16bit 32bit bus with ROM SRAM Flash Ext IO bank but supports 16 bit or 32 bit bus with SDRAM bank nSDCS 1 0 2 phot20 Not chip select strobe for SDRAM Two SDRAM banks are supported nSDRAS 1 phot20 Not row address strobe for SDRAM NSDRAS signal is used for both SDRAM banks nSDCAS 1 phot20 Not column address strobe for SDRAM NSDCAS signal is used for both SDRAM banks CKE 1 phob12 Clock Enable for SDRAM CKE
431. n user devices 9 3 6 TIC BUS One D channel accesses bus TIC bus The TIC function is implemented using 4 bits of the C I2 channel and allows multiple layer2 devices to individually gain access to the D and channels located in the first sub frame ELECTRONICS 9 3 IOM2 CONTROLLER S3C2500B 9 3 7 CHANNEL OPERATION 9 3 7 1 Monitor channel operation The monitor channel is a handshake protocol for high speed information exchange between S3C2500B and other devices The monitor channel operates on an asynchronous basis While data transfers on the bus take place synchronized to frame sync the flow of data is controlled by a handshake procedure using MX monitor transmit and MR monitor receive For example data is placed onto the monitor channel and the MX bit is activated This data will be transmitted repeatedly once per 8 KHz frame until the transfer is acknowledged via the MR bit Transmitter MX MX MD tst byte 1st Byte Acknowledge Receiver MX MD 2nd byte 2nd Byte MX MD Nth byte Acknowledge Nth Byte th byte LL n Acknowledge End of Trnasmission EOM End of Trnasmission MX Monitor transmit bit active low MR Monitor receive bit active low MD Monitor data Figure 9 2 Monitor Channel Handshake Protocol 9 4 ELECTRONICS S3C2500B IOM2 CONTROLLER The monitor protocol is illustrated in figure9 2 Before the data in IOM2MTD register is transmitted The IOM2 contr
432. nable for bank 3 0 disable 1 enable 28 Address Data muxed bus enable for bank 4 0 disable 1 enable 29 Address Data muxed bus enable for bank 5 0 disable 1 enable 30 Address Data muxed bus enable for bank 6 0 disable 1 enable 31 Address Data muxed bus enable for bank 7 0 disable 1 enable Figure 5 12 Muxed Bus Control MUXBCON Register Configuration MBEO MBE1 MBE2 MBE4 5 MBE6 MBE7 100 4 cycles 000 8 cycles 100 4 cycles 000 8 cycles 100 4 cycles 000 8 cycles 100 4 cycles 000 8 cycles 100 4 cycles 000 8 cycles 100 4 cycles 000 8 cycles 100 4 cycles 000 8 cycles 100 4 cycles 000 8 cycles 3C2500B ELECTRONICS S3C2500B MEMORY CONTROLLER 5 6 3 3 Wait Control Register Slow external I O devices requiring a long delay cycles on data read and write should set EWAITENn in the WAITCON register In this case nEWAIT pin should connected to the external device if multiple slow external I O devices are connected to nEWAIT each WAIT signals of external I O devices should be nEWAIT is low active signal When nEWAIT is a low S3C2500B is waiting until nEWAIT is high again nREADY in the WAITCON register is used when the external I O device is ready for transferring data When nREADY is low S3C2500B transfers data In addition Ext controller provides COHDIS in the WAITCON register Wh
433. nactive state in the MR bit This terminates the Monitor channel transmission 9 3 7 2 Transmission error During the transmission process the transmission is aborted only if errors in the MX MR handshake protocol occur An abort is indicated by setting the MR bit inactive for two or more frames The transmitter must react with EOM This situation is illustrated in the following figure9 3 Transmitter MX Receiver MR Abort Request 1 i Figure 9 3 Abortion of Monitor Channel Transmission ELECTRONICS 9 5 IOM2 CONTROLLER S3C2500B 9 3 7 3 Monitor channel collision detection When more than two devices is attached to IOM2 bus the S3C2500B resolves the collision by waiting inactive in the MX MR bits before sending and a per bit check on the transmitted data Monitor channel access priority is determined by the address of the monitor message contained in the first monitor byte transmitted Once the transmitter detects inactive and starts to transmit the first byte a per bit check is performed on each transmitted monitor bit If any bit mismatches the transmitter immediately withdraws from the monitor channel by setting the all remaining bits to 1 the monitor channel collision detection interrupt is generated and the transmitter reverts back to waiting for the idle condition 9 3 7 4 Channel Operation Th
434. nd data bus Ext I O bank controller has three kind of the register for eight banks and then it can be controlled by various timing control options 5 6 1 FEATURES The following is a list of the Ext Bank Controller s features 8 banks ROM SRAM Flash Memory External interface 16M byte maximum address range per bank 24 bit external address pins 32 bit internal and external data bus Various timing control options ELECTRONICS 5 13 MEMORY CONTROLLER 5 6 2 EXTERNAL DEVICE CONNECTION Figure 5 3 illustrates a simple connection between 8 bit ROM Flash and S3C2500B ADDR 23 0 ADDR DATA 7 0 iniit AOE 8 bit nOE ROM nRCS 0 ncs Flash nWBE 0 53 2500 Figure 5 3 8 bit ROM SRAM and Flash Basic Connection S3C2500B ELECTRONICS S3C2500B MEMORY CONTROLLER Figure 5 4 illustrates a example connection between two of 8 bit ROM Flash and S3C2500B for the consisting of 16 bit ROM SRAM Flash ADDR 23 0 717704 SPORES ewe 2 e nwe CS ROM Flash nWE 3C2500B ADDR 23 0 DATA 7 0 8 bit ROM Flash nWBE 1 Figure 5 4 8 bit ROM SRAM and Flash Basic Connection 8 bit Memory x 2 ELECTRONICS 5 15 MEMORY CONTROLLER S3C2500B Figure 5 5 illustrates a connection between 16 bit ROM SRAM and S3C2500B ADDR 23 0 nSDWE hWE16 16 bit u S3C2500B nBE 1 _ byte nBE O y Lower byte Figure 5 5 16
435. nd reset value of the special registers in the SDRAM controller summarized in Table 5 24 Table 5 24 SDRAM Special Registers Address Description Reset value CFGREG OxF0020000 Configuration register 0 00099 0 CMDREG OxF0020004 Command register 0x00000000 REFREG OxF0020008 Refresh timer register 0x00000020 WBTOREG OxF002000C Write buffer time out register 0x00000000 5 3 9 1 Configuration Register The configuration register is 32 bit read write some bits are read only register This register contains SDRAM control parameters such as external bus width memory type and various timing parameters Table 5 25 SDRAM Configuration Register CFGREG oxF0020000 R W SDRAM Configuration register 0 00099 0 ELECTRONICS 5 47 MEMORY CONTROLLER S3C2500B Default value EN 1 external bus width is 16 bit External data bus Width Auto Pre charge control for SDRAM accesses 5 Table 5 25 SDRAM Configuration Register Continue 0 external bus width is 32 bit 0 Auto pre charge 1 No auto pre charge CAS Latency 00 Reserved 01 CL 1 cycle 11 256M bit SDRAM memory devices 11 01 RP 2 cycles 11 RP 4 cycles 1 2 D1 1 0 4 SDRAM device Density of bank 1 00 16M bit SDRAM memory devices 01 64M bit SDRAM memory devices 10 2 128M bit SDRAM memory devices 9 8 Row Pre charge time 00 RP 1 cycle 10 RP 3 cycles X A C 3 2 B 10 CL 2
436. nding register GDMA channel 2 control register GDMA channel 2 source address register GDMA channel 2 destination address register GDMA channel 2 transfer count register GDMA channel 2 run enable register GDMA channel 2 interrupt pending register GDMA channel 3 control register GDMA channel 3 source address register GDMA channel 3 destination address register GDMA channel 3 transfer count register GDMA channel 3 run enable register GDMA channel 3 interrupt pending register GDMA channel 4 control register GDMA channel 4 source address register GDMA channel 4 destination address register GDMA channel 4 transfer count register GDMA channel 4 run enable register GDMA channel 4 interrupt pending register GDMA channel 5 control register GDMA channel 5 source address register GDMA channel 5 destination address register GDMA channel 5 transfer count register GDMA channel 5 run enable register GDMA channel 5 interrupt pending register 0x00000000 0x00543210 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 12 3 GDMA CONTROLLER S3C2500B
437. ng Table 4 3 Clock Frequencies for CLKMOD Pins CPU Pins and BUS FREQ Pins Frequency Frequency Frequency 200 Fastbus 211 Async Not supported ELECTRONICS 4 9 SYSTEM CONFIGURATION S3C2500B Table 4 3 Clock Frequencies for CLKMOD Pins CPU FREQ Pins and BUS FREQ Pins Continued Frequency Frequency Frequency 211 Async 48MHz 48MHz 48MHz 48MHz 48MHz 48MHz 48MHz 48MHz 211 Async 48MHz 48MHz 48MHz 48MHz 48MHz 48MHz 48MHz 48MHz 2011 Async 48MHz 48M Hz 48MHz 48MHz 48MHz 48MHz 48MHz 48MHz 2011 Async 48MHz 48M Hz 48MHz 48MHz 48M Hz 48MHz 48MHz 48MHz 4 10 ELECTRONICS S3C2500B SYSTEM CONFIGURATION Table 4 3 Clock Frequencies for CLKMOD Pins CPU FREQ Pins and BUS FREQ Pins Continued Frequency Frequency Frequency 211 Async 211 Async ELECTRONICS 4 11 SYSTEM CONFIGURATION S3C2500B Each PLL can also be programmed by S W register setting Each PLL is in pin configurable mode after the system reset is released You can change the PLL configuration mode to the register configurable mode by set CPLLREN SPLLREN UPLLREN PPLLREN in the SYSCFG 31 28 If the PLL register enable bit is set to 1 the PLL multiplication factor is not from the external pin but from the corresponding PLLCON regiseter CPLLCON SPLLCON UPLLCON PPLLCON registers The PLL is controlled by the 3 control variables P M S When the PLL is under the control of the S W and the PLL control va
438. ngths 2 3 2 3 2 6 8 aaa walau qaq 2 3 VAYA REGISTOS 2 4 2 7 3 The Relationship Between ARM and THUMB State 220 2 0222 2 7 2 7 4 Accessing Hi Registers in THUMB 2 8 2 8 The Program Status 2 8 2 8 1 The Condition Code 0 22 22 100000 2 9 28 2 The Gontrol BIS ihe coe t Ote eeu te tee e e ti 2 9 2 9 EXCEPTIONS MEER 2 11 2 9 1 Action on Entering an 2 11 2 9 2 Action on Leaving an 2 11 2 9 3 Exception Entry Exit 2 12 SUN 2 12 29 5 RO me 2 13 ENSE lo Pe m mE 2 13 2 9 7 Software 2 14 2 9 8 Undefined 5 2 14 2 TO EXCODUIORMOCIOTS 2 14 2 10 1t Exceptonm PEOrillGS coe Ere s teda ade uns 2 15 2 10 2 Not Exceptions Can Occur at Once
439. nit of the length field is the byte and the hexdecimal number Figure 7 2 Data Structure of Tx Buffer Descriptor ELECTRONICS S3C2500B 31 30 29 28 27 26 eis 31 0 31 30 29 28 27 26 16 Buffer pointer Ownership bit O Skip BD B SOF S EOF E Done D Rx status 26 MSO 25 Halted 24 MRx10Stat 23 BRxDone 22 RxParErr 21 MUFS 20 Overflow 19 CRCErr 18 AlignErr 17 Reserved 16 Reserved RxLength ETHERNET CONTROLLER Address of the frame data be saved 0 CPU 1 Set this bit to skip the current buffer descriptor when the ownership bit is cleared Set by the BDMA to indicate the first BD for a frame Set by the BDMA to indicate the last BD for a frame Set by the BDMA on the first BD when the reception of a frame finished and it used multiple BD s The Rx status field of the received frame Rx frame size is larger than the Maximum Rx Frame Size BRxMFS The reception of next frame is halted when MACCON 1 MHaltlmm is set or when MACRXCON 0 MRxEn is clear The frame was received over 10Mbps wire 7 interface The reception process by the BDMA is done without error MRxFIFO Parity Error Set when the size of the Rx frame is larger than the Maximum Untagged Frame Size 1518bytes if the long packet is not enabled in the MAC Rx control register MRxFIFO Overflow CRC at the end of a frame did not match the computed CRC32 or
440. nsmit Control Frame Register Description 15 0 MACTXSTAT 15 0 A 16 bit value indicating the status of a MAC control packet as it is sent to a remote station Read by the BDMA engine 7 24 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 4 2 2 MAC Control Register MAC control register provides global control and status information for the MAC The MLINK10 bit is a status bit All other bits are MAC control bits MAC control register settings affect both transmission and reception After a reset is complete the MAC controller clears the reset bit Not all PHYs support full duplex operation Setting the MAC loopback bit overrides the full duplex bit Also some 10M b s PHYs may interpret the loop 10 bit to control different functions and manipulate the link10 bit to indicate a different status condition Table 7 28 MACCON Register MACCONA 0 00 0000 R W MAC control 0x00000000 MACCONB 0 0000000 R W MAC control 0x00000000 Table 7 29 MAC Control Register Description Halt request MHaltReq Set this bit to stop data frame transmission and reception as soon as Tx Rx of any current frames has been completed Halt immediate MHaltlmm Set this bit to immediately stop all transmission and reception 2 Software reset MReset Set this bit to reset all MAC control and status register and MAC state machines This bit is automatically cleared Full duplex If the PHY chip advertising full duplex set this bit In this case c
441. nsure that any subsequent actions it undertakes can be repeated when the instruction is retried 3 15 6 INSTRUCTION CYCLE TIMES Coprocessor data transfer instructions take n 1 S 2N bl incremental cycles to execute where N The number of words transferred B The number of cycles spent in the coprocessor busy wait loop 5 and are defined as sequential S cycle non sequential N cycle and internal I cycle respectively 3 54 ELECTRONICS S3C2500B INSTRUCTION SET 3 15 7 ASSEMBLER SYNTAX lt LDC STC gt cond L p cd lt Address gt LDC STC L cond Cd Address can be 1 Load from memory to coprocessor Store from coprocessor to memory When present perform long transfer 1 otherwise perform short transfer 0 Two character condition mnemonic See Table 3 2 The unique number of the required coprocessor An expression evaluating to a valid coprocessor register number that is placed in the CRd field An expression which generates an address The assembler will attempt to generate an instruction using the PC as a base and a corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated 2 A pre indexed addressing specification Rn offset of zero Rn lt expression gt offset of lt expression gt bytes A post indexed addressing specificatio
442. nt value for CNTO Figure 14 7 High Speed UART Baud Rate Divisor Register 14 18 ELECTRONICS S3C2500B SERIAL HIGH SPEED UART 14 3 7 HIGH SPEED UART BAUD RATE EXAMPLES High Speed UART BRG input clock PCLK2 is the system clock frequency divided by 2 If the system clock frequency is 133 MHz and PCLK is selected the maximum BRGOUT output clock rate is PCLK2 16 4 156 250 Hz UCLK is the external clock input pin for High Speed UART PCLK2 UCLK can be selected by HUCON 6 register PCLK2 BRGOUT EXT UCLK 12 bit Counter Divide by 1 or 16 Divide by 16 Sample Clock Select Clock NOTE CNTO CUBRD 15 4 CNT1 CUBRD 3 0 Select Clock HUCON 6 Figure 14 8 High Speed UART Baud Rate Generator BRG Table 14 14 Typical Baud Rates Examples of High Speed UART Baud Rates 2 66 5 MHz EXT UCLK 29 4912 MHz BRGOUT CNTO CNT1 CNTO CNT1 DEC HEX DEC HEX 1200 3463 87 0 119984 120000 000 t731 6C3 0 239968 001 76722 0 240000 000 4800 865 361 o 479936 001 0 480000 9600 432160 0 959873 001 1918F 0 960000 0 00 19200 21507 o 1924190 001 955F o 1920000 000 38400 1768 3848380 022 3840000 000 560 5772569 022 0 5760000 15200 3523 11545139 022 0 11520000 00
443. nterrupt source If all interrupt pending bits are 0 when you read this register the return value is 0x00000027 This register is valid only under the IRQ or FIQ mode in the ARM940T In the interrupt service routine you should read this register before changing the CPU mode NOTE If the lowest interrupt priority priority 0 is pending the INTOFFSET value will be 0x00000000 The reset value will therefore be changed to 0x00000027 to be different from interrupt pending priority O Table 16 6 INTOFFSET FIQ INTOFFSET IRQ Register INTOFFSET 0 0140018 R FIQ interrupt offset register 0x00000027 INTOFFSET 0xF014001C IRQ interrupt offset register 0x00000027 ELECTRONICS 16 9 INTERRUPT CONTROLLER S3C2500B Table 16 7 Index Value of Interrupt Sources 65 27 26 25 24 21 20 19 17 s is a 1 n 16 10 ELECTRONICS S3C2500B INTERRUPT CONTROLLER Table 16 7 Index Value of Interrupt Sources Continued 0 9x9 O WuwroTXmemg 9x8 wp eme owe os B 9x5 M 9 8 7 6 5 4 3 2 0 ELECTRONICS 16 11 INTERRUPT CONTROLLER S3C2500B 16 4 5 INTERRUPT BY PRIORITY REGISTER The interrupt by priority registers IPRIORHI and IPRIORLO
444. nto base 22 Byte Word Bit 0 Transfer word quantity 1 Transfer byte quantity 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset bofore transfer 25 Immediate Offset 0 Offset is an immediate value 0 Offset 0 11 0 Unsigned 12 bit immediate offset 11 4 3 0 3 0 Offset register 11 4 Shift applied to Rm 31 28 Condition Field Figure 3 14 Single Data Transfer Instructions 3 28 ELECTRONICS S3C2500B INSTRUCTION SET 3 9 1 OFFSETS AND AUTO INDEXING The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction or a second register possibly shifted in some way The offset may be added to U 1 or subtracted from U 0 the base register Rn The offset modification may be performed either before pre indexed P 1 or after post indexed P 0 the base is used as the transfer address The W bit gives optional auto increment and decrement addressing modes The modified base value may be written back into the base W 1 or the old base value may be kept W 0 In the case of post indexed addressing the write back bit is redundant and is always set to zero since the old base value can be retained by setting the offset to zero Therefore post indexed data transfers always write back the modified base The only use of the W bit in a post indexed da
445. ntrols the HUnDTRO HUnDTR 1 pin Setting this pin DTR bit to one the HUnDTRO HUnDTHR 1 pin goes to Low level If you set this bit to zero it goes High level 25 Request to Send to pin This bit directly controls the High Speed UARTS pin only when the RTS High Speed UART is not hardware flow control mode If this bit set to one High Speed UARTS pin goes Low level Otherwise it remains High level 27 26 This bit should be cleared by zero pins concerning to hardware flow control 29 Software Flow Control This bit determines whether High Speed UART select software flow Enable SFEN control or not If this bit set to one High Speed UART will act in software flow control In this mode you have to use Control Character register 30 Echo Mode If this bit is set to one RX data is sent not only HURXBUF but also ECHO TX port directly so HUTXBUF data will not be transmitted 31 RTS RTR selection This selection bit determines output of HUnRTSO HUnRTS 1 pin RTS RTR 0 RTS 1 NOTE RxFIFO mode RTR goes to 1 when RxFIFO is full In nonRxFIFO mode RTR goes to 1 when RxBUF is not empty 28 Hardware Flow Control This bit determines whether High Speed UART select hardware flow Enable HFEN control or not If this bit set to one High Speed UART will control all 14 6 ELECTRONICS S3C2500B SERIAL HIGH SPEED UART 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RID W S TI
446. ntrols the data feeding and reception between the MAC and the system bus AMBA using two buffers BDMA TxBUFF BTxBUFF and BDMA RxBUFF BRxBUFF The BTxBUFF and BRxBUFF hold data and status information for frames being transmitted and received respectively Each buffer is controlled by the block which consists of a bus arbiter a control and status block buffer descriptors 7 3 7 1 Bus Arbiter The bus arbiter decides which of the BDMA buffer controllers transmit Tx or receive Rx has the highest priority for accessing the system bus The prioritization is dynamic The BDMA arbiter outputs a bus request signal nREQ to the AMBA when Rx Buffer contains 4 words data or EOF End of Frame was saved to the buffer or Tx Buffer BTxBUFF contains 4 word free space After it receives a bus acknowledgement signal nACK from the AMBA the BDMA bus arbiter determines the correct bus access priority ELECTRONICS 7 7 ETHERNET CONTROLLER S3C2500B 7 3 7 2 Control and Status This block controls the read write operations of the bus master across the AMBA The control logic supports the following operations Fixed 4 word burst size control between Tx and Rx Transmit threshold control based on 1 8 of transmit buffer size to match transmission latency to system bus latency Little Endian byte swapping to support the data transfer of Little Endian memory usage for frame data byte swap
447. ny BDMA controller initialization has occurred The transmission state machine starts transmitting the data in the FIFO and will retain the first 64 bytes until after this station has acquired the net At that time the transmitter requests more data and transmits it until the signalling the end of data to be transmitted The transmitter appends the calculated CRC to the end of the frame A frame transmit operation can be subdivided into two operations 1 MII transmit interface operation and 2 BDMA MAC transmit interface operation 7 5 1 3 1 MII Transmit Operation The transmitter block consists of three state machines the gap ok state machine the back off state machine and the main transmission state machine The gap ok state machine The gap ok state machine tracks and counts the inter gap timing between the frames When not operating in full duplex mode it counts 96 bit times from the de assertion of the carrier sense CrS signal If there is any traffic within the first 64 bit times the gap ok state machine reset itself and starts counting from zero If there is any traffic in the last 1 3 of the inter frame gap the gap ok state machine continues counting Following a successful transmission a gap ok is sent at the end of the next 96 bit times regardless of the network traffic In full duplex mode the gap ok state machine starts counting at the end of the transmission and the gap ok signal is sent at the end of the 96 bit
448. of Rd at the address STRB Rd Rb Ro STRB Rd Rb Ro Pre indexed byte store Calculate the target address by adding together the value in Rb and the value in Ro Store the byte value in Rd at the resulting address LDR Rd Rb Ro LDR Rb Ro Pre indexed word load Calculate the source address by adding together the value in Rb and the value in Ro Load the contents of the address into Rd LDRB Rd Rb Ro LDRB Rd Rb Ro Pre indexed byte load Calculate the source address by adding together the value in Rb and the value in Ro Load the byte value at the resulting address ELECTRONICS 3 77 INSTRUCTION SET S3C2500B 3 26 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 14 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples STR R2 R6 Store word in R3 at the address formed by adding R6 to R2 LDRB R2 RO R7 Loadinto R2 the byte found at the address formed by adding R7 to RO 3 78 ELECTRONICS S3C2500B INSTRUCTION SET 3 27 FORMAT 8 LOAD STORE SIGN EXTENDED BYTE HALF WORD 15 14 13 12 11 10 9 8 6 5 3 2 0 ilojil js i j 2 0 Destination Register 5 3 Base Register 8 6 Offset Register 10 Sign Extended Flag 0 Operand not sing extended 1 Operand sing extended 11 H Flag Figure 3 37 Format 8 3 27 1 OPERATI
449. of current pointer BRXBDCNTB 0 00 0014 R W BDMA Rx buffer descriptor counter 0x00000000 of current pointer Table 7 15 BDMA Receive Buffer descriptor Counter BDMA Rx buffer descriptor The maximum counter value is dependent on the BTxNBD of the Counter BDMATXCON register Buffer descriptor current address BDMARXDPTR BRXBDCNT lt lt 3 7 18 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 4 1 7 BDMA MAC Transmit Interrupt Enable Register Table 7 16 BMTXINTEN Register BMTXINTENA OxF00A0018 BDMA MAC Tx Interrupt Enable 0x00000000 R W BMTXINTENB oxFoocoo1s BDMA MAC Tx Interrupt Enable 0x00000000 Table 7 17 BDMA MAC Transmit Interrupt Enable Register Description 0 Enable MAC Tx excessive This bit enables ExColl Interrupt collision ExColllE 1 Enable MAC Tx underflow This bit enables Underflow interrupt UnderflowlE 2 Enable MAC Tx deferral This bit enables DeferErr interrupt DeferErrlE 3 Enable MAC Tx no carrier This bit enables NoCarr interrupt NoCarrlE 4 Enable MAC Tx late This bit enables LateColl interrupt collision LateColllE 5 Enable MAC Tx transmit This bit enables TxParErr interrupt parity TxParErrIE 6 Enable MAC Tx completion This bit enables TxComp interrupt TxComplE 157 Not applicable 16 Tx complete to send control This bit enable TxCFcomp interrupt frame interrupt enable TxCFcomplE 17 BDMA Tx not owner This bit enable
450. oftware controls for mode selection and for status and interrupt generation In S3C2500B software flow control or hardware flow control can be selected according to the application ELECTRONICS 14 1 SERIAL I O HIGH SPEED UART S3C2500B Modem Control Signal Transmit Data TxBuffer Register Transmit Control Transmit FIFO Transmit Status 32 Bytes HUART Transmit Shift TX pin and IR Tx Encoder E Status Block Receive Data Receive Control RxBuffer Register Receive Status Receiver FIFO HUCON IR 32 Bytes Control Character Register HUART Baud Rate id RX pin Divisor Receiver Shift Register IR Rx Decoder BaudRate Generator and Detector EXT UCLK HUCON UCLK Figure 14 1 High Speed UART Block Diagram 14 2 ELECTRONICS S3C2500B SERIAL HIGH SPEED UART 14 3 HIGH SPEED UART SPECIAL REGISTERS Table 14 1 High Speed UART 0 Special Registers Overview Register Address RW Description Size Reset Valu oxF0070000 High Speed UART contol register W 0x00000000 HUSTAT oxF0070004 RW High Speed UART status register w HUINT oxF0070008 RA High Speed UART interupt enable register W 0400000000 HUTXBUF 647007006 High Speed UART tansmitdatareuister HURXBUF High Speed UART receive data register Table 14 2 High Speed UART 1 Special Registers Overview
451. ol Registers The Ext I O Bank controller has eight external I O access control registers These registers correspond to up to eight external I O banks that are supported by S3C2500B Table 5 16 describes eight registers that are used to control the timing of external I O bank accesses The external I O access cycles can be controlled by using either a specified value or an external wait signal nEWAIT Especially to obtain access cycles that are longer than TACC of 31 cycles you can delay the active time of nOE or nWBE by nEWAIT assertion In case of ROM bank nOE nWBE signals are activated simultaneously that is there is no control parameter as like TCOS Address setup time TACS can be used when the external memory access is handled by the nOE assertion to be delayed Thus the external memory may use more stable address Access cycles TACC extend nCS cycles to access external memory After is deasserted chip selection hold time TCOH can be used when nCS is keep up BOCON is used to set the external access timings for external bank 0 B1CON is used to set the external access timing for I O bank 1 and so on BnCON Bank number Figure 5 10 BnCON Ext I O Bank controller has eight kind control registers for ROM SRAM and flash memory see Table 5 16 These registers correspond to up to eight ROM SRAM Flash banks that are supported by S3C2500B For ROM SRAM Flash bank 0 the external data bus
452. oller should verify that the transmission is idle that is MX MR is inactive 1 for two or more than 2 frames When idle status is detected the 2 controller forces the MX bit to go active 0 indicating the presence of valid monitor data in the corresponding frame As a result the receiver stores the monitor data and generates MRxBA Monitor Rx Buffer Available interrupt When the IOM2MRD is read by the CPU in response to the interrupt the receiver forces MR bit to go active 0 indicating the acknowledge of received data In response to the acknowledge the transmitter generates MTxBA Monitor Tx Buffer Available interrupt and the CPU writes data to IOM2MTD The MX bit is still in the active The transmitter indicates a new byte in monitor channel by returning the MX bit active after sending it once in the inactive state When the MRxBA interrupt is generated and the CPU read out the IOM2MRD the receiver acknowledges the data by returning the MR bit active after sending it once in the inactive state This in turn causes the transmitter to generate an MTxBA interrupt When the last byte has been transmitted and acknowledged the CPU set the MTxEOM End of Message Request to 1 This enforces inactive state in the MX bit Two frames of MX inactive indicate the end of a message When the MX bit is received in the inactive state in two consecutive frames the receiver generates the MRxEOM End of Message Received interrupt and enforces an i
453. ollision does not detected MAC loopback MLoopBack Set this bit to cause transmission signals to be presented as input to the receive circuit without leaving the controller 0 ij Hj 5 6 MII OFF Use this bit to select the connection mode If this bit is set to one 10M bits s interface will select the 10M bits s endec Otherwise the MII will be selected Loop 10 Mb s MLOOP10 If this bit is set the Loop 10 external signal is asserted to the 10M b s endec 11 8 Not applicable 12 MDC OFF Clear this bit to enable the MDC clock generation for power management If it is set to one the MDC clock generation is disabled 14 13 Not applicable 15 Link status 10 Mb s This bit value is read as a buffered signal on the link 10 pin MLINK10 read only 91 16 Not applicable emp ELECTRONICS 7 25 ETHERNET CONTROLLER S3C2500B 7 4 2 3 CAM Control Register The three acceptance bits MStation MGroup and MBroad in the CAM control register are used to override the address comparison mode by the compare enable bit MCompEn By setting the CAM control register it is possible to accept frames with all types of destination addresses The three types of destination address are as follows Broadcast address defined as FF FF FF FF FF FF Unicast Station address addresses with an even first byte For example 00 FF FF FF FF FF Multicast Group address addresses with an odd first byte but not
454. on DD 00 Increase destination address 01 Decrease destination address 10 Do not change destination address fixed 11 Reserved 12 Interrupt enable IE 0 Do not generate a interrupt when GDMA completes 1 Generate a interrupt when GDMA completes successfully 16 13 External GDMA ACK cycle count XCNT 0000 1 cycle 0001 2 cycles 0010 3 cycles 0011 4 cycles 0100 5 cycles 0101 6 cycles 0110 7 cycles 0111 8 cycles 1000 9 cycles 1001 10 cycles 1010 11 cycles 1011 12 cycles 1100 13 cycles 1101 14 cycles 1110 15 cycles 1111 16 cycles 31 Busy status BS 0 is idle 1 is active Figure 12 3 GDMA Control Register ELECTRONICS 12 11 GDMA CONTROLLER S3C2500B 12 3 3 GDMA SOURCE DESTINATION ADDRESS REGISTERS The GDMA source destination address registers contain the 32 bit source destination addresses for GDMA channels 0 1 2 3 4 and 5 These address registers cover the whole external memory space including the special purpose registers You have to reference the memory map of the S3C2500B Chapter 4 when you want to set these address registers Depending on the settings you make to the GDMA control register DCON the source or destination addresses will either remain the same or they will be increased or decreased When DCON MODE 3 1 is HUART RX mode HUART to memory 011 or DES OUT mode DES to memory 101 the DSAR register doesn t care Also when DCON MO
455. onding interrupt is enabled DISCIEN Reserved ELECTRONICS 10 17 USB CONTROLLER S3C2500B 109 8 7 5 4 3 2 1 zm ozm 0 EndPoint 0 Interrupt ENable EPOIEN 0 Endpoint 0 interrupt disable 1 Endpoint 0 interrupt enable EndPoint 1 Interrupt ENable EP1IEN 0 1 interrupt disable 1 Endpoint 1 interrupt enable 2 EndPoint 2 Interrupt ENable EP2IEN 0 2 interrupt disable 1 Endpoint 2 interrupt enable 3 EndPoint 3 Interrupt ENable 0 Endpoint 3 interrupt disable 1 Endpoint 3 interrupt enable 4 EndPoint 4 Interrupt ENable 0 Endpoint 4 interrupt disable 1 Endpoint 4 interrupt enable 7 5 Reserved 8 SUSpend Interrupt ENable SUSIEN 0 Suspend interrupt disable 1 Suspend interrupt enable 9 Reserved 10 ReSeT Interrupt ENable RSTIEN 0 Reset interrupt disable 1 Reset interrupt enable 11 DiSConnect Interrupt ENable DISCIEN 0 Disconnect interrupt disable 1 Disconnect interrput enable 31 12 Reserved Figure 10 9 USBINTRE Register 10 18 ELECTRONICS S3C2500B USB CONTROLLER 10 5 5 USB FRAME NUMBER REGISTER These registers maintain the Frame Number within SOF Packet Frame Number within SOF Packet are 1161 Table 10 10 USBFN Register USBFN R USB Frame Number register 0x00000000 Table 10 11 USBFN Register Descriptions mcu 10
456. only in the upper 32 bits the low 32 bits of the signed and unsigned results are identical As these instructions only produce the low 32 bits of a multiply they can be used for both signed and unsigned multiplies For example consider the multiplication of the operands Operand A Operand B Result OxFFFFFFF6 0 0000001 OxFFFFFF38 If the Operands are Interpreted as Signed Operand A has the value 10 operand B has the value 20 and the result is 200 which is correctly represented as OxFFFFFF38 If the Operands are Interpreted as Unsigned Operand A has the value 4294967286 operand B has the value 20 and the result is 85899345720 which is represented as 0x13FFFFFF38 so the least significant 32 bits are OxFFFFFF38 Operand Restrictions The destination register Rd must not be the same as the operand register Rm R15 must not be used as an operand or as the destination register All other register combinations will give correct results and Rd Rn and Rs may use the same register when required ELECTRONICS 3 23 INSTRUCTION SET S3C2500B 3 7 1 CPSR FLAGS Setting the CPSR flags is optional and is controlled by the S bit in the instruction The N Negative and Z Zero flags are set correctly on the result N is made equal to bit 31 of the result and Z is set if and only if the result is zero The C Carry flag is set to a meaningless value and the V overflow flag is unaffected 3 7 2 INSTRUCTION CYCLE TIMES MUL takes 15 ml
457. ontrol Character 2 Register ELECTRONICS 13 17 SERIAL CONSOLE UART S3C2500B TRANSMIT i Stop Data B P ata Bits 5 8 arity 1 2 INT TXD BE lt RECEIVE gt Data Bits 5 8 mes Data Bits INT RXD A CURXBUF Receive Data Receive Data Figure 13 12 Interrupt Based Serial Transmit and Receive Timing Diagram 13 18 ELECTRONICS S3C2500B SERIAL CONSOLE UART SIO Frame Data Bits Figure 13 13 Serial Frame Timing Diagram Normal Console UART IR Transmit Frame Data Bits Bit frame T 7 16 6 16 Figure 13 14 Infra Red Transmit Mode Frame Timing Diagram ELECTRONICS 13 19 SERIAL CONSOLE UART S3C2500B IR Receive Frame Data Bits Bit frame T 13 16 Figure 13 15 Infra Red Receive Mode Frame Timing Diagram 13 20 ELECTRONICS S3C2500B SERIAL HIGH SPEED UART SERIAL 1 0 HIGH SPEED UART 14 1 OVERVIEW The S3C2500B High Speed UART Universal Asynchronous Receiver Transmitter unit provides two independent asynchronous serial I O SIO ports High Speed UART can operate in interrupt based or DMA based mode 0 1 2 for High Speed UART Channel 0 3 4 5 for High Speed UART Channel 1 That is the High Speed UART can generate internal interrupts or DMA requests to transfer data between the CPU and the serial ports 14 2 FEATURES The most important features of the 53 2500 High Speed UART include e
458. ontroller drives TXD 3 0 and TX EN from the rising edge of TX CLK In MII mode the PHY samples TXD 3 0 and TX EN on the rising edge of TX CLK For data transfers TXCLK 10M is provided by the 10M bit s PHY MDIO 1 phbcut12 Management Data When read command is being executed data that is clocked out of the PHY is presented on this pin When a write command is being executed data that is clocked out of the controller is presented on this pin for the Physical Layer Entity PHY ELECTRONICS 1 21 PRODUCT OVERVIEW S3C2500B Table 1 1 S3C2500B Signal Descriptions Continue Group PinName Pin Type PadType Ethernet TXD1 3 0 4 phob12 Transmit Data Transmit Data for 10M Controller TXD_10M Transmit data is aligned on nibble boundaries 18 LOOP_10M TXD 0 corresponds to the first bit to be transmitted on the physical medium which is the LSB of the first byte and the fifth bit of that byte during the next clock TXD_10M is shared with TXD 0 and is a data line for transmitting to the 10 Mbit s PHY LOOP_10M is shared with TXD 1 and is driven by the loop back bit in the control register TX EN 1 1 phob4 Transmit Enable Transmit Enable for 10M TX EN provides precise framing for the data carried TXD 3 0 This pin is active during the clock periods in which TXD 3 0 contains valid data to be transmitted from the preamble stage through CRC When the controller is ready to
459. ost bit P and the up down bit 0 The registers are transferred in the order lowest to highest so R15 if in the list will always be transferred last The lowest register also gets transferred to from the lowest memory address By way of illustration consider the transfer of R1 R5 and R7 in the case where 0x1000 and write back of the modified base is required W 1 Figure 3 19 22 show the sequence of register transfers the addresses used and the value of Rn after the instruction has completed In all cases had write back of the modified base not been required W 0 Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction when it would have been overwritten with the loaded value 3 11 3 ADDRESS ALIGNMENT The address should normally be a word aligned quantity and non word aligned addresses do not affect the instruction However the bottom 2 bits of the address will appear on A 1 0 and might be interpreted by the memory system 0x100C au 0x1000 0x1000 4 1 0 0x1000 4 Figure 3 19 Post Increment Addressing ELECTRONICS 3 41 INSTRUCTION SET 3 42 Rn 3 0x100C 0x1000 4 Figure 3 20 Pre Increment Addressing 0x100C 0x1000 R1 4 2 R7 R5 R1 4 Figure 3 21 Post Decrement Addressing 0x100C 0x1000
460. p Enable ROM 0x00000000 0x80000000 ROM Banki 0x01000000 Bank1 0x81000000 ROM Bank2 0 02000000 Bank2 0x82000000 ROM Bank3 0x03000000 ROM Bank3 0x83000000 ROM Bank4 0 04000000 ROM Bank4 0x84000000 ROM 5 0x05000000 ROM Bank5 0x85000000 ROM 0 06000000 ROM Bank6 0x86000000 ROM Bank7 0 07000000 ROM Bank7 0x87000000 SDRAM 0 40000000 SDRAMO 0x00000000 SDRAM Bank1 0 80000000 SDRAM1 bank1 0x40000000 MISALIGN 7 Misalign Exception Enable S3C2500B asserts the data abort exception in case of CPU misaligned accesses But there is a limitation to that you should set off Instruction Data cache when you want misaligned access aborts HCLKO DIS 4 HCLKO output disable If this bit is set to 1 HCLKO output is activated only when sdram access sdram read write or refresh is enabled If this bit is set to 0 HCLKO is always activated 0 Enabled always 1 Enabled during sdram access System bus arbitration method 0 Round robin 1 Fixed priority ELECTRONICS 4 17 SYSTEM CONFIGURATION S3C2500B 4 9 2 PRODUCT CODE AND REVISION NUMBER REGISTER PDCODE PDCODE OxF0000004 oR Product code and revision number register 0 250000 0 SED 012500 E a 4 18 ELECTRONICS S3C2500B SYSTEM CONFIGURATION 4 9 3 CLOCK CONTROL REGISTER CLKCON There is a clock control register CLKCON in system configu
461. pancy to the next master when there is non used master For instance Number 1 GDMA Number 2 Ethernet controller 0 Number 3 Ethernet controller 1 Number 4 No HDLC 0 gt go to number 5 No HDLC 1 go to number 6 No HDLC 2 gt go to number 1 GDMA Number 5 No HDLC 1 gt go to number 6 HDLC 2 gt go to number 1 Number 6 No HDLC 2 go to number 1 GDMA ELECTRONICS 4 7 SYSTEM CONFIGURATION The following is the problem solving with software Channel Expected Real Bus System Bus Occupancy Occupancy Ethernet 1 3 controller O Ethernet 1 3 controller 1 Problem S3C2500B Channel Occupancy 3 Ethernet 1 3 controller O 3 Ethernet 1 3 controller 1 Problem Solving Writing 0x000330 instead of 0x0 will give each channel of three masters with the same amount of bus occupancy This is because GDMA is run to fill the blank of non used masters in this case HDLCO HDLC1 HDLC2 4 8 ELECTRONICS S3C2500B SYSTEM CONFIGURATION 4 7 CLOCK CONFIGURATION The S3C2500B has four PLL clocking scheme CPU PLL System BUS PLL USB PLL PHY PLL All of the PLL can operate if the corresponding clock select pin is set to O CLKSEL shared with CPU PLL and System BUS PLL USB_CLKSEL PHY_CLKSEL When the clock select pin is set to 1 the PLL goes into power down state The CPU PLL can generate ARM940T clock or system bus clock depending on clock mode selection CLKMOD 1 0
462. ping to support the data transfer of Big Endian memory usage for frame data When memory operate on Big Endian format and byte unit access Ethernet transmit receive reliable data by setting BDMATX RX CON 7 to 1 transmit receive alignment widget to circumvent word alignment restrictions The beginning of a frame should be placed on word boundary Misalignment of the BDMA transfer would complicate the design of the DMA and degrade the performance To avoid this you can use an alignment widget between the BDMA Buffer word and the MAC FIFO byte by controlling the widget field in Tx buffer descriptor The widget discards the first n bytes up to three where n is the value read from the Tx buffer descriptor that configures the alignment widget In the receiver the BDMA bus arbiter inserts a programmable number of bytes up to three into the received data stream while the preamble is being received This adds some padding to the beginning of the frame This padding can then be used to solve the alignment problem without having to use a copy of the buffer Because the data is inserted prior to the concatenation of bytes into words it does not misalign the subsequent DMA transfer The number of the alignment bytes is read from the BDMARXCON 5 4 BRxWA 7 8 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 3 7 3 Buffer Descriptor The ownership bit in the buffer descriptor controls the owner of the descriptor When the ownership bit
463. points support interface e Supports Bulk Data Transfer e CRC16 Generation and CRC5 CRC16 Checking e Suspend Resume Control e DISCONNECT state generation 10 2 3C2500B ELECTRONICS S3C2500B USB CONTROLLER 10 3 FUNCTION DESCRIPTIONS 10 3 1 USB BUS TOPOLOGY AND PHYSICAL CONNECTION There are two kinds of cable connectors A type for hub downstream port and B type for device or called as function Node So end users easily connect cable USB cable physically contains 4 lines 2 lines for signal D D 2 lines for power supply to bus powered device such as mouse keyboard USB 1 1 spec compatibly manufactured cables could be used for USB 2 0 compliant product All cables in markets are not made to fit 1 1 spec correctly but there is no problem for 1 1 or 1 0 compliant products except 2 0 products USB architecture uses bus tree topology There is only one host controller in a root and the hub which lies right next to host controller is called root hub IBM compatible PC with 2 USB ports means that there re one host and a root hub which has one upstream port from host controller and two downstream ports outside PC South bridge chips in PCs such as 82371AB EB contains USB host controller and root hub Compound devices can be designed A monitor that has a CRT and a hub Mouse or keyboard is attached to downstream ports of this monitor inside hub Maximum 5 hubs can lie between a host controller and a function because of
464. pt pending This bit is set when the interrupt is generated and cleared when the same value value of interrupt pending bit is rewritten 31 1 Not applicable 6 12 ELECTRONICS S3C2500B 2 CONTROLLER Reset IICPS Setup IICBUF Lower Address IICBUF One Byte Data Data Sent Stop Figure 6 7 Write Operation Flow Chart ELECTRONICS 6 13 2 CONTROLLER S3C2500B Setup Reset IICPS Setup IICCON Start BF IICBUF IIC Slave Address 0 x 0 IICBUF IIC Upper Address IICBUF Lower Address IICCON Repeated Start ACK IICCON Start ACK IICBUF IIC Slave Address 0 x 1 Empty the BF Bit IICBUF One Byte Data All Data Received Send No ACK IICCON Stop Figure 6 8 Read Operation Flow Chart 6 14 ELECTRONICS S3C2500B ETHERNET CONTROLLER ETHERNET CONTROLLER 7 1 OVERVIEW The S3C2500B has two Ethernet controllers that operate at either 100M bit or 10M bit per second in half duplex or full duplex mode In half duplex mode the IEEE 802 3 carrier sense multiple access with collision detection CSMA CD protocol is supported In full duplex mode the IEEE 802 3 MAC control layer is also supported including the pause operation for flow control The two Ethernet controllers support both the media independent interface MII and the buffered DMA interface BDI The MAC layer consists of a receiver and a transmitter blocks a flow control block a cont
465. ption both Rx DV and Rx er are asserted a CRC error is reported for the current packet As each nibble of the destination address is received the CAM block attempts to recognize it After receiving the last destination address nibble if the CAM block rejects the packet the receive block asserts the Rx toss signal and discards any bytes not yet removed from the receive FIFO that came from the current packet If this operation leaves the FIFO empty it drops Rx Figure 7 6 shows the MII receive data timing without error The RX DV signal which entered the MII from the PCS layer will be ON when the PCS layer recovers the Rx clk from the receive bit stream and delivers the nibble data on RxD 3 0 data line The DV signal must be ON before the starting frame delimiter SFD is received When the Rx DV signal is ON the preamble and SFD parts of the frame header are delivered to MII synchronized with the 25MHz Rx The carrier sense CrS signal was turned on during receive frame As its response to the Rx er signal the MII immediately inserts an alternative data bit stream into the receive data stream As a result the MAC discards this received error frame using the FCS Rx clk Rx DV V V Crs Rx er Figure 7 9 Receiving Frame without Error Rx clk Rx DV V V Crs Figure 7 10 Receiving Frame with Error ELECTRONICS 7 43 ETHERNET CONTROLLER S3C2500B 7 5 1 4 2 BDMA MAC Interface Operation for
466. ptor maximum count OxXXXXXFFF register HRXBDMAXCNTC 0 01200 Rx buffer descriptor maximum count OxXXXXXFFF register 8 26 ELECTRONICS S3C2500B HDLC CONTROLLER 8 7 1 HDLC GLOBAL MODE REGISTER Table 8 7 HMODEA HMODEB and HMODEC Register HMODEA 0 0100000 RW HDLC Mode register 0x00000000 R W HMODEB 0 0110000 RW HDLC Mode register 000000000 HMODEC 0xF0120000 HDLC Mode register 0x00000000 Table 8 8 HMODE Register Description Bit Bit Name Description Number 0 Multi Frame in HTxFIFO this bit is set more than one frame can be loaded into HTxFIFO In this in DMA operation case the frame size be less than the FIFO size Not applicable 2 Rx clock inversion If this bit set to 0 the receive clock samples the data at the rising edge RXCINV If this bit set to 1 the receive clock samples the data at the falling edge 3 Tx clock inversion If this bit set to 0 the transmit clock shifts the data at the falling edge TXCINV If this bit set to 1 the transmit clock shifts the data at the rising edge 4 Rx Little Endian mode This bit determines whether the data is in Little or Big endian format RxLittle HRXFIFO is in Little endian If this bit is set to 0 then the data on the system bus should be in Big endian Therefore the bytes will be swapped in Big endian 5 Tx Little Endian mode This bit determines whether Tx data is in Little or Big endian TxLittle T
467. r and V clear greater than 1101 BLE label BLE label Branch if Z set or N set and V clear or N clear and V set less than or equal NOTES 1 While label specifies a full 9 bit two s complement address this must always be half word aligned ie with bit 0 set to 0 since the assembler actually places label gt gt 1 in field SOffset8 2 Cond 1110 is undefined and should not be used Cond 1111 creates the SWI instruction see 3 35 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 23 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples 45 Branch to over if RO 45 BGT over Note that the THUMB opcode will contain the number of half words to offset over Must be half word aligned 3 92 ELECTRONICS S3C2500B INSTRUCTION SET 3 36 FORMAT 17 SOFTWARE INTERRUPT 15 14 13 11 10 7 0 12 9 8 j 7 0 Comment Field Figure 3 46 Format 17 3 36 1 OPERATION The SWI instruction performs a software interrupt On taking the SWI the processor switches into ARM state and enters Supervisor SVC mode The THUMB assembler syntax for this instruction is shown below Table 3 24 The SWI Instruction THUMB Assembler ARM Equivalent SWI Value 8 SWI Value 8 Perform Software Interrupt Move the address of the next instr
468. r ease of processing and reduced processing time HDLC Controllers and Three TSAs Four address station registers and one mask register for address search mode Selectable CRC No CRC mode Automatic CRC generator pre set Digital PLL block for clock recovery Baud rate generator NRZ NRZI FM Manchester data formats for Loop back and auto echo mode Tx and Rx FIFOs with 8 word 8 x 32 bit depth Data alignment logic Hardware flow control Embedded DMA Controller with Buffer Descriptor for channel Universal Serial Bus USB USB specification 1 1 compliant Full speed 12 Mbps operation with internal transceiver only A total of 5 endpoints 1 control endpoint and 4 data endpoints that can support control interrupt bulk transaction Two data endpoints have 32 byte FIFO two data endpoints have 64 byte FIFO General DMA support ELECTRONICS S3C2500B 1 2 FEATURES Continue 2 Controller e OM 2 terminal mode support e nter device communication via IC channel e bus access control e Monitor channel collision control e Optional signals such as BCL and STRB e Bus Deactivation Activation via Bus Reversal Universal Asynchronous Receiver Transmitter UART e Programmable baud rates e 32 byte Transmit FIFO and 32 byte Receive FIFO e UART source clock selectable Internal clock PCLK2 External clock EXT UCLK e Auto baud rate detection e Infra red IR transm
469. r of xGDMA Req signal pulse For example although xGDMA Req signal pulses 3 times in the region GDMA transfers data only one time from source address to destination address Current xGDMA signal is idle state deasserted when xGDMA siganl is idle state high Otherwise recognizes current xGDMA signal as next and transfers next data recommand that xGDMA signal is deasserted when xGDMA signal is active is minimum two cycles be programmed by setting DCON 16 13 be between 1 and 16 cycles Figure 12 11 Single and One Data Burst Mode Timing 12 20 ELECTRONICS S3C2500B GDMA CONTROLLER 12 6 2 SINGLE AND FOUR DATA BURST MODE DCON 3 1 001 4 0 5 1 xGDMA Req amp xGDMA Ack signals are active high In four data burst mode GDMA transfers four data and GDMA Transfer Count Register DTCR value decreases by four But if the value of transfer count register is not a multiple of 4 times transfer size the last misaligned data can be transferred by one transfer size Recommand deasserted time xGDMA Req xGDMA Ack Programmable by DCON 16 13 Spo sor X soz X sos 6 X sor X pz Address order is source address0 gt source address1 gt source address 2 gt source address3 gt destination address0 gt destination address1 gt destination address2 gt destination address3 and Data order is source data0 gt
470. r systems requiring virtual memory capability ARM provides an alternative product the ARM920T cached processor macrocell The 940 also features a TrackingICE mode which allows an approach similar to a conventional ICE mode of operation ELECTRONICS 2 17 PROGRAMMER S MODEL S3C2500B 2 14 ARM940T BLOCK DIAGRAM CPID 31 0 CPDIN 31 0 CPDOUT 31 0 1 31 0 ID 31 0 Control Instruction b ARMSTDMI Processor Core Integral Interface 4 0 AMBA Interface 31 0 Bcontrol BD 31 0 Figure 2 7 ARM940T Block Diagram 2 18 ELECTRONICS S3C2500B PROGRAMMER S MODEL 2 15 ABOUT THE ARM940T PROGRAMMER S MODEL The ARM940T cached processor macrocell includes the ARM9TDMI microprocessor core instruction and data caches a write buffer and a protection unit for defining the attributes of regions of memory The ARM940T incorporates two coprocessors e CP14 which allows software access to the debug communications channel e CP15 which allows configuration of the caches protection unit and other system options such as big or little endian operation The ARM940T also features an external coprocessor interface which allows the attachment of a closely coupled coprocessor on the same chip for example a floating point unit The programmer s model of the ARM940T consists of the programmer s model of the ARM9TDMI with the following additions and modifications e Memory accesses for instructio
471. rams will execute in User mode The non user modes known as privileged modes are entered in order to service interrupts or exceptions or to access protected resources ELECTRONICS 2 3 PROGRAMMER S MODEL S3C2500B 2 7 REGISTERS ARMSTDMI has a total of 37 registers 31 general purpose 32 bit registers and six status registers but these cannot all be seen at once The processor state and operating mode dictate which registers are available to the programmer 2 7 1 The ARM State Register Set In ARM state 16 general registers and one or two status registers are visible at any one time In privileged non User modes mode specific banked registers are switched in Figure 2 3 shows which registers are available in each mode the banked registers are marked with a shaded triangle The ARM state register set contains 16 directly accessible registers RO to R15 All of these except R15 general purpose and may be used to hold either data or address values In addition to these there is a seventeenth register used to store status information Register 14 is used as the subroutine link register This receives a copy of R15 when a branch and link BL instruction is executed At all other times it may be treated as a general purpose register The corresponding banked registers R14 svc R14 R14 R14 abt and R14 und are similarly used to hold the return values of R15 when interrupts and exceptions arise or when branch and link ins
472. ransmission is aborted A detected parity error sets the TxParErr bit in the BMTXSTAT register MTxFIFO Underflow The 80 byte MTxFIFO can handle a system latency of 640 bit times An underflow of the MTxFIFO during transmission indicates that the system cannot keep up with the demand of the MAC and the transmission is aborted No Carrier The carrier sense signal CrS is monitored from the beginning of the start of frame delimiter SFD to the last byte transmitted A NoCarr indicates that CrS was never present during transmission a possible network problem but the transmission will NOT be aborted Note that during loop back mode the MAC is disconnected from the network and a CrS will be detected Excessive collision error Whenever the MAC encounters a collision during transmit it will back off update the attempt counter and retry the transmission later on When the attempt counter reaches 16 16 attempts that all resulted in a collision the transmission is aborted This indicates a network problem Late collision error Normally the MAC would detect a collision if one occurs within the first 64 bytes of data that are transmitted including the preamble and SFD If a collision occurs after this time frame a possible network problem is indicated The error is reported to the transmission state machine but the transmission is NOT aborted Instead it performs a back off as usual Excessive deferral error During the fir
473. ration For the purpose of power save Clock control register CLKCON can be programmed at low frequency and the slower clock than the system clock can be made by clock dividing value When the internal system clock is divided by CLKCON its duty cycle is changed If CLKCON is programmed to zero the internal system clock remains the same as the internal clock In other case the duty cycle of internal system clock is no logner 5096 CLKCON OxF0000008 Clock control register 0x00000000 DVAL 15 0 System clock dividing value If all bits are 0 non divided clock is used Only one bit can be set in CLKCON 15 0 That is the clock dividing value is defined as 1 2 4 8 16 Internal system clock is PLL output clock CLKCON 1 HCLK CLKCON 1 Figure 4 7 Divided System Clock Timing Diagram ELECTRONICS 4 19 SYSTEM CONFIGURATION S3C2500B 4 9 4 PERIPHERAL CLOCK DISABLE REGISTER PCLKDIS There is a peripheral clock disable register in system configuration You can set this register with the specific value for the purpose of power save If you set PCLKDIS 0 to 1 the clock for channel 0 is disabled Similarly you control the clock input of each peripheral R W Peripheral clock disable register 0x00000000 PCLKDIS Bit Initial State 27 24 21 IIC clock disable TIMERS SB Register Address PCLKDIS OxF000000C 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
474. ration after it has been stopped The CPU can recognize when a GDMA operation has been completed by software polling and or when it receives an appropriate internally generated interrupt The S8C2500B controller can increment or decrement source destination addresses and conduct 8 bit byte 16 bit half word or 32 bit word data transfer The does not check the cache So software must ensure that source and destination addresses must be configured as non cacheable in the memory system configuration when it configures the GDMA channels The local priority of six channel GDMA can be programmed by fixed priority or round robin priority in similar manner to the AHB bus priority Please refer to Chapter 4 The System Configuration 12 2 FEATURE e Six Channels Memory to Memory Data Transfer e Memory to Peripheral Data Transfer High Speed UART DES USB e Support for Four External Request from Request Pins XGDMA Req0 xGDMA Req3 ELECTRONICS 12 1 GDMA CONTROLLER S3C2500B AHB BUS Mode Selection xGDMA HUARTO DES xGDMA_Req1 HUARTO DES xGDMA_Req2 HUARTO DES xGDMA Req3 DES xGDMA Req0 DES xGDMA_Req1 HUART1 DES 12 2 GDMA Channel 0 GDMA Req GDMA Ack GDMA Channel 1 GDMA Req GDMA Ack GDMA Ack GDMA Channel 3 GDMA Req GDMA Ack GDMA Channel 4 GDMA Req GDMA Ack GDMA Channel 5
475. received pause count register PZCNT stores the current value of the 16 bit received pause counter Table 7 48 PZCNT Register PZCNTB R 0x00000000 Table 7 49 Received Pause Count Register Description Pause count received The count value indicates the number of time slots the transmitter was paused due to the receipt of control pause operation frames from the MAC 7 4 2 13 MAC Remote Pause Count Register Table 7 50 RMPZCNT Register Table 7 51 Remote Pause Count Register Description Remote pause count The count value indicates the number of time slots that a remote MAC was paused as a result of its sending control pause operation frames ELECTRONICS 7 35 ETHERNET CONTROLLER S3C2500B 7 4 2 14 Content Addressable Memory CAM Register There are 21 CAM entries for the destination address and the pause control frame For the destination address CAM value one destination address consists of 6 bytes Using the 32 word space 32 x 4 bytes you can therefore maintain up to 21 separate destination addresses You use CAM entries 0 1 and 18 to send pause control frames To send a pause control frame you write the entry with the destination address the entry with the source address and the CAM 18 entry with length type opcode and operand You then set the send pause bit in the MAC transmit control register Table 7 52 CAM Register CAMA OxF00B0080 R W CAM
476. receiving is strictly prohibited 00 Disable Rx mode 01 Interrupt request 10 GDMA request 11 Reserved High speed UART 0 can use only GDMA 0 1 2 channel and High speed UART 1 can use only GDMA 3 4 5 channel Send Break SBR Set this bit to one to cause the High Speed UART to send a break If this bit value is zero a break does not send A break is defined as a continuous Low level signal on the transmit data output with the duration of more than one frame transmission time Serial Clock Selection This selection bit specifies the clock source SCSEL 0 Internal PCLK2 1 External EXT UCLK Auto Baud Rate Detect Setting this bit causes the High Speed UART to enter Auto Baud AUBD Rate Detect mode In this mode High Speed UART try to get the baud rate from input data Loop back mode Setting this bit causes the High Speed UART to enter Loop back LOOPB mode In Loop back mode the transmit data output is sent High level and the transmit buffer register HUTXBUF is internally connected to the receive buffer register HURXBUF NOTE This mode is provided for test purposes only For normal operation this bit should always be 0 Parity mode PMD The 3 bit parity mode value specifies how parity generation and checking are to be performed during High Speed UART transmit and receive operations Oxx no parity 100 odd parity 101 even parity 110 parity is forced checked as a 1 111 parity forced checked a
477. recommand that xGDMA siganl is deasserted when xGDMA signal is active state Figure 12 14 Block and Four Data Burst Timing one data burst source addressO and source data0 destination addressO and destination data0 four data burst source addressO and source data0 source address1 and source data1 source address2 and source data2 source address3 and source data3 destination addressO and destination data0 destination address1 and destination data1 destination address2 and destination data2 destination address3 and destination data3 source address4 and source data4 NOTE In four data burst mode GDMA transfers four data and GDMA Transfer Count Register DTCR value decreases by four ELECTRONICS 12 23 GDMA CONTROLLER S3C2500B NOTES 12 24 ELECTRONICS S3C2500B SERIAL CONSOLE UART SERIAL I O CONSOLE UART 13 1 OVERVIEW The S3C2500B Console UART Universal Asynchronous Receiver Transmitter unit provides one independent asynchronous serial I O SIO port The port can operate in interrupt based mode That is the Console UART can generate internal interrupts to transfer data between the CPU and the serial port 13 2 FEATURES The most important features of the S3C2500B Console UART include e Programmable baud rates e Console UART source clock selectable Internal clock PCLK2 External clock EXT UCLK e PCLK2 2 e Infra red IR tr
478. resh Timer Register REFREG 20008 Refresh timer register 0x00000020 REFCYC 15 0 SDRAM refresh cycle 0 00000020 3116 Reseved For refresh period of 15 6us in 16 64 and 128Mbit and a system bus clock frequency of 133MHz 15 6 x 10 x 133 x 10 2075 For refresh period of 7 8us in 256Mbit and a system bus clock frequency of 133MHz 7 8 x 10 x 133 x 10 1037 The refresh timer is set to 32 on reset To ensure a refresh interval of less than 15 6us in 16 64 and 128Mbit after reset The minimum frequency of system bus clock allowed is 32 15 6 x 10 2 1MHz The refresh timer is set to 32 on reset To ensure a refresh interval of less than 7 8us in 256Mbit after reset The minimum frequency of system bus clock allowed is 32 7 8 x 10 4 2MHz The refresh register should be written to as early as possible in the system start up procedure especially when clock frequency is very low 31 16 15 0 RESERVED REFCYC 15 0 SDRAM refresh cycle 31 16 Reserved Figure 5 25 SDRAM Refresh Timer Register 5 52 ELECTRONICS S3C2500B MEMORY CONTROLLER 5 7 9 4 Write Buffer Time out Register The write buffer time out register works with the merging write buffer if write buffer is enabled This 16 bit read write field of register sets the cycles for a forced flush of the write buffer Table 5 28 SDRAM Write Buffer Time out Register WBTOREG 0xF002000C Write buffer time out register 0x00
479. riables are dynamically changed by the S W the glitch may occur in the PLL output clock You can avoid the glitch generation by set the PLL clock enable bit CPLLCE SPLLCE UPLLCE PPLLCE in the SYSCFG 27 24 When the PLL clock enable bit is set to 0 during the PLL control variable change the stable PLL output clock is provided The PLL output frequency is determined as follows Fout Fin x M 8 2 x 275 Where the Fin is the frequency of the PLL input clock and the Fout is the frequency of the PLL output clock The four PLLs in the S3C2500B are controlled by above formula and the table 4 4 shows the PLL variables for the most widely used frequencies Table 4 4 P M S values of the S3C2500B PLL m names Frequency Frequency 0101000 1 30MHz 000001 0100100 00 1 266MHz 4 12 ELECTRONICS S3C2500B CLKCON 15 0 Y ARM Clock Divider Teen 166 33 MHz CLKSEL CPU PLL A XCLK T CPU FREQ 2 0 CPLLCON pdown BUS PLL ARM940T Block or CLKCON 15 0 CLKMOD 1 0 BUS FREQ 2 0 Y AMBA Clock 133 33 MHz SYSTEM CONFIGURATION CLKSEL Divider TS gt BUS FREQ 2 0 or CLKMODU O0 PLL Clock Divider HCLKO pin SPLLCON PLL TEST amp 1 0 USB CLKSEL USB SCLK Bi USB PLL 5 UPLLCO
480. ription Continued Bit Bit Name Description Number 23 Rx internal error This bit is set to 1 when received frame will be detected error possibility RxIERR due to the receive clock is unstable DMA Rx frame done This bit is set when a DMA Rx operation has successfully operated a every received frame frame to memory from HRXFIFO and when the last byte of a frame has DRxFD been written to memory This bit generate interrupt when set to 1 to know a frame is received You can clear this bit by writing 1 to this bit 25 Not applicable DMA Rx not owner This bit is set when DMA is not owner of the current buffer descriptor DRxNO and DRxnSTSK bit was set In this case DMA Rx is disabled and can generate interrupt if enabled If DRxnSTSK bit is zero this bit is always zero You can clear this bit by writing 1 to this bit 27 DMA Tx frame done In case of MFF bit is 0 default when DNA Tx operation has DTxFD successfully transferred rest byte of frame from Tx FIFO to destination this bit will be set to 1 But if is setto 1 transceiver will keep sending the data until there is no data transfer from memory to TxFIFO 29 DMA Tx not owner This bit is set when DMA is not owner of the current buffer descriptor DTxNO and DTxnSTSK bit was set In this case DMA Tx disabled and can generate interrupt if enabled If DTxnSTSK bit is zero this bit is always zero You can clear this bit by writing 1 to this b
481. rises If the processor is operating in a privileged mode they can also be manipulated by software The T bit This reflects the operating state When this bit is set the processor is executing in THUMB state otherwise it is executing in ARM state This is reflected on the TBIT external signal Note that the software must never change the state of the TBIT in the CPSR If this happens the processor will enter an unpredictable state Interrupt disable bits The and F bits are the interrupt disable bits When set these disable the IRQ and FIQ interrupts respectively The mode bits The 4 M3 M2 1 and MO bits M 4 0 are the mode bits These determine the processor s operating mode as shown in Table 2 1 Not all combinations of the mode bits define a valid processor mode Only those explicitly described shall be used The user should be aware that if any illegal value is programmed into the mode bits M 4 0 then the processor will enter an unrecoverable state If this occurs reset should be applied ELECTRONICS 2 9 PROGRAMMER S MODEL S3C2500B Table 2 1 PSR Mode Bit Values 4 0 Mode Visible THUMB State Registers Visible ARM State Registers 10000 User 7 5 PC CPSR 10001 FIQ 7 LR fiq PC CPSR SPSR fiq 10010 R7 R0 PC CPSR SPSR irq 10011 Supervisor R7 R0 LR svc SP svc PC CPSR SPSR_svc 10111 Abort R7 R0 LR abt SP abt PC
482. rite data cacheable bits p15 0 Rd c2 c0 0 Read data cacheable bits If the opcode 2 field 1 the instruction cacheable bits are programmed For example MCR p15 0 Rd c2 c0 1 Write instruction cacheable bits p15 0 Rd c2 c0 1 Read instruction cacheable bits The format for the data and instruction cacheable bits is similar as shown in Table 2 10 Setting a bit makes an area cacheable clearing it makes it non cacheable All defined bits in the control register are set to zero at reset Table 2 10 Cacheable Register Format eem e Caheabie bic s torareas le la o 2 24 ELECTRONICS S3C2500B PROGRAMMER S MODEL 2 16 1 5 Register 3 Write buffer control register This register contains a write buffer control bufferable attribute bit for each of the eight areas of memory Each bit is used in conjunction with the cacheable bit to control write buffer operation For a description of buffer behavior see The write buffer on page 4 11 Setting a bit makes an area bufferable clearing a bit makes an area unbuffered For example MCR p15 0 Rd c3 c0 0 Write data bufferable bits MRC p15 0 Rd c3 c0 0 Read data bufferable bits NOTE The opcode_2 field should be 0 because the write buffer only operates on data regions The following table therefore only applies to the DCache All defined bits in the control register are set to zero
483. rn from the 777 3 13 2 Comment 3 13 3 Instruction Cycle 3 13 4 Assembler n 3 14 Coprocessor Data Operations 3 14 1 Coprocessor Instructions a 3 14 2 Coprocessor 3 14 3 Instruction Cycle 2 2220400 00 0000000000 3 14 4 Assembler 3 15 Coprocessor Data Transfers LDC 5 20242 0000 n 3 15 1 Coprocessor Fields 3 15 2 Addressing 3 15 3 Address ND 315 5 Data ADORNS Sahak a 3 15 6 Instruction Cycle Times 3 15 7 Assembler S3C2500B RISC MICROCONTROLLER Table of Contents Continued Chapter 3 Instruction Set Continued 3 16 Coprocessor Register Transfers MRC MCR 3 56 3 16 1 The Coprocessor Fields isset ennt 3 56 3 16 2 Transfers to R15 La L L A A A nannaa ena anina tetra us a
484. rocessor information 11 8 Coprocessor number 15 12 Coprocessor destination register 19 16 Coprocessor operand register 23 20 Coprocessor operation code 31 28 Condition Field Figure 3 25 Coprocessor Data Operation Instruction 3 14 2 THE COPROCESSOR FIELDS Only bit 4 and bits 24 to 31 are significant to ARM9TDMI The remaining bits are used by coprocessors The above field names are used by convention and particular coprocessors may redefine the use of all fields except CP as appropriate The CP field is used to contain an identifying number in the range 0 to 15 for each coprocessor and coprocessor will ignore any instruction which does not contain its number in the CP field The conventional interpretation of the instruction is that the coprocessor should perform an operation specified in the CP Opc field and possibly in the CP field on the contents of CRn and CRm and place the result in CRd ELECTRONICS 3 51 INSTRUCTION SET S3C2500B 3 14 3 INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S bl incremental cycles to execute where b is the number of cycles spent in the coprocessor busy wait loop S and are defined as sequential S cycle and internal I cycle 3 14 4 ASSEMBLER SYNTAX CDP cond p lt expression1 gt cd cn cm lt expression2 gt cond pz expression cd cn and cm lt expression2 gt Examples CDP CDPEQ 3 52 Two character condition mnemonic Se
485. rotection region register Should be zero means the value transferred in the Rd A read from this register returns an unpredictable value ELECTRONICS 2 29 PROGRAMMER S MODEL S3C2500B 2 16 1 8 1 Index Segment Format Where the required value is an index segment the format is Table 2 19 CP15 Register 7 Index Segment Data Format Should be zero Should be zero 2 16 1 8 2 ICache Prefetch Data Format For the ICache prefetch operation the data format is Table 2 20 CP15 Register 7 Prefetch Address Format Should be zero 2 16 1 8 3 Wait for interrupt This operation allows the ARM940T to be placed in a low power standby mode When the operation is invoked all clocks in the processor are frozen until either an interrupt or a debug request occurs This function is invoked by a write to register 7 The following ARM instruction causes this to occur MCR p15 0 Rd c7 c0 4 The following instruction causes the same affect and has been added for backward compatibility with StrongARM SA 1 MCR p15 0 Rd c15 c8 2 This stalls the processor with internal clocks held high from the time that this instruction is executed until one of the signals nFIQ nIRQ or EDBGRQ is asserted Also if the debugger sets the debug request bit in the unit control register the wait for interrupt condition is terminated In the case of nFIQ and nIRQ the processor is woken up regardless of whether the interrupt
486. rr a4oado gt rocrmm lt z rr 5 0 4 00 rr A4oocoo aamoa aAmoux zal 3 0 MAXP value MAXP 19 OUT Data ERRor ODERR 3 0 value x 8 max packet size 0 Normal operation 6 4 Reserved 1 Data error ISO 7 MAXP value SETting enable MAXPSET bbs or 0 MAXP value isn t changed 1 FIFO flush 1 MAXP value is changed jaiai ica mous 0180 21 OUT SenD STALL OSDSTALL 0 No operation 0 interrupt mode 1 Stall handshake transmit state 1 ISO mode 22 OUT SenT STALL OSTSTALL T AuTo CLeaR OATCLR ua eed 0 No operation 1 Auto clearing ORDY when FIFO data unloaded handshake trarismitted 23 OUT CLear data TOGgle OCLTOG 0 No operation 1 Data toggle flag set to 0 24 IN IN packet ReaDY IINRDY 0 Not ready for IN operation 1 Ready for IN operation 25 IN fifo Not EMPty INEMP 0 No data packet in FIFO 1 Auto setting IINRDY when MAXP sized packet loaded 17 here is at least one packet of data FIFO 26 IN UNDER run IUNDER 14 13 Reserved 0 No operation 15 CSR2 SETting enable CSR2SET 1 Received IN token but not ready ISO 0 USBEP4CSR 12 8 isn t changed 1 USBEP4CSR 12 8 is changed IFFLUSH 16 OUT Out packet ReaDY OORDY 1 FIFO flush 0 Not received data packet 28 IN SenD STALL ISDSTALL 1 Received packet from
487. rrupt Clear register TIC which is used to clear the current interrupt These timers can operate in interval mode or in toggle mode The output signals are TOUTn The user can enable or disable timers by setting control bits in Timer Mode register TMOD An interrupt request is generated whenever a timer count out down count occurs Watchdog Timer WDT has Watchdog Timer register WDT which has control bits and data value 17 2 FEATURE e 6 Programmable Timers e Interval Mode or Toggle Mode Operation e Hardware Watchdog Timer ELECTRONICS 17 1 32 BIT TIMERS S3C2500B 17 3 INTERVAL MODE OPERATION In interval mode a timer generates one shot pulse of preset timer clock duration whenever a time out occurs This pulse generates a time out interrupt that is directly output at the timer s configured output pin TOUTn In this case the timer frequency monitored at the TOUTn pin is calculated as Where is the system bus clock frequency 17 4 TOGGLE MODE OPERATION In toggle mode the timer pulse continues to toggle whenever a time out occurs An interrupt request is generated whenever the level of the timer output signal is inverted that is when the level toggles The toggle pulse is output directly at the configured output pin Using toggle mode you can achieve a flexible timer clock range with 50 duty In toggle mode the timer frequency monitored at the TOUTn pin is calculated as follows ftour
488. ruction set extension spaces to the ARM instruction set These are e Arithmetic instruction extension space e Control instruction extension space e Coprocessor instruction extension space e Load store instruction extension space Instructions in these spaces are undefined they cause an undefined instruction exception The ARM9TDMI fully implements all the instruction set extension spaces defined in ARM Architecture v4T as undefined instructions allowing emulation of future instruction set additions 2 20 ELECTRONICS S3C2500B PROGRAMMER S MODEL 2 16 ARM940T CP15 REGISTERS 2 16 1 CP15 REGISTER MAP SUMMARY The 940 incorporates CP15 for system control The register map for C15 is shown in Table 2 5 Table 2 5 CP15 Register Map Register O 8 Cache lockdown 7 NOTE Register locations 0 2 5 and 6 each provide access to more than register register accessed depends upon the value of the opcode 2 field See the register descriptions that follow for further information 2 16 1 1 Register 0 ID code This is a read only register which returns a 32 bit device ID code The ID code register is accessed by reading CP15 register 0 with the opcode 2 field set to any value other than 1 For example MRC p15 0 rd c0 0 0 2 7 returns ID register The contents of the ID code are shown in Table 2 6 Table 2 6
489. s ELECTRONICS 3 25 INSTRUCTION SET S3C2500B 3 8 2 CPSR FLAGS Setting the CPSR flags is optional and is controlled by the S bit in the instruction The N and Z flags are set correctly on the result N is equal to bit 63 of the result Z is set if and only if all 64 bits of the result are zero Both the C and V flags are set to meaningless values 3 8 3 INSTRUCTION CYCLE TIMES MULL takes 1 m 1 l MLAL 15 m 2 l cycles to execute where m is the number of 8 bit multiplier array cycles required to complete the multiply which is controlled by the value of the multiplier operand specified by Rs Its possible values are as follows For Signed Instructions SMULL SMLAL f bits 31 8 of the multiplier operand are all zero or all one f bits 31 16 of the multiplier operand are all zero or all one f bits 31 24 of the multiplier operand are all zero or all one n all other cases For Unsigned Instructions UMULL UMLAL f bits 31 8 of the multiplier operand are all zero f bits 31 16 of the multiplier operand are all zero f bits 31 24 of the multiplier operand are all zero all other cases S and are defined as sequential S cycle and internal respectively 3 26 ELECTRONICS S3C2500B INSTRUCTION SET 3 8 4 ASSEMBLER SYNTAX Table 3 5 Assembler Syntax Descriptions Mnemonic Description UMULL cond S Rm Rs
490. s Program Data path between register and external memory WA Address whose LSB is 0 4 8 C HA Address whose LSB is 0 2 4 6 8 E BA Address whose LSB is 0 1 2 3 4 5 6 7 8 9 A B C D E F EA External Address X Don t care Table 5 3 External 32 bit Datawidth Store Operation with Big Endian Transfer Width STORE Reg External Memory Bit Num CPU r Data Es Tx EM XXXC pe CPU Address 1 BAH Bit Num S 31 31 31 PERPE Data Bus pd 2 Uie aaaa Hs aT External Address ADDR Address ADDR Bit Num 31 31 31 EE Data E 5 s Timing Sequence Sequence Table 5 4 External 32 bit Datawidth Load Operation with Big Endian Transfer Width LOAD CPU Reg lt External Memory Bit Num 31 0 31 0 31 0 31 0 31 0 31 0 31 0 CPU Register Data abcd xxab xxcd xxxb XXXC xxxd EIC External Address ADDR Address ADDR Bit Num 31 31 31 External Data m x d TimingSequence Bit Num 31 31 31 31 Data Bus bel d ae aaaa oa ELECTRONICS 5 7 MEMORY CONTROLLER S3C2500B Table 5 5 and 5 6 Using big endian and half word access Program Data path between register and external memory WA Address whose LSB is 0 4 8 C EA External Address HA Address whose LSB is 0 2 4 6 8 C E BA Address whose LSB is 0 1 2 3 4 5 6 7 8 9 A B C D E
491. s by default to the D and channels ELECTRONICS 9 7 IOM2 CONTROLLER S3C2500B The availability of the S T interface D channel is indicated in bit5 Stop Go of the DD last byte of channel2 Figure 9 5 Available Blocked Stop Go Figure 9 5 Structure of Last Byte of Channel 2 on DD The 2 controller checks the S G bit to determine if the D channel is available to access If the D channel is available S G 0 HDLC frame is transmitted If the D channel is busy with other device the 2 controller should halt the transmission Bits 7 and 6 are the D channel Echo bits from the S interface echo back the two D channel bits of the current frame and are used to determine D channel collisions The echo bits are compared with the sent D channel bits to determine if a collision has occurred The IOM2 controller does not support the bit 9 3 7 6 IC Channel Operation The 2 controller can have access to two IC channels by reading the IOM2ICRD and writing the IOM2ICTD register Only one channel must be accessed at a time since the 2 controller has registers for one channel The IC channel0 is accessed by setting the ICSEL bit to 0 Because the data output is open drain the unused IC channel and all High bits of the chosen IC channel are placed in a high impedance state unless used by an HDLC frame 9 3 7 7 Pin Direction Reversal The data signals the IOM2 bus are defined as Data Upstream DU an
492. s in Imm to the current value of the SP R7 Store the contents of Rd at the resulting address LDR Rd LDR Rd R13 Imm Add unsigned offset 255 words 1020 bytes Imm to the current value of the SP R7 Load the word from the resulting address into Rd NOTE The offset supplied lmm is a full 10 bit address but must always be word aligned ie bits 1 0 set to 0 since the assembler places 1 gt gt 2 in the Word8 field 3 30 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 18 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples STR R4 SP 492 Store the contents of R4 at the address formed by adding 492 to SP R13 Note that the THUMB opcode will contain 123 as the Word8 value 3 84 ELECTRONICS S3C2500B INSTRUCTION SET 3 31 FORMAT 12 LOAD ADDRES 15 14 13 7 0 12 11 10 8 o i o s O 7 0 8 bit Unsigned Constant 10 8 Destination Register 11 Source 0 PC 1 SP Figure 3 41 Format 12 3 31 1 OPERATION These instructions calculate an address by adding an 10 bit constant to either the PC or the SP and load the resulting address into a register The THUMB assembler syntax is shown in the following table Table 3 19 Load Address SP THUMB Assembler Equivalent ADD Rd PC ADD Rd R15 Imm
493. s lmm gt gt 2 in field Word 8 The value of the PC will be 4 bytes greater than the address of this instruction but bit 1 of the PC is forced to 0 to ensure it is word aligned 3 25 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples LDR R3 PC 844 Load into R3 the word found at the address formed by adding 844 to PC bit 1 of PC is forced to zero Note that the THUMB opcode will contain 211 as the Word8 value 3 76 ELECTRONICS S3C2500B INSTRUCTION SET 3 26 FORMAT 7 LOAD STORE WITH REGISTER OFFSET 15 14 13 12 11 10 9 8 6 5 3 2 0 2 0 Source Destination Register 5 3 Base Register 8 6 Offset Register 10 Byte Word Flag 0 Transfer word quantity 1 Transfer byte quantity 11 Load Store Flag 0 Store to memory 1 Load from memory Figure 3 36 Format 7 3 26 1 OPERATION These instructions transfer byte or word values between registers and memory Memory addresses are pre indexed using an offset register in the range 0 7 The THUMB assembler syntax is shown in Table 3 14 Table 3 14 Summary of Format 7 Instructions STR Rd Rb Ro STR Rb Pre indexed word store Calculate the target address by adding together the value in Rb and the value in Ro Store the contents
494. s BTxNO interrupt interrupt enable BTxNOIE 18 BDMA Tx Buffer empty This bit enables interrupt interrupt enable BTxEmptylE 91 19 Not applicable ELECTRONICS 7 19 ETHERNET CONTROLLER S3C2500B 7 4 1 8 BDMA MAC Transmit Interrupt Status Register Table 7 18 BMTXSTAT Register BMTXSTATA OxF00A0020 BDMA MAC Tx Interrupt Status Register 0x00000000 BMTXSTATB 0xF00C0020 Tx Interrupt Status Register 0x00000000 Table 7 19 BDMA MAC Transmit Interrupt Status Register Description Excessive collision ExColl This bit is set when collision occurred 16 times consecutively In this case the frame transmission is aborted If this bit is the cause of the interrupt MTxEn BTxEn MReset bit should be cleared for the re transmission of the current frame 1 Underflow This bit is set if the MAC TxFIFO becomes empty during the frame transmission 2 Deferral Error DeferErr This bit is set when MAC doesn t run the transmission process from TX EN falling to 6 071 nibble times or 24 284 bit times 3 No carrier NoCarr This bit is set if no carrier sense is detected during the transmission frame 4 Late collision LateColl This bit is set if a collision occurs after 512 bit times or 64 byte times 5 Transmit parity error This bit is set if a parity error is detected in the MAC TxFIFO TxParErr 6 Tx Completion TxComp This bit is set when the transmission always is completed wi
495. s LLC data fields with less than 46 bytes Options are available to suppress padding and to support the reception of short frames Long frame mode supports LLC data fields with more than 1500 bytes An option is also available to support to reception of long frames No CRC mode suppresses the appending of a CRC field mode allows the reception of frames without valid CRC fields 7 38 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 5 1 2 Destination Address Format Bit 0 of the destination address is an address type designation bit It identifies the address as either an individual or a group address Group addresses are sometimes called multicast addresses and individual addresses are called unicast addresses The broadcast address is a special group address in the special hex format FF FF FF FF FF FF Bit 1 of the destination address distinguishes between locally or globally administered addresses For globally administered or universal U addresses the bit value is 0 If an address is to be assigned locally you must set this bit to 1 For the broadcast address this bit must also be set to 1 7 5 1 3 Transmitting a Frame To transmit a frame the transmit enable bit in the transmit control register must be set and the transmit halt request bit must be zero In addition the halt immediate and halt request bits in the MAC control register must be 0 These conditions are normally set after a
496. s a 14 4 ELECTRONICS S3C2500B SERIAL HIGH SPEED UART Table 14 4 High Speed UART Control Register Description Continued 11 Number of Stop bits STB Word Length WL Infra red mode IR This bit specifies how many stop bits are used to signal end of frame EOF 0 one stop bit per frame 1 two stop bit per frame This two bit word length value indicates the number of data bits to be transmitted or received per frame 00 5 bit 01 6 bit 10 7 bit 11 8 bit The S3C2500B High Speed UART block supports infra red IR transmits and receive operations In IR mode the transmit period is pulsed at a rate of 3 16 that of the normal serial transmit rate when the transmit data value in the HUTXBUF register is zero To enable IR mode operation you set HUCON 14 to 1 Otherwise the High Speed UART operates in normal mode In IR receive mode the receiver must detect the 3 16 pulsed period to recognize a zero value in the receiver buffer register HURXBUF as the IR receive data When this bit is 0 normal High Speed UART mode is selected When it is 1 infra red Tx Rx mode is selected NOTE Changing these bits while transmitting cause one Tx data losing Because level of infra red frame start bit and idle state of normal frame are identically high 15 This bit should be cleared by zero 16 Transmit FIFO enable TFEN 17 Receive FIFO enable RFEN 18 Transmit FIFO reset TFRST
497. s a rotate right by one bit position of the 33 bit quantity formed by appending the CPSR C flag to the most significant end of the contents of Rm as shown in Figure 3 10 Contents of Rm in Value of Operand 2 Figure 3 10 Rotate Right Extended 3 14 ELECTRONICS S3C2500B INSTRUCTION SET 3 5 2 2 Register Specified Shift Amount Only the least significant byte of the contents of Rs is used to determine the shift amount Rs can be any general register other than R15 If this byte is zero the unchanged contents of Rm will be used as the second operand and the old value of the CPSR C flag will be passed on as the shifter carry output If the byte has a value between 1 and 31 the shifted result will exactly match that of an instruction specified shift with the same value and shift operation If the value in the byte is 32 or more the result will be a logical extension of the shift described above LSL by 32 has result zero carry out equal to bit 0 of Rm LSL by more than 32 has result zero carry out zero LSR by 32 has result zero carry out equal to bit 31 of Rm LSR by more than 32 has result zero carry out zero ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm ROR by 32 has result equal to Rm carry out equal to bit 31 of Rm a O P ROR by n where n is greater than 32 will give the same result and carry out as ROR n 32 therefore repeatedly subtract 32 from n until the a
498. s are enabled or disabled that is independent of the and F bits in the processor CPSR The debug related waking only occurs if DBGEN is HIGH that is only when debug is enabled If the interrupts are enabled the ARM is guaranteed to take the interrupt before executing the instruction after the wait for interrupt If debug request is used to wake up the system the processor will enter debug state before executing any further instructions 2 30 ELECTRONICS S3C2500B PROGRAMMER S MODEL 2 16 1 8 4 Drain Write Buffer This CP15 operation causes instruction execution to be stalled until the write buffer is emptied This operation is useful in real time applications where the processor needs to be sure that a write to a peripheral has completed before program execution continues An example would be where a peripheral in a bufferable region is the source of an interrupt Once the interrupt has been serviced the request must be removed before interrupts can be re enabled This can be ensured if a drain write buffer operation separates the store to the peripheral and the enable interrupt functions The drain write buffer function is invoked by a write to CP15 register 7 using the following ARM instruction MCR p15 0 Rd c7 c10 4 This stalls the processor core with CPnWAIT asserted until any outstanding accesses in the write buffer have been completed that is until all data has been written to memory 2 16 1 9 Register 9 Instructio
499. s still low until 1 when the sending frame is reached to end and 2 when there is no more data in the TxFIFO for sending a new frame General I O Port ELECTRONICS 1 25 PRODUCT OVERVIEW S3C2500B Table 1 1 S3C2500B Signal Descriptions Continue Group Pad Type HnCTSO0 phbst8 HDLC Ch 0 Clear To Send The S3C2500B stores each transition of nCTS to ensure that its occurrence will be acknowledged by the system General I O Port HnDCDO 45 8 GPIO44 phbst8 HDLC Ch 0 Data Carrier Detected A high level on this pin resets and inhibits the receiver operation Data from a previous frame that may remain in the RxFIFO is retained The pin state of transition is stored by the register General I O Port phbst8 2 Data Clock HDLC Ch 0 Receiver Clock When this clock input is used as the receiver clock the receiver samples the data on the positive or negedge of HRXCO clock This can be determined by S W selection This clock can be the source clock of the receiver the baud rate generator or the DPLL General I O Port phbst8 2 Frame Syncronization Clock HDLC Ch 0 Transmitter Clock When this clock input is used as the transmitter clock the transmitter shifts data on the positive or negative transition of the HTXCO clock input This can be determined by S W selection If you don t use HTXCO as the transmitter clock you can use it as an output pin for
500. s the control C field and precedes the frame check sequence FCS field The information field contains the data to be transferred Not every frame however must actually contain information data The word length of the I field is eight bits in the 53 2500 HDLC module And Its total length can be extended by 8 bits until terminated by the FCS field and the closing flag 8 3 1 6 Frame Check Sequence FCS Field The 16 bits that precede the closing flag comprise the frame check sequence FCS field The FCS field contains the cyclic redundancy check character CRCC The polynomial x16 x12 x5 1 is used both for the transmitter and the receiver Both the transmitter and the receiver polynomial registers are all initialized to 1 prior to calculating of the FCS The transmitter calculates the frame check sequence of all address bits control bits and information fields It then transmits the complement of the resulting remainder as the FCS value The receiver performs a similar calculation for all address control and information bits as well as for all the FCS fields received It then compares the result to FOB8H When a match occurs the frame valid RxFV status bit is set to 1 When the result does not match the receiver sets the CRC error bit RxCRCE to 1 The transmitter and the receiver automatically perform these FCS generation transmission and checking functions The S3C2500B HDLC module also supports NO CRC operation mode In NO C
501. se in determining sign of quotient amp remainder PUSH RO Justification shift 1 bit at a time until divisor RO value is just lt than dividend R1 value To do this shift dividend right by 1 and stop as soon as shifted value becomes LSR RO R1 1 MOV R2 R3 B FTO just LSL R2 1 0 CMP R2 RO BLS just 1 MOV RO 40 Set accumulator to 0 B Branch into division loop div LSR R2 1 0 CMP R1 R2 Test subtract BCC FTO SUB R1 R2 If successful do a real subtract 0 ADC RO RO Shift result and add 1 if subtract succeeded CMP R2 R3 Terminate when R2 R3 ie we have just BNE div_ tested subtracting the ones value Now fix up the signs of the quotient RO and remainder R1 POP R2 R3 Get dividend divisor signs back EOR R3 R2 Result sign EOR RO R3 Negate if result sign 1 SUB RO R3 EOR R1 R2 Negate remainder if dividend sign 1 SUB R1 R2 MOV Ir 3 98 ELECTRONICS S3C2500B INSTRUCTION SET 3 39 2 2 ARM Code signed divide ANDS RSBMI EORS ip bit 31 2 sign of result bit 30 sign of a2 RSBCS Effectively zero a4 as top bit will be shifted out later a4 a1 amp 80000000 a1 a1 40 ip a4 a2 ASR 32 a2 a2 0 Central part is identical code to udiv without MOV a4 0 which comes for free as part of signed entry sequence MOVS BEQ just CMP MOVLS BLO div 1 CMP ADC SUBCS TEQ MOVNE BNE MOV MOVS RSBCS RSBMI M
502. se the Console UART to send a break If this bit value is zero a break does not send A break is defined as a continuous Low level signal on the transmit data output with the duration of more than one frame transmission time 5 Serial Clock Select This select bit specifies the clock source SCSEL 0 Internal PCLK2 1 External EXT UCLK Reseved OS 7 Loop back mode Setting this bit causes the Console UART to enter Loop back mode LOOPB In Loop back mode the transmit data output CUTXD keeps 1 and the transmit data register CUTXBUF is internally connected to the receive data register CURXBUF NOTE This mode is provided for test purposes only For normal operation this bit should always be 0 Parity mode PMD The 3 bit parity mode value specifies how parity generation and checking are performed during Console UART transmit and receive operations No parity 100 Odd parity 101 Even parity 110 Parity is forced checked as 1 111 Parity forced checked as 0 Number of Stop bits This bit specifies how many stop bits are used to signal end of STB frame EOF 0 One stop bit per frame 1 Two stop bit per frame 13 4 ELECTRONICS S3C2500B SERIAL CONSOLE UART Table 13 3 Console UART Control Register Description Continued 13 12 Word Length WL This two bit word length value indicates the number of data bits to be transmitted or received per frame 00 5 bit 01 6
503. selection TMODE 00 Disable 01 CPU request 10 Reserved 11 Reserved 3 2 SIO receive mode selection RMODE 00 Disable 01 CPU request 10 Reserved 11 Reserved 4 Send Break SBR 0 Send normal TxData 1 Send break signal 5 Serial Clock Select SCSEL 0 Internal PCLK2 1 External EXT UCLK 6 Reserved This bit should be cleared 7 Loopback mode LOOPB 0 Normal operating mode 1 Enable Loopback mode only for test 10 8 Parity mode PMD Oxx No parity 100 Odd parity 101 Even parity 110 Parity forced checked as 1 111 Parity forced checked as 0 11 Stop Bits STB 0 1 stop bit 1 2 stop bits 13 12 Word Length WL 00 5 bit 01 6 bit 10 7 bit 11 8 bit 14 Infra red mode IR 0 Normal operating mode 1 Infra red mode Figure 13 2 Console UART Control Register 13 6 ELECTRONICS S3C2500B SERIAL CONSOLE UART 31 30 29 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 15 L T B 28 15 Reserved This bit should be cleared 29 Software Flow Control Enable SFEN 0 Disable Software Flow Control 1 Enable Software Flow Control 30 Echo Test Enable ECHO 0 Disable Echo Test 1 Enable Echo Test 31 Reserved This bit should be cleared Figure 13 3 Console UART Control Register ELECTRONICS 13 7 SERIAL CONSOLE UART S3C2500B 13 3 2 CONSOLE UART STATUS R
504. sfer PSR Contents to a Register 31 28 27 23 22 21 16 15 12 11 0 00010 Ps 001111 000000000000 15 21 Destination Register 19 16 Source PSR 0 CPSR 1 SPSHR current mode 31 28 Condition Field MRS Transfer Register Contents to PSR 31 28 27 23 22 21 12 11 4 00010 101001111 00000000 3 0 Source Register 22 Destination PSR 0 CPSR 1 SPSR current mode 31 28 Condition Field MRS Transfer Register Contents or Immediate Value to PSR Flag Bits Only 31 28 27 26 25 24 23 22 21 12 11 0 wp Pd 22 Destination PSR 0 2 CPSR 1 SPSR current mode 25 Immediate Operand 0 Source operand is a register 1 SPSR current mode 11 0 Source Operand 0 3 0 Source Register 11 4 Source operand is an immediate value 11 8 7 0 rome m 7 0 Unsigned 8 bit immediate value 11 8 Shift applied to Imm 31 28 Condition Field Figure 3 11 PSR Transfer ELECTRONICS S3C2500B INSTRUCTION SET 3 6 2 RESERVED BITS Only twelve bits of the PSR are defined in ARM9TDMI Z C V F T amp M 4 0 the remaining bits are reserved for use in future versions of the processor Refer to Figure 2 6 for a full description of the PSR bits To ensure the maximum compatibility between ARM9TDMI programs and future processors the following rules should be observed reserved bits should be preserved when changing the
505. sign extended half word found at the address formed by adding R2 to R4 3 80 ELECTRONICS S3C2500B INSTRUCTION SET 3 28 FORMAT 9 LOAD STORE WITH IMMEDIATE OFFSET 10 15 14 13 12 11 alije 2 0 Source Destination Register 5 3 Base Register 10 6 Offset Register 11 Load Store Flag 0 Store to memory 1 Load from memory 12 Byte Word Flad 0 Transfer word quantity 1 Transfer byte quantity Figure 3 38 Format 9 3 28 1 OPERATION These instructions transfer byte or word values between registers and memory using an immediate 5 or 7 bit offset The THUMB assembler syntax is shown in Table 3 16 Table 3 16 Summary of Format 9 Instructions STR Rd Rb Imm STR Rd Rb Imm Calculate the target address by adding together the value in Rb and Imm Store the contents of Rd at the address 1 LDR Rd Rb Imm LDR Rd Rb Imm Calculate the source address by adding together the value in Rb and Imm Load Rd from the address 1 STRB Rd Rb Imm STRB Rb Imm Calculate the target address by adding together the value in Rb and Imm Store the byte value in Rd at the address value in Rb and Imm Load the byte value at the address into Rd LDRB Rb LDRB Rd Rb lmm Calculate source address by adding together the NOTE For word accesses 0 the value specified by Imm is a full 7 bit address but must be word aligned ie with bits 1 0 set to 0
506. signal delay 10 3 2 FRAME GENERATION Frame divides time slot into 1ms units and the separators are SOFs Start of Frames Host broadcasts one SOF packet at a normal rate of once every 1 00ms 0 0005ms All ISO EPs in all devices can one IN OUT 1ms time period The SOF packet consists of SYNC PID frame number CRC The host transmits the lower 11 bits of the current frame number in each SOF token transmission When requested from the Host Controller the current frame number is the frame number in existence at the time the request was fulfilled The current frame number as returned by the host Host Controller or HCD is at least 32 bits although the Host Controller itself is not required to maintain more than 11 bits Frame N 1 Frame N Frame N 1 Figure 10 1 SOF Packets All full speed functions including hubs receive the SOF packets Frame timing sensitive functions which do not need to keep track of frame number e g a hub need only decode the SOF PID they can ignore the frame number and its CRC If a function needs to track frame number it must comprehend both the PID and the time stamp Full speed devices that have no particular need for bus timing information may ignore the SOF packet The SOF token holds the highest priority access to the bus Babble circuitry in hubs electrically isolates any active transmitters during the End of Frame EOF interval providing an idle bus for the SOF transmission ELECTRONICS 10 3 U
507. sion and transmits a jam pattern 32 bit 175 It then increments the collision attempt counter returns control to the back off state machine and re transmits the frame when the back off time has elapsed and the gap time is valid If there are no collisions the transmitter block transmits the rest of the frame At this time that is after the first 60 byte have been transmitted without collisions the main transmission state machine lets the BDMA engine overwrite the frame After it transmits the first 64 byte the transmitter block transmits the rest of the frame appending the CRC to the end Parity errors FIFO errors or more than 16 collisions will force the transmission state machine to abort the frame no retry and to transmit the next frame Tx Tx en TxD 3 0 Crs Figure 7 7 Timing for Transmission without Collision ELECTRONICS 7 41 ETHERNET CONTROLLER 3C2500B Tx_en PS P PZ p ve 9 MU Crs N 442422277 2 7 Figure 7 8 Timing for Transmission with Collision Preamble 7 5 1 3 2 BDMA MAC Interface Operation for Transmission The BDI transmit operation is a simple FIFO mechanism The BDMA engine stores data to be transmitted and the transmission state machine empties it when the MAC successfully acquires the net Note that the two time domains intersect at the FIFO controller The writing and reading of data is asynchronous and on different
508. sions evaluating to the valid coprocessor register numbers CRn and CRm respectively lt expression2 gt Where present is evaluated to a constant and placed in the CP field Examples MRC p2 5 R3 c5 c6 Request coproc 2 to perform operation 5 c5 and transfer the single 32 bit word result back to MCR p6 0 R4 c5 c6 Request coproc 6 to perform operation 0 on R4 and place the result in c6 MRCEQ p3 9 R3 c5 c6 2 Conditionally request coproc 3 to perform operation 9 type 2 on c5 and c6 and transfer the result back to R3 ELECTRONICS 3 57 INSTRUCTION SET S3C2500B 3 17 UNDEFINED INSTRUCTION The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction format is shown in Figure 3 28 31 2827 2524 Com on Figure 3 28 Undefined Instruction If the condition is true the undefined instruction trap will be taken Note that the undefined instruction mechanism involves offering this instruction to any coprocessors which may be present and all coprocessors must refuse to accept it by driving CPA and CPB HIGH 3 17 1 INSTRUCTION CYCLE TIMES This instruction takes 2S 11 1N cycles where S and are defined as sequential S cycle non sequential N cycle and internal I cycle 3 17 2 ASSEMBLER SYNTAX The assembler has no mnemonics for generating this instruction If it is adopted in the future for some
509. smitter should respond to this by sending EOM 1 during more than two frames Monitor Channel Tx Buffer Available 0 Cleared when the IOM2MTD is written MTxBA 1 new data can be written to IOM2MTD Monitor Channel Rx Buffer Available 0 Cleared when the IOM2MRD is read MRxBA 1 new data has received on the monitor channel 9 Monitor Channel Tx Abort Received 0 Normal MTxABT 1 Mointor channel Tx abort is received When the Rx channel receives an abrupt disruption of handshake procedure not a normal termination of handshake during monitor channel transmission this bit is set to 1 10 IC Channel Buffer Available ICBA 0 Cleared when the IOM2ICRD is read 1 new data has received on the IC channel 11 2 Bus Alive ALIVE 0 The IOM2 bus is in the inactive state DCL 1 1 The 2 bus is in the active state DCLK is clocking 12 new frame sync NEWFSC 0 cleared by CPU 1 FSC detected 2 3 5 6 7 8 Monitor Channel Collision Detected 0 normal MCOL 1 The monitor channel collision has occurred 07 9 14 ELECTRONICS S3C2500B IOM2 CONTROLLER 0 CI 0 Buffer Available CIOBA 0 normal 1 CIO buffer available 1 Reserved 2 CI 1 Buffer Available CHBA 0 Normal 1 buffer available 3 Reserved 4 Monitor Received End of Frame MRxEOM 0 Normal 1 Monitor channel transmission terminated successfully 5 Monitor Received
510. ss edge deley time 1 9 m gt 10 66ns Figure 8 6 HDLC Data Setup and Timing Diagrams Tx data will be sent with delayed 9 82nsec to 10 66nsec from the falling edge of Tx Clock The data of the red period should not be changed That is the RxD should be stable from 0 2nsec to 1 0nsec after RxC rising edge It does not allow data transition during this period The RxC will be Rx receiver clock through Rx clock selection part with some delay And this RxC delay is larger then RxD delay In Figure 8 6 the dotted clock is real internal Rx clock used by the receiver Therefore there should not be transit in Rx data to avoid setup or hold violation ELECTRONICS 8 13 HDLC CONTROLLER S3C2500B 8 5 4 HDLC TRANSMITTER OPERATION The HTxFIFO register cannot be pre loaded when the transmitter is disabled After the HDLC Tx is enabled the flag or mark idle control bit TXFLAG in HCON is used to select either the mark idle state inactive idle or the flag time fill active idle state This active or inactive idle state will continue until data is loaded into the HTxFIFO The content of the HPRMB register can be sent out by setting the TxPRMB in HCON for the remote DPLL before the data is loaded into the HTxFIFO The length of preamble to be transmitted is determined by TxPL bits in HMODE The availability of data in the HTxFIFO is indicated by the HTxFIFO available bit in HSTAT under the contro
511. st the 2 controller checks the bit 5 of DU last byte of channel2 for the status bus free BAC 1 If the bus is free the IOM2 controller starts to transmit its own TIC bus address programmed in the IOM2TBA register When the IOM 2 controller transmits the TIC bus address TAD on DU it compares the bit with the value on DU If any bit mismatches that is a sent bit set to 1 is read back as 0 the 2 controller withdraws immediately from the TIC bus If more than one device attempt to access the bus simultaneously the one with the lowest address values wins If all the TIC bus address bits match the TIC bus is immediately occupied by the 2 controller by setting the to 0 in the subsequent frame until the access request is withdrawn Figure 9 4 shows the channel2 of IOM2 interface TIC Bus Address Bus Access 0 Occupied 1 Accessible Figure 9 4 Structure of Last Byte of Channel 2 on DU When the TIC bus is occupied by one device the bus is identified to other devices as occupied via the BAC 0 After a successful bus access the 2 controller is automatically set into a lower priority class that is a new bus access cannot be performed until the status bus free is indicated in two consecutive frames If none of the devices connected to the IOM interface request access to the D and channels the TIC bus address 7 will be present The device with this address will therefore have acces
512. st attempt to send a frame the MAC may have to defer the transmission because the network is busy If this deferral time is longer than 32K bit times the transmission is aborted Excessive deferral errors indicate a possible network problem 7 48 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 5 4 2 Reporting of Reception Errors When it detects a start of frame delimiter SFD the MAC starts putting data it has received from the MII into the MRxFIFO It also checks for internal errors MRxFIFO overruns while reception is in progress When the reception process is completed the MAC checks for external errors such as frame alignment length CRC and frame too long The following is a description of the types of errors that may occur during a receive operation Parity error A parity bit protects each byte in the MRxFIFO If a parity error occurs it is reported to the MAC A detected parity error sets the RxParErr bit in the BMRXSTAT register Frame Alignment Error After receiving a frame the receiver block checks that the incoming frame including CRC was correctly framed on an 8 bit boundary If it is not and if the CRC is invalid data has been disrupted through the network and the receive block reports a frame alignment error A CRC error is also reported CRC Error After receiving a frame the receiver block checks the CRC for validity and reports a CRC error if it is invalid The PHY informs the MAC if it detects a medium error
513. st to the frame 23 Last In Frame L 0 This buffer descriptor status is not the last to the frame 1 This buffer descriptor status is the last to the frame 24 Frame Length Violation FLV 0 Normal 1 This received frame length exceeds the value of the maximum frame length register 31 Ownership O 0 CPU 12 Figure 8 11 Receive Buffer Descriptor 8 22 ELECTRONICS S3C2500B HDLC CONTROLLER Rx Buffer 2 p Start Address Buffer Data Pointer 1 Pointer Rx Bufsize Buffer Data 1 Register Status Buffer Length Value Buffer Data Pointer 2 228403 1 h Rx Bufsize HRXBDMAXCNT N Status Buffer Lengt Buffer Data 2 Register Value Buffer Data Pointer N Buffer Data N Status BufierLengih NOTE 1 Buffer length is accumulated until the last bit is set in STATUS Buffer data pointer indicates the buffer memory start address 2 After HRXBDMAXCNT Buffer Descriptors used the Rx Buffer Descriptor Address Pointer points start address Figure 8 12 Data Structure of the Receive Data Buffer ELECTRONICS 8 23 HDLC CONTROLLER S3C2500B 8 7 HDLC SPECIAL REGISTERS The HDLC special registers are defined as read only or write only registers according to the direction of information flow The addresses of these registers are shown in Table 8 4 and 8 5 The transmitter FIFO register can be accessed using two different addresses the frame terminate address and the frame continue address T
514. t 17 OUT Fifo FULL OFFULL 0 Normal operation 1 FIFO full state 18 OUT OVER run OOVER 0 Normal operation 1 Data received at FIFO full state ISO USB CONTROLLER 16 15 14 13 12 11 10 9 8 19 OUT Data ERRor ODERR 0 Normal operation 1 Data error ISO 20 OUT Fifo FLUSH OFFLUSH 0 No operation 1 FIFO flush 21 OUT SenD STALL OSDSTALL 0 No operation 1 Stall handshake transmit state 22 OUT SenT STALL OSTSTALL 0 No operation 1 Stall handshake transmitted 23 OUT CLear data TOGgle OCLTOG 0 No operation 1 Data toggle flag set to 0 24 IN IN packet ReaDY IINRDY 0 Not ready for IN operation 1 Ready for IN operation 25 IN fifo Not EMPty INEMP 0 No data packet in FIFO 1 There is at least one packet of data in FIFO 26 IN UNDER run IUNDER 0 No operation 1 Received IN token but not ready ISO 27 IN Fifo FLUSH IFFLUSH 0 No operation 1 FIFO flush 28 IN SenD STALL ISDSTALL 0 No operation 1 Stall handshake transmit state 29 IN SenT STALL ISTSTALL 0 No operation 1 Stall handshake transmitted 30 IN CLear TOGgle ICLTOG 0 No operation 1 Data toggle flag set to 0 31 Reserved Figure 10 13 USBEP1CSR Register ELECTRONICS 10 29 USB CONTROLLER S3C2500B 10 5 9 USB ENDPOINT 2 COMMON STATUS REGISTER This register includes the control bits st
515. t Continued Mnemonic Instruction _ RSB RSC SBC STC STM Stack manipulation push Sw 5 ELECTRONICS 3 3 INSTRUCTION SET S3C2500B 3 2 THE CONDITION FIELD In ARM state all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction s condition field This field bits 31 28 determines the circumstances under which an instruction is to be executed If the state of the C N Z and V flags fulfils the conditions encoded by the field the instruction is executed otherwise it is ignored There are sixteen possible conditions each represented by a two character suffix that can be appended to the instruction s mnemonic For example a branch B in assembly language becomes BEQ for Branch if Equal which means the branch will only be taken if the Z flag is set In practice fifteen different conditions may be used these are listed in Table 3 2 The sixteenth 1111 is reserved and must not be used In the absence of a suffix the condition field of most instructions is set to Always suffix AL This means the instruction will always be executed regardless of the CPSR condition codes Table 3 2 Condition Code Summary Fas Meem ignored 3 4 ELECTRONICS S3C2500B INSTRUCTION SET 3 3 BRANCH AND EXCHANGE BX This instruction is only executed if the condition is true The various conditions
516. t bit 11 becomes the MSB and bit 0 becomes the LSB The offset may be added to U 1 or subtracted from U 0 the base register Rn The offset modification may be performed either before pre indexed P 1 or after post indexed P 0 the base register is used as the transfer address The W bit gives optional auto increment and decrement addressing modes The modified base value may be written back into the base W 1 or the old base may be kept W 0 In the case of post indexed addressing the write back bit is redundant and is always set to zero since the old base value can be retained if necessary by setting the offset to zero Therefore post indexed data transfers always write back the modified base The Write back bit should not be set high W 1 when post indexed addressing is selected ELECTRONICS 3 35 INSTRUCTION SET S3C2500B 3 10 2 HALF WORD LOAD AND STORES Setting S 0 and H 1 may be used to transfer unsigned Half words between an ARM9TDMI register and memory The action of LDRH and STRH instructions is influenced by the BIGEND control signal The two possible configurations are described in the section below 3 10 3 SIGNED BYTE AND HALF WORD LOADS The S bit controls the loading of sign extended data When S 1 the H bit selects between Bytes 0 and Half words 1 The L bit should not be set low Store when Signed S 1 operations have been selected The LDRSB instruction loads the selected B
517. t 32M 8 16M x 16 8M x 32 NOTE Banks Number of external SDRAM memory bank used The controller supports up to two banks Leaf Internal bank of SDRAM devices 1 NE uM EBE 2 128M bit Bir 2 2 5 40 ELECTRONICS S3C2500B MEMORY CONTROLLER Table 5 20 Supported SDRAM Configuration of 16 bit External Bus Banks Address Size Leaf Select Total Technology Arrangement Memory Size Byte 16M bit 2M x8 HADDR 20 Ed RADDA 64M bit 8M x 8 KNEE 4M x 16 4 Bil HADDR 21 HADDR 20 16M HADDR 21 HADDR 20 10 HADDR 21 20 HADDR 21 HADDR 20 10 HADDR 21 20 HADDR 21 HADDR 20 tomm umet Inc 128M bit HE 256M bit 16M x 16 HE NOTE Banks Number of external SDRAM memory bank used The controller supports up to two banks Leaf Internal bank of SDRAM devices ELECTRONICS 5 41 MEMORY CONTROLLER S3C2500B 5 7 3 ADDRESS MAPPING Table 5 21 Illustrates the AHB address bus to the SDRAM address ADDR 14 0 mapping for various memory devices when external bus width is 32 bits Table 5 22 Illustrates the AHB address bus to the SDRAM address ADDR 14 0 mapping for various memory devices when external bus width is 16 bits Table 5 21 SDRAM Address Mapping of 32 bit External Bus Column Adaress
518. t Set this bit to halt the transmission after completing the MTxHalt transmission of any current frame Suppress padding Set this bit not to generate pad bytes for frames of less than 64 bytes Suppress CRC MNoCRC Set this bit to suppress addition of a CRC at the end ofa frame Fast back off MFBack Set this bit to use faster back off times for testing No defer MNoDef Set this bit to disable the defer counter The defer counter keeps counting until the carrier sense CrS bit is turned off Send Pause MSdPause Set this bit to send a pause command or other MAC control frame The send pause bit is automatically cleared when a complete MAC control frame has been transmitted Writing a 0 to this register bit has no effect 7 MII 10M b s SQE test mode Set this bit to enable MII 10M b s SQE test mode enable MSQEn 31 8 Not applicable ELECTRONICS 7 27 ETHERNET CONTROLLER S3C2500B 7 4 2 5 MAC Transmit Status Register A transmission status flag is set in the transmit status register MACTXSTAT whenever the corresponding event occurs In addition an interrupt is generated if the corresponding enable bit in the transmit control register is set MAC TxFIFO parity error sets TxParErr and also clears MTxEn if the interrupt is enabled Table 7 34 MACTXSTAT Register MACTXSTATB 0 000000 0 00000000 Table 7 35 MAC Transmit Status Register Description These bits
519. t clock RXD 10M is shared with RXD 0 and it is a line for receiving data from the 10 Mbit s PHY DV 0 1 phis Receive Data Valid LINK 10M PHY asserts DV synchronously holding it active during the clock periods in which RXD 3 0 contains valid data received PHY asserts RX DV no later than the clock period when it places the first nibble of the start frame delimiter SFD on RXD 3 0 If PHY asserts RX DV prior to the first nibble of the SFD then RXD 3 0 carries valid preamble symbols LINK 10M is shared with RX DV and used to convey the link status of the 10 Mbit s endec The value is stored in a status register 1 20 ELECTRONICS S3C2500B PRODUCT OVERVIEW Table 1 1 S3C2500B Signal Descriptions Continue Group PinName Pad Type Ethernet RX ERR 0 phisd Receive Error ControllerO PHY asserts ERR synchronously 18 whenever it detects a physical medium error e g a coding violation PHY asserts RX ERR only when it asserts RX DV Ethernet MDC 1 phob12 Management Data Clock Controller1 The signal level at the MDC pin is used as a 18 timing reference for data transfers that are controlled by the MDIO signal COL_1 TX_CLK_1 phis Collision Detected Collision Detected for 10M COL is asserted asynchronously with minimum delay from the start of a collision on the medium in mode COL 10M is asserted when a 10 Mbit s PHY detects a collision phis Transmit Clock Transmit Clock for 10M The c
520. t is generated when a parity error OCCUIS You have to clear this bit by writing 1 to this bit If not UART may be stopped 14 9 SERIAL I O HIGH SPEED UART S3C2500B Table 14 6 High Speed UART Status Register Description Continued Overrun Error OER This bit automatically set to 1 whenever an overrun error occurs during a serial data receiving operation When HURXBUF has a previous valid data but a new received data is going to be written into HURXBUF during non FIFO mode and when a new received data is going to be written into RXFIFO with FIFO full during FIFO mode HUSTAT 4 is set to 1 If the OER interrupt enable bit HUINT 4 is 1 a interrupt is generated when a overrun error occurs You have to clear this bit by writing 1 to this bit If not UART may be stopped Control Character Detect HUSTAT 5 is automatically set to 1 to indicate that a control CCD character has been received If the CCD interrupt enable bit HUINT 5 is 1 an interrupt is generated when a control character is detected You can clear this bit by writing 1 to this bit NOTE Software flow control mode does not affects Tx Rx operation this bit This bit informs only whether UART receives control character or not Namely if user want to stop Tx Rx operation User must program that routine Data carrier Detect Lost This bit set to 1 if HUnDCDO HUnDCD pin is high at the time High DCDL Speed UART Receiver checks a newl
521. ta FIFO 11 8 Special Registers 12 3 Programmable Priority Registers 12 4 DCONO A 2 3 4 5 12 9 Control Register Description 12 9 DSAR0 1 2 3 4 5 and DDARO 1 2 3 4 5 12 12 DTGRO 1 2 3 4 5 nennen nnns 12 13 2 3 4 5 ReQiSters 12 14 DIPEOAR 2 3 BeglsterS 5 12 15 S3C2500B RISC MICROCONTROLLER xxxi List of Tables continued Table Title Page Number Number 13 1 Console UART Special Registers Overview 0 13 3 13 2 egeo WC 13 4 13 3 Console UART Control Register 13 4 13 4 516 62 55 13 8 13 5 Console UART Status Register Description 13 8 13 6 GUI MICE Mm 13 11 13 7 Console UART Interrupt Enable Register Description 13 11 13 8 cICICHM M m 13 13 13 9 Console UART Transmit Register 13 13 13 10 CURXBUF REGISTOS rater 13 14 13 11 Console UART Receive Register Description
522. ta come from High Speed UART Rx pin data are stored to Rx Buffer FIFO via shift register If valid Rx data are received High Speed UART generates interrupt or GDMA request signal Similar to Tx Block in case of FIFO it is same as Tx block Data should be stored as the same level of trigger level If there is an error on Rx data High Speed UART does not generate GDMA request signal but generates interrupt even in case of GDMA mode Although High Speed UART is FIFO mode if error data shift to FIFO top then High Speed UART generates interrupt Transfer unit is byte same as at Tx block 14 4 1 FIFO OPERATION Tx FIFO Operation If there is no valid data on trigger level of TX FIFO High Speed UART generates interrupt INT TXD or sends a request signal to GDMA During this operation trigger level should be 30 32 empty depth FIFO depth 24 32 16 32 or 8 32 CPU or GDMA fills data into TX FIFO by byte Rx FIFO Operation If received data are filled up to RX FIFO trigger level High Speed UART generate interrupt INT RXD or send request signal to GDMA The size of transferred data is 1 byte If RX data contains error in case of GDMA mode operation High Speed UART generates interrupt instead of sending request signal to GDMA Then CPU executes interrupt service routine for error data So GDMA transmits error free valid data only from received data 14 4 2 HARDWARE FLOW CONTROL Hardware Flow Control for Transmit Operation When CTS
523. ta transfer is in privileged mode code where setting the W bit forces non privileged mode for the transfer allowing the operating system to generate a user address in a system where the memory management hardware makes suitable use of this hardware 3 9 2 SHIFTED REGISTER OFFSET The 8 shift control bits are described in the data processing instructions section However the register specified shift amounts are not available in this instruction class See Figure 3 5 3 9 3 BYTES AND WORDS This instruction class may be used to transfer a byte B 1 or a word 0 between ARM9TDMI register and memory The action of LDR B and STR B instructions is influenced by the BIGEND control signal of ARM9TDMI core The two possible configurations are described below 3 9 3 1 Little Endian Configuration A byte load LDRB expects the data on data bus inputs 7 through 0 if the supplied address is on a word boundary on data bus inputs 15 through 8 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros Please see Figure 2 2 A byte store STRB repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0 The external memory system should activate the appropriate byte subsystem to store the data A word load LDR will normally use a word aligned address However an address
524. tat interface or to 0 if the frame was received over the 10 Reception halted MRxHalted This bit is set if the MRxEn bit is cleared or the MHaltlmm bit is set Control frame received This bit is set if the frame received is a MAC control frame type 0x8808 if the CAM recognizes the frame address and if the frame length is 64 bytes 81 12 Not applicable 7 30 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 4 2 8 MAC Station Management Data Register Table 7 40 STADATA Register STADATAB 00018 000000000 Table 7 41 Station Management Register Description 15 0 Station management data This register contains a 16 bit data value for the station management function ELECTRONICS 7 31 ETHERNET CONTROLLER S3C2500B 7 4 2 9 MAC Station Management Data Control and Address Register The MAC controller provides support for reading and writing station management data to the PHY Setting options in station management registers does not affect the controller Some PHYs may not support the option to suppress preambles after the first operation Table 7 42 STACON Register STACONA OxF00B001C Station management control and address 0x00006000 STACONB OxF00D001C Station management control and address 0x00006000 Table 7 43 STACON Register Description 4 0 PHY register address A 5 bit address contained in the PHY of the register to be MPHYRegAddr read or written 9 5
525. tatus Registers 2 1 00 nnne nnne 13 8 13 3 3 Console UART Interrupt Enable Register 0 na 13 11 13 3 4 UART Transmit Data 13 13 13 3 5 UART Receive Data 13 14 13 3 6 UART Baud Rate Divisor nnne 13 15 13 3 7 Console UART Baud Rate 13 16 13 3 8 UART Control Character Register 1 and 2 13 17 Chapter 14Serial High Speed UART 14 ine ettet n ul ttes 14 1 14 2 14 1 14 3 High Speed UART Special 14 3 14 3 1 High Speed UART Control Registers 14 4 14 3 2 High Speed UART Status 14 9 14 3 3 High Speed UART Interrupt Enable Register 14 14 14 3 4 High Speed UART Transmit Buffer Register 14 16 14 3 5 High Speed UART Receive Buffer 14 17 14 3 6 High Speed UART Baud Rate Divisor 2 14 18 14 3 7 High Speed UART Baud Rate 14 19 14 3 8 High Speed UART Control Character 1 14 20 14 3 9 Hig
526. tected the transmit data parity checker does the following e stops transmission e It sets the parity error bit in the transmit status register e t generates an interrupt if enabled 7 3 4 8 Transmission State Machine The transmission state machine is the central control logic for the transmitter block It controls the passing of signals the timers and the posting of errors in the status registers ELECTRONICS 7 5 ETHERNET CONTROLLER S3C2500B 7 3 5 THE MAC RECEIVER BLOCK It complies with the IEEE802 3 standard for carrier sense multiple access with collision detection CSMA CD protocol After it receives a frame the receiver block checks for a number of error conditions CRC errors alignment errors and length errors By setting bits in appropriate control registers some error condition is disabled Depending on the CAM status the destination address and the receiver block may reject an otherwise acceptable frame 7 3 5 1 MAC RxFIFO MRxFIFO The MRxFIFO accepts data one byte at a time The parity starts with the destination address The receiver updates the counter with the number of bytes received As the FIFO stores the data the CAM block checks the destination address against its stored address If the CAM recognizes the address the MRxFIFO continues receiving the frame If the CAM block does not recognize the address and rejects the frame the receiver block discards the frame and flushes the MRxFIFO 7 3 5 2 C
527. tection unit is disabled and all areas are effectively set to no access The protection space registers therefore must be programmed before the protection unit is enabled Table 2 13 Permission Encoding 00 Privileged mode access only 01 Privileged mode full access user mode read only 2 26 ELECTRONICS S3C2500B PROGRAMMER S MODEL 2 16 1 7 Register 6 Protection region base and size registers This register is used to define 16 programmable regions eight instruction eight data in memory These registers define the base and size of each of the eight areas of memory Individual control is provided for the instruction and data memory regions The values are ignored when the protection unit is disabled On reset only the region enable bit for each region is reset to 0 all other bits are undefined At least one instruction and data memory region must be programmed before the protection unit is enabled The opcode 2 field defines whether the data or instruction protection regions are to be programmed The CRm field selects the region number Table 2 14 CP15 Data Protection Region Registers Data memory region 2 MCR MRC p15 0 Rd c6 c4 0 Data memory region 4 Table 2 15 CP15 Instruction Protection Region Registers Instruction memory region 5 MCR MRC p15 0 Rd c6 c2 1 Instruction memory region 2 MCR MRC p15 0 Rd c6 c1 1 Instruction memory region 1 MCR MRC p15 0
528. ter Description 7 0 Transmit data This field contains the data to be transmitted over the single channel Console UART When this register is written the transmit data register empty bit in the status register CUSTAT 18 should be 1 This is to prevent overwriting of transmit data that may already be present in the CUTXBUF Whenever the CUTXBUF is written with a new value the transmit register empty bit CUSTAT 18 is automatically cleared to 0 31 8 7 0 7 0 Transmit data for UART Figure 13 6 Console UART Transmit Data Register ELECTRONICS 13 13 SERIAL CONSOLE UART S3C2500B 13 3 5 UART RECEIVE DATA REGISTER Table 13 10 CURXBUF Registers Register Address RW Description Sie Reset Value CURXBUF 0060010 R Console UART receive data register Table 13 11 Console UART Receive Register Description 7 0 Receive data This field contains the data received over the single channel Console UART When the Console UART finishes receiving a data frame the receive data ready bit in the Console UART status register CUSTAT 0 should be 1 This prevents reading invalid receive data that may already be present in the CURXBUF Whenever the CURXBUF is read the receive data valid bit CUSTATT 0 is automatically cleared to 0 31 8 7 0 Reeve Data 7 0 Receive data for UART Figure 13 7 Console UART Receive Data Register 13 14 ELECTRONICS S3C2500B SERIAL
529. ter during the following cycle inserting a dummy instruction such as MOV RO after the LDM will ensure safety 3 11 5 USE OF R15 AS THE BASE R15 should not be used as the base register in any LDM or STM instruction ELECTRONICS 3 43 INSTRUCTION SET S3C2500B 3 11 6 INCLUSION OF THE BASE IN THE REGISTER LIST When write back is specified the base is written back at the end of the second cycle of the instruction During a STM the first register is written out at the start of the second cycle A STM which includes storing the base with the base as the first register to be stored will therefore store the unchanged value whereas with the base second or later in the transfer order will store the modified value A LDM will always overwrite the updated base if the base is in the list 3 11 7 DATA ABORTS Some legal addresses may be unacceptable to a memory management system and the memory manager can indicate a problem with an address by taking the abort signal high This can happen on any transfer during a multiple register load or store and must be recoverable if ARM9TDMI is to be used in a virtual memory system 3 11 7 1 Aborts During STM Instructions If the abort occurs during a store multiple instruction ARM9TDMI takes little action until the instruction completes whereupon it enters the data abort trap The memory manager is responsible for preventing erroneous writes to the memory The only change to the internal state of th
530. ternal Data eee ELECTRONICS 5 11 MEMORY CONTROLLER S3C2500B Table 5 13 and 5 14 Using little endian and byte access Program Data path between register and external memory WA Address whose LSB is 0 4 8 C EA External Address HA Address whose LSB is 0 2 4 68 C E BA Address whose LSB is 0 1 2 3 4 5 6 7 8 9 A C D E F X Don t care Table 5 13 External 8 bit Datawidth Store Operation with Little Endian Transfer Width STORE CPU Reg External Memory Bit Num 31 0 31 0 31 0 CPU Register Data abcd xxab 1 CPU Address BA Bit Num 31 0 31 0 31 0 CPU Data Bus abcd abab aaaa Bit Num 7 0 7 7 7 0 7 0 7 0 7 0 External Data a d a b 0 0 b Timing Sequence ds 2nd a it Table 5 14 External 8 bit Datawidth Load Operation with Little Endian Transfer Width LOAD CPU Reg lt External Memory Bit Num 31 0 31 0 31 0 CPU Register Data abcd xxab CPU Address 10 1 1 Bit Num 7 0 0 7 0 7 0 7 0 7 0 7 0 External Data a b 2nd rd a b a Timing Sequence ist 4h it 2nd Bit Num 31 0 3 31 0 31 0 31 0 31 0 31 0 CPU Data Bus abxx abcx abcd axax abab aaaa 7 5 12 ELECTRONICS S3C2500B MEMORY CONTROLLER 5 6 EXT BANK CONTROLLER Ext I O Bank controller can be interfaceing ROM SRAM flash memory etc except SDRAM It also supports muxed bus memory device which shares address bus a
531. ternal Pin Multiplexed Signals Channel External Interface Default Signal PCM meer UcETXGA FOMFSCA iowa Esc DCE TXCA Dock moa IOM2DU moa DbcERXcA iome bor DCE DOERXDA oce Pom Fscs rowrsce Doe Pom Pom mos oce Axos Pow pors Pom Doe Axos Pom Doe Pomrsoo 9 4 4 OPERATION The Time Slot Assigner TSA controllers are configured as follows 1 Configure the TSAxCON register Define the start bit position for each TSA Define the stop bit position for each TSA Determine operating mode for each TSA DCE PCM highway non multiplexed or multiplexed and 2 interface Enable TSA by setting TSAEN bit in IOM2CON 13 to 1 Program each intended HDLC channel 9 4 4 1 Clock Divide In PCM mode the TSA provides each HDLC channel with proper clock according to its programmed timeslot In this process the clock frequency is either the same as or 1 2 times that of the external clock When the Divide bit in TSAxCON is set to 1 each HDLC
532. th normal or abnormal status 157 Not applicable 16 Tx complete to send control This bit is set each time the MAC sends a complete control frame TxCFcomp frame 17 BDMA Tx not owner This bit is set when BDMA is not owner and the transmission BTxNO process is stop 18 BDMA TxBUFF empty This bit is set when the BDMA TxBUFF is empty BTxEmpty 91 19 Not applicable 7 20 ELECTRONICS S3C2500B ETHERNET CONTROLLER 7 4 1 9 BDMA MAC Receive Interrupt Enable Register Table 7 20 BMRXINTEN Register BMRXINTENA 0xF00A001C BDMA MAC Rx Interrupt Enable Register 0x00000000 BMRXINTENB 0xF00C001C BDMA MAC Rx Interrupt Enable Register 0x00000000 Table 7 21 BDMA MAC Receive Interrupt Enable Register Description 0 Enable MAC Rx missed roll This bit enables MissRoll interrupt MissRolllE 1 Enable MAC Rx alignment This bit enables AlignErr interrupt AlignErrlE 2 Enable MAC Rx CRC error This bit enables CRCErr interrupt 3 Enable MAC Rx overflow This bit enables Overflow interrupt OverflowlE 4 Enable MAC Rx long error This bit enables LongErr interrupt LongErrlE 5 Enable MAC Rx receive parity This bit enables RxParErr interrupt RxParErrlE 157 Not applicable 16 Enable BDMA Rx done for This bit enables BRxDone interrupt every received frames BRxDonelE 17 Enable BDMA Rx not owner This bit enables BRxNO interrupt interrupt BRxNOIE
533. the MCU writes less than MAXP data then IINRDY bit has to be set by the MCU Default 0 14 13 15 CSR2 SETtable 0 USBEP1CSR 12 8 isn t overwritten when MCU CSR2SET writes a 32bit value to USBEP1CSR register 1 USBEP1CSR 12 8 is overwritten 16 Out mode Out This bit is valid only when endpoint 1 is set to OUT packet ReaDY The USB sets this bit once it has loaded a packet of OORDY data into the FIFO Once the MCU reads the FIFO for the entire packet this bit should be cleared by MCU 17 Out mode Fifo This bit is valid only when endpoint 1 is set to OUT FULL OFFULL Indicates no more packets can be accepted if USBEP1CSR 1 7 16 is 00 No packet in FIFO 01 1 packet in FIFO 11 2 packet of MAXP lt 1 2 FIFO size or 1 packet of MAXP gt FIFO size 18 Out mode This bit is valid only when endpoint 1 is set to OUT fifo OVER run ISO OOVER This bit is set if the core is not able to load an OUT ISO packet into the FIFO 19 Out mode Data This bit is valid only when endpoint 1 is set to OUT ERRor ODERR ISO This bit should be sampled with OORDY When set it indicates the data packet due to be unloaded by the MCU has an error either bit stuffing or CRC If two packets are loaded into the FIFO and the second packet has an error then this bit gets set only after the first packet is unloaded This is automatically cleared when OORDY gets cleared 10 26 ELECTRONICS S3C2500B USB CONTROLLER
534. the last FIFO register In 4 word transfer mode it is set to 1 when the data received is available in the last four 32 bit FIFO registers Even if the data reside in FIFO for only two words when the Last bit is set Rx FIFO is regarded as valid The received data available condition is cleared automatically when the data received is no longer available During DMA Rx operation this bit is always 0 so does not generate an interrupt 10 Tx Frame Good TxFG This bit set to one when one frame sent well ELECTRONICS 8 37 HDLC CONTROLLER S3C2500B Table 8 12 HSTAT Register Description Continued Bit Bit Name Description Number Rx flag detected RxFD This bit is set to 1 when the last bit of the flag sequence is received This bit generates an interrupt if enabled You can clear this bit by writing 1 to this bit Rx data carrier detected The DCD status bit mirrors the state of the nDCD input pin If nDCD input RxDCD pin is low this status bit is 1 If nDCD input pin is High it is 0 This bit does not generate an interrupt Rx stored data carrier This bit is set to 1 when a transition in nDCD input occurs and can detected RxSDCD generate interrupt if enabled You can clear this bit by writing a 1 to this bit Rx frame valid RxFV This bit signals frame s ending boundary to the CPU and also indicates that no frame error occurred It is set when the last data byte of a frame is transferred into t
535. til the instruction reaches the head of the pipeline If the instruction is not executed for example because a branch occurs while it is in the pipeline the abort does not take place If a data abort occurs the action taken depends on the instruction type Single data transfer instructions LDR STR write back modified base registers the Abort handler must be aware of this The swap instruction SWP is aborted as though it had not been executed Block data transfer instructions LDM STM complete If write back is set the base is updated If the instruction would have overwritten the base with data ie it has the base in the transfer list the overwriting is prevented All register overwriting is prevented after an abort is indicated which means in particular that R15 always the last register to be transferred is preserved in an aborted LDM instruction The abort mechanism allows the implementation of a demand paged virtual memory system In such a system the processor is allowed to generate arbitrary addresses When the data at an address is unavailable the Memory Management Unit MMU signals an abort The abort handler must then work out the cause of the abort make the requested data available and retry the aborted instruction The application program needs no knowledge of the amount of memory available to it nor is its state in any way affected by the abort After fixing the reason for the abort the handler should
536. times regardless of the network traffic ELECTRONICS 7 39 ETHERNET CONTROLLER S3C2500B The back off state machine The back off state machine implements the back off and retry algorithm of the 802 3 CSMA CD When a collision is detected the main transmission state machine starts the back off state machine s counters and waits for the back off time including zero to elapse This time is a multiple of 512 bit times that elapse before the frame that caused the collision is re transmitted Each time there is a collision for one single frame the back off state machine increments an internal retry attempt counter An 11 bit pseudo random number generator outputs a random number by selecting a subset of the value of the generator at any time The subset is incremented by one bit for each subsequent attempt This implementation is represented by the following equation 0 lt random integer r 2 min n back off limit 10 is the number of slot times the MAC must wait in case of a collision and n is the number of retry attempts For example after the first collision is 1 and is a random number between 0 1 The pseudo random generator in this case is one bit wide and gives a random number of either 0 or 1 After the second attempt r is a random number between 0 and 3 Therefore the state machine looks at the two least significant bits of the random generator n 2 which gives a value between 0 and 3
537. to encode LSR 32 which has a zero result with bit 31 of Rm as the carry output Logical shift right zero is redundant as it is the same as logical shift left zero so the assembler will convert LSR 0 and ASR 0 and ROR 0 into LSL 0 and allow LSR 32 to be specified An arithmetic shift right ASR is similar to logical shift right except that the high bits are filled with bit 31 of Rm instead of zeros This preserves the sign in 2 s complement notation For example ASR 5 is shown in Figure 3 8 5 4 0 Contents of Rm carry out Value of Operand 2 Figure 3 8 Arithmetic Shift Right The form of the shift field which might be expected to give ASR 0 is used to encode ASR 32 Bit 31 of Rm is again used as the carry output and each bit of operand 2 is also equal to bit 31 of Rm The result is therefore all ones or all zeros according to the value of bit 31 of Rm ELECTRONICS 3 13 INSTRUCTION SET S3C2500B Rotate right ROR operations reuse the bits which overshoot in a logical shift right operation by reintroducing them at the high end of the result in place of the zeros used to fill the high end in logical right operations For example ROR 5 is shown in Figure 3 9 The form of the shift field which might be expected to give ROR 0 is 31 5 4 0 Contents of Rm carry out Value of Operand 2 Figure 3 9 Rotate Right used to encode a special function of the barrel shifter rotate right extended RRX This i
538. toggle upon reaching zero the value in the time constant register is loaded into the counter and the process is repeated The time constant may be changed any time but the new value does not take effect until the next load of the counter The output of the baud rate generator may be used as either the transmit clock the receive clock or both It can also drive the digital phase locked loop If the receive or transmit clock is not programmed to come from the TXC pin the output of the baud rate generator may be echoed out via the TXC pin The following formula relates the time constant to the baud rate where 2 or RXC is the baud rate generator input frequency in Hz BRG generates 2 output signals BRGOUT1 BRGOUT2 for transmit receive clocks and the DPLL input clock BRGOUT1 or CNTO 1 169 BRGOUT2 BRGOUT1 1 or 16 or 32 according to CNT2 value of the HBRGTC MCLK2 MCLK 2 RxC 12 bit counter Divide by Divide by BRGOUT2 1 or 16 1 or 16 or 32 BRGOUT1 CNTO HBRGTC 15 4 BRGCLK HBRGTC 3 2 CNT2 HBRGTC 1 0 BRGCLK HMODE 19 Figure 8 2 Baud Rate Generator Block Diagram ELECTRONICS 8 7 HDLC CONTROLLER S3C2500B The example in the following Table assumes a 66MHz clock from 2 a 24 576MHz clock from RxC showing a time constant for a number of commonly used baud rates Table 8 2 Baud Rate Example of HDLC BRGOUT2 CNTO CNT2
539. top 11 0 The location of START bit of time slot 23 12 The location of STOP bit of time slot 25 24 MODE 00 DCE 01 PCM Highway non multiplexed 10 IOM2 11 Highway multiplexed 26 Divide 0 1 x Clock mode 120 5 x Clock mode Figure 9 19 TSA A Control Register ELECTRONICS 9 23 IOM2 CONTROLLER S3C2500B 9 5 12 TSA B CONTROL REGISTER Table 9 16 TSABCON TSA B Control Register RW TSABCON 0xF0130034 TSA B Control Register 0x00000000 11 0 START The location of start bit of time slot assigned to HDLCB 23 12 STOP The location of stop bit of time slot assigned to HDLCB 25 24 MODE 00 DCE 01 PCM highway non multiplexed 10 IOM2 11 PCM highway multiplexed 26 Divide 0 HDLC clock is the same clock as the external clock 1 HDLC clock is 1 2 times the external clock 8127 Reserved 31 30 29 28 27 26 25 24 23 12 11 0 2 11 0 The location of START bit of time slot 23 12 The location of STOP bit of time slot 25 24 MODE 00 DCE 01 PCM Highway non multiplexed 10 IOM2 11 Highway multiplexed 26 Divide 0 1 x Clock mode 120 5 x Clock mode Figure 9 20 TSA B Control Register 9 24 ELECTRONICS S3C2500B IOM2 CONTROLLER 9 5 13 TSA C CONTROL REGISTER Table 9 17 TSACCON TSA C Control Register TSACCON 0xF0130038 TSA C Control Register 0x00000000 11 0 START The location of start bit of t
540. top conditions are always generated by the master The bus is considered to be busy after the start condition is generated The bus is considered to be free again when a brief time interval has elapsed following the stop condition Start condition High to Low transition of the SDA line while SCL is high Stop condition a Low to High transition of the SDA line while SCL is high j r C j Start Address R W ACK Condition Condition Figure 6 4 Start and Stop Conditions ELECTRONICS 6 5 2 CONTROLLER S3C2500B 6 4 6 DATA TRSANSFER OPERATIONS 6 4 6 1 Data Byte Format Every data byte that is put on the SDA line must be 8 bits long The number of bytes that can be transmitted per transfer is unlimited Each byte must be followed by an acknowledge bit Data is transferred MSB first If the receiver cannot receive another complete byte of data until it has performed some other functions such as servicing an internal interrupt it can hold the clock line SCL low to force the transmitter into a wait state The data transfer then continues when the receiver is ready for another byte of data and releases the SCL line 6 4 6 2 Acknowledge Procedure Data transfer with acknowledge is obligatory The acknowledge related clock pulses must be generated by the bus master The transmitter releases the SDA line High during the acknowledge clock pulse The receiver must pull down the SDA line during the acknowledge pulse
541. tor Collision Interrupt Enable MCOLIE 0 Disable 1 Enable 7 Monitor Transmit Buffer Available Interrupt Enable MTxBAIE 0 Disable 1 Enable 8 Monitor Receive Buffer Available Interrupt Enable MRxBAIE 0 Disable 1 Enable 9 Monitor Transmit Abort Detected Interrupt Enable MTxABTIE 0 Disable 1 Enable 10 IC Buffer Available Interrupt Enable ICBAIE 0 Disable 1 Enable 11 ALIVE Interrupt Enable ALIVEIE 0 Disable 1 Enable 12 NEWFSC Interrupt Enable NEWFSCIE 0 Disable 1 Enable Figure 9 9 IOM2 Interrupt Enable Register ELECTRONICS 9 17 IOM2 CONTROLLER S3C2500B 9 5 4 2 TIC BUS ADDRESS REGISTER Table 9 6 IOM2TBA Register TIC Bus Address Register RW IOM2TBA 0 013000 TIC Bus Address 0x00000007 2 0 TIC Bus Address TBA This field defines device specific address used to gain access to TIC bus for D and channel Gp 7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 131211109 8 7 6 5 4 32 2 0 TIC Bus Address Figure 9 10 2 TIC Bus Address Register 9 18 ELECTRONICS S3C2500B IOM2 CONTROLLER 9 5 5 IOM2 IC CHANNEL TRANSMIT DATA REGISTER Table 9 7 IOM2ICTD 2 IC Channel Transmit Data Register IOM2ICTD OxF0130010 IC Channel Transmit Data 0x000000FF zo Jim sup Reed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 7 0 IC Channel Transmit Data Figure 9 11
542. transmitted are stored into this register at first in FIFO mode if next buffer has invalid data then shifted to next buffer But in non FIFO mode a new data to transmit will be moved from HUTXBUF to Tx shift register The High Speed UART transmit buffer registers HUTXBUF contain an 8 bit data value to be transmitted over the High Speed UART channel Table 14 9 HUTXBUF Registers HUTXBUF OxF007000C W High Speed UART transmit buffer register 008000 Table 14 10 High Speed UART Transmit Register Description 7 0 Transmit data This field contains the data to be transmitted over the single channel High Speed UART When this register is written the transmit buffer register empty bit in the status register HUSTAT 18 should be 1 This is to prevent overwriting of transmit data that may already be present in the HUTXBUF Whenever the HUTXBUF is written with a new value the transmit register empty bit HUSTAT 18 is automatically cleared to 31 8 7 0 7 0 Transmit data for UART Figure 14 5 High Speed UART Transmit Buffer Register 14 16 ELECTRONICS S3C2500B SERIAL HIGH SPEED UART 14 3 5 HIGH SPEED UART RECEIVE BUFFER REGISTER S3C2500B has a 32 byte Receive FIFO and the bottom of FIFO is HURXBUF All data to be received are stored in this register at first in FIFO mode if next buffer has invalid data then shifted to next buffer But in non FIFO mode a new received data will be moved to HURXBUF
543. tructions are executed within interrupt or exception routines Register 15 holds the Program Counter PC In ARM state bits 1 0 of R15 are zero and bits 31 2 contain the PC In THUMB state bit 0 is zero and bits 31 1 contain the PC Register 16 is the CPSR Current Program Status Register This contains condition code flags and the current mode bits FIQ mode has seven banked registers mapped to R8 14 R8 fiq R14 In ARM state many FIQ handlers do not need to save any registers User IRQ Supervisor Abort and Undefined each have two banked registers mapped to R13 and R14 allowing each of these modes to have a private stack pointer and link registers 2 4 ELECTRONICS S3C2500B PROGRAMMER S MODEL ARM State General Registers and Program Counter Supervisor Undefined ARM State Program Status Register CPSR CPSR CPSR CPSR CPSR NSPSH svc M SPSR abt SPSR NSPSHR und banked register Figure 2 3 Register Organization in ARM State ELECTRONICS 2 5 PROGRAMMER S MODEL S3C2500B 2 7 2 The THUMB State Register Set The THUMB state register set is a subset of the ARM state set The programmer has direct access to eight general registers RO R7 as well as the Program Counter PC a stack pointer register SP a link register LR and the CPSR There are banked stack pointers link registers and Saved Process Status Registers SPSRs for each privileged mode This is shown in Figure 2 4 THUMB State
544. try Tfig At the end of this time ARM9TDMI will be executing the instruction at Ox1C Tsyncmax is 3 processor cycles is 20 cycles Texc is 3 cycles and Tfiq is 2 cycles The total time is therefore 28 processor cycles This is just over 1 4 microseconds in a system which uses a continuous 20 MHz processor clock The maximum IRQ latency calculation is similar but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time The minimum latency for FIQ or IRQ consists of the shortest time the request can take through the synchroniser Tsyncmin plus This is 4 processor cycles 2 12 RESET When the nRESET signal goes LOW ARM9TDMI abandons the executing instruction and then continues to fetch instructions from incrementing word addresses When nRESET goes HIGH again 1 Overwrites R14 svc and SPSR svc by copying the current values of the PC and CPSR into them The value of the saved PC and SPSR is not defined Forces M 4 0 to 10011 Supervisor mode sets the F bits in the CPSR and clears the CPSR s T bit Forces the PC to fetch the next instruction from address 0 00 Execution resumes in ARM state 2 16 ELECTRONICS S3C2500B PROGRAMMER S MODEL 2 13 INTRODUCTION FOR ARM940T The ARM940T cached processor macrocell is a member of the ARM9 Thumb Family of high performance 32 bit system on a chip processor solutions It is
545. ts of delay time between read and write operations 8 5 4 2 Transmitter DMA Mode To use DMA operation without CPU intervention you have to make Tx buffer descriptor in advance And set the DMA Tx buffer descriptor pointer DMATxPTR register to the address of the first buffer descriptor set the Tx Buffer Descriptor Maximum Count TxBDMAXCNT register which shows the maximum buffer descriptor counts and then DMA Tx channel should be enabled When Tx underrun or CTS lost condition occurs during DMA operation DMA Tx enable bit HCON 6 is cleared and DMA Tx operation is stopped This situation is reported to system with DTxABT bit set HSTAT 22 In case of Tx underrun abort signal sent and then idle pattern is sent if TxEN bit is set In case of CTS lost TxD output goes high state as long as CTS remains high level ELECTRONICS 8 15 HDLC CONTROLLER S3C2500B 8 5 5 HDLC RECEIVER OPERATION The HDLC receiver is provided with data and a pre synchronized clock by means of the RXD and the internal DPLL clock the TXC pin or the RXC pin The data is a continuous stream of binary bits One of the characteristics of this bit stream is that a maximum of five consecutive 1s can occur unless an abort flag or idle condition occurs The receiver continuously searches bit by bit for flags and aborts When flag is detected the receiver synchronizes the frame to the flag timing If a series of flags is received the receiver re synchronizes the fr
546. uction Cycle Times 3 69 3 22 Format 3 Move Compare Add Subtract Immediate nnns 3 70 322 l Operations EM 3 70 3 22 2 Instruction Cycle 5 3 70 3 23 Format 4 ALU Operations 3 71 S23 F Operation MEME ES 3 71 3 23 2 Instruction Cycle nnn nensis 3 72 3 24 Format 5 Hi Register Operations Branch 3 73 324 Tic lo ORNA c Dc 3 73 3 24 2 Instruction Cycle 5 3 74 3 24 3 The Bx 5 3 74 3 24 4 Using R15 as an 2 nat 3 75 3 25 Format 6 PC Relative 3 76 3 25 EO Io PCMCIA 3 76 3 25 2 Instruction Cycle 5 3 76 3 26 Format 7 Load Store With Register 3 77 326 ROREM 3 77 3 26 2 Instruction Cycle 5 3 78 3 27 Format 8 Load Store Sign Extended 3 79 S21 RR cc 3 79 3 27 2 Instruction Cycle 0 0 4 3 80 vi S3C2500B RISC MICROCONTROLLER Table of Contents Continued Chapter 3 Instruction Set Continued 3 28 Format 9 Load Store
547. uction into LR move CPSR to SPSR load the SWI vector address 0x8 into the PC Switch to ARM state and enter SVC mode NOTE Value 8 is used solely by the SWI handler it is ignored by the processor 3 36 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 24 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples SWI 18 Take the software interrupt exception Enter Supervisor mode with 18 as the requested SWI number ELECTRONICS 3 93 INSTRUCTION SET S3C2500B 3 37 FORMAT 18 UNCONDITIONAL BRANCH 15 14 13 10 i 12 11 10 0 Immediate Value Figure 3 47 Format 18 3 37 1 OPERATION This instruction performs a PC relative Branch The THUMB assembler syntax is shown below The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction Table 3 25 Summary of Branch Instruction THUMB Assembler ARMEquivalent 7 O B label BAL label half word offset Branch PC relative Offset11 lt lt 1 where label is PC 2048 bytes NOTE The address specified by label is a full 12 bit two s complement address but must always be half word aligned ie bit O set to 0 since the assembler places label gt gt 1 in the Offset11 field Examples here B here Branch onto itself Assembles to OXE7FE
548. uency 6 2 ELECTRONICS S3C2500B 2 CONTROLLER 6 4 PC CONCEPTS 6 4 1 BASIC OPERATION The has two wires a serial data line SDL and a serial clock line SCL to carry information between the ICs connected to the bus Each IC is recognized by a unique address and can operate as either a transmitter or receiver depending on the function of the specific ICs The is a multi master bus This means that more than ICs which are capable of controlling the bus can be connected to it Data transfers proceed as follows Case 1 A master IC wants to send data to another IC slave 1 Master addresses slave 2 Master sends data to the slave master is transmitter slave is receiver 3 Master terminates the data transfer Acknowledge Acknowledge _ from receiver from receiver SDA by Receiver SCL from Address RW ACK Condition Condition Figure 6 2 Master Transmitter and Slave Receiver Case 2 A master IC wants to receive information from another IC slave 1 Master addresses slave 2 Master receives data from the slave master is receiver slave is transmitter 3 Master terminates the data transfer ELECTRONICS 6 3 2 CONTROLLER S3C2500B Acknowledge Acknowledge from i from receiver transmitter SDA by Transmitter SDA by Receiver SCL from Master Address R W ACK Condition Condition Figure 6 3 Master Receiver and Slave Transmitter Even in this case the
549. umes fixed cycle per block 25 cycles for DES and 65 cycles for 3DES If the DES operating frequency is 133MHz and the DES has one block to be encrypted the DES performance is 341 Mbps for DES or 131 Mbps for 3DES For more real system condition the user have to consider how many cycles is needed for external memory access The memory access cycle should be included the performance calculation as follows DES Performance Calculation Formula num of block x 64 bit time of one period x of block x Cae Cmem2des time of one period 7 5 ns if operating frequency is 133 MHz 25 for DES 65 for 3DES the cycle from external memory to DESINFIFO Oges2men the cycle from DESOUTFIFO to external memory ELECTRONICS 11 11 S3C2500B GDMA CONTROLLER GDMA CONTROLLER 12 1 OVERVIEW The S3C2500B has a six channel General DMA controller called the GDMA The six channel GDMA performs the following data transfers without CPU intervention e Memory to Memory Memory to from Memory Memory to from USB e External Device to Memory External Device to from Memory e HUARTO 1 to Memory High speed UART serial port0 1 to from Memory e DES to Memory DES to from Memory The on chip can be started by software and or an external request HUARTO request HUART1 request or DES request Software can also be used to restart a GDMA ope
550. users need to byte swapped key value they can control it by using DESCON 12 If DESCON 12 is set byte swapped key is written to DESKEY2L Otherwise original key is written to DESKEY2L Table 11 9 DES 3DES Key 2 Right Side Register Description 33 64 Key 2 Right Half The right half of the Key2 should be stored to this register The 8 bit of each byte is parity bit and it isn t used for encryption decryption 11 6 ELECTRONICS S3C2500B DES 3DES If users need to byte swapped key value they can control it by using DESCON 12 If DESCON 12 is set byte swapped key is written to DESKEY2R Otherwise original key is written to DESKEY2R ELECTRONICS 11 7 DES 3DES S3C2500B 11 3 7 DES 3DES KEY 3 LEFT SIDE REGISTER Table 11 10 DES 3DES Key 3 Left Side Register Description 1 32 Key 3 Left Half The left half of the Key3 should be stored to this register The 8 bit of each byte is parity bit and it isn t used for encryption decryption If users need to byte swapped key value they can control it by using DESCON 12 If DESCON 12 is set byte swapped key is written to DESKEY3L Otherwise original key is written to Table 11 11 DES 3DES Key 3 Right Side Register Description 33 64 Key 3 Right Half The right half of the Key3 should be stored to this register The 8 bit of each byte is parity bit and it isn t used for encryption decryption If users need to byte swapped key value they c
551. ush are as follows e Write miss there is a write to SDRAM address outside the current merging quad word address e Read hit there is a read from the same address as the merging quad word e Write buffer time out the write buffer timer reaches zero e The write buffer is disabled When read hit the write back operation is completed before the requested data is read from memory to maintain data consistency between the write buffer and SDRAM memory 5 7 7 SELF REFRESH The SDRAM controller provides the auto refresh REF and self refresh SREF command to sustain the contents of the SDRAM The auto refresh is issued to SDRAM periodically when refresh timer is expired The self refresh is entered and exited by request of on chip power manager The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM In self refresh mode the SDRAM ignores all the input signals except CKE The refresh addressing and timing are internally generated to reduced power consumption Before disabling clock of the SDRAM controller the SDRAM must be in self refresh mode to sustain the SDRAM memory data Self refresh mode might be entered or exited by asserting or deasserting the self refresh request bit SRreg of the peripheral clock disable register PCLKDIS It is possible to know if the SDRAM is in self refresh mode or not by reading out the SRreg bit SRack bit of the PCLKDIS register If the self refresh mode change
552. value in a PSR Programs should not rely on specific values from the reserved bits when checking the PSR status since they may read as one or zero in future processors A read modify write strategy should therefore be used when altering the control bits of any PSR register this involves transferring the appropriate PSR register to a general register using the MRS instruction changing only the relevant bits and then transferring the modified value back to the PSR register using the MSR instruction Examples The following sequence performs a mode change MRS RO CPSR Take a copy of the CPSR BIC RO RO 0x1F Clear the mode bits ORR RO RO Znew mode Select new mode MSR CPSR RO Write back the modified CPSR When the aim is simply to change the condition code flags in a PSR a value can be written directly to the flag bits without disturbing the control bits The following instruction sets the N Z C and V flags MSR CPSR flg 40xF0000000 Setall the flags regardless of their previous state does not affect any control bits No attempt should be made to write an 8 bit immediate value into the whole PSR since such an operation cannot preserve the reserved bits 3 6 3 INSTRUCTION CYCLE TIMES PSR transfers take 1S incremental cycles where S is defined as sequential S cycle ELECTRONICS 3 21 INSTRUCTION SET S3C2500B 3 6 4 ASSEMBLER SYNTAX MRS transfer PSR contents to a register MRS cond Rd lt psr gt
553. ver discards the current frame data without dropping the flag synchronization You can use this feature to ignore a frame with a non matched address 8 16 ELECTRONICS S3C2500B HDLC CONTROLLER 8 5 5 2 Receiver DMA Mode To use DMA operation without CPU intervention you have to make Rx buffer descriptor in advance And set the DMA Rx buffer descriptor pointer DMARxPTR register to the address of the first buffer descriptor set the Rx Buffer Descriptor Maximum Count RxBDMAXCNT register which shows the maximum buffer descriptor counts and then DMA Rx channel should be enabled 8 5 6 HARDWARE FLOW CONTROL TxClock last RTS CTS Figure 8 7 nCTS Already Asserted When nCTS is active and there exists data to be transmitted in Tx FIFO nRTS enters Low allowing data transmission At the beginning of the data is an open flag while at the end a closing flag If the frame being transferred discontinues nRTS goes back to the High after the data transmission is completed TxClock 4 5 13 5 RTS 14 22 cycles i CTS 1 Figure 8 8 CTS Lost During Transmission When the condition of nCTS is shifted from Low to High it is detected at the falling edge of Tx clock where nRTS also goes High For about 5 to 13 cycles after nRTS enters High the data transmission continues nRTS remains High for a maximum of 22 cycles and goes
554. w external devices can sample the external GDMA ACK signal by setting DCON 16 13 bits DCON 16 13 bits provide the range of 1 and 16 cycles of the external GDMA ACK signal NOTE The block mode can be used only with the external GDMA request mode 12 4 3 HUART MODE S3C2500B has two HUARTs channel 0 1 2 can transmit the data of HUARTO channel 3 4 5 can transmit the data HUART1 If mode selection bit 3 1 to 010 or 011 gets ready to communicate with HUART If GDMA mode is 010 HUART TX mode and GDMA receives the request signal transmitted from HUART GDMA transfers Tx data of HUART in memory into Tx buffer FIFO of HUART If GDMA mode is 011 HUART RX mode and GDMA receives the request signal transmitted from HUART GDMA transfers Rx data of Rx buffer FIFO of HUART into memory When GDMA transmits the data of HUART GDMA operates in the unit of byte If it is requested by HUART only one byte is transmitted and waits the following request At this time if GDMA transfer count register is zero the operation ends NOTE In HUART mode you should set byte 00 on transfer size TS 7 6 of DCON register In HUART TX mode you don t need to care the destination address direction DD 11 10 of DCON register either the DDAR register In HUART RX mode you don t need to care the source address direction SD 9 8 of DCON register either the DSAR register 12 16 ELECTRONICS S3C
555. which significantly simplifies the software data abort handler e The ARM9TDMI fully implements the instruction set extension spaces added to the ARM 32 bit instruction set in architecture v4 and v4T These differences are explained in more detail below ELECTRONICS 2 19 PROGRAMMER S MODEL S3C2500B 2 15 1 DATA ABORT MODEL The base restored data abort model differs from the base updated data abort model implemented by ARM7TDMI The difference in the data abort model affects only a very small section of operating system code the data abort handler It does not affect user code With the base restored data abort model when a data abort exception occurs during the execution of a memory access instruction the base register is always restored by the processor hardware to the value the register contained before the instruction was executed This removes the need for the data abort handler to unwind any base register update which may have been specified by the aborted instruction The base restored data abort model significantly simplifies the software data abort handler 2 15 2 INSTRUCTION SET EXTENSION SPACES All ARM processors implement the undefined instruction space as one of the entry mechanisms for the undefined instruction exception That is ARM instructions with opcode 27 25 00011 and opcode 4 1 are undefined on all ARM processors including the ARM9TDMI and ARM7TDMI ARM Architecture v4 and v4T also introduced a number of inst
556. wn in Figure 3 4 28 27 26 25 24 21 20 19 16 15 12 11 0 Lus po T T 15 12 Destination Register 0 Branch 1 Branch with Link 19 16 1st operand Register 0 Branch 1 Branch with Link 20 Set condition Codes 0 Do not after condition codes 1 Set condition codes 24 21 Operation Code 0000 AND Rd Op1 AND Op2 0001 EOR Rd Op1 EOR Op2 0010 SUB Rd Op1 Op2 0011 RSB Rd 2 1 0100 ADD Rd 1 2 0101 ADC Rd 1 2 0110 SBC Rd 1 2 1 0111 RSC Rd 2 1 1 1000 TST set condition codes AND 1001 TEO set condition codes EOR 1010 CMP set condition codes on Op1 Op2 1011 SMN set condition codes on 1100 Op1 OR 1101 MOV Rd 2 1110 BIC Rd Op1 AND NOT Op2 1111 MVN Rd NOT Op2 25 Immediate Operand 0 Operand 2 is a register 1 Operand 2 is an immediate Value 11 0 Operand 2 Type Selection 11 3 4 0 3 0 2nd Operand Register 11 4 Shift applied to Rm 11 8 7 0 7 0 Unsigned 8 bit immediate value 11 8 Shift applied to Imm 31 28 Condition Field Figure 3 4 Data Processing Instructions ELECTRONICS 3 9 INSTRUCTION SET S3C2500B The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands The first operand is always a register Rn The second op
557. xLittle format HTxFIFO is in Little endian If this bit is set to 1 the data on the system bus is Little endian If this bit is set to 0 the data on the system bus is in Big endian that is the data bytes are swapped to be Little endian format It is used only by the Transmitter Interrupt Mode not by the Transmitter DMA Mode see 8 14 Rx Transparent mode If this bit set to one HDLC Rx operates transparent mode Otherwise RxTRANS operates HDLC mode 7 Tx Transparent mode If this bit set to one HDLC Rx operates transparent mode Otherwise TxTRANS operates HDLC mode 10 8 Tx preamble length These bits determine the length of preamble to be sent before the TxPL opening flag when the TxPRMB bit is set in the control register 000 1byte 001 2bytes and 111 8bytes will be sent 111 Not applicable ELECTRONICS 8 27 HDLC CONTROLLER S3C2500B Table 8 8 HMODE Register Description Continued Bit Bit Name Description Number 14 12 Data formats DF When the DF bits are 000 data is transmitted and received in the NRZ data format When DF is 001 the NRZI zero complement data format is selected DF 010 selects the FMO data format DF 011 the FM1 data format and DF 100 the Manchester data format 15 RTR RTS mode select RTR RTS mode select bit When RTRnRTS is 0 the mode is RTRnRTS RTS Request To Send when RTRnRTS is 1 the mode is RTR Received To Ready 18 16
558. y of entry points for routines which perform the various supervisor functions 3 13 3 INSTRUCTION CYCLE TIMES Software interrupt instructions take 2S 1N incremental cycles to execute where S and are defined as squential S cycle and non squential N cycle ELECTRONICS 3 49 INSTRUCTION SET 3 13 4 ASSEMBLER SYNTAX SWI cond expression S3C2500B cond Two character condition mnemonic Table 3 2 lt expression gt Evaluated and placed in the comment field which is ignored by ARM9TDMI Examples SWI ReadC Get next character from read stream SWI Writel Outputa to the write stream SWINE 0 Conditionally call supervisor with O in comment field Supervisor code The previous examples assume that suitable supervisor code exists for instance 0x08 B Supervisor EntryTable DCD ZeroRtn DCD ReadCRin DCD WritelRtn Zero EQU 0 ReadC EQU 256 Writel EQU 512 Supervisor STMFD R13 RO R2 R14 LDR RO R14 4 BIC RO RO 0xFFO000000 MOV R1 R0 LSR 8 ADR R2 EntryTable LDR R15 R2 R1 LSL 2 WritelRtn LDMFD _ R13 4RO0 R2 R15 3 50 SWI entry point Addresses of supervisor routines SWI has routine required in bits 8 23 and data if any in bits 0 7 Assumes R13 5 points to a suitable stack Save work registers and return address Get SWI instruction Clear top 8 bits Get routine offset Get start address of entry table Branch to appropriate routine Enter with
559. y received data whether the data is good frame or not If the DCD interrupt enable bit HUINT 6 is 1 a interrupt is generated when a data carrier is detected This bit can be used for error check bit in hardware flow control mode Receive FIFO Data In Receive FIFO mode this bit indicate Receive FIFO has valid data trigger level reach and reach Rx trigger level So High Speed UART request DMA to RFREA move data in Receive FIFO In non FIFO mode if HURXBUF has a received data this bit is set to 1 also An interrupt or DMA request is generated when 7 is 1 In case HUCON 3 2 2 01 and HUINT 7 1 interrupt requested and HUCON 3 2 10 11 DMA request occurred You can clear this bit by reading Receive FIFO or HURXBUF with a good data If any error this bit is cleared by writing 1 to corresponding error bit in HUSTAT register 8 Receive FIFO empty This bit is only for CPU to monitor High Speed UART When Receive FIFO is empty this bit is set to 1 After reset default value is 1 This bit is only for CPU to monitor High Speed UART When Receive FIFO is full this bit is set to 1 After reset default value is 0 Receive FIFO overrun This bit is set to 1 when Receive FIFO overrun occurs during the RFOV Receive FIFO mode You can clear this bit by writing 1 to this bit This bit is only for CPU to monitor the receiver state of High Speed UART The RxIDLE status bit indicates that the inactive
560. yte into bits 7 to O of the destination register and bits 31 to 8 of the destination register are set to the value of bit 7 the sign bit The LDRSH instruction loads the selected Half word into bits 15 to 0 of the destination register and bits 31 to 16 of the destination register are set to the value of bit 15 the sign bit The action of the LDRSB and LDRSH instructions is influenced by the BIGEND control signal The two possible configurations are described in the following section 3 10 4 ENDIANNESS AND BYTE HALF WORD SELECTION 3 10 4 1 Little Endian Configuration A signed byte load LDRSB expects data on data bus inputs 7 through to 0 if the supplied address is on a word boundary on data bus inputs 15 through to 8 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bit of the destination register and the remaining bits of the register are filled with the sign bit bit 7 of the byte Please see Figure 2 2 A half word load LDRSH or LDRH expects data on data bus inputs 15 through to 0 if the supplied address is on a word boundary and on data bus inputs 31 through to 16 if it is a half word boundary A 1 1 The supplied address should always be on a half word boundary If bit 0 of the supplied address is high then the ARM9TDMI will load an unpredictable value The selected half word is placed in the bottom 16 bits of the destination register For unsigned half words LDRH the top 16 bits of the r

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