Laboratory Experiment 6 EE348L Spring 2005
Contents
1. Madhavan Page 11 of 22 EE348L Spring 2005 2 he above means that Vps gt 2V is sufficient to ensure that MOSFET M is in saturation under reasonable variations of temperature and device parameters Using the above design choices we get K 6 9 LET 6 9 6 10 Em2 4 KN 32 R 2 2 AV Vy 6 11 pe is Vo 6 11 Ra EDD 6 12 I K Substituting the above into the expression for the magnitude of the small signal gain A we get K 32 qU T gy s2 6 13 eal va Lee 4 K The magnitude of the ac small signal gain of the source follower amplifier in Figure 6 7 is detailed in Table 6 2 for different values of Vs It can be seen for that Vso gt 2 the increase in the magnitude of the gain of the source follower is very small Based on the results in Table 6 2 we choose Vs 2 25V This implies that with the design choice of Ves2 Vin Ves2 1V 0 25 V Vez 3 5V 4 Table 6 2 Relationship between Vs and A HSpice dc simulations of a 2N7000 MOSFET as was done in the biasing supplement of laboratory experiment 5 with gate to source voltage of 0 25V source and bulk terminals at the same potential drain to source voltage of 3V ensuring that MOSFET M remains in saturation gives a dc drain current of 5 mA and a transconductance of 29 42 mS Therefore lp 5 18mA and gm2 29 42 mS This gives Rego 2 25V 5 18mA 434 4 Q Since we chose Vs 2 25V based on the r2. Your answer should indicate B Madhavan 20 of 22 EE348L Spring 2005 i how you arrived at the dc operating point of the common source amplifier ii how the component values were chosen ili Show that the calculated small signal gain is in good agreement with that obtained from your HSpice simulations iv As shown in Table 6 3 tabulate the variation in mid band frequency range of 1000 Hz to 1E5 Hz small signal gain due to variation in load resistance R for 100 Q 1 KQ 10KQ 100 KQ and 1E6 Q v Submit the results of a transient simulation with a 20mV peak to peak sinusoidal input at 10 KHz Does the gain inferred from the transient simulation agree with the gain obtained from the frequency response small signal simulation in HSpice Why or Why not 3 Derive the small signal output resistance of the common source amplifier featured in Figure 6 3 taking into account the small signal MOSFET drain to source resistance fas 4 Derive the small signal gain and output resistance of the common source cascode in Figure 6 4 taking into account the small signal MOSFET drain to source resistance ras 5 Neglecting the load but taking into account the small signal MOSFET drain to source resistance rg how much greater is the common source cascode output resistance as compared to the traditional common source amplifier This means the output resistance Rout looking down the drain of the MOSFET M for the cascode in Figure 6 4 an
3. Figure 6 13 Figure 6 14 Figure 6 9 Schematic diagram of a common source amplifier Bias circuitry is not shown 5 An Ideal Common source Configuration Bias circuitry is not shown 6 A common source with a current mirror load Bias circuitry is not shown T Common source cascode Bias circuitry is not shown eeeeeeeeeeeeesesee 7 C ascode Current MOM oi oiu auti ot dee coats Saat eoo bladum tus del a su tied 8 Common source amplifier with variable load impedance R The signal source is not SIOWI d uses veces dosi las des uoa pA Semis eL edic dint e di cime caue cia 9 Gain variation of the common source amplifier in Figure 6 6 due to variation in the BREMEN UCET 10 Source follower amplifier schematic with dc blocking capacitors C and Cc isolating the dc potentials at the gate and drain terminals of M4 from that of the signal source and that of the load The signal source and load impedance are not shown Cascade of common source amplifier with source follower amplifier schematic with dc blocking capacitors Ce Cc and C 3 The signal source and its impedance are NOLS ROWN naa a e euh E M EDD EM ws Snes EMI oa 13 HSpice netlist of the cascade of common source and source follower amplifiers in PIQUIEC 6 9 Pr 15 Gain variation of the common source source follower amplifier cascade in Figure 6 6 due to variation in the load resistor Ry cece cee
4. Kk KC Kk Ko KC KC CK Kk KK Kk KK KK kKXkk x xxx x analysis section OkCACKC KOC CK Ck Ck o CK CK CK SK SK KK MK KA Kx KG KG BG XB XB x8 Xx X X X Kk Kk Kk o S S S KK Kk Kk KR X AK X X kk dc vdrain 0 10 0 0 01 sweep vgate poi 3 2V 4V 6V END Figure 6 12 HSpice netlist for obtaining l V characteristic of an n channel MOSFET 2N7000 B Madhavan Page 17 of 22 EE348L Spring 2005 Vcos7 6V Figure 6 13 ip vps characteristics of MOSFET x1 in Figure 6 12 for gate to source voltages of 8 6 and 4 volts 6 6 Conclusion The MOS canonic cells were presented in laboratory experiment 5 These cells are the fundamental building blocks of analog integrated circuit design This lab focused on using the canonic cells in combination to overcome their inherent limitations when used as a single cell Thus when doing circuit analysis one may always break down a circuit topology into the canonic cells in order to obtain insight into the design of a circuit An advanced understanding of these basic building blocks will allow a circuit designer to effectively use canonic cells to overcome their individual limitations and satisfy the largest possible subset of circuit design specifications 6 7 MOSFET Spice model for PMOS transistor BS250P Note that the spice model for the discrete p channel MOSFET used in this laboratory experiment BS250P utilizes a subcircuit definition which includes a first order PMOS model deck SUBCKT BS250P drain
5. Ko KK CK KK CK KK KK KK KXkk k specify nominal temperature of circuit in degrees C KKEKKKKKKKKKKKKKKK SK SKK SK M MK KG KG KG KR KK KG KC KC KC KK KK S S S S S KK KK KG Kx KR AK X XXX TEMP 27 OKCk Kok CK Ck KC KC KC Ck Kk KC KC Ck k KC Kk Kok Ko Kk Kk Kk K KC KC CK Kk Ko Kk CK Kk KK KC KK KC KC KK KC KC KC Kk Ko Kk kk Xk k X AAAS analysis section kk CK KC KC KC KC Ck ck CK CK CK CK SK SK SKK MK Kx KG G8 KG BG XB XxB XB X MA M X X Ko Kk Kk S S S Sk KK Kk Kk Kk X X AK koX kk ac dec 100 1 1G sweep loadres poi 5 100 1K 10K 100K 1X OKCk Kok CK Ck K KC KC Ck Kk KC KC Ck k KC KC Kok Ko Kk Kk Kk K KC KK Kk KK KC Kk KK KC KK KC CK KK KK KC Kk KK Kk KA kk models section AKCkCck ok ck Kk ok ko ok ck ck ok ok ck ok kokKokokokKokkKkxKkKKkKKKkKK kX kk kxkkkkkkkkkk kkkkk k k k amp xk this Model is from supertex com MODEL nmos 2N7000 NMOS LEVEL 3 RS 0 205 NSUB 1 0E15 DELTA 0 1 KAPPA 0 0506 TPG 1 CGDO 3 1716E 9 RD 0 239 VTO 1 000 VMAX 1 0E7 ETA 0 0223089 NES 6 6E10 TOX 1 0 amp 8 7 LD 1 698E 9 UO 862 425 XJ 6 46606E 7 IHETA 1 0E 5 CUOO0 9 095 9 END Figure 6 10 HSpice netlist of the cascade of common source and source follower amplifiers in Figure 6 9 Table 6 3 Relationship between R and A Common Source Common Source Common Source IA dB calculated A dB simulated Source Follower A dB simulated 100 20 32 1000 16 99 17 21 22 61 10000 22 75 22 24 22 88 100000 24 15 22 905 B
6. eececcececcececeececeeaecesaeceeaeeeeaeans 16 HSpice netlist for obtaining l V characteristic of an n channel MOSFET 2N7000 17 ip Vps Characteristics of MOSFET x1 in Figure 6 12 for gate to source voltages of 8 55 dna sd VOllS RS RR Se re anu Ed 18 Pin diagram of the BS250P Courtesy of Zetex seesesseseseeeeeerne 19 Cascade of common source amplifier with source follower amplifier schematic with dc blocking capacitors C and C 3 The signal source and its impedance are not STOW Nes cesar ert rant dett Eee iste tl de IL EMIL UP dee 20 B Madhavan 4 of 22 EE348L Spring 2005 6 Experiment Z6 MOSFETs Continued 6 1 Introduction Laboratory experiment 5 introduced the MOSFET canonic cells used in MOSFET amplifier design The ac small signal model was presented for each canonic cell and was used to discuss its performance What the previous lab didn t clearly present are the limitations of the canonic cells These limitations are one reason why circuits don t comprise of just a single stage that incorporates a single canonic cell An integrated circuit amplifier doesn t consist on just one common source amplifier To be sure a common source canonic cell s may be used in the amplifier topology but other elements and canonic cells are also used to address the performance limitations of the amplifier Another example is the voltage buffer A voltage buffer in an integrated circuit design doesn t consist of a sin
7. effectively slow the circuit down This could also potentially render the amplifier unstable if the dominate pole criteria is violated Bipolar transistors have a much larger gm associated with them which increases the Miller Effect when doing IC design with BJTs Vu M 3 M 2 M M Re I ref I DQ Figure 6 5 Cascode current mirror It was stated above that one of the main benefits of the cascode was to increase the output resistance of the common source amplifier thus increasing the gain This modification was successful because the assumption of very large drain source of the traditional common source resistance is no longer valid when dealing with small geometry devices In Figure 6 4 the load is symbolized by an effective resistance Rer but it is assumed that this effective resistance would B Madhavan 8 of 22 EE348L Spring 2005 be replaced by some sort of active circuitry such as a current mirror as shown in Figure 6 3 Now if the assumption of large drain to source resistance is not valid for the traditional common source then it may not be valid for the devices in the current mirror either Figure 6 5 shows how to increase the output resistance by applying the cascode configuration to the current mirror The output resistance is derived by replacing all the transistors with their ac small signal model followed by a small signal analysis at the output This is left as a pre lab exercise See page 649 of the textbook Microelect
8. 5 dB RL 10K gain 22 24 dB R 71K gain 17 21 dB Figure 6 7 Gain variation of the common source amplifier in Figure 6 6 due to variation in the R In order to reduce the impact of varying load resistance on the small signal gain of the common source amplifier in Figure 6 6 we need to insert a buffer stage between the drain of MOSFET M and the load resistance R The output impedance of the buffer needs to be low so that the variation in R does not affect the output impedance of the buffer Since the output of the common source amplifier in Figure 6 6 is a voltage signal the buffer stage is a voltage in B Madhavan 10 of 22 EE348L Spring 2005 voltage out stage with high input impedance and low output impedance The canonic cell that has these characteristics is the source follower amplifier whose output impedance is approximately 1 g but suffers from a gain that is at best close to 1 but always less than 1 A schematic of a source follower common drain amplifier is shown in Figure 6 8 Note that the source and bulk terminals of M are tied together which is typical of most discrete MOSFET devices unless specified otherwise M is a discrete n channel MOSFET device such as the 2N7000 used in this lab experiment resistor connected between the power supply Vaa and the drain terminal of Mz R55 and R establish a dc bias voltage Veo at the gate terminal of M2 Vp is the dc bias voltage at the drain term
9. K S SK KK MK Kx KG KG BG XB XB XB Xx XA M X X Ko Kk S S S Sk S Kk KKK KR AK AK X kk see page 8 63 and 8 66 of HSpice user manual probe dc idrain par id m1 B Madhavan 14 of 22 EE348L Spring 2005 probe de cocgd par SIRIM probe dc cgs par 1x20 m17 probe dc cgtotal coper oueeiuml probe dc vthreshold par lv9 ml probe cc vdsat par lv10 ml probe dc gm par lx7 ml probe dc gmbs par lx9 ml probe dc gds par lx8 ml probe dc rds par 1 1x8 m1 probe dc gain par 20 10g10 v drain v gate probe dc gain2 par 20 10g10 v drain v gatec probe dc vgs par v gate v source probe dc vgsov par v gate v source l1v9 m1 probe dc vds par v drain v source probe ac idrain par irzdiml probe ac cgd pax t lxi19 mly probe ac cgs part LxZ0 tnd probe ac uogtotal epar Ixo mL probe ac vthreshold par lv9 ml probe ac vdsat par lvliOtnl probe ac gm par lx7 ml probe ac gmbs par bombo probe ac gds par lx8 m1 sprobe ac rds par 1 1x8 m1 probe ac gain par 20 10g10 v drain v gatec probe ac gain2 par 20 10g10 v drainc v gatec probe ac vgs par v gate v source probe ac vgsov par v gate v source lv9 m1 probe ac vds par v drain v source OKCk KO CK CK Ck Ko KC Ck ok Kk KC KC Ck ok Kok Kk Kok Kk ok K Ko Kk Kk Kk Ko Kk Kk Ko Kk Kok
10. Laboratory Experiment 6 EE348L Spring 2005 B Madhavan Spring 2005 B Madhavan Page 1 of 22 EE348L Spring 2005 B Madhavan 2 of 22 EE348L Spring 2005 Table of Contents 6 Experiment 6 MOSFETs Continued eere een 5 o MEME VOC eis T E IUE Ur 5 6 2 Common source Amplifier elsseeesssessssessseeee eene nnne nennen nennen nnns 5 63 CaSCOdS COMMUN NON t Dp 7 6 4 A systematic procedure for biasing a source follower amplifier 9 6 4 1 Verification of the systematic procedure for biasing a common source amplifier 14 6 5 HSpice simulation of discrete p channel MOSFET BS250P eeeeeeeeesss 16 6 6 GU QeiP ior E a a ea daioueluant 18 6 7 MOSFET Spice model for PMOS transistor BS250P ccc ccccceeececeeeeeceeeeeeeeeeseeeeees 18 0 9 Revision HISLODy io oodd HE mats ee te dme dM ad mM dM PE bU E MT Ed UTE 19 B 9 JSCISIell COS onec epiac Me DI Mq MEI Eu dir 19 6 10 ProdaD EXGrCI SES P M 19 6 11 LADE KON GI SOS coena pass Fiov Esta au A seeds Qu utu dale E 22 6 12 General Report Format Guidelines ni cete et ao Doce ec tuia oed uudus 22 B Madhavan Page 3 of 22 EE348L Spring 2005 Table of Figures Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 Figure 6 8 Figure 6 9 Figure 6 10 Figure 6 11 Figure 6 12
11. Madhavan Page 15 of 22 EE348L Spring 2005 1000000 23 7 24 25 22 908 The simulation results of the frequency response of the cascade of common source and source follower amplifiers in Figure 6 9 using the netlist in Figure 6 10 are summarized in Table 6 3 and Figure 6 11 for values of RL varying from 100 Q to 1E6 Q The results in Table 6 3 compare the mid band gain of the common source and the cascaded common source source follower amplifier The variation in gain due to variation in R is reduced from 22 6 dB to less than 2 6 dB R 710K gain 22 88 dB P uds R 1K gain 22 61 dB R 100 gain 20 32 dB i 1D 100 1k 10k 100k ix Figure 6 11 Gain variation of the common source source follower amplifier cascade in Figure 6 6 due to variation in the load resistor R_ 6 5 HSpice simulation of discrete p channel MOSFET BS250P Figure 6 12 is an example of a netlist that can be used to plot the ip Vps characteristics of the MOSFET BS250P specified by the subcircuit named BS250P in Figure 6 12 We use a subcircuit definition because we do not have a properly characterized model deck for the BS250P from the manufacturer that accounts for all aspects of its behavior The drain to source voltage Vos is swept from OV through 10V in steps of 0 01V at gate to source voltages Vas of 2 V 10 V 8V 4V 10V 6V and 6V 10V 4V The HSpice simulation results are shown in Figure 6 13 Refer to Laboratory experiment 3
12. and maximum values of the particular discrete MOSFET device that you are using Build the common source amplifier you designed in pre lab question 1 Verify your results for load resistances of 1 KQ 10K and100 KQ Does your gain remain the same for sine wave inputs at 10 KHz with peak to peak values of 20mV 100mV 200mV and 400mV Tabulate the output peak to peak values obtained Calculate the gain observed from your transient signal measurement as the ratio of the output peak to peak voltage to the input peak to peak voltage Do your results agree with you HSpice results Why or why not Using the results from pre lab question 2 build the amplifier in Figure 6 15 Verify your results for load resistances of 1 KQ 10KO and100 KQ Does your gain remain the same for sine wave inputs at 10 KHz with peak to peak values of 20mV 100mV 200mV and 400mV Tabulate the output peak to peak values obtained Calculate the gain observed from your transient signal measurement as the ratio of the output peak to peak voltage to the input peak to peak voltage Do your results agree with you HSpice results Why or why not Bonus Question Build the circuit from pre lab question 7 Note that your job is to correctly bias the circuit for maximum signal swing while making sure all devices are in saturation Measure the maximum signal swing you can achieve by adjusting the amplitude of a 5 KHz sine wave Do these results agree with what you derived in the pre
13. c small signal model Both of the above are left as pre lab exercises The cascode configuration has a couple of advantages over the traditional common source amplifier As you should find out in the pre lab the output resistance Ro in Figure 6 4 is increased especially for short channel devices with gate length lt 14m Consequently the gain of the overall circuit is increased Another benefit is achieved from a speed perspective The common gate stage reduces the Miller multiplication of the gate to drain capacitance Ca of transistor Mi seen by the source Vs The Miller Effect occurs when a capacitor is connected between two nodes one of which experiences inverting gain with respect to the other This effectively increases the effective capacitance seen at the input by a factor of one plus the gain In a traditional common source configuration such as Figure 6 1 there isn t an explicit capacitor between the gate and drain terminals of the MOSFET M The MOSFET small signal model has a parasitic gate drain capacitance Cg associated with it Also from laboratory experiment 5 it is known that a common source amplifier has a transconductance gain of Jm between the gate and drain The effective capacitance seen by the input to the common source amplifier Figure 6 1 is Cy 7 C t g R 6 3 where R is the effective load resistance at the drain Hence one can now see that the time constant associated with this node has increased and will
14. d MOSFET M for the traditional common source amplifier in Figure 6 1 6 Calculate the small signal output resistance of the cascode current mirror shown in Figure 6 5 taking into account the small signal MOSFET drain to source resistance fas How much larger is it compared to the traditional current mirror See pages 563 564 of the textbook Microelectronic Circuits by Sedra and Smith for basic current mirrors and page 649 for cascaded current mirrors Also see laboratory experiment 5 7 One drawback of using cascode topologies is that the maximum achievable signal swing is reduced Replace Reg in Figure 6 4 with the cascode current mirror in Figure 6 5 and derive an expression for maximum AC signal swing i e Vomax lt V lt Vomin that can be achieved It should be in terms of device DC biasing voltages i e Vg and Vas and guarantees that all devices operate in saturation What are the maximum and minimum voltages at the output that will allow all MOSFET devices to be in the saturation region B Madhavan Page 21 of 22 EE348L Spring 2005 6 11 Lab Exercises 1 2 3 use the model deck for 2N7000 in Figure 6 10 use the model deck for BS250P in Figure 6 12 Submit plots relevant to reach question in your lab report Use the supply voltage that you used in your pre lab HSpice simulations for this lab Take care that you look up the manufacturer s datasheet to determine the threshold voltage range minimum typical
15. eriment 5 biasing supplement design a common source amplifier Figure 6 8 in HSpice with source degeneration resistance which has the following specifications a Supply voltage of 10 V bonus points if you achieve specification with lower supply voltage between 5V and 8V b small signal gain gt 25 dB between O C and 125 C for an ac coupled load resistance R 2100 KQ in the frequency range of 1000 Hz to 1E5 Hz c small signal gain gt 20 dB at 27 C for R min 1 KQ in the frequency range of 1000 Hz to 1E5 Hz Your answer should indicate i how you arrived at the dc operating point of the common source amplifier ii how the component values were chosen iii Show that the calculated small signal gain is in good agreement with that obtained from your HSpice simulations iv As shown in Table 6 1 tabulate the variation in mid band frequency range of 1000 Hz to 1E5 Hz small signal gain due to variation in load resistance R for 100 Q9 1 KQ 10KQ 100 KO and 1E6 Q v Submit the results of a transient simulation with a 20mV peak to peak sinusoidal input at 10 KHz Does the gain inferred from the transient simulation agree with the gain obtained from the frequency response small signal simulation in HSpice Why or Why not 2 Modify your design in pre lab question 1 as shown in Figure 6 15 so that the variation in mid band small signal gain due to variation in load resistance R from 100 Q to 1E6 Q is no more than 5 dB
16. esults in Table 6 2 and separately chose Vps 3V to ensure that MOSFET M remains in saturation Vp 5 25V Since Vaa 10V as in the biasing supplement of laboratory experiment 5 Rp 5 25V 5 18mA 1013 5 Q The design point of the source follower amplifier is e Vs 2 25V e Voo 3 50 V e Vpo 5 25V e Ip 5 18 mA e Oma 29 42 mS e Vad 10V B Madhavan 12 of 22 EE348L Spring 2005 e Rss2 2 25V 5 18MA 434 4 Q e Rp2 525V 5 18mA 1013 5 Q We want to cascade the common source amplifier that we designed in the biasing supplement of laboratory experiment 5 with the source follower amplifier that we have just designed as shown in Figure 6 9 We note that the ac coupling capacitor C2 the biasing resistors Ry5 and Rp in Figure 6 9 can be removed if we directly connect the gate terminal of MOSFET M to the drain terminal of MOSFET M However the drain terminal of MOSFET M in the common source amplifier is at 3V and gate terminal of MOSFET M in the source follower amplifier is at 3 5V design point Vc 3 50V see above Figure 6 9 Cascade of common source amplifier with source follower amplifier schematic with dc blocking capacitors Cc Cc and C The signal source and its impedance are not shown Therefore we have two choices We can adjust the drain voltage of MOSFET M from 3 0V to 3 5V or change the gate voltage of MOSFET M from 3 5V to 3 0V Choice 1 Changing the drain voltage of MOSFET M fro
17. ewood Cliffs New Jersey 1990 Richard C Jaeger Introduction to Microelectronic Fabrication Addison Wesley Publishing Company Reading Massachusetts 1993 S M Sze Physics of Semiconductor Devices John Wiley amp Sons Inc New York 1981 Paul R Gray amp Robert G Meyer Analysis and Design of Analog Integrated Circuits John Wiley amp Sons Inc New York 1993 6 10 Pre lab Exercises Note e For HSpice simulations use the model deck for 2N7000 in Figure 6 10 and the model deck for BS250P in Figure 6 12 See HSpice guidelines in Laboratory Experiment 3 and Laboratory Experiment 5 Read Laboratory Experiment 5 biasing supplement carefully Submit plots relevant to each question in your lab report B Madhavan Page 19 of 22 EE348L Spring 2005 e Note The 2N7000 and BS250P are not small geometry devices so the approximation of large small signal drain to source resistance in the saturation region rg is normally valid e Device Specifications Caution Never exceed the device maximum limitations during design 2N7000 Idmax 200mA Vdsmax 60V Vth 0 8V BS250P Idmax 250mA Vdsmax 45V Vth 1V Vja Vu Rp Rp Ru Vp V M M Figure 6 15 Cascade of common source amplifier with source follower amplifier schematic with dc blocking capacitors C and C 3 The signal source and its impedance are not shown 1 Following the systematic procedure for biasing a common source amplifier outlined in laboratory exp
18. ficient from a layout area standpoint The gain of the common source canonic cell Figure 6 1 was increased by using the low frequency small signal resistance of a MOSFET current mirror as B Madhavan 6 of 22 EE348L Spring 2005 shown in Figure 6 3 which is much higher than the resistance that can be realized with a typical on chip passive resistor However this assumes that the drain to source or output resistance ras Of a MOSFET is very large As device geometries become smaller this assumption begins to fail This next section will deal with what is known as a cascode configuration which is a cascade of the common source and common gate canonic cells that increases the drain to source resistance of a MOSFET T V Figure 6 3 A common source with a current mirror load Bias circuitry is not shown 6 3 Cascode configuration Figure 6 4 Common source cascode Bias circuitry is not shown B Madhavan Page 7 of 22 EE348L Spring 2005 The cascode configuration is shown in Figure 6 4 Going back to laboratory experiment 5 one can see that this cascode configuration is nothing more than a common gate that has been stacked on top of the common source amplifier Since we have derived the small signal transfer function of each canonic cell we should be able to calculate the small signal transfer function of the overall amplifier by inspection The new output resistance should be calculated by replacing each transistor with its a
19. gate source M1 drain gatel source source MBS250 RG gate gatel 160 RL drain source 1 2E8 Cl gatel source 47E 12 C2 gatel drain l0E 12 Di drain source DBS250 MODEL MBS250 PMOS TVIO 354 193 RS 2 041 RD0 697 ISSIE 15 KP 0 217 TOBDeLUSE 1 PB 1 LAMBDA 1 2E 2 MODEL DBS250 D ISSZE IL5 RS 0 509 sENDS BS250P In order to use this device in an HSpice netlist the above subcircuit is defined before the start of the circuit description Then a subcircuit call is used to instantiate the BS250P in the HSPice netlist as shown below B Madhavan 18 of 22 EE348L Spring 2005 x1 drain gate source BS250P G S E Line TO92 Compatible Figure 6 14 Pin diagram of the BS250P Courtesy of Zetex 6 8 Revision History This laboratory experiment is a modified version of the laboratory experiment 7 MOSFET Dynamic circuitsll created by Jonathan Roderick 6 9 References 1 2 3 4 5 6 7 8 9 Bindu Madhavan Laboratory Experiment 5 biasing supplement EE348L Spring 2005 Avant HSpice User Manual Version 2001 4 December 2001 posted on EE348L class web site Avant HSpice Device Models Reference Manual Version 2001 4 December 2001 posted on EE348L class web site Bindu Madhavan EE348L Laboratory Experiment 3 Spring 2005 Adel Sedra and K C Smith Microelectronic Circuits fifth edition Oxford University Press Ben G Streetman Solid State Electronic Devices Prentice Hall Inc Engl
20. gle common drain source follower canonic cel As you probably discovered in the pervious lab the gain of a common drain source follower amplifier is less than unity and depending on the MOS technology used it can be considerably less than one This lab will present ways to combine the canonic cells in order to overcome certain inherent limitations of a single cell The design strategies and topologies presented here are not comprehensive of all the possible solutions known to overcome the limitations of MOSFET amplifiers However they should give you insight into how to approach practical problems in MOSFET analog integrated circuit design 62 Common source Amplifier A common occurrence a circuit designer faces is get more gain out of a common source amplifier One reason is the relatively low transconductance associated with a MOSFET as compared to a bipolar transistor A common source amplifier is shown below in Figure 6 1 Note that the circuitry necessary to establish the proper operating point of the MOSFET M is not shown Only the ac circuit schematic is shown Figure 6 ty Schematic diagram of a common source amplifier Bias circuitry is not shown From the previous lab it was shown that a common source amplifier has gain y A o R 6 1 Cy TE 6 1 This is assuming that the drain to source resistance fas of the MOSFET is much greater than R If it isn t than the net effective resistance is the parallel combinat
21. igure 6 2 with a PMOS version of the current mirror that was presented in laboratory experiment 5 as shown below in Figure 6 3 Note It can be seen in Figure 6 3 that the PMOS current mirror uses a passive resistor R4 to establish the reference current le needed to bias the common source amplifier As in Figure 6 1 this resistance is usually realized with a MOSFET Normally another NMOS transistor that is either diode connected or biased with a dc voltage is used to present the required amount of resistance For the purposes of this explanation it will be left as an effective resistance Re Figure 6 3 doesn t show the bias circuitry that establishes a dc bias voltage at the gate of MOSFET M It is assumed that the input signal V has the appropriate amount of DC offset to ensure that MOSFET M is biased in the saturation region Note that the current mirror formed by PMOS transistors Mz and M are correctly biased by appropriate choice of current l e resistor Reg and device sizes if applicable of M and Ms One may recognize that the small signal output resistance of the topology feature in Figure 6 3 Rout is nothing more than the parallel combination of the output resistance of MOSFET M and that of MOSFET M4 This derivation is left as a pre lab exercise As stated before a passive on chip resistor consumes a great deal of area and its resistance is proportional to that area Thus high value on chip passive resistors are extremely inef
22. inal of M2 Va not shown in the figure is the dc bias voltage at the source terminal of Mz The function of resistor Rp2 is to limit the voltage at the drain of MOSFET M so that it does not enter into breakdown For low values of Vaa Rp2 can be eliminated from the circuit schematic The ac small signal gain of the source follower amplifier in Figure 6 8 is given by Gales 6 5 l g R m2 SS2 where gm2 is the transconductance of MOSFET M which is biased in saturation Figure 6 8 Source follower amplifier schematic with dc blocking capacitors C and C isolating the dc potentials at the gate and drain terminals of M from that of the signal source and that of the load The signal source and load impedance are not shown The dc drain current lp of MOSFET Moz which is assumed to be in the saturation region of operation is 5 Ves i V j 6 6 a A 6 7 The expression for the transconductance gm2 equation 5 10 of MOSFET M is given by Em K Vos i V 2KI 6 8 where Vesz Ip2 and Vin are the dc gate to source potential the dc drain current and the threshold voltage of MOSFET M in Figure 6 8 To bias MOSFET M in Figure 6 8 in the saturation region we make the following design choices where Vp is the dc bias voltage at the drain terminal of M2 Vs is the dc bias voltage at the source terminal of Mz and Vc is the dc bias voltage at the gate terminal of Mo 1 Ves2 Vin is chosen to be 0 25 V B
23. ion of the resistor R and the drain source resistance of the device The transconductance gm of a MOSFET is defined as B Madhavan Page 5 of 22 EE348L Spring 2005 b p Ur Jr 6 2 From these equations it can be seen that the only gain variables that a circuit designer has control over are the load resistance R the drain bias current Ibo and the gate aspect ratio or size of the transistor W L In integrated circuit design a resistor is not usually a passive element as depicted in Figure 6 1 Active devices usually realize resistances Large on chip passive resistance takes up much more area than a resistance realized by using an active device In the case of the common source amplifier shown in Figure 6 1 a PMOS device would be biased in saturation with a dc bias voltage at its gate terminal specified by the designer to achieve the desired resistance Ideally you would like that PMOS to act like a dc current source shown in Figure 6 2 At low frequency this would maximize the small signal gain due to the very large ideally infinite resistance associated with a dc current source Figure 6 2 An Ideal Common source Configuration Bias circuitry is not shown We can attempt to maximize the amount of gain that can be realistically obtained from the circuit topology in Figure 6 2 by making the small signal resistance as large as possible In most MOSFET integrated circuits this is achieved by replacing the DC current source in F
24. lab Why or why not 6 12 General Report Format Guidelines 1 Data Present all data taken during the lab It should be organized and easy to read 2 Discussion Answer all the questions in the lab For each laboratory exercise make sure that you discuss the significance of the results you obtained How do they help your investigation Explain the meaning the numbers alone aren t good enough 3 Conclusion Wrap up the report by giving some comments on the lab Do the results clearly agree with what the lab was trying to teach Did you have any problems Suggestions B Madhavan 22 of 22 EE348L Spring 2005
25. m 3 0V to 3 5V Changing the drain voltage of MOSFET M from 3 0V to 3 5V requires us to change the value of Rp from 1323 Q to 10V 3 5V 5 29mA 1229 Q Assuming that this small change 0 5V in drain voltage does not change lp Gm and ras of MOSFET Mi the ac small signal gain of the common source amplifier changes from 15 31 Table 6 1 assuming that RL gt 1E6 Q and that ras 9 97 KQ to 14 35 assuming that RL gt 1E6 and that ry 9 97 KQ From Table 6 2 the gain of the source follower amplifier A 0 95 for our design choice of Vs 2 25V The overall gain of the cascade of common source followed by the source follower amplifier is the product of the individual gains 14 35 x 0 95 13 633 22 69dB Choice 2 Changing the gate voltage of MOSFET M from 3 5V to 3 0V Changing the gate voltage of MOSFET M from 3 5V to 3 0V requires that we change the design value of Vso 2 25V to Vs 1 75V to preserve the gate to source overdrive Ves2 Vin 3V 1 75V 1V 0 25V From Table 6 2 the gain of the source follower amplifier A 0 9333 for our design choice of Vs 1 75V The overall gain of the cascade of common source followed by the source follower amplifier is the product of the individual gains 15 31 x 0 933 14 29 23 1dB Very Important Point Since the source and bulk terminals of MOSFET M which is a discrete device are tied together and at the same potential there is no change in the drain cur
26. nterest when ac coupling capacitor C is a short is given by Rp ras Rt RL does not affect the gain of the amplifier in Figure 6 6 as long as it is larger than Rp ras However as R becomes comparable or smaller than Rp ras the ac small signal gain of the amplifier in Figure 6 6 begins to decrease The ac small signal gain is given by A Jet Ira E 6 4 Dg In the laboratory experiment 5 biasing supplement the design values for the common source amplifier in Figure 6 6 with a small signal gain close to 20 were found to be 1 Vp 3V B Madhavan Page 9 of 22 EE348L Spring 2005 2 Ve 1 475V 3 Vg 0 225V 4 lp 2 5 29 mA 9 Tas 9 97 KQ 6 gm 7 29 72 mS T Reg 42 53 Q 8 Rp 1323 Q The revised gain for different values of R are shown in the table below which shows excellent agreement between calculated and simulated values The influence of varying load resistance R on the frequency response of the common source amplifier in Figure 6 6 can be seen in Figure 6 7 which shows the HSpice simulation of the common source amplifier in Figure 6 6 with the design values and MOSFET operating piont developed in the laboratory experiment 5 biasing supplement Table 6 1 Relationship between R and A Ri Rollrasi Ri Axl IA dB A dB calculated simulated 92 114 1000 538 75 7 07 16 99 10000 1045 85 22 24 100000 1154 52 15 16 236 24 15 1000000 1166 63 15 31 24 25 R 7100K gain 24 1
27. o S S Sk Sk Kk Kk Kk Kk Kk X X kk kk xl drain date source BSZ50P OKCk Kok CK ok K KC Ck ok Kk KC KC ok ok Kok Kok Ko KC Kk Ck K KC KC Kk Kk Ko Kk Kk Ko Kk KC CK KK KC KK KC KC KC Kk KK kk Ak k X sources section AKCkCck ok ck Kk ok ko ok ok ck ok ok ck ok okokKokokokKokkKkxkKKkKKKkKK KXkk kxkkkkkkk kkk kkkkk k k k k vdrain drain vss Sad V VSOUurce Source vss Tu ME vgate gate VSS 4 0V v2 VSS O DW OKCk Kok CK ok K KC KC Ck Kk KC KC Kk ok Kok Kk k Kok kk K Ko KK Kk Ko Kk Kk Ko Kk KK KK KK KK KC KC Kk Ko KK KA kk analysis section KKEKKKKKKKKKKKKKKKK SK SK KK M MK KG KG BG XB XB XB Xx X X Kk ck ck ck c S S S KK KK KK X KA KR X XXX see page 8 63 and 8 66 of HSpice user manual probe dco idrain par rax mL probe dc cgd paw LRTI Sam probe dc cgs cpar tt ebx20 xlzmby t probe dc ogtotal par l1x18 xl ml probe dc vthreshold par lv9 xl ml probe dco wvdsat oar clvr0 sxl mlyt probe dc gm par lx7 xl ml probe dc gmbs par ix9 xliml probe dc gds par lx8 xl ml probe de rds par 1 1x8 xl m1 OKCk Kok KC Ck K KC KC Ck Kk KC KC Ck k KC Kk Kok Ko Kk Kk Kk K Ko KC K Kk KK KK KK KC CK KK CK KK KK KC Kk Ko K Kk kA kk specify nominal temperature of circuit in degrees OkCACK KC KOC Ck Kk C Ck CK CK CK SK SKK M MK KG KG KG KG KG KG KK KC KK KK S S S SK SK KK KK KG X KR X X XX kk TEMP 27 OKCk KO KC CK Ck K KC KC Ck Kk KC KC ok k KC KC Kk ok Kok Kk ok Kk Ko Kk Kk Kk Ko Kk Kk Ko
28. or the HSpice user manual version 2001 4 December 2001 for help on plotting using mwaves awaves PMOSFET I V characteristic for BSZ50P This file has been used to generated figures for labo Written Mar 4 2005 for EE348L by Bindu Madhavan ckCKCk KC KC KC Ck K KC Kk kk Kok Kk ok Kok Kok Ko Kk kk Kk Kok CK Kk Ko Kk Kk Kk Ko Ko Kk Kk Ko KK KK Ko Kk Kk KK Kk kKkk k options section ACKCkC Ck Kk Kk ok KC KC Kk ok Kk KC Kk Ck Kk Kok Kok Kok kk K Kok CK K KK KK KK KK KK KK KK KK KK KK KK KK KR X X X options post 1 brief nomod alt999 accurate acct 1 opts options unwrap dccap 1 numdgt 9 param capop 4 CACKCk KC Ck CK ok K KC Kk ok Kk KC kk Kk KC Kk Kk Kk Kok Kk Kk Ko KC Kk Kk Ko KK KK KK KK KK KK KK KK KK KK KK xk X subcircuit definition X K ck K Kk Kk k k k kk kk kk kk kk kk kk kk kk kk KKK KK KK KKK KK KK KK kk kk kk kk B Madhavan 16 of 22 EE348L Spring 2005 SUBCKT BS250P drain gate source M1 drain gatel source source MBS250 RG gate gatel 160 RL drain source 1 2E8 Cl gatel source 47E 12 C2 gatel drain LI0E 12 Di drain source DBS250 MODEL MBS250 PMOS TWIOSCO L199 BoeS2 041I RDS0 0697 IS amp SIE I5 KRP0 2477 TOCBDSeLOSE LZ PB 1 LAMBDA 1 2E 2 MODELJDBSZS0 D TXSSZ2E IS RSS0 3509 ENDS BSZ50P OKCk Kok KC Ck K KC KC ok Kk KC KC kk Kok Kok Ko Kk kk K Ko Kk Ck Kk Ko Kk Kk Ko KK Kk Ko KK KK KK KK KK Kk KAkk k sono TPC LT descripto ACC KOC CK CK Ck KK CK CK SK SK SK KK MK KG Kx G B x x XB M x8 Xx MA M X X Kk K
29. rent and transconductance of MOSFET M when the gate voltage is changed from 3 5V to 3 0V and the gate to source B Madhavan Page 13 of 22 EE348L Spring 2005 voltage Vaso remains unchanged Therefore the output impedance of the source follower amplifier remains unchanged in this particular case This is not the case when the bulk terminal of the n channel MOSFET namely M and M are tied to the lowest potential in the circuit as one might be required to do if this design were to be fabricated on an integrated circuit 6 4 4 Verification of the systematic procedure for biasing a common source amplifier Very Important Point See pages 4 18 to 4 20 of the HSpice user manual version 2001 4 December 2001 page 8 14 for the general MOSFET model statement pages 8 21 to 8 26 for the MOSFET equivalent circuits 8 59 to 8 101 for MOSFET capacitance models and pages 9 20 to 9 33 for the Level 3 MOSFET model deck in the HSpice Device Models Reference Manual version 2001 4 December 2001 AC coupled Common Source amplifier with Source Degeneration Resistor This file has been used for cs source follower amplifier Written March 3 2005 for EE348L by Bindu Madhavan OKCk Kok Ck Ck KC KC KC Ck Kk KC KC Ck ok KC KC Kok Ko Kk Kk Kk K KK KK KK KK KK KU KK KU KK KK KK KG KK MK KG KA KK XX Doe OPLOG GOC CLON OkCkCAKC KOC CK Ck CK C CK CK SK SK S S KK MK KA KA KG G8 BG B XB XB x8 Xx XA M X X Kk Kk o S S Sk KK Kk Kk KR KR X AK X kk options pos
30. ronic Circuits by Sedra and Smith 6 4 Asystematic procedure for biasing a source follower amplifier In the laboratory experiment 5 biasing supplement we developed a systematic biasing procedure for a common source amplifier with a source degeneration resistor After making some design choices we related the ac small signal gain of the amplifier to the dc bias voltages of the amplifier We then used HSpice simulation to determine the drain current lp and transconductance gm of the MOSFET corresponding to the dc bias point for a desired ac small signal gain The simulated ac small signal gain of the complete amplifier and the gain observed from transient simulation of the amplifier were found to be in excellent agreement with the initial calculations In this section we repeat the procedure for a source follower common drain amplifier Before doing this we motivate the need for a source follower amplifier by looking at the limitation of the common source amplifier whose schematic is shown in Figure 6 6 We note that the discrete n channel MOSFET that we use is 2N7000 whose datasheet may be found at http www supertex com Vu Rp Ry M de C R t Rp Rss vt Vin t Figure 6 6 Common source amplifier with variable load impedance R The signal source is not shown If the small signal drain to source resistance of MOSFET M is denoted by ras the effective load impedance seen by MOSFET M in the frequency range of i
31. t 1 brief nomod alt999 accurate acct 1 opts options unwrap dccap 1 param capop 4 KKKKKKKKKKKKKKKKKKK KK M MK MK KG KG KG KG KG KK KC KK KK KK S S S S S KK KG KG KR KR AK AK Kk kk AN EI IGI eS Crip tO OkCkCKC KOC CK CK CK CK CK CK CK SK SKK SK MK KA KG KG B x XB XB x8 Xx X X X ko ck ck ck Kk o S Sk Kk Kk Kk Kk AK ko k kk rbl vdd gate 8 525K rb2 gate vss 1 475K ml drain gate source source nmos 2N7000 W 0 8E 2 L 2 5E 6 rs source vss shrocres 5500 pd wdd drair tdgrarnres 51500 ccl gatec gate 10uF source follower amplifier dc coupled raz vdd xudurarinz Lola m2 drain2 drain source2 source2 nmos 2N7000 W 0 8E 2 L 2 5E 6 f52 SOULTCEZ vss 435 CC2 Source2 drainc 10uF ri drainc vss loadres KK CK K K Ko k kk Kk Kk kk kk kk kk kk kk Kk kk Kk kk kk kk kk kk kk kk kk kk kk kk kk Uo parsnmeters Securon OAkCkCK KOC CK Ck Kk o CK CK CK SK SKK KK M KA KG KG G8 KG G8 BG XB XB Xx X KC Kk Kk KK S S S SK S A KK KK KK KR X X XX kk param drainres 1229 param srcres 42 53 param loadres 100K OKCk Kok CK Ck KC KC KC Ck Kk KC KC Ck k KC Kk Kk Ko Kk Kk Kk K KC KK Kk KK KK KK KC KK KC CK KK KK CK CK KK Kk KA kk sources section AKCkCck ok Kk Kk ok ko ok ok ko ok kk ok kokKokokokKokokKkxkKKkKKkK KkK kX kk kxkk kkkkkkkk kkk kk k k k amp xk vl vdd vss 10V vgate gatec vss ac 1 sin 0V 10mV 100k V2 VSS 0 OV KEKKKKKKKKKKKRKKKKRKKKKKRKKKKRKKKKRKRKKKRKKKKKRKKKKRKKKKEKKKKKKK wU analysis Sect Lon OkCACK KOC KC CK Ck Ck c CK CK CK S
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