Home

User Manual - Sundance Multiprocessor Technology Ltd.

1. Setting Bit 0 Description 0 0 Normal Operation 1 1 Keep VGAO in Power Down mode Gain settings preserved Setting Bit 1 Description 0 0 Normal Operation 1 1 Keep VGA1 in Power Down mode Gain settings preserved Setting Bit 2 Description 0 0 Normal Operation 1 1 Keep VGA2 in Power Down mode Gain settings preserved Setting Bit 3 Description 0 0 Normal Operation 1 1 Keep VGA3 in Power Down mode Gain settings preserved Setting Bit 4 Description 0 0 Normal Operation 1 1 Keep DDSO in Power Down mode Setting Bit5 Description 0 0 Normal Operation 1 1 Keep DDS1 in Power Down mode Setting Bit8 Description 0 0 Normal Operation 1 1 VGAO gets updated with current register settings Setting Bit 9 Description 0 0 Normal Operation 1 1 VGA1 gets updated with current register settings Setting Bit 10 Description 0 0 Normal Operation 1 1 VGA 2 gets updated with current register settings Setting Bit 11 Description 0 0 Normal Operation 1 1 VGAS3 gets updated with current register settings Setting Bit 2 Description 0 0 Normal Operation 1 1 DDSO gets updated with current register settings Setting Bit 3 Description 0 0 Normal Operation 1 1 DDSI gets updated with current register settings Setting Bit 14 Description 0 0 Normal Operation 1 1 Forces DDSO to reload its registers Self clear To be used in conjunction of bit 15 to synchronise both DDS chips Set
2. Unit Module Description Multi output DDS based SLB Mezzanine Unit Module Number SMT399 160 Document Issue Number 3 Issue Date 24 05 2007 Original Author PSR User Manual for SMT399 160 Sundance Multiprocessor Technology Ltd Chiltern House Waterside Chesham Bucks HP5 1PS This document is the property of Sundance and may not be copied nor communicated to a third party without prior written permission Sundance Multiprocessor Technology Limited 2006 Certificate Number FM 55022 Revision History ou AAA We kou Original Document 08 01 2007 Power consumption added 12 01 2007 Modification MMBX connectors fitted 24 05 2007 Table of Contents 1 Intreducioi ian 6 2 Related Documents sesse sede Se SNAKE SES AGS GN SG Ge Ge GN ed Ne Ge SON RENS 7 3 Examples of application esse se gee ee ee Re ve kn ka dee ke ak ee ka kin kn pk a a AAA NA W 8 4 Functional Description sessies es ESE D ES anna 9 41 Block Dier eN et etik GEN ee SGA EO OGE Ge ee Pe Gee Ro ek ma Reve kek ki ew 9 4 2 ModiebDestiphoi snai 9 4 3 SMT399 160 characteristics wi ri iaia 10 44 Power Supply structure sccscscsscsnscsscssscsssescseecesecessccessecseecescesstesseecseecesteessreess 10 45 Cibona 11 4 6 Output Variable Gain AMPIE 11 4 7 Daughter sub module interface iii 11 A Caienna 11 4 9 Duane MOAB ek a kap kk a ok kak EE an a kk e e pk a kek an
3. Word 1 0x14 DDSO Register E 0xE RAM Segment Control Read back FPGA Register DDSO Register E OxE Word 1 0x15 DDSO Register F OxF RAM Segment Control Read back FPGA Register DDSO Register F OxF Word 1 0x16 DDSO Register 10 0x10 RAM Segment Control Read back FPGA Register DDSO Register 10 Word 2 0x10 0x17 DDSO Register 11 0x11 RAM Segment Control Read back FPGA Register DDSO Register 11 0x11 Word 2 0x18 DDSO Register 12 0x12 RAM Segment Control Read back FPGA Register DDSO Register 12 0x12 Word 2 0x19 DDSO Register 13 0x13 RAM Segment Control Read back FPGA Register DDSO Register 13 0x13 Word 3 Ox1A DDSO Register 14 Ox1A RAM Segment Control Read back FPGA Register DDSO Register 14 0x14 Word 3 0x1B DDSO Register 15 0x1B RAM Segment Control Read back FPGA Register DDSO Register 15 0x15 Word 3 Ox1C DDSO Register 16 Ox1C Falling Delta Frequency Read back FPGA Register DDSO Falling Delta Tuning Word Frequency Tuning Word 0x1D DDSO Register 17 Ox1D Falling Delta Frequency Read back FPGA Register DDSO Falling Delta Tuning Word Frequency Tuning Word Ox1E DDSO Register 18 0x1E Falling Sweep Ramp rate Read back FPGA Register DDSO Falling Sweep Word Ramp rate Word Ox1F DDSO Register 19 0x1F Rising Delta Frequency Read back FPGA Register DDSO Rising Delta Tuning Word Freguency Tuning Word
4. Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0 0 Frequency Tuning Word 0 23 16 Default 00000000 1 Frequency Tuning Word 0 31 24 Default 00000000 DDSO Register 0xC Frequency Tuning Word 0 Setting Frequency Tuning Description Word The frequency tuning word is a 32 bit register that controls the rate of accumulation in the phase accumulator of the DDS core 5 4 14 DDSO Register 0xD Phase Offset Word For more details refer to AD9954 datasheet DDSO Register 0xD Phase Offset Word Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Phase Offset Word 7 0 Default 00000000 1 Not Used Phase Offset Word 13 8 Default 00 000000 DDSO Register 0xD Phase Offset Word Setting Phase Offset Description Word The phase offset word is a 14 bit register that stores a phase offset value 5 4 15 DDSO Register OxE Frequency Tuning Word 1 For more details refer to AD9954 datasheet DDSO Register OxE Frequency Tuning Word 1 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BitO 0 Frequency Tuning Word 1 7 0 Default 00000000 User Manual SMT399 160 Page 26 of 39 Last Edited 24 05 2007 17 12 00 1 Frequency Tuning Word 1 15 8 Default 00000000 DDSO Register OxE Frequency Tuning Word 1 Setting Frequency
5. 1 RAM Segment 1 Address Ramp Ratel 15 8 Default 00000000 5 4 22 DDSO Register 0x15 RAM Segment Control Word 1 For more details refer to AD9954 datasheet DDSO Register 0x15 RAM Segment Control Word 1 Byte Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 RAM Segment 1 Address Ramp Rate 7 0 Default 00000000 1 Not Used Default 00000000 User Manual SMT399 160 Page 28 of 39 5 4 23DDSO Register 0x16 RAM Segment Control Word 24 For more details refer to AD9954 datasheet DDSO Register 0x16 RAM Segment Control Word 2 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 RAM Segment 2 Mode Control No Dwell RAM Segment 2 Beginning Address 9 6 Active Default 000 0 0000 1 RAM Segment 2 Beginning Address 5 0 RAM Segment 2 Final Address 9 8 Default 000000 00 5 4 24DDSO Register 0x17 RAM Segment Control Word 2 For more details refer to AD9954 datasheet DDSO Register 0x17 RAM Segment Control Word 2 Byte Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit1 BitO 0 RAM Segment 2 Final Address 7 0 Default 00000000 1 RAM Segment 2 Address Ramp Ratel 15 8 Default 00000000 5 4 25 DDSO Register 0x18 RAM Segment Control Word 2 For more details re
6. 20Technical 20 Specifications pdf O TIM specifications TI ftp ftp2 sundance com Pub documentation pdf files tim spec vlOl pdf O Xilinx Virtex II PRO FPGA Xilinx http direct xilinx com bvdocs publications ds083 pdf O MMBX Connectors Hubert Suhner MMBX Connectors 3 Examples of application The SMT399 160 module can be used in the following application Radio systems Compatible with Sundance s TIM Modules it can be combined with DAQ modules such as ADCs and DACs as a clock generator The SMT399 160 fine tuning makes it even more suitable for such platform to generate up to four synchronised and or quadrature signals Test systems It is sometimes very helpful to have a signal generator capable of generators various frequencies to evaluate some radio system Fast hopping is the key word here Dual tone signals are useful to characterise a receiver system to evaluate its capabilities of receiving signals close to each other in frequency DDSs also to generate a ramp a pattern or a frequency sweep Programmable system As most of system it a very important top control every part of a system The SMT399 160 is fully controllable via software Etc As both pairs of DDSs are synchronised and coupled master slave the module can generate 90 degree phase shift signals and be part of a quadrature modulator system Ext Clk ADCs a Ext Clk DAC Ext Clock SMT390 VP Dual 2
7. 1 Top View par WEE A ol SR Tre NIN i m mf cm ln imta Figure 10 Layout Top Side 6 2 Bottom View N Figure 11 Layout Bottom Side Page 34 of 39 7 Connector Location The following diagram shows where connectors are located on the board J13 J14 J15 J20 DDSO DOSO DDS1 DDSI Output0 Output1 Output0 Output1 ORO 4 A 4 4 1 J e J enn 4 J16 J17 n J16 19 all fitted tor dual fi LI l l lone mode L amk LULL oo External Reference J25 J24 Square Square Output0 Output Tngger NE Ee mion 111111 uit PS ie Figure 12 Connector Location 8 Support Packages An example code is provided with the SMT 399 160 often part of one of Sundance s software packages The example code if not targeting exactly the hardware platform used can be used as a base for an other platform 9 Physical Properties Dimensions maximum height 12 8 mm Weight 35 gramms Supply Voltages 3 3 and 5 Volts through SLB power connector Supply Current 12V N A 5V 0 3A Max 0 02A under Reset 3 3V 0 5A Max 0 35A under Reset 5V N A 12V N A MTBF It is strongly recommended to allow some air flow around the SMT399 160 module especially when used in a closed PC case in order to avoid it to reach high temperature 10 Safety This module presents no hazard to t
8. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 RAM Segment 0 Final Address 7 0 Default 00000000 User Manual SMT399 160 Page270f39 Last Edited 1 RAM Segment 0 Address Ramp Rate 15 8 Default 00000000 5 4 19 DDSO Register 0x12 RAM Segment Control Word 0 For more details refer to AD9954 datasheet DDSO Register 0x12 RAM Segment Control Word 0 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 RAM Segment 0 Address Ramp Rate 7 0 Default 00000000 1 Not Used Default 00000000 5 4 20DDSO Register 0x13 RAM Segment Control Word 1 For more details refer to AD9954 datasheet DDSO Register Ox13 RAM Segment Control Word 1 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 RAM Segment 1 Mode Control No Dwell RAM Segment 1 Beginning Address 9 6 Active Default 000 0 0000 1 RAM Segment 1 Beginning Address 5 0 RAM Segment 1 Final Address 9 8 Default 000000 00 5 4 21 DDSO Register 0x14 RAM Segment Control Word L For more details refer to AD9954 datasheet DDSO Register 0x14 RAM Segment Control Word 1 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 RAM Segment 1 Final Address 7 0 Default 00000000
9. Block Diagram 4 2 Module Description The module is built around two Direct Digital Synthesizers DDS two AD9954 The AD9954 is a DDS featuring 14 bit DAC operating at up to 400MSPS It forms a digitally programmable high frequency synthesizer capable of generating an analog output sinusoidal waveform at up to 160MHz The AD9954 provides fast frequency hopping and fine tuning resolution 32 bit frequency tuning word The AD9954 includes an integrated 1024x32 static RAM to support flexible frequency sweep capability in several modes It also supports a user defined linear sweep mode of operation The frequency resolution of the AD9954 is 0 0931 Hz when clocked at 400MHz Both analog outputs can be linked together via jumpers in order to generate a dual tone signal DDS outputs are doubled and combined with Variable Gain Amplifiers VGA Analog signals are all single ended and output on MMBX connectors J 13 J 14 J 15 and J 20 for connection to a 50 Ohm load Output Sine waves can be turned into sharp square signals using the AD9954 built in comparator Square signals one per DDS are also available on MMBX connectors J 24 and J 25 on LVTTL format All DDS settings travel via the FPGA present on SLB base module Information comes from a Comport and the FPGA stores it first into internal registers and interfaces it to the DDS chips via the SLB connector Comports follow the Texas Instrument C4x standard 4 green LEDs are also
10. For more details refer to AD9954 datasheet RefClk Multiplier VCO Range Charge Pump Current 00000 0 00 User Manual SMT399 160 Page 23 of 39 Last Edited 24 05 2007 17 12 00 Not Used High speed Hardware Crystal Not Used synch Manual Output Pin enable Sync active enable 0 Y 0 0 Y The high speed enhancement is off The high speed enhancement is on The hardware synch function is off The hardware synch function is on CRYSTAL OUT pin is inactive CRYSTAL OUT pin is active Valid values are decimal 4 20 Ox4 to 0x14 The VCO operates in a range of 100MHz to 250MHz The VCO operates in a range of 250MHz to 400MHz 0x0 75uA Ox1 100uA 0x2 125uA or 0x3 150uA User Manual SMT399 160 Page 24 of 39 Last Edited 24 05 2007 17 12 00 5 4 10 DDSO Register 0x9 Amplitude Scale Factor For more details refer to AD9954 datasheet DDSO Register 0x9 Amplitude Scale Factor Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0 0 Amplitude Scale Factor Register 7 0 Default 00000000 1 Auto Ramp Rate Speed Amplitude Scale Factor Registerf 13 8 Default 00 000000 DDSO Register 0x9 Amplitude Scale Factor Setting Auto Ramp Ra
11. available and driven by the FPGA to report working or failing conditions to the user Other green LEDs show that all power supplies are ON and working Two external triggers J 11 and J 23 are also available 4 3 SMT399 160 characteristics Analog Outputs J13 J14 J15 and J20 0 to 2 12 Volts without saturation sine wave Analog Output Voltage Range 0 to 3 0 Volts with saturation Output level set via Control Register VGA Frequency Resolution Figure 3 Output main characteristics 4 4 Power Supply structure The SMT399 160 conforms to the TIM standard for single width modules The TIM connectors supply 5 Volts to the base module which also requires an additional 3 3 Volt power supply which must be provided by the two diagonally opposite mounting holes This 3 3 volt is present on all Sundance TIM carrier boards From these two power rails are generated a filtered 3 3 volt as well as a 1 8 volt source for both AD9954s Greens LEDs placed on the board report the state of the power supplies The SMT399 160 requires 2 power rails from the SLB power connector 3 3 and 5 Volts 4 5 On board crystal The AD9954 are clocked from a crystal 20MHz The master DDS then passes the sampling clock to the slave DDS to ensure synchronisation Synchronisation can also be achieved when cascading several SMT399 160 daughter modules There is an automatic synchronisation available from the DDS registers 4 6 Outpu
12. 0x20 DDSO Register 20 0x20 Rising Delta Frequency Read back FPGA Register DDSO Rising Delta Tuning Word Frequency Tuning Word 0x21 DDSO Register 21 0x21 Rising Sweep Ramp rate Read back FPGA Register DDSO Rising Sweep Word Ramp rate Word 0x26 DDS1 Register 0 0x0 Control Function Register Read back FPGA Register DDS1 Register 0 0x0 0x27 DDS1 Register 1 0x1 Control Function Register Read back FPGA Register DDS1 Register 1 0x1 0x28 DDS1 Register 2 0x2 Control Function Register Read back FPGA Register DDS1 Register 2 0x2 0x29 DDS1 Register 3 0x3 Amplitude Scale Factor Read back FPGA Register DDS1 Register 3 0x3 Register 0x2A DDS1 Register 4 0x4 Amplitude Ramp Rate Read back FPGA Register DDS1 Register 4 0x4 Register 0x2B DDS1 Register 5 0x5 Frequency Tuning Word 0 Read back FPGA Register DDS1 Register 5 0x5 0x2C DDS1 Register 6 0x6 Frequency Tuning Word 0 Read back FPGA Register DDS1 Register 6 0x6 0x2D DDS1 Register 7 0x7 Phase Offset Word Read back FPGA Register DDS1 Register 7 0x7 Ox2E DDS1 Register 8 0x8 Frequency Tuning Word 1 Read back FPGA Register DDS1 Register 8 0x8 Ox2F DDS1 Register 9 0x9 Frequency Tuning Word 1 Read back FPGA Register DDS1 Register 9 0x9 0x30 DDS1 Register A OxA RAM Segment Control Read back FPGA Register DDS1 Register A OxA Word 0 0x31 DDS1 Register B 0xB RAM Se
13. 1 Bit 0 0 Falling Sweep Ramp Rate 7 0 Default 00000000 1 Not Used Default 00000000 DDSO Register Ox1E Falling Sweep Ramp rate Word Setting Falling Delta Frequency Word Description The Falling Sweep Ramp Rate is a 7 bit register that is used in the sweeping mode 5 4 32DDSO Register Ox1F Rising Delta Frequency Tuning For more details refer to AD9954 datasheet DDSO Register 0x1F Rising Delta Frequency Word Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BitO 0 Rising Delta Frequency Word 7 0 Default 00000000 1 Rising Delta Frequency Word 15 8 Default 00000000 User Manual SMT399 160 Page3lof39 Last Edited 24 05 2007 17 The Rising Delta Frequency word is a 32 bit register that is used in the sweeping mode For more details refer to AD9954 datasheet Rising Delta Frequency Word 23 16 00000000 Rising Delta Frequency Word 31 24 00000000 The Rising Delta Frequency word is a 32 bit register that is used in the sweeping mode For more details refer to AD9954 datasheet Rising Sweep Ramp Rate 7 0 00000000 Not Used 00000000 The Rising Sweep Ramp Rate is a 7 bit register that is used in the sweeping mode User Manual SMT399 160 Page 32 of 39 Last Edited 24 05 2007 17 12 00 6 PCBLayout 6
14. 10 MSPS ADC SMT370 Dual ADC DAC ChAO Analogue Converters Up to 160MHz Quadrature ChAO Analogue Converters Up to 160MHz ChA1 SMT399 160 ChBO Up to 160MHz Quadrature chB1 Ext Clock Channel A and Channel B synchronised SMT390 V P Dual 210 MSPS ADC ChAI SMT399 160 ChBO Up to 160MHz Ext Clk ADCs ChB1 Ext Clk DAC All channels synchronised SMT370 Dual ADC DAC Analogue Converters Analogue Converters Dual Quadrature Sampling Multi DAQ synchronisation ChAO Bi Up to 160MHz Clocks ChAI Analog SMT399 160 chie SMT390 VP Up to 160MHz or test pattern Dual 210 MSPS ADC ChB1 Analogue Converters ChBO Sampling with test pattern Figure 1 Examples of applications 4 Functional Description In this part we will see the general block diagram and some comments on the main entities 4 1 Block Diagram The following diagram shows the block diagram of the SMT399 160 Sundance SLB base module SMT338 VP SMT398 VP or SMT368 for example 68 I O pins 3 3V 5V SMT399 160 SLB D External Reference Option On board 1xAD9954 DDS Channel A AD8370 Crystal 14 bit 400MSPS VGA 48 pin TQFP Synchronisation AD8370 VGA 1xAD9954 DDS Channel B 14 bit 400MSPS MO 48 pin TOFP AD8370 VGA VOs Daughter Module SM7399 160 Figure 2 SMT399 160
15. 4 18 DDSO Register 0x11 RAM Segment Control Word 0 se se ee 27 5 4 19 DDSO Register 0x12 RAM Segment Control Word 0 28 5 4 20 DDSO Register 0x13 RAM Segment Control Word 1 n 28 5 4 21 DDSO Register 0x14 RAM Segment Control Word 1 see se ee 28 5 4 22 DDSO Register 0x15 RAM Segment Control Word L in 28 5 4 23 DDSO Register 0x16 RAM Segment Control Word 2 ed ee 29 5 4 24 DDSO Register 0x17 RAM Segment Control Word 2 sesse se se 29 5 4 25 DDSO Register 0x18 RAM Segment Control Word 2 sesse ed 29 5 4 26 DDSO Register 0x19 RAM Segment Control Word 3 se ee 29 5 4 27 DDSO Register 0x1A RAM Segment Control Word 3 n 30 5 4 28 DDSO Register 0x1B RAM Segment Control Word 3 30 5 4 29 DDSO Register 0x1C Falling Delta Frequency Tuning ee 30 5 4 30 DDSO Register 0x1D Falling Delta Frequency Word 31 5 4 31 DDSO Register Ox1E Falling Sweep Ramp Rate Word 31 5 4 32 DDSO Register 0x1F Rising Delta Frequency Tuning ee ee al 5 4 33 DDSO Register 0x20 Rising Delta Frequency Word ee 32 5 4 34 DDSO Register 0x21 Ri
16. Reserved 0000000 Gain Mode Gain 0 0000000 LG Mode Low Gain The Gain can be from 11 to 17dBs HG Mode Low Gain The Gain can be from 6 to 34dBs Gain value Binary The scale is from 11 to 17dBs LG Mode or from 6 to 34dBs HG Mode For more details refer to AD8370 datasheet Reserved 0000000 Gain Mode Gain 0 0000000 LG Mode Low Gain The Gain can be from 11 to 17dBs HG Mode Low Gain The Gain can be from 6 to 34dBs Gain value Binary The scale is from 11 to 17dBs LG Mode or from 6 to 34dBs HG Mode For more details refer to AD8370 datasheet Reserved 0000000 User Manual SMT399 160 Page 19 of 39 Last Edited 24 05 2007 17 12 00 Gain 0000000 LG Mode Low Gain The Gain can be from 11 to 17dBs HG Mode Low Gain The Gain can be from 6 to 34dBs Gain value Binary The scale is from 11 to 17dBs LG Mode or from 6 to 34dBs HG Mode Digital Comp DAC Clock External Linear SYNC_CLk Not Used Power Power Power Input Power Sweep No Out Down Down Down Power down Dwell Disable down Mode Y Q o 0 o Q Q 0 Load SRR AutoClear AutoClear Enable Clear Freq Clear SDIO LSB First IO UD Freq Phase Sine Accum Phase Input Only Accum Accum Output Accum Y Q o 0 Y 0 0 o The Linear Swee
17. Sundance LVDS Bus base modules such as SMT338 VP or SMT398 VP or SMT368 and cannot be used on its own It is built around two AD9954s Direct Digital Synthesizer DDS Analog Devices featuring 14 bit DAC operating sampling at up to 400 MHz Both devices are separately programmable can contain up to 4 profiles and have the possibility of being synchronised The architecture allows generating single tone or dual tone signals DDS outputs are split into two legs each of them featuring a programmable amplifier VGA The SMT399 160 has got in total two pairs of outputs A Xilinx FPGA Virtex II Pro or Virtex4 from the base module is used to control DDSs and Variable Gain Amplifiers VGAs of the SMT399 160 after receiving command words via a Comport SMT399 160 modules can be cascaded and work into the AD9954 Master Slave mode PCB connectors are MMBXs from Hubert Suhner It can be used in the following application Radio systems as a clock generator fine tuning Test systems dual tone and fast hopping Programmable system software programmable Etc 2 Related Documents O AD9954 Datasheet Analog Devices http www analog com Analog Root productPage productHome 0 2121 AD9954 00 html O Sundance High speed Bus SHB specifications Sundance ftp ftp2 sundance com Pub documentation pdf files SHB Technical Specification pdf O Sundance LVDS Bus SLB Sundance http www sundance com docs SLB 20
18. Tuning Description Word 1 The frequency tuning word is a 32 bit register that controls the rate of accumulation in the phase accumulator of the DDS core 5 4 16 DDSO Register OxF Frequency Tuning Word 1 For more details refer to AD9954 datasheet DDSO Register OxF Frequency Tuning Word 1 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Frequency Tuning Word 1 23 16 Default 00000000 1 Frequency Tuning Word 1 31 24 Default 00000000 DDSO Register OxF Frequency Tuning Word 1 Setting Frequency Tuning Description Word 1 The frequency tuning word is a 32 bit register that controls the rate of accumulation in the phase accumulator of the DDS core 5 4 17 DDSO Register 0x10 RAM Segment Control Word 0 For more details refer to AD9954 datasheet DDSO Register 0x10 RAM Segment Control Word 0 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 RAM Segment 0 Mode Control No Dwell RAM Segment 0 Beginning Address 9 6 Active Default 000 0 0000 1 RAM Segment 0 Beginning Address 5 0 RAM Segment 0 Final Address 9 8 Default 000000 00 5 4 18 DDSO Register 0x11 RAM Segment Control Word 0 For more details refer to AD9954 datasheet DDSO Register 0x11 RAM Segment Control Word 0 Byte Bit 7
19. a 12 40 Badiou 12 AVI LED Llano 13 5 Control Register Selms asses N De Ge do Ne N Ge EE GR Ge Ge Re Ese ede 13 5 1 Control Badesi rai 13 5 2 Reading and Writing Reg stes 14 5 3 Memory Mob aaa 14 54 Register Descriptions iss EE kak ol pe kle ie ap kk iaia 16 5 4 1 Reset and Update Register 0x0 erre eri 16 5 4 2 Profile Hester Ela 18 5 4 3 VGAD Register ellenica 18 5 44 VAT Heese Dida lai 19 54 9 VGA2 Register DA ei reali AAA Ani 19 5 4 6 VGA3 Register UD illa in 19 5 4 7 DDSO Register 0x6 Control Function Register rr 20 5 4 8 DDSO Register 0x7 Control Function Register rr 22 5 4 9 DDSO Register 0x8 Control Function Register rire 23 5 4 10 DDSO Register 0x9 Amplitude Scale Factor ine 25 5 4 11 DDSO Register OxA Amplitude Ramp Rate iii 25 5 4 12 DDSO Register 0xB Frequency Tuning Word 0 i 25 5 4 13 DDSO Register OxC Frequency Tuning Word 0 i 26 5 4 14 DDSO Register 0xD Phase Offset Word iii 26 5 4 15 DDSO Register OxE Frequency Tuning Word L i 26 5 4 16 DDSO Register OxF Frequency Tuning Word 1 iii 27 5 4 17 DDSO Register 0x10 RAM Segment Control Word 0 ee ee 27 5
20. ddress5 Address4 Address3 Address2 Address1 Address 0 3 Data 15 Data 14 Data 13 Data 12 Data 11 Data 10 Data 9 Data 8 4 Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 Figure 7 Setup Packet Structure 5 2 Readingand Writing Registers Control packets are sent to the SMT399 160 over Comport3 only in the standard firmware This is a bi directional interface The format of a Read Packet is the same as that of a write packet 1 Write Packet Fixed Sequence Read Write Address Read Write Data Read Write Data ComPort 3 SMT399 160 Figure 8 Control Register Read Sequence 5 3 Memory Map The write packets must contain the address where the data must be written to and the read packets must contain the address where the required data must be read The following figure shows the memory map for the writable and readable Control Registers on the SMT399 160 Address Writable Registers Readable Registers 0x00 Reset and Update Register Reserved 0x01 DDSO and 1 Profile Register DDSO and DDSI Profile Register 0x02 VGAO Read back FPGA Register VGAO 0x03 VGA1 Read back FPGA Register VGA1 0x04 VGA2 Read back FPGA Register VGA2 0x05 VGA3 Read back FPGA Register VGA3 0x06 DDSO Register 0 0x0 Control Function Register Read back FPGA Register DDSO Register 0 0x0 0x07 DDSO Register 1 0x1 Control Function Reg
21. e 4 leds are labelled on silkscreen LED1 LED2 LED3 and LED4 In the standard firmware provided with the board LEDO and LED2 are flashing in opposite phase as soon as the FPGA is configured and the on board crystal of the SLB based module is working LED1 is connected directly to the trigger signal coming from J 11 LED3 is connected directly to the trigger signal coming from J 23 External triggers have no more action than driving LED1 and LED3 The other 4 LEDs are connected on power rails and should be ON at all time If not it is strongly recommended to put the module off power and to contact Sundance 5 Control Register Settings The Control Registers control the complete functionality of the SMT399 160 They are setup via the Comport3 in the standard FPGA firmware provided 5 1 Control Packet Structure The data passed on to the SMT399 160 over the Comports must conform to a certain packet structure Only valid packets will be accepted and only after acceptance of a packet will the appropriate settings be implemented Each packet will start with a certain sequence indicating the start of the packet OxFF The address to write the data payload into will follow next After the address the data will follow This structure is illustrated in the following figure Byte Content Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BitO 0 T T T T T T T T 1 Address7 Address6 A
22. fer to AD9954 datasheet DDSO Register 0x18 RAM Segment Control Word 2 Byte Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit1 BitO 0 RAM Segment 2 Address Ramp Rate 7 0 Default 00000000 1 Not Used Default 00000000 5 4 26DDSO Register 0x19 RAM Segment Control Word 3 For more details refer to AD9954 datasheet DDSO Register 0x19 RAM Segment Control Word 3 Byte Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit1 BitO 0 RAM Segment 3 Mode Control No Dwell RAM Segment 3 Beginning Address 9 6 Active Default 000 0 0000 1 RAM Segment 3 Beginning Address 5 0 RAM Segment 3 Final Address 9 8 Default 000000 00 User Manual SMT399 160 5 4 27 DDSO Register 0x1A RAM Segment Control Word 3 For more details refer to AD9954 datasheet DDSO Register Ox1A RAM Segment Control Word 3 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 RAM Segment 3 Final Address 7 0 Default 00000000 1 RAM Segment 3 Address Ramp Ratel 15 8 Default 00000000 5 4 28 DDSO Register 0x1B RAM Segment Control Word 3 For more details refer to AD9954 datasheet DDSO Register 0x1B RAM Segment Control Word 3 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 RAM Segment 3 Address Ramp Rate 7 0 Default 00000000 1 N
23. gh The linear sweep no dwell function is inactive fay The linear sweep no dwell function is active The SYNC_CLK pin is active The SYNC CLK pin assumes a static 0 Autoatic Software Linear Not Used Sync Manual Enable Sync Enable o o Y 00000 RAM RAM Dest Internal Profile Control Load ARR OSK Auto OSK Enable is Phase Enable Keying Word 0 o 000 Y 0 0 The RAM disabled The RAM is active for operation The RAM drives the phase accumulator User Manual SMT399 160 Page 22 of 39 The RAM drives the phase offset adder Last Edited 24 05 2007 17 12 00 __ Internal Profile control The Amplitude Ramp Rate timer is loaded only upon timeout and is not loaded due to an Io Update input signal The Amplitude Ramp Rate timer is loaded only upon timeout and is loaded due to an Io Update input signal Shaped on off keying is bypassed Shaped on off keyingis enabled Manual on off keying operation selected Automatic on off keying operation selected The auto synchronisation of multiple AD9954 is inactive The auto synchronisation of multiple AD9954 is active The manual synchronisation of multiple AD9954 is inactive The manual synchronisation of multiple AD9954 is active 0 The linear frequency sweep capabilities are inactive 1 The linear frequency sweep capabilities are active
24. gment Control Read back FPGA Register DDS1 Register B 0xB Word 0 0x32 DDS1 Register C 0xC RAM Segment Control Read back FPGA Register DDS1 Register C 0x0 Word 0 0x33 DDS1 Register D 0xD RAM Segment Control Read back FPGA Register DDS1 Register D OxD Word 1 0x34 DDS1 Register E OxE RAM Segment Control Read back FPGA Register DDS1 Register E OxE Word 1 0x35 DDS1 Register F OxF RAM Segment Control Read back FPGA Register DDS1 Register F OxF Word 1 0x36 DDS1 Register 10 0x10 RAM Segment Control Read back FPGA Register DDS1 Register 10 0x10 Word 2 0x37 DDS1 Register 11 0x11 RAM Segment Control Read back FPGA Register DDS1 Register 11 0x11 Word 2 0x38 DDS1 Register 12 0x12 RAM Segment Control Read back FPGA Register DDS1 Register 12 0x12 Word 2 0x39 DDS1 Register 13 0x13 RAM Segment Control Read back FPGA Register DDS1 Register 13 0x13 Word 3 Ox3A DDS1 Register 14 0x14 RAM Segment Control Read back FPGA Register DDS1 Register 14 0x14 Word 3 0x3B DDS1 Register 15 0x15 RAM Segment Control Read back FPGA Register DDS1 Register 15 0x15 Word 3 0x3C DDS1 Register 16 0x1C Falling Delta Frequency Read back FPGA Register DDS1 Falling Delta Tuning Word Frequency Tuning Word 0x3D DDS1 Register 17 0x1D Falling Delta Frequency Read bac
25. he user when in normal use 11 EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the output cables Short circuiting any output to ground does not cause the host PC system to lock up or reboot
26. ister Read back FPGA Register DDSO Register 1 0x1 0x08 DDSO Register 2 0x2 Control Function Register Read back FPGA Register DDSO Register 2 0x2 0x09 DDSO Register 3 0x3 Amplitude Scale Factor Read back FPGA Register DDSO Register 3 0x3 Register Ox0A DDSO Register 4 0x4 Amplitude Ramp Rate Read back FPGA Register DDSO Register 4 0x4 Register 0x0B DDSO Register 5 0x5 Frequency Tuning Word 0 Read back FPGA Register DDSO Register 5 0x5 Ox0C DDSO Register 6 0x6 Frequency Tuning Word 0 Read back FPGA Register DDSO Register 6 0x6 0x0D DDSO Register 7 0x7 Phase Offset Word Read back FPGA Register DDSO Register 7 0x7 Ox0E DDSO Register 8 0x8 Frequency Tuning Word 1 Read back FPGA Register DDSO Register 8 0x8 Ox0F DDSO Register 9 0x9 Frequency Tuning Word 1 Read back FPGA Register DDSO Register 9 0x9 0x10 DDSO Register A 0xA RAM Segment Control Read back FPGA Register DDSO Register A OxA Word 0 Ox11 DDSO Register B 0xB RAM Segment Control Read back FPGA Register DDSO Register B OxB Word 0 0x12 DDSO Register C 0xC RAM Segment Control Read back FPGA Register DDSO Register C OxC Word 0 0x13 DDSO Register D 0xD RAM Segment Control Read back FPGA Register DDSO Register D 0xD
27. k FPGA Register DDS1 Falling Delta Tuning Word Frequency Tuning Word 0x3E DDS1 Register 18 0x1E Falling Sweep Ramp rate Read back FPGA Register DDS1 Falling Sweep Word Ramp rate Word 0x3F DDS1 Register 19 0x1F Rising Delta Frequency Read back FPGA Register DDSI Rising Delta Tuning Word Frequency Tuning Word 0x40 DDS1 Register 20 0x20 Rising Delta Frequency Read back FPGA Register DDS1 Rising Delta Tuning Word Frequency Tuning Word 0x41 DDS1 Register 21 0x21 Rising Sweep Ramp rate Read back FPGA Register DDS1 Rising Sweep Word Ramp rate Word Figure 9 Register Memory Map Analog Devices provides an Interactive Web Tool to calculate Tuning words It can be found at the following URL http designtools analog com dtDDSWeb dtDDSMain aspx part AD9954 5 4 Register Descriptions 5 4 1 Reset and Update Register 0x0 Reset Register 0x0 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 DDS1 DDSO DDS1 DDSO VGA3 VGA2 VGA1 VGAO IO Update IO Update Update Update Update Update Update Update Default 0 0 0 0 0 Oo 0 0 0 Reserved Reserved DDS1 DDSO VGA3 VGA2 VGA1 VGAO Reset Reset Reset Reset Reset Reset Default 0 0 1 1 1 1 1 1 Reset Register 0x0
28. ot Used Default 00000000 5 4 29DDSO Register 0x1C Falling Delta Frequency Tuning For more details refer to AD9954 datasheet DDSO Register 0x1C Falling Delta Frequency Word Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Falling Delta Frequency Word 7 0 Default 00000000 1 Falling Delta Frequency Word 15 8 Default 00000000 DDSO Register 0x1C Falling Delta Frequency Word Setting Falling cn Description Word The Falling Delta Frequency word is a 32 bit register that is used in the sweeping mode User Manual SMT399 160 Page30of39 5 4 30DDSO Register 0x1D Falling Delta Frequency Word For more details refer to AD9954 datasheet DDSO Register 0x1D Falling Delta Frequency Word Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Falling Delta Frequency Word 23 16 Default 00000000 1 Falling Delta Frequency Word 31 24 Default 00000000 DDSO Register 0x1D Falling Delta Frequency Word Setting Falling Delta Frequency Word Description The Falling Delta Frequency word is a 32 bit register that is used in the sweeping mode 5 4 31DDSO Register Ox1E Falling Sweep Ramp Rate Word For more details refer to AD9954 datasheet DDSO Register 0x1E Falling Sweep Ramp rate Word Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit
29. p Ramp Rate timer is loaded only upon timeout and is not loaded due to an Io Update input signal The Linear Sweep Ramp Rate timer is loaded only upon timeout and is loaded due to an Io Update input signal The state of the frequency accumulator remains unchanged Clears the frequency accumulator for one cycle on an IO Update signal The state of the phase accumulator remains unchanged Clears the phase accumulator for one cycle on an IO Update signal User Manual SMT399 160 Page 20 of 39 Last Edited 24 05 2007 17 12 00 Cosine Function Sine Function The frequency accumulator functions as normal The frequency accumulator is cleared until this bit is cleared The phase accumulator functions as normal The phase accumulator is cleared until this bit is cleared SDIO is bidirectional SDIO is unidirectional MSB first format is active LSB first format is active All Digital functions and clocks are active All non IO digital functions is suspended The comparator is enabled for operation The comparator is disabled The DAC is enabled for operation The DAC is disabled User Manual SMT399 160 Page 21 of 39 Last Edited 24 05 2007 17 12 00 The clock input circuitry is enabled The Clock input circuitry is disabled o Only digital logic and DAC are powered down when PWRDWNCTL pin is high m All functions are powered down when PWRDWNCTL pin is hi
30. sing Sweep Ramp Rate Word 32 6 PUBIAVOnE QQ 33 bl IDR 33 0 2 Bottom iN EE 34 7 Connector EE Ad ed EE EE MEE 35 8 Support Packages ii k kk sa ai ke mannara 36 9 Physical Properties kane paste anana one neve Eon EG Oe EG senten ante aksan enan es Re GR AYI Ge 37 EE EE NE EE N EE N EE N NE 38 IU INC 39 Table of Figures Figure 1 Examples of applications esse lese de EE Ee eo Ede ee Se GR Ge ee AR Ge Gee GR Eed NE 8 Figure 2 SMT399 160 Block Diagram lla 9 Figure 3 Output main characteristics rire 10 Figure 4 Connections for cascading modules ieri 11 Figure 5 Multi module synchronisation COMNECUOTS scesceseceseceeceeecesceeeceeceaeeeeceseeeaeeesees 12 Figure 6 Dual Tone Mode ie EE a or ka e n a a ek e e ke ak n e ke pea eee ken bn Ee 2 Figure 7 Setup Packet Structure scsscsssssccsssssssssssssessssscesscessssscesesssssscesssssssessesessasenees 13 Figure 8 Control Register Read Sequence ie 4 Figure 9 Register Memory Map cpl 16 Figur 10 oops 33 Figure 11 Layout Bottom Side nana 34 Figure 12 Connector Location osse eene dee ENE eta so p so kk ke eg De Fee GE pe Ri Ode Ge n Ee 35 1 Introduction The SMT399 160 is a multi output mezzanine single width module which is able to generate sine waves at up to 160MHz This mezzanine board is to be fitted on one of Sundance SLB
31. t Variable Gain Amplifier Each output is driven by a Variable Gain Amplifier VGA AD8370 digitally controlled that uses 8 bits to code the gain and provides a power down mode Two ranges of gains are available from 11 to 17dBs or from 6 to 34dBs 4 7 Daughter sub module interface The link between the main and the daughter sub module is made via two Samtec connectors There is no fast signal travelling between both cards The first connector passes control signals and the second one passes a 3 3 volt and 5 volt supplies and a ground between sub modules The female differential connector is located on the main module The Samtec Part Number for this connector is QTH 060 01 F D DP A The female power connector is located on the main module The Samtec Part Number for this connector is BKS 133 03 F V A The male differential connector is located on the daughter card The Samtec Part Number for this connector is QSH 060 01 F D DP A The male power connector is located on the daughter card The Samtec Part Number for this connector is BKT 133 03 F V A The mated height between the main module and the daughter card is 5 mm 4 8 Cascading modules Several SMT399 160s can be cascaded All DDSs can be synchronised by linking the modules via connectors J 1 and J 3 both are 2 mm 3 pin headers J 1 of the master module should be connected to J 3 of the slave module as follows SMT399 160 SMT399 160 Master J 1 Sla
32. te Speed Description Bit 15 14 0 0 Tell the OSK block how many amplitude steps to each increase DDSO Register 0x9 Amplitude Scale Factor Setting Amplitude Sani Description Bit 13 0 Programs the maximum value achievable by the OSK 5 4 11 DDSO Register OxA Amplitude Ramp Rate For more details refer to AD9954 datasheet DDSO Register OxA Amplitude Ramp Rate Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Amplitude Ramp Rate Default 00000000 DDSO Register OxA Amplitude Ramp Rate Setting Amplitude a Description 7 0 The 8 bit amplitude ramp rate used in the auto OSK mode 5 4 12 DDSO Register 0xB Frequency Tuning Word 0 For more details refer to AD9954 datasheet DDSO Register 0xB Frequency Tuning Word 0 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0 0 Frequency Tuning Word 0 7 0 Default 00000000 1 Frequency Tuning Word 0 15 8 Default 00000000 User Manual SMT399 160 Page 25 of 39 Last Edited 24 05 2007 17 12 00 DDSO Register 0xB Frequency Tuning Word 0 Setting Frequency Tuning Word 0 Description The frequency tuning word is a 32 bit register that controls the rate of accumulation in the phase accumulator of the DDS core 5 4 13 DDSO Register OxC Frequency Tuning Word 0 For more details refer to AD9954 datasheet DDSO Register 0xC Frequency Tuning Word 0
33. ting Bit 5 Description 0 0 Normal Operation 1 1 Forces DDSO to reload its registers Self clear To be used in conjunction of bit 14 to synchronise both DDS chips User Manual SMT399 160 Page 17 of 39 Last Edited 24 05 2007 17 12 00 Note 0 Reset bits don t get cleared automatically so a device can remain reset while not used to reduce the global power consumption Note 1 Update andIO_ Update bits get cleared automatically r 0x1 Any 16 bit value written in this register can be read back to check that the Comport used works properly Not Used Profile Selection DDS1 Profile Selection DDSO 00 00 0000 Profile 0 Selected DDSO OV Profile 1 Selected DDSO 10 Profile 2 Selected DDSO Profile 3 Selected DDSO Profile 0 Selected DDS1 OV Profile 1 Selected DDS1 10 Profile 2 Selected DDS1 qr Profile 3 Selected DDS1 5 4 3 VGAO Regis er 0x2 For more details refer to AD8370 datasheet Reserved 0000000 Gain Mode Gain 0 0000000 LG Mode Low Gain The Gain can be from 11 to 17dBs HG Mode Low Gain The Gain can be from 6 to 34dBs Gain value Binary The scale is from 11 to 17dBs LG Mode or from 6 to 34dBs HG Mode For more details refer to AD8370 datasheet
34. ve J 3 Crystal Out Crystal In J1 pin 1 J3 pin 3 Gnd Gnd J1 pin 2 J3 pin 2 Synch In Synch Out J1 pin 3 J3 pin 1 Figure 4 Connections for cascading modules J1 Synch out J3 Synchin EA Out 3 Crystal in yy 2 2 Gnd 3 Synch out 1 Synch in 18 Supply 1 5V 2 Gnd J6 Supply 3 3 3V Bii 3 5V 2 Gnd 1 3 3V Figure 5 Multi module synchronisation connectors 4 9 Dual tone Mode The SMT399 160 can used as a dual tone generator Both DDS outputs can be mixed together In this case all four analog outputs J 13 J 14 J 15 and J 20 would show the same signal at relevant amplitudes To configure the SMT399 160 into the dual tone mode simply fit J 16 J 17 J 18 and J 19 in place The normal mode of operation is obtained by leaving 16 J 17 J 18 and J 19 open J16 19 all fitted for dual tone mode Figure 6 Dual Tone Mode 4 10 External Trigger Two external triggers are available on J23 and J11 Both are straight through i e the connector is directly connected to the FPGA There is no protection so it is to the user to make sure levels present on the connector are compatible with the pad implemented in the FPGA In the default firmware provided J 23 is connected to LED1 and J 11 to LED3 see silkscreen for LED locations 4 11 LEDs There are 8 LEDs on the board Only 4 are user defined i e accessible from the FPGA on the SLB base module Thes

User Manual - Sundance Multiprocessor Technology Ltd.

Contents

Download Pdf Manuals

Related Search

Related Contents