SIS8300 µTCA FOR PHYSICS Digitizer User Manual
Contents
1. a Write Data Bit 1 Read Data Bit 1 0 Write Data Bit 0 LSB Read Data Bit 0 LSB The power up default value is 0x0 ADC Synch Cmd generates an synch pulse with AD9510 1 FPGA clock Page 36 of 67 Sd innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 17 ADC Input Tap delay registers 0x49 define SIS3305_ADC_INPUT_TAP_DELAY 0x49 The input tap delay registers are used to adjust the FPGA data strobe timing De 11 SO Function None ADC 9 10 ADC 7 8 ADC 5 6 ADC 3 4 ADC 1 2 None Tap delay value Select Select Select Select Select x 78ps write read 31 J J Tap Delay Logic BUSY Flag ENS f NN WEN el ADC 9 10 Select Bit 11 ADC7 8 Select Bit o 10 ADCS5 6 Select Bit 9 ADC3 4 Select Bit 8 ADC1 2 Select Bit Tap delay value Bit 7 Tap delay value Bit 7 6 _ Tap delay value Bit 6 Tap delay value Bit 6 Tap delay value Bit Tap delay value Bit 1 0 Tap delay value Bit 0 Tap delay value Bit 0 7 9 18 Virtex D System Monitor registers define SIS8300_VIRTEX5_SYSTEM_MONITOR_DATA_REG Ox90 define SIS8300_VIRTEX5_SYSTEM_MONITOR_ADDR_REG 0x91 define SIS8300 VIRTEX5 SYSTEM MONITOR CTRL REG 0x92 The Virtex 5 system monitor registers give access to temperature and voltages of the FPGA on the SIS8300 Refer to the sysmon c routine and the Virtex 5 FPGA documentation for details Page 37 of 67 Wie Innovative systeme Struck Documenta2. 0 x 0000 001E 0 x 0000 001F 0 x 1000 000E 0 x 1000 000F 0 x 1FFF FFEO 0 x 1FFF FFE1 0 x 1FFF FFFE 0 x 1FFF FFFF The structure of the memory buffer with 1 GByte i e 4 x 2 GBit memory chips is illustrated below 1 GByte 4 x 128M x 16bit 512M x 16bit 64M x 128bit 32M x 256bit Memory 256 bit Block Addresses O x 00 0000 O x 00 0001 O x 00 0002 0x FF FFFF Ox 100 0000 Ox 100 0001 O x 100 0002 Ox 1FF FFFF Memory 64 bit Addresses 4 x 256 bit Address O x 000 0000 O x 000 0001 O x 000 0002 O x 000 0003 O x 400 0000 O x 400 0001 O x 400 0002 O x 400 0003 0x 7FF FFFC 0x 7FF FFFD 0x 7FF FFFE Ox 7FF FFFF Wi Wi D Wi H Wi Wi Se Ss asserat K wg e Pea e PLA of Pa ei e Memory 32 bit Addresses 8 x 256 bit Address O x 000 0000 O x 000 0001 O x 000 0006 O x 000 0007 O x 800 0002 O x 800 0003 0x FFF FFF8 0x FFF FFF9 Ox FFF FFFE 0x FFF FFFF t mee oor oe oor e oo Prd P wg e Memory 16 bit Addresses 16 x 256 bit Address D x 0000 0000 D x 0000 0001 O x 0000 0
3. Right click on the selected component and open the Programming Property menu B ISE iMPACT P 68d Boundar L i File Edit View Operations Output Debug Window Help A DGX n ost BSA Tl HW iMPACT Flows O Fx a Boundary Scan T SIS8300V2 V1402 bat prom mcs File SystemACE Create PROM File PROM File Format H WebTalk Data las in 1 Program Verify Erase Blank Check Readback Get Device ID Get Device Checksum Get Device Signature Usercode One Step SVF One Step XSVF Assign New Configuration File Set Erase Properties Launch File Assignment Wizard Page 59 of 67 Struck Documentation SIS8300 uTCA for Physics Digitizer Enable the property items verify and parallel Mode 3 Boundary Scan fi SIS8300V2 V1402 b50 prom mcs dE File SystemACE Create PROM File PROM File Format H WebTalk Data b Device Programming Properties Device 1 Programming Properties Boundary Scan Device 1 PROM2 xcf32p Property Name Device 2 FPGA xcSvlx50t Verify Design Specific Erase Before Programming Read Protect PROM CoolRunner Il Usercode 8 Hex Digits Load FPGA Parallel Mode During Configuration PROM is Configuration Master check to select clock source External Clock select clock source During Configuration PROM is Slave clocked externally Saeed innovat
4. 7 5 19 2 Trigger Threshold registers define SIS8300_TRIGGER_THRESHOLD_CH1_REG 0x110 define SIS8300 TRIGGER THRESHOLD CH10 REG 0x119 These read write registers hold the threshold values for the 10 ADC channels 7 5 19 2 1 Trigger Threshold FIR Trigger Mode 0 Threshold value OFF edel value ON default after Reset 0x0 A trigger output pulse is generated on two conditions e GT is set GT in trigger setup register the trigger Out pulse will be issued if the actual sampled ADC value goes above the threshold value ON and OFF A new Trigger Out Pulse will be suppressed until the ADC value goes below the threshold value OFF e GT is cleared LT in trigger setup register the trigger Out pulse will be issued if the actual sampled ADC value goes below the threshold value ON and OFF A new trigger Out pulse will be suppressed until the ADC value goes above the threshold value OFF the trigger Out pulse will be issued if the actual sampled ADC value goes below the threshold value GT greater than LT lower than Page 39 of 67 Struck Documentation SIS8300 aa innovative uTCA for Physics Digitizer systeme 7 5 19 2 2 FIR Trigger Threshold FIR Trigger Mode 1 baang threshold value default after Reset 0x0 The value of the Sum trapezoidal value depends on the peaking time P Therefore the selection of the value of the Trapezoidal threshold depends on P also Trapezoidal value calculation Trapezoidal v
5. In order to be able to decide whether a connected RTM is compatible to the SIS8300 the RTM record shall contain one of the Zone 3 Identifier records listed in the table below Supported Zone 3 Identifier Records Interface Identifier OEM IANA PEN Private Zone 3 OEM record Descripton enterprise number compatibility compatibility Page 56 of 67 S Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 9 Firmware upgrade Two files are needed for the updating process the real firmware as a binary file and an EPROM file The FPGA is programmed with the Xilinx software iMPACT 9 1 Create programming file Before creating the programming file the value of the Configuration Rate should be set to 42 E tg Inst ext reg test ext reg test Behavioral d Et Process Properties Configuration Options mg ad9510 synch logic risingedge2pulse gene LEE d adcl clock buffer adc clock buffer Beha adc2 clock buffer adc clock buffer Behay Switch Name Property Name Value adc3 clock buffer adc clock buffer Beha General Options a g ConfigRate Configuration Rate wj adc4_clock_buffer adc clock buffer Beha Configuration Options t S artup Options g CclkPin Pett Up Category Configuration Clk Configuration Pins i Du Inst adc input block adc input block Be Readback Options g MOPin Configuration Pin MO Pull Up J adc_chl_fir_and_threshold_tri
6. The contents of the sample memory start address register is assigned as memory data storage address with the arm command key address arm sampling or with the enable command key address enable sampling The read function from these registers give the information of the actual sampling address for the given ADC channel at the moment only valid if the logic is not busy Read Function ADC chx Actual Sample Address reserved Actual Sample Address in 256 bit Blocks 16 bit word address x 16 The value is given in 256 bit Blocks 16bit word address x 16 Page 41 of 67 Wie Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 21 Sample Length register define SIS8300 SAMPLE LENGTH REG Oxl2A This register defines the number of sample blocks of each ADC channel The register must be set to number of sample blocks 1 The size of one sample block for each ADC channel is 256 bit 16 x 16 bit word Bit 31 24 Sample Block Length 1 Default after Reset 0x0 7 9 22 Ringbuffer Delay register fdefine SIS8300 PRETRIGGER DELAY REG 0x12B This register defines the number of pre trigger delay samples for all channels The maximum pre trigger delay value is 2046 Bit 31 12 Page 42 of 67 Wine Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 23 Test Histogram Pattern Memory Address register define SIS8300 TEST HISTO MEM ADDR OxLZC This regis
7. 0 x 00 0000 0 x 00 0001 0 x 00 0002 0x7F FFFF 0 x 80 0000 0 x 80 0001 0 x 80 0002 O x FF FFFF Memory 64 bit Addresses 4 x 256 bit Address 0 x 000 0000 0 x 000 0001 0 x 000 0002 0 x 000 0003 0 x 200 0000 0 x 200 0001 0 x 200 0002 0 x 200 0003 0 x 3FF FFFC 0 x 3FF FFFD 0x 3FF FFFE 0x 3FF FFFF Ss Wi Wi Se Se Wi amar ore tee Se Bi e wg e e e LI e Pid e Memory 32 bit Addresses 8 x 256 bit Address 0 x 000 0000 0 x 000 0001 0 x 000 0006 0 x 000 0007 0 x 400 0002 0 x 400 0003 0x 7FF FFF8 0x 7FF FFF9 0x 7FF FFFE 0 x 7FF FFFF 16 x 256 bit Address e B eg oe D I on oo mee Memory 16 bit Addresses 0 x 0000 0000 0 x 0000 0001 0 x 0000 000E 0 x 0000 000F 0 x 0800 0006 0 x 0800 0007 0x OFFF FFFO 0 x OFFF FFF1 0 x OFFF FFFE 0 x OFFF FFFF Memory 8 bit byte ce ef e ef e e e e oo e oo e e ei e D P ei e Addresses 32 x 256 bit Address 0 x 0000 0000 0 x 0000 0001
8. 0000FFFF Page 22 of 67 Sd innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 9 3 XILINX JTAG register define SIS8300_XILINX_JTAG_REG 0x02 This register is used in the firmware upgrade process over PCIe only A TCK is generated upon a write cycle to this register read Function TDO 30 IxShifted TDO M 4 nones o O 3 nones Qo 0 0 0 0 0 0 O 2 mom oo TMS o ooo 0 mm J30xShfiedTDO 9 O The read register function operates as a shift register for TDO The content of the read register is shifted to the right by one bit with every positive edge of TCK and the status of TDO is transferred to Bit 30 Bit 31 reflects the current value of TDO during a read access 7 5 4 XILINX Virtex5 Error Detection register define SIS83300 XILINX ECC REG 0x03 XILINX Virtex5 configuration memory error detection register 3 0 s O C OO Frame ECC output indicating a valid SYNDROME value JI CRC Error ECC Error SYNDROME Status bit 11 SYNDROME Status bit 1 0 SYNDROME Status bit 0 Page 23 of 67 Sd innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 5 User Control Status register define SIS8300_USER_CONTROL_STATUS_REG 0x04 The control register is implemented as a selective J K register a specific function is enabled by writing a 1 into the set enable bit the function is disabled by writing a 1 into the clear disable b
9. 1 External Trigger Enable 8 LNVDS Input 0 External Trigger Enable LVDS Input 0 External Trigger Enable 6 LVDS Input 6 External Trigger falling edge LVDS Input Bit 6 E ee LVDS Input 1 External Trigger falling edge LVDS Input Bit 1 Note external trigger in signals are synchronized with the FPGA CLKO5 Page 28 of 67 Sd Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 10 Harlink Connector Input Output Control register define SIS8300 HARLINK IO CONTROL REG 0x13 Read 21 Nofuction S 0 0 00 9 Harlink Input 2 External Trigger Enable Harlink Input 2 External Trigger Enable 8 Harlink Input 1 External Trigger Enable Harlink Input External Trigger Enable 7 Nofuction 4 JO O 6 Nofucio amp 4 0 09 O 5 jNofucion 64 4 JO 9 O 4 Nofunction 0 0 Nofuction jHarinkInut O only if Harlink Test Output Enable 1 only if Harlink Test Output Enable 0 Harlink Connector Input 1 external trigger In Harlink Connector Output 1 adc chx or trigger out Note external trigger in signals are synchronized with the FPGA CLKO5 Page 29 of 67 Sd Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 11 Clock Distribution Multiplexer control regis
10. 46 7 5 29 Read DMA Card Memory Source address aaiaaaiaaaaiasaiasatasatasanasananananannnnnnnnannnnnananinannaaanaaia 46 7 5 30 Read DMA Transfer length ege be deen 47 Ree V Nb xen EE 47 7 5 32 Readout DMA Sample byte gwanp 47 7 5 33 Write DMA System Source address lower 32bits aaaaiaaaiasaiasaiasanasaaanatnnninnanananananananaaaanaaa 48 7 5 34 Write DMA System Source address upper 32bits aaaiaaaiasaiasaiasaiasaaasatasatasanasatanananaaaaaaaaaa 48 7 5 35 Write DMA Card Memory Destination address 48 1 3 36 Write DMA Transiter Wen WE 49 Joo cu cod A We rolls T M 49 7 5 38 DAQ Done DMA Chain Control iiaaaaaaaaaaaaaaasasassasansannnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnninnnnnnnnnnnia 50 pos MOEN eee eet E ee em rT er eT 50 ype E O25 EE 51 TAL IOC i E 51 Be GTA EE 51 T343 RAMPIFO EE TT 52 Io Ja Ta e 53 Vet User Block tan DMA T TT 55 4 06 User DMI IN rk em 55 EE 56 STI E 57 9 1 CI DUN l a ace Mae l a dunes haar DU Ree UMEN AU eames 57 DS MEME A r B Ji BUILT um 58 25 us uicit POA a a m cs 50 10 PIS VI E 61 10 1 Power rior LEE 61 10 2 Ordering E E 61 10 3 RTM Zone 3 connectors J75 and Tip 62 10 3 1 J75 connector pin asgeignmentz 62 10 3 2 J76 connector pin asgeignmentzg 63 10 3 3 Note on AC DC input stage selecton 63 10 4 RTM connector schemancg 65 11 mro AVS
11. 63 RZAD feira H BE HEN HEN HEN HEN BEN EHE HEN HEN Wu me 7 Ses Inpa fe maha EN EN EN o E res D H scoort R m d nm UA Tu g T any ony eon Es SIT id 1 3 OO 9 9 E KEE TOK Su OOO EE ase E pg panasi e E Bea S M SC i P XA y em es omg me Gs DT E Ze p Es Misa Lee as R23 S seeeeeene e EAS feas SCT s 1J76 b s iridis uk ar EE ati CH li nm T 5 ar gummi YT 2s mH EB EB TTT S SON 22098 HITT Can FP IN e ee OSC c Der Se EE e U241 MMMM Say E pA jo nm nn Sum uT d 4 MH m m o TP514 ZE a comen ES sn 8 g scu wwe UD RB LS Spas Acme ee RR jaa Er D no M E a Ex Xu eo y 4 II 2 SIT L H dE CH T ms 1 um DO B sew emi K xs o c80 Bc 32 C87 1 Connector types The used connectors are listed 1n the table below 77 RTMKeying On J Note The used Key may depend on the hardware configuration of the SIS8300 Page 13 of 67 O ve Ss oO e Sa Z D E r c Un S Sa Q un v 8 0 NJ ONG 13NNVHO2O vna L NJ Av 13d Y4Y344N9ONIY L N3 32018 M e D See ee E E E EE E EA M TT Oe Se im 5 ue WOp HID LO sdpez lt S i X gt sdooz Aeq 5 x5 Loay ung 09d HID LJAYV e ap syjo p Eyep aye z DS LXO Bay Ippy WO UE Yls Ploysesy wua BIR Le 231607 sseJppy SS idi E poser Hal eee E BEI p
12. O 7 5 42 IRQ Refresh define IRQ REFRESH 0x223 This register refreshes the interrupt logic This might be needed in the case an interrupt happens while the software interrupt service routine was still handling the previous interrupt Refresh IRQ logic MMM Page 51 of 67 Sd innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 43 RAM FIFO debug register define RAM FIFO DEBUG 0x231 This register provides fifo information of internal read and write fifo pipes in the DDR2 memory controller It also allows to selectively reset each data path Bit read 31 Reset read address data fifos Reset status Selected fifo status bit 27 O unused jSelected fifo status bit 0 Fifo O status bits Bit write read 27 mme 12 mme Read data fifo almost empty Read data fifo empty 9 funused 0 0 00 0 Junused Fifo 1 status bits Bit 0 Read address fifo fill count bit 9 Read address fifo fill count bit 0 Fifo 2 status bits Bit 0 Write data fifo fill count bit 9 Write data fifo fill count bit O Page 52 of 67 Sd Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer Fifo 3 status bits read e ee 10 3 unsed Write address fifo fill count bit 9 O unused Write address fifo fill count bit 0 7 6 External register interface The external register interface provides the user wit
13. Q 66 Page 4 of 67 SIS Documentation SIS8300 PST innovative uTCA 16 bit Digitizer systeme 1 Introduction The SIS8300 is a ten 10 channel 125 MS s digitizer with 16 bit resolution according to the uTCA for Physics draft standard SIS8300 with SFPs installed As we are aware that no manual is perfect we appreciate your feedback and will incorporate proposed changes and corrections as quickly as possible The most recent version of this manual can be obtained by email from info struck de the revision dates are online under http www struck de manuals html Note 1 It is PICMG s policy to prohibit claims of compliance with respect to a specification under development Any such claims must be understood as applying to a draft which is subject to change Note 2 The SIS8300 is developed in co operation with DESY under ZIM grant 2460101MS9 ZIM Zentrales Innovationsprogramm Mittelstand 1 1 Related documents A list of available firmware designs can be retrieved from http www struck de sis8300firm html Page 5 of 67 Struck Documentation SISS300 0e uTCA for Physics Digitizer systeme 2 Design The central building block of the SIS8300 card is a Xilinx Virtex 5 FPGA It holds the 4 lane PCI Express interface and is in control of all active components 2 1 Functionality The key properties of the SIS8300 card are listed below AMC A uTCA for Physics Board 4 Lane PCI Express Interface Dual SFP Card Cage for
14. S T ae e OLUD MI J DIousaJuJ Eep OLUD MOO JeBBu p lal erp oru asind 1266u1 OLUO OUR Sav esing J BBU x49 Iv o11u02 e duues sJeDBu puxa SNES UIUOD 9 2d Page 15 of 67 Struck Documentation SIS8300 uTCA for Physics Digitizer 7 2 Memory Interface 4innovative systeme The sis ddr2 interface with histogramming provides the user logic with the possibility to write to the Memory and to increment histogram the content of 32 bit memory values sis ddr2 interface Head Interface Data Fifo PCle DMA Interface 512 x 128 Address Fifo sis write addr fifo wr en sis write 64bit addr fifo din 512 x 32 Write Interface Address Fifo sis write addr fifo wr count 512 x 32 sis write data fifo wr en sis write data fifo din Data Fifo sis write data fifo wr count 1023 x 128 sis write histo addr fifo wr en sis write histo 32bit addr fifo din protocol addr data Histogram Interface Address Fifo sis write histo addr fifo wr count 512 x 32 DDR2 Memory 512 MByte 64M x 64 bit or 1 GByte 128M x 64 bit User Interface block diagram for Memory read write and histogram operations Page 16 of 67 Struck Document
15. Sample Start Address Actual Address register Page 20 of 67 Un truck Documentation SIS8300 innovative Oxi21 R W ADC ch2 Memory Sample Start Address Actual Address register ee eee ADC ch10 Memory Sample Start Address Actual Address register MMM ADC chx Sample Length register ADC chx Ringbuffer Delay register 0 to 2046 NENNEN ee Test Histogram Pattern Memory Address register Test Histogram Pattern Memory Data Write register Test Histogram Control register SIS8900 RTM LVDS Test Input Output Control register Kb WE WE E NENNEN NENNEN EG 0x221 R IRQSmus 00 O Mapped out of register bank to top level May be used for user defined register implementation See Section 7 6 EE es o es xare LRN Page 21 of 67 Sild Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 Register description 7 5 1 Module Id and Firmware Revision register define SIS8300_IDENTIFIER_VERSION_REG 0x00 This register holds the module identifier SIS8300 and the firmware version and revision 31 16 FFFF0000 Module Identifier 0x8300 is ream es 0000FFOO Example The initial version of the SIS8300 reads 0x83001400 7 5 2 Serial Number register define SIS8300_SERIAL_NUMBER_REG 0x01 This register holds the Serial Number of the module BIT access Name Function 31 16 reserved FFFF0000 Ro Serial Number 1 65535
16. optional Multi Gigabit Link Xilinx Virtex 5 FPGA DDR2 Memory Interface 4 x GBit default DDR2 memory 4 x 2 GBit option Atmegal28 IPMI External Clock and Trigger Inputs Frontpanel digital I O 4in 4 out on Harlink Connectors RTM ADC Analog Inputs I2C Bus 10 ADC Channels 125MS s 16 Bit 2 DAC Channels 250MS s 16 Bit Clock distribution with phase shifting 4 M LVDS uTCA Ports 2 uTCA Clocks 2 2 Block Diagram A simplified block diagram of the SIS8300 is shown below Page 6 of 67 Struck Documentation SIS8300 Saree innovative uTCA for Physics Digitizer systeme 2 3 Platform Management The management code of the SIS8300 is implemented in an Atmel Atmegal281 16MU microcontroller and can be upgrade in field over connector J32 see section 3 3 Page 7 of 67 iie innovative systeme S Struck Documentation SIS8300 uTCA for Physics Digitizer 2 4 Clock Distribution The clock distribution scheme of the SIS8300 is illustrated below 2 FPGA r S LO O Bo z 1 FPGA CLKO5 0 E LO d B Q rf t ADCLK925 ADCLK925 1 Ch1 ChO 3 1 2 0 3 1 2 0 RTM CLKO gt RTM CLK1 9 z e N Q RTM CLK2 st EXTCLKA X F SMA E 9 3 Q CLK e 1 O c EXTCLKB x n HARLINK amp gt EI R Q CLK2 K O c Page 8
17. 00 top bit E F ui cm g m tu 3 Page 58 of 67 Sd innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 9 3 Program FPGA After a Boundary Scan and the initialisation of the chain select the created mcs file m File Edit View Operations Output Debug Window Help D amp H XaBxzzi mxie nm ie IMPACT Flows au D GN E Hg Boundary Scan SFR Si jf gay us i File E SystemACE i 1 amp Create PROM File PROM File Format CET neon i WebTalk Data xc5vlxS0t bypass F Assign New Configuration File Organisieren v Neuer Ordner Favoriten Name Anderungsdatum EE Desktop A Gossip EU et 15 10 2013 14 14 Dateiordner Downloads A Ge L EE 15 10 2013 14 21 Dateiordner Zuletzt besucht A EE 15 10 2013 14 23 Dateiordner l Se abes 05 05 2011 10 51 MCS Datei 4 718 KB Bibliotheken _ SIS8300V2 V1400 50 prom mcs 19 01 2012 11 49 MCS Datei 6 721 KB E Bilder SIS8300V2 V1402 bat prom mcs 21 12 2012 15 04 MCS Datei 4 718 KB E Dokumente 3 SIS8300V2 V1402 lx85 opt portl4 15 pro 23 09 2013 10 57 MCS Datei 7 837 KB a Musik E Subversion iMPACT Processes 08x E Videos Available Operations are umb Erase jE Computer mb Blank Check mb Readback Get Device ID Get Device Checksum Get Device Signature Usercode Ke Dateiname SIS8300V2 V1402 lx50 prom mcs v All Design Files mcs isc bs v Abbrechen
18. 00E 0 x 0000 000F Ox 1000 0006 Ox 1000 0007 0x 1FFF FFFO Ox 1FFF FFF1 O x 1FFF FFFE 0x 1FFF FFFF Memory 8 bit byte Addresses 32 X 256 bit Address a a ef e e ef e e Di ei e BI D e e D ef D D eg e e e D e e 0 x 0000 0000 D x 0000 0001 0 x 0000 001E 0 x 0000 001F 0 x 2000 000E 0 x 2000 000F 0 x 3FFF FFEO 0 x 3FFF FFE1 O x 3FFF FFFE O x 3FFF FFFF Page 19 of 67 Struck Documentation SIS8300 innovative 7 4 Address Map Following 32 bit addresses are implemented Function Denn IR Module Identifier Firmware Version register ox0 R Serial number register XILINX JTAG register 0x03 OO R XILINX Virtex5 configuration memory Error Detection register a eee User Control Status register JK 0x05 R jFimwarOptonsregister ww LLL d Link 2 set control refer to VHDL code LU ee UR EUVgNWNWNWMWMWMWMgg WM oo T DAC Control register DAC Data register ADC SPI Interface register ADC Input Tap delay register VIRTEX5_SYSTEM_MONITOR_ADDR register VIRTEX5_SYSTEM_MONITOR_CTRL register ADC ch Trigger Setup register ADC ch2 Trigger Setup register ADC ch10 Trigger Setup register ADC ch2 Trigger Threshold register ADC ch10 Trigger Threshold register ADC chl Memory
19. 44 Test Histogram Pattern Memory Address 43 Test Histogram Pattern Memory Data Write 43 trigger setup 38 39 trigger threshold 39 User Control Status 24 XILINX JTAG 23 XILINX Virtex5 Error Detection 23 registers Virtex 5 System Monitor 37 RTM 56 RTM connector schematics 65 RTM connectors 62 RTM management 56 SAMTEC 13 SIS8300 uTCA for Physics Digitizer Sd Innovative systeme SFP 6 12 13 SI5326 34 SIS8300 5 SMA 12 SYNDROME 23 TDI 23 TDO 23 temperature 37 TMS 23 TORB 35 trigger threshold 39 Two s complement 35 TYCO 13 U 10 U222 31 U223 31 U240 31 U250 31 U251 31 U500 9 user LED 24 user blockram dma interface 55 user interrupt interface 55 Virtex 5 6 Virtex5 Error Detection register 23 watchdog reset 9 XCSVLX110T 1FFG1136C oi XC5VLXS50T 3FFG1136C 61 Xilinx 6 ZIM 5 Zone 3 62 Page 67 of 67
20. 5 gt dpoint device Inst ingress path ingress fifo data 1 01 01 GE GE E l c uU 9 endpoint device Inst ingress path ingress fifo data ooot ooot O Oo 7 npg ci gt Inst ext reg test data out 0001 0001 C 0001000 4 000500 O Q 5 The signals from top to bottom are A read request from the external register space causes the signals to change as follows 1 register read pulse 2 register write pulse The address bus changes its value to the current selected register 3 register address bus 8 bits wide 4 register data write bus 32 bits wide The read enable signal is pulsed for 1 clockperiod 5 register data read bus 32 bits wide from user H defined register logic The user data from the external register 1s expected to be valid 1 clockperiod after the read pulse N ON A c X OM uu CO gt 2 HI 8300 endpoint device Inst register bank fsm reg 0x400 Ox4FF rd en 0 0 lt S198300 endpoint _device Inst_ register bank reg 0x400 Deae wr en of of TP E gt nst sis8300 endpoint device Inst ingress path ingress fifo data 1 07 07 RE Ge EE el 5 9 Inst sis8300 endpoint device Inst ingress path ingress fifo data 1234 1234 12345678 LIZ D SD EEF O OZ OZO OSOS O O c The signals from top to bottom are A write request to the external register space causes the signals to change as follows S 1 register read pulse 5 2 register wri
21. 5 and J76 J75 and J76 are 90 pin right angle female connectors providing 30 contact pairs each 60 signal contacts and 30 ground contacts Every contact pair is surrounded by a L shaped male shield blade The shielding contact is designated with the names of the corresponding signal pair signal pin a and b is affiliated with shielding contact ab e g The picture below shows the connector contact layout as seen from the rear side of the board QOO MA Oa 10 3 1 J75 connector pin assignments The J75 connector routes the differential analog input signals of the ADC channels and ground to the RTM The characters TF in signal names stand for signals to the AC coupled transformer input stages In same fashion PA stands for DC coupled preamplifier input stage Col gt ef f e cd C Seil po Lo LL Ll C Lt LL 9 GND CHI_TF CHI TF GND GND GND GND CH8_PA CH8_PA 8 GND CH7 PA CH7 PA GND GND GND GND CH2 TF CH2 TF 6 GND CH5_PA CH5_PA GND GND GND GND CH4_TF CH4 TF Page 62 of 67 Nd Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 10 3 2 J76 connector pin assignments The J76 connector is used to route power data and system management pins to the RTM board Col Row 10 GND GND GND GND GND GND GND GND GND o ann oe oer GND OND op GND Ou Oe 8 GND GND GND GND CLK7 CLK2
22. B 0 binary 1 Two s complement S EE Select i eman Test Mode Bit 1 O Test Mode Bit 0 po The power up default value is 0x0 0 0 Data from DAC Data register 0 II Ramp Test Mode 1 jo ADCUADCH DACIDAC H reserved Noles ADC 1 Clock is used as DAC clock 7 5 15 DAC Data register define SIS8300_DAC_DATA REG 0x46 a Ng i EB ea BEE 0 DACIDaaO0 7 The power up default value is 0x0 data 0 1 V data 0xFFFF 1V output with TORB 1 i e in Two s complement mode Note The default DAC range is 1V 1 V into a 50 O load Page 35 of 67 Sd Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 16 ADC Serial Interface SPI interface register define SIS8300 ADC SERIAL INTERFACE REG 0x48 Several parameters of the ADC AD9268 chip can be configured with the SPI serial Peripheral Interface Please refer to the documentation of the ADC AD9268 chip for details ADC Synch cmd Write Read Logic BUSY Flag a 26 ADCSeectMuxBit2 Jooo o 25 _ ADC Select Mu Bn 24 _ ADCSelectMuxBitO 23 Read Cmd le ES A sss 20 Address Bit12 19 J Address Bit II ooo a ee E BE 2 Address Bit b 11 AddesBit3 le JO AddesBit2 le 9 Address Dn le 8 Address BitO 6 WrieDataBit Read Data Bit 6
23. DR LO32 0x210 This register holds the lower 32bits of the destination address in system memory from which the card will transfer data it 31 0 Function System memory address lower 32bits D 7 5 34 Write DMA System Source address upper 32bits define DMA WRITE DST ADR HI32 Ox This register holds the upper 32bits of the destination address in system memory from which the card will transfer data Bit 31 0 Function System memory address upper 32bits 7 5 35 Write DMA Card Memory Destination address define DMA WRITE DST ADR LO32 0x212 This register holds the 32bit destination address in the cards address space which is used to select the data source which is written to Bit Function 31 0 Card address space Depending on the populated amount of dram on the module the address layout 1s 512MB Models Address 0x0 OxlFFFFFFF DDR2 Memory Page 48 of 67 Wie Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 1GB Models Address 0x0 Ox3FFFFFFF DDR2 Memory 7 9 36 Write DMA Transfer length define DMA WRITE LEN 0x213 This register holds the amount of data which is going to be transferred Bit DMA Transfer length 7 5 37 Write DMA Control define DMA WRITE CTRL 0x214 This register starts the Write DMA process and allows to poll the transfer status 31 wmued Jl PEN OO 1 fumused Jl 0 Lana jDMArmnng Page 49 of 67 Sd Innovative syst
24. GND GND GND 7 GND GND GND GND GND GND GND GND GND 6 GND Dii Dil GND D10 D10 GND D Dr 5 GND D amp D8 GND D D7 GND D D r 3 GND D D2 GND Di Di GND D Dir 10 3 3 Note on AC DC input stage selection The AC transformer or DC operation amplifier Opamp input path is selected on the SIS8300 card via 0603 solder bridges as illustrated for channels 0 and 1 on the screenshot below The designators for all channels can be found in the table below AC Transtormer Input DC Opamp Input Page 63 of 67 Wie Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer Input for ADC O SW63A ADC CHO O SW 3B X ADC CHO SW6 lA X ADCCHI ADC CHI 2 SW58A X ADC CH2 2 SW58B X ADC CH 3 SW56A ADC CH3 6 SW48A ADC CH6 gt 6 SWABB _ ADC_ CH6 S 8 SWBA LADC CH 8 SW43B X ADCCHE 9 SWAA ADC CH9 9 SW4IB ADCCH Ill Page 64 of 67 Struck Documentation SIS8300 qnte innovative systeme uTCA for Physics Digitizer 10 4 RTM connector schematics d SS T SE un a iE 8 E 3 SZ uu g ER E 3 3 3 3 E i A E 1 F i 2 E s e JE JE ae S i LE E 28 Slat z ME amp amp a ER 8 T S N ES dee E em i PARERE E E E gd E
25. Interface read EE Cmd Bit 1 Write Read Logic BUSY Flag Cmd Bit 0 n Set Function Output Level Status of Set Function Output Level 28 Select Function Status of Select Function synchronisation CLK synchronisation CLK k sus ADSSIBE 23 Read Cycle Bit m pM a o E 20 Address Bit 12 o o H Adesi OO Bit 11 EBBS EEN NND p E L L E SE BE 12 _ AddressBit4 l jAddesBi3 O Le le 10 AddesBi2 E 9 JlAddesBitl 1 1 a 8 j AdmsBto SO S 7 Write Data Bit 7 MSB Read Data Bit 7 MSB 6 Write Data Bit6 Read Data Bit6 Write Data Bit 1 Read Data Bit 1 0 Write Data Bit 0 LSB Read Data Bit 0 LSB The power up default value 1s 0x20000000 Page 32 of 67 Struck Documentation SIS8300 uTCA for Physics Digitizer Wine Innovative systeme Command Bit 31 30 Explanation Cmd Bit 1 Cmd Bit 0 Command 0 O No Function 0 I X R WCMD l Function CMD Generates a pulse at the Function Input pin of the AD9510 which is synchronous to the selected clock The clock selection is done via Bit 28 Function Syn CLK The actual function depends on the programming of the selected AD9510 Select Function synchronisation CLK Bit 28 Explanation Clock Source 0 PCI Clock FPGA CLK 69 Note 1 enable READ by writing 0x90 to addr 0x0 2 and set Read Cycle Bit Note Please refer to the SI
26. Interface SPI interface register 0x41 read write 32 7 5 13 Clock Multiplier IC 515326 SPI interface register aaaiaaaiacaiasaiasaaannannnannnananannnnnannnnnannaai 34 JOE DAC C OBI OLET EE 35 Dee DAC PEERS ARES ENTRE mee 35 7 5 16 ADC Serial Interface SPI interface register aaaiaaaiaaaiasaianannnnnnnnannnannnainnannnainnanaaaalaaaaaaa 36 7 5 17 ADC Input Tap delay registers 0x49 aaiaaaiaaaiasaiasaaaasaaasatasanananananannnnnnnnnnnnnnnnnnnnnnnninnnnannnaai 37 7 5 18 Vittex 5 System Monitor registers aaiaaaiaaaaaaaiasainsnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnaai 37 EE br Kee EE 38 7 5 20 Memory Sample Start Address Actual Sample Address regtgterg 4 JL Sampie Lengih TES S Or eege eegen 42 1 3 22 RingDuiter Delay register eisai Diesen tasa intmd E Fannie du un Fat emen Fano Mata M du Iu manae kn Hin 42 7 5 23 Test Histogram Pattern Memory Address regigter 43 7 5 24 Test Histogram Pattern Memory Data Woteregtster 43 L323 Test ISTO OT ali E OBITOL Eed 44 7 5 26 SIS8900 RTM LVDS Test Input Output Control register aaaiaaaiiasaiasaiasaiasanasanasaaaaaaaaaa 45 7 5 27 Read DMA System Destination address lower 32bits eese 46 Page 3 of 67 SIS Documentation SIS8300 Seated innovative uTCA for Physics eme Digitizer 7 5 28 Read DMA System Destination address upper 32bits aaiaaaiasaiasaiassaasaaasasasatasatasaaasaaaaaaaaa
27. MA in 8byte steps 7 8 User Interrupt Interface The User Interrupt interface consists of the following signals user irg i i std logic user irq clear out std logic user irq User interrupt pulse input to the PCIe endpoint The connected logic has to supply a pulse of at least 1 clockperiod in length to trigger the interrupt logic If the driver user software has enabled the corresponding interrupt line an interrupt is generated on the PCIe interface user irq clear A 1 clock period wide pulse which is triggered when the driver software has serviced the issued interrupt in the interrupt service routine This pulse may be used to reset any logic that depends on user feedback through the software interface The interface is synchronous to the User Blockram DMA interface clock See 7 7 Page 55 of 67 Struck Documentation SIS8300 S innovative systeme uTCA for Physics Digitizer 8 RIM management Connected RTMs shall be compliant to the PICMG MTCA 4 specification in a way that they must have an on board PC EEProm on address 0x50 and a NXP PCF8574 compatible port expander on address 0x7C Required port expander connection map for normal operation PO Hot Swap Switch low active P6 PowerEnable low active The EEprom shall contain any relevant device information FRU records about the RTM refer to PICMG AMC 0 Additionally the EEprom shall contain the new record types defined in PICMG MTCA 4
28. RmetZD 10x3P FEM ERmetZD 10x3P FEM J76E ERmetZD 10x3P FEM 2 M un z 2 E a 2 8 E 3 a Ki Li 5 3 E Eb A i8 8 L lo EE LE AE az amp Z a z a Z la zc za za za z amp Z a za Zio z amp z a z a Z a z az je za za z PZ en Z m Le m Z d el el ii el Z m Ze Z geg P eps ega SEE Saa SEE sesa Fs fs EIE EE Eel x EE akak aaa ER B B EN seseeeee GSBOSBOSS B SEERE SEBER ER SEE EE EE EE EE EE Eh KE ers ER zr zeze z p s p EPA es Re FP l a Bi Li ES ieee F S EISE amp sek Se E EFE ER SE 5588 PAET g ss SEET BK LEEE g seeeesee z eeekesee REES EEE 2 Se DI Pp V D 4 D X Q p d J V Si S Y f lt z z x zx Ge E een Page 65 of 67 Struck Documentation 11 Index 12 V 61 3 3 V 61 8 bit 9 A 10 AC 63 AD9268 36 AD9510 32 ADC Sample Logic 14 Address Map 20 AdvancedMC 6 AMC 6 AMC 0 56 Appendix 61 arm 41 Atmega 13 Atmegal28 9 Atmel 7 9 AVR JTAG 9 binary 35 Block diagram 6 board layout 13 clock input 12 clock distribution 8 CON600 9 connector types 13 CRC 23 DAC 13 DAC range 35 DAC impedance 35 DC 63 design 6 DESY 5 ECC 23 ERNI 13 external register interface 53 FIFO Link 1 20 Link 2 20 firmware version 22 Firmware 14 Firmware Options register 25 Firmware upgrade 57 FPGA 6 front panel 11 FRU 56 functionality 6 Harlink 12 HARTING 13 IANA 56 IANA PEN 56 ICS853S057 30 IDT 30 impac
29. S8300_AD9510_SPI_ Setup routine as illustration and to the AD9510 documentation for details Page 33 of 67 Sd Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 13 Clock Multiplier IC SI5326 SPI interface register define SIS8300_CLOCK_MULTIPLIER_SPI_REG 0x42 Several parameters of the Clock Multiplier 815326 chip can be configured with the SPI serial Peripheral Interface Please refer to the documentation of the 515326 chip for details read Cmd Bit Write Read Logic BUSY Flag Cmd Bit 0 Reset Decrement or Increment Cmd BUSY Flag TL II Si53xx LOL Status de BAS INT CIB Status Instruction Byte Bit 7 Mm 8 Instruction Byte Bit 0 NN Address Data Byte Bit 7 Read Data Bit 7 MSB ef Read Data Bit 1 0 Address Data Byte Bit 0 Read Data Bit 0 LSB The power up default value is 0x0 Cmd Bit 1 Cmd Bit 0 CO Execute SPI Write Read Cmd o jt JjReeCmd S 0 JDeremmntCmd Reset Cmd generates an lus reset pulse Decrement Cmd generates an lus Skew Decrement pulse Increment Cmd generates an lus Skew Increment pulse Note INC DEC Time between consecutive pulses must be greater than 16ms Page 34 of 67 Sd Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 14 DAC Control register define SIS8300 DAC CONTROL REG 0x45 read C C sss s DAC DCM Reset pulse Ese KEE power down 1 power up TOR
30. Seabee Innovative systeme SIS Documentation SISS300 uTCA 16 bit Digitizer SIS8300 uTCA FOR PHYSICS Digitizer User Manual SIS GmbH Harksheider Str 102A 22399 Hamburg Germany Phone 4449 0 40 60 87 305 0 Fax 4 49 0 40 60 87 305 20 email info struck de http www struck de Version SIS8300 M 1402 1 V105 doc as of 17 10 2013 Page of 67 Seale innovative systeme SIS Documentation SISS300 uTCA for Physics Digitizer Revision Table Revision Date Modification S 1 00 02 1 2012 BasedonSIS8300 M 1102 2 V21 2 O Firmware V1400 add Firmware Option register add Memory Histogramming Feature add Harlink Connector Output Test Mode add SIS8900 RTM LVDS Test I O Control register 13 01 2012 Added DMA register description fixed reset register descr 16 03 2012 Fix of broken reference 03 28 09 2012 FW v1401 add IRQ register description add DAQ done IRQ add DAQ done DMA start signal chain add RAM FIFO debug register 19 12 2012 FW v1402 fixed MLVDS Bit7 Trigger enable bit added Register 0x205 bitO for byte swapped sample readout 1 05 17 10 2013 Fixed Sample Length Register description Added Firmware upgrade description Page 2 of 67 innovative SIS Documentation SIS8300 Table of contents Table Of content 3 rie Te E 5 1 1 Eltere geegent geet 5 Doa T E E E Ra a a R L 6 2 1 Functionality aaaiaaaiasaiasaiasan
31. alue SUM2 SUMI Where x P SUMI A Si EK x P sumG SUM Sj j x sumG The FIR filter logic generates the Trapezoidal by subtraction of the two running sums This implies that the internal value of the trapezoid is on average 0 A trigger output pulse is generated e GT is set GT the Trigger Out Pulse will be issued if the actual trapezoidal value goes above the programmable trapezoidal threshold value e GT is cleared LT the Trigger Out Pulse will be issued if the actual trapezoidal value goes below the negated programmable trapezoidal threshold value Page 40 of 67 Sd Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 20 Memory Sample Start Address Actual Sample Address registers define SIS8300 SAMPLE START ADDRESS CH1 REG 0x120 define SIS8300 SAMPLE START ADDRESS CH10 REG 0x129 If the Firmware Option register bit DUAL CHANNLE SAMPLING 0 then all 10 registers are used If the Firmware Option register bit DUAL CHANNLE SAMPLING 1 then only the first 5 registers are used The write function to these registers defines the memory start address The value is given in 256 bit blocks Write Function ADC chx Memory Sample Start Address 230 S reserved _ Memory Sample Start Address 256 bit blocks Memory Start Address 256 bit blocks 16 bit word address x 16 default after Reset 0x0 Explanation memory sample start address
32. asannnnnnnnnnnnnnnnannnannnnnnnnnnnnnnnnannnnnnnannnannnannnannnnnnnnnnnnnninnninnailnailnanlnanuaan 6 e bI a a a a 6 2 r l Ee EE 7 p ME D a o aE e E 8 Jamp r Connecctor EE 9 3 1 Ol INE C a E a a a a 9 Ge ere To S S 9 de DEE ANEN E EE 9 EE 10 4 1 Te RE E 10 LIMEN iudici E 10 4 3 eh TE CET 10 ENEE 11 5 1 Harlink LVDS DIS T L 12 A SMA lok 1 0 0 101 a ee 12 5 3 sinl 8 2110 cru T M 12 Boara Bon oD E 13 EE 14 7 1 ADE DE LO sd d a 14 Ta uou o RD TT 16 7 2 1 Memory Wirte Mri Ee 17 dod Memory Histogram Interface 18 VE Monon DoE E ene eter ER 19 p EE uu i EE 20 To Bo ar dN me 22 7 5 1 Module Id and Firmware Revision register deene eene ege BEES EE 22 T2 Sera IN Ulin TEOS O a terres tate r quM BI baer tI E Vete UD NAE l QUU M MUTA EHE 22 7 5 3 TN AREE ur EK 23 7 5 4 XILINX Vittex5 Error DetectiOl T6PIS e osos e erede roeken anina peni EEN AX UR Ue EENAA RENEE 23 7 5 5 Usercontol EE 24 7 5 6 PV Wy AO GONG TESSIE ee 25 7 5 7 ADC Acquisition ege 26 7 5 8 ADC Sample C EE EE EE 27 7 5 9 MEY DS Input Output Control register eege 28 7 5 10 Harlink Connector Input Output Control register aaaiaaaiaaaiasaiasa asanaasannsananananananananaaaaaanaaa 20 7 5 11 Clock Distribution Multiplexer controlregster 30 7 5 12 Clock Distribution AD9510 Serial
33. ation SIS8300 uTCA for Physics Digitizer systeme 7 2 1 Memory Write Interface The Write Interface consists of the following signals sis write fifo wr clk in std logic data write fifo sis write data fifo wr en in std logic sis write data fifo din in std logic vector 127 downto 0 sis write data fifo wr count out std logic vector 9 downto 0 address write fifo sis write addr fifo wr en in std logic sis write 64bit addr fifo din in std logic vector 31 downto 0 sis write addr fifo wr count out std logic vector 9 downto 0 A write cycle to the memory consists of one write command to the Address Fifo and two write commands to the Data Fifo One write command to the Address FIFO a valid sis write addr fifo wr en signal over one clock period sis write fifo wr clk along with sis write 64bit addr fifo din Two write commands to the Data FIFO a valid sis write data fifo wr en signal over two clock periods sis write fifo wr clk along with ais Write data fifo din When issuing a write command to the Address Fifo the second write command to the Data Fifo must be issued no more than one clock cycle later It is only allowed to write to the Address FIFO if sis write addr fifo wr count IS lower than X 1FF not full It is only allowed to write to the Data FIFO if sis write data fifo wr count is lower than X 3FE not full The Memory Controller writes with one write
34. channels share the same Memory Address Control Logic Logic needs more FPGA resources 2500 Registers 700 Slices Memory Dual Channel Copy To Memory Logic To The Single Channel Copy 10 BlockRams than the L NJ ONMdAVS T3NNVHO vna sDe J 14 OZLXO Boy Div 2107 sseJppy AOWA LHO ZHO sDe J 14 ach eyg ALUS sseJppy lqd po z SSeJppy Aowa K sbe 4 qu PZLXO Boy JD 2107 sseJppy Aow GHO OLHO SMeIS ONUOD 31507 Aiowaly 0 Adoxa urewoq 419 AdOO 10 ureuiop WO Aowa zyaad az EEP LUD OJI3 SYNG Eep LUD az EIEP CU M OU Jeung JBIEp ZUD ad Eep BUD EN edel lt IER BUD ody EeP OLUO EN oud 4ng EIS OLUO kat sbe 4 qu Aejag 325018 Jaynqbury YA SA4L L N3 AVT3Q S3dJn85NIH L NJ 32018 43991941 uieulop I2 LO sdpez sdo X sdoo Age I2 LOG V dnd 030 MO Lodv Aejap Sp p ejep 9jec Luo ousalu GZ LXZ LG MI J plouse1u seep L49 yoolg JaBBUL EES Si aging Je86u LUD Luo 20V 0 Aeleg yoo g 1ndu ejeg e p Sj p Sep zu9 Lu LOAV ED cu2 dobai gz v LG Ejep CC EH 4EJep ZUD xX9o g JeBBu asing JebBu zu cu ov UIEWOP I2 SOdV aye zx D 64D m elep GUD yoojg JeBBu L esing JeDDu 649 me sdyez sdos X sdoo Age 410 sov 4na 030 MO soav Aejap sx p ejep Y14 PIOYSSJY 1 ejep 6u2 ejqeuuuue15oud 0 Aeleg yoo g 1ndu eje GEES 0 LU9 6U9 coav
35. cycle 256 bits 4 x 64 bits to the Memory Therefore the lower 2 address bits of the written 64 bit address must be 0 and the next address will be incremented by 4 Page 17 of 67 Struck Documentation SIS8300 ae uTCA for Physics Digitizer systeme 7 2 2 Memory Histogram Interface The Histogram Interface consists of the following signals Histogramming address write fifo SIS wriLe hrsto addr rito clr zn std logic SIS write histo addr fifo wr clks ian std logic 315 write histo addr fifo wr en in std logic sis write histo 32bit addr fifo din in std logic vector 31 downto 0 sis write histo addr fifo wr count out std logic vector 9 downto 0 A write command to the Histogram Address Fifo will increment by one the content of the 32 bit Memory value addressed with the written 32 bit Memory Address It is only allowed to write to the Histo Address FIFO if sis write histo addr fifo wr count 1s lower than X 1FF not full The histogramming memory controller supports an update rate of 5MHz 20 MHz within one 2K memory page amid differing three lowest order bits Page 18 of 67 Struck Documentation 7 3 Memory buffer SIS8300 uTCA for Physics Digitizer Sd Innovative systeme The structure of the memory buffer with 512 MByte i e 4 x 1 GBit memory chips is illustrated below 012 MByte 4 x 64M x 16bit 256M x 16bit 32M x 128bit 16M x 256bit Memory 256 bit Block Addresses
36. dress 0x80000000 OxAFFFFFFF Repeated User DMA space 1GB Models Address 0x0 Ox3FFFFFFF DDR2 Memory readout Address 0x80000000 OxAFFFFFFF Repeated User DMA space Page 46 of 67 Struck Documentation SIS8300 4 innovative uTCA for Physics Digitizer systeme 7 5 30 Read DMA Transfer length define DMA_READ_LEN 0x203 This register holds the amount of data which is going to be transferred Bit DMA Transfer length 7 5 31 Read DMA Control define DMA READ CTRL 0x204 This register starts the Read DMA process and allows to poll the transfer status 31 mued 0 0 PENNE NNNM 1 mued 0 0 0 0 0 0 0 0 0 0 StatDMA DMA running 7 7 5 32 Readout DMA Sample byte swap define DMA READ BYTESWAP 0x205 This register allows swapping each byte in a sample for optimizing data handling on big little endian machines Example for disabled swapping Byte address offset Sample value 00 Sample 0 lo byte LSB 01 Sample 0 hi byte MSB 02 Sample 1 lo byte LSB 03 Sample 1 hi byte MSB Example for enabled swapping Byte address offset Sample value 00 Sample 0 hi byte MSB 01 Sample 0 lo byte LSB 02 Sample 1 hi byte MSB 03 Sample 1 lo byte LSB Page 47 of 67 Sd Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer read ee 0 Byteswap enable Byteswap enable status 7 5 33 Write DMA System Source address lower 32bits define DMA WRITE DST A
37. eme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 38 DAQ Done DMA Chain Control define DAQ DMA CHAIN 0x216 This register allows the chaining of the DAQ Done Signal into the DMA Start Signal read d use S 0 0 0 DAQ Done DMA Start Chain enable Chain enabled 7 5 39 IRQ Enable define IRQ_ENABLE 0x220 This register enables each interrupt source for interrupt generation The register is implemented as a J K register Disable User IRQ D Disable DAQ Done IRQ Oo unused Oo a a MM 8 mud 0 0 17 Disble Write DMA Done RO Ju Disable Read DMA Done IRQ Ju unused Enable Write DMA Done IRQ Write DMA Done IRQ enabled status Enable Read DMA Done IRQ Read DMA Done IRQ enabled status 13 mud Ji o Page 50 of 67 Sd Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 40 IRQ Status define IRQ STATUS 0x221 This register lists the latched interrupt bits for which an interrupt has been generated read 16 mud Ji User IRQ happened DAQ Done IRQ happened unused 2 uused iii Write DMA Done IRQ happened O junsed sf Read DMA Done IRQ happened 7 5 41 IRQ Clear define IRQ CLEAR 0x222 This register clears any handled interrupts an allows the logic to generate new interrupts 31 unused 10 O 0000 00 16 musel O User IRQ clear oO DAQ Done IRQ clear unused Write DMA Done IRQ clear Read DMA Done IRQ clear EN o unused
38. er Value 0x000000 g Select MAPAbort SelectMAP Abort Sequence Enable JA pede He GGG Property display level Advanced Display switch names Default a Page 57 of 67 Saeed innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 9 2 Create PROM file Select in the left IMPACT menu the item Create PROM File The following picture shows how to fill in the menu FB PROM File Formatter General File Detail Checksum Fill Value Configure Single FPGA Configure MultiBoot FPGA xcf32p 32 M iuis 102 sis8300 V 1402 Ix50 Source E BPI Flash eo V Configure Single FPGA Configure MultiBoot FPGA Flash PROM File Property _ Configure from Paralleled PROMs 7 File Format Generic Parallel PROM Enable Revisioni Enable Compression The PROM File Formatter will guide you through the steps to format bitstream BIT files into a PROM file that is compatible with Xilinx and third party PROM programmers The programmed PROM device can then be used to configure the target FPGA Additional capabilities of the PROM File Formatter indude Select the created PROM file and click on Generate File A TCE AADAC s Lot IMPAC INX F jj File Edit View Operations Output Debug Window Help DAR ane T w H a Boundary Scan 8 SystemACE Create PROM File PROM File Format WebTalk Data 0x0000_0000 DI xcf32p is83
39. gger_block ad Encryption Options g M1Pin Configuration Pin M1 Pull Up adc ch2 fir and threshold trigger block ad n x adc ch3 fir and threshold trigger block ad FY Gesetten Pul Up adc ch4 fir and threshold trigger block adj g ProgPin Configuration Pin Program Pull Up adc ch5 fir and threshold triager block adi g DonePin Configuration Pin Done Pull Up emm EM g InitPin Configuration Pin Init Pull Up gt CQ No Processes Running g CsPin Configuration Pin CS Pull Up Y Processes sis8300_top Behavioral g DinPin Configuration Pin Din Pull Up ER X Design Summary Reports g BusyPin Configuration Pin Busy Pull Up g y Design Utilities A 5 E t C Create Schematic Symbol g RdWrPin Configuration Pin RdWr Pull Up E View Command Line Log File g HswapenPin Configuration Pin HSWAPEN Pull Up View HDL Instantiation Template a rm g TckPin JTAG Pin TCK v User Constraints soris x dai QN Synthesize XST g TdiPin JTAG Pin TDI Pull Up View RTL Schematic g TdoPin JTAG Pin TDO Pull Up View Technology Schematic g TmsPin JTAG Pin TMS Pull Up C Check Syntax e g UnusedPin Unused IOB Pins Pull Down g UserID UserID Code 8 Digit Hexadecimal OxFFFFFFFF j J g DCIUpdateMode DCI Update Mode Ae Required En Analyze Design Using ChipScope g configFallback Fallback Reconfiguration Enable Watchdog Timer Mode Off g TIMER CFG TIMER USR Watchdog Tim
40. h the possibility to implement up to 256 32bit registers on the top level of the HDL design The registers are embedded into the devices regular register space from address 0x400 to Ox4FF The External register interface consists of the following signals reg O0x400 Ox4FF adr out std logic vector 7 downto 0 reg O0x400 Ox4FF wr data out std logic vector 31 downto 0 reg O0x400 Ox4FF rd data in std logic vector 31 downto 0 reg O0x400 Ox4FF wr en out std logic reg O0x400 Ox4FF rd en out std logic reg 0x400 Ox4FF adr Sbit wide addressbus which selects the next register to be read from or written to reg 0x400 Ox4FF wr data 32bit wide databus which holds the data to be written to the addressed register reg 0x400 Ox4FF rd data 32bit wide databus to which the user logic must provide the read data from the addressed register reg 0x400 OxAFF wr en Write enable pulse to indicate that a write request has been issued from the PCIe interface reg 0x400 OxAFF rd en Read enable pulse to indicate to that a read request has been issued from the PCIe interface The interface is synchronous to the User Blockram DMA interface clock See 7 7 See the following graphs on how the device expects user logic to interact with the interface Page 53 of 67 S device Inst register bank fsm reg 0x400 Ox4FF rd en 0 0 O int device Inst register bank reg 0x400 Ox4FF wr en 0 0 q P aS c C gt
41. imum peak to peak signal level of 3V into 50 Ohms The clock input signal is coupled to the internal logic via a capacitor The schematic of the input stage 1s shown below U200 PECL 1 6 IN OUT C200Y L 23 EXT CLKAO P 4 GND Lei VREF 5 2 EXT CLKAQ NAC pe 100nF m 21 EXT CLKAL P AC unn BAIL CLKAI gt 20 EXT CLKAL N 2 ET CKAN Uin max 3Vp p Rin 50 Ohm Impedanz 17 EXT CLKA2 P ACE pee 16 EXT CLKA2 N ZC Lupum ON200 SMA8400A 1 9000 SMA l CLK IN GND 3 3V GND D 3 3V 3 3V GND 3 3V GND GND ADCLK946BCPZ 5 3 SFP Card Cage The dual card cage can host two SFP link media They can be enabled in the sis8300top vhd VHDL code as shown below and are active in the Ox1102 firmware design e g DUAL_OPTICAL_INTERFACE_EN integer Communication is handled through registers 0x14 to 0x17 refer to the VHDL code Page 12 of 67 Struck Documentation SIS8300 Sn innovative uTCA for Physics Digitizer systeme 6 Board Layout A print of the silk screen of the component side 1s shown below S3 4 S5 S6 S7 S8 ERN ZH EH SEMIS F E m mlu mig img mg mE H dn mg imi I EBENEN F Ia az eli li ml kat Wa d ao AC ers fal e THE infa sr zi IE rius E TECUM oral e Se Sw Si RS M ES Mc MI Ge wescssesn e 9 DTN GmbH 03 2011 SIS8300 V2 www struck de III 299099029 Tal T4 46 ap T51 58 T l
42. it which location is 16 bit higher in the register An undefined toggle status will result from setting both the enable and disable bits for a specific function at the same time The only function at this point in time is user LED on off On read access the same register represents the status register 31 Clear reserved 15 9 0 30 Glarrsevedl4d 10 29 Clarrseved13 10 28 _ Clearreserved 12 t 0 27 Clearreserved 11 0 O 26 X Glarrsevedl0O 10 O 25 Clarrseved9 0 24 jClarrseved8 O 0 S O 23 Clarrseved7 0 22 Clearreserved6 0 O 21 Clearreserved5 10 O 20 Clarrserved4 0 19 Clearreserved3 0 O 18 Clarrseved2 JI 17 Switch off LED test 10 O 16 SwithoffuserLED Oe 9 JjSetrsevedO Status reserved9 O O Z 8 JSetreserved8 L iamsresenel 8 6 jSetrseved Status reserved6 4 _ Setreserved4 L tatusrmgesened Z _ _ O 2E 3 Status User LED 1 LED on 0 LED off denotes power up default setting Page 24 of 67 Wie Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 6 Firmware Options register define SIS8300_FIRMWARE_OPTIONS_REG 0x05 This register holds the information of the Xilinx firmware option features 0 fe m 9 esoe 8 _ FPGA SX IGByte Memory 6 DUAL OPTICAL INTERPACE EN 0 TRIGGER BLOCK EN FPGA SX IGByte Memory 0 Vir
43. ive systeme Finally the new firmware can be programmed into the select component notice watchdog settings 3 2 TCF AADAT ISE iMPACT P 68 ndar File Edit View Operations Output Debug Window Help DPAOEIXABSBBxXRS BK SBS RT SN iMPACT Flows O x SS BoundaryScan m Hi E sse3002V1402b60prommes fo x Cree CS M Lea E SystemACE i age Create PROM File PROM File Format 1 k eene 2 B WebTalk Data xcf32p xc5vlx50t Sis8300v2 v140 bypass mb Erase m Disnl hasl Page 60 of 67 Struck Documentation SIS8300 4 innovative uTCA for Physics Digitizer systeme 10 Appendix 10 1 Power Consumption The currents drawn by the SIS8300 are listed in the table below 100 mA These currents are typical values during normal operation They can vary depending on the loaded firmware design 10 2 Ordering options The available part numbers are listed in the table below Struck part number FPGA 04075 SIS8300 V2 with XCS5VLX50T 3FFGI136C 4 x 1 GBit To be defined XCSVLX110T 1 3FFG1136C 5 x GBit Note The V1 and V2 preseries cards are stuffed with the fastest available speed grade 3 A lower speed grade 1 version may be desirable for high volume applications when speed considerations are not an issue Page 61 of 67 Wine Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 10 3 RTM Zone 3 connectors J7
44. novative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 26 SIS8900 RIM LVDS Test Input Output Control register define SIS8300 RTM LVDS IO CONTROL REG OXIZE Read Ca MMM COS Enable RTM LVDS Output Bit D 11 ed MM NN 2 E 2 EH RTM LVDS Output Bit D 11 RTM LVDS Output Bit D 11 RTM LVDS Output Bit D 7 RTM LVDS Output Bit D 7 RTM LVDS Output Bit D 6 RTM LVDS Output Bit D 6 Sof RTM LVDS Input Bit DS Ao RTMLVDS Input Bit DI Oo JRTMLVDS Input Bit DO Page 45 of 67 Struck Documentation SIS8300 aa innovative uTCA for Physics Digitizer systeme 7 5 27 Read DMA System Destination address lower 32bits define DMA READ DST ADR LO32 0x200 This register holds the lower 32bits of the destination address in system memory into which the card will transfer data Bit Function System memory address lower 32bits 7 5 28 Read DMA System Destination address upper 32bits define DMA READ DST ADR HI32 0x201 This register holds the upper 32bits of the destination address in system memory into which the card will transfer data System memory address upper 32bits 7 5 29 Read DMA Card Memory Source address define DMA READ SRC ADR 1032 0x202 This register holds the 32bit source address in the cards address space which is used to select the data source which 1s read from Bit Card address space The address layout is 512MB Models Address 0x0 OxlFFFFFFF DDR2 Memory readout Ad
45. of 67 Sd Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 3 Jumper Connector Pin Assignments The following subsections describe the pin assignments of jumpers and connectors 3 1 CON100 JTAG The SIS8300 s on board logic can load its firmware from a serial PROM via the JTAG port on connector CON100 PCI Express or via the MMC Hardware like the XILINX HW USB JTAG in connection with the appropriate software will be required for in field JTAG firmware upgrades CON100 is a 2mm e metric 14 pin header that allows you to reprogram the firmware of the SIS8300 board with a JTAG programmer The pin out is shown in the schematic below It is compatible with the cable that comes with the XILINX HW USB II G JTAG platform cable CON100 can be found at the right bottom side of the board D 2 5V L CON JTAG TMS NES CON JTAG TCK 4 8 CON JTAG TDO 10 CON JTAG TDI Note 1 The board has to be powered for reprogramming over JTAG Note 2 The FPGA uses 8 bit parallel mode to load the firmware from the serial PROM Make sure to check the Parallel Load box in Impact when specifying the programming properties for the PROM 3 2 J604 Watchdog Reset J604 can be found next to the left upper edge of U500 largest chip on the card With J604 closed the boards watchdog reset is connected to the reset logic J604 should be opened for JTAG firmware programming 3 3 J32 AVR JTAG This 10 pin header is u
46. plane 7 5 11 3 Multiplexer C Input Signals U240 SelO and Sell MUXAB SEL Multiplexer C select lines 0 0 EXT_CLKBO Clock from Harlink Connector CI1 4 IN frontpanel 0 l ENT LKA J Clock from SMA Connector CLK IN frontpanel 1 O0 MUXACLKI Multiplexer A Output Signal 7 5 11 4 Multiplexer D Input Signals U250 SelO and Sell MUX2A SEL Multiplexer D select lines D 0 MUXACLKO Multiplexer A Output Signal 0 MUL CLK JClockMultplier U242 Output2Signal 1 O J EXTCLKBI Clock from Harlink Connector CI1 4 IN frontpanel Clock from SMA Connector CLK IN frontpanel 7 5 11 5 Multiplexer E Input Signals U251 Sel0 and Sell MUX2B SEL Multiplexer E select lines selected Input Net Name Clock source Description 0 0 MUXB CLKO Multiplexer B Output Signal 0 l MUL CLKO Clock Multiplier U242 Output 1 Signal 1 O ENT CLKB2 Clock from Harlink Connector CI1 4 IN frontpanel EXT CLKA2 Clock from SMA Connector CLK IN frontpanel Page 31 of 67 Wine Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 12 Clock Distribution AD9510 Serial Interface SPI interface register 0x41 read write define SIS8300_AD9510_SPI_REG 0x41 The parameters of the Clock Distribution IC AD9510 chips can be configured with the SPI serial Peripheral
47. sed to connect to the JTAG of the Atmel Atmegal28 microcontroller providing the IPMI MCH functionality of the SIS8300 ET GND O i TDO VIREF O TMS nSRST O O nc nIRST O TDI GND O Page 9 of 67 Wie Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 4 LEDs 4 1 AMC LEDs The AMC LEDs are implemented according to the standard 4 2 Front Panel LEDs The SIS8300 in Gigalink stuffing option has 4 green front panel LEDs Function in Gigalink design PCI Express Access User LED PCIe Link up ADC Sampling active 43 SMDLEDs A number of surface mount red LEDs are on the SIS8300 to visualize part of the board status D20A SI Firmware dependent SNE D20B S2 Firmware dependent TI TA ue D110A TX FAULT 2 Link 2 transmitter fault D110B RX LOS 2 Link 2 receiver loss of signal Page 10 of 67 Struck Documentation SIS8300 seabed innovative uTCA for Physics Digitizer systeme 5 Front panel The SIS8300 is a uTCA for Physics board A sketch of the front panel is shown below Page 11 of 67 Struck Documentation SIS8300 Seated innovative uTCA for Physics Digitizer systeme 5 1 Harlink LVDS In Outputs The Harlink LVDS Output and Input connectors have 5 signals each The Clock signal to the left hand side 1s marked with C and the other 4 signals are labelled with 1 4 5 2 SMA Clock Input The front panel SMA clock input is designed to accept a max
48. t 9 iMPACT 57 introduction 5 IPMI 7 9 J32 7 9 J604 9 Page 66 of 67 SIS8300 uTCA for Physics Digitizer Sd Innovative systeme J75 62 63 JTAG 9 13 20 AVR 9 over PCIe 23 register 23 Jumper 9 JYEBAO 13 LI 10 12 L2 10 12 LED 10 20A 10 A 10 D105A 10 D105B 10 D110A 10 D110B 10 D20B 10 D20C 10 D20D 10 D20E 10 D20F 10 D20G 10 D20H 10 D21D 10 LI 10 L2 10 test 24 U 10 user 24 LEDs AMC 10 Front Panel 10 SMD 10 Link 1 20 Link 2 20 LVDS 12 M 38 MCH 9 memory buffer 19 memory histogram interface 18 memory interface 16 memory write interface 17 microcontroller 7 9 MOLEX 13 MTCA 4 56 multiplexer A 31 multiplexer B 31 multiplexer C 31 multiplexer D 31 multiplexer E 31 NXP 56 ordering options 61 P 38 parallel load 9 PCF8574 56 PCI Express 6 PEN 56 PICMG 5 platform management 7 Power Consumption 61 PROM File 58 register ADC Acquisition Control Status 26 Struck Documentation ADC IOB delay 37 ADC Sample Control 27 ADC serial interface 36 clock distribution AD9510 SPI interface 32 clock distribution multiplexer control 30 Clock Multiplier IC SI5326 SPI interface 34 control 22 DAC control 35 DAC Data 35 Firmware Options 25 firmware revision 22 Harlink Connector Input Output Control 29 Memory Sample Start Address 41 MLVDS Input Output Control 28 module Id 22 ringbuffer delay 42 Sample Length 42 serial number 22 SIS8900 RTM LVDS Test Input Output Control register 45 Test Histogram Control
49. te pulse The address and write data bus change their values to the current selected register and the new 3 register address bus 8 bits wide register data 5 4 register data write bus 32 bits wide The write enable signal is pulsed for 1 clockperiod Q Be un Page 54 of 67 Struck Documentation SIS8300 4 innovative uTCA for Physics Digitizer systeme 7 7 User Blockram DMA Interface The User Blockram DMA interface consists of the following signals bram dma cik out std logic bram dma adr out std logic vector 31 downto 0 bram dma rd en out std logic Dram dma rd data in std logic vector 63 downto 0 bram dma clk Free running 125MHz clock to which the data and control signals are synchronous to bram dma adr 32bit wide addressbus which 1s mapped over the 512MB of onboard sample RAM The addresses ranges from 0x00000000 to Ox IFFFFFFF 512MB bram dma rd en Optional Read enable pulse for connected logic The read enable pulse is valid 1 clockperiod before the data 1s expected to be valid on the databus bram dma rd data 64bit wide due to PCIe endpoint design databus which holds the data to be transmitted over PCIe The data needs to be valid 1 clockperiod after ram dma rd en is valid Note This interface was built to be directly able to connect to a Xilinx CoreGen generated blockram module with a 64bit wide read bus Due to PCIe endpoint design constraints the user has to read the blockram via D
50. ter define SIS8300_CLOCK_DISTRIBUTION_MUX_REG 0x40 The SIS8300 has 5 IDT ICS853S057 clock multiplexer chips which are labelled A to E in the clock distribution schematic in section 2 4 The multiplexer control register holds the two select bits for the 5 multiplexer chips as shown in the table below The assignment of the inputs to the resources ie clock inputs is listed in subsection 7 5 11 1 FFFFFO000 11 10 MUXE_SEL Multiplexer E select bits 00000C00 no 9 8 MUXD SEL Multiplexer D select bits 00000300 Eum quem KR 000000C0 5 MUXC_SEL Multiplexer C select bits 00000030 3 2 MUXB_SEL Multiplexer B select bits 0000000C 1 0 MUXA SEL Multiplexer A select bits 00000003 Page 30 of 67 Sd Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 11 1 Multiplexer A Input Signals U222 Sel0 and Sell MUXIA SEL Multiplexer A select lines Clock source Description D 0 RTMCLKO Clock2 from pRTM card 0 1 TCLKRBO Clock2 Telecom Clock B from AMC Connector Backplane 1 0 J TCLKA0 J Clock 1 Telecom Clock A from AMC Connector Backplane Onboard Clock chip 250MHz 7 5 11 2 Multiplexer B Input Signals U223 Sel0 and Sell MUXIB SEL Multiplexer B select lines O 0 RTMCLK Clock2 from uRTM card 0 l TCLKBI jClock2 Telecom Clock B from AMC Connector Backplane 1 0 TCLKA Clock Telecom Clock A from AMC Connector Back
51. ter defines the Write Address of the Test Histogram Pattern Memory 4Kx28 11 0 default after Reset 0x0 7 5 24 Test Histogram Pattern Memory Data Write register define SIS8300_TEST_HISTO_MEM DATA WR Ox 12D The write function to this register writes the data to the Test Histogram Pattern Memory 4Kx28 Bit 31 28 default after Reset 0x0 Page 43 of 67 Sd Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 25 Test Histogram Control register define SIS8300_TEST_HISTO_CONTROL Ox12E Read Test Histogram Control Bit 1 Test Histogram Control Bit 0 Copy Logic Busy Flag 238 seng e LLL 17 reserved o G O 16 reserved sss Copy Length Bit 15 Read Copy Length Bit 15 MSB Copy Length Bit 1 Read Copy Length Bit 1 0 Copy Length Bit 0 Read Copy Length Bit 0 LSB The power up default value is 0x0 Control Bit Control Bit 0 GE M LLNRLLRLAS M ODE Copy Length 1 values from Test Histogram Pattern Memory start with addr 0 to the Histogram Fifo Continuously histogramming of ADC channel 1 and 2 average of 128 values every 125 128 us Histogram of Channel 1 Byte addr 0x0 Ox3ffff 64K Histogram of Channel 2 Byte addr 0x40000 0x7ffff 64K Continuously histogramming of Coincidence channel 1 channel 2 average of 128 values every 125 128 us Coincidence Histogram 256 x 256 Byte Addr 0x0 0x3 ffff 64K Page 44 of 67 Sd In
52. tex 50LX50T and 512 MByte Memory FPGA SX IGByte Memory 21 Virtex 508X50T and 1 GByte Memory Page 25 of 67 Struck Documentation SIS8300 S innovative systeme uTCA for Physics Digitizer 7 5 7 ADC Acquisition Control Status register define SIS8300_ACQUISITION_CONTROL_STATUS_REG 0x10 read 21 E ee EB S exc NN 7 Z Staas DDR Memory Init OK 5 Status internal Sample Logic Buffer FIFO Not Empty MM ED Reset Sample Logic Start with next trigger Wait for trigger NE CLE Arm and Start Trigger The power up default value is 0x0 Page 26 of 67 Sild Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 8 ADC Sample Control register define SIS8300_SAMPLE_CONTROL_REG Ox 1 ADC channels can be disabled from storing data to memory by setting the corresponding disable bit in this register write PEN PEN 9 DisabeSamplingChlO 00 g 8 Disable Sampling Ch9 Disable Sampling Ch3 Disable Sampling Ch2 Disable Sampling Chl The power up default value is 0x0 6 o Page 27 of 67 Sd Innovative systeme Struck Documentation SIS8300 uTCA for Physics Digitizer 7 5 9 MLVDS Input Output Control register define SIS8300 MLVDS IO CONTROL REG 0x12 Read Enable LVDS Output Bit 7 Enable LVDS Output Bit 7 Enable LVDS Output Bit 6 Enable LVDS Output Bit 6 a BEE uuu BE iii 9 LVDS Input 1 External Trigger Enable LVDS Input
53. tion SIS8300 uTCA for Physics Digitizer 7 5 19 Trigger registers The Trigger Block contains Logic to generate internal triggers only implemented if the Firmware Option register bit TRIGGER_BLOCK_EN 1 Two types are implemented A threshold trigger and a FIR trigger 7 5 19 1 Trigger setup registers define SIS8300_TRIGGER_SETUP_CH1_REG Ox100 define SIS8300_TRIGGER_SETUP_CH10_REG 0x109 These read write registers hold the 8 bit wide trigger pulse length 1n sample clocks the Peaking and Gap Time of the trapezoidal FIR filter Gap Time SumG Time Peaking Time C Trigger Pulse Length SumG time only FIR trigger LD jSumGbit4 time between both sums 9 mum 8 SumGbit0 Z 0D 6 reserved Peaking time P only FIR trigger 5 reserved 00000 4 Pi x P t si ju 0 PbitO The power up default value reads Ox 00000000 Si Sum of ADC input sample stream from x to x P Page 38 of 67 Struck Documentation SIS8300 4 innovative uTCA for Physics Digitizer systeme P Peaking time number of values to sum SumG SumGap time distance in clock ticks of the two running sums The maximum SumG time 16 clocks The minimun SumG time 1 clocks Values gt 16 will be set to 16 Value 0 will be set to 1 The maximum Peaking time 16 clocks The minimun Peaking time 1 clocks Values gt 16 will be set to 16 Value 0 will be set to 1
54. u k e qeurue6o4d D Aowa LL sBe 4 qu asing 6u Lyd Luo 20 o Kejaq e DENEN xolg indui N cd D t AERP SADE CEPS Ge FT oh 9 LZ en Bey pp er oes a9 Zu MIJ PIouseJu 7 9180 ssappy Ere E Bee pee Eep CUD DIE Zu yoolg UL ag HP UO O Kowa zH2 Sea asing 1e66u zuo cuo OQdv O c 2 Co 2 ONEN d wO A NUM O cO un ejeg Aowa O gt in Un E on eee esc Q p Un a sseippv HA b9 ureuiop 419 GOAY UT 5 ED 74 sseuppy Lous sdg XE dooz eeg g S WC 620v using lt 3 S 030 HII sav Q E 5 elep sy p ejep GC TD ec LX0O Bay uppy 3429 GI als PloYyseJy j n EIER BUD o O eer x Jemp GUO ei eyep BUD LEET voy span EE A 649 DAY y 8 mm Re Kowa BHO sBe 4 qu es ng 186641 649 0 Kejeg o 9 41 pu Ur O Q D elap ep p ejep eq EE 0142 649 SOdY Z ez Lan Bey Jppy ez Lx Lo Ooo Lll 4 018 OUD oU Jung E CH L 2 21607 sse1ppy T EN K vam H da BIEP OLUD xoo g 4e88u T Byep oiu OD Q Kowa OLHO gelaf es ng 1e55u 0142 OLU ody n c Keleg 12018 Oo gt QJ Eb Jeynqbury YA SANYL Q 3 gt us snyeyou05 O Q Ka 21607 Aowa 03 Ado Sn IV rum CS 043u02 alduge O rm lt e ureurog 419 AdOO 10 ureuop HID Aowa ZYAA seb jeurex t 3 u rs R KL o En SNIRIG JONUOD eld e x Q c3 Un N N R 4 R innovative SIS8300 uTCA for Physics Struck Documentation systeme Digitizer The block diagram shows the ADC data handling Two ADC
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