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Avme9630/9660 Industrial I/O Pack User`s Manual
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1. A B C D E F G H PIN 50 OF P1 amp P2 CONNECT 1 P2 GROUND SHIELD p4 56 5d P2 P1 49 49 TO 48 48 AVME9630 9660 F MODEL 5025 552 47 47 CARRIER BOARD 1 0 TERMINATION 46 46 P3 OR P4 P5 P6 PANEL 45 45 44 44 45 45 X s 2 FEE 40 40 TOP VIEW 39 39 38 38 37 37 36 36 35 35 34 34 STRAIN 50 PIN 5 55 RELIEF RIBBON CABLE BLACK LINE ON CABLE CONNECTOR s 1004 534 2002 261 INDICATES PIN 50 1004 512 3 30 i 30 29 29 28 28 ES 27 27 E 26 26 S 25 25 SS 24 24 SS 23 25 Ss 22 22 SS POLARIZING 21 21 SS KEY 20 20 Ss 4 19 19 S 18
2. A B T D E F G H ACCESS PULSE FPGALOGCO 1 LED STRETCHER CONTROL BUS 1 P3 P7 Gans A CARRIER l 556 15 status e REGISTER ADDRESS MODIFIERS P1 ee DS DS1 Ded T I INTERRUPT Agni IPA B07 BD8 LEVEL LWORD FIELD lt gt IP MODULE A 3 l REGISTER WRITE 5015 800 x vo NIREQQA tas 5 SYSRESET xm 807 800 wp error m D7 R POW et 541 Pow REGISTER 5 2 E Sappy eit 4 jej AA FILTERS 12v 5 lacte ators TEN IP MEMORY DATA IACKIN D pe POED le ENABLE TRANSFER IACKOUT P4 P8 PT Dla RESET REG
3. A B Cc D E F G H A 1 T TOUT gt ok gt 2 2 B D C B A 3 3 92 F 4 4 ADDRESS DECODE JUMPER BLOCK J1 gt E EHEEREAE ER HEEREERE 5 5 1 h 5 MODEL AVME9630 MODEL AVME9660 ADDRESS DECODE BASE ADDRESS PROGRAMMING JUMPER BLOCK J1 ADJACENT PINS OF JUMPER JI F400 1 REPRESENT THE UPPER 6 BITS OF THE 28 BASE ADDRESS A JUMPER PRESENT ifs REPRESENTS A BIT VALUE OF 1 A reco RRB A JUMPER REMOVED REPRESENTS A BIT aras fe pesca sar eB VALUE OF 9 rea Hc piss lest Loe oe ALL PRESENT AVME9630 966 JUMPER amp IP LOCATIONS j D 2 4501 450 BE A B C D E F G H A B C D E F G H B 1 FLAT HEAD i i SCREW i I l N
4. 10 GENERATING INTERRUPTS sese 11 Interrupt Configuration Example 11 Sequence of Events for an Interrupt 11 4 0 THEORY OF 11 CARRIER BOARD OVERVIEW 11 VMEbus Interface eene 11 Carrier Board 12 IP Logic Interface wee 12 Carrier Board Clock Circuitry 12 Read and Write Cycle Timing 12 VME Interrupter w 12 Power Failure Monitor ES 13 Assess LEDs and Pulse Stretcher Circuitry us 13 Power Supply Filters 13 5 0 SERVICE AND 13 SERVICE AND REPAIR ASSISTANCE 13 PRELIMINARY SERVICE PROCEDURE 13 6 0 5 5 13 GENERAL SPECIFICATIONS ie 13 VMEbus 14 INDUSTRIAL PACK COMPLIANCE 14 APPENDIX eder iiy eR eee ee Oa te ede 15 CABLE MODEL 5025 550 15 CABLE MODEL 5025 551 i 15 TERMINATION PANEL MODEL 5025 552 15 TRANSITION MODULE MODEL TRANGS GP
5. VMEbus INTERFACE CONFIGURATION Address Decode Jumper Configuration VMEbus Address Modifiers sssse Interrupt Configuration 5 Carrier Field I O Connectors modules A D IP Field I O Connectors IP modules A D IP Logic Interface Connectors IP modules A D VMEbus Connections eene POWER UP TIMING AND LOADING DATA TRANSFER FIELD GROUNDING CONSIDERATIONS 3 0 PROGRAMMING INFORMATION MEMORY MAPS Identification PROM Carrier Board Status Interrupt Level IP Error Register TE IP Memory Enable IP Memory Base Address amp Size Registers QD cO cO Oo O0 000 OO OO O10101010101 I 3 33 3 3 00 00 00 IO ID IP Interrupt Enable Register E 10 IP Interrupt Pending Register 10 IP Interrupt Clear 10 GENERAL PROGRAMMING CONSIDERATIONG 10 Board
6. 18 INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS D E F G H A B C D 1 125 48 49 50 123 48 49 50 125 48 49 50 123 48 49 50 CONNECTORS 1 ON PC BOARD MODEL TRANS GP MODULE SCHEMATIC CONNECTORS 1253 48 49 50 123 48 49 50 125 48 49 50 1253 48 49 50 oN FRONT PANEL A B C D 2 TOP VIEW 2 lt 9 19 233 4 gt A gt o W H H p Hd p t 3 3 3 15 i o i TT 3 36 80 0 E m v8 y 85 1 N p Hd p q 4 i HII Of uUlui ilt t m pg 4 Y ay co a o rH rH il
7. p q p q Y FRONT VIEW 5 5 0 78 e 2 8 19 8 ar B ar lt 10 31 261 9 6 6 TRANS GP MECHANICAL DIMENSIONS AND SIMPLIFIED SCHEMATIC Acromag pexemri muri NOTE DIMENSIONS ARE IN INCHES MILLIMETERS ks MEE TRANSITION MODULE D AVME Tor me 4501 465 Ag A B 5 D E F G H THIS SPACE LEFT BLANK 19
8. 15 DRAWINGS Page 4501 450 AVME9630 9660 JUMPER amp IP LOCATIONS 16 4501 434 MECHANICAL ASSEMBLY DRAWING 16 4501 451 AVME9630 9660 BLOCK DIAGRAM T 17 4501 462 CABLE 5025 550 NON SHIELDED 17 4501 463 CABLE 5025 551 SHIELDED ay 18 4502 106 TERMINATION PANEL 5025 552 m 18 4501 465 TRANSITION MODULE TRANS GP 19 IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall System design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility 1 0 GENERAL INFORMATION The AVME9630 9660 Series of VMEbus cards are carriers for the Industrial Pack IP mezzanine board field I O modules The carrier boards facilitate a modular approach to system assembly since each carrier can be populated with any combination of analog input output and digital input output IP modules Thus the user can create a board which is customized to the application which saves money and space a single carrier board populated with IP modules may replace several dedicated function VMEbus boards The AVME9630 9660 non intelligent carrier boards provide impressive functionality at low cost
9. Each IP contains an identification ID PROM that resides in the ID space per the IP specification This area of memory contains 32 bytes of information at most Both fixed and variable information may be present within the ID PROM Fixed information includes the IPAC identifier model number and manufacturer s identification codes Variable information may include unique information required for the module The identification Section for each IP module is located in the carrier board memory map per Table 3 1 ID PROM bytes are addressed using only the odd addresses in a 64 byte block The ID PROM contents are shown in Table 3 2 for a generic IP Refer to the documentation of your IP module for specific information Table 3 2 Generic IP Module ID Space Identification ID PROM Hex Offset From ID PROM ASCII Numeric Character Value Field Equivalent Base Address Description All IP modules have Not Used Revision 00 Reserved Not Used Driver ID Low Not Used Driver ID High Total Number of ID PROM IP Specific Space yy Not Used Notes Table 3 2 1 The IP model number is represented by a two digit code within the ID PROM e g the IP405 model is represented by 01 Hex Carrier Board Status Register Read Write Base C1H The Carrier Board Status Register reflects and controls functions globally on the carrier board MSB LSB D7 DO ACE Not Not Soft GIP Not Not Used Used Reset
10. Models are available in two standard VMEbus sizes 3U and 6U with support for up to two and four IP modules respectively MODEL VMEbus Supported Operating Board Size IP Slots Temperature Range AVME9630 2 A amp B 0 to 70 C AVME9660 4 A B C D 0 to 70 C AVME9630E 2 A amp B 40 to 85 C AVME9660E 4 A B C D 40 to 85 C INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS KEY AVME9630 9660 FEATURES Interface for Two or Four IP Modules Provides an electrical and mechanical interface for up to four industry standard IP modules IP Modules are available from Acromag and other vendors in a wide variety of Input Output configurations to meet the needs of varied applications Provides Full IP Data Access Supports accesses to IP input output memory and ID PROM data spaces Full IP Register Access Makes maximum use of logically organized programmable registers on the carrier boards to provide for easy configuration and control of IP modules The only hardware jumper settings required on the carrier boards set the base address of the card in the VMEbus short I O space LED Displays Simplify Debugging Front panel LED s are dedicated to each IP module to give a visual indication of successful IP accesses Front Panel Connectors Access Front panel access to field I O signals is provided via industry standard 50 pin headers A separate header is provided for each IP module All hea
11. X Shielded Cable or Model 5025 550 X Non Shielded Cable A Flat 50 pin cable with female connectors at both ends for connecting AVME9630 9660 or other compatible carrier boards to Model 5025 552 termination panels The unshielded cable is recommended for digital I O while the shielded cable is recommended for optimum performance with precision analog I O applications Termination Panel Model 5025 552 DIN rail mountable panel provides 50 screw terminals for universal field I O termination Connects to Acromag AVME9630 9660 or other compatible carrier boards via flat 50 pin ribbon cable Model 5025 550 X or 5025 551 X Transition Module Model TRANS GP This module repeats field I O connections of IP modules A through D for rear exit from the card cage It is available for use in card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth Connects to Acromag Termination Panel 5025 552 from the rear of the card cage and to AVME9630 9660 boards within the card cage via flat 50 pin ribbon cable within the card cage cable Model 5025 550 X or 5025 551 X INDUSTRIAL I O PACK SOFTWARE LIBRARY Acromag provides an Industrial I O Pack Software Library diskette Model IPS
12. termination panel 1 50 correspond to P2 pins 1 50 on the Industrial I O Pack IP Each Industrial I O Pack IP has its own unique P2 pin assignments Refer to the IP module manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 464 Field Wiring 50 position terminal blocks with screw clamps Wire range 12 to 26 AWG Connections to AVME9630 9660 P1 50 pin male header with strain relief ejectors Use Acromag 5025 550 x or 5025 551 x cable to connect panel to VME board Keep cable as short as possible to reduce noise and power loss Mounting Termination panel is snapped on the DIN mounting rail 15 Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 100 C Storage Temperature 40 C to 10056 Shipping Weight 1 25 pounds 0 6kg packed TRANSITION MODULE MODEL TRANS GP Type Transition module for AVME9630 9660 boards Application To repeat field I O signals of IP modules A through D for rear exit from VME card cages This module is available for use in card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth Connects
13. 18 SS 17 17 Ss 14 14 SS S 13 13 E 12 12 11 11 50 PIN bw 10 19 CONNECTOR 9 9 1004 512 PIN 1 TU TON CABLE 8 8 NO MARKINGS STRAIN RELIEF i 7 7 1004 534 6 6 5 5 FRONT VIEW 4 4 3 3 NOTE SEVEN DIGIT PART NUMBERS ARE 2 2 ACROMAG PART NUMBERS 1 1 Y e MODEL 5025 551 x SCHEMATIC 5 Acromag seres x tater CABLE 5025 551 x SHIELDED MODEL 5025 551 x SIGNAL CABLE SHIELDED S SHIELDED A B C D E F G H A B C D E F H 125456 7 8 9 10111213 1415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P1 12345678 910112151415 16 17 18 19 20 2122 2524 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 4445 46 47 4849 50 81 MODEL 5025 552FLK TERMINATION PANEL SCHEMATIC A 3 P1 TERMINATION p PANEL ACROMAG PART NUMBER 4001 107 272 69 0 TB1 oooo0oo0o0o000o0020 00 3 6 9 2H 8 21 M 27 30 39 35 42 45 48 DD DBODBOBODBDOBODO 4 2 5 8 T nw 7 2 2 25 2 32 35 B 4 4 opnooopnoooooDoOOODO Y 1 4 7 0 6 9 2 25 B 31 M S7 B 46 9 3 ts J SIDE VIEW 93 1 TOP VI NOTES 5 DIMENSIONS ARE IN INCHES MILLIMETERS TOLERANCE 40 020 40 5 mE MODEL 5025 552FLK TERMINATION PANEL 6 o Acromag festa ET war es Em cor t ENGINDOC DRIVE FRONT VI EW MF MODEL 5025 552FLK TERMINATION PANEL PROGRAM P CAD 2006 SCH FILENAME 4502106ASCH pe 101 4502 106 A A B Cc D E F G H
14. Space 4 Low Byte 017F IP B 0181 Base Address Hex 0 00CO J Not Used 00 0100 IPB Space 017E High Byte ID Space 4 0180 J Not Used 01BE Low Byte 01BF 01C0 01C1 i Not Used Not Used 01FE 01FF 0200 0201 l Not Used Not Used 4 03FE 03FF Table 3 1B AVME9660 6U Carrier Bd Short I O Memory Map INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS Base Address Base Address EVEN Byte ODD Byte Hex D15 D08 D07 DOO Hex 0000 IPA IPA 0001 I O Space Space 007E High Byte Low Byte 007F 0080 IPA 0081 E Lo v byte 0 00 Low Byte OOBF 0060 Carrier Board 00C1 4 Not Used Registers l 00 See Table 83 10 OOFF 0100 IPB IPB 0101 4 Space Space 4 017E High Byte Low Byte 017F 0180 IPB 0181 4 Not Used ID Space 4 01BE Low Byte 01BF 0160 0161 l Not Used Not Used 4 01FE 01FF 0200 IPC 4 I O Space 027E High Byte ID Space 4 0280 Not Used Low Byte 02BF 02C1 Not Used Not Used 02FE 02FF 0300 IP D IP D 0301 Space Space 4 037E High Byte Low Byte 037F 0380 IP D 0381 E Lo y byte 0 03BE Low Byte 03 0360 0361 l Not Used Not Used RE 03 0201 Space 4 Low Byte 027F IPC 0281 02BE 02C0 The Input Output 1 and Identification ID spaces of each IP are accessible via the VMEbus Short I O space as shown in Tables 3 1A and 3 1B The carrier bo
15. Status Register The carrier board then waits for an interrupt acknowledge from the VMEbus host after asserting the appropriate VMEbus interrupt request When the carrier board recognizes an interrupt acknowledge cycle on the VMEbus it checks for a match of the IP interrupt requests If none is pending or the interrupt level does not match it will pass the acknowledgment signal along without consuming it If there is a match the carrier board will initiate an acknowledgment cycle with the requesting IP which must supply the interrupt vector during the cycle The VMEbus interrupt acknowledge signal is consumed by the carrier board during a valid cycle Note that if multiple IP interrupt requests are pending then the carrier board will prioritize the requests and handle them in order Interrupt Configuration Example 1 Clear the global interrupt enable bit in the Carrier Board Status Register by writing a 0 to bit 3 2 Write interrupt vector to the location specified on the IP and perform any other IP specific configuration required do for each supported IP interrupt request 3 Write to the Interrupt Level Register to program the desired interrupt level per bits 2 1 0 4 Write 1 to the IP Interrupt Clear Register corresponding to the desired IP interrupt request s being configured 5 Write 1 to the IP Interrupt Enable Register bits corresponding to the IP interrupt request to be enabled 6 Enable interrupts from the
16. connectors are made by the specific IP model used and correspond identically to the pin numbers of the front panel connectors IP Logic Interface Connectors IP modules A through D The logic interface sides of IP modules A through D mate to connectors P11 P14 P13 amp P14 are not used on Model AVME9630 respectively on the carrier board IP location is silk screened on the board for easy identification Field and logic side connectors are keyed to avoid incorrect assembly P11 P14 are 50 pin male plug header connectors These AMP 173280 3 connectors mate to AMP 173279 3 connectors or similar on the IP modules This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers supplied with Acromag IP modules provide additional stability for harsh environments see Drawing 4501 434 for assembly details Pin assignments for these connectors are defined by the IP module specification and are shown in Table 2 2 Table 2 2 Standard IP Logic Interface Connections P11 P14 Pin Description Number Pin Description Number DOO 4 Do2 6 Do4 8 Dos 9 Do 10 f os 35 5 t j L 0 L3 e 7 m e m a s f o f mme ae Om 43 INTRegi 44 Bs 20 45 STROBE 46 2v 22 47 Asterisk is used to indicate an active low signal BOLD ITALIC Logic Line
17. information on our many isolated signal conditioning products that could be used to interface to the IP input output modules 3 0 PROGRAMMING INFORMATION This Section provides the specific information necessary to operate the AVME9630 9660 non intelligent carrier boards The board is addressable on 1K byte boundaries in the Short I O A16 Address Space This Acromag VMEbus non intelligent slave carrier board has a Board Status register but no ID PROM ID PROM s are provided per the Industrial I O Pack logic interface specification on the mezzanine IP boards which are installed on the carrier The 1K byte of memory consumed by the board is composed of blocks of memory for the I O and ID spaces of up to four IP modules The rest of the 1K byte address space is unused or contains registers or memory specific to the function of the carrier board The memory map for AVME9630 and AVME9660 are shown in Tables 3 1A and 3 1B respectively Note that the memory maps for the two models are identical for IP modules A and B and the control register locations The AVME9630 does not contain IP modules C or D MEMORY MAPS Table 3 1A AVME9630 3U Carrier Bd Short Memory Base EVEN Byte ODD Byte Address D15 D08 D07 DOO Hex 0000 IPA IPA 0001 4 l O Space Space 007 High Byte Low Byte 007F 0080 IPA 0081 Not Used ID Space OBE Low Byte OOBF Carrier Board 00C1 Registers 4 See Table 3 1C o0FF IP B 0101 I O
18. 16 D16 D08 O IP Module I O Space A16 D16 D08 EO IP Module Memory Space A24 D16 D08 EO Supports Short I O Address Modifiers Supports short A16 address modifiers 29H 2DH H Hex Short I O space is used for all carrier registers and IP module I O and ID spaces The carrier board base address is set by hardware jumpers and decoded on 1K byte boundaries Supports Standard I O Address Modifiers Supports standard A24 address modifiers 39H 3DH H Hex Standard address space is used when an IP supports memory space The carrier board is configured using programmable registers to set the IP starting address and size 1Mbyte to 8Mbytes Supports Read Modify Write Cycles Carrier board supports VMEbus read modify write cycles Interrupt Support 1 7 interrupter D16 D08 O Up to two interrupt requests are supported for each IP module The VMEbus interrupt level is software programmable Carrier board software programmable registers are utilized as interrupt request control and status monitors Interrupt release mechanism is Release On Register Access RORA type SIGNAL INTERFACE PRODUCTS See Appendix for more information on compatible products This IP carrier board will mate directly to all industry standard IP modules Acromag provides the following interface products all connections to field signals are made through the carrier board which passes them to the individual IP modules Cables Model 5025 551
19. 200mS after power up thus inhibiting any data transfers from taking place IP control registers are also reset following a power up sequence disabling interrupts etc see Section 3 for details DATA TRANSFER TIMING VMEbus data transfer time is measured from the falling edge of DSx to the falling edge of DTACK during a normal data transfer cycle Typical transfer times are given in the following table Data Transfer Time All Carrier Registers 500 nS Typical IP Registers 750 nS Typical If No Wait States See IP module specifications for information on wait states IP module register access time will increase by the number of wait states multiplied by 125nS the period of the 8 MHz clock FIELD GROUNDING CONSIDERATIONS Carrier boards are designed with passive filters on each supply line to each IP module This provides maximum filtering and signal isolation between the IP modules and the carrier board However the boards are considered non isolated since there is electrical continuity between the VMEbus and the IP grounds Therefore unless isolation is provided on the IP module itself the field I O connections are not isolated from the VMEbus Care should be taken in designing installations without isolation to avoid ground loops and noise pickup This is particularly important for analog I O applications when a high level of accuracy resolution is needed 12 bits or more Contact your Acromag representative for
20. A through D may have up to two requests Note that the Global Interrupt Enable bit in the Carrier Board Status Register must be set for interrupts to be enabled from the carrier board The user must also configure the VMEbus interrupt level using the Interrupt Level Register If multiple IP interrupt sources are enabled they will be serviced in order from highest to lowest priority with bit O IP A IntO having the highest priority and bit 7 IP D Int1 having the lowest priority IPC IPB IPB Int1 IntO Inti IntO Ena Ena Ena Ena MSB D7 Lowest Priority IPA Int1 Ena Bits not used on AVME9630 Where Bits Writing a 1 to a bit enables interrupts for IP Interrupt Enable the corresponding IP module and interrupt Read Write level A zero disables the corresponding interrupt Reset Condition Set to 0 IP interrupts disabled IP Interrupt Pending Register Read Base E3H The IP Interrupt Pending Register is used to individually identify pending IP interrupts If multiple IP interrupts are pending they will be serviced in order from highest to lowest priority with bit 0 IP A IntO having the highest priority and bit 7 IP D Int1 having the lowest priority IPD IntO Pend IP C Int1 Pend IntO Pend IP B Inti Pend IP B IntO Pend IPA Inti Pen d Bits not used on AVME9630 Where All Bits A bit will be a 1 when the corresponding IP Interrupt Pending IP i
21. Acromag 4M Series AVME9630 9660 Industrial I O Pack VMEbus 3U 6U Non Intelligent Carrier Boards USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 1994 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 482 9 INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc Table of Contents Page 1 0 GENERAL KEY AVME9630 9660 FEATURES ss VMEbus INTERFACE FEATURES sess SIGNAL INTERFACE PRODUCTS ius INDUSTRIAL I O PACK SOFTWARE LIBRARY 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION e CARD CAGE BOARD
22. COMPONENT SIDE OF IP MODULE i i I 2 2 THREADED M2 gt 8 il B COMPONENT SIDE SPACER i i OF CARRIER BOARD Sai l l r1 iru at ho h E l P1 CONNECTOR FRONT 5 zd 5 CONNECTOR ca E s Ye mxs PAN HEAD SCREW ASSEMBLY PROCEDURE 1 THREADED SPACERS ARE PROVIDED IN TWO DIFFERENT LENGTHS 4 THE SHORTER LENGTH IS FOR USE WITH AVME 9650 9660 CARRIER 4 BOARDS SHOWN CHECK YOUR CARRIER BOARD TO DETERMINE ITS REQUIREMENTS MOUNTING HARDWARE PROVIDED MAY NOT BE COMPATIBLE WITH ALL TYPES OF CARRIER BOARDS 2 INSERT FLAT HEAD SCREWS ITEM A THROUGH SOLDER SIDE OF 4 IP MODULE AND INTO HEX SPACERS ITEM B AND TIGHTEN 4 PLACES UNTIL HEX SPACER IS COMPLETELY SEATED 3 CAREFULLY ALIGN IP MODULE TO CARRIER BOARD AND PRESS TOGETHER UNTIL CONNECTORS AND SPACERS ARE SEATED 4 INSERT PAN HEAD SCREWS ITEM C THROUGH SOLDER SIDE 5 OF CARRIER BOARD AND INTO HEX SPACERS ITEM B AND 5 TIGHTEN 4 PLACES IP MODULE TO CARRIER BOARD MECHANICAL ASSEMBLY s Acromag come Em ooo vov rnc TE IP MECHANICAL ASSEMBLY iP tort E 4501 434 8E A B C D E F G 16 INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS
23. G ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS The board utilizes static sensitive components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier board plus the installed IP modules within the voltage tolerances specified IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature The dense packing of the IP modules to the carrier board restricts air flow within the card cage and is cause for concern Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering BOARD CONFIGURATION The carrier board may be configured for different applications All possible configuration settings will be discussed in the following Sections The jumper locations and IP module positions are shown in Drawing 4501 450 Power should be removed from the board when installing IP modules cables termination panels and field wiring Refer to Mechanical Assembly Drawing 4501 434 and your IP module documentation for specific configuratio
24. ISTER amp INTERRUPT LE CONTROLLER INTERRUPT MEMORY I Request FEQZSCIRQTS V imm 7 00 QUEST M 1E DRIVERS i IP B E POWER FIELD IP MODULE B I ld 1 IP INTERRUPT be FAILURE 8 07 00 3 vo a INIREQOB T8 SLI NENABEES Ea 1 Monitor ERROR 5 REGISTER 45V 5 hese power Po c c 12V pea supply pety A Ja 07 80 Ly nuages Room be REGISTER lt IP C T 2 p _ IP INTERRUPT ACCESS M GREEN IP C AND IP D CIRCUITRY PRESENT ON AVME9660 MODEL ONLY PULSE O D 807 800 5 LED STRETCHER REGISTER l P RESET BIR o A MENSELC Less ciel i EL to for short i f oso ADDRESS 2 IS B a ADDRESS j gt Marcy re T P c i D l ELECTION DECODE LATCHES Lt IP MODULE C SU fuda EP l OAR ESL vd AVME9660 ONLY 15 ERRORCe x A ADDRESS IP21 ET gt BUFFERS f Lese Mpower e 5 ep supply px tl Es ee a 1 LO Jema FILTERS je El INI 5 STRETCHER e BAG BAt x P6 18 fel ene Ly 8015 800 x B ty I MRSE BUFFERS E IE nise IDSELD Pim AVME9630 9660 CARRIER EE xe x Shp STs p d IP MODULE D Seo in m BOARDS BLOCK DIAGRAM AVME9660 ONLY 1 y um BM 35v 6 Le 50 owen B Acromag Isseseix I or op fel 2 0 sippy be tay Wixom MICH su e
25. P modules Enabling IP memory has no effect on the and ID spaces of the module MSB LSB D7 D1 DO Not Not Not Not IP D IP C IP B IP A Used Used Used Used Mem Mem Mem Mem Ena Ena Ena Ena These Bits are Not Used on AVME9630 Where Bits 7 6 5 4 Not used equal 0 if read Bit 3 Writing 1 to this bit enables the IP D Memory Enable memory space for IP D A zero disables Read Write memory space accesses Reset Condition Set to 0 memory Space accesses disabled for IP D Bit 2 Writing a 1 to this bit enables the IP C Memory Enable memory space for IP C A zero disables Read Write memory space accesses Reset Condition Set to 0 memory space accesses disabled for IP C Bit 1 Writing a 1 to this bit enables the IP B Memory Enable memory space for IP B A zero disables Read Write memory space accesses Reset Condition Set to 0 memory Space accesses disabled for IP B Bit 0 Writing a 1 to this bit enables the IP A Memory Enable memory space for IP A A zero disables Read Write memory space accesses Reset Condition Set to 0 memory space accesses disabled for IP A IP Memory Base Address amp Size Registers Read Write IP_A Base D1H IP_B Base D3H IP_C Base D5H Not used on AVME9630 IP_D Base D7H Not used on AVME9630 The IP Memory Base Address amp Size Registers are user programmable to define the starting address of standard A24 mem
26. This link is implemented and controlled by the carrier board s FPGA The VMEbus to IP logic interface link allows a VMEbus master to e Access up to 32 ID Space bytes for IP module identification via D08 O data transfers using VMEbus A16 short address space e Access up to 128 I O Space bytes of IP data via D16 D08 EO data transfers using VMEbus A16 short address space e Access up to 8Mbytes of IP data mapped to Memory Space via D16 or DO8 EO transfers using VMEbus A24 standard address space e Respond to two IP module interrupt requests per IP with software programmable VMEbus interrupt levels Carrier Board Clock Circuitry The VMEbus 16MHz system clock is divided down by the FPGA to obtain the IP module 8MHz clock signals Separate IP clocks are driven to each IP module All clock lines include series damping resistors to reduce clock overshoot and undershoot and 12 similar length PC board trace lengths are employed to minimize clock skew between the IP modules IP Read and Write Cycle Timing An IP read or write cycle is carried out via a VMEbus A24 or A16 data transfer The data transfer starts when the VMEbus Data Strobe 0 DS0 goes active and ends when the carrier board drives Data Transfer Acknowledge DTACK active back to the VMEbus master The carrier board typically has a 750ns IP module data transfer cycle time A typical IP module data transfer cycle is described here starting with DSO going act
27. Used Used Notes 1 ACE this bit is Auto Clear Interrupt Enable 2 GIE this bit is a Global Interrupt Enable 3 GIP this bit is Global Interrupt Pending Where Bits 7 Writing a 1 to this bit will enable automatic clear of pending interrupts on the carrier When this bit is set pending interrupts will not be latched or registered on the carrier An interrupt will only remain set as pending on the carrier if its corresponding IP module has an active interrupt request Bits 6 5 Not used equal 0 if read Bit 4 Writing a 1 to this bit causes a Software Reset software reset Writing 0 or reading Write the bit has no effect When set the software reset bit will have a duration of 1us Reset Condition Set to 0 Bit 3 Writing a 1 to this bit enables Global Interrupt interrupts to be serviced provided that Enable GIE interrupts are supported and configured Read Write A 0 disables servicing interrupts Reset Condition Set to 0 interrupts disabled Bit 2 This bit will be 1 when there is an Global Interrupt interrupt pending This bit will be O Pending GIP when there is no interrupt pending Read Polling this bit will reflect the board s pending interrupt status even if the Global Interrupt Enable bit is set to 0 Reset condition Set to 0 Bits 1 0 Not used equal 0 if read Interrupt Level Register Read Write Base C3H The carrier board passes interrupt request
28. W LIB MO3 1 44MB MSDOS format to simplify communication with Acromag IP modules All functions are written in the C programming language and can be linked to your application Refer to the README TXT file in the root directory on the diskette for more details and the 96X0 TXT files of the AVME9660 9630 subdirectories that correspond to your carrier model INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened lf the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions lt is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment It is recommended that the board be visually inspected for evidence of mishandling prior to applying power V CAUTION SENSITIVE ELECTRONIC DEVICES DO NOT SHI OR STORE NEAR STRON
29. able which mates with the IP field connections of the carrier board The electronic link from the field I O connections to the carrier board is made via the IP module selected for your specific application To facilitate easy connection of external devices to the IP field pins of the carrier board optional Termination Panels are available A ribbon cable connects a 50 pin IP field I O connector on the carrier board to the Termination Panel At the Termination Panel field I O signals are connected to a 50 position terminal block via screw clamps The AVME9660 contains four IP modules and thus 200 I O connections are provided on the A B C and D connectors The AVME9630 contains two IP modules and provides 100 connections on the A and B connectors The VMEbus and IP module logic commons have a direct electrical connection i e they are not electrically isolated However the field I O connections can be isolated from the VMEbus if an IP module that provides this isolation between the logic and field side is utilized A wide variety of IP modules are currently available from Acromag and other vendors that allow interface to many external devices for both digital and analog I O applications VMEbus Interface The carrier board s VMEbus interface is used to program and monitor and carrier board s registers for configuration and control of the board s documented modes of operation see section 3 In addition the VMEbus interfac
30. address FF0000 Hex and 32 bit CPU s at FFFF0000 Hex VMEbus Address Modifiers No hardware jumper configuration is needed The carrier board will respond to both address modifiers 29H and 2DH in the VMEbus short I O space This means that both short supervisory and short non privileged accesses are supported The carrier board will respond to both address modifiers 39H and 3DH in the VMEbus standard address space when standard address space accesses to IP memory are enabled via programmable registers on the carrier board refer to Section 3 for programming details INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS Interrupt Configuration No hardware jumper configuration is required All interrupt enabling status and VMEbus interrupt level selections are configured via programmable registers on the carrier board see Section 3 for programming details The carrier board passes interrupt requests from the IP modules to the VMEbus It does not originate interrupt requests Refer to the IP modules for their specific configuration requirements CONNECTORS Carrier Field Connectors IP modules A through D Field I O connections are made via front panel connectors A B C and D for IP modules in positions A through D respectively C amp D not used on AVME9630 IP module assignment is marked on the front panel for easy identification see jumper amp IP location drawing 4501 450 for physica
31. ake any IP specific action required to remove the interrupt request at its source C Clear the interrupting IP by writing a 1 to the appropriate bit in the IP Interrupt Clear Register 11 D Enable the interrupting IP by writing a 1 to the appropriate bit in the IP Interrupt Enable Register 8 Ifthe IP interrupt stimulus has been removed and no other IP modules have interrupts pending the interrupt cycle is completed i e the carrier board negates its interrupt request A Ifthe IP interrupt stimulus remains a new interrupt request will immediately follow If the stimulus cannot be removed then the IP should be disabled or reconfigured B If other IP modules have interrupts pending then the interrupt request IRQx will remain asserted This will start a new interrupt cycle 4 0 THEORY OF OPERATION This section describes the basic functionality of the circuitry used on the carrier board Refer to the Block Diagram shown in the Drawing 4501 451 as you review this material CARRIER BOARD OVERVIEW The carrier board is a VMEbus slave board providing up to four industry standard IP module interfaces for the AVME9660 and two IP module interfaces for the AVME9630 The carrier board s VMEbus interface allows an intelligent single board computer VMEbus Master to control and communicate with electronic devices that are external to the VMEbus card cage The external electronic hardware is linked to the carrier board via ribbon c
32. ard may optionally occupy memory in the VMEbus standard A24 address space if needed for IP modules containing Memory space IP memory will only be mapped into the standard memory space if it is enabled for a particular IP per the user programmable IP Memory Enable Register see Table 3 1C and subsequent description The starting memory address for each enabled IP and the memory size for each enabled IP module is user programmable via its associated IP Memory Base Address amp Size Register see Table 3 1C and subsequent description Base Table 3 1C AVME9630 9660 Carrier Board Registers Base Address Address Hex D15 D08 D07 DOO Hex eder d Not Used Status Register 00C1 Not Used Register 00C3 IP Error mL 00C5 IP Memory 00C4 00C6 00C7 00C8 00C9 4 Not Used Not Used 4 00CE 00CF 00D0 IP_A Memory Base Address amp Size Register IP_B Memory Base Address amp Size Register IP_C Memory Base Address amp Size Register IP_D Memory Not Used Base Address amp Size Register 00D7 00D8 00D9 4 Not Used Not Used Y 00DE 005 IP Interrupt Not Used Enable Register IP Interrupt Not Used Pending Register IP Interrupt Not Used Clear Register 00 6 00 7 4 Not Used Not Used Y e Registers not used on AVME9630 00D1 00D4 00D6 INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS Identification PROM Read Only 32 Odd Byte Addresses
33. ate a software reset can be issued When an IP module places data on the bus for all data read cycles any undriven data lines are read by the VMEbus as high because of pull up resisters on the carrier board s data bus VME Interrupter Interrupts are initiated from an interrupting IP module However the carrier board will only pass an interrupt generated by an IP module to the VMEbus if the carrier board has been first enabled for interrupts Each IP module can initiate two interrupts which can be individually enabled on the carrier board After interrupts are enabled on the carrier board via the Interrupt Enable Register see section 3 for programming details an IP generated interrupt is recognized by the carrier board and is recorded in the carrier board s Interrupt Pending Register INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS A carrier board pending interrupt will cause the board to release the interrupt to the VMEbus provided the Global Interrupt Enable bit of the carrier s Status Register has been enabled see section 3 for programming details The carrier board releases the interrupt to the VMEbus by asserting the interrupt request level as pre programmed in the carrier s Interrupt Level Register The carrier board s interrupt logic then monitors the VMEbus Interrupt Acknowledge Input IACKIN signal An active IACKIN signal detected by the carrier board is either passed to Interrupt Acknowl
34. carrier board by writing a 1 to bit 3 global interrupt enable bit in the Carrier Board Status Register Sequence of Events For an Interrupt 1 The IP asserts an interrupt request to the carrier board asserts IntReqO0 or IntReq1 2 The AVME9630 9660 carrier board acts as an interrupter in making the VMEbus interrupt request asserts IRQx corresponding to the IP interrupt request 3 The VMEbus host interrupt handler asserts IACK and the level of the interrupt it is seeking on A01 A03 4 When the asserted VMEbus IACKIN signal daisy chained is passed to the AVME9630 9660 the carrier board will check if the level requested matches that specified by the host If so the carrier board will assert the IntSel line to the appropriate IP together with carrier board generated address bit A1 to Select which interrupt request is being processed A1 low corresponds to IntReq0 A1 high corresponds to IntReg1 5 The IP puts the appropriate interrupt vector on the local data bus D00 D07 if an D08 O interrupter or DOO D15 if a D16 interrupter and asserts Ack to the carrier board The carrier board passes this along to the VMEbus D08 O or D16 and asserts DTACK 6 The host uses the vector to point at which interrupt handler to execute and begins its execution 7 Example of Generic Interrupt Handler Actions A Disable the interrupting IP by writing a O to the appropriate bit in the IP Interrupt Enable Register B T
35. ders can be connected to flat ribbon cable from the front panel without interference from boards in adjacent slots Ejector latches on the headers provide for excellent connection integrity and easy cable removal Optional Screw Termination Panel Model supports field connection via screw terminals using the optional DIN rail mount termination panels Memory Space Access Support IP memory space accesses are supported and software configurable from 1Mbyte to 8Mbytes in the VMEbus standard address space Supports Two Interrupt Channels per IP Up to two interrupt requests are supported for each IP The VMEbus interrupt level is software programmable Additional registers are associated with each interrupt request for control and status monitoring Supervisory Circuit for Reset Generation A microprocessor supervisor circuit provides power on power off and low power detection reset signals to the IP modules per the IP specification Individually Filtered Power Filtered 5V 12V and 12V DC power is provided to the IP modules via passive filters present on each supply line serving each IP This provides optimum filtering and isolation between the IP modules and the carrier board and allows analog signals to be accurately measured or reproduced on IP modules without signal degradation from the carrier board logic signals VMEbus INTERFACE FEATURES Slave Module Carrier Register Short I O Access A16 D16 D08 O IP Module ID Space A
36. e is also used to communicate with and control external devices that are connected to an IP module s field I O signals assuming an IP module is present on the carrier board The VMEbus interface is implemented in the logic of the carrier board s Field Programmable Gate Array FPGA The FPGA implements VMEbus specification revision C 1 as an interrupting slave including the following data transfers types e A16 D16 DO8 O Carrier Register Short I O Access e A16 D16 DO8 O IP Module ID Space e A16 D16 DO8 EO IP Module Space e A24 D16 D08 EO IP Module Memory Space INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS The carrier board s VMEbus data transfer rates are typically e b50Ons for accesses to the carrier board registers e 750nsfor data transfers to the IP modules assuming 0 wait states on IP The carrier board s FPGA monitors the base address jumper setting which is jumperable on 1K byte boundaries in the VMEbus Short I O A16 Address Space When the selected base address matches the A16 address provided by the VMEbus master the FPGA controls and implements the required bus transfer allowing communication with the carrier board s registers or IP modules Carrier Board Registers The carrier board registers presented in section 3 are implemented in the logic of the carrier board s FPGA An outline of the functions provided by the carrier board registers include Software res
37. edge Output IACKOUT or consumed by the carrier board IACKIN is passed to IACKOUT if the VMEbus interrupt level does not match that programmed into the carrier s Interrupt Level Register If a match is detected the carrier board responds to the interrupt by consuming IACKIN The carrier board also responds to an interrupt by driving IP Interrupt Select INTSEL active to the IP that generated the interrupt provided only one interrupt has been issued If two or more interrupts occur at the same time then INTSEL is driven active to the IP with the highest priority IP A intO has the highest priority IP D Int1 has the lowest priority see section 3 for more detail The IP module responds by placing the interrupt vector on the data bus and asserts ACK active The carrier then asserts DTACK active and the VMEbus master responds by executing the code at the address of the interrupt vector The user written interrupt routine should include code to clear the carrier board s pending interrupt via the carrier s Interrupt Clear Register see section 3 since the interrupt release mechanism is type Release on Register Access RORA In addition the IP module may need similar attention see your IP module documentation Power Failure Monitor The carrier board contains a 5 volts undervoltage monitoring circuit which provides a reset to the IP modules when the 5 volt power drops below 4 27 volts typical 4 15 volts minimum This circuit
38. et can be issued to reset the FPGA Logic and all IP modules present on the carrier board via the Status Register e Monitoring the error signal received from each IP module is possible via the IP Error Register e Configuration of VMEbus A24 standard address space for optional Memory Space on each IP module is possible Memory Space access to the IP modules can be individually enabled via the IP Memory Enable Register The base address and address range size is programmed via carrier registers IP A IP B IP C and IP D Memory Base Address amp Size Registers The address size can be selected from 1M 2M 4M or 8M bytes Enabling of VMEbus interrupt requests from each IP module via the IP Interrupt Enable Register is possible The desired VMEbus interrupt level desired can be set via the Interrupt Level Register and pending interrupts can be monitored and cleared via carrier registers IP Interrupt Pending and IP Interrupt Clear Registers e Lastly pending interrupts can be globally monitored and released to the VMEbus via the Status Register IP Logic Interface The IP logic interface is also implemented in the logic of the carrier board s FPGA The carrier board implements revision 0 7 1 Industrial I O Pack logic interface specification and includes four IP logic interfaces on an AVME9660 and two interfaces on an AVME9630 carrier The VMEbus address and data lines are linked to the address and data of the IP logic interface
39. fy Write cycles 500nS Typical all carrier board 14 registers measured from the falling edge of DSx to the falling edge of DTACK 750nS Typical IP registers with no wait states See IP specifications for information on wait states IP register access time will increase by the number of wait states multiplied by 125nS the period of the 8 Mhz clock VMEbus Address Modifier Codes Short I O Space Standard Addr Interrupts essSpace Base address is hardware jumper selectable Occupies 1K byte Responds to both address modifiers 29H amp 2DH in the VMEbus short I O space for carrier board registers and IP and ID PROM spaces Responds to both address modifiers 39H amp 3DH in the VMEbus standard address space when such accesses to IP memory are enabled via programmable registers on the carrier board Base addresses and sizes of IP memory are programmable from 1M to 8M bytes Creates 1 7 programmable request levels up to two requests sourced from each IP D16 D08 O interrupter interrupt vectors come from IP modules Carrier registers for control amp status monitoring Interrupt release mechanism is Release On Register Access RORA type INDUSTRIAL PACK COMPLIANCE Specification This device meets or exceeds all written Industrial I O Pack specifications per revision 0 7 1 Electrical Mechanical Interface AVME9630 E supports two single
40. is also easily done through registers Board Diagnostics The board is a non intelligent slave and does not perform self diagnostics It does however provide front panel LED s to indicate successful communication with each of the four IP modules A through D C amp D are not used on AVME9630 These LED s are driven by the corresponding IP acknowledge signal which is lengthened by circuitry on the carrier board to make the access visible to the user This means that frequent accesses to an IP will result in constant LED illumination The LED s indicate I O memory interrupt acknowledge and ID PROM accesses Note that the LED s will not illuminate during accesses of carrier board registers or accesses to IP modules which are not physically present or to unsupported memory space The LEDs may temporarily illuminate upon initial power up Additional information about the error status of the IP modules can be obtained by reading the IP Error Register INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS GENERATING INTERRUPTS Interrupt requests do not originate from the carrier board but rather from the IP modules Each IP may support 0 1 or 2 interrupt requests The carrier board processes the request from the IP and uses the Interrupt Level Register data to map the request to the desired VMEbus interrupt level if locally enabled within the Interrupt Enable Register and globally enabled within the Carrier Board
41. is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier board to verify that it is correctly configured Replacement of the carrier and or IP with one that is known to work correctly is a good technique to isolate a faulty board CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS Acromag s Applications Engineers can provide further technical assistance if required When needed complete repair services are also available from Acromag 6 0 SPECIFICATIONS GENERAL SPECIFICATIONS Operating Temperature 0 to 70 C 40 to 850 E Versions Note that visual LED performance may be degraded below 20 C Relative Humidity 5 95 non condensing Storage Temperature 55 to 100 C Physical Configuration AVME9630 90 6 3 937 inches 100 0 mm Width 6 299 inches 160 0 mm Board Thickness 0 062 inches 1 59 mm Max Component Height 0 550 inches 13 97 mm Recommended Card Spacing 0 800 inches 20 32mm Ph
42. ive DSO is sampled on the rising edge of the system 16MHz clock edge after it goes active All operations are then synchronized to the IP 8MHz clock as required by the IP module specification Thus typically three 8MHz clock cycles later an IP select line goes active IOSEL IDSEL 3 or INTSEL With no IP wait states an active IP Acknowledge 3 signal is driven active by the IP on the next rising edge of the 8MHz clock The carrier board samples ACK one clock cycle later and then asserts DTACK active ending the VMEbus data transfer The carrier board releases the select line IOSEL IDSEL MEMSEL or INTSEL on the first rising edge of the 8MHz clock cycle after DSO goes inactive Timing Diagram CLK SH hujua SER mz Len DSO0 IHG i j j j j i j IOSEL ACK DTACK Note that the select line IOSEL DSEL MEMSEL or INTSEL is held active a short time after DTACK is issued However the IP module should not expect data to be held after ACK is detected by the carrier board in a data write cycle If a select line IOSEL IDSEL INTSEL or MEMSEL is driven active to an IP module and the IP module does not return active then DTACK will also not be generated by the carrier board This will cause a bus transfer time out error and the VMEbus system may need to be reset In addition the carrier board will remain in a state waiting for ACK from the IP To take it out of this st
43. l locations of the IP modules Flat cable assemblies and Acromag termination panels or user defined terminations can be quickly mated to the front panel connectors Pin assignments are defined by the IP module employed since the pins from the IP module field side correspond identically to the pin numbers of the front panel connectors Connectors A through D are 50 pin header male connectors 3M 3433 D303 Connectors are high density stacked Condo type with A amp B and C amp D residing on the same part These connectors include long ejector latches and 30 microns of gold in the mating area for excellent connection integrity per MIL G 45204 Type Grade C IP Field Connectors IP modules A through D The field side connectors of IP modules A through D mate to connectors P7 P10 respectively on the carrier board P9 amp P10 are not used on Model AVME9630 IP location is silk screened on the board for easy identification Field and logic side connectors are keyed to avoid incorrect assembly P7 P10 are 50 pin plug header male connectors These AMP 173280 3 connectors mate to AMP 173279 3 connectors or similar on the IP modules This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers supplied with Acromag IP modules provide additional stability for harsh environments see Drawing 4501 434 for assembly details Pin assignments for these
44. n and assembly instructions VMEbus INTERFACE CONFIGURATION The carrier board is shipped from the factory configured as follows e Carrier board with VMEbus Short I O Base Address of 0000H Board will respond to both Address Modifiers 29H and 2DH Registers on the carrier board plus the I O and ID spaces on any installed IP modules will be accessible e Programmable software registers default to IP memory space VMEbus standard address space accesses disabled Programmable software registers default to IP interrupt requests disabled and VMEbus interrupt level none Address Decode Jumper Configuration The carrier board interfaces with the VMEbus as a 1K byte block of address locations in the VMEbus short I O address space refer to Section 3 for memory map details J1 decodes the six most significant address lines A10 through A15 to provide segments of 1K address space The configuration of the jumpers for different base address locations is shown in Table 2 1 IN means that the pins are shorted together with a shorting clip OUT indicates that the clip has been removed Table 2 1 Address Decode Jumper Selections J1 Pins Base Hex 11 amp 12 9 amp 10 7 amp 8 5 amp 6 3 amp 4 1 amp 2 l l l l l 1000 Consult your host CPU manual for detailed information about addressing the VMEbus short I O A16 16 bit space In many cases CPU s utilizing 24 bit addressing will start the 16 bit
45. nterrupt is pending A bit will be a 0 Read when its corresponding interrupt is not pending Polling this bit will reflect the IP modules pending interrupt status even if the IP interrupt enable bit is set to 0 Reset Condition Set to 0 10 IP Interrupt Clear Register Write Base E5H The IP Interrupt Clear Register is used to individually clear the IP interrupt Pending bits set in the IP Interrupt Pending register MSB LSB D1 DO IP D Int1 Clear IP D IntO Clear IP C Int1 Clear IntO Clear IP B Inti Clear IP B IntO Clear IPA Inti Clear IPA Into Clear Bits not used on AVME9630 Where All Bits Writing a 1 to a bit causes the IP Interrupt Clear corresponding IP interrupt Pending bit to Write clear Writing 0 or reading has no effect Reset Condition Set to 0 GENERAL PROGRAMMING CONSIDERATIONS The carrier board register architecture makes the configuration fast and easy The only set of configuration hardware jumpers is for the base address of the carrier board in the VMEbus short I O space Once the carrier board is mapped to the desired base address communication with its registers and the I O and ID spaces of the IP modules is straightforward The carrier board is easily configured to communicate with IP memory space if present through two configuration registers Interrupt configuration control if supported by IP modules
46. ory space and the size of that memory space corresponding to IP modules A through D The memory size for each enabled IP module is user programmable from 1MByte to 8MByte in multiples of two Note that memory on IP modules can only be accessed if enabled within the IP Memory Enable Register and that the memory bases for enabled IP modules must not be programmed to overlap with each other The size selected by these registers should be matched to that required by the associated IP To lon oe l Ja Io A23 22 A21 A20 Not p pes e er er e er A23 A22 A21 Not Not Not IEEE A23 A22 Not Not Not pst ee deed soe Used Used A23 Not Not Not Not ee Uses Used Used Used oea Where Memory Size Bit 7 6 5 4 These bits define the memory base IP Memory Base address Read and write operations are Address implemented on all bits even if labeled Read Write unused Thus a read operation will return the last value written Reset Condition Set to 0 memory base address 0 Bit 3 2 Not used equal 0 if read Bit 1 0 These bits define the memory size selected IP Memory Size Read Write 1MB 2MB 4MB or 8MB as shown in the previous table Reset Condition Set to 0 1MB memory size INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS IP Interrupt Enable Register Read Write Base E1H The IP Interrupt Enable Register is used to individually enable disable IP interrupts Each IP
47. rat oe eoe e 12 0 FILTERS ix ME AVME963 9660 BLOCK DIAGRAM D 7 Aw tor 1 on 4501 451 AF A c D E F G H A B e D E F e H P2 P1 50 50 1 49 49 P2 P1 48 48 TO TO 47 47 AVME9630 9660 MODEL 5025 552 46 46 CARRIER BOARD TERMINATION 45 45 P3 OR P4 5 6 PANEL 44 44 43 43 42 42 ke x gt 41 41 40 40 FEET 39 39 7 38 38 TOP VIEW 37 37 36 36 35 35 34 34 gt zm a 31 31 RELIEF NON SHIELDED CONNECTOR d 30 1004 534 An RIBBON CABLE 1004 512 28 29 2002 211 28 28 3 127 27 26 26 25 25 24 24 23 25 22 22 21 21 lt POLARIZING 20 20 KEY 19 19 18 18 17 17 4 16 16 16 15 14 14 13 13 12 12 11 11 PIN 1 19 19 50 PIN 9 9 a Pru PIN 1 ON CABLE 7 7 IS DESIGNATED WITH STRAIN RELIEF b 6 RED INK 1004 534 5 5 5 4 4 FRONT VIEW 2 2 NOTESEVEN DIGIT PART NUMBERS ARE 1 1 ACROMAG PART NUMBERS XXXX XXX MODEL 5025 550 x SIGNAL CABLE NON SHIELDED MODEL 5025 550 x SCHEMATIC 6 Acromag sse x soe ec CABLE 5025 550 x NON SHIELDED Tort 54501 462 A B e D E F G H E rd INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS
48. ry is implemented per the Industrial Pack specification Assess LEDs and Pulse Stretcher Circuitry An LED display and pulse stretcher circuit is dedicated to each IP module for indication of a data transfer to from the corresponding IP module An IP acknowledged data transfer activates the pulse stretcher circuit The pulse stretcher s circuit is programmed to illuminate the LED for a duration of 0 1 seconds typical Power Supply Filters Power line filters are dedicated to each IP module for filtering of the 5 12 and 12 volt supplies The power line filters are a T type filter circuit comprising ferrite bead inductors and a feed thru capacitor The filters provide improved noise performance as is required on precision analog IP modules Specifically the filters are typically capable of over 40dB of insertion loss for undesirable noise and oscillations in the 100MHz frequency range and over 2048 of insertion loss for noise and oscillations in the 10MHz frequency range 13 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it
49. s are NOT USED by the carrier board VMEbus Connections Table 2 3 indicates the pin assignments for the VMEbus signals at the P1 connector The P1 connector is the upper rear connector on the AVME9630 9660 board as viewed from the front The connector consists of 32 rows of three pins labeled A B and C Pin A1 is located at the upper left hand corner of the connector if the board is viewed from the front VMEbus connector P2 is not used Refer to the VMEbus specification for additional information on the VMEbus signals INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS TABLE 2 3 VMEbus P1 CONNECTIONS Pin Description Pin Description Pin Description 1A Doo BBSY 2c 6A Do5 6B BGIIN 7A 06 78 BGIOUT 9A GND 9B BG2OUT 25A Ao6 258 IRQe Asterisk is used to indicate an active low signal BOLD ITALIC Logic Lines are NOT USED by the carrier board POWER UP TIMING AND LOADING The AVME9630 9660 boards use a Field Programmable Gate Array FPGA to handle the bus interface and control logic timing Upon power up the FPGA automatically clocks in configuration vectors from a local PROM to initialize the logic circuitry for normal operation This time is measured as the first 145mS typical after the 5 Volt supply rises to 2 5 Volts at power up The VMEbus specification requires that the bus master drive the system reset for the first
50. s from the IP modules to the VMEbus It does not originate interrupt requests The Interrupt Level Register allows the user to control the mapping of IP interrupt requests to the desired VMEbus interrupt level Note that the Global Interrupt Enable bit in the Carrier Board Status Register must be set for interrupts to be enabled from the carrier board Also the specific IP interrupt request must be enabled via its corresponding bit in the Interrupt Enable Register described subsequently LSB D1 DO Not Not Not Not Not IL2 IL1 ILO Used Used Used Used Used MSB D7 Where Bits 7 6 5 4 3 Not used equal 0 if read Bits 2 1 0 These bits control the VMEbus interrupt IL2 ILO Read Write request level associated with IP interrupt requests as illustrated in the next table Reset Condition Set to 0 no interrupt request None CT d oo 2 y Sofi Sifo BEES NENNEN Jijo en GS y Sifi r o 0 1 0 1 0 1 0 1 INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS IP Error Register Read Base C5H The IP Error Register allows the user to monitor the Error signals of IP modules A through D The Industrial I O Pack specification states that the error signals indicate a non recoverable error from the IP such as a component failure or hard wired configuration error Refer to your IP specific documentation to see if
51. size IP modules A B or one double size 32 bit IP modules are Not Supported AVME9660 E supports four single size IP modules A D or two double size 32 bit IP modules are Not Supported VO Space A16 D16 or DO8 EO supports 128 byte values per IP ID 8 8 A16 D08 O supports 32 bytes per IP consecutive odd byte Memory Space addresses D16 is also supported with pull ups on the carrier board holding the upper 8 bits high A24 D16 or DO8 EO supports 1M to 8M bytes per IP module INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS Supports two interrupt requests per IP and interrupt acknowledge cycles D16 D08 O APPENDIX CABLE MODEL 5025 550 x Non Shielded MODEL 5025 551 x Shielded Type Flat Ribbon Cable 50 wires female connectors at both ends The x suffix designates the length in feet 12 feet maximum Choose shielded or unshielded cable according to model number The unshielded cable is recommended for digital I O while the shielded cable is recommended for optimum performance with precision analog applications Application Used to connect Model 5025 552 termination panel to the AVME9630 9660 non intelligent carrier board A D connectors Both have 50 pin connectors Length Last field of part number designates length in feet user specified 12 feet ma
52. support 15V and 15V supplies but the carrier boards are designed to handle these if needed for unique situations The power supply filters are typically capable of over 40dB of insertion loss for undesirable noise and oscillations in the 100MHz frequency range and over 2048 of insertion loss for noise and oscillations in the 10MHz frequency range The power failure monitor circuit provides a reset to IP modules when the 5 volt power drops below 4 27 volts typically 4 15 volts minimum Currents specified are for the carrier board only add the IP module currents for the total current required from each supply 5 Volts 596 AVME9630 E 210mA Typical 275mA Maximum AVME9660 E 210mA Typical 275mA Maximum 12 Volts 1596 or 15 Volts 596 OmA Not Used 12 Volts 45 or 15 Volts 5594 OmA Not Used Non Isolated VMEbus and IP module logic commons have a direct electrical connection As such unless the IP module provides isolation between the logic and field side the field I O connections are not isolated from the VMEbus LED illuminate duration 0 1 second typical VMEbus COMPLIANCE Specification This device meets or exceeds all written VME specifications per revision C 1 dated October 1985 IEC 821 1987 and IEEE 1014 1987 A24 A16 D16 D08 EO DTB slave supports Read Modi
53. the error signal is supported and what it indicates MSB LSB D7 DO Not Not IP D IP C IP B IP A Used Used Used Used Error Error Error Error Bits not used on AVME9630 equal 0 if read Where Bits 7 6 5 4 Not used equal 0 if read Bit 3 This bit will be a 1 when IP D asserts its IP D Error Error signal This bit will be 0 when there is Read no error Reset Condition Bit will be 0 no error unless driven by IP Bit 2 This bit will be a 1 when IP C asserts its IP C Error Error signal This bit will be 0 when there is Read no error Reset Condition Bit will be 0 no error unless driven by IP Bit 1 This bit will be a 1 when IP B asserts its IP B Error Read Error signal This bit will be 0 when there is no error Reset Condition Bit will be no error unless driven by IP Bit 0 This bit will be a 1 when IP A asserts its IP A Error Read Error signal This bit will be 0 when there is no error Reset Condition Bit will be 0 no error unless driven by IP IP Memory Enable Register Read Write Base C7H The IP Memory Enable Register allows the user to program which IP modules will be accessible in the standard A24 memory space An enable bit is associated with each IP A through D This register must be used in conjunction with the IP Memory Base Address amp Size Registers to fully define the addressable memory space of the I
54. to Acromag termination panel 5025 552 from the rear of the card cage and to AVME9630 9660 boards within card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Schematic and Physical Attributes See Drawing 4501 465 Field Wiring 100 pin header male connectors 3M 3433 D303 or equivalent employing long ejector latches and 30 micron gold in the mating area per MIL G 45204 Type Grade C Connects to Acromag termination panel 5025 552 from the rear of the card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Connections to AVME9630 9660 50 pin header male connectors 8M 3433 1302 or equivalent employing long ejector latches and 30 micron gold in the mating area per MIL G 45204 Type Il Grade C Connects to AVME9630 9660 boards within the card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Mounting Transition module is inserted into a 6U size single width slot at the rear of the VMEbus card cage Printed Circuit Board Six layer military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 to 85 C Storage Temperature 55 C to 10500 Shipping Weight 1 25 pounds 0 6Kg packed INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS
55. ximum It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 50 wire flat ribbon cable 28 gage Non Shielded cable model uses Acromag Part 2002 211 3M Type C3365 50 or equivalent Shielded cable model uses Acromag Part 2002 261 3M Type 3476 50 or equivalent Headers Both Ends 50 pin female header with strain relief Header Acromag Part 1004 512 3M Type 3425 6600 or equivalent Strain Relief Acromag Part 1004 534 3M Type 3448 3050 or equivalent Keying Headers at both ends have polarizing key to prevent improper installation Schematic and Physical Attributes For Non Shielded cable model see Drawing 4501 462 For Shielded cable model see Drawing 4501 463 Shipping Weight 1 0 pound 0 5Kg packed TERMINATION PANEL MODEL 5025 552 Type Termination Panel For AVME9630 9660 Boards Application To connect field I O signals to the Industrial I O Pack IP Termination Panel Acromag Part 4001 040 Phoenix Contact Type FLKM 50 The 5025 552 termination panel facilitates the connection of up to 50 field I O signals and connects to the AVME9630 9660 3U 6U non intelligent carrier boards A D connectors only via a flat ribbon cable Model 5025 550 x or 5025 551 x The A D connectors on the carrier board connect the field I O signals to the P2 connector on each of the Industrial I O Pack modules Field signals are accessed via screw terminal strips The terminal strip markings on the
56. ysical Configuration AVME9660 6U Eength 9 187 inches 233 3 mm Width eese 6 299 inches 160 0 mm Board Thickness 0 062 inches 1 59 mm Max Component Height 0 550 inches 13 97 mm Recommended Card Spacing 0 800 inches 20 32mm Connectors P1 8 DIN 41612 96 pin Type C Level P2 8 Not Used A D Carrier Field l O 50 pin Male Header x2 stacked condo type 3M 3433 D303 with ejector latches AVME9660 A B Carrier Field l O 50 pin Male Headers No ejector latches AVME9630 INDUSTRIAL I O PACK SERIES AVME9630 9660 VMEbus 3U 6U CARRIER BOARDS Data Transfer Bus VMEbus Access Time A Right angle pins 3M 2550 5002UB or equiv B Straight pins 3M 2550 6002UB or equiv P7 P10 IP Field l O 50 pin male plug header AMP 173280 3 or equivalent P9 P10 are not present on AVME9630 E P11 P14 IP Logic Interface 50 pin male plug header AMP 173280 3 or equivalent P13 P14 are not present on AVME9630 E Power Board power requirements are a function of the installed IP modules This specification lists currents for the carrier boards only The carrier boards individually filter and provide 5V 12V and 12V power to each IP from the VMEbus Note that the VMEbus standard does not
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