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EXC-1394PCI User`s Manual

1. 09 10 08 07 06 05 04 03 00 02 2 3 5 PCI Architecture PCI Status Register for PCI Express Bit Name Detected Parity Error Signaled System Error Received Master Abort Received Target Abort Signaled Target Abort Device Select DEVSEL Timing Status Data Parity Reported Fast Back to Back Capable UDF Supported 66MHz capable Capability List enable Interrupt Status Reserved Address 0008 H Length 8 bits Read Only Description This bit is set whenever a parity error is detected It functions independently from the state of Command Register Bit 6 This bit may be cleared by writing a 1 to this location Not used This bit is set when the device receives a master abort to terminate a transaction This bit can be reset by writing a 1 to this location Not used Not used Set to 00 fast timing Not used Set to 0 Set to 0 Set to 0 Set to 1 This bit is set when an interrupt is received Revision Identification Register RID This register contains the revision identification number of the EXC 1894PClfe The value at power up is 0001 H 2 3 6 Class Code Register CLCD Address 0009 H Length 24 bits Read Only This register s value indicates that the EXC 1394PCl e does not fit into any of the defined class codes The value at power up is FF0000 H page 2 6 Excalibur Systems Chapter 2 PCI Architecture 2 3 7 Cache Line Register Size Regi
2. 0084 0087 H 0088 H 008C 008F H 0090 H 0094 0097 H 0098 H 009C H 00A0 H 00A4 00A7 H Read Write Read Only Read Only Read Write Write 1 to Clear Read Write Read Write Read Only Read Only Read Only Write Only Read Write Read Only Read Only Read Only Read Only Read Only Read Only Page Number 4 4 4 4 4 4 4 5 4 6 4 6 4 6 4 6 4 7 4 7 4 8 4 8 Excalibur Systems Chapter 4 Register Name Firmware Revision Register Pointer to Current Entry of Transmit Stack Mode Select Register Start Register Excalibur Node Status Register Port Status Register Reserved 1394 Node ID Register CC Run Configuration Register Pointer to Beginning of Single Shot Stack Pointer to Beginning of Continuous Mode Stack Pointer to Beginning of Receive Linked List Pointer to End of Receive Linked List Reserved Speed Code Register Reserved Options Register Reserved STOF Period Register Last STOF Message Status Register Last STOF Message Area Last STOF Time Tag Registers Reserved Pointer to Most Recent Message Pointer to Least Recent Message Reserved Message Type Receive Control Table CC STOF Offsets Table Message Area EXC 1394PCI amp EXC 1394PCle User s Manual Byte Address 00A8 H OOAC H OOBO H 00B4 H 00B8 H OOBC H 00C0 00C7 H 00C8 H 00CC H 00D0 H 00D4 H 00D8 H OODC H OOEO O
3. Base Address 0 0010 H 8MB Node memory space Base Address 1 0014 H 128 bytes Global registers For PCI Express Three memory pages are required by the board one for the node memory space one for the Global registers and one for the DMA registers See Table 2 5 Table 2 5 Base Address Registers Definition for PCI Express Register Offset Size Function Base Address 0 0010 H 8MB Node memory space Base Address 2 0018 H 4 KB Global registers Base Address 4 0020 H 8KB DMA registers Note Each Base Address Register contains 32 bits Since the PCI Express board uses 64 bit address space each memory page covers two base addresses 0 1 2 3 4 5 Tables 2 6 and 2 7 describe the bits of the Base Address Register Table 2 6 Base Address Register for PCI Bit Description 04 31 Address of memory region with lower 4 bits removed 03 Always 0 memory is not prefetchable 01 02 Always 0 memory may be mapped anywhere within the 32 bit memory space 00 Always 0 indicates memory space Table 2 7 Base Address Register for PCI Express Bit Description 04 31 Address of memory region with lower 4 bits removed 03 Always 1 memory is prefetchable 01 02 Always 2 memory may be mapped anywhere within the 64 bit memory space 00 Always 0 indicates memory space page 2 8 Excalibur Systems Chapter 2 PCI Architecture 2 3 12 Cardbus CIS Pointer Address 0028 H Length 32 bits Read Only This registe
4. 08 11 DMA channel state These bits describe the state of the DMA read channel 0000 idle state Last transfer ended successfully 0001 idle state Last transfer was stopped by a node 0010 idle state Last transfer ended because of CPL timeout 0011 idle state Last transfer ended because of CPL UR error 0100 idle state Last transfer ended because of CPL CA error 0101 0111 idle state Reserved 1000 busy state DMA channel is busy processing 1001 busy state Requesting transfer The DMA channel is in the process of requesting data from the host computer 1010 busy state The DMA channel is waiting for completion of a read data transfer in response to a DMA read request 1011 busy state Waiting for board to provide accept data The DMA channel is waiting for completion of a data transfer to or from the internal node memory 1100 1111 busy state Reserved 04 07 Reserved set to 0 03 Abort DMA transfer 1 Abort transfer 0 no effect 02 Start DMA transfer 1 Start DMA transfer 0 no effect 00 01 Reserved set to 0 EXC 1394PCl amp EXC 1394PCle User s Manual page 2 13 Chapter 2 PCI Architecture 2 5 24 7 DMA Interrupt Status Register Address 0034 H Length 2 bits Read Write Write 1 to Clear Bit 0 of this register is set upon completion of a DMA transfer on DMAO a DMA write Bit 1 is set upon completion of a DMA transfer on DMA1 a DMA read To clear either bit
5. 4 2 16 Pointer to Current Entry of Transmit Stack 4 9 4 2 17 Mode Select ReGISten AE EE OE EK 4 9 4 2 18 dae RE N EE OE N 4 10 4 2 19 Excalibur Node Status Register iese ee ee ee ee Re ee ee ee ee ee ee ke ee ee ee 4 10 4 2 20 Port Status Register ui EE a GER ithe DEE Ee Ges Ee ENE 4 11 4 2 21 1394 Node ID Regist r iis Es see NR SERE RE ee EER ee Ge eae Re ER ee ese ER ekke ee 4 13 4 2 22 CC Run Configuration Register ees se ee ee ek ee Ge Re ee ee ee ke ee ee 4 13 4 2 23 Pointer to Beginning of Single Shot StacK sees ees see ee Re AR Re ee ee ee 4 13 4 2 24 Pointer to Beginning of Continuous Mode Stack seenen 4 14 4 2 25 Pointer to Beginning of Receive Linked List ee ee ee Re GR Re ee ee ee 4 14 4 2 26 Pointer to End of Receive Linked List ee se ee ee Re ee GR ee ee Re ee ee ee 4 14 4 2 27 Speed Code Register is EL Ee Meee 4 14 4 2 28 Options re SR N EE EE OE EE EE OE 4 15 4 2 29 STOF Period Redister sies Eie gee skies Ge Gee y Ag Ee ees Eg Eeu ED EED ee Re EE Ee Ek ER EER EES 4 15 EXC 1394PCI amp EXC 1394PCle User s Manual Chapter 4 Control Computer Operation 4 2 30 Last STOF Message Status Register se ee ee ee ee ee ee ee ee ee ee eke ee 4 15 4 2 31 Last STOF Message Area iis a ee es se ee ee ee ee ee ee ee a Ee ee ee ee ee ee ee ee 4 16 4 2 32 Last STOF Time Tag Registers se ee ee ee Ee Re Ee ee ee ee ee ee ee ee ee ee 4 16 4 2 33 Pointer to Most Recent Message ie ee ee se ee Ee
6. Each bit indicates the occurrence of a specific event condition The bits in this register are lit when the event condition occurs regardless of whether the event condition is set to generate an interrupt For information on generating interrupts see the Interrupt Mask Register on page 5 5 page 5 4 Excalibur Systems Chapter 5 Table 5 2 Bit 31 30 29 07 28 06 05 04 03 02 01 00 Remote Node Operation Interrupt Status Register Description Interrupt occurred on start of message transmit for a specific message queuing in progress can change the data pointer Check Stack Status Words for which message Interrupt occurred on end of message transmit for a specific message queuing complete can change the data Check Stack Status Words for which message Interrupt occurred on end of message receive for a specific message Check Buffer Or Receive Stack Status Words for which message Reserved STOF receive complete End of message queuing transmit Start of message transmit End of message receive CC recognized as failed Network Bus Mode changed Message error 5 2 4 Interrupt Mask Register Address 0008 H Length 32 bits Read Write Use this register to set interrupts Each bit is a flag that enables or disables the generation of a specific interrupt When an interrupt is received check the Interrupt Status Register to see which condition or conditions caused the interrupt
7. H Bits 0 5 Read Only This register contains the hours value of the BCD time of year subword within the IRIG B coded message 2 7 6 IRIG B Time Minutes Register Address 002C H Bits 8 14 Read Only This register contains the minutes value of the BCD time of year subword within the IRIG B coded message 2 7 7 IRIG B Time Seconds Register Address 002C H Bits 0 6 Read Only This register contains the seconds value of the BCD time of year subword within the IRIG B coded message 2 7 8 Control Functions High and Low Registers Address 0030 H Bits 0 10 High Address 0034 H Bits 0 15 Low Read Only The IRIG B time code formats reserve 27 bits known as Control Functions The Control Functions are for user defined encoding of various control identification or other special purpose functions No standard coding system exists The control bits may be programmed in any predetermined coding system 2 7 9 FPGA Revision Register Address 0038 H Bits 0 31 Read Only This register contains the FPGA revision of the board EXC 1394PCI amp EXC 1394PCle User s Manual page 2 21 Chapter 2 PCI Architecture 2 8 Global Timer Registers For the location of the registers on the memory map see Global Registers Map on page 2 15 2 8 1 Timer Prescale Register Address 003C H Bits 0 31 Read Write Use this register to define the resolution of the General Purpose Timer It is based on the Global Ti
8. OOE4 H Length 32 bits Read Write Use this register to specify the last byte of the Receive Message Stack 5 2 26 Speed Code Register Address 00F0 H Length 16 bits Read Write Use this register to select the communications speed of the node Table 5 20 Speed Code Register Bit Description 02 15 Reserved 00 01 Speed Code Table 5 21 Speed Code Bits 0 100 Mbps 0 0 200 Mbps 0 1 400 Mbps 1 0 Not Supported 1 1 5 2 27 Options Register Address 00F4 H Length 32 bits Read Only This register contains information about the node Table 5 22 Options Register Bit Description 02 15 Reserved 01 1 By default the Vehicle Time quadlet of each STOF message is updated before transmission in CC mode When this bit is lit the option to prevent updating the Vehicle Time quadlet is available see CC Run Configuration Register on page 4 13 0 The option to prevent updating the Vehicle Time quadlet of the STOF message before transmission is not available 00 1 Asynchronous mode is available 0 Asynchronous mode is not available EXC 1394PCI amp EXC 1394PCle User s Manual Remote Node Operation page 5 13 Chapter 5 Remote Node Operation 5 2 28 STOF Period Register Address 0100 H Length 16 bits Read Write Use this register to set the period of time in usec within which the STOF is expected to be received The value of this register defaults to 12500 upon power up and reset T
9. Table 5 3 Bit 07 31 06 05 04 03 02 01 00 Interrupt Mask Register Description Reserved Interrupt on end of STOF receive Interrupt on end of Transmit Stack message Interrupt on start of Transmit Stack message Interrupt on end of received message Interrupt when CC recognized as failed Interrupt when Network Bus Mode changes Interrupt on message error EXC 1394PCI amp EXC 1394PCle User s Manual page 5 5 Chapter 5 Remote Node Operation 5 2 5 Reset Time Register Address 000C H Length 16 bits Read Write Use this register to reset the node s Time Tag Table 5 4 Reset Time Register Bit Description 01 15 Reserved 00 Reset Time Tag Resets the Time Tag to 0 All message Time Tags STOF offsets and STOF timing are based on this Time Tag value 5 2 6 Time Tag Registers Address 0010 H Length 48 bits Read Only These three registers represent the current value of the Time Tag All message Time Tags STOF offsets and STOF timing are based on this Time Tag value The Time Tag has a precision of 100 nanoseconds per bit The Time Tag should be read from address 10 then 12 then 14 When reading address 10 the Time Tag registers are frozen reading address 14 unfreezes them Table 5 5 Time Tag Registers Address Description 10 Low 16 bits of Time Tag 12 Middle 16 bits of Time Tag 14 High 16 bits of Time Tag 5 2 7 Reset Node Register Address 0018 H Length 16 bits Write Only Use this
10. ee ee ee ee Re ee ee GR ee ee ee ee ee ee 2 18 2 7 IRIG B Global Registers sere Eer SE REG ERGE Gee Esek Ger ie ie 2 19 2 1 1 Syne IRIG B Registe tec e ceeds tes Ee ERGE Ge Dee ERG ee Ee GR ee 2 20 2 7 2 IRIG B Time SBS High Register iss ee ee se ee ee ee se ee ke ee ee Re Age ee ek ke ee ee 2 20 2 7 3 IRIG B Time SBS Low Register ee ee ee ee ee ee ee ee ee Ke ee ee ee ee ee ee 2 20 2 7 4 IRIG B Time Days Register ie ee se ee ee ek Re Re AR Ge Re Re ee ee ee ee ede ee 2 21 2 7 5 IRIG B Time Hours Register ies sites ESE EE RSG ee GE GEE Ese Gee Ee GR ER ER GUN eke see ek Ee pes 2 21 2 7 6 IRIG B Time Minutes Register eee ee ee ek ee Ge Re ee Re ee Ge Ke ee ee ee ee ee ee 2 21 2 7 7 RIG B Time Seconds Register ee ee ek ee Ge Re ee Re ee ee Ke ee ee ee ee ee ee 2 21 2 7 8 Control Functions High and Low Registers ees esse ee ee ee ee ee ee ee ke ee ee ee ee 2 21 2 7 9 FPGA Revision Register ees ed eed ee dek SR Re ede ee ee Ge eg oe Deeg Ge Rees Ee pe 2 21 2 8 Global Timer Registers iese ee Ge Ged 2 22 2 8 1 Timer Prescale Register iis ee ee ee ER Re AA ER Ge AA Re Re Re ee ee Aa ee ede ee 2 22 2 8 2 Timer Preload Register 2 8 3 Timer Control Redister siese ee Se RE ER Be De GED Ee Ee sa go ED Ge De GR EED EE ee 2 8 4 General Purpose Timer Register iese ee ee ee ee ee Re ee ee Re ee ee Re ee ee ee ee 2 23 Chapter 3 Node Operation Overview 3 1 Node General Memory Map RR ee ee ee ee ee e
11. number and message number Note that the interrupt on end of message which can be set here is reflected in the Interrupt Status Register bit 29 Table 4 30 describes the fields of the CC Receive Control Word Table 4 30 CC Receive Control Word Bit Description 04 15 Reserved 03 Store Do not Store 02 Reserved 01 Interrupt on end of message 00 Reserved EXC 1394PCI amp EXC 1394PCle User s Manual page 4 17 Chapter 4 Control Computer Operation 4 3 4 2 36 CC STOF Offsets Table For each channel number this table contains STOF offset information in usec The table is indexed by channel number The information must be filled in for each channel to which the CC will transmit messages It is used to determine when to send out the message at the appropriate receive offset It is also used for generating the message trailer This table is read once when CC mode is started Changes made while running only take effect when the CC is stopped and restarted Table 4 31 describes the fields of each entry in the CC STOF Offsets Table Table 4 31 CC STOF Offsets Table Word Description 0 1 Initial receive offset used for transmitting messages in the Single Shot Stack 2 3 Transmit Offset 4 5 Receive Offset used for transmitting messages in the Continuous Stack 6 7 Datapump offset Message Area The CC Message Area contains e CC Transmit Messages CC Transmit Stacks e CC Linked List Area 4 3 1 CC Tran
12. 0104 H 0130 H 0136 0137 H 0138 H 013A 02FF H 0300 H 0304 H 0308 H 030C H 0310 H 0314 H 0318 H 031C 12FF H 1300 13EFF H 13F00 1FFFFF H Remote Node Operation Read Write Read Only Read Write Read Only Read Write Read Write Read Write Read Write Read Write Read Only Read Write Read Write Read Only Read Only Read Write Read Write Read Write Read Write Read Write Read Only Read Only Read Only Read Write Read Write Page Number 5 10 5 12 5 12 5 12 5 13 5 13 5 13 5 14 5 14 5 15 5 15 5 15 5 17 5 16 5 16 5 17 5 17 5 18 5 18 5 18 5 19 page 5 3 Chapter 5 Remote Node Operation 5 2 RN Mode Register Definitions 5 2 1 Hardware Revision Register Address 0000 H Length 16 bits Read Only This register contains the revision number of the hardware logic 12 bits are used for the major revision and four bits are used for the minor revision For example for hardware revision 2 1 2 is stored in the high 12 bits and 1 is stored in the low four bits 5 2 2 Excalibur Node ID Register Address 0002 H Length 16 bits Read Only This register contains the identifier of the Excalibur Node This is set to 1394 H 5 2 3 Interrupt Status Register Address 0004 H Length 32 bits Read Write Write 1 to Clear This register indicates the occurrence various interrupt events or conditions
13. 012F H 0130 H 0136 0137 H 0138 138FF H 13900 1FFFFF H Excalibur Systems Chapter 4 Chapter 4 Control Computer Operation Control Computer Operation Chapter 4 describes operation in Control Computer CC mode In CC mode the node acts as the Root Node and Bus Manager and is responsible for sending out the STOF message at a precise predefined programmable interval It has two Transmit Stacks one for Single Shot and one for Continuous to allow the first frame to be configured differently than the other frames The node has programmable STOF offsets for each RN with two receive offsets for each RN one for the Single Shot Stack and one for the Continuous Stack Receive messages can be filtered by a combination of message number and transmitting RN message type Interrupts can be requested for all messages or for specific message types as well as for various error conditions There are three possible transmission modes e Continuous e Single Shot e Both stacks In this mode the Single Shot stack is transmitted once and the Continuous stack is transmitted continuously thereafter This is useful in a scenario where the first frame must be according to the original preset offsets The CC updates the RNs with new offsets which are used in all subsequent frames The following topics are covered 4 1 CC Memory Map iese ESE eee ee 4 2 4 2 CC Mode Register Definition S ss ss Es ee ee
14. 1 0 0 EXC 1394PCI amp EXC 1394PCle User s Manual Remote Node Operation page 5 11 Chapter 5 Remote Node Operation 5 2 20 Number of Bad STOF Messages for CC Fail Register Address 00C4 H Length 32 bits Read Write Use this register to set the number of bad STOF messages to allow without considering the CC to have failed After this amount of bad STOF messages the CC is given a status of failed The value of this register reset to 3 upon power up and node reset Table 5 18 Number of Bad STOF Messages for CC Fail Register Bit Description 00 31 Number of missed STOF messages to allow 5 2 21 1394 Node ID Register Address 00C8 H Length 32 bits Read Only This register contains the node ID assigned automatically during bus configuration Table 5 19 1394 Node ID Register Bit Description 00 31 1394 Node ID 5 2 22 Pointer to Beginning of Transmit Stack Address 00D0 H Length 32 bits Read Write Use this register to specify the beginning of the Transmit Message Stack 5 2 23 Pointer to Beginning of Datapump Stack Address 00D8 H Length 32 bits Read Write Use this register to specify the beginning of the Datapump Message Stack 5 2 24 Pointer to Beginning of Receive Stack Address 00E0 H Length 32 bits Read Write Use this register to specify the beginning of the Receive Message Stack page 5 12 Excalibur Systems Chapter 5 5 2 25 Pointer to End of Receive Stack Address
15. 20 Pointer to End of Receive Stack ees esse ee ee ee ee ee ke ee ee ee ee ee ee ke ee ee ee 7 12 7 2 21 OptlOnS REGISTER EE OE EE EE OE EE 7 13 7 2 22 STOF Period Redistef ii ii ee SA Ee Ese GE SE a e ER De RE RR ee be Se ge DER 7 13 7 2 23 Last STOF Message Status Register sees se ee ee ke ee ee ee ee ke ee ee ee 7 13 7 2 24 Last STOF Message Alea Ke EES Ee EE ede eee Be eed ese De ge Be Ke gedoen Ke de bee 7 14 7 2 25 Last STOF Time Tag Registers se ee ee ee Ee AA ee Ge ee ee ee ee ee ede ee 7 15 7 2 26 Store STOF Messages Register iese se ee ee ek ee ee Re ee Ee ee ee ke ee ee 7 15 7 2 27 Pointer to Most Recent Message ie ee ee se ee Ee ee ee Ge ee ee ee ee ee ee ee 7 15 7 2 28 Pointer to Least Recent Message ie ee ee se ee Ee ee RR ee ee ee ee ee ee ee 7 16 7 2 29 Pointer to Trigger Message esse Ee ees de ee ee Ge Ede Ge Ede ek ee ee Rd de ee 7 16 7 2 30 Trigger Control Register ies eed n e EE Ge EES Ee ee 7 16 7 2 31 Trigger Position Register see seer ER inet Nee ee GR GER Ese RE KERE REKE Ee Kees 7 17 page iv Excalibur Systems Table of Contents 7 2 32 Linked List Fill Control Register ees se ee ee ee Re ee ee ee ee ee ee ke ee ee ee 7 18 7 2 33 Control Table Selection Register ees se ee ee ek ee Ge Re ee Ge ee ke ee ee 7 18 7 2 34 STOF Offsets Control Register ie ees se ee ee ek ee Ge Re ee Re ee ee ke ee ee 7 18 7 2 35 STOF Filter Window Begin Register esse ees see ee ek ee
16. 21 7 21 7 21 7 21 page 7 3 Chapter 7 Bus Monitor Operation Register Name Byte Address Read Write Page Number Message Type Receive Control Table 0300 34FF H Read Write 7 22 Source and Destination Channel Receive 3500 44FF H Read Write 7 22 Control Table Bus Monitor STOF Offsets Table 5500 SAFF H Read Write 7 23 Reserved 5B00 5CFF H Data Trigger Table 5D00 5E8F H Read Write 7 24 Reserved 5E90 5EEF H Message Area 5EFO 1FFFFF H 7 26 7 2 Bus Monitor Mode Register Definitions 7 2 1 Hardware Revision Register Address 0000 H Length 16 bits Read Only This register contains the revision number of the hardware logic 12 bits are used for the major revision and four bits are used for the minor revision For example for hardware revision 2 1 2 is stored in the high 12 bits and 1 is stored in the low four bits 7 2 2 Excalibur Node ID Register Address 0002 H Length 16 bits Read Only This register contains the identifier of the Excalibur Node This is set to 1394 H 7 2 3 Interrupt Status Register Address 0004 H Length 32 bits Read Write Write 1 to Clear This register indicates the occurrence various interrupt events or conditions Each bit indicates the occurrence of a specific event condition The bits in this register are lit when the event condition occurs regardless of whether the event condition is set to generate an interrupt For information on genera
17. 4 4 4 2 1 Hardware Revision Register ii see ee ee ese ee se ee ee ee ee ee Re ee ee ee ee ee Re Re ee ee ee ee ee Re ee ee 4 4 42 2 Excalibur Node ID Register eise eis seed Ge ee ES EE de Dee AE Ge ee Ge ee ed ee ee 4 4 4 2 3 Interrupt Status Register cece ee ee AR ee ee Re ee ee ee GR Ke ee ee ee ee ee ee 4 4 4 2 4 Interrupt Mask Register ii se ee ee ee ee Re Re AA ee Ee Re ee ee ee ee Re Re ee ee ee ee ee ede ee 4 5 42 5 Reset Time Register is se se ee EA AR Ge AE AA Re Re AG ee AA Re A E ee ee 4 6 4 26 TIMES Tag Redisters se Ek EER EER EE ERG Ke DE Se ee RE peas GEEN ER GED ds ede ke Ee bees ee 4 6 4 2 7 Reset Node Register iii ie ee ee AR Re AA EA AR Ge Re AG AA ee AA ee ee ee 4 7 4 2 8 Vehicle Time Preload Value Register ie ee ee ER ee Ke ee ee ee ee ee ee 4 7 4 2 9 Transmit Message Counter Register sesse ee ee Re ee ee ee ee ee ee ee ee ee ee 4 7 4 2 10 Receive Message Counter ReGister c ccccceceeeeeececeeeeeseeeeaeeeeeeeseeeeaees 4 8 4 2 11 STOF Message Counter Register esse ee ee ee ee ee ee GR ee Ge Re ee ee ee 4 8 4 2 12 Receive Message Error Counter Register ees see ee ee ee ek ee ee Re ee ee ee 4 8 4 2 13 Transmit Message Error Counter Register sees ee es se ke ee ee ee ee ek ke ee ee 4 8 4 2 14 Discarded Message Counter Register ee se ke ee ee Re ee ee Re ee ee ee 4 9 4 2 15 Firmware Revision Register iese ee ee ee ek ee ee ee Ke ee ke ee Ge Re ee ee ee 4 9
18. 5 2 23 Pointer to Beginning of Datapump StaCK iese esse ee ee Re ee ee ee Ge Re ee ee ee 5 12 5 2 24 Pointer to Beginning of Receive Stack ii se ee ee ee Re Ee ee ee ee ee 5 12 5 2 25 Pointer to End of Receive Stack iese esse ee ee ee ee ek ke ee ee Re ee ee ee ee ee ke ee ee ee 5 13 5 2 26 Spe d Gode R dister EE aue see Ee MERE FEE ee EE De Re ee Ee Ee een ee SE Rek ER 5 13 5 2 27 Options Register Ee Ee Re ER Ee ge Ee De ee ee iari ee UR ee 5 13 5 2 28 STOF Period Register susse de Ses esse cs ke pedeanGeendaneeta DERE Ee Ee See Ee See eg Ke Ee ie 5 14 5 2 29 Last STOF Message Status Register sees ee ee ee Re ee ee ee ee ke ee ee ee 5 14 5 2 30 Last STOF Message Area ese ee ee ee Re ee ee AR ke ee ee ee ee ee ee ee ee ke ee ee ee 5 15 5 2 31 Last STOF Time Tag Registers ees ese ee ee ee ek Ke ee Ge ee ee ee ee Ge ke ee ee ee 5 15 5 2 32 Store STOF Messages Register ies se ee ee ek ee Ge Re ee ee ee ee ke ee ee 5 15 5 2 33 Receive STOF Offset Register ee se ee ee ee AR ee ee AR ee Ge Re ee ee ee 5 16 5 2 34 Transmit STOF Offset Register sees se ee ee Re ee ee AR Ke ee ee ee ee ee 5 16 5 2 35 Datapump STOF Offset Register ese ee ee Re ee ee ee GR ee ee ke ee ee ee 5 17 5 2 36 Channel Number Register ese ee ee Ge ee ee AR ee Ge Re ee ee ee ee ke ee ee 5 17 5 2 37 Receive STOF Offset In Use Register ees ee ee ee ee Re Ge Ke ee ee ee 5 17 5 2 38 Transmit STOF Offset In Use Register ees see ee
19. 5 39 describes the fields of the RN Transmit Stack Entry Control Word Table 5 39 RN Transmit Stack Entry Control Word Bit Description 04 15 Reserved 03 Not end of stack this bit is set to indicate that this is a real message After the last message in the stack insert an extra entry with this bit cleared to indicate the end of the stack 02 Interrupt on start of transmission queuing 01 Interrupt on end of transmission queuing 00 Skip this entry Note that the interrupts in the Control Word are reflected in bits 30 and 31 of the Interrupt Status Register See Interrupt Status Register on page 5 4 Table 5 40 describes the fields of the RN Transmit Stack Status Word Table 5 40 RN Transmit Stack Entry Status Word Bit Description 15 Message queuing complete 14 Message queuing in progress do not change the data 13 Message queuing beginning do not change the data pointer 01 12 reserved 00 Message error timed out waiting for message to queue Note Ensure that the total transmission length of a frame does not exceed the transmit STOF offset time allocation EXC 1394PCI amp EXC 1394PCle User s Manual page 5 217 Chapter 5 Remote Node Operation 5 3 3 RN Receive Message Stack The Receive Message Stack describes the last x number of messages received by the node The number of messages stored in the stack is determined by the Pointer to Beginning of Receive Stack and the Pointer to End of Receive Stack S
20. 8 7 2 10 Receive Message Error Counter Register ees see ee ee ee Re ee ee Re ee ee ee 7 8 7 2 11 Discarded Message Counter Register ee se ee Ee AR ee ee Re ee ee ee 7 8 7 2 12 Firmware Revision Register iese se se ee ee ee ee Ee ee ee ee ee ee Re Re ee ee ee ee ee ede ee 7 8 7 2 13 Mode Select Register iss EES SKEER EE DERE Dee ES SEGE Ge VEREER GEN iaiki 7 9 7 2 14 Start Register ss EERS FREE De EE DER Ee oe ER eo ee te EE Reen ee ee ke ee 7 9 7 2 15 Excalibur Node Status Register see ee ee ee ee ee ee ee ek ke ee ee Re ee ee ee 7 9 7 2 16 Port Status Register eise ss ERWEE EES SE EE BEG ek Re ee seed ee ee ee nia Ee 7 10 7 2 17 Number of Bad STOF Messages for CC Fail Register esse se ee ee 7 12 7 2 18 Pointer to Beginning of Receive Linked List ee ee ee GR Re ee ee 7 12 7 2 19 Pointer to Beginning of Receive Stack ee ee se ee ee Re ee Re ee ee ee 7 12 7 2 20 Pointer to End of Receive Stack iese esse ee ee ee ee ek ke ee ee ee ee ee ee Ge ke ee ee ee 7 12 7 2 21 OptonsRedister tuie EE ES ER EE wee ee Es Ee DEE Res GE n AE ED 7 13 7 2 22 STOF Period Redistef iii SS Eg ER N SE ER Lege task Ge Ee Medea ee SPR ADS 7 13 7 2 23 Last STOF Message Status Register sees se ee ee Re ee ee ee ee Ge Re ee ee ee 7 13 7 2 24 Last STOF Message Area eie Ese Ee ee de a Nn ee eg ee Ee ge de Ke ge Seen Ke de ee 7 14 7 2 25 Last STOF Time Tag Registers ees se ee ee ee ee Re ee ee ee ee ee ee Re ee ee ee 7 15 7 2 26 Sto
21. 8 3 selected ID BIS sits SEE IERE RE e ER seed Oe GELEE EER et de 8 3 Table 8 4 J1 Gofinector PINOUtS is ER RE eN Ee eg ER AR antes GEE ES EE nang ase 8 5 Table 8 5 J1 Connector Signal Descriptions ie ee ee ee AR ee AR ee AR ee ee 8 6 Table 8 6 PCI Bus Edge Connector PinoutS see ees se ee ee es se ee ee ee ke ee ee ke ee ee ee 8 8 Table 8 7 PCI Express Bus Edge Connector PinoutS ees sesse se se ee ee ee ke ee ee ee 8 10 Table 9 1 Ordering die ein en OE OE EE OE RE OE EE 9 1 page x Excalibur Systems Chapter 1 Introduction Chapter 1 Introduction Chapter 1 provides an overview of the EXC 1394PCI and EXC 1394PCle avionics communication boards The following topics are covered Ee VW 62 cid hss EE OO N Ee EE 1 1 GER Ged EE EE EE EE EE EE EE OE 1 2 1 1 2 BIOCKDIAGIAM ME REGEER E ee ER Ee GE tera ates Renee E 1 4 T Z Installato Nene de DE EG DES Ge De oi E 1 5 12 1 Installingthe BoaFds EE ER ER oh ie eter anion SAA Raia 1 5 1 2 2 Installing Excalibur Software Tools ese ee ee ee ee ee Re ee ee ee ee ee ke ee ee ee ee ee ee 1 6 1 3 Technical SUDDORLS N GEE NE EG cheek ae ee Ge ak ae eee 1 6 1 1 Overview The EXC 1894PCle is an intelligent test and simulation board for interfacing with an IEEE 1394 data bus It implements a 1394b physical layer which can operate at 100 200 or 400 Mbps It provides up to three fully independent nodes each node having three full duplex ports associated with it and has a
22. A 10 Vertical Parity Check Read Only 4 2 32 Last STOF Time Tag Registers Address 0130 H Length 48 bits Read Only These three 16 bit registers represent the value of the node s Time Tag at the time the last STOF was transmitted Table 4 27 Last STOF Time Tag Registers Word Description 0 Low 16 bits of Time Tag 1 Middle 16 bits of Time Tag 2 High 16 bits of Time Tag page 4 16 Excalibur Systems Chapter 4 Control Computer Operation 4 2 33 Pointer to Most Recent Message Address 013C H Length 32 bits Read Only This register contains a pointer to the beginning of the last complete message received by the node Table 4 28 Pointer to Most Recent Message Bit Description 00 31 Pointer to sentinel of most recent message in the buffer 4 2 34 Pointer to Least Recent Message Address 0140 H Length 32 bits Read Only This register contains a pointer to the beginning of the oldest complete message received by the node Table 4 29 Pointer to Least Recent Message Bit Description 00 31 Pointer to sentinel of the oldest message in the buffer 4 2 35 Message Type Receive Control Table Between transmissions the CC looks for receive messages These messages are stored in a sequential Linked List A data structure of 6400 by 16 bits contains a CC Receive Control Word for each potential message within each channel This structure is a two dimensional array of 16 bit words indexed by source channel
23. AR Ge ee ee ee ee ee ee ee ee 4 17 4 2 34 Pointer to Least Recent Message ie ee ee se ee Ee ee Re ee ee ee ee ee ee ee 4 17 4 2 35 Message Type Receive Control Table ccccccceceeceeeeeeeeeecaeeeeeeeeesenaees 4 17 4 2 36 GE STOF Offsets Table ssa ia i DER Ge Ge Re net Ned sb ee Ee SEG Gee ean 4 18 4 3 Message AB oe Re N N N e 4 18 4 3 1 CC Transmit Messages iii ei se ee ee AR Ee ee ee ee ee ee Re Re ee ee ee ee ee Re Re ee ee ee ee ee Re de ee 4 18 4 3 2 CG Transmit Stacks isis Ee EE Ee ES EG ieee see eg Ge ee RE Gen eg ie 4 19 4 3 3 CC BARS TER EE EE EE RE AE EE Ee 4 21 4 1 CC Memory Map Table 4 1 page 4 2 Register Name Hardware Revision Register Excalibur Node ID Register Interrupt Status Register Interrupt Mask Register Reset Time Register Reserved Time Tag Low Register Time Tag Middle Register Time Tag High Register Reserved Reset Node Register Reserved Vehicle Time Preload Value Register Reserved Transmit Message Counter Register Reserved Receive Message Counter Register Reserved STOF Message Counter Register Reserved Receive Message Error Counter Register Transmit Message Error Counter Register Discarded Message Counter Register Reserved CC Mode Memory Map Registers Byte Address 0000 H 0002 H 0004 H 0008 H 000C H 000E 000F H 0010 H 0012 H 0014 H 0016 0017H 0018 H 001A 001B H 001C 0020 007F H 0080 H
24. Beginning of Receive Stack Address 00E0 H Length 32 bits Read Only This register contains a pointer to the beginning of the Receive Stack Use this address to access the stack Note This register is not defined when the Linked List is in DPRAM 7 2 20 Pointer to End of Receive Stack Address 00E4 H Length 32 bits Read Only This register contains a pointer to the last byte of the Receive Stack page 7 12 Excalibur Systems Chapter 7 Bus Monitor Operation 7 2 21 Options Register Address OOF4 H Length 32 bits Read Only This register contains information about the node Table 7 17 Options Register Bit Description 02 15 Reserved 01 1 By default the Vehicle Time quadlet of each STOF message is updated before transmission in CC mode When this bit is lit the option to prevent updating the Vehicle Time quadlet is available see CC Run Configuration Register on page 4 13 0 The option to prevent updating the Vehicle Time quadlet of the STOF message before transmission is not available 00 1 Asynchronous mode is available 0 Asynchronous mode is not available 7 2 22 STOF Period Register Address 0100 H Length 16 bits Read Write Use this register to set the period of time in usec within which the STOF is expected to be received The value of this register defaults to 12500 upon power up and reset Table 7 18 STOF Period Register Bit Description 00 15 Period in usec to
25. Buffer to freeze 0 7 Note that the interrupt on end of message which can be set here is reflected in the Interrupt Status Register Bit 29 Table 5 45 describes the buffer size bits Table 5 45 Buffer Size Bits Buffer size Message Buffer size bits ize byt size bytes Bit 12 Bit 11 of the Header of the Header Control Word Control Word 272 528 1040 2064 256 0 0 512 0 1 1024 1 0 2048 1 1 EXC 1394PCI amp EXC 1394PCle User s Manual page 5 25 Chapter 5 Remote Node Operation Table 5 46 describes the fields of the Receive Data Block Status Word Table 5 46 Data Block Header Status Word Bit Description 15 Message in progress 14 No unfrozen buffer when message received message discarded 03 13 Reserved 00 02 Currently active buffer 0 7 Table 5 47 describes the remote node receive data buffer Table 5 47 Data Block Buffer Word Description 0 Buffer Status Word see Table 5 48 1 Reserved 2 4 Time Tag of message 5 Reserved 6 7 1394 Header quadlet 8 15 ASM header Length based on Payload payload length 8 words Packet trailer Note The 1394 Header CRC and 1394 Data CRC are stripped from the packet and are not stored by the node page 5 26 Excalibur Systems Chapter 5 Table 5 48 describes the fields of the Buffer Status Word Table 5 48 Buffer Status Word Bit Description 15 Message complete 14 Message in progress 13 Buffer had to be overwr
26. Chapter 2 PCI Architecture Table 2 12 Interrupt Status Register Bit 04 31 03 02 01 00 Description Reserved set to 0 1 indicates that an interrupt was generated by the General Purpose Timer See Global Timer Registers on page 2 22 1 indicates that node 2 is interrupting 1 indicates that node 1 is interrupting 1 indicates that node 0 is interrupting Note When using DMA this register works together with the DMA Interrupt Status Register See DMA Interrupt Status Register on page 2 14 2 6 4 Address Write On Use thi nterrupt Reset Register 000C H Length 32 bits ly s register to reset the interrupting nodes by writing to the relevant bits of the register Table 2 13 Interrupt Reset Register Bit Description 04 31 Reserved set to 0 03 1 Resets General Purpose Timer interrupt 0 No effect 02 1 Resets node 2 interrupt 0 No effect 01 1 Resets node 1 interrupt 0 No effect 00 1 Resets node 0 interrupt 0 No effect Note When using DMA this register works together with the DMA Interrupt Status Register See DMA Interrupt Status Register on page 2 14 2 6 5 Node Info Registers Address 0010 H Length 32 bits Read Only These registers provide information for each of the 3 channel respectively EXC 1394PCI amp EXC 1394PCle User s Manual page 2 17 Chapter 2 PCI Architecture Table 2 14 Node Info Registers Bit Description 00 02 Node ID 0000 H No
27. High Register esse ee ee ee se ee ee ee Ge ee ee ee ee ee ke ee ee ee ke ee 2 20 2 7 3 IRIG B Time SBS Low Register iese ee ee ee ek Ke ee ee ee ee ee ee Re ee ee ee 2 20 2 7 4 IRIG B Time Days Register ie ees se ee ee ee Re Re Re ee ee ee ee ee ee ee ee ee ee ee 2 21 2 7 5 IRIG B Time Hours Register esse sees es se ee ee ee ee ee ee ee ee ee ke ee ee ee ee ee ke ee ee ee 2 21 2 7 6 IRIG B Time Minutes Register se ee ee ee ee Ee ee Ee ee ee ee ee ee ee ee ee ee ee ee 2 21 2 7 7 IRIG B Time Seconds Register ee se ee ee Re ee ee ee ee ee ee Re ee ee ee 2 21 2 7 8 Control Functions High and Low Registers sis se ee ee ee ee ee ee ee ee ee ee ee 2 21 2 7 9 FPGA Revision Register sessies see Ese Re Es b ede GED ER GREG Ee EN EED ee We be eN GEE eie De 2 21 EXC 1394PCI amp EXC 1394PCle User s Manual page 2 1 Chapter 2 2 8 Global Timer Registers iese Ee De EE SE EE EDE Se 2 8 1 Timer Prescale Register se se ee ee ee Ee Re ee ee ee ee 2 8 2 Timer Preload Register ie ee ee ee ee Ee Re ee ee ee ee 2 8 3 Timer Control Register see ee ee ee Re ee ee ee ee ee ee 2 8 4 General Purpose Timer Register se see ee ee ee ee 2 1 PCI Memory Structure The EXC 1394PCI requests two memory blocks PCI Architecture e The first memory block Base 0 is 8 MB in size and contains the memory space for the nodes on the board For more information see Node Memory Space Map on page 2 14 e The second m
28. If you want to stop the counter and start from the original preload value or from a new preload value this value must to be rewritten EXC 1394PCl amp EXC 1394PCle User s Manual page 2 23 Chapter 2 PCI Architecture to the Timer Preload Register prior to the restarting of the General Purpose Timer Register Note The maximum clock period of the General Purpose Timer is 4295 seconds 1 hour 11 min amp 35 Seconds page 2 24 Excalibur Systems Chapter 3 Node Operation Overview Chapter 3 Node Operation Overview Chapter 3 provides a general overview of the operation of each of the EXC 3 1 1394PCl e nodes Node General Memory Map Each node occupies 2 MB of memory space that is shared between the hardware registers control registers and data blocks Each node can operate in one of the following modes For a description of each mode see Overview on page 1 1 CC mode RN mode Bus Monitor mode Asyncronous mode Table 3 1 indicates which areas of memory are mode specific and which areas are common to all modes Memory maps for each specific mode are provided in the chapters 4 through 7 as well as description of the registers in each mode Table 3 1 Node General Memory Map Register Name Byte Address Hardware Revision Register 0000 H Excalibur Node ID Register 0002 H Interrupt Status Register 0004 H Interrupt Mask Register 0008 H Reset Time Register 000C H Reserved 000E 000F H Time Tag
29. Register Bit Description 00 15 0 Do not use Control Tables 1 Use Message ID Receive Control Table 2 Use Source and Destination Channel Receive Control Table 7 2 34 STOF Offsets Control Register Address 0152 H Length 16 bits Read Write Use this register to turn configure STOF offsets checking When STOF offsets checking is OFF the Monitor Mode Bus Monitor STOF Offsets Table on page 23 is not used When STOF offsets checking is ON STOF timing errors are identified For example it is determined whether a node transmitted at the wrong time that is not at its transmit offset a node did not transmit anything at its transmit offset the CC did not transmit to a node at its receive offset etc The STOF offsets filter window limits the messages recorded to those that come in between these two offsets from the STOF message The size and location of the window are controlled by the STOF Filter Window Begin Register and the STOF Filter Window End Register If your initial STOF frame has different offsets from the others and you do not want STOF offset errors reported for the first frame use the option Ignore STOF offset errors in first STOF frame page 7 18 Excalibur Systems Chapter 7 Bus Monitor Operation Table 7 30 STOF Offsets Control Register Bit Description 15 Use STOF offset filter window 02 14 Reserved 01 Ignore STOF offset errors in first STOF frame 00 Check STOF offsets 7 2 35 STOF Filter W
30. Register Reserved Mode Select Register Start Register Excalibur Node Status Register Port Status Register Reserved Bus Monitor Mode Memory Map Registers Byte Address 0000 H 0002 H 0004 H 0008 H 000C H 000E 000F H 0010 H 0012 H 0014 H 0016 0017H 0018H 001A 0087 H 0088 H 008C 008F H 0090 H 0094 0097 H 0098 H 009C 009F H 00A0 H 00A4 00A7 H 00A8 H 00AC 00AF H 00B0 H 00B4 H 00B8 H OOBC H 00C0 00C3 H Read Write Read Only Read Only Read Write Write 1 to Clear Read Write Read Write Read Only Read Only Read Only Write Only Read Only Read Only Read Only Read Only Read Only Read Write Read Write Read Only Read Only Page Number 7 4 7 4 7 4 7 5 7 6 7 7 7 7 7 7 7 8 7 8 7 8 7 8 7 9 7 9 7 10 Excalibur Systems Chapter 7 Register Name Number of Bad STOF Messages for CC Fail Register Reserved Pointer to Beginning of Receive Linked List Reserved Pointer to Beginning of Receive Stack Pointer to End of Receive Stack Reserved Options Register Reserved STOF Period Register Last STOF Message Status Register Last STOF Message Area Last STOF Time Tag Registers Reserved Store STOF Messages Register Reserved Pointer to Most Recent Message Pointer to Least Recent Message Pointer to Trigger Message Trigger Control Register Trig
31. Status WOrd ee ee ee ee AR ee AR ee AR ee ee 4 20 CC Linked List Structure ees ee ee ee AR ee AR ee AR ee ee ee ee 4 21 CC Receive Message Status Word iese ee ee ee AR ee AR ee ee 4 22 RN Mode Memory Map Registers ee esse ee ee se ee ee ke ee ee ke ee ee ee 5 2 Interrupt Status Register ee ee ee ee ee ee dF TARRAK ee ee ee ee 5 5 Interrupt Mask Register ees ee ee ee ee ee ee Ge ee ek ee ee ee 5 5 Reset Time Register iss es se ee Ge ee Ge ee ee ee ee de ee ee ee 5 6 Time Tag Register S rria RE ued AE Re Ee ER EG ES EN ee neces 5 6 Reset Node Register siese see ge Ge ee ke ee ee Ge ee ke ee AR Ge Ee ee 5 6 Transmit Message Counter Register iese eed ee ee ee ee de ee ee ee 5 7 EXC 1394PCI amp EXC 1394PCle User s Manual page vii Table of Contents Table 5 8 Receive Message Counter Register ie se ee ee ee Re ee 5 7 Table 5 9 STOF Message Counter Register ees esse ees se ee ee ee ke ee Ge ke ee 5 7 Table 5 10 Receive Message Error Counter Register eie se ee se ee ee 5 8 Table 5 11 Transmit Message Error Counter Register iese sees esse ee de ee ee ee 5 8 Table 5 12 Discarded Message Counter Register se ee ee ee ee Re ee 5 8 Table 5 13 Mode Select Register iese E T Ge ee ke ee AE Ee Ee ee 5 9 Table 5 14 Start Register te ses in Re RE ie tat ee eE ea ee DE AS ie tate Ee ee ee 5 9 Table 5 15 Excalibur Node Status Register ees se ee ee ee ee ee ee ke ee ee ke
32. Table 7 20 Last STOF Message Area Quadlet Description 0 1394 Header Word 1 Control Computer Branch Status 2 Network Bus Mode 3 Vehicle State 4 Vehicle Time 5 9 Reserved 10 Vertical Parity Check Note The 1394 Header CRC and 1394 Data CRC are stripped from the packet and are not stored by the node page 7 14 Excalibur Systems Chapter 7 Bus Monitor Operation 7 2 25 Last STOF Time Tag Registers Address 0130 H Length 48 bits Read Only These three 16 bit registers represent the value of the node s Time Tag at the time the last STOF was received Table 7 21 Last STOF Time Tag Registers Word Description 0 Low 16 bits of Time Tag 1 Middle 16 bits of Time Tag 2 High 16 bits of Time Tag 7 2 26 Store STOF Messages Register Address 0138 H Length 16 bits Read Write Use this register to set whether STOF message information will be included in the Receive Message Stack and whether the STOF messages themselves will be included in the Linked List The data associated with the most recent STOF message is always placed in the Last STOF Message Area regardless of which options are selected in this register Table 7 22 Store STOF Messages Register Bit Description 02 15 Reserved 01 1 include STOF messages in Linked List 0 Do not include STOF messages in Linked List 00 1 include STOF messages in Message Stack 0 Do not include STOF messages in Message Stack Note This is only relevant whe
33. Time Tags that are implemented on the modules to other boards or systems See Time Tag Clock Select Register on page 2 18 Not Connected Ground IRIG B120 Input IRIG B120 signals have the following specifications B 100 pulses per second PPS 10 msec count 1 Sine wave carrier amplitude modulated 2 1 kHz carrier wave 1 msec resolution 0 Binary Coded Decimal BCD Control Functions CF depending on the user application Straight Binary Second SBS of day 0 86400 External Time Tag Reset TTL Output This low active signal is activated each time a Global Time Tag Reset is applied Use the signal to synchronize other boards or systems to the Time Tags that are implemented on the modules This signal is activated by either the internal Global Time Tag signal see Software Reset Register on page 2 16 or from the External Time Tag signal EXTTRSTn 2 External Time Tag Clock TTL Output 1 MHz This signal is the Global Clock that is supplied to all the modules for their Time Tags Use the signal to synchronize other boards or systems to the Time Tags that are implemented on the modules The source of this clock is either the External Time Tag Clock EXTTCLKI or the Internal Time Tag Clock See Time Tag Clock Select Register on page 2 18 2 See Synchronization with External Sources on page 8 11 and Synchronizing Between EXC 1394PCl e Boards on page 8 12 page 8 6 Excalibur Systems Chapter 8 Pin 3 4
34. Words 5 and 6 of the Transmit Handshake Registers message size and receive timeout are supplied by the user when creating the transmit message Word 0 Control Word is supplied by the user to notify the firmware that a transmit message is ready to be sent Words 2 4 Time Tag are supplied by the firmware at the time that the message is queued for transmission Words 1 and 7 Status Word and Ack code are supplied by the firmware when the a message is received in response or the timeout period was reached EXC 1394PCI amp EXC 1394PCle User s Manual page 6 11 Chapter 6 Table 6 15 Transmit Handshake Registers Word Description Control Word see Table 6 16 on page 6 12 Status Word see Table 6 17 on page 6 12 4 Time Tag of transmission 48 bits 0 1 Di 5 Size of message in quadlets including message header 6 Receive timeout in milliseconds 7 5 bit Ack code 4 bits from the standard 1 bit of extra information see Table 6 18 on page 6 13 8 15 Reserved Table 6 16 Control Word Bits Bit Description 15 Fresh data 00 14 Reserved Table 6 17 Status Word Bits Bit Description 15 Message queuing complete 14 Message queuing in progress 01 13 Reserved 00 Message error timed out waiting for message to queue page 6 12 Asynchronous Operation Excalibur Systems Chapter 6 Asynchronous Operation Table 6 18 Ack Codes Ack Code Name 00000 Reserved 00001 Ack_complete 00010 Ack_pendin
35. as of the date of shipping Software and documentation updates can be found and downloaded from our website www mil 1553 com The standard software provided with Excalibur boards and modules is for Windows operating systems Software for other operating systems may be available Check on our website or write to excalibur mil 1553 com Technical Support Excalibur Systems is ready to assist you with any technical questions you may have For technical support see the Technical Support section of our website www mil 1553 com You can also contact us by phone To find the location nearest you see the Contact section of our website page 1 6 Excalibur Systems Chapter 2 PCI Architecture Chapter 2 PCI Architecture Chapter 2 describes the PCI architecture The following topics are covered 2 1 PCLMemory StrUct rS vi issie Sens cerieenicerSecniiendssntteridenideniaeeds 2 2 2 2 PCI Configuration Space Header esse ee ee ee eke ee ee ee ee ee ee ee ee ee 2 2 2 3 PCI Configuration Registers iese ee ee ee 2 4 2 3 1 Vendor Identification Register VID c ccccceeeeeceeceeceeeeeseeeeeaeeeeeeeseeseaeeeeees 2 4 2 3 2 Device Identification Register DID for PCI oo ee ee ee ee ee ee Re ee ee 2 4 2 3 3 PCI Command Register PCICMD ee ee ee ee ee ee Re GR ee ee Re ee ee ee 2 4 2 34 PCI Status Register PCISTS ee ee ee ee ee Ge AA ee Ge ee ee ee ee ee 2 5 2 3 5 Revision Identification Register RID
36. but was not yet set into an operational mode Remote Node RN Mode Control Computer CC Mode Bus Monitor Mode Asynchronous Mode 4 2 18 Start Register Address 00B4 H Length 32 bits Read Write Use this register to start and stop the operations of the node Table 4 15 Start Register Bit Description 01 31 Reserved 00 1 Start Operation 0 Stop Operation 4 2 19 Excalibur Node Status Register Address 00B8 H Length 32 bits Read Only Control Computer Operation This register indicates the current status of the node It also provides power on self test information page 4 10 Excalibur Systems Chapter 4 Table 4 16 Excalibur Node Status Register Bit Description 31 Reserved 30 Message fragment detected the receive FIFO 29 17 28 16 05 15 04 03 02 01 00 had part of a message There was probably an overrun or other technical glitch in receiving Out of frame message received received a message before first STOF or after missing STOFs Reserved Wrong LLC version indicates that the link layer chip had technical difficulties Reserved 1 Running 0 Halted 1 Self Test Passed 0 Self Test Failed Reserved 1 RAM test passed 0 RAM test failed 1 Ready 0 Not ready 4 2 20 Port Status Register Address OOBC H Length 32 bits Read Only This register indicates the status of the three ports EXC 1394PCI amp EXC 1394PCle Us
37. ee Re ee Ee ee ke ee ee 7 19 7 2 36 STOF Filter Window End Register esse see ese se ee ee ee ee ee ee Re ee ee Ee ee ee ee ke ee ee 7 19 7 2 37 Memory Select Register ius se EES Ee OE BEd ee EE Ge GEE Seed Ke Ee de Se eg ee Gee ee 7 20 7 2 38 Bank SelectRegister i s ER Rd es Ee a a De EED ERG De Ges Ee ENE 7 20 7 2 39 Current Bank Register esse eitant egea EE RE ee EER Geb GR REK Se 7 21 7 2 40 PHY Base Registers ike Ee De ke kes Gee Ene ee oer Be KERE Wee ee es 7 21 7 2 41 PHY Port 0 Status Registers eee es se ee ee ee ee ee ke ee ee ee ee ee ee ee ke ee ee ee 7 21 7 2 42 PHY Port 1 Status Registers esse se ese ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee 7 21 7 2 43 PHY Port 2 Status Registers sesse ees es se ee ee ee ee ee ke ee a ee ee ee ee ee ke ee ee ee 7 22 7 2 44 Monitor Control Tables ee ee ek ee ee ee ee AR Ke ee ee ee ee ee ee Re ee ee ee 7 22 7 2 45 Bus Monitor STOF Offsets Table occ se ee ee ee Re ee ee ee ee ee Ge Re ee ee ee 7 23 7 2 46 BETER Nee NE OR EE EE OE N EE EER E 7 24 1 Messade red idee ee aee ee de ed ee Oe 7 26 7 3 1 Bus Monitor Receive StackK ies es se ee Ee AA ER AA Ee EA AR ER RR ee ee Ee Re ee ee ee ee 7 26 7 3 2 Bus Monitor Linked List iii eise Ee Ee Re RE ee see ee AR ee EE Se Ge ee RE soe ee Keer gee ek ee 7 27 7 3 3 Banked Window into SDRAM ee ee ee ee ee ee ee ee ee ee Ke ee ee ee ee ee ee ee 7 31 Chapter 8 Mechanical and Electrical Specifications 8 1 Board
38. ee ede ee 7 21 7 2 42 PHY Port 1 Status Registers EE EE DEE i ui ee Ge eg ekke See ee ee Ee 7 21 7 2 43 PHY Port 2 Status Registers eee es se ee ee ee ee ee ke ee ee ke ee ee ee ee ee ke ee ee ee 7 22 EXC 1394PCI amp EXC 1394PCle User s Manual page 7 1 Chapter 7 Bus Monitor Operation 7 2 44 Monitor Control Tables sis esse ee ee Dee ed ee Ee Ge SG EE DU Pe Se Vo A Ve Ge 7 22 7 2 45 Bus Monitor STOF Offsets Table iese se se ee ee ee ee ee ee ee ee Re ER ee ee ee ee ee Re Re ee ee 7 23 7 2 46 Data Mee AE lo ER AE ROL GE EI OK EEN 7 24 1 3 Message Aledo ioc EA eee eee ee ae teat 7 26 7 3 1 Bus Monitor Receive StaCK ees ss ee ee ee ee EE ee ee Re ER ee ee Re ER ee ee ee ee ee Re Re ee ee 7 26 1 3 2 Bus Monitor Linked List sisie se ES Ge N ee Syed ROG So Ge ig ee ie pe Ges eggs ese 7 27 7 33 Banked Window into SDRAM cccccccccccsccecesececececeeececeseeeseceseeeeaeeseeeeeueeaeass 7 31 7 1 Bus Monitor Memory Map Table 7 1 page 7 2 Register Name Hardware Revision Register Excalibur Node ID Register Interrupt Status Register Interrupt Mask Register Reset Time Register Reserved Time Tag Low Register Time Tag Middle Register Time Tag High Register Reserved Reset Node Register Reserved Receive Message Counter Register Reserved STOF Message Counter Register Reserved Receive Message Error Counter Register Reserved Discarded Message Counter Register Reserved Firmware Revision
39. ee ee AR Ee AA ee ee ee ee ee ek ee ee ee 6 4 Table 6 4 Reset Time Register seeni anaana E TERE AEE Ge ee Ge RA ee Re 6 5 page viii Excalibur Systems Table of Contents Table 6 5 Time Tag Registers ss EE des deed peed eigen Need ee eed eners ee 6 5 Table 6 6 Receive Message Counter Register ee ee ee ee ke ee 6 5 Table 6 7 Receive Message Error Counter Register ee se ee se ee ee 6 6 Table 6 8 Discarded Message Counter Register ese ee ee ee ee ke ke ee 6 6 Table 6 9 Mode Select Register sesse sees se ee ee RA Ee ee Ee Ee ee ed ee Ge ee Ge RE ee ee 6 7 Table 6 10 otart Registers ethene GEL lsat ane ER EE Oe GEL Ge GE Te ete 6 7 Table 6 11 Excalibur Node Status Register ee se ee ee ee Ee Re ee ee ke ee ee ee 6 8 Table 6 12 Port Status Register sees ee se e Ge ER Ge Ee ee Ee ee Ee ee ee ee 6 9 Table 6 13 Port opeed Bits iis des ee NS GER ranches sa Re Eg ge BEE RE De eg 6 9 Table 6 14 Options AG EER EE AO RE 6 10 Table 6 15 Transmit Handshake Registers iis sees se ee de ee se ee ee ee ee ee de ee ee ee de ee 6 12 Table 6 16 Control Word Bits 0 0 0 ee ee ee ee ee ee AR ee AR ee AR ee AR ee AR ee ee 6 12 Table 6 17 Status Word Bits ie GE Ee SE gee a lial a ee gese ee ee de 6 12 Table 6 18 ACK Codes EE RR A AA ee ee 6 13 Table 6 19 1394 Header and Data Area ese esse ee ee se ee ee Re ee ee Re ee ee ke ee ee ee 6 13 Table 6 20 Receive Message Information Registers ie ee ee ee ee ee 6 14 T
40. for filtering interrupting and triggering on subsets of messages The active table depends upon the settings in the Control Table Selection Register on page 7 18 Message Type Receive Control Table This Control Table contains 6400 16 bit word entries and is indexed by source channel number and message number It allows filtering by source channel and message number and allows interrupts and triggers to be generated upon receipt of specific message types Source and Destination Channel Receive Control Table This Control Table contains 4096 16 bit word entries and is indexed by source channel number and destination channel number It allows filtering by message path by any combination of source and destination channels and it allows interrupts and triggers to be generated upon receipt of messages directed to or from a specific channel or channels Control Table Fields Each Control Table entry consists of one 16 bit Control Word which controls behavior of the node upon receipt of a message Table 7 36 describes each entry in the Monitor Mode Receive Control Table Table 7 36 Monitor Mode Receive Control Table Bit Description 05 15 Reserved 04 Trigger on end of message 03 Store Do not Store 02 Reserved 01 Interrupt on end of message 00 Reserved When the Bus Monitor receives a message matching a Control Table entry with the trigger bit set it acts according to the Trigger Position Register setting page 7 22 Excali
41. hours at 25 C Gr S217F For PCI Express 70 480 hours at 25 C Gr S217F Host Interface e PCIPCIe compliance For PCI Master Target 16 32 bit 33 MHz clock speed For PCI Express x1 lane PCle v1 1 e Memory space occupied 8 MB e Interrupts For PCI INTA For PCI Express INTA Virtual Wire e Power For PCI 1 8A 5V For PCI Express 2 1A 3 3V Software Support e C drivers with source code e Exalt Plus Excalibur Analysis Laboratory Tools optional See Ordering Information on page 9 1 for the exact part numbers EXC 1394PCI amp EXC 1394PCle User s Manual page 1 3 Chapter 1 Introduction 1 1 2 Block Diagram PCI J1 BUS N Port 0 Port 1 Node 0 ti gt Port 2 Add iq PCI Bus Addr Data Interface Pata 9 Cntrl lt gt Catrl_ 6 Port 0 O W Port 1 zZ ri Node 1 gt z N Port 2 O O gt Port 1 Node 2 ay Port 2 Figure 1 1 EXC 1394PCI Block Diagram page 1 4 Excalibur Systems Chapter 1 PCI EXPRESS BUS HSI pI HSO PCle Bus Interface Node 0 REFCLK N Port 0 Port 1 Port 2 o gt Node 1 N Port 0 Port 1 J Port 2 gt Node 2 N Port 0 Port 1 Port 2 ao Figure 1 2 EXC 1394PCle Block Diagram 1 2 Installation To operate the EXC 1394PCl e board e Install the board in your computer e Install the So
42. me EE EER ona oe lac aged Rae Ee ee BEE RE 7 13 Table 7 18 STOF Period Register ee se ee ee ee AR ee AR ee ee ee ee ee ee 7 13 Table 7 19 Last STOF Message Status Register ie ees se ee ee ee ee ke ee 7 14 Table 7 20 Last STOF Message Area iese esse ee ese dee ee ee ee Se ee ee ee ee ee dee ee 7 14 Table 7 21 Last STOF Time Tag Registers eie ees se ee ee Ge ke ee ee ee ke ee ee ke ee 7 15 Table 7 22 Store STOF Messages Register ees ee ee de ee ee ee ee ee ee ee 7 15 Table 7 23 Pointer to Most Recent Message ee se ee ee ke ee ee ee ke ee ee ke ee 7 15 Table 7 24 Pointer to Least Recent Message ee ee ee ee ee Ke ee ee ke ee 7 16 Table 7 25 Pointer to Trigger Message ee ee ee ee ke ee ee ke ee Ge ke ee ee ke ee 7 16 Table 7 26 Trigger Control Register see ee ee Ee AA Re AA ee ee ee ee ee 7 17 Table 7 27 Trigger Position Register neiere eE ee ETARE ee ee ATEA 7 17 EXC 1394PCI amp EXC 1394PCle User s Manual page ix Table of Contents Table 7 28 Linked List Fill Control Register ees se ee se ee ee ke ee ee ke ee 7 18 Table 7 29 Control Table Selection Register ee ee ee ee ee AR ee AR ee ee 7 18 Table 7 30 STOF Offsets Control Register ees ee ee ee ee AR ee ee ee ee 7 19 Table 7 31 STOF Filter Window Begin Register ees dee ee ee ee ee ee ee ee ee 7 19 Table 7 32 STOF Filter Window End ees se ee ee ee ee ee ee ee ee ee ee ee ee ee ee 7 19 Table 7 33 Memory Select Register ees ee se k
43. messages in Message Stack 0 Do not include STOF messages in Message Stack 5 2 33 Receive STOF Offset Register Address 0300 H Length 32 bits Read Write Use this register to select the default receive STOF offset in usec upon starting the node If the first message received from the Control Computer contains a newer value the newer value will be used in all future STOF messages instead of the value in this register Note This value may be overridden by the STOF offset values in the first packet received by the RN from the CC Table 5 28 Receive STOF Offset Register Bit Description 00 31 Receive STOF offset 5 2 34 Transmit STOF Offset Register Address 0304 H Length 32 bits Read Write Use this register to select the default transmit STOF offset in psec upon starting the node If the first message received from the Control Computer contains a newer value the newer value will be used in all future STOF messages instead of the value in this register Note This value may be overridden by the STOF offset values in the first packet received by the RN from the CC Table 5 29 Transmit STOF Offset Register Bit Description 00 31 Transmit STOF offset page 5 16 Excalibur Systems Chapter 5 Remote Node Operation 5 2 35 Datapump STOF Offset Register Address 0308 H Length 32 bits Read Write Use this register to select the default Datapump STOF offset in usec upon starting the node If the first message rec
44. of the beginning of the received Linked List 4 2 26 Pointer to End of Receive Linked List Address 00DC H Length 32 bits Read Write Use this register to specify the address of the end of the received Linked List 4 2 27 Speed Code Register Address 00F0 H Length 16 bits Read Write Use this register to select the communications speed of the node Table 4 21 Speed Code Register Bit Description 02 15 Reserved 00 01 Speed Code Table 4 22 Speed Code Bits 0 100 Mbps 0 0 200 Mbps 0 1 400 Mbps 1 0 Not Supported 1 1 page 4 14 Excalibur Systems Chapter 4 Control Computer Operation 4 2 28 Options Register Address OOF4 H Length 32 bits Read Only This register contains information about the node Table 4 23 Options Register Bit Description 02 15 Reserved 01 1 By default the Vehicle Time quadlet of each STOF message is updated before transmission in CC mode When this bit is lit the option to prevent updating the Vehicle Time quadlet is available see CC Run Configuration Register on page 4 13 0 The option to prevent updating the Vehicle Time quadlet of the STOF message before transmission is not available 00 1 Asynchronous mode is available 0 Asynchronous mode is not available 4 2 29 STOF Period Register Address 0100 H Length 16 bits Read Write Use this register to set the period of time in usec within which the STOF is expected to be received The value of th
45. register to reset the node Table 5 6 Reset Node Register Bit Description 01 15 Reserved 00 Reset Node resets the node clears the control registers and resets the Time Tag page 5 6 Excalibur Systems Chapter 5 Remote Node Operation 5 2 8 Transmit Message Counter Register Address 0080 H Length 32 bits Read Only This register contains a running counter of all messages transmitted by the node It is reset to 0 upon power up node reset and when the node is started Table 5 7 Transmit Message Counter Register Bit Description 00 31 Number of messages transmitted by the node 5 2 9 Receive Message Counter Register Address 0088 H Length 32 bits Read Only This register contains a running count of all messages received and stored by the node It does not include STOF messages which are counted separately It does not include messages which did not pass the filters and thus were not saved It is reset to 0 upon power up node reset and when the node is started Table 5 8 Receive Message Counter Register Bit Description 00 31 Number of messages received and stored by the node 5 2 10 STOF Message Counter Register Address 0090 H Length 32 bits Read Only This register contains a running count of all STOF messages received by the node It is reset to 0 upon power up node reset and when the node is started Table 5 9 STOF Message Counter Register Bit Description 00 31 Number of STOF mes
46. 04 GROUND AD 02 AD 00 5V REQ64 5V 5V page 8 9 Chapter 8 8 4 3 Table 8 7 Pin Signal Name 1 12V 2 12V 3 RSVD 4 GND 5 SMCLK 6 SMDAT 7 GND 8 3 3V 9 JTAG1 10 3 3Vaux 11 WAKE 12 RSVD 13 GND 14 HSOp 15 HSOn 16 GND 17 PRSNT 2 18 GND page 8 10 PCI Express Bus Edge Connector Pinouts Side B Connector Description 12 volt power 12 volt power Reserved Ground SMBus clock SMBus data Ground 3 3 volt power TRST 3 3 volt auxiliary power Link reactivation Mechanical and Electrical Specifications PCI Express Bus Edge Connector Pinouts Signal Name PRSNT 1 12V 12V GND JTAG2 JTAG3 JTAG4 JTAGS 3 3V 3 3V PWRGD MECHANICAL KEY Reserved Ground Transmitter lane differential pair Ground Hot plug detect Ground GND REFCLK REFCLK GND HSIp HSIn GND Side A Connector Description Hot plug presence detect 12 volt power 12 volt power Ground TCK TDI TDO TMS 3 3 volt power 3 3 volt power Power good Ground Reference clock differential pair Ground Receiver lane differential pair Ground Excalibur Systems Chapter 8 Mechanical and Electrical Specifications 8 5 Synchronization with External Sources To synchronize an EXC 1894PClle board to an external system the external clock source and the external reset must be connected to the EXTTCLKI and the EXTTRSTn signals respectively SYNCHRONIZATION CLOCK OUT EXTTCLKI EXTERN
47. 1 Asynchronous mode is available 0 Asynchronous mode is not available page 6 10 Excalibur Systems Chapter 6 Asynchronous Operation 6 3 Message Area The Asynchronous mode has e Asynchronous Transmit Message Area e Asynchronous Stream Transmit Message Area e Asynchronous Receive Message Area 6 3 1 Asynchronous Transmit Message Areas There are two Transmit Message areas e The Asynchronous Transmit Message Area is located at 1000 181F H This area is for all Asynchronous messages except for Asynchronous Stream messages e The Asynchronous Stream Transmit Message Area is located at 5000 581F H This area is for Asynchronous Stream messages Both Transmit Message areas have the same structure There are three main sections e Handshake Register Area The data in these registers 1s necessary to communicate with the firmware but are not transmitted with the message e 1394 Header The 1394 Header is transmitted with the message e Data Area The Data Area is transmitted with the message Its contents vary depending on the type of Asyncronous message Note The data area must not contain the header CRC or the data CRC They are automatically generated by the firmware Tables 6 15 through 6 19 list the information related to a transmit message This information is comprised of e Transmit Handshake Registers e 1394 Header and Data Area The Transmit Handshake Registers are described in Table 6 15
48. 1 PCI Configuration Space Header for PCI MAX_LAT MIN_GNT Interrupt Pin 003C H 0038 H Cap pointer 0034 H 0030 H Subsystem Vendor ID 002C H 0028 H 0024 H 0020 H 001C H oeo or rof BIST Cache Line Size 000C H nt i a ajae oje Figure 2 2 PCI Configuration Space Header for PCI Express EXC 1394PCI amp EXC 1394PCle User s Manual page 2 3 Chapter 2 2 3 PCI Architecture PCI Configuration Registers 2 3 1 Vendor Identification Register VID Address 0000 H Length 16 bits Read Only This register contains the PCI Special Interest Group vendor identification number assigned to Excalibur Systems The value at power up is 1405 H 2 3 2 Device Identification Register DID for PCI Address 0002 H Length 16 bits Read Only This register contains the board s device identification number For PCI The value at power up is 1394 H For PCI Express The value at power up is EFOO H 2 3 3 PCI Command Register PCICMD Address 0004 H Length 16 bits Read Only This register contains the PCI Command Table 2 1 PCI Command Register Bit Bit Name Description 10 15 Reserved Set to Os 09 Fast Back to Back Enable Always set to 0 08 System Error Enable Always set to 0 07 Address Stepping Support For PCI Always set to 1 For PCI Express Always set to 0 06 Parity Error Enable Always set to 0 05 VGA Palette Snoop Enable Always set to 0 04 Memory Write a
49. 11 Table 4 12 Table 4 13 Table 4 14 Table 4 15 Table 4 16 Table 4 17 Table 4 18 Table 4 19 Table 4 20 Table 4 21 Table 4 22 Table 4 23 Table 4 24 Table 4 25 Table 4 26 Table 4 27 Table 4 28 Table 4 29 Table 4 30 Table 4 31 Table 4 32 Table 4 33 Table 4 34 Table 4 35 Table 4 36 Table 4 37 Table 5 1 Table 5 2 Table 5 3 Table 5 4 Table 5 5 Table 5 6 Table 5 7 Table of Contents Node General Memory Map see ese ee ee ee Ge Re ee Ge Re ee ee Re ee ee ee 3 1 CC Mode Memory Map Registers ees se ee ee ee ke ee ee ke ee Ge ke ee 4 2 Interrupt Status Register ee ee ee de AA ee ee Ge ee ee ee ke ee ee ee 4 5 Interrupt Mask Register ees eed ee ee ee ee ee ee ee ee ee ee ee 4 6 Reset Time Register dee Se ee Se ERA Ee ee EE Ee ee ER dee Ge ee Ge RE ee ee 4 6 Time Tag Registers isi BR EE KERE esa GEWESE ER SE ER EK SEDES Reg Eeden 4 7 Reset Node Register iis ese ee ee AE ee ee Re ee ee ee ee de ee ee 4 7 Vehicle Time Preload Value ee ee AR Ee AR ee ee ee ee 4 7 Transmit Message Counter Register iese eed ee ee de ee ee ee ee ee 4 7 Receive Message Counter Register ie ee se ee ee ee Re ee 4 8 STOF Message Counter Register ees esse ee ee ee ke ee ee ke ee Ge ke ee 4 8 Receive Message Error Counter Register eie se ee se ke ee ee 4 8 Transmit Message Error Counter Register esse sees esse ee de ee ee ee 4 9 Discarded Message Counter Register ese ee ee ee e
50. 1TPAOL OTPA2H Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 J1 Connector Pinouts Signal OTPA2L OTPA1H OTPA1L OTPAOH OTPAOL N C GND IRIGBIN SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD EXC 1394PCI amp EXC 1394PCle User s Manual Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Mechanical and Electrical Specifications Signal SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD SHIELD EXTTRSOn EXTTCLKO 2TPB2H 2TPB2L Pin 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Signal 2TPB1H 2TPB1L 2TPBOH 2TPBOL 1TPB2H 1TPB2L 1TPB1H 1TPB1L 1TPBOH 1TPBOL OTPB2H OTPB2L OTPB1H OTPB1L OTPB1H OTPB1L page 8 5 Chapter 8 Mechanical and Electrical Specifications J1 Connector Signal Descriptions Table 8 5 Pin 1 21 22 23 24 43 44 J1 Connector Signal Descriptions Signal Name EXTTRSTn EXTTCLKI N C GND IRIGBIN SHIELD EXTTRSOn EXTTCLKO Description External Time Tag Reset TTL Input Use this low active pulsed signal minimum 100 nsec wide to simultaneously reset the Time Tags of all the modules from an external source Use the signal to synchronize these Time Tags to other boards or systems External Time Tag Clock TTL Input Nominal value 1 MHz This signal supplies an external global clock for the Time Tags of all the modules Use the signal to synchronize the
51. 25 26 45 46 5 6 27 28 47 48 7 8 29 30 49 50 9 10 31 32 51 52 11 12 33 34 53 54 13 14 35 36 55 56 15 16 37 38 57 58 17 18 39 40 59 60 19 20 41 42 61 62 Signal Name 2TPA2H 2TPA2L 2TPB2H 2TPB2L 2TPA1H 2TPAIL 2TPB1H 2TPB1L 2TPAOH 2TPAOL 2TPBOH 2TPBOL 1TPA2H 1TPA2L 1TPB2H 1TPB2L 1TPA1H 1TPA1L 1TPB1H 1TPB1L 1TPAOH 1TPAOL 1TPBOH 1TPBOL OTPA2H OTPA2L OTPB2H OTPB2L OTPA1H OTPA1L OTPB1H OTPB1L OTPAOH OTPAOL OTPBOH OTPBOL Description Rx Rx Reference Shield Txt Tx Rx Rx Reference Shield Tx Tx Rx Rx Reference Shield Tx Tx Rx Rx Reference Shield Tx Tx Rx Rx Reference Shield Tx Tx Rx Rx Reference Shield Tx Tx Rx Rx Reference Shield Tx Tx Rx Rx Reference Shield Tx Tx Rx Rx Reference Shield Txt Tx EXC 1394PCI amp EXC 1394PCle User s Manual Mechanical and Electrical Specifications Node 2 Port 2 1394B Node 2 Port 1 1394B Node 2 Port 0 1394B Node 1 Port 2 1394B Node 1 Port 1 1394B Node 1 Port 0 1394B Node 0 Port 2 1394B Node 0 Port 1 1394B Node 0 Port 0 1394B page 8 7 Chapter 8 PCI Bus Edge Connector Pinouts 8 4 2 Table 8 6 Pin Signal Name B1 12V B2 TCK B3 GROUND B4 TDO B5 5V B6 5V B7 INTB B8 INTD B9 PRSNT1 B10 RESERVED B11 PRSNT2 Eis CONNECTOR KEY B14 RESERVED B15 GROUND B16 CLK B17 GROUND B18 REQ B19 5V I O B20 AD 31 B21 AD 29
52. 3 5 Table 8 3 Selected ID Bits Selected ID Bit 1 Bit 2 Bit 3 Bit 4 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 Figure 8 3 DIP Switch SW1 with All Switches Set to ON Select ID 0 EXC 1394PCI amp EXC 1394PCle User s Manual page 8 3 Chapter 8 Mechanical and Electrical Specifications 8 4 Connectors The EXC 1394PCl e board contains the following connectors e One 62 pin communications I O connector e One PCI Bus Edge connector 8 4 1 Communications I O Connector J1 The EXC 1394PCl e contains all communication I O signals on one female 62 pin right angle connectors J1 P N CONEC 164A20959X A mating connector P N 163A16629X and a plastic hood are included The connector pinouts and signal descriptions are described below O N A N 2 e e e e e e e e e e e e e e e e e e e e e eoeoceoeoececeeeeeeeeeeeee Neeeeeeeeeeeeeeeeeeeee A Go an Figure 8 4 Connectors J1 Layout Front View Each node s signals are grouped together on the connector All external signals are contained on connector J1 except for External Trigger which is grouped with each node s signals Pinouts and signal descriptions are listed in Table 8 4 and Table 8 5 page 8 4 Excalibur Systems Chapter 8 J1 Connector Pinouts Table 8 4 Pin O N DO BU ND 11 12 13 14 15 Signal EXTTRSTn EXTTCLK 2TPA2H 2TPA2L 2TPA1H 2TPA1L 2TPAOH 2TPAOL 1TPA2H 1TPA2L 1TPA1H 1TPA1L 1TPAOH
53. 4 When reading address 10 the Time Tag registers are frozen reading address 14 unfreezes them page 4 6 Excalibur Systems Chapter 4 Control Computer Operation Table 4 5 Time Tag Registers Address Description 10 Low 16 bits of Time Tag 12 Middle 16 bits of Time Tag 14 High 16 bits of Time Tag 4 2 7 Reset Node Register Address 0018 H Length 16 bits Write Only Use this register to reset the node Table 4 6 Reset Node Register Bit Description 01 15 Reserved 00 Reset Node resets the node clears the control registers and resets the Time Tag 4 2 8 Vehicle Time Preload Value Register Address 001C H Length 32 bits Read Write Use this register to set the initial default value of the vehicle time timer that will be used when the timer is reset The vehicle time is in units of 25 usec Table 4 7 Vehicle Time Preload Value Bit Description 00 32 Vehicle time 42 9 Transmit Message Counter Register Address 0080 H Length 32 bits Read Only This register contains a running count of all messages transmitted by the node It is reset to 0 upon power up node reset and when the node is started Table 4 8 Transmit Message Counter Register Bit Description 00 31 Number of messages transmitted by the node EXC 1394PCI amp EXC 1394PCle User s Manual page 4 7 Chapter 4 Control Computer Operation 4 2 10 Receive Message Counter Register Address 0088 H Length 32 bits Read Only Thi
54. 5 7 5 2 11 Receive Message Error Counter Register iss ee ees ee ee se ee ee ee ee ee ede ee 5 7 5 2 12 Transmit Message Error Counter Register see esse ees se ke ee ee ee ek ke ee ee 5 8 5 2 13 Discarded Message Counter Register ee se ee ee ek ee ee Re ee ee ee 5 8 5 2 14 Firmware Revision Register ees see ee ee ek ee ee ee ee ee ek ke ee ee Re ee ee ee 5 8 5 2 15 Pointer to Current Entry of Transmit Stack iis see ee ee ee ee ee se ee ee ee ee ee ee ede ee 5 8 5 2 16 Mode Select Register sn n se ee hie Niel Ge Be Se DS See 5 9 5 2 17 Start EG eN EE OE RE ER HE EL 5 9 5 2 18 Excalibur Node Status Register sesse ee ek ee ee Re ee ee ek ke ee Ge Re ee ee ee 5 9 5 2 19 Port Status Registers ses EE sg Ee See ees gee Wie ee i DE ge Ee ee 5 10 5 2 20 Number of Bad STOF Messages for CC Fail Register sesse ees ee 5 12 5 2 21 1394 NodeID Registef rini GEE RE Red EE EE ED ER ee ee ee ae Ge EG Ge 5 12 5 2 22 Pointer to Beginning of Transmit Stack ie se ee ee ee ee ee Ee ee ee ee ee ee 5 12 5 2 23 Pointer to Beginning of Datapump Stack eee ee ee ee Ge ee ee Re ee ee ee 5 12 5 2 24 Pointer to Beginning of Receive Stack ii se ee ee RA Re Ee ee ee ee ee ee 5 12 5 2 25 Pointer to End of Receive StacK ees see ee ee ee ek ee ee ee Re ee ee ee ee ee ke ee ee ee 5 13 5 2 26 speed Code Register sc iS RE fendi Gees Gag SG GE Seed EE De Se De SEA 5 13 5 2 27 Options Register 2 0 0 2 se ee ee ee Ge AA cece
55. 94 header length Bad VPC Message error an error occurred specified in one of the other bits 7 3 3 Banked Window into SDRAM The node supports 128 MB of SDRAM You can select to use SDRAM via the Memory Select Register on page 7 20 When using SDRAM you can view 1 MB blocks of SDRAM when the node is stopped via the Bank Select Register When you activate this register the node copies the SDRAM to the DPRAM in addresses 100000 H to 1FFFFF H You can check which SDRAM bank is currently displayed in the DPRAM window via the Current Bank Register For more information see the Bank Select Register on page 7 20 and the Current Bank Register on page 7 21 EXC 1394PCI amp EXC 1394PCle User s Manual page 7 31 Chapter 8 Mechanical and Electrical Specifications Chapter 8 Mechanical and Electrical Specifications Chapter 8 describes the mechanical and electrical specifications of the EXC 1394PCl e The following topics are covered 9 1 Board EOE ogee pce eee ED EE AO OD 8 1 8 2 LED Indicators c2 cccdasacaiesssadesscanasasabsnadalatecaeasacinateldecdeatasieebasadibtess 8 2 8 3 DIP Switches ese ee ee Ee ee ee Ee ee ee ee ee ee Ee ee ee ee ee ee 8 3 8 3 1 Selected ID DIP Switch SW1 e ee ee ee ee ee ee ee ee ee ee ee ee 8 3 8 4 Connectors os eise ee N ai Re Pe Go De ES 8 4 8 4 1 Communications I O Connector U1 oo ee ee eee see ee ee AR Ke ee Ee Re ee ee ee ee ee ke ee ee 8 4 8 4 2 PCI Bus Edge Connector Pino
56. AL SYSTEM EXC 1394PCI SYNCHRONIZATION RESET OUT EXTTRSTn Figure 8 5 Synchronization of an EXC 1394PCl e Board to an External System To synchronize an external system to an EXC 1394PClI e board the EXTTCLKO and the EXTTRSOn signals need to be connected to the external clock source and the external reset respectively SYNCHRONIZATION CLOCK EXTTCLKO EE EXC 1394PCI SYSTEM SYNCHRONIZATION RESET EXTTRSTOn Figure 8 6 Synchronization of an External System to an EXC 1394PCl e Board Note The synchronization clock and reset signals may be connected to multiple targets to achieve system wide synchronization EXC 1394PCl amp EXC 1394PCle User s Manual page 8 11 Chapter 8 8 6 Synchronizing Between EXC 1394PCl e Boards Mechanical and Electrical Specifications To synchronize multiple EXC 1394PCI e boards the EXTTCLKO and the EXTTRSOn signals of one board need to be connected to all the EXTTCLKI and the EXTTRSTn signals respectively of the remaining boards EXTTCLKO EXC 1394PCI SELECTED ID 0 EXTTRSOn Figure 8 7 Synchronization Between EXC 1394PCl e Boards 8 7 Power Requirements EXTTCLKI EXC 1394PCI SELECTED ID1 EXTTRSTn EXTTCLKI EXC 1394PCI SELECTED ID 2 EXTTRSTn The typical power requirements for the EXC 1394PCI and EXC 1894PCle boards are as follows For PCI 1 8A 5V For PCI Express 2 1A 3 3V page 8 12 Excalibur Syste
57. B22 GROUND B23 AD 27 B24 AD 25 B25 3 3V B26 CIBEISW B27 AD 23 B28 GROUND B29 AD 2 B30 AD 19 B31 3 3V B32 AD 17 B33 C BE 2 B34 GROUND B35 IRDY B36 3 3V page 8 8 Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 Mechanical and Electrical Specifications PCI Bus Edge Connector Pinouts Signal Name TRST 12V TMS TDI 5V INTA INTC 5V RESERVED 5V RESERVED CONNECTOR KEY RESERVED RST 5V GNT GROUND RESERVED AD 30 3 3V AD 28 AD 26 GROUND AD 24 IDSEL 3 3V AD 22 AD 20 GROUND AD 18 AD 16 3 3V FRAME GROUND TRDY Excalibur Systems Chapter 8 Pin Signal Name B37 DEVSEL B38 GROUND B39 LOCK B40 PERR B41 3 3V B42 SERR B43 3 3v B44 C BE 1 B45 AD 14 B46 GROUND B47 AD 12 B48 AD 10 B49 GROUND CONNECTOR KEY B52 AD 08 B53 AD 07 B54 3 3V B55 AD 05 B56 AD 03 B57 GROUND B58 AD 01 B59 5V I O B60 ACK64 B61 5V B62 5V EXC 1394PCI amp EXC 1394PCle User s Manual Pin A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 Mechanical and Electrical Specifications Signal Name GROUND STOP 3 3V SDONE SBO GROUND PAR AD 15 3 3V AD 13 AD 11 GROUND AD 09 CONNECTOR KEY C BE O 3 3V AD 06 AD
58. EXC 1394PCI amp EXC 1394PCle Test and Simulation Boards for PCI Systems User s Manual NM XCALIBUS EXCALIBUR SYSTEMS 311 Meacham Avenue Elmont N Y 11003 Tel 516 327 000 Fax 516 327 4645 e mail excalibur mil 1553 com website www mil 1553 com Copyright 2008 2015 Excalibur Systems All Rights Reserved Table of Contents Table of Contents Chapter 1 Introduction T V OVERVIOW n Sects beta Ee 1 1 14 1 Board Featur S Eie EES SEE EE Ee decade A EER EE Re GER Re Ese KEER NR ee Ee 1 2 1 1 2 Block Didgtam RE EE AE EE NE 1 4 AE Eli RR TT RO N N N eE 1 5 12 InstallingstieBoBrd EE EE ED dae Gen ee oe een Rg gee 1 5 1 2 2 Installing Excalibur Software TOOIS e ees ee ee ee ee ee ek ee ee ke ee ee ee ee ee ee 1 6 1 3 Te lnieal SpPOrts sis ed ed is ed od Sto fot ed i 1 6 Chapter 2 PCI Architecture 2 1 PCI Memory Structure 2 Ee EE EE ES ESE ERGE Ee EE Ee ese EG 2 2 2 2 PCI Configuration Space Header iese ees ee ee ee ee ee ee ee ee ee ee ee 2 2 2 3 PCI Configuration Registers EE se lndimelnee ine 2 4 2 3 1 Vendor Identification Register VID iese ee ee ee ee AR ee ee Re ee ee ee ee ee ee ee 2 4 2 3 2 Device Identification Register DID for PCI ee ke GR Re ee ee ek ee ee 2 4 2 3 3 PCI Command Register PCICMD ee ee ee ee AR ee ee Re ee ee ee ee ee ee 2 4 234 PCI Status Register PCISTS ee ee sk ee ee Re ee ee AR ee ee Ge Re ee ee ee ed ee ee ee 2 5 2 3 5 Revi
59. F Offset In Use Register see see se ee ee de ee 5 18 Table 5 34 Datapump STOF Offset In Use Register se ee ee ee ee Ee RA ee 5 18 Table 5 35 Message Type Receive Control Table ee se ee ee ee ee ee 5 18 Table 5 36 CONO OV RR RE EE OE OR ORE ON RE 5 19 Table 5 37 RN Message Data Area ees se ee ee Re ee Ge Re ee Ge Re ee ee Re ee ee ke ee 5 19 Table 5 38 RN Transmit Datapump Stack ENHY ees ee ee ee ee se se eke ee ee ee ee ee Re ee ee 5 21 Table 5 39 RN Transmit Stack Entry Control Word ee ee ee se ee ee ke ee 5 21 Table 5 40 RN Transmit Stack Entry Status Word ees se ee ee ee ee ee ee ke ee 5 21 Table 5 41 RN Receive Message Stack ii ee se ee ee ee GR ke ee ee Re ee ee ke ee 5 22 Table 5 42 RN Receive Message Stack Status Word ie ee se ee ee ee 5 22 Table 5 43 Data Block Headlands ee ee ee ee ee Taa Ge ee ee ee Ee PAARIS dee ee 5 25 Table 5 44 Data Block Header Control Word ees se ee ee ee ee ee ke ee ee ke ee 5 25 Table 5 45 Butler Sze RR EE sativa A 5 25 Table 5 46 Data Block Header Status Word ees se ee ee ee ke ee ee ke ee ee ke ee 5 26 Table 5 47 Data Block Buer aec ER N RD OD 5 26 Table 5 48 Buffer Status Word is ree dese SEE Ee ee Dee Se EO DER GM ee eek ee dee ee bek 5 27 Table 6 1 RN Mode Memory Map Registers esse ee es se ee ee ke ee ee ke ee ee ee 6 2 Table 6 2 Interrupt Status Register see ee EAER EEEa ee eea ATIRA ee ee ee 6 4 Table 6 3 Interrupt Mask Register esse ee
60. H 0008 H 0004 H 0000 H Bit No 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 121110 9 8 765 43 2 1 0 Figure 2 5 EXC 1394PCl e Global and IRIG B Registers Map 1 IRIG B Time SBS Hi Register EXC 1394PCI amp EXC 1394PCle User s Manual page 2 15 Chapter 2 PCI Architecture 2 6 1 Board Identification Register Address 0000 H Length 32 bits Read Only Table 2 10 Board ldentification Register Bit Description 16 31 Hard coded to the value 1394 H 12 15 For PCI Hard coded to the value of 0 H For PCI Express Hard coded to the value of E H 04 11 Reserved set to 0 00 03 DIP switch selected ID 2 6 2 Software Reset Register Address 0004 H Length 32 bits Write Only Use this register to perform reset operations of the nodes Individual nodes can be reset Bit 04 the Global Time Tag reset bit resets all the node Time Tag counters Table 2 11 Software Reset Register Bit Description 05 31 Reserved set to 0 04 Global Time Tag reset 1 reset all Time Tag counters 0 no effect 03 Reserved set to 0 02 Node 2 reset 1 reset node 0 no effect 01 Node 1 reset 1 reset node 0 no effect 00 Node 0 reset 1 reset node 0 no effect 2 6 3 Interrupt Status Register Address 0008 H Length 32 bits Read Only This register indicates which nodes are currently interrupting or if the General Purpose Timer has produced an interrupt page 2 16 Excalibur Systems
61. Interrupt Mask Register ietsie ees Ne ERG Ee e Vs GR Ee DERE GEE Ee ia Pe eg ee 7 5 7 2 5 Reset Time Register iis ee ee ee Ee Re AA AR Re AA AA AR Re Re AA ea ek Re Re ee ea ee ne 7 6 7 2 6 Time Tag Registers oes EEUE EEDEN ee a EE ge vide ee Ee ee Pe Ee eb be 7 7 1 2 1 Reset Node Register ie NESER ea dane edad ge Ge Ee SE SERE EE SEE gee en 7 7 7 2 8 Receive Message Counter Register iii ee ee ee ee ee ek ee ee ee Re AA ek ke ee ee 7 7 7 2 9 STOF Message Counter Register ei ees se ee ee ee ek ke ee ee ee ee ee ee ee ke ee ee 7 8 7 2 10 Receive Message Error Counter Register ees see ee ee ee ee ee ee Re ee ee ee 7 8 7 2 11 Discarded Message Counter Register ee se ke ee ee ek ee Ge Re ee ee ee 7 8 7 2 12 Firmware Revision Register iese se se ee ee ee ee Ee Re Ge ee ee ee ee Re Re ee ee ee ee ee ee 7 8 7 2 13 Mode Select Register iss sR REKE Een Ee ERG R EE see E GEGEE VEL EER GENE Ee END SR E ER eed De 7 9 7 2 14 Start BEES AR OE AE DA OE EE IE DK 7 9 7 2 15 Excalibur Node Status Register eee ee ee ek ee ee Re ee ee ee ke ee ee Re ee ee ee 7 9 7 2 16 Port Status Register este GEKNERS DES DEE BEG ek Re ee Ee de EE Re ge ee Ee Ne See NR Ee 7 10 7 2 17 Number of Bad STOF Messages for CC Fail Register esse ee ee ee 7 12 7 2 18 Pointer to Beginning of Receive Linked List ee ee se AE ee ER Re ee 7 12 7 2 19 Pointer to Beginning of Receive Stack ee ee ek ee ee ee Re Ge Re ee ee ee 7 12 7 2
62. Layout pm Ee EE EG EG GE Ge EE 8 1 OZ LED Indicator S se EE 8 2 8 3 DIP Switches ss Me ge DA Ge Ge Ge Ga de 8 3 8 3 1 Selected ID DIP Switch SW1 ee esse ee ek ee AR RA ee RA ee RA ee ek ee ee 8 3 84 CONNEC OTS AE EE Ee Ee ed ed ae EE 8 4 8 4 1 Communications VO Connector J1 ees ee ee AR ee ee ee ee ee ee ke ee ee 8 4 8 4 2 PCI Bus Edge Connector PinoutS ee se ee ee ee ee ee ee ee ee ke ee ee ee ee ee ee ee ke ee ee 8 8 8 4 3 PCI Express Bus Edge Connector Pinout eee ees se ee ee ee ee ee ee ke ee ee ee ee ee ee ee 8 10 8 5 Synchronization with External Sources 8 11 8 6 Synchronizing Between EXC 1394PCl e Boards 5 8 12 8 7 Power Requirements FEE TREER EERSG ER RS BESEF DEEG RES GEES RENE Ee 8 12 Chapter 9 Ordering Information Appendix A 1394 Message Formats EXC 1394PCI amp EXC 1394PCle User s Manual page v Table of Contents Figures Figure 1 1 EXC 1394PCI Block Diagram ee ee ee ee ke ee Ge Re ee Ge Re ee ee ke ee 1 4 Figure 1 2 EXC 1394PCle Block Diagram iese ees ee ee ee ee Ge ke ee ee ke ee Ge ke ee 1 5 Figure 2 1 PCI Configuration Space Header for PCI see ee se ee ee ke ee ee ee 2 3 Figure 2 2 PCI Configuration Space Header for PCI Express esse se ee esse see 2 3 Figure 2 3 DMA Registers Map ees ee ee ee ee ee ke ee ee Re ee ee Ge ke ee ee ee ke ee ee ee ke ee 2 11 Figure 2 4 Node Memory Space Map iese ee se ke ee ee Re ee Ge ke ee ee ke ee ee ke e
63. Low Register 0010 H Time Tag Middle Register 0012 H Time Tag High Register 0014 H Reserved Mode Specific Registers Reserved Mode Specific Registers 0016 0017 H 0018 0019 H 001A 001B H 001C 001F H Reserved 0020 007F H Mode Specific Registers 0080 H Reserved 0084 0087 H Receive Message Counter Register 0088 H Reserved 008C 008F H STOF Message Counter Register reserved in Asynchronous mode 0090 H EXC 1394PCI amp EXC 1394PCle User s Manual page 3 1 Chapter 3 page 3 2 Register Name Reserved Receive Message Error Counter Register Reserved Discarded Message Counter Register Reserved Firmware Revision Register Mode Specific Registers Mode Select Register Start Register Excalibur Node Status Register Port Status Register Mode Specific Registers Reserved Options Register Reserved STOF Period Register reserved in Asynchronous mode Last STOF Message Status Register reserved in Asynchronous mode Last STOF Message Area reserved in Asynchronous mode Last STOF Time Tag Registers reserved in Asynchronous mode Reserved Mode Specific Registers Message Area Node Operation Overview Byte Address 0094 0097 H 0098 H 009C OO9F H 00A0 H 00A4 00A7 H 00A8 H OOAC H OOBO H 00B4 H 00B8 H OOBC H 00C0 00F1 H 00F2 00F3 H OOF4 00F7 H OOF8 OOFF H 0100 H 0102 H 0104
64. OEF H OOFO H OOF2 OOF3 H OOF4 00F7 H OOF8 OOFF H 0100 H 0102 H 0104 012F H 0130 H 0136 013B 013C H 0140 H 0144 02FF H 0300 34FF H 3500 38FF H 3900 1FFFFF H Control Computer Operation Read Write Read Only Read Only Read Write Read Write Read Only Read Only Read Only Read Write Read Write Read Write Read Write Read Write Read Write Read Only Read Write Read Write Read Only Read Only Read Only Read Only Read Write Read Write Read Write Page Number 4 9 4 9 4 9 4 10 4 10 4 11 4 13 4 13 4 13 4 14 4 14 4 14 4 14 4 15 4 15 4 15 4 16 4 16 4 17 4 17 4 17 4 18 4 18 page 4 3 Chapter 4 Control Computer Operation 4 2 CC Mode Register Definitions 4 2 1 Hardware Revision Register Address 0000 H Length 16 bits Read Only This register contains the revision number of the hardware logic 12 bits are used for the major revision and four bits are used for the minor revision For example for hardware revision 2 1 2 is stored in the high 12 bits and 1 is stored in the low four bits 4 2 2 Excalibur Node ID Register Address 0002 H Length 16 bits Read Only This register contains the identifier of the Excalibur Node This is set to 1394 H 4 2 3 Interrupt Status Register Address 0004 H Length 32 bits Read Write Write 1 to Clear This register indicates the occurrence
65. Payload payload length 8 words Packet trailer Note The 1394 Header CRC and 1394 Data CRC are stripped from the packet and are not stored by the node EXC 1394PCI amp EXC 1394PCle User s Manual page 4 217 Chapter 4 Control Computer Operation Table 4 37 describes the fields of the CC Receive Message Status Word Table 4 37 CC Receive Message Status Word Bit 15 14 07 13 06 05 04 03 02 01 00 page 4 22 Description Message complete Message in progress Reserved Lost quadlets Some quadlets that were received on the bus were lost probably due to heavy communications traffic Reserved Low word count actual length does not match 1394 header length Reserved Bad CRC or high word count actual length does not match 1394 header length Bad VPC Message error an error occurred specified in one of the other bits Excalibur Systems Chapter 5 Remote Node Operation Chapter 5 Remote Node Operation Chapter 5 describes operation in Remote Node RN mode In RN mode the node acts as a remote node on the Bus It transmits according to its predefined transmit STOF offset and has separate stacks for transmitting regular messages and Datapump messages It is ready to receive data at any time during the STOF frame Received data can be filtered by a combination of message number and transmitting RN message type Data blocks are configurable for each message type with up to eight buffers p
66. R Re aai e Ge Re AA a Re RA ee ee ee Ge Re ee ee ee 6 5 6 2 7 Receive Message Counter Register ii ee se ee ee AR ee GR Re ee ee ee ee ee ee 6 5 6 2 8 Receive Message Error Counter Register ee ee ek ee ee Re ee ee AR ee ee 6 6 6 2 9 Discarded Message Counter Register ees see ee ee ee Re ee Ge Re ee ee ee ee ee ee ee 6 6 6 2 10 Firmware Revision Register ee see ee ee ee ee Ge Re ee ee GR Ke ee Ge Re ee ee ee 6 6 6 2 11 Mode Select Register se ee ER Re AA AA AR Ge Re AA Re ee ee ee ee ee 6 6 6 2 12 ERA EA RE OR EE RE NE 6 7 6 2 13 Excalibur Node Status Register see ee ee ek ee ee ee ee ee Ke ee ee Re ee ee ee 6 7 6 2 14 Port Status Register iis Gys GEED DE GES ES Ee Deed N GER eee daai 6 9 6 2 15 Options IE ME N EE RE EN EE N N 6 10 6 3 Message Area ee ee ee ee ee ee ee ee ee 6 11 6 3 1 Asynchronous Transmit Message Areas ies ees se ee ee ee Ke ee ee ee ee ee ee 6 11 6 3 2 Asynchronous Receive Message Area se ee ee ee ee GR ee ee ee Re ee 6 14 Chapter 7 Bus Monitor Operation 7 1 Bus Monitor Memory Maps sesse ge ees bedes dk Ge 7 2 7 2 Bus Monitor Mode Register DefinitionS ese RR RR Re ee 7 4 7 2 1 Hardware Revision Register ees se ee es ee ee ee ke ee ee ee ee ee ke ee Ge ke ee ee ee ee ke ee ee 7 4 7 2 2 Excalibur Node ID Register rociera n Re AA AR a ee AR Ge ee ea ee 7 4 7 2 3 Interrupt Status Register see ee ee ee ee ee Re ee aa ee ek Ke ee Ge Re ee ee ee ee ee ke ee ee 7 4 7 24
67. Re Re ee ee ee ee Re ee ee ee ee 5 19 5 3 2 RN Transmit Datapump Message StacksS iis ee ee ee ek Re Re Ee ee Ee Re ee ee ee ee 5 20 5 3 3 RN Receive Message StacK ii se ee ee AA ER AA Ee AA ER RA Ee ee Ee Re ee ee ee ee 5 22 5 3 4 RN Receive Data Blocks ii ee ee ea Ee ee Ee AA ER AA AA AR ER Re Re AA ee ee ee 5 23 5 1 RN Memory Map Table 5 1 Register Name RN Mode Memory Map Registers Byte Address Hardware Revision Register 0000 H Excalibur Node ID Register 0002 H Interrupt Status Register 0004 H Interrupt Mask Register 0008 H Reset Time Register 000C H Reserved 000E OOOF H Time Tag Low Register 0010 H Time Tag Middle Register 0012 H Time Tag High Register 0014 H Reserved 0016 0017H Reset Node Register 0018 H Reserved 001A 007F H Transmit Message Counter Register 0080 H Reserved 0084 0087 H Receive Message Counter Register 0088 H Reserved 008C 008F H STOF Message Counter Register 0090 H Reserved 0094 0098 H Receive Message Error Counter Register 0098 H Transmit Message Error Counter Register 009C H Discarded Message Counter Register OOAO H Reserved 00A4 00A7 H Firmware Revision Register 00A8 H Pointer to Current Entry of Transmit Stack OOAC H Mode Select Register OOBO H Start Register 00B4 H Excalibur Node Status Register 00B8 H page 5 2 Read Write Read Only Read Only Read Write Write 1 to Clear Read Wr
68. T MON RN CC ACT MON RN CC Color White Blue White Blue White Blue White Blue White Blue White Blue Indication Node 0 Active Node 0 Monitor mode active Node 0 RN mode active Node 0 CC mode active Node 1 Active Node 1 Monitor mode active Node 1 RN mode active Node 1 CC mode active Node 2 Active Node 2 Monitor mode active Node 2 RN mode active Node 2 CC mode active Excalibur Systems Chapter 8 Mechanical and Electrical Specifications 8 3 DIP Switches The EXC 1394PCl e contains one DIP switch SW1 8 3 1 Selected ID DIP Switch SW1 This four contact DIP switch provides the board s Select ID It represents a four bit number of which position 1 is the most significant bit When a specific bit of the switch is e Offa value of 1 will be set for that bit e On a value of 0 will be set for that bit Multiple Board Applications To provide a unique Selected ID to identify a board by the application software in a multiple board application the DIP switch should be set differently for each board For example Table 8 2 Dip Switch Settings for Unique Selected ID Board ID 1 ID 3 Bit 1 On On Bit 2 On On Bit 3 On Off Bit 4 Off Off For multiple board applications each board s device number may be set by using the Excalibur configuration utility program provided with the drivers and by setting the unique ID to match that set on the DIP switch shown in Figure
69. Table Control Word Table 5 36 Control Word Bit Description Table 1 15 Reserved 0 Store 1 Do not store 0 Note Ensure that there is no overlap when laying out the data blocks 5 3 Message Area The RN Message Area contains RN Transmit Datapump Messages RN Transmit Datapump Message Stacks RN Receive Message Stack RN Receive Data Blocks Its address range is 13900 1FFFFF 5 3 1 RN Transmit Datapump Messages Table 5 37 describes the fields in each Transmit Datapump message Table 5 37 RN Message Data Area Word Description 0 1 1394 Header quadlet 2 9 ASM Header Length based on Payload payload length Note The data area must not contain the header CRC the data CRC or the trailer The trailer is comprised of the three STOF offsets and the VPC and is automatically generated by the firmware based on the values in the STOF Offsets Table EXC 1394PCI amp EXC 1394PCle User s Manual page 5 19 Chapter 5 Remote Node Operation Figure 5 1 shows the information that you must supply in a Transmit Message 1394 L Data Length Tag Channel Tcode Sync Header Message ID ASM J Reserved Security Header N Node ID Priority Message Payload Data Length gt Health Status Word Message Data Word 0 Heartbeat Message Data Word 1 Payload lt Data e Message Data Word Length 1 Figure 5 1 Transmit Message 5 3 2 RN Transmit Datapump Message Stacks In RN mode most of
70. able 5 23 STOF Period Register Bit Description 00 15 Period in usec to expect to receive STOF 5 2 29 Last STOF Message Status Register Address 0102 H Length 16 bits Read Write This register contains the status of the STOF message area Check this register to see whether the data in the STOF Message area and STOF Time Tag area are consistent and to check for errors in the STOF messages Table 5 24 Last STOF Message Status Register Bit Description 15 Message complete 14 Message in progress 09 13 Reserved 08 Vehicle time not progressing 07 STOF timing error early or late STOF 06 Lost quadlets Some quadlets that were received on the bus were lost probably due to heavy communications traffic 05 Reserved 04 Low word count actual length does not match 1394 header length 03 Reserved 02 Bad CRC or high word count actual length does not match 1394 header length 01 Bad VPC 00 Message error an error occurred specified in one of the other bits page 5 14 Excalibur Systems Chapter 5 Remote Node Operation 5 2 30 Last STOF Message Area Address 0104 H Length 11 32 bit words Read Only This register contains the last STOF message received by the node When the STOF is updated the Last STOF Message Status Register is set to 0 and the Message In Progress bit is set When the update is complete the STOF Message Counter Register is updated the Message In Progress bit is cleared the Message Comp
71. able 6 21 Status Word ed ET EE EE EE 6 14 Table 6 22 1394 Header and Data Area ees esse ee ee se ee ee Re ee ee Re ee ee ke de ee ee 6 15 Table 7 1 Bus Monitor Mode Memory Map Registers see esse se ee es se ge ee ee ee 7 2 Table 7 2 Interrupt Status Register see ee a ee AR ee ee ee ee ee ee ee 7 5 Table 7 3 Interrupt Mask Register ees eed ee ee ee AA ee ee Ge ee ee ee 7 6 Table 7 4 Reset Time Register iss ee ed Se ee ee Ge ee ee ee ee 7 6 Table 7 5 Time Tag Registers ia steeks ees ie evi se ie ges i a 7 7 Table 7 6 Reset Node Register iese ee Gee Ee RA AR Ge ee Re Se Ge ee be ee 7 7 Table 7 7 Receive Message Counter Register ee se ee ee ee Re ke ee 7 7 Table 7 8 STOF Message Counter Register ees ese ee ee ee ee ee ke ee Ge ke ee 7 8 Table 7 9 Receive Message Error Counter Register sees se ee se ke ee ee 7 8 Table 7 10 Discarded Message Counter Register ese ee ee ee Re ee ee 7 8 Table 7 11 Mode Select Register sesse esse ee se ee RE Ge ee ee SE AREA Ke ER Ge ee 7 9 Table 7 12 StartRegister id PEN Po dee EE PR AE dia ait ed 7 9 Table 7 13 Excalibur Node Status Register ees se ee ee ee ee ee ee ke ee ee ke ee 7 10 Table 7 14 Port Status Register ee ee se ee ee iraidd ee Ge ee ee Re ee ke ed 7 11 Table 7 15 Port Speed Bits EE EE Ee sage EE De reining EE anda lage eevee Ee de NE Ee 7 11 Table 7 16 Number of Bad STOF Messages for CC Fail Register sesse 7 12 Table 7 17 Options Redistel
72. age 4 8 Excalibur Systems Chapter 4 Control Computer Operation Table 4 12 Transmit Message Error Counter Register Bit Description 00 31 Number of transmit messages with errors 4 2 14 Discarded Message Counter Register Address 00A0 H Length 32 bits Read Only This register contains a running count of all messages that were discarded by the node It is reset to 0 upon power up node reset and when the node is started Table 4 13 Discarded Message Counter Register Bit Description 00 31 Number of messages received and discarded by the node 4 2 15 Firmware Revision Register Address 00A8 H Length 32 bits Read Only This register contains the revision number of the firmware running on the node 16 bits are used for the major revision and 16 bits are used for the minor revision For example for firmware revision 2 1 2 is stored in the high 16 bits and 1 is stored in the low 16 bits 4 2 16 Pointer to Current Entry of Transmit Stack Address 00AC H Length 32 bits Read Only This register contains a pointer to the location in the Transmit Stack that is currently being transmitted 4 2 17 Mode Select Register Address 00B0 H Length 32 bits Read Write Use this register to select the operational mode of the node EXC 1394PCI amp EXC 1394PCle User s Manual page 4 9 Chapter 4 Table 4 14 Mode Select Register Bit Value 00 31 0 1 2 3 4 Description Node was initialized
73. als comparison value 1 trigger on data value not equal to comparison value 2 trigger on data value less than comparison value 3 trigger on data value greater than comparison value 4 5 Mask Each bit set to 1 corresponds to a relevant data bit Each bit set to 0 corresponds to a do not care value 6 7 Comparison value the value to which the incoming data is to be compared All comparisons are performed after the mask is applied 8 Control Word 9 Status Word Table 7 41 describes the fields of the Bus Monitor Data Trigger Control Word Table 7 41 Bus Monitor Data Trigger Control Word Bit Description 01 15 Reserved 00 Trigger on 1 off 0 Table 7 42 describes the fields of the Bus Monitor Data Trigger Status Word Table 7 42 Bus Monitor Data Trigger Status Word Bit Description 01 15 Reserved 00 Triggered EXC 1394PCI amp EXC 1394PCle User s Manual page 7 25 Chapter 7 Bus Monitor Operation 7 3 Message Area The Bus Monitor Message Area contains e Bus Monitor Receive Stack e Bus Monitor Linked List e Banked Window into SDRAM 7 3 1 Bus Monitor Receive Stack When saving messages to SDRAM a message stack with 1000 entries describes the last 1000 messages to be saved by the node allowing you to see during runtime a summary of the messages being saved See Pointer to Beginning of Receive Stack on page 7 12 to obtain the Receive Stack in Dual Port RAM Table 7 43 describes t
74. alue of this register should be 0 EXC 1394PCI amp EXC 1394PCle User s Manual page 2 11 Chapter 2 PCI Architecture 24 3 DMAO Control Register Address 000C H Length 32 bits Read Write This register contains information about and controls the DMA write data transfer Table 2 8 DMAO Control Register Bit Description 12 31 Reserved set to 0 08 11 DMA channel state These bits describe the state of the DMA write channel 0000 idle state Last transfer ended successfully 0001 idle state Last transfer was stopped by a node 0010 idle state Last transfer ended because of CPL timeout 0011 idle state Last transfer ended because of CPL UR error 0100 idle state Last transfer ended because of CPL CA error 0101 0111 idle state Reserved 1000 busy state DMA channel is busy processing 1001 busy state Requesting transfer The DMA channel is in the process of requesting data from the host computer 1010 busy state The DMA channel is waiting for completion of a read data transfer in response to a DMA read request 1011 busy state Waiting for board to provide accept data The DMA channel is waiting for completion of a data transfer to or from the internal node memory 1100 1111 busy state Reserved 04 07 Reserved set to 0 03 Abort DMA transfer 1 Abort transfer 0 no effect 02 Start DMA transfer 1 Start DMA transfer 0 no effect 00 01 Reserved set to 0 244 DMA Addr
75. anual page 6 1 Chapter 6 6 1 Table 6 1 page 6 2 Asynchronous Memory Map Register Name Hardware Revision Register Excalibur Node ID Register Interrupt Status Register Interrupt Mask Register Reset Time Register Reserved Time Tag Low Register Time Tag Middle Register Time Tag High Register Reserved Receive Message Counter Register Reserved Receive Message Error Counter Register Reserved Discarded Message Counter Register Reserved Firmware Revision Register Reserved Mode Select Register Start Register Excalibur Node Status Register Port Status Register Reserved Options Register Reserved Asynchronous Transmit Message Area Reserved Asynchronous Receive Message Area Reserved Asynchronous Stream Transmit Message Area Reserved RN Mode Memory Map Registers Byte Address 0000 H 0002 H 0004 H 0008 H 000C H 000E 000F H 0010 H 0012 H 0014 H 0016 0087 H 0088 H 008C 0097 H 0098 H 009C 009F H 00A0 H 00A4 00A7 H 00A8 H 00AC 008F H 00B0 00AF H 00B4 H 00B8 H OOBC H 00C0 00F3 H 00F4 00F7 H OOF8 OFFF H 1000 181F H 1820 2FFF H 3000 380F H 3810 OFFF H 5000 581F H 5820 1FFFFF H Asynchronous Operation Read Write Read Only Read Only Read Write Write 1 to Clear Read Write Read Write Read Only Read Only Read Only Read Onl
76. atus byte after each time you read it The following topics are covered 6 1 Asynchronous Memory Map eeeeeeeeeeeeee 6 2 Asynchronous Mode Register Definitions 6 2 1 Hardware Revision Register sees se ee ee ee ee ee ee ee 6 2 2 Excalibur Node ID Register ese ee ee ee ee ee ee ee 6 2 3 Interrupt Status Register ee see ee ee ee ee ee AR ee ee 6 2 4 Interrupt Mask Register iii se ee ee ee ee Ge ee Ge ee ee ee ee ee ee 6 2 5 Reset Time Register ii se ee AA GR Re AA AA AR Re Re ee 6 2 6 Time Tag Registers ie ee se ee Ge EA AR Re Re Ee ee ee Re ke ee ee 6 2 7 Receive Message Counter Register iis ek ee ee ee 6 2 8 Receive Message Error Counter Register iis ese ee ee 6 2 9 Discarded Message Counter Register esse se ee ee ee 6 2 10 Firmware Revision Register ies se ee ee ee ee ee ee ee 6 2 11 Mode Select Register se ee ee AR Re Re AA ee ek ee 6 2 12 Start Register is se ee ee AA ee ee AA ee Ge ee ee ee ee 6 2 13 Excalibur Node Status Register ese ee ee ee ee ee 6 2 14 Port Status Register ii is se ee ee AR Ge Re AA ee se ke ee ee 6 2 15 Options Register seisis seg se ERG hteeessceneeivheatyeaunasnesce 6 3 Message Area Ee GE GR ES EE GR ESE Ee GR Ee Re Ge Ee 6 3 1 Asynchronous Transmit Message Areas esse see ee ee ee 6 3 2 Asynchronous Receive Message Area ee ee ee ee ee EXC 1394PCI amp EXC 1394PCle User s M
77. bur Systems Chapter 7 Bus Monitor Operation 7 2 45 Bus Monitor STOF Offsets Table For each channel number this table contains STOF offset information The table is indexed by channel number The information must be filled in if you want the monitor to report timing errors It is used to determine whether a message has come in at the right time whether an RN is transmitting at its transmit offset and whether the CC is transmitting to an RN at its receive offset Changes made while the monitor is running may only take effect when the monitor is restarted It is recommended to make changes while the node is stopped Table 7 37 describes the fields in the Bus Monitor STOF Offsets Table Table 7 37 Bus Monitor STOF Offsets Table Word Description 0 1 Transmit offset 2 Transmit offset duration Control Word 5 Receive offset Status Word 3 4 6 Receive offset duration 7 8 9 Datapump offset 1 1 0 Datapump offset duration 1 Reserved EXC 1394PCI amp EXC 1394PCle User s Manual page 7 23 Chapter 7 Bus Monitor Operation Table 7 88 describes the fields of the Bus Monitor STOF Offsets Table Control Word Table 7 38 Bus Monitor STOF Offsets Table Control Word Bit 15 12 14 11 10 09 08 07 05 06 04 03 02 01 00 Description Check offsets for this RN Reserved Trigger if node did not transmit at its Datapump offset occurs at the end of the Datapump window Trigger i
78. d KEER EG Gee Ed SEED EE Sek ese EE ee 4 16 4 2 32 Last STOF Time Tag Registers ees se ee ee ee Re ee Ge ee ee ee ee ee ke ee ee ee 4 16 4 2 33 Pointer to Most Recent Message iese ee ee ee Re ee ee ee ee ee Ge Re ee ee ee 4 17 page ii Excalibur Systems Table of Contents 4 2 34 Pointer to Least Recent Message iese ee ee ek Ke ee ee ee ee ee ee Re ee ee ee 4 17 4 2 35 Message Type Receive Control Table iii se ee ee RA AE AR Ge ee ee 4 17 4 2 36 CC STOP Offsets Table EE RE OE EE N 4 18 4 3 Message Area issie se EE De Ke Ek De Ke EE De Ke Ek De Ke EE De ke Ee De 4 18 43 1 CC Transmit Messages EE Ve nein dle shinies Ve de ee Ke gese ee Ve ge ed 4 18 4 3 2 CC Transmit Stacks ie REDS E OD E pens caeenluadhes Deed SEE Ke OGE E a see ees 4 19 4 3 3 CC Linked LISTATEA RR OE EE EE EN 4 21 Chapter 5 Remote Node Operation 5 1 RN Memory Map ER ke ais fig ee fag ee fe a Se dae 5 2 5 2 RN Mode Register Definitions iis ee ee 5 4 5 2 1 Hardware Revision Register se ee ee ee ee ee Ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee 5 4 5 2 2 Excalibur Node ID Register sissit ee ee ee ee ee ee ee AR Ke tapie ee ee ee ee ek ke ee ee 5 4 5 2 3 Interrupt Status Register see ee ee ee ee ee ee Re atao dea ee ee ee ee ee ek ke ee ee 5 4 5 2 4 Interrupt Mask Register ii ese ee ee ee ee Ee ee ee Ee ee Ee ee ee ee Re Re ee ee ee ee ee Re Re ee ee ee ee ee 5 5 5 2 5 Reset Time Register iis see ee r Ke Re AA AA AR Re Re AA aai Re
79. ddress of Contiguous Host Memory ees see ee ee ee ee ee ke ee ee ee ee ee ee 2 11 24 2 DMAO Data Transfer Size iese ee se ee ee aiana an inedi ee ee ee 2 11 24 3 DMAO Control Registers sete Ee ES sheet ec chee be EG cote nose ee bene GRA Ee Eye 2 12 244 DMA Address of Contiguous Host Memory ees see ee ee ee ee ee ke ee Ge Re ee ee ee ee 2 12 24 5 DMA1 Data Transfer Size iese ee ee ke ee ee AR Ke ee Ge Re ee Re ee ee ee Ke ee ee ee ek ee ee 2 13 24 6 DMA1 Control Register iese ee ee ee ee ee ke ee Ge Re ee ee ee ee Ke ee ee ee ee ee ee 2 13 24 7 DMA Interrupt Status Register ees ee ee ek ee Ge Re ee ee ee ee Ge Ke ee ee ee ee ee ee 2 14 24 8 Base Address for DMAO and DMA1 Transfers eneee 2 14 2 5 Node Memory Space Map ees ee ee ee ee RR RE ee ee ee ee ee ee 2 14 2 6 Global Registers Map ass de ee n n a 2 15 2 6 1 Board Identification Register ees ee ee ek ee ee Re ee Re ee GR Re ee ee ee ee ee ee 2 16 2 6 2 Software Reset Registers iii Ee Ese ENE ee SE Ee Ge DERE ge GER ee aa Ee vs ee eg Eed ee 2 16 2 6 3 Interrupt Status Register ee se ee ee ek Ke ee ee Re ee Re ee ee Ke ee ee ee ee ee ee 2 16 2 6 4 Interrupt Reset RegisteF iis ee ee Ee Ee Re AA AR Ee AA ee Ee Re AA ee ee ee ede ee 2 17 2 6 5 Node Info Registers sesse EDEN EE GESE EG sven Dev gee eeue EEUE e Dee EED ee 2 17 EXC 1394PCI amp EXC 1394PCle User s Manual page i Table of Contents 2 6 6 Time Tag Clock Select Register
80. de 0 Info Register 0001 H Node 1 Info Register 0002 H Node 2 Info Register 05 31 Reserved set to 0 2 6 6 Time Tag Clock Select Register Address 0018 H Length 32 bits Read Write Use this register to set either an internal 10 MHz or external source for the board s Global Time Tag Clock For details on the External Time Tag Clock see Communications I O Connector J1 on page 8 4 Table 2 15 Time Tag Clock Select Register Bit Description 01 31 Reserved set to 0 00 Time Tag Clock Select 1 External Source 0 Internal Source Default page 2 18 Excalibur Systems Chapter 2 PCI Architecture 2 7 IRIG B Global Registers The EXC 1394PCl e is able to receive and decode standard serial IRIG B120 time code format signals via its External Signal Connector J1 See Communications I O Connector J1 on page 8 4 IRIG B120 signals have the following specifications B 100 pulses per second PPS 10 msec count 1 Sine wave carrier amplitude modulated 2 1 kHz carrier wave 1 msec resolution 0 Binary Coded Decimal BCD Control Functions CF depending on the user application Straight Binary Second SBS of day 0 86400 For more information visit irig org The IRIG B signal which contains 3 types of words within each Time Code Frame can be used to synchronize the Time Tags of the nodes on the EXC 1394PCI e 1st Word Time of year in binary coded decimal BCD notation in hours minutes a
81. de ID Priority Message Payload Data Length Health Status Word Message Data Word 0 Heartbeat Message Data Word 1 lt Message Data Word Length 1 STOF Transmit Offset STOF Receive Offset lt STOF Datapump Offset Vertical Parity Check 1394 Data CRC a Figure A 2 Asychronous Data Packet Format Figure A 2 shows the complete data packet transmitted received in CC RN and Bus Monitor modes For Transmit Messages this includes parts that are supplied by the user and by the firmware For the parts that are supplied by the user see Figure 4 1 on page 4 19 and Figure 5 1 on page 5 20 For Asynchronous mode messages see Figure 6 1 on page 6 13 Note e The EXC 1894PClI e board s Message ID is a 32 bit number represented as an unsigned long integer It is a decimal number The lowest two digits represent the message number from 00 99 for a total of 100 messages per channel The next two digits represent the channel number 0 63 The rest of the Message ID usually representing the CC branch is ignored by the node e The 1394 Header CRC and 1394 Data CRC are stripped from the packet and are not stored by the node pageA 2 Excalibur Systems The information contained in this document is believed to be accurate However no responsibility is assumed by Excalibur Systems Inc for its use and no license or rights are granted by implication or otherwise in connection there
82. e the node receives all bus messages that pass through its ports and stores them in memory with their timestamps Filtering is available for storing only specific messages Triggering is available to capture a snapshot of data surrounding a specific event Data can be recorded either to the almost 2 MB Dual Port RAM buffer or to a 128 MB SDRAM buffer The Dual Port RAM can be used for real time monitoring The 128 MB SDRAM should be used in conjunction with triggering to record a large buffer relating to a specific event 1 MB at a time can be accessed via DPRAM when the node is stopped The following topics are covered 7 1 Bus Monitor Memory Maps is issie ese ese ee gede eers 7 2 7 2 Bus Monitor Mode Register DefinitionS iese RR RR Re 7 4 7 2 1 Hardware Revision Register iese se ee ee se ee ee Re ee ee ee ee ee ke ee Ge ke ee ee ee ee ke ee ee 7 4 7 2 2 Excalibur Node ID Register 00 0 ee ee se ee ee ee ee AR Ke ee ee ee ee ee ee ee ke ee ee 7 4 7 2 3 Interrupt Status Register see ee ee ee ee ee Re ee ee ee ee ek Ke ee ee ee aE ee ee 7 4 1 24 Interrupt Mask Register ietsie Des usted e se Ee EA GEE Ee Se De Bede 7 5 7 2 5 Reset Time Register 7 2 6 Time Tag Registers 7 2 7 Reset Node Register 7 2 8 Receive Message Counter Register iii ee ese ee ee ee AR ee ee Re ee Re AA ek Ke ee ee 7 7 7 2 9 STOF Message Counter Register isi ees se ee ee ee ee ek Ke ee Ge Re ee ee ee ee ek ke ee ee 7
83. e 2 14 Figure 2 5 EXC 1394PCl e Global and IRIG B Registers Map esse se 2 15 Figure 4 1 Transmit MCSSAGC AR AL ER N OE OE EE EE AE 4 19 Figure 5 1 Transmit Message iss see Se sae SE Ee Re E E Ee Ee be ed ee ee ede 5 20 Figure 5 2 RN Receive Data Block ee se ee ee ee ee ee ee ee ee Ke ee ee ke ee 5 23 Figure 6 1 Asynchronous Stream Transmit Message se ee ee ke ee 6 13 Figure 6 2 Asynchronous Receive Message ee ee ee ke ee ee ee 6 15 Figure 8 1 EXC 1394PCI Board LayOUt ees ee ee ee ee ke ee Ge ke ee ee ke ee ee ke ee 8 1 Figure 8 2 EXC 1394PCle Board LayOU ee ees ee ee ee ke ee Ge ke ee ee ke ee ee ke ee 8 2 Figure 8 3 DIP Switch SW 1 with All Switches Set to ON Select ID O see 8 3 Figure 8 4 Connectors J1 Layout Front VIEW ees ees ee ee ee ee ke ee ee ke ee ee ke ee 8 4 Figure 8 5 Synchronization of an EXC 1394PCl e Board to an External System 8 11 Figure 8 6 Synchronization of an External System to an EXC 1394PClfe Board 8 11 Figure 8 7 Synchronization Between EXC 1394PClle Boards iese ese 8 12 Figure A 1 STOF Packet Format uitsteek ie dedi a edie A 1 Figure A 2 Asychronous Data Packet Format iese se ee de ee se ee ee ee ee ke ee ee A 2 Tables Table 2 1 PCI Command Register seteriai A Re ee Re ee ee Re ee ee ee ee ee 2 4 Table 2 2 PCI Status Register for PCI ee ee ee ee ee Re ee Ge Re ee ee ee ee ee 2 5 Table 2 3 PCI Status Register for PCI Express
84. e 2 9 Chapter 2 PCI Architecture 2 4 reserved The value of 255 signifies either unknown or no connection for the system interrupt The value at power up is 0000 H 2 3 18 Interrupt Pin Register INTPIN Address 003D H Length 8 bits Read Only The value of this register is set to INTA The value at power up is 0001 H 2 3 19 Minimum Grant Register MINGNT Address 003E H Length 8 bits Read Only This register is not implemented on the EXC 1394PCI e The value at power up is 0000 H 2 3 20 Maximum Latency Register MAXLAT Address 003F H Length 8 bits Read Only This register is not implemented on the EXC 1394PCI e The value at power up is 0000 H DMA Registers for PCI Express Direct Memory Access DMA enables the EXC 1394PCle board to access system memory for reading and writing independently of the computer s CPU This results in faster data transfer to and from the board with much less CPU overhead than when not using DMA There are two DMA channels e DMAO DMA channel 0 is used for DMA writes e DMA1 DMA channel 1 is used for DMA reads page 2 10 Excalibur Systems Chapter 2 PCI Architecture 0044 AFFF H Base Address for DMAO and DMA1 Transfers 0040 H 0038 H Reserved Bits 2 31 DMA Interrupt Status 0034 H Bits 0 1 0030 H 0028 H 0024 H 0020 H DMA1 Control 001C H DMA1 Data Transfer Size 0018 H DMA1 Address of Contiguous Host Me
85. e ee 3 1 Chapter 4 Control Computer Operation 4 1 CC Memory Map or SE eee ai eee er are Pr aa ere 4 2 4 2 CC Mode Register Definition ee 4 4 4 2 1 Hardware Revision Register ii see ee ee ee ee se ee ee ee ee ee Ee Re ee ee ee ee ee Re Re ee ee ee ee ee ede ee 4 4 4 2 2 Excalibur Node ID Register iii see ee ee Ee ee ee AR Ee Re ee ee ee Ge Re Re ee ee ee ee ee ee ee 4 4 42 3 Interrupt Status Register iese ss de ee ee de ee ed ee Gee de de Re ed Re ee ed ee ee 4 4 4 2 4 Interrupt Mask Register ie se ee ee ee ee Re Re AR Ge Re ee ee ee ee Re Re ee ee ee ee ee ee 4 5 4 2 5 Reset Time Register ER EV ae a De GER Ea Ge ee Bee eo Ee SR RE Deeg 4 6 426 Time Tag Registers see ee se Re Re EA AR Ge ee ee AR Ge ee ee ee ee Ge Re ee ee ee ee ee ee 4 6 4 27 Reset Node Register ii EE EE Ee de EE eerie ee Ve i Ke Ke gees Ve lene 4 7 4 2 8 Vehicle Time Preload Value Register ii see ee ee Ee Re AE AR GR Re AE ee AR ee ede ee 4 7 4 2 9 Transmit Message Counter Register iese ee ee ee Re AR Ke ee ee ee ee ee ee 4 7 4 2 10 Receive Message Counter Register ees ee ee ee ee AA ee ee ee Re ee ee ee 4 8 4 2 11 STOF Message Counter Register esse ee ee ek ee ee ee Re ee ee Re ee ee ee 4 8 4 2 12 Receive Message Error Counter Register ees ee ee ee ek ee ee Re ee ee ee 4 8 4 2 13 Transmit Message Error Counter Register see esse ee es se ee ee ee ee ee ke ee ee 4 8 4 2 14 Discarded Message Counter Register ee s
86. e ee Ge Re ee ee Re ee ee ke ee ee ke ee 7 20 Table 7 34 Bank Select Register iese ee ee AR ee Ke Ge ee AR ee ee ee Ke ee ee 7 20 Table 7 35 Current Bank Register ee ee ee ee ee ee AR ee AR ee ee ee ee ee ee 7 21 Table 7 36 Monitor Mode Receive Control Table ie ee se ee ee ke ee ee ke ee 7 22 Table 7 37 Bus Monitor STOF Offsets Table ees se ee ee ee ke ee ee ke ee ee ke ee 7 23 Table 7 38 Bus Monitor STOF Offsets Table Control Word ees se ee ee 7 24 Table 7 39 Bus Monitor STOF Offsets Table Status Word ees ee ee ke ee 7 24 Table 7 40 Bus Monitor Data Trigger Table ee ee ee Ge ke ee ee Ke ee ee ke ee 7 25 Table 7 41 Bus Monitor Data Trigger Control Word ees ee se ee ee ke ee 7 25 Table 7 42 Bus Monitor Data Trigger Status Word ee se ee ee ke ee ee ke ee 7 25 Table 7 43 Bus Monitor Receive StaCK ee ee ee ee ee ee GR Re ee ee Re ee ee ke ee 7 26 Table 7 44 Bus Monitor Message Stack Status Word ee ee ee ee ee ke ee 7 27 Table 7 45 Bus Monitor Linked List Structure for a General Message 45 7 28 Table 7 46 Receive Message Status Word for a General Message ees 7 29 Table 7 47 Bus Monitor Linked List Structure for a STOF Message 0 7 30 Table 7 48 Receive Message Status Word fora STOF Message sees 7 31 Table 8 1 LED Indicators see ccna n Gee ee Ge ee Ee inline eee 8 2 Table 8 2 Dip Switch Settings for Unique Selected ID see ee ee RR Re Ee 8 3 Table
87. e ee ee 4 9 Mode Select Register iese a Se RA Ge ee a Ee ee 4 10 tart Registers EE EL cae ee had aes AG EE eae 4 10 Excalibur Node Status Register ees se ee ee ee ee ee ke ee ee ke ee 4 11 Port Status Register osese ni eia ee ee Ge ee RA ee Ge ee ee ee ee ee ee 4 12 Port Speed BIS n ES SE sees oe ils ES Ge Ee SE De Atte DR es es ide 4 12 1394 Node RR ET EE NE RE OT EA 4 13 CC Run Configuration Register ee ee ee ee ee AR ee AR ee ee 4 13 Speed Code Register iss see se ee de ee ee ee ee ee ede 4 14 Speed Code Bits ibia EA RA Ee ee ee aiaei ee ee ea ee 4 14 Oplos Redistelf EE teens HERE EE DER cette ee eeue Doe gee eg Tee ete 4 15 STOF Period Registo ooren aa E EA A G 4 15 Last STOF Message Status Register ees se ee ee ee ee ke ee 4 16 Last STOF Message Area iese ees ee ee ee ee ke ee ee ee ke ee ee ee Re ee ee ee ke ee 4 16 Last STOF Time Tag Registers ei ees se ee ee ee ke ee ee ke ee ee ke ee 4 16 Pointer to Most Recent Message ee se ee ee ee ee ee ke ee ee ke ee 4 17 Pointer to Least Recent Message ee ee ee ee ee ke ee ee ke ee 4 17 CC Receive Control Word ee ee ee Re AR ee ee ee AR ee ee 4 17 CC STOF Offsets Table siese ee see ee se ee ed ee Ge ee de ee de ee ee 4 18 Transmit Message Data Area ee see ee de ee Ee AA ee ee ee de ee ee 4 18 CC Transmit Stack Entry iec ees se ee ee ee ee ee ee ee ee ee ee ee ee ee 4 20 CC Transmit Stack Control Word ee ee AR ee AR ee AR ee ee 4 20 CC Transmit Stack
88. e ee ee ek ee ee Re ee ee ee 4 9 4 2 15 Firmware Revision Register ese ee ee ek ee ee Re ee Ee ek ke ee ee Re ee ee ee 4 9 4 2 16 Pointer to Current Entry of Transmit Stack 4 9 4 2 17 Mode Select Register iese ERROR ee Ao Ed AK REG EE ects EE SEA Ge See ed ee 4 9 4 2 18 StartRegisters sr De Dr Ge Ee De eee lett eae ieee 4 10 4 2 19 Excalibur Node Status Register iese ee ee ee Re ee ee ee ee ee Ge ke ee ee ee 4 10 4 2 20 Port Status Register rus EER EN GEREEN SEE GE SEGE ewe ee Dee Eg VERE ee See DE es 4 11 4 2 21 1394 Node ID Register sie sce RR EES LS Ee ee eee ese needs Kg ge de eg ed EE GE 4 13 4 2 22 CC Run Configuration Register ees se ee ee ke ee Ge Re ee Ke ee ee ke ee ee 4 13 4 2 23 Pointer to Beginning of Single Shot StacK esse ees se ee Re Ge Re ee ee ee 4 13 4 2 24 Pointer to Beginning of Continuous Mode StaCK iis se ee ee ee ee ee ee ee 4 14 4 2 25 Pointer to Beginning of Receive Linked List ee ee ee Re AR Re ee ee 4 14 4 2 26 Pointer to End of Receive Linked List ee ee ee ee ee ee ee ee Ge Re ee ee ee 4 14 4 2 27 Speed Code Register innin ESE RE EE ER EO KERSE OE GREG EK Ged Re Ee Ge EE Re snes 4 14 4 2 28 Options Register se EE EE EE o se Ee Ee Eg eutectic 4 15 4 2 29 STOF Period Register sees see ee RE ee EE OOR Re KERE ee Se Re ke BEER KERE EE Re Ese 4 15 4 2 30 Last STOF Message Status Register sees ee ee ee ke ee ee ee ee Ge Re ee ee ee 4 15 4 2 31 Last STOF Message Area iseer es ie DE Goe
89. e running will only take effect when the monitor is stopped and restarted Trigger on data quadlet s in the Trigger Control Register on page 7 16 uses this table to specify several data triggers each one identifying a quadlet within a page 7 24 Excalibur Systems Chapter 7 Bus Monitor Operation message including data and trailer guadlets and compares it with an expected value The Trigger Channel Number and Trigger Message Number identify the type of message on which to evaluate the trigger The Trigger Data Index identifies which quadlet s contents are to be looked at where the first quadlet of the message data is at index 0 of the message data Note that index 0 is the Health Status Word and index 1 is the Heartbeat The Trigger Mask is applied to the quadlet contents to isolate important bits in case not all 32 bits are relevant The Trigger Comparison Value contains the data to which to compare the incoming data and the Trigger Function indicates the type of comparison to be performed that is lt gt or Table 7 40 describes the fields of each entry in the Bus Monitor Data Trigger Table Table 7 40 Bus Monitor Data Trigger Table Word Description 0 Source channel number 1 Message number 2 Data index The index is from the beginning of the payload area that is 0 is the Health Status Word 1 is the Heartbeat 2 is the first message data quadlet etc 3 Function 0 trigger on data value equ
90. ea does not contain the header CRC or the data CRC Tables 6 20 through 6 22 list the information in a receive message Table 6 20 Receive Message Information Registers Word Description 0 Reserved 1 Status Word see Table 6 21 on page 6 14 2 4 Time Tag when the message was received 48 bits 5 Actual quadlet count 6 7 Reserved Table 6 21 Status Word Bits Bit Description 15 Message complete 14 Message in progress 08 13 Reserved 07 Timed out waiting for async response 06 Lost quadlets some quadlets that were received on the bus were lost probably due to heavy communications traffic 05 Reserved 04 Low word count actual length does not match the 1394 header length 03 Reserved 02 Bad CRC or high word count actual length does not match the 1394 header length 01 Reserved 00 Message error an error occurred specified in one of the other bits page 6 14 Excalibur Systems Chapter 6 Asynchronous Operation Table 6 22 1394 Header and Data Area Word Description 0 3 1394 Header quadlets see Figure 6 2 4 256 Payload area length used based on payload length oe yi Data Length Tag Channel Tcode Sync eader N si Data lt N Figure 6 2 Asynchronous Receive Message EXC 1394PCI amp EXC 1394PCle User s Manual page 6 15 Chapter 7 Bus Monitor Operation Chapter 7 Bus Monitor Operation Chapter 7 describes operation in Bus Monitor mode In Bus Monitor mod
91. ed Bit 2 17 Port 0 Spare 16 Port 0 Spare 15 Port 1 Connected 14 Port 1 Receive OK 13 Port 1 Beta Mode 12 Port 1 Speed Bit 0 11 Port 1 Speed Bit 1 10 Port 1 Speed Bit 2 09 Port 1 Spare 08 Port 1 Spare 07 Port 2 Connected 06 Port 2 Receive OK 05 Port 2 Beta Mode 04 Port 2 Speed Bit 0 03 Port 2 Speed Bit 1 02 Port 2 Speed Bit 2 01 Port 2 Spare 00 Port 2 Spare Table 7 15 Port Speed Bits Speed Bit 2 Bit 1 Bit 0 100 Mbps 0 0 0 200 Mbps 0 0 1 400 Mbps 0 1 0 Not Supported 0 1 1 Not Supported 1 0 0 EXC 1394PCI amp EXC 1394PCle User s Manual Bus Monitor Operation page 7 11 Chapter 7 Bus Monitor Operation 7 2 17 Number of Bad STOF Messages for CC Fail Register Address 00C4 H Length 32 bits Read Write Use this register to set the number of bad STOF messages to allow without considering the CC to have failed After this amount the CC has a status of failed The value of this register reset to 3 upon power up and node reset Table 7 16 Number of Bad STOF Messages for CC Fail Register Bit Description 00 31 Number of missed STOF messages to allow 7 2 18 Pointer to Beginning of Receive Linked List Address 00D8 H Length 32 bits Read Only This read only register contains a pointer to the beginning of the Linked List Use this address to access the list Note This register does not contain valid data when received messages are stored in SDRAM See Memory Select Register on page 7 20 7 2 19 Pointer to
92. ee 5 10 Table 5 16 Pott Status Registers se IR EE Ee SR Ee DE AG Se tht GR Gee Ee GE ee De 5 11 Table 5 17 Port Speed BIS ME SEE MO SEE SE OD E ER Oe Gee n De ee es de 5 11 Table 5 18 Number of Bad STOF Messages for CC Fail Register sesse 5 12 Table 5 19 1394 Node ID Register ee ee se ee Re ee Re ee ek ee ee 5 12 Table 5 20 Speed Code Register ss ee ee de de ee ee ee ee ed 5 13 Table 5 21 Speed Code BIS EE ED Ee Ge RE GE EG De tae bates dad Re Ek 5 13 Table 5 22 Options REGISTER i s is HEESE epee HEL See Bee EE Se Tea ec 5 13 Table 5 23 STOF Period Register iese ss sees dees ke ee gee Ai de ee see 5 14 Table 5 24 Last STOF Message Status Register iese se ee ee ke ee ee ke ee 5 14 Table 5 25 Last STOF Message Area iese ees ee ke ee Ge ke ee Ge ke ee ee ee ke ee ee ee ke ee ee 5 15 Table 5 26 Last STOF Time Tag Registers iese ee se ee ee ee ke ee ee ke ee ee ke ee ee 5 15 Table 5 27 Store STOF Messages Register ees ee ee ee ee ee ee ee ee ee ee 5 16 Table 5 28 Receive STOF Offset Register ie ee se ee ke ee ee ke ee ee ke ee 5 16 Table 5 29 Transmit STOF Offset Register iese see ee ee se de ee ee de ee 5 16 Table 5 30 Datapump STOF Offset Register ee ee ee ee se Re ee ee ee Ee Re ee ee 5 17 Table 5 31 Channel Number Register ees ee ee ee ee ee AR ee AR ee AR ee ee 5 17 Table 5 32 Receive STOF Offset In Use Register ees se ee ee ee ek ke ee 5 17 Table 5 33 Transmit STO
93. ee Ge ee ee Ee Re Re ee ee ee Re Re ee ee ee ea ee 5 13 5 2 28 STOF Period Register se rs EE ELE ee Ve Ee RES Ee Dee tended DREK ese Ed We 5 14 5 2 29 Last STOF Message Status Register sees se ee ee ee ee ee ee ke ee ee ee 5 14 5 2 30 Last STOF Message Area ese ese ee ee Re ee ee ee ee Ke ee ee ee ee ee ee ee ke ee ee ee 5 15 5 2 31 Last STOF Time Tag Registers ees se ee ee ee ee Re ee ee ee ee ee ee Re ee ee ee 5 15 5 2 32 Store STOF Messages Register iese ee se ee Re ee Ge Re ee ee be ee ee ke ee ee 5 15 5 2 33 Receive STOF Offset Register ee se nnee enan 5 16 5 2 34 Transmit STOF Offset Register sees se ee ee ee Re AR ke ee Ge ee ee ee ee 5 16 5 2 35 Datapump STOF Offset Register ese ee ee ee ee ee ee ee ee ee ke ee ee ee 5 17 5 2 36 Channel Number Register see ee ee se Re ee ee AR Ke ee Ge Re ee ee ee ee ke ee ee 5 17 5 2 37 Receive STOF Offset In Use Register ee se ee ee Re GR ee AR Re ee ee ee 5 17 5 2 38 Transmit STOF Offset In Use Register ees see ee ee ee ee Re ee ee ee ee ee ee 5 18 5 2 39 Datapump STOF Offset In Use Register ees se ee ee ee ee Ge Re ee ee ee 5 18 EXC 1394PCI amp EXC 1394PCle User s Manual page 5 1 Chapter 5 Remote Node Operation 5 2 40 Message Type Receive Control Table cccccccceseeceeeeeeeeeenaeeeeeeeeeeeeaees 5 18 5 3 Message ence ener ener edcecncrederencceccreneredetcneceserenecedece 5 19 5 3 1 RN Transmit Datapump MessageS ii ee ee ee Ee ee AR
94. ee ee ee 5 6 5 2 6 Time Tag Registers isani EERS EG se EE Ee AS EER EG Se Ne AE DE EE hii 5 6 5 2 7 ResetNode Register iii iese LEEG ER aa EL GE Ke eek bee ede gee be sage sed 5 6 5 2 8 Transmit Message Counter Register iese ee ee ee ee Re ee Ge Re ee ee ee ee ke ee ee 5 7 5 2 9 Receive Message Counter Register iii ee ee ee ee ee AR ee ee Re AA ek ke ee ee 5 7 5 2 10 STOF Message Counter Register ees see ee ee Re ee ee ee GR ee ee Re ee ee ee 5 7 5 2 11 Receive Message Error Counter Register ees see ee se ee ee ek ee ee Re ee ee ee 5 7 5 2 12 Transmit Message Error Counter Register sesse ees se ke ee ee ed ee ee ke ee ee 5 8 5 2 13 Discarded Message Counter Register ee se ee Ke ek ee ee Re ee ee ee 5 8 5 2 14 Firmware Revision Register iese ee ee ek ee Ge Re ee ee ee ee ee Re ee ee ee 5 8 5 2 15 Pointer to Current Entry of Transmit Stack 5 8 5 2 16 Mode Select Registers ii Es en ea N dek il Hades Acree tee 5 9 5 2 17 ARE el Es 20s RE EA N ER EE NE N 5 9 5 2 18 Excalibur Node Status Register sees ee ee ek ee ee Re ee ee ee ke ee ee Re ee ee ee 5 9 5 2 19 Port Status Register iis EE ees EE DEE Se dd NEER ee gues suuecdbesbantendandeneestnes 5 10 5 2 20 Number of Bad STOF Messages for CC Fail Register esse ee ee ee 5 12 5 2 21 1394 Node ID Register EER EES EERS Ge EE oes Ke ee Ee BERE e Ee se Ee n Fe 5 12 5 2 22 Pointer to Beginning of Transmit Stack ie se ee ee ee ER Re Ee ee ee ee ee ee 5 12
95. ee ee ee ee AR ee ee 5 18 5 2 39 Datapump STOF Offset In Use Register ees ees ee ee ee AR Re ee ee ee 5 18 5 2 40 Message Type Receive Control Table ie ee se ee ee ee Re ee Ge Re ee ee ee 5 18 5 3 Message re se es EA alata adie leno ede den ee 5 19 5 3 1 RN Transmit DatapUMp MessageS issie ees se ee ee ge ek ee ee Ge Re ee ee ee ee ee ee ee 5 19 5 3 2 RN Transmit Datapump Message Stacks eie ees se ee ee ek ee ee Re ee ee ee ee ee ee ee 5 20 5 3 3 RN Receive Message StackK ies ee ek ee Ge ee AR ee ee Re ee ee AR ee ee 5 22 5 3 4 RN Receive Data BlockS ie ED EE EE ieee ivy ieee titel ER ee Ee De Ee eg 5 23 EXC 1394PCI amp EXC 1394PCle User s Manual page iii Table of Contents Chapter6 Asynchronous Operation 6 1 Asynchronous Memory Map ee RR RR RR RR RR ee Re ee ee ee ee ee ee ee 6 2 6 2 Asynchronous Mode Register Definitions 1 0 0 0 ee ee 6 3 6 2 1 Hardware Revision Register ee ee ek ee ee Re ee ee AR ee ee Re ee ee ee ee ee ee ee 6 3 6 2 2 Excalibur Node ID Register see ee ee ee ee ee Re ee ee AR ee ee Re ee ee ee ee ee ee ee 6 3 6 2 3 Interrupt Status Register ee see ee ee Re ee ee Re ee ee AR ee ee Re ee ee ee ee ee ee ee 6 3 6 2 4 Interrupt Mask Register iis ee ee ee GR ee ee ee Re Re ee ee AR ee Re de ee ee ee ee ee Re Re ee ee ee 6 4 6 25 Reset Time Register tse EE oe He EE EE RE es ei Ee ee te EE boe geen SEE EL N 6 5 6 2 6 Time Tag Registers ies se Re ee e E
96. ee page 5 12 The actual message data is not stored in the stack The message data is stored in the RN Receive Data Blocks See RN Receive Data Blocks on page 5 23 STOF messages are only included the Receive Message Stack when the Store STOF Messages Register is set to Store Table 5 41 describes the RN Receive Message Stack Table 5 41 RN Receive Message Stack Word Description 0 Status 1 Message identifier sending channel bits 0 6 message number bits 7 13 STOF indicator is Bit 15 2 3 1394 Header Word 4 6 48 bit Time Tag 7 Reserved Table 5 42 describes the fields of the RN Receive Message Stack Status Word Table 5 42 RN Receive Message Stack Status Word Bit Description 15 Message complete 14 Message in progress 09 13 Reserved 08 Vehicle time not progressing 07 STOF timing error early or late STOF 06 Lost quadlets Some quadlets that were received on the bus were lost probably due to heavy communications traffic 05 Reserved 04 Low word count actual length does not match 1394 header length 03 Reserved 02 Bad CRC or high word count actual length does not match 1394 header length 01 Bad VPC 00 Message error an error occurred specified in one of the other bits Note Bits 7 and 8 are STOF message errors page 5 22 Excalibur Systems Chapter 5 534 RNReceive Data Blocks Remote Node Operation Each data block contains a header area and up to eight fixed size data buffe
97. egister Bit Description 31 Reserved 30 Message fragment detected the receive FIFO had part of a message There was probably an overrun or other technical glitch in receiving 29 Out of frame message received received a message before first STOF or after missing STOFs 17 29 Reserved 16 Wrong LLC version indicates that the link layer chip had technical difficulties 5 15 Reserved 04 1 Running 0 Halted 03 1 Self Test Passed 0 Self Test Failed 02 Reserved 01 1 RAM test passed 0 RAM test failed 00 1 Ready 0 Not ready 5 2 19 Port Status Register Address 00BC H Length 32 bits Read Only This register indicates the current status of the three ports page 5 10 Remote Node Operation Excalibur Systems Chapter 5 Table 5 16 Port Status Register Bit Description 24 31 Reserved 23 Port 0 Connected 22 Port 0 Receive OK 21 Port 0 Beta Mode 20 Port 0 Speed Bit 0 19 Port 0 Speed Bit 1 18 Port 0 Speed Bit 2 17 Port 0 Spare 16 Port 0 Spare 15 Port 1 Connected 14 Port 1 Receive OK 13 Port 1 Beta Mode 12 Port 1 Speed Bit 0 11 Port 1 Speed Bit 1 10 Port 1 Speed Bit 2 09 Port 1 Spare 08 Port 1 Spare 07 Port 2 Connected 06 Port 2 Receive OK 05 Port 2 Beta Mode 04 Port 2 Speed Bit 0 03 Port 2 Speed Bit 1 02 Port 2 Speed Bit 2 01 Port 2 Spare 00 Port 2 Spare Table 5 17 Port Speed Bits Speed Bit 2 Bit 1 Bit 0 100 Mbps 0 0 0 200 Mbps 0 0 1 400 Mbps 0 1 0 Not Supported 0 1 1 Not Supported
98. eived from the Control Computer contains a newer value the newer value will be used in all future STOF messages instead of the value in this register Note This value may be overridden by the STOF offset values in the first packet received by the RN from the CC Table 5 30 Datapump STOF Offset Register Bit Description 00 31 Datapump STOF offset 5 2 36 Channel Number Register Address 030C H Length 32 bits Read Write Use this register to specify the channel number of the remote node the channel is to simulate Only messages addressed to this channel number or to the STOF channel are received Table 5 31 Channel Number Register Bit Description 06 32 Reserved 00 05 Channel number 5 2 37 Receive STOF Offset In Use Register Address 0310 H Length 32 bits Read Only This register contains the receive STOF offset currently in use in psec When the node is started this is the same as the Receive STOF Offset Register If the CC updates the STOF offsets the new value is stored in this register See Receive STOF Offset Register on page 5 16 Table 5 32 Receive STOF Offset In Use Register Bit Description 00 31 Receive STOF offset EXC 1394PCI amp EXC 1394PCle User s Manual page 5 17 Chapter 5 Remote Node Operation 5 2 38 Transmit STOF Offset In Use Register Address 0314 H Length 32 bits Read Only This register contains the transmit STOF offset currently in use in usec When the node is
99. emory block Base 1 is 128 bytes in size and contains the Global Registers For more information see Global Registers Map on page 2 15 The EXC 1394PCle requests three memory blocks e The first memory block Base 0 is 8 MB in size and contains the memory space for the nodes on the board For more information see Node Memory Space Map on page 2 14 e The second memory block Base 2 is 4 KB in size and contains the Global Registers For more information see Global Registers Map on page 2 15 e The third memory block Base 4 is 8 KB in size and contains the DMA Registers For more information see DMA Registers for PCI Express on page 2 10 2 2 PCI Configuration Space Header The EXC 1394PCI and EXC 1894PCle include a PCI Configuration Space Header as required by PCI specification The registers contained in this header enable software to set up the Plug and Play operation of the board and set aside system resources page 2 2 Excalibur Systems Chapter 2 PCI Architecture MAX_LAT MIN_GNT Interrupt Pin Interrupt Line 003C H 0038 H 0084 H coo H 202c H 2028 H 0024 H Base Address Register 4 not used 0020 H Base Address Register 3 not used 001C H Base Address Register 2 not used 0018 H 0014 H coro sist Hessertyne 0 Latency Timmer Gachetine Sze oooc voos H Status Register Command Register 0004 H Device ID Vendor ID 0000 H J O 0 Figure 2
100. entinel 1394 Header Word ASM Header Payload Packet trailer Note The 1394 Header CRC and 1394 Data CRC are stripped from the packet and are not stored by the node page 7 28 Excalibur Systems Chapter 7 Bus Monitor Operation Table 7 46 describes the fields in the Receive Message Status Word Table 7 46 Receive Message Status Word for a General Message Bit Description 15 Message complete 14 Message in progress 13 Matched trigger 12 Header length mismatch length in 1394 header and payload length in ASM header disagree 10 11 Reserved 09 STOF offset timing error node transmitted at wrong offset only if using STOF Offsets Table 07 08 Reserved 06 Lost quadlets Some quadlets that were received on the bus were lost probably due to heavy communications traffic 05 Reserved 04 Low word count actual length does not match 1394 header length 03 Reserved 02 Bad CRC or high word count actual length does not match 1394 header length 01 Bad VPC 00 Message error an error occurred specified in one of the other bits EXC 1394PCI amp EXC 1394PCle User s Manual page 7 29 Chapter 7 Bus Monitor Operation Table 7 47 describes the fields in each entry of the bus monitor Linked List structure for STOF messages Table 7 47 Word 0 10 11 12 13 14 15 16 17 18 19 10 words 2 words Bus Monitor Linked List Structure for a STOF Message Description Sentinel has four legal value
101. er Address 014C H Length 16 bits Read Write Use this register to control what the node does when a message matching a trigger is received Table 7 27 Trigger Position Register Bit Description 02 15 Reserved 00 01 0 Trigger at beginning when the trigger is encountered the monitor stores one complete buffer of data with the message that triggered as the oldest message in the buffer 1 Trigger at end the monitor stores all messages until the trigger message is encountered It stops with the trigger message being the last message in the buffer 2 Trigger in middle the monitor stores all messages until the trigger message is encountered It then continues storing messages until it fills half of the buffer The trigger message is then in the middle of the resulting buffer EXC 1394PCI amp EXC 1394PCle User s Manual page 7 17 Chapter 7 Bus Monitor Operation 7 2 32 Linked List Fill Control Register Address 014E H Length 16 bits Read Write Use this register to control the behavior of the node when the Linked List data buffer is full Table 7 28 Linked List Fill Control Register Bit Description 01 15 reserved 00 1 Stop node when buffer is full 0 Overwrite start of buffer when buffer is full 7 2 33 Control Table Selection Register Address 0150 H Length 16 bits Read Write Use this register to select which of the Control Tables to use Table 7 29 Control Table Selection
102. er data block and a selectable buffer size Interrupts can be requested for all messages or for specific data buffers as well as various error conditions Note When the first message from the CC assigns new offsets to a node in RN mode the node automatically adjusts its STOF offsets The following topics are covered 5 1 RN Memory Mea ies oi Es Si as toe ic tae a a i Aa ak ac toe enne 5 2 5 2 RN Mode Register Definition RR RR RR RR RR RR RR Re RR ee ee ee ee 5 4 5 2 1 Hardware Revision Register iese se ees se ee ee ee ee ee ee ee Ke ee Ge ke ee ee ee ee ee ke ee ee 5 4 5 2 2 Excalibur Node ID Register iii se ee ee ee ee ee ee Ee ee ee ee Re Re ee ee ee ee ee ee ee ee ee ee 5 4 5 2 3 Interrupt Status Register cenin sees Eie EE ee RE a AR AK bee ek Ge de a ede ee 5 4 5 2 4 Interrupt Mask Register iis e ee ee Re AR ee ee Ee ee ee ee ee Ke Re ee ee ee ee ee ee ee ee ee ee ee 5 5 5 2 5 Reset Time Register REEN ee seinen Ke sel EE ge Oe Ve ee Ee ee Pe Ee eie 5 6 5 26 Time Tag Registers HEER EES gee a ee EEN Ee Ee N ge Ee RS SERE Ee ge ee 5 6 52 7 ResetNode Register si EEN ERG RE geo Ee Gee Eve Ke AE Gee ego gegee Ee 5 6 5 2 8 Transmit Message Counter Register iss ee ee ee Ee Ke Re Ge ee ee ee ee ee ee ee ee ee 5 7 5 2 9 Receive Message Counter Register iii ee se ee ee ee AR ee ee ee Re AR Ke ee ee 5 7 5 2 10 STOF Message Counter Register see ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee
103. er s Manual Control Computer Operation page 4 11 Chapter 4 Table 4 17 Port Status Register Bit Description 24 31 Reserved 23 Port 0 Connected 22 Port 0 Receive OK 21 Port 0 Beta Mode 20 Port 0 Bit 0 of maximum possible speed 19 Port 0 Bit 1 of maximum possible speed 18 Port 0 Bit 2 of maximum possible speed 17 Port 0 Spare 16 Port 0 Spare 15 Port 1 Connected 14 Port 1 Receive OK 13 Port 1 Beta Mode 12 Port 1 Bit O of maximum possible speed 11 Port 1 Bit 1 of maximum possible speed 10 Port 1 Bit 2 of maximum possible speed 09 Port 1 Spare 08 Port 1 Spare 07 Port 2 Connected 06 Port 2 Receive OK 05 Port 2 Beta Mode 04 Port 2 Bit 0 of maximum possible speed 03 Port 2 Bit 1 of maximum possible speed 02 Port 2 Bit 2 of maximum possible speed 01 Port 2 Spare 00 Port 2 Spare Table 4 18 Port Speed Bits Speed Bit 2 Bit 1 Bit 0 100 Mbps 0 0 0 200 Mbps 0 0 1 400 Mbps 0 1 0 Not Supported 0 1 1 Not Supported 1 0 0 page 4 12 Control Computer Operation Excalibur Systems Chapter 4 Control Computer Operation 4 2 21 1394 Node ID Register Address 00C8 H Length 32 bits Read Only This register contains the node ID assigned automatically during bus configuration Table 4 19 1394 Node ID Bit Description 00 31 1394 Node ID 4 2 22 CC Run Configuration Register Address 00CC H Length 32 bits Read Write Use this register to specify the type of node operation Single Shot Continuous or a combination of t
104. ess of Contiguous Host Memory Address 0010 H Length 32 bits Low Address 0014 H Length 32 bits High Read Write The start address of the Contiguous Host Memory must be written to this register by the user The address stored in this register is automatically incremented during the process of the DMA transfer The current value in this register is the address following the address of the last requested data Upon successful completion of a transfer this register contains the following value Start Address Read Transfer Size where Start Address is the start address of the Contiguous Host Memory page 2 12 Excalibur Systems Chapter 2 PCI Architecture 2 4 5 DMA1 Data Transfer Size Address 0018 H Length 32 bits Read Write This register contains the total amount of data in bytes to be read during a DMA read transfer The total transfer size must be written to this register by the user The transfer size value stored in this register is automatically decremented during the process of the DMA transfer The current value stored indicates the remaining amount of data that needs to be transferred Upon successful completion of a DMA read transfer the value of this register should be 0 24 6 DMA Control Register Address 001C H Length 32 bits Read Write This register contains information about and controls the DMA read data transfer Table 2 9 DMA1 Control Register Bit Description 12 31 Reserved set to 0
105. expect to receive STOF 7 2 23 Last STOF Message Status Register Address 0102 H Length 16 bits Read Write This register contains the status of the STOF message area Check this register to see whether the data in the STOF Message area and STOF Time Tag area are consistent and to check for errors in the STOF messages EXC 1394PCI amp EXC 1394PCle User s Manual page 7 13 Chapter 7 Table 7 19 Bit 15 14 09 13 08 07 06 05 04 03 02 01 00 Bus Monitor Operation Last STOF Message Status Register Description Message complete Message in progress Reserved Vehicle time not progressing STOF timing error early or late STOF Lost quadlets Some quadlets that were received on the bus were lost probably due to heavy communications traffic Reserved Low word count actual length does not match 1394 header length Reserved Bad CRC or high word count actual length does not match 1394 header length Bad VPC Message error an error occurred specified in one of the other bits 7 2 24 Last STOF Message Area Address 0104 H Length 11 32 bit words Read Only This register contains the last STOF message received by the node When the STOF is updated the Last STOF Message Status Register is set to 0 and the Message In Progress bit is set When the update is complete the STOF Message Counter Register is updated the Message In Progress bit is cleared the Message Complete bit is set
106. f CC did not transmit to node at node s receive offset occurs at the end of the receive window Trigger if CC transmitted to node at the wrong offset Trigger if node did not transmit at its transmit offset occurs at the end of the transmit window Trigger if node transmitted at wrong offset Reserved Interrupt if node did not transmit at its Datapump offset occurs at the end of the Datapump window Interrupt if CC did not transmit to node at node s receive offset occurs at the end of the receive window Interrupt if CC transmitted to node at the wrong offset Interrupt if node did not transmit at its transmit offset occurs at the end of the transmit window Interrupt if node transmitted at wrong offset Table 7 39 describes the fields of the Bus Monitor STOF Offsets Table Status Word Table 7 39 Bus Monitor STOF Offsets Table Status Word Bit Description 05 15 Reserved 04 Node did not transmit at its Datapump offset 03 CC did not transmit to node at node s receive offset 02 CC transmitted to node at the wrong offset 01 Node did not transmit at its transmit offset 00 Node transmitted at wrong offset 7 2 46 Data Trigger Table The Data Trigger Table can contain up to 20 data trigger definitions Each trigger has a Control Word allowing the trigger to be marked on or off and a Status Word which indicates whether the trigger was triggered This table is read once when Monitor mode is started Changes made whil
107. ffer is not in the progress of being written to but the buffer that you froze is the active buffer it is not recommended to read from that buffer Instead unfreeze the buffer and read a different buffer However reading the buffer will not cause problems with data integrity If the buffer is frozen when the node tries to write to it the data is written to the previous buffer and the message in the previous buffer is overwritten If you are only using one buffer all incoming messages are discarded until you unfreeze the buffer Read and check the Buffer Status Word See Buffer Status Word on page 5 27 Read the buffer After reading the buffer unfreeze the buffer Excalibur Systems Chapter 5 Remote Node Operation Table 5 43 describes the fields of the receive data block header Table 5 43 Data Block Header Word Description 0 1 Data Block Control Word Data Block Status Word Table 5 44 describes the fields of the Data Block Buffer Header Control Word Table 5 44 Data Block Header Control Word Bit 13 15 11 12 08 10 07 04 06 03 00 02 Description Reserved Buffer size 256 512 1K or 2K plus 16 bytes for the first 8 words of the Data Block Buffer This header information is not part of the 1394 message payload see Table 5 45 and Table 5 47 Number of buffers 0 1 buffer 1 2 buffers through 7 8 buffers Interrupt on end of message Reserved Freeze buffer Boolean
108. ftware Tools 1 2 1 Installing the Board Installation of the EXC 1394PClI e board is similar to that of all PCI Local Bus boards The EXC 1894PCI e complies with the Plug and Play specification of the PCI standard Therefore its absolute address is determined by the BIOS at start up J1 VO CONNECTIONS Introduction Caution Wear a suitably grounded electrostatic discharge wrist strap whenever handling the Excalibur board and use all necessary antistatic precautionary measures To install the EXC 1394PCl e 1 Make sure that the computer power source is disconnected 2 Insert the EXC 1394PClI e board into any PCI slot 3 Tighten the EXC 1394PCI e board s PCI bracket with the slot screw to ground the board to the computer EXC 1394PCI amp EXC 1394PCle User s Manual page 1 5 Chapter 1 Introduction 1 3 4 Attach the adapter cable to the board and to the communication bus The cable may be connected to and disconnected from the board while power to the computer is turned on but not while the board is transmitting over the bus 1 2 2 Installing Excalibur Software Tools For hardware and software installation instructions see the readme pdf file on the root folder of the installation CD When downloading new software from the Excalibur website the readme pdf file is contained in the zip file The Excalibur Installation CD you received with your package is the most recent release of the CD
109. g 00011 Reserved 00100 Ack_busy_X 00101 Ack_busy_A 00110 Ack_busy_B 00111 01010 Reserved 01011 Ack_tardy 01100 Ack_conflict_error 01101 Ack_data_error 01110 Ack_type_error 01111 Ack address error 10000 No ack received Note The following codes are added by the link layer and are not part of the IEEE 1394 1995 standard 10001 Ack too long more than 8 bits 10010 Ack too short less than 8 bits 10011 11111 Reserved Table 6 19 1394 Header and Data Area Word Description 0 3 1394 Header quadlets see Figure 6 1 4 256 Payload area length used based on payload length ie 1394 J Data Length Tag Channel Tcode Sync Header id Data pie eooo d Figure 6 1 Asynchronous Stream Transmit Message EXC 1394PCI amp EXC 1394PCle User s Manual page 6 13 Chapter 6 Asynchronous Operation 6 3 2 Asynchronous Receive Message Area This register contains the last Asynchronous message received by the node Its located at 3000 380F H The Asynchronous Receive Message Area has three main sections e Receive Message Information Registers The data in these registers is based on communicate with the firmware but was not received with the message e 1394 Header The 1394 Header that was received with the message e Data Area The Data Area contains the data that was received with the message Its contents vary depending on the type of Asyncronous message Note The data ar
110. ger Position Register Linked List Fill Control Register Control Table Selection Register STOF Offsets Control Register STOF Filter Window Begin Register STOF Filter Window End Register Reserved Memory Select Register Bank Select Register Current Bank Register Reserved PHY Base Registers PHY Port 0 Status Registers PHY Port 1 Status Registers PHY Port 2 Status Registers Reserved EXC 1394PCI amp EXC 1394PCle User s Manual Byte Address 00C4 H 00C8 00D7 H 00D8 H 00DC OODF H OOEO H OOE4 H 00E8 00F3 H 00F4 00F7 H 00F8 00FF H 0100 H 0102 H 0104 H 0130 H 0136 0137 H 0138 H 013A 013B H 013C H 0140 H 0144 H 0148 H 014C H 014E H 0150 H 0152 H 0154 H 0158 H 015C 015F H 0160 H 0162 H 0164 H 0166 0167 H 0168 016F H 0170 0177 H 0178 017F H 0180 0187 H 0188 02FF H Bus Monitor Operation Read Write Read Write Read Only Read Only Read Only Read Only Read Write Read Write Read Only Read Only Read Write Read Only Read Only Read Only Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Only Read Only Read Only Read Only Read Only Page Number 7 12 7 12 7 12 7 12 7 13 7 13 7 13 7 14 7 15 7 15 7 16 7 16 7 16 7 17 7 18 7 18 7 18 7 19 7 19 7 20 7 20 7 21 7
111. gister indicates the current status of the three ports Table 6 12 Port Status Register Bit Description 24 31 Reserved 23 Port 0 Connected 22 Port 0 Receive OK 21 Port 0 Beta Mode 20 Port 0 Speed Bit 0 19 Port 0 Speed Bit 1 18 Port 0 Speed Bit 2 17 Port 0 Spare 16 Port 0 Spare 15 Port 1 Connected 14 Port 1 Receive OK 13 Port 1 Beta Mode 12 Port 1 Speed Bit 0 11 Port 1 Speed Bit 1 10 Port 1 Speed Bit 2 09 Port 1 Spare 08 Port 1 Spare 07 Port 2 Connected 06 Port 2 Receive OK 05 Port 2 Beta Mode 04 Port 2 Speed Bit 0 03 Port 2 Speed Bit 1 02 Port 2 Speed Bit 2 01 Port 2 Spare 00 Port 2 Spare Table 6 13 Port Speed Bits Speed Bit 2 Bit 1 Bit 0 100 Mbps 0 0 0 200 Mbps 0 0 1 400 Mbps 0 1 0 Not Supported 0 1 1 Not Supported 1 0 0 EXC 1394PCI amp EXC 1394PCle User s Manual Asynchronous Operation page 6 9 Chapter 6 Asynchronous Operation 6 2 15 Options Register Address OOF4 H Length 32 bits Read Only This register contains information about the node Table 6 14 Options Register Bit Description 02 15 Reserved 01 1 By default the Vehicle Time quadlet of each STOF message is updated before transmission in CC mode When this bit is lit the option to prevent updating the Vehicle Time quadlet is available see CC Run Configuration Register on page 4 13 0 The option to prevent updating the Vehicle Time quadlet of the STOF message before transmission is not available 00
112. h the Time Tags are synchronized add 1 to the value of the IRIG B time stored into these registers 0 The previous valid IRIG B message should not be stored in the IRIG B registers This bit is automatically reset by the board after the storage of the IRIG B time 08 1 Resets and synchronizes Time Tags of all the nodes to the next rising edge of the on time Reference Point Pr of the IRIG B signal Also sets Bit 09 to a value of in order to store and display the IRIG B time and control functions into the 6 IRIG B registers 0 No reset synchronization of Time Tags relative to the Pr of the IRIG B signal This bit is automatically reset by board after reset of Time Tags Note All bits are read and write 2 7 2 IRIG B Time SBS High Register Address 0020 H Bit 0 Read Only This register contains the MSB of the 17 bit straight binary representation of the seconds of day code word within the IRIG B message 2 7 3 IRIG B Time SBS Low Register Address 0024 H Bits 0 15 Read Only This register contains the lower 16 bits of the 17 bit straight binary representation of the seconds of day code word within the IRIG B message page 2 20 Excalibur Systems Chapter 2 PCI Architecture 2 7 4 IRIG B Time Days Register Address 0028 H Bits 6 15 Read Only This register contains the days value of the BCD time of year subword within the IRIG B coded message 2 7 5 IRIG B Time Hours Register Address 0028
113. he Memory Select Register on page 7 20 use this register to gain read only access to blocks of the 128 MB SDRAM SDRAM cannot be accessed directly When using this register the node copies a 1 MB block of SDRAM to DPRAM where it can be read To use this register write the desired bank number 0 127 to this register The node then copies the selected block from the SDRAM to DPRAM in addresses 100000 1FFFFF H After the contents are copied the node writes the bank number and to the Current Bank Register and sets Bit 15 of that register to 1 which indicates that the contents are valid You can then read the 1 MB block of SDRAM directly from the DPRAM window Note This register can only be used when the node is stopped not monitoring Table 7 34 Bank Select Register Bit Description 07 15 Reserved 00 06 The bank number 0 to 127 you would like to access through the DPRAM window page 7 20 Excalibur Systems Chapter 7 Bus Monitor Operation 7 2 39 Current Bank Register Address 0164 H Length 16 bits Read Only This register shows which SDRAM bank is currently displayed in the DPRAM window 100000 H 1FFFFF H and whether the data is valid Table 7 35 Current Bank Register Bit Description 15 1 if bank contents are valid 0 if bank contents are invalid or out of date this bit is cleared when the node is started 07 14 reserved 00 06 IfBit 15 1 this field contains the ban
114. he fields of the Bus Monitor Receive Stack Table 7 43 Bus Monitor Receive Stack Word Description 0 Status 1 Message identifier sending channel bits 0 6 message number bits 7 13 STOF indicator Bit 15 2 3 1394 Header Word 4 6 48 bit Time Tag 7 Reserved page 7 26 Excalibur Systems Chapter 7 Bus Monitor Operation Table 7 44 describes the fields of the Bus Monitor Message Stack Status Word Table 7 44 Bus Monitor Message Stack Status Word Bit Description 15 Message complete 14 Message in progress 09 13 Reserved 08 Vehicle time not progressing 07 STOF timing error early or late STOF 06 Lost quadlets Some quadlets that were received on the bus were lost probably due to heavy communications traffic 05 Reserved 04 Low word count actual length does not match 1394 header length 03 Reserved 02 Bad CRC or high word count actual length does not match 1394 header length 01 Bad VPC 00 Message error an error occurred specified in one of the other bits 7 3 2 Bus Monitor Linked List The 2 MB Dual Port Ram is accessible in real time The 128 MB SDRAM is accessible only when the Start bit is off and is accessed via Bank Select Register You can select to which memory bank the Bus Monitor stores its messages Dual Port RAM or SDRAM via the Memory Select Register page 7 20 The following pointers are provided for navigating the Linked List e Pointer to Most Recent Message o
115. he two Single Shot with transmission from the Single Shot Stack automatically followed by continuous transmission from the Continuous Stack To select the combined option set both bits to 1 Table 4 20 CC Run Configuration Register Bit Description 03 31 Reserved 02 1 Do not update the Vehicle Time quadlet of the STOF message before each STOF message is transmitted Any data provided by the user will be transmitted instead 0 Allow the firmware to update the Vehicle Time quadlet of the STOF message before each STOF message is transmitted default 01 1 Run for one STOF frame transmitting from the Single Shot Stack 0 Do not run using the Single Shot Stack default 00 1 Run continuously using Continuous Stack default 0 Do not run continuously 4 2 23 Pointer to Beginning of Single Shot Stack Address 00D0 H Length 32 bits Read Write Use this register to specify the address at which to put the beginning of the Single Shot Transmit Message Stack EXC 1394PCI amp EXC 1394PCle User s Manual page 4 13 Chapter 4 Control Computer Operation 4 2 24 Pointer to Beginning of Continuous Mode Stack Address 00D4 H Length 32 bits Read Write Use this register to specify the address at which to put the beginning of the Continuous Mode Transmit Message Stack 4 2 25 Pointer to Beginning of Receive Linked List Address 00D8 H Length 32 bits Read Write Use this register to specify the address
116. hicle time not incrementing Interrupt on STOF VPC error Interrupt on STOF timing error missed early or late STOF Interrupt on bus reset Interrupt on data trigger Interrupt on STOF offset error Interrupt on end of STOF receive Reserved Interrupt on end of message Interrupt when CC recognized as failed Interrupt when Network Bus Mode changes Interrupt on message error 7 2 5 Reset Time Register Address 000C H Length 16 bits Read Write Use this register to reset the node s Time Tag Table 7 4 Bit 01 15 00 page 7 6 Reset Time Register Description Reserved Reset Time Tag Resets the Time Tag to 0 All message Time Tags STOF offsets and STOF timing are based on this Time Tag value Bus Monitor Operation Excalibur Systems Chapter 7 Bus Monitor Operation 7 2 6 Time Tag Registers Address 0010 H Length 48 bits Read Only These three registers represent the current value of the Time Tag All message Time Tags STOF offsets and STOF timing are based on this Time Tag value The Time Tag has a precision of 100 nanoseconds per bit The Time Tag should be read from address 10 then 12 then 14 When reading address 10 the Time Tag registers are frozen reading address 14 unfreezes them Table 7 5 Time Tag Registers Address Description 10 Low 16 bits of Time Tag 12 Middle 16 bits of Time Tag 14 High 16 bits of Time Tag 7 2 7 Reset Node Register Address 0018 H Length 16 bits Write O
117. iese ee ee ee ee Re ee Ge Re ee ee ee 2 6 2 3 6 Class Code Register CLCD ee ee ee ee AR Re ee eii Ge Re ee ee ee 2 6 2 3 7 Cache Line Register Size Register CALN ie ee ee ke ee ee AR Re ee ee ee 2 7 2 3 8 Latency Timer Register LAT iese ee ee Re ee ee Re ee ee ee ee Ke ee Ge Re ee ee ee 2 7 2 3 9 Header Type Register HDR ees se ee ee ee ee ee ee ee ee ee Re ee be ee ee ee ke ee ee Re ee ee ee 2 7 2 3 10 Built In Self Test Register BIST ee ee ek ee Ge Re ee ee AR ee ee Ke ee ee ee 2 7 2 3 11 Base Address Registers BADR ee ee ee ee ee ee ee AR ee ee Re ee ee ee 2 7 2 3 12 Cardbus CIS Pointer ui ies EE aiipata ESRA be ee sg RegS EE bene SE ee ese EER ee eb 2 9 2 3 13 Subsystem I EE OE EE EO OR EO OE DE 2 9 2 3 14 SUDVENGOR dIE EE OE EE DE EE 2 9 2 3 15 Expansion ROM Base Address Register XROM 2 9 2 3 16 PCI GapabilitiesPointer i Ee Es SE des lace EE a dek Ge ERG We Ee Re Se ESE Ee 2 9 2 3 17 Interrupt Line Register INTLN ese ee ee ee Re ee ee Re ee Ee AR Ke ee ee Re ee ee ee 2 9 2 3 18 Interrupt Pin Register INTPIN ee ees ese ee ee ee ek ee ee ee ee ee ee Ge Re ee ee ee 2 10 2 3 19 Minimum Grant Register MINGNT ee ee ee ee ee AR ee AR Re ee ee ee 2 10 2 3 20 Maximum Latency Register MAXLAT ee ee ee ee ee ee ee ee ee ee Re ee ee ee 2 10 2 4 DMA Registers for PCI Express sees ee see ee ee ee ee ee ee ee ee 2 10 2 4 1 DMAO Address of Contiguous Host MeMOFY se
118. indow Begin Register Address 0154 H Length 32 bits Read Write Use this register to specify the offset in usec from the STOF message at which to begin recording messages For more information see the STOF Offsets Control Register on page 7 18 Table 7 31 STOF Filter Window Begin Register Bit Description 00 31 Starting offset from STOF offset in usec 7 2 36 STOF Filter Window End Register Address 0158 H Length 32 bits Read Write Use this register to specify the offset in usec from the STOF message at which to stop recording messages For more information see the STOF Offsets Control Register on page 7 18 Table 7 32 STOF Filter Window End Bit Description 00 31 Ending offset from STOF in usec EXC 1394PCI amp EXC 1394PCle User s Manual page 7 19 Chapter 7 Bus Monitor Operation 7 2 37 Memory Select Register Address 0160 H Length 16 bits Read Write Use this register to select whether the node records data in the Dual Port RAM buffer close to 2 MB or the SDRAM buffer 128 MB Use the Dual Port RAM when real time monitoring is required Use 128 MB SDRAM in conjunction with triggering to record a large buffer relating to a specific event Table 7 33 Memory Select Register Bit Description 01 15 Reserved 00 1 128 MB SDRAM buffer selected 0 2 MB DPRAM buffer selected 7 2 38 Bank Select Register Address 0162 H Length 16 bits Read Write When using SDRAM storage see t
119. is register defaults to 12500 upon power up and reset Table 4 24 STOF Period Register Bit Description 00 15 Period in usec to transmit STOF 4 2 30 Last STOF Message Status Register Address 0102 H Length 16 bits Read Write This register contains the status of the STOF message area Check this register to see whether the data in the STOF Message area and STOF Time Tag area are consistent and to check for errors in the STOF messages EXC 1394PCI amp EXC 1394PCle User s Manual page 4 15 Chapter 4 Control Computer Operation Table 4 25 Last STOF Message Status Register Bit Description 15 1 STOF Complete the parts of the STOF message data written by the node and the Time Tag can be read 0 STOF not available e g no STOF has yet been sent or in mid update 14 STOF message queuing in progress do not change or read the data or read the Time Tag 01 13 Reserved 00 1 error in STOF transmit 0 no error 4 2 31 Last STOF Message Area Address 0104 H Length 11 32 bit words Read Only This register contains information on the last STOF message transmitted by the node It also contains the data for the next STOF message to be transmitted Table 4 26 Last STOF Message Area Quadlet Description Read Write 00 1394 Header Word Read Write 01 Control Computer Branch Status Read Write 02 Network Bus Mode Read Write 03 Vehicle State Read Write 04 Vehicle Time Read Only 05 09 Reserved N
120. ite Read Write Read Only Read Only Read Only Write Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Write Read Write Read Only Page Number 5 4 5 4 5 4 5 5 5 6 5 6 5 6 5 6 5 7 5 7 5 7 5 8 5 8 Excalibur Systems Chapter 5 Register Name Port Status Register Reserved Number of Bad STOF Messages for CC Fail Register 1394 Node ID Register Reserved Pointer to Beginning of Transmit Stack Reserved Pointer to Beginning of Datapump Stack Reserved Pointer to Beginning of Receive Stack Pointer to End of Receive Stack Reserved Speed Code Register Reserved Options Register Reserved STOF Period Register Last STOF Message Status Register Last STOF Message Area Last STOF Time Tag Registers Reserved Store STOF Messages Register Reserved Receive STOF Offset Register Transmit STOF Offset Register Datapump STOF Offset Register Channel Number Register Receive STOF Offset In Use Register Transmit STOF Offset In Use Register Datapump STOF Offset In Use Register Reserved Message Type Receive Control Table Message Area EXC 1394PCI amp EXC 1394PCle User s Manual Byte Address OOBC H 00CO0 00C3 H 00C4 H 00C8 H 00CC 00CF H 00D0 H 00D4 H 00D8 H 00DC OODF H OOEO H OOE4 H 00E8 OOEF H 00F0 H 00F2 00F3 H 00F4 00F7 H 00F8 OOFF H 0100 H 0102 H
121. itten because a message came in when the subsequent buffer would have been the active buffer but was frozen see Accessing the Buffers on page 5 24 07 12 Reserved 06 Lost quadlets Some quadlets that were received on the bus were lost probably due to heavy communications traffic 05 Reserved 04 Low word count actual length does not match 1394 header length 03 Reserved 02 Bad CRC or high word count actual length does not match 1394 header length 01 Bad VPC 00 Message error an error occurred specified in one of the other bits EXC 1394PCI amp EXC 1394PCle User s Manual Remote Node Operation page 5 27 Chapter 6 Chapter 6 Asynchronous Operation Asynchronous Operation Chapter 6 describes operation in Asynchronous mode Asynchronous mode is a simple command response mode In this mode after sending a message the node will not send another message until a response is received or the timeout period defined for the message has passed The one exception is an Asynchronous Stream message When sending an Asynchronous Stream message the node does not wait for a response and another message can be transmitted immediately To check for a new receive message check the Asynchronous Receive Message Area To make sure the receive message is in response to the latest transmit message make sure the Time Tag is later than the transmit message or read the Status byte of the receive message and clear the St
122. ive Message Error Counter Register Address 0098 H Length 32 bits Read Only This register contains a running count of all messages with errors received and stored It does not include messages which did not pass the filters and thus were not saved It is reset to 0 upon power up node reset and when the node is started Table 6 7 Receive Message Error Counter Register Bit Description 00 31 Number of messages with errors received and stored by the node 6 2 9 Discarded Message Counter Register Address 00A0 H Length 32 bits Read Only This register contains a running count of all messages that were discarded by the node It is reset to 0 upon power up node reset and when the node is started Table 6 8 Discarded Message Counter Register Bit Description 00 31 Number of messages received and discarded by the node 6 2 10 Firmware Revision Register Address 00A8 H Length 32 bits Read Only This register contains the revision number of the firmware running on the node 16 bits are used for the major revision and 16 bits are used for the minor revision For example for firmware revision 2 1 2 is stored in the high 16 bits and 1 is stored in the low 16 bits 6 2 11 Mode Select Register Address 00B0 H Length 32 bits Read Write Use this register to set the operational mode of the node page 6 6 Excalibur Systems Chapter 6 Table 6 9 Mode Select Register Bit Value Description 00 31 0 N
123. k number reflected in DPRAM addresses 100000 H to 1FFFFF H 7 2 40 PHY Base Registers Address 0168 H Length 64 bits Read Only These registers contain a copy of the PHY base registers Since the PHY Port Status registers are copied to the node Byte 7 which contains the Page_Select and Port_Select registers for accessing the port registers are not required and are reserved For more information refer to the documentation for the Texas Instruments TSB41BA38 EP chip Note All of the port status registers are accessible at the same time 7 2 41 PHY Port 0 Status Registers Address 0170 H Length 64 bits Read Only These registers contain a copy of the port status registers for Port 0 For more information refer to the documentation for the Texas Instruments TSB41BA3 EP chip 7 2 42 PHY Port 1 Status Registers Address 0178 H Length 64 bits Read Only These registers contain a copy of the port status registers for Port 1 For more information refer to the documentation for the Texas Instruments TSB41BA3 EP chip EXC 1394PCI amp EXC 1394PCle User s Manual page 7 21 Chapter 7 Bus Monitor Operation 7 2 43 PHY Port 2 Status Registers Address 0180 H Length 64 bits Read Only These registers contain a copy of the port status registers for Port 2 For more information refer to the documentation for the Texas Instruments TSB41BA3 EP chip 7 2 44 Monitor Control Tables There are two control tables
124. leared to indicate the end of the stack 02 Interrupt on start of message queuing in progress can change the data pointer 01 Interrupt on end of message queuing complete can change the data 00 Skip this entry Table 4 35 describes the fields of each CC Transmit Stack Status Word Table 4 35 CC Transmit Stack Status Word Bit Description 15 14 13 01 12 00 page 4 20 Message queuing complete Message queuing in progress do not change the data Message queuing beginning do not change the data pointer reserved Message error timed out waiting for message to queue Excalibur Systems Chapter 4 Control Computer Operation 4 3 3 CC Linked List Area The Linked List message area is populated with receive messages Table 4 36 describes the fields of each CC Linked List entry Table 4 36 CC Linked List Structure Word Description 0 Sentinel Has three legal values 1394 H indicates a valid message C1C1 H indicates no message AAAA H indicates time to wrap around to beginning of Linked List Any other value is illegal and probably means that you are not keeping up with the node and there was an overrun Message Status 2 3 Message Counter number of messages received by node since power up or node reset 4 6 48 bit Time Tag 7 8 Reserved 9 Number of 16 bit words from the sentinel of this message until the next sentinel 2 words 1394 Header Word 8 words ASM Header Length based on
125. lete bit is set Table 5 25 Last STOF Message Area Quadlet Description 00 1394 Header Word 01 Control Computer Branch Status 02 Network Bus Mode 03 Vehicle State 04 Vehicle Time 05 09 Reserved 10 Vertical Parity Check Note The 1394 Header CRC and 1394 Data CRC are stripped from the packet and are not stored by the node 5 2 31 Last STOF Time Tag Registers Address 0130 H Length 48 bits Read Only These three 16 bit registers represent the value of the node s Time Tag at the time the last STOF was received Table 5 26 Last STOF Time Tag Registers Word Description 0 Low 16 bits of Time Tag 1 Middle 16 bits of Time Tag 2 High 16 bits of Time Tag 5 2 32 Store STOF Messages Register Address 0138 H Length 16 bits Read Write Use this register to set whether STOF message information will be included in the Receive Message Stack The data associated with the most recent STOF message is always placed in the Last STOF Message area regardless of which option is selected in this register Since some nodes may receive only one message per STOF including EXC 1394PCI amp EXC 1394PCle User s Manual page 5 15 Chapter 5 Remote Node Operation STOF messages in the stack could result in every second entry referring to a STOF message effectively halving the number of entries available for data messages Table 5 27 Store STOF Messages Register Bit Description 01 15 Reserved 00 1 include STOF
126. me Tag Clock nominally 1 MHz and provides the General Purpose Timer resolution as follows Table 2 17 Timer Prescale General Purpose Timer Resolution Timer Prescale General Purpose Time Register Value DEC Resolution usec 0 or 1 1 default 2 2 3 3 10 10 65535 65535 Note The Timer Prescale Register can only be changed when the timer has been stopped 2 8 2 Timer Preload Register Address 0040 H Bits 0 31 Read Write Use this register to set the starting count value for the General Purpose Timer from which it will start to count down The Timer Preload Register can only be changed while the timer is stopped and has a maximum count value of 65535 Note The General Purpose Timer will not start counting if a value of zero is stored in the Timer Preload Register Default value 00 00 page 2 22 Excalibur Systems Chapter 2 PCI Architecture 2 8 3 Timer Control Register Address 0044 H Bits 0 3 Read Write Use this register to control the General Purpose Timer Register The value stored in bits 01 to 08 take effect when the General Purpose timer reaches a value of zero Bit 0 is used to start and stop the General Purpose Timer The values of bits 01 03 can only be changed when the General Purpose Timer Register is stopped Default value 00 00 Table 2 18 Timer Control Register Bit Description 04 15 Reserved set to 0 03 Global reset on count 1 Causes global reset of all installed nodes com
127. mory High 32 bits 0014 H DMA1 Address of Contiguous Host Memory Low 32 bits 0010 H DMAO Control 000C H DMAO Data Transfer Size 0008 H DMAO Address of Contiguous Host Memory High 32 bits 0004 H DMAO Address of Contiguous Host Memory Low 32 bits 0000 H Figure 2 3 DMA Registers Map 24 1 DMAU0 Address of Contiguous Host Memory Address 0000 H Length 32 bits Low Address 0004 H Length 32 bits High Read Write The start address of the Contiguous Host Memory must be written to this register by the user The address stored in this register is automatically incremented during the process of the DMA transfer The current value in this register is the address following the address of the last requested data Upon successful completion of a transfer this register contains the following value Start Address Write Transfer Size where Start Address is the start address of the Contiguous Host Memory 2 4 2 DMAO Data Transfer Size Address 0008 H Length 32 bits Read Write This register contains the total amount of data in bytes to be written during a DMA write transfer The total transfer size must be written to this register by the user The transfer size value stored in this register is automatically decremented during the process of the DMA transfer The current value stored indicates the remaining amount of data that needs to be transferred Upon successful completion of a DMA write transfer the v
128. ms Chapter 9 Ordering Information Chapter 9 Ordering Information Chapter 9 explains which options to indicate when ordering the EXC 1894PClle board Table 9 1 Ordering Information Basic Part Option Description EXC 1394PCI x EXC 1394PCle x E 001 The EXC 1394PCI is a 1394 PCI interface board with up to four nodes Supports CC RN Asynchronous and Bus Monitor modes Note x indicates the number of nodes required 1 3 The EXC 1394PCle is a 1394 PCI Express interface board with up to four nodes Supports CC RN Asynchronous and Bus Monitor modes Note x indicates the number of nodes required 1 3 Extended temperature board 40 85 With conformal coating EXC 1394PCI amp EXC 1394PCle User s Manual page 9 1 Appendix A 1394 Message Formats Appendix A 1394 Message Formats Data Length Tag Channel Tcode Sync 1394 Header 1394 Header CRC CC Branch Status Network Bus Mode Vehicle State STOF Data Vehicle Time Quadlets 4 8 TBD Vertical Parity Check 1394 CRC 1394 Data CRC Figure A 1 STOF Packet Format Note e The Vehicle Time is specified in increments of 25 usec e The 1394 Header CRC and 1394 Data CRC are stripped from the packet and are not stored by the node EXC 1394PCI amp EXC 1394PCle User s Manual pageA 1 1394 Header ASM Header Payload Data Packet Trailer 1394 CRC 1394 Header CRC Message ID Reserved Security No
129. n page 7 15 e Pointer to Least Recent Message on page 7 16 e Pointer to Trigger Message on page 7 16 e Pointer to Beginning of Receive Linked List on page 7 12 Note The Pointer to Beginning of Receive Linked List is only valid when the Linked List is in Dual Port RAM Otherwise access the Linked List through the Banked Window See Banked Window into SDRAM on page 7 31 When the Linked List is stored in SDRAM the other three pointers are offsets into SDRAM EXC 1394PCI amp EXC 1394PCle User s Manual page 7 27 Chapter 7 Bus Monitor Operation Table 7 45 describes the fields in each entry of the bus monitor Linked List structure Table 7 45 Bus Monitor Linked List Structure for a General Message Word Description 0 2 words 8 words Length based on payload length 8 words Sentinel has four legal values 1394 H indicates a valid general message This value is not valid for STOF messages 570F H indicates a STOF message This value is not valid for general messages C1C1 H indicates no message AAAA H indicates time to wrap around to beginning of Linked List Any other value is illegal and probably means that you are not keeping up with the node and there was an overrun Message Status Receive Message Counter number of messages received by node since power up or node reset 48 bit Time Tag Reserved Number of 16 bit words from the sentinel of this message until the next s
130. n saving the Linked List in SDRAM When saving the Linked List to DPRAM there is no Message Stack 7 2 27 Pointer to Most Recent Message Address 013C H Length 32 bits Read Only This register contains a pointer as an offset from the beginning of DPRAM or SDRAM depending on the option selected in the Memory Select Register to the beginning of the last complete message received by the node Table 7 23 Pointer to Most Recent Message Bit Description 00 31 Pointer to sentinel of most recent message in the buffer EXC 1394PCI amp EXC 1394PCle User s Manual page 7 15 Chapter 7 Bus Monitor Operation 7 2 28 Pointer to Least Recent Message Address 0140 H Length 32 bits Read Only This register contains a pointer as an offset from the beginning of DPRAM or SDRAM depending on the option selected in the Memory Select Register to the beginning of the oldest complete message received by the node Table 7 24 Pointer to Least Recent Message Bit Description 00 31 Pointer to sentinel of the oldest message in the buffer 7 2 29 Pointer to Trigger Message Address 0144 H Length 32 bits Read Only This register contains a pointer as an offset from the beginning of DPRAM or SDRAM depending on the option selected in the Memory Select Register to the beginning of the message which triggered the node to halt where such a message exists Such a message will not exist when the node was triggered by an event such a
131. nd Always set to 0 Invalidate Enable 03 Special Cycle Enable Always set to 0 02 Bus Master Enable For PCI Always set to 0 For PCI Express Always set to 1 01 Memory Access Enable Always set to 1 00 VO Access Enable Since the EXC 1394PCl e board does page 2 4 not use I O space the value of this register is ignored Excalibur Systems Chapter 2 PCI Architecture 2 3 4 PCI Status Register PCISTS Address 0006 H Length 16 bits Read Only This register contains the PCI status information Table 2 2 Bit 15 14 13 12 11 09 10 08 07 06 05 04 00 03 PCI Status Register for PCI Bit Name Description Detected Parity Error Signaled System Error Received Master Abort Received Target Abort Signaled Target Abort Device Select DEVSEL Timing Status Data Parity Reported Fast Back to Back Capable Reserved 66MHz capable Capability List enable Reserved EXC 1394PCI amp EXC 1394PCle User s Manual This bit is set whenever a parity error is detected It functions independently from the state of Command Register Bit 6 This bit may be cleared by writing a 1 to this location Not used Not used Not used This bit is set whenever this device aborts a cycle when addressed as a target This bit can be reset by writing a 1 to this location Set to 10 slow timing Not used Set to 1 Set to 0 Set to 1 page 2 5 Chapter 2 Table 2 3 Bit 15 14 13 12 11
132. nd seconds 2 4 Word Set of bits reserved for decoding various control identification and other special purpose functions 3rdWord Seconds of day weighted in straight binary seconds SBS notation These three words can be stored and displayed in the IRIG B global registers 0020 002B H For the location of the registers on the memory map see Global Registers Map on page 2 15 Note The synchronization of IRIG B time can take up to two seconds IRIG B functions are meant to be used on an occasional basis not on a constant basis EXC 1394PCI amp EXC 1394PCle User s Manual page 2 19 Chapter 2 PCI Architecture 2 7 1 Sync IRIG B Register Address 0020 H Bits 08 10 Read Write Use this register to control the synchronization of a node s Time Tags relative to the IRIG B input signal and the display of the IRIG B time within the IRIG B Time registers Table 2 16 Sync IRIG B Register Bit Description 10 1 Set by board to indicate that the current IRIG B time has been stored in the IRIG B registers 0 No IRIG B time has been stored in the IRIG B registers This bit must be reset after the board has written a 1 09 1 Stores and displays the IRIG B time and control functions into the 6 IRIG B registers 0014 001E H corresponding to the previous valid IRIG B message If bit 08 is set then the IRIG B time is stored at the same time that the Time Tags are reset To calculate the real time to whic
133. nly Use this register to reset the node Table 7 6 Reset Node Register Bit Description 01 15 Reserved 00 Reset Node resets the node clears the control registers and resets the Time Tag 7 2 8 Receive Message Counter Register Address 0088 H Length 32 bits Read Only This register contains a running count of all messages received and stored by the node It does not include STOF messages which are counted separately It does not include messages which did not pass the filters and thus were not saved It is reset to 0 upon power up node reset and when the node is started Table 7 7 Receive Message Counter Register Bit Description 00 31 Number of messages received and stored by the node EXC 1394PCI amp EXC 1394PCle User s Manual page 7 7 Chapter 7 Bus Monitor Operation 7 2 9 STOF Message Counter Register Address 0090 H Length 32 bits Read Only This register contains a running count of all STOF messages received by the node It is reset to 0 upon power up node reset and when the node is started Table 7 8 STOF Message Counter Register Bit Description 00 31 Number of STOF messages received by the node 7 2 10 Receive Message Error Counter Register Address 0098 H Length 32 bits Read Only This register contains a running count of all messages with errors received and stored It does not include messages which did not pass the filters and thus were not saved It is reset to 0 upon po
134. node does not wait for a response and another message can be transmitted immediately Note Startup and Initializing modes are not supported 1 1 1 Board Features General Features Supports up to three IEEE 1394 nodes with three ports per node IEEE 1394b PHY Operating modes CC RN Asynchronous or Bus Monitor Supports AS56438 Autonomous operation in all modes 2 MB dual port RAM per node 128 MB SDRAM per node 48 bit Time Tag Polling or interrupt driven Real time operation Programmable STOF offsets Flexible interrupt support Receive message filtering Control Computer Support for unique initial frame for changing STOF offsets Single Shot and Continuous stacks Two receive offsets for each node Error injection 1394 header error ASM header error Footer quadlet error page 1 2 Excalibur Systems Chapter 1 Introduction Remote Node Transmits at predefined STOF offsets Receives data any time during the STOF frame Multiple receive buffers up to eight STOF error detection Configurable data blocks Bus Monitor Real time monitoring with 2 MB dual port RAM 128 MB buffer for later analysis STOF error detection e J e e Several triggering options for capturing current bus data Physical Characteristics e Dimensions 157 0 mm x 107 0 mm e Weight 140 grams Operation Environment e Temperature 0 to 70 C 40 to 85 C optional e Humidity 5 90 noncondensing e MTBF For PCI 73 830
135. nous Operation 6 2 5 Reset Time Register Address 000C H Length 16 bits Read Write Use this register to reset the node s Time Tag Table 6 4 Reset Time Register Bit Description 01 15 Reserved 00 Reset Time Tag Resets the Time Tag to 0 All message Time Tags STOF offsets and STOF timing are based on this Time Tag value 6 2 6 Time Tag Registers Address 0010 H Length 48 bits Read Only These three registers represent the current value of the Time Tag The Time Tag has a precision of 100 nanoseconds per bit The Time Tag should be read from address 10 then 12 then 14 When reading address 10 the Time Tag registers are frozen reading address 14 unfreezes them Table 6 5 Time Tag Registers Address Description 10 Low 16 bits of Time Tag 12 Middle 16 bits of Time Tag 14 High 16 bits of Time Tag 6 2 7 Receive Message Counter Register Address 0088 H Length 32 bits Read Only This register contains a running count of all messages received and stored by the node It does not include STOF messages which are counted separately It does not include messages which did not pass the filters and thus were not saved It is reset to 0 upon power up node reset and when the node is started Table 6 6 Receive Message Counter Register Bit Description 00 31 Number of messages received and stored by the node EXC 1394PCI amp EXC 1394PCle User s Manual page 6 5 Chapter 6 Asynchronous Operation 6 2 8 Rece
136. ode was initialized but was not yet set into an operational mode Remote Node RN Mode Control Computer CC Mode Bus Monitor Mode A OO N Asynchronous Mode 6 2 12 Start Register Address 00B4 H Length 32 bits Read Write Use this register to start and stop the operations of the node Table 6 10 Start Register Bit Description 01 31 Reserved 00 1 Start Operation 0 Stop Operation 6 2 13 Excalibur Node Status Register Address 00B8 H Length 32 bits Read Only Asynchronous Operation This register indicates the current status of the node It also provides power on self test information EXC 1394PCI amp EXC 1394PCle User s Manual page 6 7 Chapter 6 Asynchronous Operation Table 6 11 Excalibur Node Status Register Bit Description 31 Reserved 30 Message fragment detected the receive FIFO had part of a message There was probably an overrun or other technical glitch in receiving 29 Out of frame message received received a message before first STOF or after missing STOFs 17 29 Reserved 16 Wrong LLC version indicates that the link layer chip had technical difficulties 5 15 Reserved 04 1 Running 0 Halted 03 1 Self Test Passed 0 Self Test Failed 02 Reserved 01 1 RAM test passed 0 RAM test failed 00 1 Ready 0 Not ready page 6 8 Excalibur Systems Chapter 6 6 2 14 Port Status Register Address OOBC H Length 32 bits Read Only This re
137. pleted 0 No effect 02 Interrupt on count 1 Output an interrupt see Interrupt Status Register on completed page 2 16 0 No effect 01 Reload mode 1 Reload mode 0 Non reload One shot mode 00 Start Stop 1 Start 0 Stop 2 8 4 General Purpose Timer Register Address 0048 H Bits 0 31 Read Only This register stores the current count value of the General Purpose Timer The General Purpose Timer is controlled by the Timer Control Register When the General Purpose Timer is started it counts down to zero at which point either an interrupt can be generated and or all installed nodes can be reset If the General Purpose Timer is in reload mode then the current value in Timer Preload Register is stored into the General Purpose Timer and the timer starts to count down from this value If the General Purpose Timer is in non reload one shot mode when it reaches zero it stops and a value of zero is displayed in the General Purpose Timer Register In this case Bit 0 the Start Stop bit of the Timer Control Register is automatically set to zero If the General purpose Timer Register is then started it starts to count from the current Timer Preload Register value automatically without the need to do a write to the Timer Preload Register At any point in time the General Purpose Timer can be stopped at the current count value When a start is then issued the General purpose Timer starts to count down from this current count value
138. pump messages It is ready to receive data at any time during the STOF frame Received data can be filtered by a combination of message number and transmitting RN message type Data blocks are configurable for each message type with up to eight buffers per data block and a EXC 1394PCI amp EXC 1394PCle User s Manual page 1 1 Chapter 1 Introduction selectable buffer size Interrupts can be reguested for all messages or for specific data buffers as well as various error conditions Bus Monitor mode In Bus Monitor mode the node receives all bus messages that pass through its ports and stores them in memory with their timestamps Filtering is available for storing only specific messages Triggering is available to capture a snapshot of data surrounding a specific event Data can be recorded either to the almost 2 MB Dual Port RAM buffer or to a 128 MB SDRAM buffer The Dual Port RAM can be used for real time monitoring The 128 MB SDRAM should be used in conjunction with triggering to record a large buffer relating to a specific event 1 MB at a time can be accessed via DPRAM when the node is stopped Asynchronous mode Asynchronous mode is a simple command response mode In this mode after sending a message the node will not send another message until a response is received or the timeout period defined in the message has passed The one exception is an Asynchronous Stream message When sending an Asynchronous Stream message the
139. r is not implemented on the EXC 1394PCI e The value at power up is 0000 H 2 3 13 Subsystem ID Address 002C H Length 16 bits Read Only The value at power up is 0000 H 2 3 14 Subvendor ID Address 002E H Length 16 bits Read Only The value at power up is 0000 H 2 3 15 Expansion ROM Base Address Register KROM Address 0030 H Length 32 bits Read Only This register is not implemented on the EXC 1394PCI e The value at power up is 0000 H 2 3 16 PCI Capabilities Pointer Address 0034 H Length 8 bits Read Only The PCI Capabilities Pointer Cap Pointer indicates the location of the PCI Capabilities Identification ID Register The Capabilities ID Register stores a pointer to a structure within the configuration space With a known Capabilities ID value the associated structure can be found during the scanning process The value at power up is 0050 H 2 3 17 Interrupt Line Register INTLN Address 003C H Length 8 bits Read Only This register indicates the interrupt routing for the PCI Controller The value of this register is system architecture specific For 86 based PCs the values in this register correspond with the established interrupt numbers associated with the dual 8259 controllers used in those machines the values of 0001 to OOOF H correspond with the IRQ numbers 1 through 15 and the values from 0010 H to OOFE H are EXC 1394PCI amp EXC 1394PCle User s Manual pag
140. re STOF Messages Register ees se ee ee ee Re ee ee Re ee Ge ee ee ke ee ee 7 15 7 2 27 Pointer to Most Recent Message iese ee ee ek ee ee ee ee ee ee Re ee ee ee 7 15 7 2 28 Pointer to Least Recent Message ie ee ee se ee Ee ee RA Re ee ee ee ee ee ee 7 16 7 2 29 Pointer to Trigger Message ee ee ee ee Re AR Ke ee ee ee ee ee ee Re ee ee ee 7 16 7 2 30 Trigger Control Register se Es ge See see ee geo ee EE Ee pes 7 16 7 2 31 Trigger Position Register ees see ee ee ee ee ee Re ee ee ee AR ke ee Ge ee ee ee ee 7 17 7 2 32 Linked List Fill Control Register ees se ee ee ee ek ee ee ee ee ee ee Ge Re ee ee ee 7 18 7 2 33 Control Table Selection Register ees se ee ee Re ee Ge Re ee ee ee ke ee ee 7 18 7 2 34 STOF Offsets Control Register sisarena hiana ee ee ee ke ee ee 7 18 7 2 35 STOF Filter Window Begin Register ees se ee ee ek ee Ge Re ee Ee ee ee ke ee ee 7 19 7 2 36 STOF Filter Window End Register esse see ees se ee ee ek ee ee ee Re ee ee ee ee ee ke ee ee 7 19 7 2 37 Memory Select Register iese esse ende se ee eg SEER EES ER ek Ke ee ge ee Ee ee Gee ee ese 7 20 7 2 38 Bank Select Register isi EE NE GE EES Ee See ER SE adidadis Ne Re ge ee 7 20 7 2 39 Current Bank Register ius se EES GEE Ke Ee Ge KERS Ee Dee GE EA Be Edge EE ROES ese 7 21 7 2 40 PHY Base Registers ER Ed SE dais Ed es e Dek EE eee 7 21 7 2 41 PHY Port 0 Status Registers iese se ee ee ee ee Ee Re Re ee ee ee ee ee ee ee ee ee
141. register to start and stop the operations of the node Table 7 12 Start Register Bit Description 01 31 Reserved 00 1 Start Operation 0 Stop Operation 7 2 15 Excalibur Node Status Register Address 00B8 H Length 32 bits Read Only This register indicates the current status of the node It also provides power on self test information EXC 1394PCI amp EXC 1394PCle User s Manual page7 9 Chapter 7 Table 7 13 Bit 31 30 29 17 29 16 05 15 04 03 02 01 00 Excalibur Node Status Register Description Reserved Message fragment detected the receive FIFO had part of a message There was probably an overrun or other technical glitch in receiving Out of frame message received received a message before first STOF or after missing STOFs Reserved Wrong LLC version indicates that the link layer chip had technical difficulties Reserved 1 Running 0 Halted 1 Self Test Passed 0 Self Test Failed Reserved 1 RAM test passed 0 RAM test failed 1 Ready 0 Not ready 7 2 16 Port Status Register Address OOBC H Length 32 bits Read Only This register indicates the current status of the three ports page 7 10 Bus Monitor Operation Excalibur Systems Chapter 7 Table 7 14 Port Status Register Bit Description 24 31 Reserved 23 Port 0 Connected 22 Port 0 Receive OK 21 Port 0 Beta Mode 20 Port 0 Speed Bit 0 19 Port 0 Speed Bit 1 18 Port 0 Spe
142. rs Each buffer contains a Buffer Status Word followed by the 1394 header followed by the message data including ASM header and packet trailer Figure 5 2 shows the contents of an RN Receive Data Block Data Block Control Word Data Block Status Word Buffer 0 Buffer 1 Buffer 2 Buffer 3 Buffer 4 Buffer 5 Buffer 6 Buffer 7 Figure 5 2 RN Receive Data Block Buffer Status Word Reserved Time Tag Reserved 1394 Header Word Message 2 bytes 1 word 2 bytes 1 word 6 bytes 3 words 2 bytes 1 word 4 bytes 2 words 256 512 1024 2048 bytes Note The 1394 Header CRC and 1394 Data CRC are stripped from the packet and are not stored by the node EXC 1394PCI amp EXC 1394PCle User s Manual page 5 23 Chapter 5 Remote Node Operation Accessing the Buffers It is possible that during the process of freezing the desired buffer the desired buffer became the active buffer It is also possible that that buffer is currently being written to To avoid data integrity problems in these cases do the following 1 2 page 5 24 After freezing the desired buffer recheck the active buffer If the desired buffer has become the active buffer check the Buffer Status Word of that buffer to make sure it is not in the progress of being written to See Buffer Status Word on page 5 27 If the buffer is in the progress of being written to do not read the buffer If the bu
143. s 1394 H indicates a valid general message This value is not valid for STOF messages 570F H indicates a STOF message This value is not valid for general messages C1C1 H indicates no message AAAA H indicates time to wrap around to beginning of Linked List Any other value is illegal and probably means that you are not keeping up with the node and there was an overrun Message Status STOF Message Counter number of STOF messages received by node since power up or node reset 48 bit Time Tag Reserved Number of 16 bit words from the sentinel of this message until the next sentinel 1394 Header Word CC Branch Status Network Bus Mode Vehicle State Vehicle Time STOF TBD data quadlets see Figure A 1 VPC Note The 1394 Header CRC and 1394 Data CRC are stripped from the packet and are not stored by the node page 7 30 Excalibur Systems Chapter 7 Table 7 48 Bit 15 14 09 13 08 07 06 05 04 03 02 01 00 Bus Monitor Operation Receive Message Status Word for a STOF Message Description Message complete Message in progress Reserved Vehicle time not progressing STOF timing error early or late STOF Lost quadlets Some quadlets that were received on the bus were lost probably due to heavy communications traffic Reserved Low word count actual length does not match 1394 header length Reserved Bad CRC or high word count actual length does not match 13
144. s a bus reset which is not related to any message In this event the contents of this register will be zero Table 7 25 Pointer to Trigger Message Bit Description 00 31 Pointer to sentinel of the message which triggered the node to stop 7 2 30 Trigger Control Register Address 0148 H Length 32 bits Read Write Use this register to set up events that will stop the node Use this register to like an oscilloscope trigger to focus on a particular event It is particularly useful when used in conjunction with the 128 MB SDRAM buffer since the data in SDRAM cannot be viewed in real time Use the trigger to stop bus monitoring when the buffer contains the desired data Use this register in conjunction with the Trigger Position Register on page 7 17 page 7 16 Excalibur Systems Chapter 7 Bus Monitor Operation Table 7 26 Trigger Control Register Bit Description 13 31 Reserved 12 Trigger when STOF vehicle time not incrementing 11 Trigger on STOF VPC error 10 Trigger on STOF timing error missed early or late STOF 09 Trigger on bus reset 08 Trigger on data quadlet s Enable Trigger Control Table see Data Trigger Table on page 7 24 07 Trigger on STOF offset error for more information see the Bus Monitor STOF Offsets Table status for each channel 03 06 Reserved 02 Trigger when CC recognized as failed 01 Trigger when Network Bus Mode changes 00 Trigger on message error 7 2 31 Trigger Position Regist
145. s register contains a running count of all messages received and stored by the node It does not include messages which did not pass the filters and thus were not saved It is reset to 0 upon power up node reset and when the node is started Table 4 9 Receive Message Counter Register Bit Description 00 31 Number of messages received and stored by the node 4 2 11 STOF Message Counter Register Address 0090 H Length 32 bits Read Only This register contains a running count of all STOF messages transmitted by the node It is reset to 0 upon power up node reset and when the node is started Table 4 10 STOF Message Counter Register Bit Description 00 31 Number of STOF messages transmitted by the node 4 2 12 Receive Message Error Counter Register Address 0098 H Length 32 bits Read Only This register contains a running count of all messages with errors received and stored It does not include messages which did not pass the filters and thus were not saved It is reset to 0 upon power up node reset and when the node is started Table 4 11 Receive Message Error Counter Register Bit Description 00 31 Number of messages with errors received and stored by the node 4 2 13 Transmit Message Error Counter Register Address 009C H Length 32 bits Read Only This register contains a running count of all transmit messages with errors It is reset to 0 upon power up node reset and when the node is started p
146. sages received by the node 5 2 11 Receive Message Error Counter Register Address 0098 H Length 32 bits Read Only This register contains a running count of all messages with errors received and stored It does not include messages which did not pass the filters and thus were not saved It is reset to 0 upon power up node reset and when the node is started EXC 1394PCI amp EXC 1394PCle User s Manual page 5 7 Chapter 5 Remote Node Operation Table 5 10 Receive Message Error Counter Register Bit Description 00 31 Number of messages with errors received and stored by the node 5 2 12 Transmit Message Error Counter Register Address 009C H Length 32 bits Read Only This register contains a running count of all transmit messages with errors It is reset to 0 upon power up node reset and when the node is started Table 5 11 Transmit Message Error Counter Register Bit Description 00 31 Number of transmit messages with errors 5 2 13 Discarded Message Counter Register Address 00A0 H Length 32 bits Read Only This register contains a running count of all messages that were discarded by the node It is reset to 0 upon power up node reset and when the node is started Table 5 12 Discarded Message Counter Register Bit Description 00 31 Number of messages received and discarded by the node 5 2 14 Firmware Revision Register Address 00A8 H Length 32 bits Read Only This register con
147. se ees se se ee es se ee ee ee ee ge ee ee ee 2 6 Table 2 4 Base Address Registers Definition for PCI ee se ee 2 8 Table 2 5 Base Address Registers Definition for PCI Express eee 2 8 Table 2 6 Base Address Register for POLI ee ee ee ee ee ke ee ee ee 2 8 Table 2 7 Base Address Register for PCI Express ie dees se se ee es se ee ee ee ee ke ee ee ee 2 8 Table 2 8 DMAO Control Register ees ee ee ke ee ee ke ee Ge ke ee ee ee ke ee ee ee ke ee 2 12 Table 2 9 DMA1 Control Register ees se ee Re ee ee Se ER ee Se de ee Ge ee ee RA ee 2 13 Table 2 10 Board Identification Register ees se ee ee ee Ge Re ee Ge ke ee ee ke ee 2 16 Table 2 11 Software Reset Register ee ee ee AR ee AR ee AR ee AR ee ee 2 16 Table 2 12 Interrupt Status Register ee se ee se ee ee ee Re ee ek ee ee 2 17 Table 2 13 Interrupt Reset Register ee se ee Ge ee ee ee Re ee ee ke de ee ee 2 17 Table 2 14 Node Info Registers arnore eE A dee Re ee ee ee dee ee ee ee 2 18 Table 2 15 Time Tag Clock Select Register se ee ee ee AA ee 2 18 Table 2 16 Sync IRIG B Register ss ed ese se ed ed ee ee de ee e ee de se 2 20 Table 2 17 Timer Prescale General Purpose Timer Resolution iese ees ees 2 22 Table 2 18 Timer Control Register iss sees esse ee ks ea 2 23 page vi Excalibur Systems Table 3 1 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 4 7 Table 4 8 Table 4 9 Table 4 10 Table 4
148. sion Identification Register RID ies se ee EA ER RA Re AR Ge Re Re ee ee ee 2 6 2 3 6 Class Code Register CLCD ee ee ee ee ee ee Ee AR ee ee Re ee ee ee ee ee 2 6 2 3 7 Cache Line Register Size Register CALN ee ee ee ee GR Re ee ee AR ee ee 2 7 2 3 8 Latency Timer Register AT ee ek ee ee Re ee ee ee ek ee ee Re ee ee ee ee ee ee ee 2 7 2 3 9 Header Type Register HDR ii iese ede ee esse ee dee ed ee Ge ke gee ee Ke ee eek ee dee Ed de ee 2 7 2 3 10 Built In Self Test Register BIST ee ee ek ee Ge Re ee ee AA GR ee ee Re ee ee ee 2 7 2 3 11 Base Address Registers BADR c eccececeeeeeeeeeaeeeeeeeseceeeaeeeeeeeeeeeenaees 2 7 2 3 12 Cardbus ClS de ER BE OER EE EE 2 9 2 3 13 Subsystem EE OE EE EE OE 2 9 2 3 14 Subvendor Di EE RE ES Ge DE Des Ee Ben REDE i eee 2 9 2 3 15 Expansion ROM Base Address Register XROM 2 9 2 3 16 PCI Capabilities Pointer eise sesse de ks see RE Ke GE priredi ROG KA Ee EE Ge We EDE ee Ee be 2 9 2 3 17 Interrupt Line Register INTLN ese ee ee ek ee Ge Re ee ee ee ee Ke ee Ge Re ee ee ee 2 9 2 3 18 Interrupt Pin Register INTPIN ee ees se ee ee ee Re ee ee ee ee ee ee Re ee ee ee 2 10 2 3 19 Minimum Grant Register MINGNT ee ee ee ee ee AR ee ee Re ee ee ee 2 10 2 3 20 Maximum Latency Register MAXLAT iese ee se ee ee ee ee ee ee ee ee ee ee ee ee 2 10 2 4 DMA Registers for PCI Express ee ee ee ee ee ee ee ee ee ee ee 2 10 24 1 DMAO A
149. smit Messages Table 4 32 describes the fields of the Transmit Message Data Area Table 4 32 Transmit Message Data Area Word Description 0 1 1394 Header quadlet 2 9 ASM Header Length based on Payload payload length Note The data area must not contain the header CRC the data CRC or the trailer The trailer is comprised of the three STOF offsets and the VPC and is automatically generated by the firmware based on the values in the STOF Offsets Table The interrupts which can be set in the Control Word are reflected in the Interrupt Status Register bits 30 and 31 See Interrupt Mask Register on page 4 5 page 4 18 Excalibur Systems Chapter 4 Control Computer Operation Figure 4 1 shows the information that you must supply in a Transmit Message 1394 L Data Length Tag Channel Tcode Sync Header Message ID ASM J Reserved Security Header N Node ID Priority Message Payload Data Length gt Health Status Word Message Data Word 0 Heartbeat Message Data Word 1 Payload lt Data e Message Data Word Length 1 Figure 4 1 Transmit Message 4 3 2 CC Transmit Stacks You can configure the Control Computer to use the Single Shot Stack the Continuous Stack or both The Single Shot Stack is transmitted once and the Continuous Stack is transmitted repeatedly When both stacks are selected the contents of the Single Shot Stack are transmitted once followed by the contents of the Continuous S
150. sse ees se se ee ee ee ee Ge Re ee ee ee 2 11 2 4 2 DMAO Data Transfer Size ees ee ee ee Re AR Ke ee ee ee ee ee ee Re ee ee ee 2 11 2 4 3 DMAO Control Register ee ee ee ee ee Re AR Ke ee ee ee ee ee ee ke ee ee ee 2 12 244 DMA1 Address of Contiguous Host MeMOFY sesse ees se ke ee ee ee ee Ge ke ee ee ee 2 12 2 4 5 DMA1 Data Transfer Size ees ee ee ee ee Re GR Ke ee ee ee GR ee ee Ge ke ee ee ee 2 13 24 6 DMA1 Control Register ese ee ee ee ee arna i Ge ee ee ke ee ee ee 2 13 2 4 7 DMA Interrupt Status Register iii se ee ee ee ee Re ee ee ee ee ee ee ee ee ee ee ede ee 2 14 2 4 8 Base Address for DMAO and DMA1 Transfers ees see ee ee ee ee ke ee ee ee 2 14 2 5 Node Memory Space Map ees ee ee ee ee RARR ee ee ee ee ee ee 2 14 2 6 Global Registers Map SR Se RS ES ee ge Se 2 15 2 6 1 Board Identification Register ees ee se ee ee ee AR Re ee ee ee ee ee ee Ke ee ee ee 2 16 2 6 2 Software Reset Register 0 c ccsseeeteesenceesecuhertaeseeneedeceheetuoeeeasneetbeneeetees 2 16 2 6 3 Interrupt Status Register Es Ese de GESE Ge DER GR se Ee ke OD EN Ge Ek SE Ee hele ee 2 16 2 6 4 Interrupt Reset Register sees se ee ee ee ee AR Ke ee ee ee ee ee ee ee ke ee ee ee 2 17 2 6 5 N de ed RE ME EE EE EE N 2 17 2 6 6 Time Tag Clock Select Register sees ee ee ee ee AR Ke ee Ge AR ee ee 2 18 2 7 IRIG B Global Registers ee ee ee ee 2 19 2 7 1 Sync IRIG B Regis RR RE RR EE EN 2 20 2 7 2 IRIG B Time SBS
151. started this is the same as the Transmit STOF Offset Register If the CC updates the STOF offsets the new value is stored in this register See Transmit STOF Offset Register on page 5 16 Table 5 33 Transmit STOF Offset In Use Register Bit Description 00 31 Transmit STOF offset 5 2 39 Datapump STOF Offset In Use Register Address 0318 H Length 32 bits Read Only This register contains the Datapump STOF offset currently in use in usec When the node is started this is the same as the Datapump STOF Offset Register If the CC updates the STOF offsets the new value is stored in this register See Datapump STOF Offset Register on page 5 17 Table 5 34 Datapump STOF Offset In Use Register Bit Description 00 31 Datapump STOF offset 5 2 40 Message Type Receive Control Table Use the Message Type Receive Control Table to filter incoming messages Its address range is 1300 13EFF H The CC branch is ignored since a given node receives all its messages from the same CC branch 6400 entries are used The table is indexed by source channel number and message number Table 5 35 describes the fields of each entry in the RN Receive Control Table Table 5 35 Message Type Receive Control Table Word Description Read Write 0 Control Word Write 1 Reserved N A 2 3 32 bit pointer to data block Write 4 5 Reserved N A page 5 18 Excalibur Systems Chapter 5 Remote Node Operation Table 5 36 describes the Receive Control
152. ster CALN Address 000C H Length 8 bits Read Only For PCI The value at power up is 0000 H For PCI Express The value at power up is 0010 H Note This register is not used on the EXC 1894PCI e 2 3 8 Latency Timer Register LAT Address 000D H Length 8 bits The value at power up is 0000 H Note This register is not used on the EXC 1894PCI e 2 3 9 Header Type Register HDR Address 000E H Length 8 bits Read Only This register contains whether the device is single or multifunction The EXC 1394PClf e is a single function PCI device Therefore Bit 7 is set to 0 The value at power up is 0000 H 2 3 10 Built In Self Test Register BIST Address 000F H Length 8 bits Read Only This register is not implemented in the EXC 1394PCI e The value at power up is 0000 H 2 3 11 Base Address Registers BADR Address 0010 0014 0018 001C 0020 0024 H Length 32 bits Read Only These registers are used by the system BIOS to determine the number size and base addresses of memory pages required by the board within host address space The power up value of each register is 0000 H For PCI Two memory pages are required by the board one for the node memory space and one for the Global registers See Table 2 4 EXC 1394PCI amp EXC 1394PCle User s Manual page 2 7 Chapter 2 PCI Architecture Table 2 4 Base Address Registers Definition for PCI Register Offset Size Function
153. tack repeatedly Each stack is pointed to by a register you set Each stack ends when an end of stack marker message is reached Messages in the Single Shot Stack are transmitted at the initial receive offset for the specified RN Messages in the Continuous Stack are transmitted at the regular receive offset for the specified RN The messages are not sorted by the node rather the node traverses the stack in order To ensure that the messages go out at their proper times put them in the stack in time order EXC 1394PCI amp EXC 1394PCle User s Manual page 4 19 Chapter 4 Control Computer Operation Table 4 33 describes the fields of each CC Transmit Stack entry Table 4 33 CC Transmit Stack Entry Word O OO N B ND O O wo 10 15 Description Control Word see below Status Word see below 32 bit pointer to the beginning of message Time Tag of last actual transmission 48 bits Reserved Channel number of destination RN Size of message without trailer in quadlets the 1394 header is one quadlet the ASM header is four quadlets the message payload is a minimum of two quadlets no trailer Reserved Table 4 34 describes the fields of the CC Transmit Stack Control Word Table 4 34 CC Transmit Stack Control Word Bit Description 04 15 Reserved 03 Not end of stack this bit is set to indicate that this is a real message After the last message in the stack insert an extra entry with this bit c
154. tains the revision number of the firmware running on the node 16 bits are used for the major revision and 16 bits are used for the minor revision For example for firmware revision 2 1 2 is stored in the high 16 bits and 1 is stored in the low 16 bits 5 2 15 Pointer to Current Entry of Transmit Stack Address 00AC H Length 32 bits Read Only This register contains a pointer to the location in the Transmit Stack that is currently being transmitted page 5 8 Excalibur Systems Chapter 5 Remote Node Operation 5 2 16 Mode Select Register Address 00B0 H Length 32 bits Read Write Use this register to set the operational mode of the node Table 5 13 Mode Select Register Bit Value Description 00 31 0 Node was initialized but was not yet set into an operational mode Remote Node RN Mode Control Computer CC Mode Bus Monitor Mode A WwW N Asynchronous Mode 5 2 17 Start Register Address 00B4 H Length 32 bits Read Write Use this register to start and stop the operations of the node Table 5 14 Start Register Bit Description 01 31 Reserved 00 1 Start Operation 0 Stop Operation 5 2 18 Excalibur Node Status Register Address 00B8 H Length 32 bits Read Only This register indicates the current status of the node It also provides power on self test information EXC 1394PCI amp EXC 1394PCle User s Manual page 5 9 Chapter 5 Table 5 15 Excalibur Node Status R
155. the 2 MB Dual Port RAM is available for storing receive and transmit messages The buffers are variable in size A Transmit Message Stack enables you to schedule several messages to be transmitted in each STOF interval There are two stacks one used at transmit STOF offset and one at Datapump STOF offset The beginning of the Transmit Message Stack is defined by the Pointer to Beginning of Transmit Stack on page 5 12 The end of the stack is defined by the first message that has the Not end of stack bit cleared Messages in the Transmit Stack are transmitted according to the remote node s transmit offset An identical stack is used to schedule Datapump messages The beginning of the Datapump Message Stack is defined by the Pointer to Beginning of Datapump Stack on page 5 12 The end of the stack is defined by the first message that has the Not end of stack bit cleared Messages in the Datapump Stack are transmitted according to the remote node s Datapump offset Table 5 38 describes the fields in each transmission stack entry page 5 20 Excalibur Systems Chapter 5 Remote Node Operation Table 5 38 RN Transmit Datapump Stack Entry Word Description Control Word see below Status Word see below 32 bit pointer to data buffer 0 1 2 3 4 6 Time Tag of last actual transmission 48 bits 7 8 Reserved 9 Buffer size 1 0 11 Message Counter number of times this message has been sent 12 15 Reserved Table
156. ting interrupts see the Interrupt Mask Register on page 7 5 page 7 4 Excalibur Systems Chapter 7 Table 7 2 Bit 30 31 29 15 28 14 13 12 11 10 09 08 07 06 04 05 03 02 01 00 Bus Monitor Operation Interrupt Status Register Description Reserved Interrupt occurred on end of message receive for a specific message Check Linked List Status Words for which message Reserved End of buffer reached Buffer midpoint reached STOF vehicle time not incrementing STOF VPC error STOF timing error missed early or late STOF Bus reset Data trigger matched STOF offset error for more information see the Bus Monitor STOF Offsets Table status for each channel STOF receive complete Reserved End of message CC recognized as failed Network Bus Mode changed Message error 7 2 4 Interrupt Mask Register Address 0008 H Length 32 bits Read Write Use this register to set interrupts Each bit is a flag that enables or disables the generation of a specific interrupt When an interrupt is received check the Interrupt Status Register to see which condition or conditions caused the interrupt EXC 1394PCI amp EXC 1394PCle User s Manual page7 5 Chapter 7 Table 7 3 Bit 15 31 14 13 12 11 10 09 08 07 06 04 05 03 02 01 00 Interrupt Mask Register Description Reserved Interrupt on end of buffer reached Interrupt on buffer midpoint reached Interrupt when STOF ve
157. tus Register to see which condition or conditions caused the interrupt EXC 1394PCI amp EXC 1394PCle User s Manual page 4 5 Chapter 4 Control Computer Operation Table 4 3 Interrupt Mask Register Bit Description 15 31 Reserved 14 Interrupt on end of buffer reached 13 Interrupt on buffer midpoint reached 07 12 Reserved 06 Interrupt on end of STOF transmit 05 Interrupt on end of Transmit Stack message 04 Interrupt on start of Transmit Stack message 03 Interrupt on end of received message 02 Reserved 01 Reserved 00 Interrupt on message error 4 2 5 Reset Time Register Address 000C H Length 16 bits Read Write Use this register to reset the node s Time Tag and vehicle time Table 4 4 Reset Time Register Bit Description 02 15 Reserved 01 Reset vehicle time Resets the vehicle time to the value set in the Vehicle Time Preload Value Register See page 4 7 This is the timer used to fill in the Vehicle time field in the STOF messages 00 Reset Time Tag Resets the Time Tag to 0 All message Time Tags STOF offsets and STOF timing are based on this Time Tag value 4 2 6 Time Tag Registers Address 0010 H Length 48 bits Read Only These three registers represent the current value of the Time Tag All message Time Tags STOF offsets and STOF timing are based on this Time Tag value The Time Tag has a precision of 100 nanoseconds per bit The Time Tag should be read from address 10 then 12 then 1
158. universal PCI interface that is compatible with any 32 bit 33 66 MHz PCI slot It interfaces with the 1394 bus through a high density 62 pin DB type female connector The board comes with onboard active transformers Each node has 2 MB of memory for message data and control registers A 48 bit Time Tag is used to provide accurate time stamping of messages All STOF offsets are programmable as is the STOF timing frame rate itself Each node can operate in one of the following modes Control Computer CC mode Remote Node RN mode Bus Monitor mode Asynchronous mode CC mode In CC mode the node acts as the Root Node and Bus Manager and is responsible for sending out the STOF message at a precise predefined programmable interval It has two Transmit Stacks one for Single Shot and one for Continuous to allow the first frame to be configured differently than the other frames The node has programmable STOF offsets for each RN with two receive offsets for each RN one for the Single Shot Stack and one for the Continuous Stack Receive messages can be filtered by a combination of message number and transmitting RN message type Interrupts can be requested for all messages or for specific message types as well as for various error conditions RN mode In RN mode the node acts as a remote node on the Bus It transmits according to its predefined transmit STOF offset and has separate stacks for transmitting regular messages and Data
159. us Register Bit Description 31 Interrupt occurred on start of message transmit for a specific message queuing in progress can change the data pointer Check Stack Status Words for which message 30 Interrupt occurred on end of message transmit fora specific message queuing complete can change the data Check Stack Status Words for which message 29 Interrupt occurred on end of message receive for a specific message Check Buffer Or Receive Stack Status Words for which message 07 28 Reserved 06 STOF receive complete 05 End of message queuing transmit 04 Start of message transmit 03 End of message receive 02 CC recognized as failed 01 Network Bus Mode changed 00 Message error 6 2 4 Interrupt Mask Register Address 0008 H Length 32 bits Read Write Use this register to set interrupts Each bit is a flag that enables or disables the generation of a specific interrupt When an interrupt is received check the Interrupt Status Register to see which condition or conditions caused the interrupt Table 6 3 Interrupt Mask Register Bit Description 07 31 Reserved 06 Interrupt on end of STOF receive 05 Interrupt on end of Transmit Stack message 04 Interrupt on start of Transmit Stack message 03 Interrupt on end of received message 02 Interrupt when CC recognized as failed 01 Interrupt when Network Bus Mode changes 00 Interrupt on message error page 6 4 Excalibur Systems Chapter 6 Asynchro
160. utS sesse se ee ee ee ee ee ee ee ek Ke ee ee ee ee ee ee ee ke ee ee 8 8 8 4 3 PCI Express Bus Edge Connector PinoutS eise ees se ee ee ee ee ee ee ke ee ee ee ee ee ee ee 8 10 8 5 Synchronization with External Sources 8 11 8 6 Synchronizing Between EXC 1394PCl e Boards 5 8 12 8 7 Power Reauirements issie koe es eg De Ge 8 12 8 1 Board Layout A Channel 0 e242 21 Channel 1 N ae E E j oO Channel 2 N 43 22 1 Ki SELECTED ID FT swt 4 157 00mm 6 18 l ai Figure 8 1 EXC 1394PCIBoard Layout EXC 1394PCI amp EXC 1394PCle User s Manual page 8 1 Chapter 8 Mechanical and Electrical Specifications SELECTED ID pr o H 7 LD4 LD3 LD2 LD1 Channel 0 J1 43 55 1 Channel 1 LD14 L013 LD12 LD T MON 107 00mm 4 21 Channel 2 LD24 L023 LD22 LD2 ACTMONRN CC Figure 8 2 8 2 LED Indi 157 00mm 6 18 y EXC 1394PCle Board Layout cators The EXC 1394PCl e contains the following LEDs Table 8 1 LED LD1 LD2 LD3 LD4 LD11 LD12 LD13 LD14 LD21 LD22 LD23 LD24 page 8 2 LED Indicators Name ACT MON RN CC AC
161. various interrupt events or conditions Each bit indicates the occurrence of a specific event condition The bits in this register are lit when the event condition occurs regardless of whether the event condition is set to generate an interrupt For information on generating interrupts see the Interrupt Mask Register on page 4 5 page 4 4 Excalibur Systems Chapter 4 Table 4 2 Bit 31 30 29 15 28 14 13 07 12 06 05 04 03 02 01 00 Interrupt Status Register Description Interrupt occurred on end of message transmit for a specific message queuing complete can change the data Check Stack Status Words for which message Interrupt occurred on start of message transmit for a specific message queuing in progress can change the data pointer Check Stack Status Words for which message Interrupt occurred on end of message receive for a specific message Check Linked List Status Words for which message Reserved End of buffer reached Buffer midpoint reached Reserved STOF transmit complete End of message queuing transmit Start of message transmit End of message receive Reserved Reserved Message error 42 4 Interrupt Mask Register Address 0008 H Length 32 bits Read Write Control Computer Operation Use this register to set interrupts Each bit is a flag that enables or disables the generation of a specific interrupt When an interrupt is received check the Interrupt Sta
162. wer up node reset and when the node is started Table 7 9 Receive Message Error Counter Register Bit Description 00 31 Number of messages with errors received and stored by the node 7 2 11 Discarded Message Counter Register Address 00A0 H Length 32 bits Read Only This register contains a running count of all messages that were discarded by the node It is reset to 0 upon power up node reset and when the node is started Table 7 10 Discarded Message Counter Register Bit Description 00 31 Number of messages received and discarded by the node 7 2 12 Firmware Revision Register Address 00A8 H Length 32 bits Read Only This register contains the revision number of the firmware running on the node 16 bits are used for the major revision and 16 bits are used for the minor revision For example for firmware revision 2 1 2 is stored in the high 16 bits and 1 is stored in the low16 bits page 7 8 Excalibur Systems Chapter 7 Bus Monitor Operation 7 2 13 Mode Select Register Address 00B0 H Length 32 bits Read Write Use this register to select the operational mode of the node Table 7 11 Mode Select Register Bit Value Description 00 31 0 Node was initialized but was not yet set into an operational mode Remote Node RN Mode Control Computer CC Mode Bus Monitor Mode A OUO N Asynchronous Mode 7 2 14 Start Register Address 00B4 H Length 32 bits Read Write Use this
163. with Specifications are subject to change without notice November 2015 Rev A 8
164. write a 1 to the corresponding location Note The two bits of the DMA Interrupt Status Register work together with the four bits of the Global Interrupt Status Register When any of these six bits are set an interrupt is generated To locate the source of an interrupt both of these registers need to be read In order to reset the interrupt you must reset the appropriate bits of both the DMA Interrupt Status Register and the Global Interrupt Reset Register See Interrupt Status Register on page 2 16 2 4 8 Base Address for DMAO and DMA1 Transfers Address 0040 H Length 32 bits Read Write This register contains the start address of the current DMA transfer read or write transfer The base must be written to this register by the user Node Memory Space Map The node memory space map resides in the first memory block Each node is allocated a space of 2 MB See Figure 2 4 for the memory space mapping 600000 5FFFFF 400080 40007F 400000 3FFFFF 200080 20007F 200000 1FFFFF 000080 00007F 000000 DPR Node 2 Hardware Registers Node 2 DPR Node 1 Hardware Registers Node1 DPR Node 0 Hardware Registers Node 0 Figure 2 4 Node Memory Space Map page 2 14 Excalibur Systems Chapter 2 PCI Architecture 2 6 Global Registers Map The board global registers reside in the second memory block Control Functions Low 0034 H Control Functions High 0030 H oun I eee ome 0018 H 0014 H 0010 H 000c
165. y Read Only Read Only Read Only Read Write Read Write Read Only Read Only Read Only Read Write Read Read Write Page Number 6 3 6 3 6 3 6 4 6 5 6 5 6 5 6 5 6 6 6 6 6 7 6 7 6 9 6 10 6 14 Excalibur Systems Chapter 6 Asynchronous Operation 6 2 Asynchronous Mode Register Definitions 6 2 1 Hardware Revision Register Address 0000 H Length 16 bits Read Only This register contains the revision number of the hardware logic 12 bits are used for the major revision and four bits are used for the minor revision For example for hardware revision 2 1 2 is stored in the high 12 bits and 1 is stored in the low four bits 6 2 2 Excalibur Node ID Register Address 0002 H Length 16 bits Read Only This register contains the identifier of the Excalibur Node This is set to 1394 H 6 2 3 Interrupt Status Register Address 0004 H Length 32 bits Read Write Write 1 to Clear This register indicates the occurrence various interrupt events or conditions Each bit indicates the occurrence of a specific event condition The bits in this register are lit when the event condition occurs regardless of whether the event condition is set to generate an interrupt For information on generating interrupts see the Interrupt Mask Register on page 6 5 EXC 1394PCI amp EXC 1394PCle User s Manual page 6 3 Chapter 6 Asynchronous Operation Table 6 2 Interrupt Stat

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