Hynix GMS90C320, GMS90L320 User`s Manual
Contents
1. top view P MQFP 44 0 oe Bh e N q anan a E E lt lt lt lt TON SG ATA K K K K KZ ZR S K S 2 99 SS SS a 2 Z P1 5 10 33 PO 4 AD4 P1 6 2 32 PO 5 AD5 P1 7 3 31 PO 6 AD6 RESET 4 30 PO 7 AD7 RxD P3 0 5 29 EA N C 6 28 N C TxD P3 1 7 27 ALE INTO P3 2 8 26 PSEN INT1 P3 3 9 25 P2 7 A15 TO P3 4 10 24 P2 6 A14 T1 P3 5 Tau sea cee isd esa E 0 P2 5 A13 rrr r r N A ON Na gt O A ON CI d lt lt Z z lt lt lt E x gt aa VO F IE le Tigas 4 OCT 2000 Ver 1 2 Buis gip Voc Vss XTAL1 Port O XTAL2 8 bit Digital I O Port 1 8 bit Digital I O RESET Port 2 8 bit Digital I O EA ALE Port 3 PSEN 8 bit Digital I O Logic Symbol OCT 2000 Ver 1 2 5 GMS90C320 Pin Definitions and functions lavpmix Pin Number Input Symbol Function p tcc 44 Pomo PWOFP Output P1 0 P1 7 2 9 1 8 40 44 1 0 Port1 1 3 is an 8 bit bidirectional I O port with internal pull ups Port 1 pins that have 1s written to them are pulled high by the internal pull up resistors and can be used as inputs As inputs port 1 pins that are externally pulled low will source current because of the pulls ups I in the DC characteristics Pins P1 0 and P1 1 also Port 1 also receives the low order address byte during program memory verification Port1 al2. SFR bit and byte addressable SFR not bit addressable This bit location is reserved OCT 2000 Ver 1 2 hix GMS90C320 Timer Counter 0 and 1 Timer Counter 0 and 1 can be used in four operating modes as listed in Table 4 Table 4 Timer Counter 0 and 1 Operating Modes TMOD Input Clock Mode Description GATE CT M Mo Internal EE 0 8 bit timer counter with a f f divide by 32 prescaler Xx X 0 0 se S ria s 1 16 bit timer counter x x 0 4 fosc fosc 12 24 2 8 bit timer counter with 8 bit x x i 0 fosc fosc autoreload 12 24 3 Timer counter 0 used as one 8 bit timer counter and one 8 fosc fosc ka X X 1 1 Lou wan bit timer 12 24 Timer 1 stops In the timer function C T 0 the register is incremented every machine cycle Therefore the count rate is fosc 12 In the counter function the register is incremented in response to a 1 to 0 transition at its corresponding external input pin P3 4 TO P3 5 T1 Since it takes two machine cycles to detect a falling edge the max count rate is fosc 24 External inputs INTO and INTI P3 2 P3 3 can be programmed to function as a gate to facilitate pulse width measurements Figure 2 illustrates the input clock logic gt fosc 12 Timer 0 1 Input Clock P3 4 TO max fosc 24 Control P3 2 INTO J gt P3 3 INT1 Figure2 Timer Counter 0 and 1 Input Cloc
3. top view P LCC 44 a O e QU on MON DAAA s lt lt Z TtaNTtIB Sao Es pa Re E RO SAS OO O 2ooooaoZo gt aaaa is PO 4 AD4 P1 6 P0 5 AD5 P1 7 P0 6 AD6 RESET P0 7 AD7 RxD P3 0 FA N C N C TxD P3 1 ALE INTO P3 2 PSEN INTT P3 3 Pe 7 A15 TO P3 4 P2 6 A14 duba P2 5 A13 O 0 O r a 00 L 0 o A N N N N N N EN qq ON AN O AD Or a 4 gt oY E 2 o lt lt rm Es lt lt 2 z lt lt lt E C C aa aa lr re Caner Y 2 OCT 2000 Ver 1 2 hix 40 PDIP Pin Configuration top view GMS90C320 T2 P1 0 T2EX P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 RESET RxD P3 0 TxD P3 1 INTO P3 2 INT1 P3 3 TO P3 4 T1 P3 5 WR P3 6 RD P3 7 XTAL2 XTAL1 Vss o on oo ON SE SR a E K SSE h O QI ELM M oO M a a O O ON P DIP 40 40 39 38 37 36 35 34 33 32 30 29 28 27 26 25 24 23 22 21 Vec Po 0 ADO PO 1 AD1 P0 2 AD2 P0 3 AD3 P0 4 AD4 PO 5 AD5 P0 6 AD6 PO 7 AD7 EA ALE PSEN P2 7 A15 P2 6 A14 P2 5 A13 P2 4 A12 P2 3 A11 P2 2 A10 P2 1 A9 P2 0 A8 OCT 2000 Ver 1 2 lavpmix GMS90C320 44 PLCC Pin Configuration
4. ee eee 10mA to 10 mA Absolute sum of all input currents during overload condition eee eee 1100 mA SS TTS TT TBD Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the oper ational sections of this specification is not implied Exposure to absolute maximum rating conditions for longer periods may affect device reliability During overload conditions Viv gt Vcc or Vin lt Vss the Voltage on Vcc pins with respect to ground Vss must not exceed the values defined by the absolute maximum ratings OCT 2000 Ver 1 2 21 GMS90C320 DC Characteristics DC Characteristics for GMS90C320 Vec 5V 10 15 Vss 0V Ti 0 C to 70 C lavpmix Limit Values Parameter Symbol Unit Test Conditions Min Max Input low voltage e m A except EA RESET Vit kai 0 2 Ve OH ki Input low voltage EA Vi 0 5 0 2Vec 0 3 V Input low voltage RESET Vito 0 5 0 2Vcc 0 1 V Input high voltage except XTAL1 EA RESET Vin 0 2Vcc 0 9 Vcc 0 5 V Input high voltage to XTAL1 Viri 0 7Vcc Vec 0 5 V Input high voltage to EA GE 9 Vio 0 6Vcc Vec 0 5 V Output low voltage 0 3 lo 100uA ports 1 2 3 VoL 0 45 V lo 1 6mA 1 0 lo 3 5mA Output low v
5. 3 5 to 24MHz Parameter Symbol Unit Min Max Min Max RD pulse width RLRH 180 GtercL 70 ns WR pulse width hL 180 6tcict 70 ns Address hold after ALE ti LAx2 56 2tcrcr 27 ns RD to valid data in taLov 118 5teLci 90 ns Data hold after RD tanox 0 0 ns Data float after RD tauDz 63 2tcrcL 20 ns ALE to valid data in tiipv 200 8tcrcL 133 ns Address to valid data in tavov 220 9tcrcr 155 ns ALE to WR or RD tuw 75 175 3tcici 50 3tcic 50 ns Address valid to WR or RD tavwe 67 4tcic 97 ns WR or RD high to ALE high twHLH 17 67 teLc 25 toro 25 ns Data valid to WR transition tavwx 5 s leie 37 ns Data setup before WR tavwa 170 Ttcrcr 122 ns Data hold after WR twHax 15 teLci 27 ns Address float after RD taLaz 0 0 ns Advance Information 24MHz External Clock Drive Table 11 Variable Oscillator Parameter Symbol Freq 3 5 to 24MHz Unit Min Max Oscillator period terel 41 7 285 7 ns High time tcHcx 12 terer teLex ns Low time toLox 12 tener teHcx ns Rise time tcLcH 12 ns Fall time tcHct 12 ns OCT 2000 Ver 1 2 31 GMS90C320 AC Characteristics for 40MHz version Vec 5V 10 159 Vss OV T 0 C to 70 C CL for port 0 ALE and PSEN outputs 100pF Ci for all other outputs 80pF External Program Memory Characteristics lavpmix 40 MHZ O
6. 3toreL 15 a ns PSEN to valid instruction in teuv 20 3tcrcL 40 ns Input instruction hold after PSEN tpxix 0 0 ns Input instruction float after PSEN lays 10 toucL 10 ns Address valid after PSEN texav 15 touci 5 S ns Address to valid instruction in taviv 45 Btcrci D5 ns Address float to PSEN tazeL 5 5 ns 1 Interfacing the GMS90C320 to devices with float times up to 20 ns is permissible This limited bus contention will not cause any damage to port 0 Drivers 34 OCT 2000 Ver 1 2 hix AC Characteristics for 50MHz External Data Memory Characteristics GMS90C320 at 50 MHz Clock Variable Clock 1 teLc 3 5 to 50MHz Parameter Symbol Unit Min Max Min Max RD pulse width lal Ru 90 I Btctc 30 ns WR pulse width twiwh 90 I BtoLc 30 E ns Address hold after ALE ti LAX2 25 2tcrcL 15 ns RD to valid data in taLov 60 5tcici 40 ns Data hold after RD tanox 0 0 ns Data float after RD taHoz 28 2torcL 12 ns ALE to valid data in tiipv 120 8tcrcL 40 ns Address to valid data in tavov 125 9teLc 55 ns ALE to WR or RD tuw 45 75 3terc 15 3tercL 15 ns Address valid to WR or RD tavwi 50 4tcici 30 ns WR or RD high to ALE high twHLH 5 35 torci 15 toco 15 ns Data valid to WR transition tovwx 5 2 terc1 15 ns Data setup before WR tavwa 100 TtcrcL 40
7. 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial port interrupt Timer 2 interrupt 0003 000B 0013 001By 00234 002By A low priority interrupt can itself be interrupted by a high priority interrupt but not by another low priority interrupt A high priority interrupt cannot be interrupted by any other interrupt source If two requests of different priority level are received simultaneously the request of higher priority is serviced If requests of the same priority are received simultaneously an internal polling sequence determines which request is serviced Thus within each priority level there is a second priority structure determined by the polling sequence as shown in Table 9 Table 9 Interrupt Priority Within Level Interrupt Source Priority IEO TFO IE TF1 RI TI TF2 EXF2 External interrupt O Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial port interrupt Timer 2 interrupt High y Low OCT 2000 Ver 1 2 19 GMS90C320 hymnix Power Saving Modes Two power down modes are available the Idle Mode and Power Down Mode The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode respectively If the Power Down mode and the Idle mode are set at the same time the Power Down mode takes precedence Table 10 gives a general overview of the power saving modes Table 10 Power Saving Modes Overview Mode En
8. 1 2 hix AC Characteristics for 16MHz External Data Memory Characteristics GMS90C320 16 MHz Oscillator Variable Oscillator 1 teLc 3 5 to 16MHz Parameter Symbol Unit Min Max Min Max RD pulse width taLaH 275 Btoci 100 a ns WR pulse width twiwa 275 BtoLci 100 ns Address hold after ALE ti LAX2 127 2tcrcL 40 ns RD to valid data in tatov 183 5teLc 130 ns Data hold after RD tanox 0 0 ns Data float after RD taHoz 75 2tcrcL 50 ns ALE to valid data in tiipv 350 8tcrcL 150 ns Address to valid data in tavov 398 9toLc 165 ns ALE to WR or RD tuw 138 238 3tercL 50 3tercL 50 ns Address valid to WR or RD tavwi 120 4tcic 130 ns WR or RD high to ALE high twHLH 28 97 torci 35 toto 35 ns Data valid to WR transition tavwx 13 tic 50 ns Data setup before WR tovwi 288 7terc 150 ns Data hold after WR twHax 23 tercL 40 ns Address float after RD taLaz 0 0 ns Advance Information 16MHz External Clock Drive Variable Oscillator Parameter Symbol Freq 3 5 to 16MHz Unit Min Max Oscillator period teLoL 62 5 285 7 ns High time tonox 17 torci teucx ns Low time teLcx 17 toLcL toucx ns Rise time tcicH 17 ns Fall time tonel a 17 ns OCT 2000 Ver 1 2 29 GMS90C320 AC Characteristics for 24MHz version Vec 5V Voc 5V 10 15 Vss OV Ta 0 C to 70 C C
9. 40 44PLCC GMS90C320 Q40 44MQFP 4 25 5 5 GMS90C320 50 40PDIP GMS90C320 PL50 ROM less 256 50 44PLCC GMS90C320 Q50 44MQFP GMS90L320 40PDIP 2 7 5 5 GMS90L320 PL ROM less 256 24 44PLCC GMS90L320 Q 44MQFP OCT 2000 Ver 1 2 lavpmix GMS90C320 GMS90C320 L320 CMOS SINGLE CHIP 8 BIT MICROCONTROLLER ROM less Version for 90C52 Operating Voltage V Device Name ROM RAM Fre En PEE 4 25 5 5 GMS90C320 ROM less 256 x 8bit 40 50 2 7 5 5 GMS90L320 ROM less 256 x 8bit 24 Features Fully compatible to standard MCS 51 microcontroller Versions for 40 50 MHz operating frequency Low voltage version for 24MHz operating frequency 256 bytes of on chip data RAM 64K external program memory space 64K external data memory space Four 8 bit ports Three 16 bit Timers Counters Timer 2 with up down counter feature USART Six interrupt sources two priority levels Power saving Idle and power down mode 2 7Volt low voltage version available P DIP 40 P LCC 44 P MQFP 44 package 1 0 1 0 1 0 ROM less 1 0 The GMS90C320 described in this document is compatible with the standard 80C32 can be used for all present standard 80C32 applications OCT 2000 Ver 1 2 1 GMS90C320 44 PLCC Pin Configuration lavpmix
10. V lo 1 6mA1 ports 1 2 3 oL 0 30 lo 1004A1 Output low voltage V _ 0 45 V lo 3 2mA1 port O ALE PSEN Out 0 30 lo 200uA1 Output high voltage V 2 0 _ V lou 20uA ports 1 2 3 gs 0 9Vcc loH 10uA Output high voltage lou 800UA2 port O in external bus mode ALE Vout 0 S V va 80 se PSEN Vcc OH OULL Logic 0 input current E E ports 1 2 3 lL 1 50 LA Vin 0 45V Logical 1 to 0 transition current f E Vin 2 0V ports 1 2 3 hi 25 250 LA N 2 0 input leakage current L YA 0 45 lt Vi lt Voc Pin capacitance fo 1MHz G i so PE T 25 C Power supply current Active mode 16 MHz3 loc 10 mA Voc 3 3V4 Idle mode 16MHz3 loc 5 25 mA Vec 3 3V5 Active mode 24MHz3 loc 16 Voc 3 3V4 Idle mode 24MHz3 lec z 8 25 Vec 3 3V5 Power Down Mode leg N 10 uA Voc 3 6V6 24 OCT 2000 Ver 1 2 lavpmix GMS90C320 AC Characteristics Explanation of the AC Symbols Each timing symbol has 5 characters The first character is always a stand for time The other characters depending on their positions stand for the name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for A Address T Time C Clock V Valid D Input Data W WR signal H Logic level HIGH X No longer a valid logic level l Instruction program memory contents Z Float L Logic level LOW or ALE P PSEN For example Q O
11. through RxD ETE TxD outputs the shift clock 8 bit are transmitted received LSB first 1 0 1 Timer 1 2 overflow rate 8 bit UART 10 bits are transmitted through TxD or received RxD 2 1 0 f f 9 bit UART OSC Osc 3 Na 11 bits are transmitted through TxD or received RxD 3 1 1 Timer 1 2 overflow rate 9 bit UART Like mode 2 except the variable baud rate Table 7 Formulas for Calculating Baud rates Baud Rate derived from Interface Mode Baud rate Oscillator 0 fosc 12 2 2SMOD x fosc 64 Timer 1 16 bit timer 1 3 a i A SMOD 1 overfl 8 bit timer with 8 bit autore AAA AE load 1 3 28MOD x fosc 32 x 12 x 256 TH1 Timer 2 1 3 fosc 32 x 65536 RC2H RC2L OCT 2000 Ver 1 2 17 GMS90C320 hymnix Interrupt System The GMS90C320 provides 6 interrupt sources with two priority levels Figure 3 gives a general overview of the interrupt sources and illustrates the request and control flags High Priority Low Priority Timer O Overflow TCON 5 IE 1 Timer 1 Overflow TCON 7 IE 3 Timer 2 Overflow T2CON 7 P1 1 Ea T2CON 3 SCON 0 USART 2 vi vi Figure 3 Interrupt Request Sources 18 OCT 2000 Ver 1 2 lavpmix Table 8 GMS90C320 Interrupt Sources and their Corresponding Interrupt Vectors Source Request Flags Vector Vector Address IEO TFO IE1 TF1 RI TI TF2 EXF2 External interrupt
12. 0 Ver 1 2 11 GMS90C320 lumix Table 2 Special Function Registers Functional Blocks Content Block Symbol Name Address after Reset CPU ACC Accumulator E041 005 B B Register FO 004 DPH Data Pointer High Byte 83H 00 DPL Data Pointer Low Byte 824 00 PSW Program Status Word Register DO 1 004 SP Stack Pointer 814 074 Interrupt System IE Interrupt Enable Register AB OX000000p IP Interrupt Priority Register B841 XX00000052 Ports PO Port 0 801 FFy P1 Port 1 9041 FFy P2 Port 2 A041 FFy P3 Port 3 BO FFy Serial Channels PCON Power Control Register 87H OXXX0000p2 SBUF Serial Channel Buffer Register 99 XX3 SCON Serial Channel 0 Control Register 9841 OO Timer 0 Timer 1 TCON Timer 0 1 Control Register 8841 004 THO Timer 0 High Byte 8Cy 00 TH1 Timer 1 High Byte 8Dy 00 TLO Timer 0 Low Byte 8A 00 TL1 Timer 1 Low Byte 8By 00 TMOD Timer Mode Register 894 00 Timer 2 T2CON Timer 2 Control Register C841 005 T2MOD Timer 2 Mode Register C94 XXXXXXX052 RC2H Timer 2 Reload Capture Register High Byte CB 00 RC2L Timer 2 Reload Capture Register Low Byte CA 00 TH2 Timer 2 High Byte CD 004 TL2 Timer 2 Low Byte CCu 004 Power Saving PCON Power Control Register 87H OXXX00002 Modes 1 Bit addressable Special Function Registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the va
13. 58 of the instructions are executed in 1 0pts Special Function Register PSW MSB LSB Bit No 7 6 5 4 3 2 1 0 Addr DOy CY AC FO RS1 RS2 OV F1 P PSW Bit Function CY Carry Flag AC Auxiliary Carry Flag for BCD operation FO General Purpose Flag RS1 RSO Register Bank select control bits 0 0 Bank 0 selected data address 004 074 0 1 Bank 1 selected data address 084 0F 1 0 Bank 2 selected data address 104 174 1 1 Bank 3 selected data address 184 1Fy OV Overflow Flag F1 General Purpose Flag P Parity Flag Set cleared by hardware each instruction cycle to indicate an odd even number of one bits in the accumulator i e even parity Reset value of PSW is 00x OCT 2000 Ver 1 2 9 GMS90C320 lumix Special Function Registers All registers except the program counter and the four general purpose register banks reside in the special function register area The 27 special function registers SFR include pointers and registers that provide an interface between the CPU and the other on chip peripherals There are also 128 directly addressable bits within the SFR area All SFRs are listed in Table 1 Table 2 and Table 3 In Table 1 they are organized in numeric order of their addresses In Table 2 they are organized in groups which refer to the functional blocks of the GMS90C320 Table 3 illustrates the contents of the SFRs Table 1 Special Fu
14. HYNIX SEMICONDUCTOR INC 8 BIT SINGLE CHIP MICROCONTROLLERS GMS90C320 User s Manual Ver 1 2 Nujnix Semiconductor REVISION HISTORY VERSION 1 2 Oct 2000 This book Correct the pin number of 44 MQFP package type on page 6 VERSION 1 1 Oct 1999 Before version Version 1 2 Published by MCU Application Team Copy right 02001 Hynix semiconductor All right reserved Additional information of this manual may be served by Hynix semiconductor offices in Korea or Distributors and Repre sentatives listed at address directory Hynix semiconductor reserves the right to make changes to any information here in at any time without notice The information diagrams and other data in this manual are correct and reliable however Hynix semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual GMS90C320 Device Naming Structure H G MS90X320 XXXX Hynix semiconductor MCU MCU Series Frequency Blank 24MHz 40 40MHz 50 50MHz Package Type Blank 40PDIP PL 44PLCC Q 44MQFP Enhanced ROM less version Operating Voltage C Normal voltage L Low voltage lavpmix OCT 2000 Ver 1 2 GMS90C320 GMS90C320 ordering information lavpmix Operatin ROM size RAM size Operating max Voltage Y Device name bytes bytes batent MHz Package Type GMS90C320 40 40PDIP GMS90C320 PL40 ROM less 256
15. cr 12 ns ALE to valid data in tLLov 150 8tcrcL S50 ns Address to valid data in tavov 150 9teLcL 75 ns ALE to WR or RD tuw 60 90 3terc 15 3tercL 15 ns Address valid to WR or RD tavwi 70 4tcici 30 ns WR or RD high to ALE high twHLH 10 40 teLc 15 torci 15 ns Data valid to WR transition tovwx 5 2 terci 20 ns Data setup before WR tovwh 125 TtcrcL 50 ns Data hold after WR twHox 5 teLci 20 ns Address float after RD taLaz 0 0 ns Advance Information 40MHz External Clock Drive Variable Oscillator Parameter Symbol Freq 3 5 to 40MHz Unit Min Max Oscillator period teLoL 25 285 7 ns High time tonox 10 torci teucx ns Low time teLcx 10 tect tcHcx ns Rise time teLcH 10 ns Fall time tcHcL a 10 ns OCT 2000 Ver 1 2 33 GMS90C320 lumix AC Characteristics for 50MHz version Voc 5V 10 1590 Vss OV Ti 0 C to 70 C CL for port 0 ALE and PSEN outputs 100pF Ci for all other outputs 80pF Variable Clock Vcc 5V 1 tere 3 5MHZ to 50 MHz External Program Memory Characteristics Variable Oscillator Parameter Symbol Ea La 1 tcic 3 5 to 50MHz Unit Min Max Min Max ALE pulse width tini 25 2tcrcL 15 ns Address setup to ALE tavii 5 terc_ 15 ns Address hold after ALE tLLAx 5 teLo 15 ns ALE low to valid instruction in tLuiv 40 4tcrcr 40 ns ALE to PSEN tu 5 teLc 15 ns PSEN pulse width turn 45
16. en while XTAL2 is left unconnected There are no require ments on the duty cycle of the external clock signal since the input to the internal clocking circuitry is divided down by a divide by two flip flop Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed OCT 2000 Ver 1 2 hix GMS90C320 Symbol Pin Number P MQFP P DIP 40 44 P LCC 44 Input Output Function P2 0 P2 7 24 31 21 28 18 25 1 0 Port 2 Port 2 is an 8 bit bidirectional I O port with internal pull ups Port 2 pins that have 1s written to them are pulled high by the internal pull up resistors and can be used as inputs As inputs port 2 pins that are externally pulled low will source current because of the pulls ups li in the DC characteristics Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pull ups when emitting 1s During accesses to external data memory that use 8 bit addresses MOVX Ri port 2 emits the contents of the P2 special function register PSEN 32 29 26 The Program Store Enable The read strobe to external program memory when the device is executing code from the external program memory PSEN is acti vated twice each machine cycle except that two PSEN act
17. for port O ALE and PSEN outputs 100pF C for all other outputs 80pF Vec 3 3V Voc 3 3V 0 3V 0 6V Vss OV Ta 0 C to 70 C C for port O ALE and PSEN outputs 50pF C for all other outputs 50pF Variable clock Vcc 5V 1 tcicr 3 5 MHz to 24 MHz Vcc 3 3V 1 teic 1 MHz to 24 MHz External Program Memory Characteristics lavpmix Variable Oscillator Parameter Symbol ue eliator 1tcrer 3 5 to 24MHz Unit Min Max Min Max ALE pulse width tLHLL 43 2tcrcL 40 ns Address setup to ALE tavii 17 teLc 25 ns Address hold after ALE tLLax 17 teLc 25 ns ALE low to valid instruction in tLuiv 80 4tcrci 87 ns ALE to PSEN trt 22 torci 20 ns PSEN pulse width lal pu 95 3tercL 30 ns PSEN to valid instruction in truiv 60 3tcLc 65 ns Input instruction hold after PSEN texix 0 0 ns Input instruction float after PSEN tex 32 l terci 10 ns Address valid after PSEN texav 37 E tetcL 5 S ns Address to valid instruction in taviv 148 5tcicL 60 ns Address float to PSEN tazeL 10 10 ns 1 Interfacing the GMS90C320 to devices with float times up to 35 ns is permissible This limited bus contention will not cause any damage to port 0 Drivers 30 OCT 2000 Ver 1 2 hix AC Characteristics for 24MHz External Data Memory Characteristics GMS90C320 24 MHz Oscillator Variable Oscillator 1 teLc
18. ication in the GMS97C5x External pull up resistors are required during program verification 22 20 16 Circuit ground potential 44 40 38 Supply terminal for all operating modes 1 12 6 17 23 34 28 39 No connection OCT 2000 Ver 1 2 GMS90C320 lumix Function Description The GMS90 series is fully compatible to the standard 8051 microcontroller family It is compatible with the standard 80C32 While maintaining all architectural and operational characteristics of the standard 80C32 the GMS90C320 incorporates some enhancements in the Timer 2 unit Figure 1 shows a block diagram of the GMS90C320 XTAL1 RaM OSC amp Timing 256 x 8 XTAL2 RESET CPU Timer 0 Port 0 ALE lt Timer 1 PSEN Port 1 m Gai 8 bit Digital O EA Timer 2 sid ort mn Ponz 8 bit Digital I O Interrupt Unit Port 3 Serial Channel Figure 1 Block Diagram of the GMS90C320 8 OCT 2000 Ver 1 2 hynix GMS90C320 CPU The GMS90C320 is efficient both as a controller and as an arithmetic processor It has extensive facilities for binary and BCD arithmetic and excels in its bit handling capabilities Efficient use of program memory results from an instruction set con sisting of 44 one byte 41 two byte and 15 three byte instructions With a 12 MHz crystal
19. ivation are skipped during each access to external data memory PSEN is not activated during fetches from internal program memory RESET RESET A high level on this pin for two machine cycles while the oscillator is running resets the device An internal diffused resistor to Vss permits power on reset using only an external capacitor to Vcc ALE 33 30 27 The Address Latch Enable Output pulse for latching the low byte of the address during an access to external memory In normal operation ALE is emitted at a constant rate of 1 6 the oscillator frequency and can be used for external timing or clocking Note that one ALE pulse is skipped during each access to external data memory 35 31 29 External Access Enable EA must be external held low to enable the device to fetch code from external program memory locations 0000 to FFFFy If EA is held high the device executes from internal program memory unless the program counter contains an address greater than its internal memory size PO O PO 7 43 36 39 32 37 30 1 0 Port 0 Port 0 is an 8 bit open drain bidirectional I O port Port O pins that have 1s written to them float and can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program and data memory In this application it uses strong internal pull ups when emitting 1s Port 0 also outputs the code bytes during program verif
20. k Logic OCT 2000 Ver 1 2 15 GMS90C320 lumix Timer 2 Timer 2 is a 16 bit Timer Counter with an up down count feature It can operate either as timer or as an event counter which is selected by bit C T2 T2CON 1 It has three operating modes as shown in Table 5 Table 5 Timer Counter 2 Operating Modes T2CON Input Clock T2MO Tocon P11 Mode RxCLK CP ane BEEN EXEN T2EX Remarks Int External or _ nterna TxCLK RL2 P1 0 T2 16 bit Auto 0 0 1 0 0 X reload upon overflow reload 0 0 1 0 1 J reload trigger falling edge fosc fosc 0 0 1 1 x 0 Down counting a max aa 0 0 1 1 X 1 Up counting 16 bit 0 1 1 X 0 X 16 bit Timer Counter only Capture up counting fosc fosc 0 1 1 x 1 L capture o MAT TH1 TL2 gt RC2H RC2L Baud Rate 1 X 1 X 0 X no overflow interrupt request Generator TF2 fosc fosc 1 x 1 x 1 J extra external interrupt 12 max 4 Timer 2 off X X 0 X X X Timer 2 stops al iNote J A falling edge 16 OCT 2000 Ver 1 2 hix GMS90C320 Serial Interface USART The serial port is full duplex and can operate in four modes one synchronous mode three asynchronous modes as illustrated in Table 6 The possible baud rates can be calculated using the formulas given in Table 7 Table 6 USART Operating Modes SCON Mode Baudrate Description SMO SM1 0 0 0 fosc Serial data enters and exits
21. logic 1 and Vitmax for a logic 0 0 45V Figure 7 AC Testing Input Output Waveforms VLoaD 0 1 Vo 0 1 ee Timing Reference Points VLoaD 0 2Vcc 0 1 VLoAD 0 1 Vo 0 1 For timing purposes a port pin is no longer floating when a 100mV change from load voltage occurs and begins to float when a 100mV change from the loaded Vor Vo level occurs lot lou gt 20mA Figure 8 Float Waveforms 0 2 Vcc 0 1 0 45V tcHcL touch Figure 9 External Clock Cycle 38 OCT 2000 Ver 1 2 hix OSCILLATOR CIRCUIT CRYSTAL OSCILLATOR MODE C2 a XTAL2 P LCC 44 Pin 20 P DIP 40 Pin 18 M QFP 44 Pin 14 XTAL1 P LCC 44 Pin 21 P DIP 40 Pin 19 M QFP 44 Pin 15 C1 C2 30pF 10pF for Crystals For Ceramic Resonators contact resonator manufacturer Figure 10 Recommended Oscillator Circuits DRIVING FROM EXTERNAL SOURCE External Oscillator Signal XTAL2 P LCC 44 Pin 20 P DIP 40 Pin 18 M QFP 44 Pin 14 XTAL1 P LCC 44 Pin 21 P DIP 40 Pin 19 M QFP 44 Pin 15 GMS90C320 Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator Since each crystal and ceramic resonator have their own characteristics the user should consult the crystal manufacturer for appropriate values of external components OCT 2000 Ver 1 2 39 amssoc320 tix Plastic Package P LCC 44 Plastic Leaded Chi
22. lue is indeterminate and the location is reserved 12 OCT 2000 Ver 1 2 lavpmix Table 3 Contents of SFRs SFRs in Numeric Order Address 80H 814 82H 83H 874 88H 89 BAL 8By 8Cy 8D 904 984 994 AO ABL BO B84 CBL C94 Register PO SP DPL DPH PCON TCON TMOD TLO TL1 THO TH1 P1 SCON SBUF P2 T2CON T2MOD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMOD a GF1 GFO PDE IDLE TF1 TR1 TFO TRO 1E1 IT1 IEO ITO GATE C T M1 Mo GATE C T M1 Mo SMO SM1 SM2 REN TB8 RB8 TI RI EA l ET2 ES ETI EX1 ETO EXO E PT2 PS PT1 PX1 PTO PXO TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 l E DCEN OCT 2000 Ver 1 2 SFR bit and byte addressable SFR not bit addressable This bit location is reserved GMS90C320 13 GMS90C320 Table 3 Contents of SFRs SFRs in Numeric Order cont d Address CA 14 CB CCh CDy DO EO FO Register RC2L RC2H TL2 TH2 PSW ACC B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 lavpmix Bit 2 Bit 1 Bit 0 CY AC FO RS1 RSO OV F1 P
23. nction Registers in Numeric Order of their Addresses Address Register men Address Register S 804 PO FF AO P21 FFy 81 SP 074 Aly reserved XXy2 82 DPL 004 A2y reserved XXy2 83 DPH 00 A reserved XXy2 844 reserved XXy2 A4 reserved XX42 85 reserved XXu2 AB reserved XXy2 864 reserved XXy2 AG reserved XXy2 874 PCON 0XXX000052 A7 reserved XX2 884 TCON 004 AB IE OX000000p2 89 TMOD 004 A94 reserved XX2 BAL TLO 004 AA reserved XXu2 8B TL1 00 AB reserved XXy2 8Ch THO 004 ACH reserved XXu2 8D TH1 00 AD reserved XXy2 BEL reserved XXpu2 AE reserved XXy2 BEL reserved XX42 AFu reserved XXu2 901 P1 FFy BO P31 FFy 91 reserved 001 Bi reserved XXy2 924 reserved XXy2 B24 reserved XXy2 93 reserved XXy2 B3 reserved XX 94y reserved XXy2 B44 reserved XXy2 954 reserved XXy2 B54 reserved XX42 96 reserved XXy2 B6 reserved XXy2 97H reserved XX 2 B74 reserved XX 2 98H SCON 004 B84 IP XX00000052 994 SBUF XX2 B94 reserved XXy2 9AH reserved XXy2 BA reserved XXu2 IB reserved XXy2 BB reserved XXh2 9C reserved XXy2 BCy reserved XXy2 9D reserved XXu2 BD reserved XXy2 9E reserved XXu2 BE reserved XX 2 9Fy reserved XXu2 BF reserved XXy2 1 Bit addressable Special Function Register 2 X means that the value is indeterminate and the location is reserved 10 OCT 2000 Ver 1 2 lavpmix Table 1 Special Function Registers in numeric o
24. no 20 ns OCT 2000 Ver 1 2 27 GMS90C320 AC Characteristics for 16MHz version Vec 5V Voc 5V 10 15 Vss OV Ta 0 C to 70 C C for port O ALE and PSEN outputs 100pF C for all other outputs 80pF Vec 3 3V Voc 3 3V 0 3V 0 6V Vss OV Ta 0 C to 70 C C for port O ALE and PSEN outputs 50pF C for all other outputs 50pF Variable clock Vec 5V 1 tcicr 3 5 MHz to 16 MHz Vcc 3 3V 1 tc c 1 MHz to 16 MHz External Program Memory Characteristics himquix Variable Oscillator Parameter Symbol andenn 1tcrer 3 5 to 16MHz Unit Min Max Min Max ALE pulse width tLHLL 85 2tcrcL 40 ns Address setup to ALE tavii 23 toLc 40 ns Address hold after ALE tLLAX 43 teLc 40 ns ALE low to valid instruction in tLuiv 150 4tcrci 100 ns ALE to PSEN tp 38 tetcr 25 ns PSEN pulse width lal pu 153 I 3teLc 35 ns PSEN to valid instruction in touv 88 3tcic 100 ns Input instruction hold after PSEN texix 0 0 ns Input instruction float after PSEN texiz 43 terci 20 ns Address valid after PSEN texav 55 teLc 8 F ns Address to valid instruction in taviv 198 5tercL 115 ns Address float to PSEN hze 10 10 ns 1 Interfacing the GMS90C320 to devices with float times up to 35 ns is permissible This limited bus contention will not cause any damage to port 0 Drivers 28 OCT 2000 Ver
25. ns Data hold after WR twHax 5 teLci 15 ns Address float after RD taLaz 0 0 ns Advance Information 50MHz External Clock Drive Variable Oscillator Parameter Symbol Freq 3 5 to 50MHz Unit Min Max Oscillator period teLoL 20 285 7 ns High time tonox 10 torci teucx ns Low time teLcx 10 terer tcHcx ns Rise time teLcH 10 ns Fall time tcHcL a 10 ns OCT 2000 Ver 1 2 35 GMS90C320 lavpmix ALE PSEN PORTO PORT 2 lt tu gt tavu lt tv gt lt tier pe tpn lt touv gt A8 A15 Figure 4 External Program Memory Read Cycle 36 OCT 2000 Ver 1 2 A lt lt ALE ti pe twHLH PSEN a hrg gt N lt tiw RLRH gt tavil fe A0 A7 from Y V YO RI or DPL ANANA e tww 1 lt tavov gt PORT 2 P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH INSTR IN PORT 0 DATA IN L AO A7 from PCL Figure 5 External Data Memory Read Cycle ALE tur gt twHLH PSEN PORT 0 INSTR IN PORT 2 P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH Figure 6 External Data Memory Write Cycle OCT 2000 Ver 1 2 37 GMS90C320 lix Voc 0 5V 0 2Vcc 0 9 Test Points 0 2Vcc 0 1 AC Inputs during testing are driven at Vcc 0 5V for a logic 1 and 0 45V for a logic 0 Timing measurements are made a Vinma for a
26. oltage 0 3 lo 200uA port O ALE PSEN Vout 0 45 V lo 3 2mA1 1 0 lo 7 0mA Output high voltage V 2 4 _ V lon 80uA ports 1 2 3 aa 0 9Vec lou 10LA Output high voltage zi 2 port O in external bus mode Vout 0 a V as cae ALE PSEN TRE BS SVD Logic O input current E l m ports 1 2 3 lL 10 50 LA Vin 0 45V Logical 1 to 0 transition cur L rent ports 1 2 3 hr 65 650 uA Vin 2 0V Input leakage current je port 0 EA lu 1 uA 0 45 lt Vin lt Vec Pin capacitance Cio 10 pF fc 1MHz Ta 25 C Power supply current Active mode 12MHz3 loc 16 mA Vec 5V4 Idle mode 12MHz3 loc 7 5 mA Vec 5V5 Active mode 24 MHz3 loc y 26 mA Voc 5V4 Idle mode 24MHz3 lcc E 13 5 mA Vcc 5V5 Active mode 40 MHz loc 44 mA Voc 5V4 Idle mode 40 MHz _ Vcc 5V5 i lcc 18 mA Active mode 50 MHz3 Voc 5V4 lec a 55 mA Idle mode 50 MHz 22 5 A Voc 5V5 Power Down Mode ae m Voo 5 5V8 lpp E 50 LA 22 OCT 2000 Ver 1 2 hynix GMS90C320 1 Capacitive loading on ports O and 2 may cause spurious noise pulses to be superimposed on the Vo of ALE and port 3 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operation In the worst case capacitive loading gt 50pF at 3 3V gt 100pF at 5V the noise pulse on ALE line may exceed 0 8V In such cases it may be desirable to qualify ALE with a schmitt trigger or use an add
27. p Carrier 44PLCC UNIT INCH le 0 695 0 685 le 0 656 gt min 0 020 0 650 A A o D s ou elsa S glg SiS la oo oo U H 2 oo ojo 2 q D Y 0 012 B gt 2050880 iS 0 120 0 090 0 180 gt 0 165 no OCT 2000 Ver 1 2 hynix GMS90C320 Plastic Package P DIP 40 Plastic Dual in Line Package 40DIP AAA a m Hea bim Gm Une ENS Ga A ee O td O O UNIT INCH ETE A PS DS PE SS O GT PGS O E CE EST 2 075 E 2 045 a 0 600 BSC E L o s 0 550 o d Q 0 530 2 E ARAN Yo PA ee Gia 2 0 022 0 065 E 0 100BSC Es gt J lt skons 0 015 0045 RI 0 15 OCT 2000 Ver 1 2 41 cmssocszz0 DUS Plastic Package P MQFP 44 Plastic Metric Quad Flat Package P MQFP 44 13 45 ki 12 95 10 10 UNIT MM 9 90 re la s 58 Qe e Y E SEE DETAIL A q 2 i a eis 1 03 SC L 0 73 pa 1 60 co a _ 030850 180 DETAIL A 42 OCT 2000 Ver 1 2
28. rder of their addresses cont d GMS90C320 Address Register bi ei ai Address Register se r CO reserved XXy EU ACC 00 Cty reserved XXy Ely reserved XXy C2h reserved XXy2 E24 reserved XXy2 C3h reserved XXy2 ESh reserved XXy2 Cd reserved XXy2 Edu reserved XX42 C54 reserved XXy2 E5H reserved XXu2 CBL reserved XXy2 E64 reserved XXy2 C7u reserved XX 2 E74 reserved XX 2 C84 T2CON 004 E84 reserved XXy C9 T2MOD XXXXXXX082 E94 reserved XX2 CA RC2L 004 EA reserved XXy CB RC2H 004 EB reserved XXy2 CCy TL2 004 ECH reserved XXp2 CD TH2 00 ED reserved XXy2 CE reserved XXu2 EE reserved XXy2 CF reserved XX 2 EE reserved XXu2 DO PSW 004 FOu Bi 00 D14 reserved XXy FI reserved XXy D24 reserved XX42 F24 reserved XXy2 D3y reserved XXy2 F3 reserved XX 2 D4y reserved XXy2 F4 reserved XXy2 D5y reserved XX2 F5H reserved XX2 D6y reserved XXu2 F6 reserved XXy2 D7 reserved XX 2 F7a reserved XX 2 D84 reserved XXy2 F84 reserved XX42 D94 reserved XXy F94 reserved XXy DA reserved XXp2 FA reserved XXy2 DB reserved XX42 FB4 reserved XXu DCh reserved XXy2 FCH reserved XX42 DD reserved XXy2 FDy reserved XXy2 DE reserved XXy2 FEy reserved XXp2 DF reserved XX 2 FFy reserved XXu2 1 Bit addressable Special Function Register 2 X means that the value is indeterminate and the location is reserved OCT 200
29. ress latch with a schmitt trigger strobe input SD Capacitive loading on ports 0 and 2 may cause the Voy on ALE and PSEN to momentarily fall below the 0 9V specification when the address lines are stabilizing e loc max at other frequencies is given by active mode lec 1 0 x fosc 3 16 idle mode loc 0 37 x fosc 3 63 where fosc is the oscillator frequency in MHz lcc values are given in mA and measured at Vcc 5V loc active mode is measured with XTAL1 driven with teLcH tcHcL 5ns Vi Vss 0 5V Vin Vec S 0 5V XTAL2 N C EA Port 0 RESET Vcc all other pins are disconnected Icc would be slightly higher if a crystal oscillator is used appr 1mA loc Idle mode is measured with all output pins disconnected and with all peripherals disabled XTAL1 driven with teLcH tcHcL 5ns Vi Vss 0 5V Vin Vec gt 0 5V XTAL2 N C RESET EA Vss Port0 Vcc all other pins are disconnected K L lpp Power Down Mode is measured under following conditions EA Port 0 Vcc RESET Vss XTAL2 N C XTAL1 Vss all other pins are disconnected OCT 2000 Ver 1 2 23 GMS90C320 hymnix DC Characteristics for GMS90L320 Vec 3 3V 0 3V 0 6V Vss 0V Ta 0 C to 70 C Limit Values Parameter Symbol Mi ap Unit Test Conditions in ax Input low voltage Vi 0 5 0 8 V Input high voltage Vin 2 0 Voc 0 5 V Output low voltage V A 0 45
30. scillator Variable Oscillator Parameter Symbol Titcic 3 5 to 40MHz Unit Min Max Min Max ALE pulse width tii 35 2tcrci 15 ns Address setup to ALE tavii 10 tcrcL 15 ns Address hold after ALE tLLAx 10 torcL 15 ns ALE low to valid instruction in tLuiv 55 Atcic 45 ns ALE to PSEN heL 10 toLoi 15 ns PSEN pulse width turn 60 z 3toL0 15 ns PSEN to valid instruction in touv 25 3tcrcL 50 ns Input instruction hold after PSEN tpxix 0 0 ns Input instruction float after PSEN lays 15 toucL 10 ns Address valid after PSEN texav 20 touci 5 ns Address to valid instruction in taviv 65 BtcLci 60 ns Address float to PSEN tazeL 5 5 ns 1 Interfacing the GMS90C320 to devices with float times up to 20 ns is permissible This limited bus contention will not cause any damage to port 0 Drivers 32 OCT 2000 Ver 1 2 hix GMS90C320 AC Characteristics for 40MHz External Data Memory Characteristics Variable Clock Parameter Symbol ai ob 1ceL 3 5 to 40MHz Unit Min Max Min Max RD pulse width RLRH 120 GtercL 30 ns WR pulse width twiwa 120 Btcici 30 ns Address hold after ALE tiLax2 10 teLc 15 ns RD to valid data in taLov 75 I BtoLc 50 ns Data hold after RD tanox 0 0 ns Data float after RD tauDz 38 2tcr
31. so serves alternate functions of Timer 2 2 1 40 P1 0 T2 Timer counter 2 external count input 3 2 41 P1 1 T2EX Timer counter 2 trigger input P3 0 P3 7 11 13 10 17 5 7 1 0 Port 3 19 13 is an 8 bit bidirectional I O port with internal pull ups Port 3 pins that have 1s written to them are pulled high by the internal pull up resistors and in that state they can be used as inputs As inputs port 3 pins being externally pulled low will source current li in the DC characteristics because of internal pulls up resistors Port 3 also serves the special features of the 80C51 family as listed below 11 10 5 P3 0 RxD receiver data input asynchronous or data input output synchronous of the serial interface 0 13 11 7 P3 1 TxD transmitter data output asynchronous or clock output synchronous of the serial interface 0 14 12 8 P3 2 INTO interrupt O input timer O gate control 15 13 9 P3 3 INT1 interrupt 1 input timer 1 gate control 16 14 10 P3 4 TO counter O input 17 15 11 P3 5 T1 counter 1 input 18 16 12 P3 6 WR the write control signal latches the data byte from port O into the external data memory 19 17 13 P3 7 RD the read control signal enables the external data memory to port O XTAL2 20 18 14 O XTAL2 Output of the inverting oscillator amplifier XTAL1 21 19 15 l XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits To drive the device from an external clock source XTAL1 should be driv
32. ssible This limited bus contention will not cause any damage to port O Drivers 26 OCT 2000 Ver 1 2 hix AC Characteristics for 12MHz version External Data Memory Characteristics GMS90C320 A Variable Oscillator Parameter Symbol TEM Os tor 1 tcrer 3 5 to 12MHz Unit Min Max Min Max RD pulse width RLRH 400 BtcroL 100 ns WR pulse width twiwh 400 l GtercL 100 3 ns Address hold after ALE tLLAx2 127 2tcrcL 40 ns RD to valid data in taLov 252 I 5teLc 165 ns Data hold after RD tanox 0 0 ns Data float after RD tanoz 97 2toLc1 70 ns ALE to valid data in tiipv 517 8tcrcL 150 ns Address to valid data in tavov 585 9tcrcr 165 ns ALE to WR or RD tuw 200 300 3teLc 50 3tercL 50 ns Address valid to WR or RD tavwi 203 4tcic 130 ns WR or RD high to ALE high twHLH 43 123 toLc 40 toto 40 ns Data valid to WR transition tavwx 33 2 teLc 50 ns Data setup before WR tavwH 433 7tec 150 ns Data hold after WR twHax 33 toLc 50 ns Address float after RD taLaz 0 0 ns Advance Information 12MHz External Clock Drive Variable Oscillator Parameter Symbol Freq 3 5 to 12MHz Unit Min Max Oscillator period Vcc 5V telel 83 3 285 7 Oscillator period Vcc 3 3V terel 83 3 1 ns High time toucx 20 terer tcLox ns Low time tcLox 20 terer tcHcx ns Rise time tcLcH 20 ns Fall time to
33. tering Instruction Leaving by Remarks Example Idle mode ORL PCON 01H enabled interrupt CPU is gated off Hardware Reset CPU status registers maintain their data Peripherals are active Power Down ORL PCON 02H Hardware Reset Oscillator is stopped contents of Mode on chip RAM and SFR s are main tained leaving Power Down Mode means redefinition of SFR con tents In the Power Down mode of operation Vcc can be reduced to minimize power consumption It must be ensured however that Vcc is not reduced before the Power Down mode is invoked and that Vcc is restored to its normal operating level before the Power Down mode is terminated The reset signal that terminates the Power Down Mode also restarts the oscillator The reset should not be activated before Vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize similar to power on reset 20 OCT 2000 Ver 1 2 lumix GMS90C320 Absolute Maximum Ratings Ambient temperature under bias TA sss 40 to 85 C Storage temperature Tera ecoa seat ee ke at ko kibo a ae odepa t ke dia kone ta opa ee ok en ken ESA 65 to 150 C Voltage on Vcc pins with respect to ground VSS sese 0 5 V to 6 5 V Voltage on any pin with respect to ground Vo5 ccessecsssessecessceeseceseececeeseeceecesaesessecsueecsueseseeeeeesaeseeecnas 0 5 to Vcc 0 5 V Input current on any pin during Overload condition
34. utput Data tavu Time from Address Valid to ALE Low R RD signal tip Time from ALE Low to PSEN Low OCT 2000 Ver 1 2 25 GMS90C320 AC Characteristics for 12MHz version Vec 5V Voc 5V 10 15 Vss OV Ta 0 C to 70 C C for port O ALE and PSEN outputs 100pF C for all other outputs 80pF Vec 3 3V Voc 3 3V 0 3V 0 6V Vss OV Ta 0 C to 70 C C for port O ALE and PSEN outputs 50pF C for all other outputs 50pF Variable clock Vcc 5V 1 tcicr 3 5 MHz to 12 MHz Vcc 3 3V 1 toLcL 1 MHz to 12 MHz External Program Memory Characteristics himquix Variable Oscillator Parameter Symbol 1A Me Ce atr 1 tcier 3 5 to 12MHz Unit Min Max Min Max ALE pulse width huu 127 2tcrcL 40 ns Address setup to ALE taviL 43 tenc 40 ns Address hold after ALE ti LAX 43 tcrcL 40 ns ALE low to valid instruction in tLuiv 233 4tcrci 100 ns ALE to PSEN tiver 58 torci 25 ns PSEN pulse width lal pu 215 3tercL 35 ns PSEN to valid instruction in teuiv 150 3tcrcL 100 ns Input instruction hold after PSEN texix 0 0 5 ns Input instruction float after PSEN texiz 1 3 63 toici 20 ns Address valid after PSEN texav 75 teLc 8 ns Address to valid instruction in taviv 302 5tcrci 115 ns Address float to PSEN tazeL 10 10 ns 1 Interfacing the GMS90C320 to devices with float times up to 75 ns is permi
Download Pdf Manuals
Related Search