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MN102L610B/F61G LSI User`s Manual

1. No 8 Up to 16k bytes 8bit same as those in the above 8 bit bus width of No 1 Use D07 to D00 as general purpose ports A13 to A00 D15 to D08 P3DIR 1 0 0 0 0 0 0 P3MD Use A23 to A14 as general purpose ports 16bit PODIR to P2DIR P4DIR and POMD to P2MD P4MD are Use A23 to A14 as general purpose ports D15 to D00 same as those in the above 16 bit bus width of No 1 P3DIR and P3MD are same as those in the above 8 bit pus wiatn PODIR to P2DIR P4DIR and POMD to P2MD P4MD are No 9 Up to 32k bytes 8bit same as those in the above 8 bit bus width of No 1 Use D07 to D00 as general purpose ports A14 to A00 D15 to D08 P3DIR P3MD o 1 Use A23 to 15 as general purpose ports PODIR to P2DIR P4DIR and POMD to P2MD are 16bit same as those in the above 16 bit bus width of No 1 Use A23 to A15 as general purpose ports D15 to D00 P3DIR and P3MD are same as those in the above 8 bit bus width PODIR to P2DIR P4DIR and POMD to P2MD P4MD are No 10 Up to 64k bytes 8bit same as those in the above 8 bit bus width of No
2. P Fla Instruction Mnemonic Operation K CINE NE m Cycle Machine Code MOV MOV Dm An DmAn 2 2 F2 30 Dm lt lt 2 An MOV An Dm An gt Dm 2 2 F2 F0 An lt lt 2 Dm MOV Dn Dm Dn gt Dm 1 1 80 Dn lt lt 2 Dm 1 MOV An Am An gt Am 2 2 F2 70 An lt lt 2 Am MOV PSW Dn PSW Dn 0 2 2 F3 F0 Dn MOV Dn PSW Dn PSW 2 F3 D0 Dn lt lt 2 MOV MDR Dn MDR Dn 0 2 2 F3 E0 Dn MOV Dn MDR Dn MDR 2 2 F3 C0 Dn lt lt 2 An Dm mem16 An gt Dm S 1 1 20 An lt lt 2 Dm d8 An Dm mem16 An d8 gt Dm S 2 1 60 An lt lt 2 Dm d8 d16 An Dm mem16 An d16 gt Dm S 4 2 F7 C0 An lt lt 2 Dm d16 l d16 h d24 An Dm mem16 An d24 gt Dm S 5 3 F4 80 An lt lt 2 Dm d24 d24 m d24 h MOV Di An Dm mem16 An Di gt Dm S 2 2 F1 40 Di lt lt 4 An lt lt 2 Dm MOV abs16 Dn mem16 abs16 Dn S 3 1 C8 Dn abs16 l abs16 h MOV epus Dn 16 524 5 5 3 F4 C0 Dn abs24 l abs24 m abs24 h An mem24 An gt Am 2 2 70 An lt lt 2 Am 00 2 8 Am mem24 An d8 gt Am 2 2 70 An lt lt 2 Am d8 MOV d16 An Am mem24 An d16 gt Am 4 3
3. Read 16 bit Write 8 bit Write Low Side Figure 2 2 4 1 Wait Access Timing with 16 bit Bus Width Chapter 2 Bus Interface B ROM RAM Access Timing with 16 bit Bus Width SYSCLK 23 00 F EE D07 00 T NE Li L 1 E x dm WAIT 16 bit Read 16 bit Write Figure 2 2 5 Handshake Access Timing with 16 bit Bus Width B ROM RAM Access Timing with 8 bit Bus Width SYSCLK A23 00 A00 0 A00 1 D15 08 CS 1 WEH r1 16 bit Read 8 bit Write Figure 2 2 6 No Wait Access Timing with 8 bit Bus Width External Memory Connection Example 45 Chapter 2 Bus Interface B ROM RAM Access Timing with 8 bit B
4. TMnIB Input TMnIA Input TMnCA Register value TMnCB 5A87 Example Register value 0033 Example Figure 4 1 7 One phase Capture Input Timing Timer6 and Timer 7 TMnBC Value Time TMnIB i TMnIA 0033 Example TMnCB 5A87 Example Figure 4 1 8 Two phase Capture Input Timing Timer 6 and Timer 7 TMnBC Value TMnIA ETET 2 Input Figure 4 1 9 Two phase Encoder 4x Timing IV 70 Timers Chapter 4 Timers Counters TMnBC Value TMnIA we dem ANN Input Figure 4 1 10 Two phase Encoder 1x Timing Timer 6 and Timer 7 TMnBC Value TMnIB Input TMnIA Input Figure 4 1 11 External Count Direction Control Timing Timer 6 and Timer 7 TMnBC Value TMnCA TMnIA TMnIB Input TMnIG Input Figure 4 1 12 External Count Reset Control Two phase Encoder Timing Timer 6 and Timer 7 Timers 71 Chapter 4 Timers Counters Timer 1 to timer 5 can cascade For example cascading
5. No I Up to 16 bytes 8 bit PODIR OMD Use D07 to D00 as general purpose ports A03 to A00 D15 to D08 PIDIR 0 IMD P2DIR 0 2MD Use A23 to A04 as general purpose ports P3DIR 3MD PADIR T T9 4MD ofofofofofofo fo 16 bit PODIR 0 OMD Use A23 to A04 as general purpose ports D15 to DOO PIDIR to P4DIR and PIMD to P4MD are same as those in the above 8 bit bus width of No 1 No 2 Up to 256 bytes 8 bit PODIR OMD Use D07 to D00 as general purpose ports A07 to A00 15 to D08 PIDIR 0 IMD Use A23 to A08 as general purpose ports P2DIR 0 2MD P3DIR to and PIMD to are same as those in the above 8 bit bus width of No 1 16 bit PODIR 19 OMD Use A23 to 08 as general purpose ports D15 to DOO PIDIR to P4DIR and PIMD to P4MD are same as those in the above 8 bit bus width PODIR to P2DIR P4DIR and POMD to P2MD
6. 15 14 13 12 11 7 16 5 2 CPUM w osclstoplHattloscilosco RST Ing1 Ingo ID 00 00 RW R R R R R R R R R CPU Mode Control Tr k TT x 1 Register 16 bit access register 15 Watchdog Timer Enable 0 Enable 1 Disable and clear Setting WDRST to 0 after set 14 13 Watchdog Timer Count 00 219 clears Me watchdog timer counting value and starts 01 24 10 28 counting The watchaog met consists of a 17 bit binary 11 Reserved counter counting on the oscilla tion clock Therefore clear the 4 System Clock Monitor 0 High speed watchdog timer counting value 1 Low speed within 219 65 536 machine cycles 3 CPU Operating Control 0000 NORMAL mode Changing the set value reduces STOP tranfer request 0001 IDLE mode the wait time for oscillation stabi 0011 SLOW mode lization when returning from 2 CPU Operating Control 0100 HALTO mode STOP mode HALT tranfer request 0111 HALT1 mode walt np oscillation d 1000 mode Adi 1 0 Oscillator Control 1011 STOP1 mode The following describes programming rules and precautions in the STOP HALT mode
7. TM7CB 0001 TM7BC 0000 0001 0002 0003 _ 0000 0001 0002 0003 0000 SYSCLK 1 Y Y Y 1 Y Y TM7EN ON TM7IOB Input ij 5 TM7IOA Output Figure 4 3 9 One shot Pulse Output Timing Chapter 4 Timers Counters 16 bit Timer Setup Examples IV 103 Chapter 4 Timers Counters Use the MOV instruction to set the data and always use 16 bit write operations Stop TM7BC counting and initial ize clear TM7BC and RS F F 104 16 bit Timer Setup Examples 4 3 8 External Count Direction Control Using 16 bit Timer The external count direction control setup procedures for timer 6 and timer 7 are same In this example timer 7 counts SYSCLK and controls the counting direction using An interrupt occurs when TM7BC reaches the set value m Interrupt Enable Setup 1 Enable interrupts At the same time clear all prior interrupt requests Set G7LV 2 0 bits of the G7ICR to the interrupt level of 6 to 0 TM7BIR and TM7BIE to 0 and 1 respectively For example write x 4400 to the G7ICR register Thereafter an interrupt occurs when the timer 7 capture B oc curs Timer 7 Setup 2 Set the operating mode to the timer 7 mode register TM7MD Verify that counting is stopped and an interrupt is disabled The count direction is up when pin is 1 while the count direct
8. 7 to 0 0 Address Data Output Bus Controller POIN7 to 0 P07 to 00 007 00 ADO7 to 00 Data Input Bus Controller Chapter 8 Ports Table 8 1 1 Port Functions 2 of 8 Port Pin Function Shared Pin P17 to P10 Port 1 is used as the port 1 general purpose port data address data separated D15 to 008 input output or address data address data shared input output At reset this port AD15 to ADO8 operates as a general purpose port input during other modes except processor mode as D15 to 008 AD15 to ADO8 pins during processor mode The mode for port 1 either port data or address data mode is selected in 8 bit unit During processor mode without 8 bit bus width setting for all spaces P1MD is invalid During memory expansion mode set P1MD and P1DIR to 1 and 0 respectively DHP Address Data Output Control Bus Controller P1DIRO P1OUT7 to 0 Address Data Bus Controller P1IN7 to 0 P17 to 10 AD15 to 08 Data Input Bus Controller P27 to P20 Port 2 is used as the port 2 general purpose port or address output At reset this A07 to 00 port operates as a general purpose port input during other modes except processor mode and as A07 to A00 pins during processor mode During processor mode P2MD
9. S S 22025 lt 9 8 9 2 a ANN GQ O Fj a zle g 86809 5 ag SERRE SS gt a alc 8 wo Q N aw a Figure 2 1 5 Processor Mode Address Data Shared Pin Configuration OSCO 24 25 lt l PA2 RQ2 PA3 IRQ3 PA4 IRQ4 RST P00 D00 gt P01 DO1 P02 D02 t m P03 D03 P04 D04 P05 D05 lt P06 D06 gt P07 D07 lt Vss gt D08 lt D09 lt 010 lt 011 012 013 gt 014 015 76 77 78 79 80 81 82 83 84 85 86 8 8i 89 90 91 92 93 94 95 96 97 98 99 9555898 e x gaa SEE 858 f lt D mq lt raa 600900 666 RER GOOG a z 252259 gt lt lt lt lt gt FFF FF FF F F gt F F F oY BEORARARER ent nat ORRE 485588 858838 88 5 MN102LF61G L610B TOP VIEW s 100 pin LQFP ND 100 26 5 6 7 8 9 25 2 82 TM1IO P81 lt TM010 P80 4 A23 WDOUT AN7 P47 lt gt gt A22 STOP AN6 P46 A21 gt A20 Vss 19 gt A18 A17 F 16 A15 H 14 A13 A12 4
10. 15 14 13 12 11 10 9 8 7 6 5 4 2 1 ANCTR AN AN AN AN AN 2 2 NCH2 NCH1 INCHO 1CH2 1CH1 4CHO TM1 CK1 MD1 MDO x 00FDAO R R W RW RAW RAW RW R RAV RAW RAW RW A D Converter o O1 o OF 0 1 Control Register 14 12 Channel Selection for Multiple Channel Conversion 10 8 Channel Selection for 3 2 1 0 Single Channel Conversion Conversion Start Execution Flag Conversion Start at Timer 1 underflow Clock Source Selection Operating Mode Selection IX 212 Data Appendix 8 16 bit access register 000 Convert ANO 001 Convert from ANO to AN1 010 Convert from ANO to AN2 011 Convert from ANO to AN3 100 Convert from ANO to AN4 101 Convert from ANO to AN5 110 Convert from ANO to AN6 111 Convert from ANO to AN7 000 Convert ANO 001 Convert AN1 010 Convert AN2 011 Convert AN3 100 Convert AN4 101 Convert AN5 110 Convert AN6 111 Convert AN7 0 Reserved 1 Conversion start Conversion in progress 0 Disable 1 Enable 00 SYSCLK At 1 0 MHz to 20 MHz oscillation 01 SYSCLK 2 b 10 and b 11 are available At 5 10 SYSCLK 4 MHz to 10 MHz oscillation 6 01 11 SYSCLK 8 b 10
11. II 36 ROM Burst Mode Access Timing II 37 Access Timing Memory Connection Example during ROM Burst Mode II 38 Memory Connection Example with 16 bit Bus Width Address Data Separated Mode II 42 Memory Connection Example with 8 bit Bus Width Address Data Separated Mode II 43 No Wait Access Timing with 16 bit Bus Width 2 22 2 2 4 2 1 II 44 1 Wait Access Timing with 16 bit Bus Width 2 2 22 2 II 44 Handshake Access Timing with 16 bit Bus Width 2 2 2 2 II 45 No Wait Access Timing with 8 bit Bus Width a aaa II 45 1 Wait Access Timing with 8 bit Bus Width esee II 46 Handshake Access Timing with 8 bit Bus Width sess II 46 Access Timing during Bus Request Address Data Separated Mode II 47 Memory Connection Example with 16 bit Bus Width Address Data Shared Mode 50 Memory Connection Example with 8 bit Bus Width Address Data Shared II 51 Fixed Wait Access Timing with 16 bit Bus Width 2 2 2 2 II 52 Handshake Access Timing with 16 bit Bus Width 2 2 2 II 52 Figure 2 2 14 Figure 2 2 15 Figure 2 2 16 Fixed Wait Access Ti
12. TMO BC7 BC6 BC5 BC4 BC3 BC2 BC1 BCO R R R R R R R R 0 0 0 0 0 0 0 0 01 o1 7 0 Timer 0 Count Value 7 6 5 4 3 2 1 0 TM1 TM1 TM1 TM1 TM1 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BCO R R R R R R R R 0 0 0 0 0 0 0 0 0 7 0 Timer 1 Count Value 7 6 5 4 3 2 1 0 TM2 2 2 TM2 TM2 2 TM2 TM2 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BCO R R R R R R R R 0 0 0 0 0 0 0 0 01 7 0 Timer 2 Count Value IX 216 Data Appendix TMOBC x 00FEOO Timer 0 Binary Counter 8 16 bit access register TMOBC is a read only register TM1BC x 00FEO1 Timer 1 Binary Counter 8 bit access register 16 bit access is possible from even address TM1BC is a read only register TM2BC x 00FEO02 Timer 2 Binary Counter 8 16 bit access register TM2BC is a read only register 7 6 5 4 3 2 1 0 TM3 TM3 TM3 5 4 BC2 BCO R R R R R R R R 0 0 0 0 0 0 0 0 70 Timer 3 Count Value 7 6 5 4 3 2 1 0 TM4 TM4 TM4 TM4 TM4 BC7 BC6
13. V 115 Chapter 6 Table 6 1 1 Table 6 1 2 Chapter 7 Table 7 1 1 Table 7 1 2 Chapter 8 Table 8 1 1 Table 8 1 1 Table 8 1 1 Table 8 1 1 Table 8 1 1 Table 8 1 1 Table 8 1 1 Table 8 1 1 Table 8 1 2 Table 8 3 1 Chapter 9 Table 9 6 1 Analog Interface A D Converter Functions Lus ua an a a usss su 1 125 List of A D Conversion Control Registers eese VI 129 ATC Functions ipe ea p beidet VII 136 List ATC Control Registers VII 138 Ports Port Functions 8 nn speso nenne Rael ened VIII 142 Port Functions 2 of 8 csse VIII 143 Poit Functions 0f 8 aan mene eei VIII 144 Port Functions 4 0 8 sa u enne VIII 145 Port Functions SOf 8 t Ree sane Ani her epe VIII 146 Port Functions 6 8 VIII 147 Port Functions 7 0f 8 csi aita eit VIII 148 Port Functions 8 of 8 VIII 149 List of Port Control Registers essere VIII 150 Pull up Control Register VIII 159 Appendix Maximum minimum rating of the Oscillator Frequency IX 270 Contents Chapter 1 Overview Chapter 1 Overview l 2 Overview 1 1 Overview 1 1 1 Introduction The MN102 series linear addressing version designs the new architecture for C language programming based on a detailed analysis for embedded applications This
14. 5600 5 0 500 500 8500 SCO SCO SCO SCO SCO SCO SCO SCO SCO SCO 225 PTL OD 2 LN PTY2 PTY1 PTYO SB POD 51 SO 1 1 0 0 0 0 0 1 1 1 1 1 0 0 1 8 Set the first data to be transferred to the serial 0 transmit receive register SCOTRB When the data to be transferred is set to the SCOTRB register the transmission starts synchronizing with timer 2 Execute the interrupt service routine and transfer the next data when an interrupt occurs Tmer2underlowte 4 A AAA RE AA AAA ata sBoo STjbO bi b2 bS b4 bS b6 b7 PT SP SP ST bO b1 b2 Interrupt Request Interrupt Service Routine Figure 5 2 2 Bit Transmission Timing in Asynchronous Mode V 118 Serial Interface Setup Examples Chapter 5 Serial Interface Serial Interface Setup Examples V 119 Chapter 5 Serial Interface 5 2 2 Serial Reception in Synchronous Mode Using Timer 2 This section describes the example of serial interface 0 reception in synchronous mode with the following settings Bit Order MSB 8 bit data transfer Even parity The next data is read when a reception end interrupt occurs m Pin Setup Set P70 pin and P71 pin to serial clock input and data input of serial interface 0 respectively See Chapter 8 Ports m Seria
15. PO PO our7 oure ours our4 oura oure ourt x OOFFCO RAW RAW RAW RAW RW RW Rw RW Port 0 Output Er r 03 Reqist fom on on egister 8 16 bit access register 70 Port 0 Output 7 6 5 4 3 2 1 0 P1 OUT Pi N our7 oure ours our4 oura oure ourt x OOFFC1 RAW RAW RAW RAW RW RW Rw RW Port 1 Output oo o ot on on egister 8 bit access register 16 bit access is possible 7 P 0 ort 1 Output from even address 7 6 5 4 3 2 1 0 P2 O UT 2 2 P2 P2 2 P2 2 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUTO x 00FFC2 R W R W RAW RW R W RW R W Port 2 Output 0 0 0 0 0 0 0 0 Reaister 01 0 1 9 8 16 bit access register 70 Port 2 Output 7 6 5 4 3 2 1 0 P3 U OUT7 OUT6 OUT5 OUTA4 OUT3 OUT2 x 00FFC3 R W R W R W R W R W R W RW RW Port 3 Output 0 0 0 0 0 0 0 0 R ister 01 01 01 0 1 01 egiste 8 bit access register 16 bit access is possible 7 0 Po
16. 8 OWN SAPE 90 0 01 00 005300 gant amp 1 ANGONV 4 3ngzNv snasny ang9NV ovq3J00x Dok LOK 2 e 0105 815196 060400 X 5 19095 guloOS HLlS00S 080400 855900 ON 88S 040400 51918 1 D v e H1991V aaa ones LDK S1JejsiDo1 099400 A GI L X HOLD 9199 0702 00 29151 o QININ3IN 020400 6 000400 JEMOT dew 2 2 6 IX 246 Data Appendix Chapter 9 Appendix 558999 16 8 Ioqui s ON AWEd gNSd RTT 55 9 qissod SI SSDL 110 9 559999 8 GW6d 888002 19 91 O 559998 19 91 8 044400 21084 064 093400 Ned e N8d Nl6d 04 00 1NO0d LNOld 1 UK NI9d 1nO8d LNO6d x 094400
17. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PPLU SB1P SBOP PA4P PA2P PA1P PAOP CSP REWEP P60P AHP ALP DHP DLP x 00FFBO RW RW Rw RW RAW R W R W RAW RW RW RW RW Port Pullup Control Register o fot ot on ot 04 ot ot on o ort Note Always set 0 16 bit access register 14 Pullup Resistors of Serial 1 0 Off 1 On Always set bit 15 to 0 Related Pins SBT1 581 SBO1 13 Pullup Resistors of Serial 0 0 Off 1 On Related Pins SBTO SBIO SBOO 12 Pullup Resistor of IRQ4 4 0 Off 1 On 11 Pullup Resistor of IRQ3 PA3 0 Off 1 On 10 Pullup Resistor of IRQ2 PA2 0 Off 1 On 9 Pullup Resistor of IRQ1 PA1 0 Off 1 On 8 Pullup Resistor of IRQO PAO 0 Off 1 On 7 Pullup Resistors of CS3 to CS0 0 Off 1 On 6 Pullup Resistors of External 0 Off 1 On Memory Related Pins RE BSTRE WEH WEL 5 Pullup Resistor of WAIT P60 0 Off 1 On 4 Pullup Resistors of A23 to A16 0 Off 1 On 3 Pullup Resistors of A15 to A8 0 Off 1 On 2 Pullup Resistors of A7 to AO 0 Off 1 On 1 Pullup Resistors of D15 to D8 0 Off 1 On 0 Pullup Resistors of D7 to DO 0 Off 1 On Data Appendix IX 229 Chapter 9 Appendix 7 6 5 4 3 2 1 0 PO U
18. AS IV 66 4 1 1 ONE ER UU HERE OUR UE IV 66 4 1 2 Control Registers IV 74 4 1 3 Timer Block Diagrams eee IV 75 8 bit Timer Setup Examples IV 80 4 2 1 Event Counter Using 8 bit Timer 2 IV 80 4 2 2 Clock Output Using 8 bit Timer IV 82 4 2 3 Interval Timer Using 8 bit Timer s IV 85 16 bit Timer Setup Examples IV 88 4 3 1 Event Counter Using 16 bit Timer IV 88 4 3 2 PWM Output Using 16 bit Timer IV 90 4 3 3 Two phase PWM Input Using 16 bit Timer IV 93 4 3 4 One phase Capture Input Using 16 bit Timer IV 96 4 3 5 Two phase Capture Input Using 16 bit Timer IV 98 4 3 6 Two phase Encoder Input Using 16 bit Timer 4x IV 100 4 3 7 One shot Pulse Output Using 16 bit Timer IV 102 4 3 8 External Count Direction Control Using 16 bit Timer Casauboni tente ar tmn IV 104 4 3 9 External Reset Control Using 16 bit Timer IV 106 Serial Interface serial Intertaces ua eT rH a ERO V 110 5 1 1 ONE EEE V 110 5 1 2 Control Registers iiciin eeneioe arerin oei reens i iis V 111 5 1 3 Serial Interface Connection a V 113 Serial Interface Setup Example
19. Burst ROM Setting mov INIT dO mov dO Aexmctr Set the number of wait cycles for block 0 to the MEMMDO register Set bit 10 HSWTIOE bit 9 NWAITIOE and bit 8 WAITSET of the MEMCTR register to 1 0 and 0 respec tively Set pins Set the number of wait cycles for each block to the associ ated MEMMDn register 1 2 3 Set the EXMCTR register when the burst ROM is used the ALE signal polarity is changed the pulse width of write enable signal is short ened Register Initialization 0 00 mov 0 041 mov 90 42 40 03 mov d0 a0 mov 0 1 mov d0 a2 mov STACK TOP a3 Interrupt Enable mov INIT 5 00 mov dO psw Clear register to 0 Execute this operation although this step is not always required Set the initial value of the stack pointer Always set the even address When using an interrupt set the interrupt mode and set the interrupt enable flag of PSW to 1 after setting the stack Chapter 9 Appendix Initialization Program IX 261 Chapter 9 Appendix x 80000 x9FFFF IX 262 Flash EEPROM Version 9 6 Flash EEPROM Version 9 6 1 Overview MN102LF61G is equivalent to MN102L610B with 128 KB of internal Flash EEPROM which is capable of being programmed erased electrically MN102LF61G is programmed one of two modes PROM writer mode which uses a dedicated PROM writer for a microcontroller s sta
20. 1 Read 0 Address 16 bit Unpopulated iFlash data register Register FDREG Address 72 Use 5 Addressing register for internal flash EEPROM serial programming 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O FDR FDR FDR FDR FDR FDR FDR FDR FDR FDR FDR FDR FDR FDR FDR Bit EG15 EG14 EG13 EG15 EG11 EG10 EG9 EG8 EG7 EG6 EG5 EG4 EG2 EG1 EGO RAW Atreset_ o ojojo ojojo o ojojo ojojojo o Read 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 01 0 1 O 1 0 1 0 1 bit Description 15 0 Address 15 to 0 bit Flash EEPROM Version IX 267 Chapter 9 Appendix 9 6 6 Pin Configuration in Onboard Serial Programming This section describes pin configuration for YDC serial writer All input output pins are input pins at reset release SBD connected with writer 73 74 should be connected SBT connected with writer to pull up resistors even when writer is not used OB P92 OA P91 C P90 OB P87 OA P86 c oo gt gt TM2IO P82 TM11O P81 TMOIO P80 WDOUT P47 STOP P46 P45 RESET G P44 ted 3 4 Vss with writer MN102LF61G Pas P41 TOP VIEW P40 100 pin QFH 16 gt 99 P17 gt 100 9 self excited or externaly excited 1 MHz to 22 6 MHz Figure 9 6 5 Pin Configuration for Serial Programming Connect 73 74 and 8
21. IV 95 Figure 4 3 6 One phase Capture Timing IV 97 Figure 4 3 7 Two phase Capture Timing IV 99 Figure 4 3 8 Two phase Encoder Input Timing 2 IV 101 Figure 4 3 9 One shot Pulse Output Timing IV 103 Figure 4 3 10 External Count Direction Control Timing IV 105 Figure 4 3 11 External Reset Control IV 107 Chapter 5 Serial Interface Figure 5 1 1 Figure 5 1 2 Figure 5 1 3 Figure 5 1 4 Figure 5 1 5 Figure 5 2 1 Figure 5 2 2 Figure 5 2 3 Chapter 6 Figure 6 1 1 Figure 6 1 2 Figure 6 1 3 Figure 6 1 4 Figure 6 1 5 Figure 6 1 6 Figure 6 1 7 Figure 6 2 1 Figure 6 2 2 Figure 6 2 3 Chapter 7 Figure 7 1 1 Figure 7 2 1 Figure 7 2 2 Serial Interface V 110 SCnSTR Change V 112 Asynchronous Connection x ite be Rte V 113 Syn hronous Conhection tite te dete e RR ee etd V 113 FC Mode Connection nianon saq V 114 Aynchronous Transmission Configuration sese V 116 Bit Transmission Timing Asynchronous Mode sess V 118 Transmission Reception in 22 V 122 Analog Interface Analog Interface Configuration 2 VI 124 A D Conversion eee ee ee te rre Hep Cone a VI 125 One Channel Single Conversion Timing
22. VI 126 Multiple Channels Single Conversion VI 126 One Channel Continuous Conversion VI 127 Multiple Channels Continuous Conversion VI 127 Analog Interface Block Diagram VI 128 One Channel A D Conversion VI 130 Multiple Channel A D Conversion VI 132 A D Conversion Timing Single Conversion of Channel 2 to Channel 0 VI 133 ATC ioc ittm eee etd VII 137 Serial Reception Data Transfer VII 140 Last Data Transfer Timing VII 140 Chapter 8 Ports Figure 8 2 1 Chapter 9 Figure 9 1 1 Figure 9 1 2 Figure 9 1 3 Figure 9 1 4 Figure 9 1 5 Figure 9 1 6 Figure 9 1 7 Figure 9 1 8 Figure 9 1 9 Figure 9 1 10 Figure 9 1 11 Figure 9 1 12 Figure 9 1 13 Figure 9 1 14 Figure 9 6 1 Figure 9 6 2 Figure 9 6 3 Figure 9 6 4 Figure 9 6 5 Figure 9 6 6 Figure 9 6 7 Figure 9 6 8 Figure 9 6 9 Figure 9 6 10 Figure 9 6 11 Figure 9 6 12 Figure 9 6 13 Byte Swap Register aa anun a a ih qa nen nenne VIII 158 Appendix System Clock Timing IX 181 Reset Timing one eet e ote cte i ente e Re EARS IX 181 Data Transfer Signal Timing Address Data Separate Mode Without Wait IX 182 Data Transfer Signal Timing Address Data Separate Mode With Walit IX 183 Data Transfer Signal
23. 044400 IdMS8d dMSHT1 5 0V4400 X 1902 1900 IX 247 Data Appendix Chapter 9 Appendix 9 2 3 List of P n Functions EE External excitation Pin Name Input Output Schmitt Pull up RESET BREQ L STOP HALT level level trigger register 1 P60 WAIT TTL CMOS Yes Programmable Hi Z Hi Z Hi Z i 2 P61 RE TIL CMOS Yes Programmable Hi Z High High Hi Z at RE Hi Z at RE 3 P62 WEL CMOS Yes Hi Z High High Hi Zat WEL Hi Zat WEL 4 P63 WEH TIL CMOS Yes Programmable Hi Z High High Hi Z at WEH Hi Z at WEH 5 50 650 CMOS Yes Programmable Hi Z High High Hi Z at 650 Hi Z at GSO 6 P51 CS1 TTL CMOS Yes Programmable Hi Z High High Hi Z at C81 Hi Z at 651 7 P52 CS2 CMOS Yes Hi Z High High Hi Z at CS2 Hi Z at C82 8 53 653 TTL CMOS Yes Programmable Hi Z High High Hi Z at CS3 Hi Z at CS3 9 P54 BREQ CMOS Yes No Hi Z Hi Z Hi Z Low 10 P55 BRACK TIL CMOS Yes No Hi Z Hi Z Hi Z Low 11 p56 ALE ALE BSTRE CMOS Yes Programmable Hi Z High High Hi Z except P56 Hi Z except P56 12 P57 WORD TTL CMOS Yes No Hi Z Hi Z Hi Z i 13 P20 A00 CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Zat 00 Hi Z at A00 14 P21 A01 TTL CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Z at
24. Special Registers 1 KB External Memory 448 KB Internal ROM 128 KB External Memory 884 KB Burst ROM Support Area External Memory 3072 KB External Memory 4 MB Actual Image 32 KB External Memory 4 MB CSO Area CS2 Area CS3 Area Y External Memor Peres Y Block 0 Block 3 Figure 2 1 1 Address Space Single chip Mode Memory Expansion Mode Processor Mode Chapter 2 Bus Interface X000000 Access Prohibited Area External Memory External Memory Figure 2 1 2 shows the bus con 008000 troller of the MN102LF61G Internal RAM Internal RAM Internal RAM X009000 Access Prohibited Area Access Prohibited Area Access Prohibited Area Special Registers Special Registers Special Registers 010000 Access Prohibited Area External Memory External Memory 080000 Reset Handler Reset Handler Reset Handler Internal ROM Interrupt Handler nternal ROM Interrupt Handler Interrupt Handler External Memory x 0A0000 Access Prohibited Area External Memory X FFFFFF Pin Mode H Pin Mode H Pin Mode L After reset set ports 0 1 2 3 4 5 6 to Bus controller of the A23 00 D15 000 and Bus interface MN102LF61G signals using software Figure 2 1 2 Bus Controller In this series the addresses of x 000000 to x 007FFF replaces
25. 15 14 13 12 11 110 9 8 7 5 4 3 2 1 0 G4 G4 G4 SCIR SC1T IRQ3 SC1R SC1T TM3 IRQ3 1 1 IRQ3 LV2 LV1 LVO IE IE IE IE IR IR IR IR ID ID ID ID R W R W RW RAW RAW RW RW R R R R yo o on ot ot on ot on on 14 12 Group 4 Interrupt 000 level 0 to 110 level 6 Priority Level 11 Serial 1 Reception End 0 Disable 1 Enable Interrupt Enable Flag 10 Serial 1 Transmission End 0 Disable 1 Enable Interrupt Enable Flag 9 Timer 3 Underflow 0 Disable 1 Enable Interrupt Enable Flag 8 IRQ3 Interrupt Enable Flag 0 Disable 1 Enable 7 Serial 1 Reception End 0 No interrupt requested Interrupt Request Flag 1 Interrupt requested 6 Serial 1 Transmission End 0 No interrupt requested Interrupt Request Flag 1 Interrupt requested 5 Timer 3 Underflow 0 No interrupt requested Interrupt Request Flag 1 Interrupt requested 4 IRQ3 Interrupt Request Flag 0 No interrupt requested 1 Interrupt requested 3 Serial 1 Reception End 0 No interrupt detected Interrupt Detect Flag 1 Interrupt detected 2 Serial 1 Transmission End 0 No interrupt detected Interrupt Detect Flag 1 Interrupt detected 1 Timer 3 Underflow 0 No interrupt detected Interrupt Detect Flag 1 Interrupt detect
26. AD00 0 cs e WEH i kr L 8 bit U 8 bit WEL x Access Access Le 4 M 16 bit Read 8 bit Write 8 bit Write High Side Low Side Figure 2 2 14 Fixed Wait Access Timing with 8 bit Bus Width r OSCI SYSCLK A23 A16 I Address Data Address Data AD15 AD08 Address Address 7 AD07 AD00 ADOO 0 AD00 1 x CS RE WEH WEL i Lower Upper 8 bit Access Access 2 16 bit Write Us Figure 2 2 15 Handshake Access Timing with 8 bit Bus Width External Memory Connection Example 53 Chapter 2 Bus Interface m Access Timing during Bus Request Address Data Shared Mode OSCO SYSCLK A23 A16 FLOAT NG D15 D00 A D FLOATING Bianca s ALE
27. 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 Set the timer 6 duty Since the duty is 2 5 of SYSCLK set 1 to the timer 6 compare capture register B TM6CB The valid range for TM6CB is 1 2 TM6CB lt TM6CA TM6CB x 00FE38 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 TM6 6 6 TM6 6 TM6 CB15 CB14 CB13 CB12 1 10 9 CB8 CB7 6 5 2 CB1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 In the double buffer mode compare TM6BC to TM6CAX The TM6CAX is updated when TM6CAX TM6BC so that TM6CAX remains x 0000 be fore TM6BC starts counting Therefore to load the TM6CA value to TM6CAX write the dummy data to TM6CAX The dummy data can be any values TM6CAX x 00FE36 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 TM6 6 TM6 TM6 TM6 TM6 TM6 TM6 TMe TM6 TM6 TM6 TM6 TM6 TM6 TM6 15 14 13 12 CAX11 CAX10 CAX8 CAX6 5 CAX2 CAX1 CAXO 6 In the double buffer mode compare TM6BC to TM6CBX The TM6CBX is updated when TM6CBX TM6BC so that TM6CBX remains x 0000 be fore TM6BC starts counting Therefore to load the TM6CA value to TM6CBX write the dummy data to TM6CBX The dummy data can be any valu
28. TM4 BR7 TM4 BR6 TM4 BR5 TM4 BR4 TM4 BR3 TM4 TM4 BR2 BR1 TM4 BRO R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Timer 4 Count Cycle Set the count cycle 2 to 256 Timer 4 counts the set value plus 1 The valid range for is 0 to 255 5 BR7 TM5 BR6 5 BR5 TM5 BR4 5 5 BR2 5 BR1 TM5 BRO R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Timer 5 Count Cycle Set the count cycle 2 to 256 Timer 5 counts the set value plus 1 The valid range for is 0 to 255 Set the count cycle 2 to 256 Timer 3 counts the set value plus 1 The valid range for TM3BR is 0 to 255 Chapter 9 Appendix TM3BR 13 Timer 3 Base Register 8 bit access register 16 bit access is possible from even address TM3BR is set to 0 after timer 3 starts See 4 2 8 bit Timer Setup Examples for details TM4BR x OOFE14 Timer 4 Base Register 8 16 bit access register 4 is set to 0 after timer 4 starts See 4 2 8 bit Timer Setup Examples for details TM5BR x 00FE15 Timer 5 Base Register 8 bit access register 16 bit access is possible from even address TM5BR is set to 0 after timer 5 star
29. 8 bit access register 16 bit access is possible 5 0 Port 7 Output from even address A 6 5 4 3 2 1 0 P8 U T 2 Pa PB PB OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUTO x 00FFC8 RAW RA RAV RAW RW Port 8 Output 1 ot ot on ot ort Register 8 16 bit access register 7 0 Port 8 Output ENTEN P9OUT P9 P9 P9 P9 OUT3 OUT2 OUT1 x 00FFC9 R R R RW Port 9 Output olololololololo Regist for egister 8 bit access register 16 bit access is possible 3 0 Port 9 Output from even address 7 6 5 4 3 2 1 0 PAOUT 5 ours our4 ours oure ourt ouro x 00FFCA R gw Rw RW RW RW RW Port Output TETTE TETT TEITE Reaist on egister 8 16 bit access register 5 0 A Output 232 Data Appendix 7 6 5 4 3 2 1 0 PO ING IN5 INA INS IN2 IN1 INO R R R R R R R R Port Port Port Port
30. 89 TOP VI EW 37 9A14 P36 P06 D06 ADO6 90 36 4 d A13 P35 P07 D07 AD07 lt 91 35 gt A12 P34 Vss 92 34 4 P10 D08 ADO8 93 33 A11 P33 P11 D09 AD09 94 32 10 2 P12 D10 AD10 95 31 gt A09 P31 P13 D11 AD11 96 30 9 A08 P30 P14 D12 AD12 97 29 4 A07 P27 P15 D13 AD13 98 4 A06 P26 16 014 014 99 gt 05 25 P17 D15 AD15 100 26 A04 P24 N 4 P50 CS0 5 6 P52 CS2 t 7 10 17 SYSCLK lt 18 Vss 19 XI 20 XO 21 22 OSCI 23 OSCO 24 MODE 25 51 51 P53 CS3 8 54 9 P21 A01 4 5 14 P61 RE lt 2 P20 A00 w s 13 P22 A02 gt 15 P23 A03 16 P62 WEL lt 3 P60 WAIT lt 1 P63 WEH P55 BRACK P57 WORD 12 P56 ALE ALE BSTRE gt 11 Use 33 to 50 Figure 1 4 1 Pin Configuration The unused input pins are connected to Vpp Vss the unused output pins 1 are opened and the unused pins are connected to Vpp Vss by setting the direction in ports or opened I 12 Pin Description 1 4 1 List of Pin Functions Chapter 1 Overview Refer to 9 2 3 List of Pin Functions for each pin s input level and S
31. 1 67 66 04 65 63 62 bti bO Transmit Interrupt Request SBT Pin Output START Detect Bit 1 2 V 122 Serial Interface Setup Examples Transmit Interrupt Request Iinnnnnnnnme nnnnmnnnm 3 6 STOP Detect Bit 1 8 Figure 5 2 3 Transmission Reception in Mode Chapter 6 Analog Interface 3 Chapter 6 Analog Interface VI 124 Analog Interface 6 1 Analog Interface 6 1 1 Overview This LSI series contains a 8 bit charge redistribution A D converter The A D converter supports digital signal processing in the voice and audio frequency ranges with a 8 bit resolution a maximum con version frequency of 208 kHz 4 8 per channel with 20 MHz oscillator and a low current VDD A Dn Conversion Data Buffer ANO ANOBUF 1 AN1BUF M 8 bit AN2BUF AN3 0 gt S H Successive gt Approximation ANABUF ANS X ANSBUF AN6 AN6BUF AN7 AN7BUF Vss Figure 6 1 1 Analog Interface Configuration m Notices When Using A D Converter 1 Set the impedance of the analog signal for A D conversion to 8 kO or less 2 Connect the A D input pin to the condenser of 2000 pF or more to control the voltage change of the A D input pin if the impedance of the
32. 6 6 6 6 15 14 13 12 11 10 CB9 CB8 7 6 5 CB2 R W R W R W R W R W R W R W R W R W R W R W R W R W RW RW 01 0 1 01 01 Oft 15 0 Timer 6 PWM Change or Interrupt Generation IX 224 Data Appendix TM6BC 00 2 6 Counter 16 bit access register is a read only register TM6CA x 00FE34 Timer 6 Compare Capture Register A 16 bit access register When capture is selected TM6CA reads the captured values and a timer 6 capture A interrupt is gen erated when capture occurs When compare is selected set the PWM cycle When this regis ter matches the timer 6 binary counter a timer 6 capture A inter rupt occurs 6 x 00FE38 Timer 6 Compare Capture Register B 16 bit access register When capture is selected TM6CB reads the captured values and a timer 6 capture B interrupt is gen erated when capture occurs When compare is selected set the PWM cycle When this regis ter matches the timer 6 binary counter a timer 6 capture B inter rupt occurs Chapter 9 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM7MD 7 7 TM7 TM7 TM7
33. Figure 2 2 11 MEMMDO x 00FC30 Memory Connection Example with 8 bit Bus Width Address Data Shared Mode 15 14 13 12 11 10 9 8 7 5 4 2 1 0 In the MN102 series the data is input to the upper pins of D15 to 008 1 0 MEMMD1 x 00FC32 15 14 13 12 10 9 8 7 5 4 2 1 0 BMOD 1 0 1 00 6 15 14 13 12 11 10 9 8 7 5 4 2 1 0 BMOD WAIT1 WAITO External Memory Connection Example II 51 Chapter 2 Bus Interface B ROM RAM Access Timing with 16 bit Bus Width OSCI SYSCLK A23 A16 __ Address Data Address Data Address Data Address AD15 AD08 Address Data ddress Data Address Address Data AD07 AD00 I NN AD00 0 1 AD00 0 AD00 1 000 0 ALE Read 16 bit Write 8 bit Write
34. P7IN3 P7INO Serial I F Clock Input Ports 147 Chapter 8 Ports Table 8 1 1 Port Functions 7 of 8 Port Pin Function Shared Pin Port 8 is used as the port 8 general purpose port or timer input output pins TMOIO TM6IOB to 5 TM6IOA TM6IOB At reset this port operates as a general purpose port P86 input P85 to P80 P8DIR7 to 0 5 to TMOIO P8MD7 to 0 P8OUT7 to 0 0 Timer Output 1 P87 TM6IOB P86 TM6IOA P8IN7 to 0 P85 to 80 to TMOIO Timer Input P97 to P94 Port 9 is used as the port 9 general purpose port timer input output pins or A D AN3 to ANO converter input pins AN3 to ANO TM7IC 7 TM7IOA TM6IC At reset this P93 port operates as a general purpose port input TM7IC 92 P9DIRS to 0 TM7IOB P91 TM7IOA P90 TM6IC P9MD2 P9MD1 P9OUTS to 0 0 Mux C Timer Output P92 TM7IOB P93 and P90do not have MUX 27 1 P91 PSINS to 0 1 P90 TM6IC Timer Input P9DIR3 P9OUTS P93 TM7IC P9IN3 Timer Input P9MD3 P9DIR3 VIII 148 Ports Chapter 8 Ports Table 8 1 1 Port Functions 8 of 8 Port Function en Pin Port
35. TM1BR TM1 TM1 TM1 TM1 TM1 TM1 TM1 BR7 BR5 BR2 BR1 BRO x 1 1 R W R W R W RW R W RW RW R W Timer 1 Base Register 0 0 0 0 0 0 0 0 01 0 1 01 04 0 1 0 1 8 bit access register 16 bit access is possible 7 0 Timer 1 Count Cycle from even address Set the count cycle 2 to 256 Timer 1 counts the set value plus 1 The valid range for TM1BR is 0 to 255 TM1BR is set to 0 after timer 1 starts See 4 2 8 bit Timer Setup Examples for details TM2BR TM2 TM2 2 2 TM2 2 2 2 BR7 BR6 BRA BR2 BRO x 1 2 R W R W R W R W R W RW RW R W Timer 2 Base Register 0 0 0 0 0 0 0 0 0 1 01 01 01 01 8 16 bit access register 7 0 Timer 2 Count Cycle Set the count cycle 2 to 256 Timer 2 TM2BR is set to 0 after timer 2 counts the set value plus 1 The valid starts See 4 2 8 bit Timer range for TM2BR is 0 to 255 Setup Examples for details IX 218 Data Appendix TM3 BR7 TM3 BR6 TM3 BR5 TM3 BR4 TM3 BR3 TM3 TM3 BR2 BR1 TM3 BRO R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Timer 3 Count Cycle
36. crie testet reet I 8 Block Dia stam eae ee o etie o ipte eere es I 10 Pim Description iiie er I 12 1 4 1 List Of Pin 1 13 Package Dimension iL I 23 Bus Interface Bus Intetface II 26 2 1 1 patei 26 2 1 2 Control Registers ehe ete ertet II 32 2 1 3 ROM Burst Mode II 36 External Memory Connection Examples II 40 2 2 1 Memory Expansion Mode Address Data Separated Mode II 40 2 2 2 External Memory Connection Examples Address Data Separeted II 42 2 2 3 Memory Expansion Mode Address Data Shared Mode II 48 2 2 4 External Memory Connection Examples Address Data Shared Mode II 50 Interrupts Interrupt Groups iiiter ete e D III 56 3 1 1 OV ELVIEW E E III 56 External Interrupts iu s rentre err YR III 58 3 2 1 External Pin Interrupts III 58 3 2 2 NMI Pin Interrupts eere enis III 58 Interrupt Setup Examples 60 3 3 1 External Pin Interrupt 60 3 3 2 Watchdog Timer Interrupt III 62 Chapter 4 4 1 4 2 4 3 Chapter 5 5 1 5 2 Timers Counters TIS oir
37. 0 TMO TMO BR7 5 BR4 BR2 BR1 BRO Chapter 4 Timers Counters This verification is unnecessary immediately after a reset a If setting 1 of divisor write the dummy value for example once 8 bit Timer Setup Examples IV 85 Chapter 4 Timers Counters If selecting 1 of divisor set 0 to the timer 0 base register TMOBR once again after step 7 The first count is the value set in step 4 but the second count becomes 1 For example if 0 is setto TMOBR in step 4 the first count is 257 and the second count becomes 1 This verification is unnecessary immediately after a reset Changing the clock source while controlling count operation will corrupt the binary counter value IV 86 8 bit Timer Setup Examples b Load the TMOBR value to TMOBC To do this set TMOLD and TMOEN to 1 and 0 resepctively TMOMD 20 7 6 5 4 3 2 1 0 TMO TMO TMO TMO LD 0 0 1 0 6 Set both TMOLD and TMOEN of the TMOMD register to O If this setting is omitted the timer 0 binary counter may not start at the first cycle 7 Set TMOLD and TMOEN to 0 and 1 respectively This starts timer 0 Count ing starts at the beginning of the next cycle When the timer 0 binary counter TMOBC reaches 0 and loads the value of 1 from the timer 0 base register TMOBR
38. 2900 uS 4Byle Oscillator frequency Write time Guaranteed programming Touch time am Electrical Characteristics IX 163 Chapter 9 Appendix C Electrical Characteristics 1 DC Characteristics Vpp 5 0 V Vss 0 V Ta 40 C to 85 C Parameter Conditions Unit Max Power supply Vi Vpp or Vss current during Fosc1 22 6 MHz 75 operation Output pins open Power supply Vi or Vss current during slow Fosc2 32 kHz mode Output pins open Power supply current in HALTO mode Fosc1 22 6 MHz Fosc2 32 kHz Power supply Fosc1 Oscillator current in HALT1 stop mode Fosc2 32 kHz Power supply current in STOP Oscillator Stop uA All functions stop mode IX 164 Electrical Characteristics Chapter 9 Appendix Vpp 4 5 V to 5 5 V Vss 0 V 40 C to 85 G Capacitance Parameter Symbol Conditions OX Unit Input Output Pins 1 Output pushpull Input TTL level schmidt trigger gt TMnIO n 0 to 5 TMnIOA n26 7 TMnIOB n 6 7 TM6IC ADSEP 5 0 V 5 0 V Input Output Pins 2 Output pushpull Input TTL level schmitt trigger Programmable pullup 5801 5 5811 5800 580 SBTO Voo 5 0 V Output high voltage ae ORA Voo 5 0 V Output low voltage ig 4 0 mA C16 Pullup resistance PPU1 MS SUN 10 30 50 1 5 Electrical Characteristics IX 165 Chapter 9 Appendix Vpop 4 5 V to 5 5 V Vss 0 V 40 C
39. AN7 to 6 Watchdog overflow STOP 7 PAIN7 to 6 To A D Converter Pots 145 Chapter 8 Ports Table 8 1 1 Port Functions 5 of 8 Port Pin Function Shared Pin P57 to P50 Port 5 is used as the port 5 general purpose port or external memory interface WORD signals pins WORD BSTRE ALE ALE BREQ CS3 to CSO At reset BSTRE this port operates as a general purpose port input during other modes except pro ALE ALE cessor mode while P56 P53 to P50 pins operate as BSTRE ALE ALE BRACK BRACK CS3 to CSO pins during processor mode During processor mode P5MD6 BREQ to P5MDO are invalid CS3 to CS0 BIFP1 to 0 P57 P55 P54do not External memory Interface Signal contain pull up resistors Output Control Bus Controller P5DIR7 to 0 P5MD6 to 0 P5OUT7 to 0 MR P57 to 50 External Memory Interface Signal 1 WORD CS3 to0 Bus Controller P57 does not have MUX i BSTRE ALE ALE P5IN7 to 0 WORD BREQ Bus Controller P63 to P60 Port 6 is used as the port 6 general purpose port or external memory interface WEL WEH signals pins WAIT RE WEH WEL At reset this port operates as a general RE WAIT purpose port input during other modes except processor mode while P63 to P61 pins operate a
40. Transfer Content 2 Stat Serial Reception Internal RAM Write uffer i Figure 7 2 2 Last Data Transfer Timing VII 140 ATC Setup Examples Chapter 8 Ports 8 Chapter 8 Ports Port Pin Shared Pin VIII 142 Ports 7 to P00 007 to 000 AD07 to ADOO 8 1 Ports 8 1 1 Overview This LSI series contains ten I O ports Of ports 0 to 5 port 8 and port 9 are 8 bits Port 7 and port A are 6 bits Port 6 is 4 bits All ports are bidirectional Port 0 and Port 1 control the I O direction 8 bit unit Port 2 controls the I O direction in 4 bit unit while ports 3 to A control the I O direction in bit unit Table 8 1 1 Port Functions 1 of 8 Port 0 is used as the port 0 general purpose port data address data separated input output or address data address data shared input output At reset this port operates as a general purpose port input during other modes except processor mode and as 007 to DOO AD07 to ADOO pins during processor mode However this port operates as a general purpose port during processor mode when 8 bit bus width is selected for all spaces in address data separated mode The mode for port 0 is selected in 8 bit unit During processor mode without 8 bit bus width setting for all spaces POMD is invalid During memory expansion mode set POMD and PODIR to 1 and 0 respectively DLP Address Data Output Control Bus Controller PODIRO
41. 01 7 0 Port4 Input 7 6 5 4 3 2 1 0 P5 P5 P5 P5 P5 P5 IN6 IN5 2 INA INO R R R R R R R R Port Port Port Port Port Port Port Port 01 0 1 0 1 0 1 0 1 0 1 7 0 Port 5 Input IX 234 Data Appendix x 00FFD3 Port 3 Input Register 8 bit access register 16 bit access is possible from even address PAIN x OOFFD4 Port 4 Input Register 8 16 bit access register x 00FFD5 Port 5 Input Register 8 bit access register 16 bit access is possible from even address Chapter 9 Appendix 7 6 5 4 3 2 1 0 P6 P6 P6 P6 IN2 IN1 INO x 00FFD6 SEE DENE SEE Port 6 Input 0 0 0 0 Port Port Port Port Register 8 16 bit access register 3 0 Port 6 Input 7 6 5 4 3 2 1 0 P7IN P7 P7 P7 P7 P7 P7 IN5 IN4 INO X 00FFD7 BEE m E n Port 7 Input 1 1 Port Port Port Port Port Port R l r 1 1 01 eg ste 8 bit access register 16 bit access is possible 5 0 Port 7 Input from even address 7 6 5 4 3 2 1 0 PSIN P8 P8 P8 P8 P8 P8 P8 P8
42. 7 1 PODIR to PIDIR and re set as same as Use A23 to A22 as general purpose ports those in the above P4DIR 1 1 1 ofof 1 No 8 i PODIR to PIDIR and MD are set as same as Use A23 as a general purpose port those in the above P4DIR 1 1 MD of 1 1 P6MD o No 9 Up to 16 Mbytes PODIR to PIDIR and POMD and P1MD are set as same as those in the above P4DIR 1 P4MD P6MD II 48 External Memory Connection Example Chapter 2 Bus Interface External Memory Connection Example II 49 Chapter 2 Bus Interface During the address data shared mode this LSI series operates in 1 wait cycle even though WAIT 1 0 are set to 00 2 2 4 Address Data Shared Mode External Memory Connection Examples This section describes the external memory connection examples B Memory System with 16 bit Bus Width The following is the example of connecting the 4 Mbit ROM 256 kilo words x 16 bits the 1 Mbit SRAM 128 kilo words x 8 bits and the ASIC with 16 bit bus width to the CSO area 1 wait cycle fixed the CS1 area 1 wait cycle fixed and the CS3 area handshake respectively 15 8 N N 1 18 16 AD15 AD08 A23 A19 AD07 A00 ALE cso cst ADSEP WAIT WORD CS3 7 0 15 0 15 15 0 18 16 D Q E 15
43. Start serial writer load program Branch to address 81808 t Execute user program Figure 9 6 10 Branching to the reset start routine When the reset starts the serial writer load program initializes only if SBD is low Otherwise the program branches to the user program at address 0x81810 2 Branching to the interrupt start routine Interrupt start address 80008 jmp 81810 instruction 3 bytes 2 cycle Write a branch instruction to address 81810 Branch to address 81810 Execute user interrupt service routine 2 cycle delay is generated Figure 9 6 11 Branching to the interrupt start routine In the interrupt start address place a simple branch instruction pointing to address 0x81810 Flash EEPROM Version IX 273 Chapter 9 Appendix 9 6 10 Serial Interface for Onboard Programming B Features Fixed length serial interface Character length 8 bits Transfer bit LSB first Source clock External clock Maximum transfer rate 5 Mbps at 20 MHz oscillating Error detection Overrun error Buffer Transmission reception buffer transfer single buffer re ception double buffer m Data timing SBD LSB MSB SBT Figure 9 6 12 Data Transfer Timing Serial data is transferred in 8 bits LSB first IX 274 Flash EEPROM Version Chapter 9 Appendix mRegister Configuration Fixed length serial transmission reception buffer Register SFTRB Address x 00FD72 Use Hol
44. 11 10 CA9 CA6 5 CA4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 Write 1 to TM7CB TM7CB x 00FE48 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM7 TM7 7 7 7 7 TM7 CB15 CB14 CB13 CB12 CB11 CB10 CB9 TM7 CB8 TM7 CB7 TM7 CB6 TM7 CB5 TM7 CB4 TM7 CB3 TM7 CB2 TM7 CB1 TM7 CBO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 4 Set TM7NLD and TM7EN to 1 and 0 respectively This enables TM7BC T F F and RS F F 5 Set TM7EN to 1 when TM7IOB rises Counting starts at the beginning of the next cycle after TM7IOB rises Figure 4 3 9 shows the one shot pulse output timing Set TM7EN on the falling edge of TM7IOB and start counting from the next cycle Before counting starts TM7BC is 0 the initial value of is 0 and a reset R signal and a set S signal cannot be output When counting starts TM7BC changes from 0 to 1 and the S signal is output TM7IOA becomes 1 and the pulse is output TM7BC reaches 3 TM7BC resets and changes from 3 to 0 At the same time the R signal is output and TM7IOA outputs 0 Because TM7ONE is set to 1 the TM7EN flag is also reset and counting stops When rises again TM7EN is set and the same operation is repeated As a result the one shot pulse is output TM7CA 0003
45. D15 to D08 P4DIR 0 0 0 0 0 0 0 0 P4MD In addition use A23 to A22 as general purpose ports when the address is P6MD EL determined by CS3 to CSO PODIR to P3DIR and POMD to P3MD are same as those 16bit in the above 16 bit bus width of No 10 Use CS3 to CSO as general purpose ports D15 to DOO P4DIR and P4MD are same as those in the above 8 bit bus width In addition use A23 to A22 as general purpose ports when the address is determined by CS3 to CS0 External Memory Connection Example Chapter 2 Bus Interface II 41 Chapter 2 Bus Interface 2 2 2 External Memory Connection Examples Address Data Separeted Mode This section describes the external memory connection examples B Memory System with 16 bit Bus Width The following is the example of connecting the 4 Mbit ROM 256 kilowords x 16 bits the 1 Mbit SRAM 128 kilo words x 8 bits and the ASIC with 16 bit bus width to the CSO area 1 wait cycle fixed the CS1 area no wait cycle fixed and the CS3 area handshake respectively A18 A00 D15 D00 18 1 16 0 150 158 150 A23 A19 615 000 A17 A00 07 0 A16 A00 D A Port ROM SRAM CS1 pu E ASIC ADSEP WAIT WAIT WorD CS3 58 N N WEL RE l i Figure 2 2 1 Memory Connection Example with 16 bit Bus Width Ad
46. H Y TM410 pin Timer 3 cascade Reset Low speed 4 Selector 1 2 Figure 4 1 18 Timer 4 Block Diagram Data Bus 8 8 8 00 15 Timer 5 Base Register TM5BR Load Reload lt 00 05 Sie Timer 4 cascade signal U 8 TMAIO pin pin P30 Timer 4 cascade TimerO Low speed 4 Selector Timer 5 Binary Counter m 5 iQ 5 e Y gt 1 2 Figure 4 1 19 Timer 5 Block Diagram Underflow Interrupt Controller 0 TMBIO pin P30 Chapter 4 Timers Counters Timers IV 77 Chapter 4 Timers Counters Timers IV 78 TM6IC ECLR 4 Clear 5 amp han 21 9 TM6BC x00FE32 SYSCLK EN DL pg og 4 U D Contro Load I When TM6BC 0 LP ASEL S 100 TM6CA
47. IBREDR4e m Fig 9 1 7 Data Transfer Signal Timing Burst ROM Interface IX 186 Electrical Characteristics Chapter 9 Appendix BRACK Z BREQ TBREQS Fig 9 1 8 Bus Authority Request Signal Timing tNMIW Fig 9 1 9 Interrupt Signal Timing SBT1 0 SBO1 0 trxDD tTXDH 1 Fig 9 1 10 Serial Interface Signal Timing 1 Synchronous Serial Transmission Transfer in Progress SBT1 0 SBI1 0 lt M lt M trxDD Fig 9 1 11 Serial Interface Signal Timing 2 Synchronous Serial Transmission Transfer End Timing at SBT Input Electrical Characteristics IX 187 Chapter 9 Appendix SBT1 0 SBI1 0 lt P Fig 9 1 12 Serial Interface Signal Timing Synchronous Serial Transmission Transfer End Timing at SBT Output SBT1 0 SBI1 0 tRxps Fig 9 1 13 Serial Interface Signal Timing 2 Synchronous Serial Reception TMnlO n 5 0 TMnIOA n 6 7 N 7 N TMnIOB n 6 7 TMnIC n 6 7 m trccLkL mum g Fig 9 1 14 Timer Counter Signal Timing IX 188 Electrical Characteristics Chapter 9 Appendix 9 2 Data Appendix 9 2 1 List of Special Registers Data Appendix IX 189 Chapter 9 Appendix About This Section Description of Each Page Each page of this chapter
48. P10 lt 93 100 pin LQFP 33 P33 P11 94 32 P32 P12 95 31 w P31 96 gt P30 P14 97 29 P27 P15 98 o 28 P26 P16 gt 99 27 P25 P17 100 26 P24 ran AEA T D AE 5 o gt XS HO gt 2 Figure 2 1 7 Single chip Mode 30 Bus Interface Chapter 2 Bus Interface Bus Interface II 31 Chapter 2 Bus Interface II 32 Bus Interface 2 1 2 Control Registers These registers control the bus interface the memory control regis ter MEMCTR the memory moode control register MEMMDn and the external memory control register EXMCTR Table 2 1 2 List of Bus Interface Control Registers Register Address RW Function MEMCTR x 00FC02 R W Memory Control Register MEMMDO x 00FC30 R W Memory Mode Control Register 0 MEMMD1 x 00FC32 R W Memory Mode Control Register 1 MEMMD2 x 00FC34 RW Memory Mode Control Register 2 MEMMD3 x00FC36 RW Memory Mode Control Register 3 EXMCTR x 00FD00 RW Control The MEMCTR register and the MEMMDn register need to set the conditions matched the system configuration during the initialization program See 9 4 Initialization Program MEMCTR register sets 4 n 0 to the wait cycle of special registers is normally 1 du
49. Points for Programming 1 Setting the CPUM address in the address register in advance set the CPUM register using the MOV instruction with the register indirect addressing mode 2 Immediately after the MOV instruction locate three NOPs consecutively 3 Immediately before the MOV instruction locate the JMP instruction and align to the even address This avoids the effects by the differences of the bus widths in the memory mode or expansion mode and provides the same result when operating in any conditions Programming Coding Example in Assembler as 102Ver 1 0 Ver 2 0 MOV CPUM AO Set A0 to the CPUM address MOV A0 DO Transfer the contents of CPUM to DO OR 000 DO Generate the data to set the STOP HALT mode JMP STP HLT Branch unconditionally to the even address to ALIGN 2 eliminate the difference of operating conditions STP HLT MOV DO A0 Setthe STOP HALT mode to CPUM NOP Dummy NOP Dummy NOP Dummy Precautions 1 of OR instruction varies depending on the STOP or HALT mode 2 Setthe ALIGN value to 2 or more in the above file when the ALIGN value is set using SECTION dummy instruction before this programming coding is described 3 Code the above programming in another file of the assembler source file when the program is developed with C complier cc 102 Data Appendix IX 191 Chapter 9 Appendix 15 14 13
50. Timing SBO SBT SCnSTS Start Detect SCnTRB Write d SCnSPS 7 After reset the signal is low during the first I C transmission The signal is high during other transmission Figure 5 1 2 SCnSTR Change Timing V 112 Serial Interface Chapter 5 Serial Interface 5 1 3 Serial Interface Connection There are six serial interface connecting methods Asynchronous Mode The serial interface can connect using either simplex transfer or duplex transfer mode SBO SBO SBO SBO A 5 58 SBI C SBI SBI amp E E 2 2 Transmit Receive Simplex Connection Duplex Connection Figure 5 1 3 Asynchronous Connection Synchronous Mode The serial interface can connect using either simplex transfer duplex transfer or half duplex transfer mode SBO SBO 5 580 580 5 gt 2 SBI SBI E SBI SBI gt 2 2 2 SBT SBT SBT SBT 2 Transmit Receive See Chapter 7 for SBT port setup Simplex Connection Duplex Connection SBO SBO SBI A SBI SBT SBT Half duplex Connection SAIS09H NWSUEI 9AI999H IUISUPI Figure 5 1 4 Synchronous Connection When the data cannot be tra
51. are No3 Up to 512 bytes 8 bit as those in the above 8 bit bus width of No 1 Use D07 to D00 as general purpose ports A08 to A00 15 to D08 P3DIR o e e e e e eL Use A23 to A09 as general purpose ports 16 bit PODIR to P2DIR P4DIR and POMD to P2MD P4MD are Use A23 to A09 as general purpose ports 015 to D00 same as those in the above 16 bit bus width of No 1 and P3MD are same as those in the above 8 bit bus width PODIR to P2DIR P4DIR and POMD to P2MD No4 Upto Ik bytes 8bit as those in the above 8 bit bus width of No 1 Use D07 to 00 as general purpose ports A09 to A00 D15 to D08 P3DIR o o P3MD 2 0 0 0 0 0 1 1 Use A23 to A10 as general purpose ports 16bit PODIR to P2DIR P4DIR and POMD to P2MD P4MD are Use A23 to A10 as general purpose ports D15 to D00 same as those in the above 16 bit bus width of No 1 P3DIR and P3MD are same as those in the above 8 bit bus width PODIR to P2DIR P4DIR and POMD to P2MD P4MD are No 5 Upto2k bytes 8bit same as those in the above 8 bit bus width of No 1 Use D07 to DOO as general purpose ports A10 to A00 15 to D08 P3DIR P3MD 1 Use A23 to A11 as general purpose ports 16bit PODIR to P2DIR P4DIR and POMD to P2MD P4MD are Use A23 to A11 as general purpose ports D15 to D00 same as those in the above 16 bit bus width of No 1 P3DIR and P3MD are same a
52. please obtain product specifications from the sales office Package Demension I 23 Chapter 2 Bus Interface Chapter 2 Bus Interface The MN102L610B has only pro cessor mode MN102L610B does not contain internal ROM Accessing the virtual area us ing the program means access ing the real area in this series II 26 Bus Interface 2 1 Bus Interface 2 1 1 Overview This series contains three memory modes of single chip mode memory expansion mode and processor mode The chip of this series connects to the external memory or consisted of gate array in the expansion mode or processor mode The address space is divided into four fixed areas Block 0 to Block 3 Each block has approximately 4 MB area and generates four chip select signals to its corresponding external space The address space is optionally divided when the chip select signals are generated externally 16 bit bus width or 8 bit bus width is selected for each block The WORD pin sets the 16 bit bus width or 8 bit bus width for Block 0 where the reset handler exists On the other hand the MEMMDn register sets the bus width for Block 1 to Block 3 See 1 4 Pin Functions for pin setting x 000000 x 008000 x 009000 x 00FC00 x 010000 x 080000 0 0000 x 100000 x 400000 x 800000 x C00000 x FFFFFF Virtual Image 32 KB External Memory Internal RAM 4 KB ccess Prohibited 27
53. 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 Whenever the up or down counter reaches the TM7CA value a compare capture A interrupt occurs at the beginning of the next cycle 4 Set the value for a timer 7 interrupt when the interrupt occurs at the TM7CB value The valid range is 0 to TM7CA When the up or down counter reaches this value a compare capture B interrupt occurs at the beginning of the next cycle Set the value for timer 7 interrupt when the TM7BC counts from 0 to FFFF The valid range is 0 to x FFFF b Set TM7NLD and TM7EN to 1 and 0 respectively This enables TM7BC and RS F F Do not change other bits of the TM7MD register 6 Set both TM7NLD and TM7EN to 1 This starts timer 7 Counting starts at the beginning of the next cycle W interrupt Processing 6 Execute interrupt processing The interrupt processing specifies the inter rupt group and vector and clears IRFn The following figure shows the count direction Fig 0 1 1 7 1FFF 7 1000 TM7BC 0000 1FFF 1FFE 1FFD 1FFF 0000 0001 1000 1001 TM7IOA TM7IOB Interrupts Figure 4 3 8 Two phase Encoder Input Timing Chapter 4 Timers Counters If this step is omitted TM7BC may not count during the first cycle 16 bit Timer Setup Examples IV 101 Chapter 4 Timers Counters Use the
54. 11 Capture A when pin is high Capture B when pin is high 5 TM7BC Clear When TM6IC 0 Don t clear 1 Clear Clear TM7BC synchronizing is 1 externally 4 TM7BC Clear TM7CA Reload When 7 7 while up counting 0 Don t clear TM7BC 1 Clear TM7BC Clear TM7BC when PWM is When 7 0 while down counting output 0 Don t reload TM7CA 1 ReloadTM7CA When TM7LP is 1 and up counting is selected 7 is 3 TM710OA Pin Output 0 RS F F output one phase PWM cleared to 0 on the next cycle if 1 T F F output two phase PWM TTB counts untl TIMES matches TM7CA or x FFFF x 5 When down counting is selected 2 0 Clock Source Selection 000 Timer 4 output TM7BC is set to TM7CA on the 001 Timer 5 output next cycle regardless of this bit 010 TM7IOB pin clock setting if TM7BC becomes O0 011 SYSCLK 100 Two phase encoder 4x of TM7IOA pin TM7IOB pin 101 Two phase encoder 1x of TM7IOA pin TM7IOB pin 11 Reserved Data Appendix IX 225 Chapter 9 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM7 7 TM7 TM7 TM7 7 7 TM7 7 7 TM7 TM7 7 7 TM7 TM7 BC15 BC14 BC13 BC12 BC11 BC10 BC8 BC6 BC5 BC4 BC2 BC1 BCO 01 01 01 0 1 0 1 0 1
55. 15 0 Timer 7 Count Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM7 7 TM7 TM7 7 7 7 TM7 7 TM7 7 TM7 7 7 TM7 TM7 CA15 CA14 13 12 10 CA9 CA6 CA5 CA4 CA2 CA1 CAO R W R W R W R W R W R W R W R W R W R W R W R W R W RW R W 01 01 01 01 01 01 0 1 0 1 0 1 15 0 Timer 7 Count Cycle Set the count cycle minus 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM7 7 TM7 TM7 7 7 7 TM7 7 TM7 7 TM7 7 TM7 TM7 TM7 CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 7 CB6 5 2 R W R W R W R W R W R W R W R W R W R W R W R W RW RW RW 01 01 15 0 Timer 7 PWM Change or Interrupt Generation IX 226 Appendix TM7BC 00 42 7 Counter 16 bit access register TM7BC is a read only register TM7CA x 00FE44 Timer 7 Compare Capture Register A 16 bit access register When capture is selected TM7CA reads the captured va
56. 9 8 7 6 5 4 3 2 1 0 OVR DIR END9 END8 END7 END6 END5 END4 END3 END2 END1 ENDO RW RW R RW R R RAW RW R W R W RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 o ot on 15 Enable 0 Disbale 1 Enable 14 Overrun Error Flag 0 No error 1 Error 13 ATC Transfer Direction 0 From serial ch 0 to Internal RAM 1 From Internal RAm to serial ch 0 9 0 ATC End Address Set the ATC end address IX 204 Data Appendix the lower 10 bits of the internal RAM area EXMCTR x 00FD00 External Memory Control Register 8 16 bit access register Setting a page size of ROM burst mode is invalid when ROM burst mode is disabled ATCCTR x 00FD10 ATC Control Register 8 16 bit access register The upper 14 bits are fixed at 00000000100000 because the internal RAM addresses for TC operation are x 008000 to x 0083FF Set the larger value than the ATCBC value Chapter 9 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATC B C BC9 BC8 BC7 6 5 BC2 BC1 BCO x 0 0 FD12 R R R R R R R W RW R W R W RW R W R W R W RW R
57. BC5 4 2 BC1 BCO R R R R R R R R 0 0 0 0 0 0 0 0 on T 0 Timer 4 Count Value 7 6 5 4 3 2 1 0 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BCO R R R R R R R R 0 0 0 0 0 0 0 0 01 0A 70 Timer 5 Count Value Chapter 9 Appendix x OOFEO3 Timer 3 Binary Counter 8 bit access register 16 bit access is possible from even address is a read only register TM4BC 00 4 Timer 4 Binary Counter 8 16 bit access register is read only register TM5BC x 00FEO05 Timer 5 Binary Counter 8 bit access register 16 bit access is possible from even address 5 is a read only register Data Appendix IX 217 Chapter 9 Appendix TMOBR TMO TMO TMO TMO TMO TMO TMO TMO BR7 BRS BR2 BR1 BRO x 00 1 0 R W R W R W R W R W RW RW R W Timer 0 Base Register 0 0 0 0 0 0 0 0 04 0 1 01 8 16 bit access register 7 0 Timer 0 Count Cycle Set the count cycle 2 to 256 Timer 0 TMOBR is set to 0 after timer 0 counts the set value plus 1 The valid starts See 4 2 8 bit Timer range for TMOBR is 0 to 255 Setup Examples for details
58. Chapter 4 Timers Counters 10 Set both TM1LD and TM1EN of the TM1MD register to O If this setting is omitted the timer 0 binary counter may not start at the first cycle 11 Set TM1LD and TM1EN to 0 and 1 respectively This starts timer 1 Count ing starts at the beginning of the next cycle When the TM1BC value reaches 0 TM1IO output is inverted as soon as the value of 2 from the timer 1 base register is loaded Immediately after TM1BC starts counting the TM1IO output pin outputs 0 The output pin outputs 1 at the beginning of the next cycle when TM1BC becomes 0 Then the TM1IO output pin outputs O again at the beginning of the next cycle This repeated operation results in 12 clock cycles SYSCLK TMOBR TMOBC TMO Output TM1BR TM1BC TM11O Output Procedure IV 84 8 bit Timer Setup Examples 00 01 00 01 00101100 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 i i 4 i 4 a 02 00 02 01 00 02 01 00 02 3 4 5 6X7 8 9 10 11 Figure 4 2 3 Clock Output Timing 4 2 3 Interval Timer Using 8 bit Timer The interval timer setup procedures for timer O to timer 5 are same In this example timer O timer 2 and timer 3 generate an interrupt at regular intervals 1 second To divide SYSCLK by 10 000 00
59. F7 B0 An lt lt 2 Am d16 l d16 h MOV d24 An Am mem24 An d24 gt Am 5 4 F4 F0 An lt lt 2 Am d24 l d24 m d24 h MOV abs16 An mem24 abs16 An 4 3 F7 30 An abs16 l abs16 h MOV abs24 An 24 6524 5 4 F4 D0 An abs24 l abs24 m abs24 h MOV Dm mem16 An 1 1 00 An lt lt 2 Dm MOV Dm d8 An Dm gt mem16 An d8 2 1 40 An lt lt 2 Dm d8 MOV Dm d16 An Dm mem16 An d16 4 2 F7 80 An lt lt 2 Dm d16 l d16 h MOV Dm d24 An Dm mem16 An d24 5 3 F4 00 An lt lt 2 Dm d24 d24 m d24 h Dm Di An Dm mem16 An Di 2 2 F1 C0 Di lt lt 4 An lt lt 2 Dm MOV Dn abs16 Dn mem16 abs16 3 1 C0 Dn abs16 l abs16 h MOV Dn abs24 1 6 abs24 5 3 F4 40 Dn abs24 l abs24 m abs24 h MOV 24 2 2 50 lt lt 2 00 3 MOV 48 24 8 2 2 50 An lt lt 2 Am d8 MOV Am d16 An 24 16 4 3 F7 A0 An lt lt 2 Am d16 l d16 h Am d24 An 24 424 5 4 4 10 lt lt 2 24 424 24 An abs16 gt 24 0516 4 3 F7 20 An abs16 l abs16 h MOV An abs24 An mem24 abs24 5 4 F4 50 An abs24 l abs24 m abs24 h imm8 Dn imm8 Dn S 2 1 80 Dn lt lt 2 Dn imm8 MOV imm16 Dn imm16 Dn S 3 1 F8 Dn imm16 l imm16 h MOV imm24 Dn imm24 Dn 5 3 F4 70 Dn imm24 l imm24 m imm24 h MOV imm16 An imm16 An 0 3 1 DC An imm16 l imm16 h MOV imm24 An imm24 An 5 3 F4 74 An imm24 l
60. FLOATING CSn 1 FLOATING RE FLOATING FLOATING mm WAIT BRACK Bus Master CPU 22 External Device ai CPU Figure 2 2 16 Access Timing during Bus Request Address Data Shared Mode II 54 External Memory Connection Example Chapter 3 Interrupts Chapter 3 Interrupts III 56 3 1 Interrupt Groups 3 1 1 Overview The interrupt controller contains eight groups Each group has some interrupt vectors When an interrupt occurs the CPU receives an interrupt request t Reserved A corresponding flag does not actually exist Qm IOoO nNouo o nouo o nuo o nouo o n OoO mcoj jo mnmoio Interrupt Groups MN102L Series LSI User s Manual Table 3 1 1 List of Interrupt Control Registers Interrupt Vector Interrupt Group Number is IDTn bit position Control Register Undefined Instruction Interrupt Watchdog Timer Interrupt NMI Interrupt Reserved Timer Counter 5 Underflow Timer Counter O Underflow External Interrupt IRQO Reserved A D Conversion End Timer Counter 1 Underflow External Interrupt IRQ1 Serial Ch0 Reception End Serial Ch0 Transmission End Timer Counter 2 Underflow External Interrupt IRQ2 Serial Ch1 Reception End Serial Ch1 Transmission End Timer Counter 3 Underflow External Interrupt IRQ3 Reserved Set the corresponding enable flag always to 0 Reserved Set the corresponding enable flag always to 0 Timer Counter 4 Underflow
61. IN6 IN5 INA IN3 IN2 INA INO x OOFFD8 8 Port Port Port Port Port Port Port Port 01 01 Register 8 16 bit access register 7 0 Port 8 Input 7 6 5 4 3 2 1 0 P9IN P9 P9 P9 P9 P9 P9 IN6 IN5 INA IN3 IN2 INA INO x 00FFD9 GE GE Port 9 Input Port Port Port Port Port Port Port Port 0 1 01 Register 8 bit access register 16 bit access is possible 7 0 Port 9 Input from even address Data Appendix 235 Chapter 9 Appendix 7 6 5 4 3 2 1 0 PAI N NMI PA PA PA PA PA 5 INA INO x OOFFDA RR IR Port A Input 0 NMI Port Port Port Port Port Port 0 01 01 04 0 1 Register 8 bit access register 16 bit access is possible 5 0 Port A Input from even address Bit 6 is the level of NMI pin 7 6 5 4 3 2 1 0 PODIR NE 4 x OOFFEO RJR BR RW Port 0 Input Output 0 0 0 0 0 0 0 0 o lo o Control Register 8 16 bit access register 0 All Pin Input Output of Port 0
62. IV 66 Timers Table 4 1 1 Timer Function 2 2 Chapter 4 Timers Counters Timer 8 bit Timer 16 bit Timer Function Timer 4 Timer 5 Timer 6 Timer 7 Interrupt Request Destination Group 5 G5ICR Group 1 G1ICR Group 6 G6ICR Group 7 G7ICR TM4IR TMSIR TM6UIR TM7UIR TM6AIR TM7AIR TM6BIR TM7BIR Interrupt Source Timer 4 underflow Timer 5 underflow Timer 6 underflow Timer 6 compare or capture A match Timer 6 compare or capture B match Timer 7 underflow Timer 7 compare or capture A match Timer 7 compare or capture B match Clock Source TM4IO pin Timer 3 Timer 0 fxi 4 TMBIO pin Timer 4 Timer 0 4 SYSCLK Timer 4 Timer 5 TM6IOB Two phase encoder SYSCLK Timer 4 Timer 5 TM7IOB pin Two phase encoder Counting Method Down counting Down counting Up Down counting Up Down counting Interval Timer 9 Event Counter 9 Timer Output 9 PWM z Arbitrary duty Arbitrary duty Two phase Timer Output E One shot Pulse Output 9 One phase Capture Input Two phase Capture Input Two phase Encoder 4x 4x External Count Direction Control 9 External Count Reset Control i Serial Interface Transfer Clock Genera 5 7 tion A D Conversion Timing Genera
63. Note Note Note Note Note Buffer 01 Note Undefined 8 16 bit access register 7 0 A D Conversion Result of Ch 2 AN2 Pin AN2BUF is a read only buffer Data Appendix IX 213 Chapter 9 Appendix 6 5 4 3 2 1 0 AN3BUF AN3 AN3 AN3 AN3 AN3 AN3 AN3 AN3 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUFO x 00FDAB LZ A D 3 Conversion Data Note Note Note Note Note Note Note Note Buffer 01 01 01 01 01 01 0 1 Note Undefined 8 bit access register 16 bit access is possible 7 0 A D Conversion Result of Ch 3 Pin from even address AN3BUF is a read only buffer 7 6 5 4 3 2 1 0 A N 4 B U F AN4 AN4 AN4 ANA AN4 AN4 ANA AN4 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUFO x OOFDAC A D 4 Conversion Data Note Note Note Note Note Note Note Buffer 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note Undefined 8 16 bit access register 7 0 Conversion Result of Ch 4 ANA Pin is a read only buffer 7 6 5 4 3 2 1 0 A N 5 B U F AN5 ANB AN5 AN5 AN5 AN5 AN5 AN5 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUFO x OOFDAD A D 5 Conversion Data Note Note
64. PanaNSeries TheOnetoWatch for Constant Innovation Making the Future ComeAlive MICROCOMPUTER MN102L MN102L610B F61G LSI User s Manual Pub No 22261 011E Panasonic PanaX Series is a trademark of Matsushita Electric Industrial Co Ltd The other corporation names logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations 1 2 3 4 5 Request for your special attention and precautions in using the technical informaition and semiconductors described in this book An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the Foreign Exchange and Foreign Trade Law is to be exported or taken out of Japan The contents of this book are subject to change without notice in matters of improved function When finalizing your design therefore ask for the most up to date version in advance in order to check for any changes We are not liable for any damage arising out of the use of the contents of this book or for any infringement of patents or any other rights owned by a third party No part of this book may be reprinted or reproduced by any means without written permission from our company This book deals with standard specification Ask for the latest individual Product Standards or Specifications in advance for
65. Port Port Port Port 0 1 0 1 01 7 0 Port 0 Input 7 6 5 4 3 2 1 0 P1 P1 P1 P1 P1 P1 P1 P1 ING IN5 INA INS IN2 IN1 INO R R R R R R R R Port Port Port Port Port Port Port Port 0 1 0 1 01 7 0 Port 1 Input 7 6 5 4 3 2 1 0 P2 P2 P2 P2 P2 P2 P2 P2 ING IN5 INA INS IN2 INA INO R R R R R R R R Port Port Port Port Port Port Port Port 0 1 7 0 Port 2 Input Chapter 9 Appendix POIN x 00FFDO Port 0 Input Register 8 16 bit access register x OOFFD1 Port 1 Input Register 8 bit access register 16 bit access is possible from even address P2IN x 00FFD2 Port 2 Input Register 8 16 bit access register Data Appendix IX 233 Chapter 9 Appendix 7 6 5 4 3 2 1 0 IN6 IN5 INA IN3 IN2 INA INO R R R R R R R R Port Port Port Port Port Port Port Port 01 01 01 7 0 Port 3 Input 7 6 5 4 3 2 1 0 P4 IN5 INA INA INO R R R R R R R R Port Port Port Port Port Port Port Port 01 01
66. Recommend to write x 0410 to MEMCTR INIT In the program the following sym bols and register addresses are equivalent Amemctr x FC02 x FC30 x FC32 2 x FC34 x FC36 IX 260 Initialization Program 9 5 Initialization Program After reset the initialization program must be located in the CS0 area x 010000 to x 3FFFFF In the initialization program set the number of wait cycles for Block 0 to the MEMMDO register Next set the MEMCTR register Always set bits 8 0 of the MEMCTR register to 100 The number of wait cycles set the MEMMDO register is valid after setting the MEMCTR register Initialization Program int equ Memory Mode Setting for Block 0 mov 00 mov d0 Amemmd0 Handshake Mode Setting mov 00 mov dO Amemctr Pin Setting in Memory Expansion Mode or Processor Mode mov PO1M 00 mov d0 Ap01md mov PO1D INIT dO mov dO ApOtdir mov P23M 00 mov d0 Ap23md mov P23D INIT dO mov dO Ap23dir mov 45 0 mov d0 Ap45md mov P45D INIT dO mov dO Ap45dir mov P6M INIT dO movb dO Ap6md mov P6D 0 movb d0 Ap6dir Memory Mode Setting for Block1 Block2 Block 3 mov 00 mov d0 Amemmd1 mov 2 00 mov d0 Amemmd2 mov 00 mov dO Amemmd3
67. VIII 160 Byte Swap Registers Chapter 9 Appendix 9 Chapter 9 Appendix IX 162 Electrical Characteristics 9 1 Electrical Characteristics 9 1 1 Electrical Characteristics 5 V CMOS integrated circuit Application General purpose 16 bit microcontroller Pin Configuration Figure 1 4 1 External Dimensions Figure 1 5 1 A Absolute Maximum Ratings VSS 0 V Power supply tagel Voo 0 3 to 7 0 Input pin voltage 0 3 to Vpp 0 3 out pin voltage 0 3 to Vpp 0 3 voltage 5 Operating ambient Topr 40 to 85 C temperature A6 Storage temperature 55 to 125 Note 1 Absolute Maximum Ratings are stress ratings not to cause damage to the device Operation at these ratings is not guaranteed 2 Al ofthe VDD and Vss pins are external pins Connect them directly to the power source and ground 3 To prevent latch up tolerance connect more than one by pass condenser between power supply pins and ground Use atleast 0 2 mF condenser Chapter 9 Appendix B Operating Conditions 0 V 40 C to 85 Capacitance Parameter Conditions Crystal Oscillator 1 OSCI il lo eget Crystal Oscillator 2 XI Oscillator frequency Fosc2 MN102L610B does not B Flash Programming Operating Conditions contain flash memory Vss 0 V 0 C to 70 Capacitance Parameter Symbol Conditions Power supply voltage During programming 5 5 4 Byte write VDD 5 0 V T 25 C
68. be fore TM6BC starts counting Therefore to load the TM6CA value to TM6CBX write the dummy data to TM6CBX The dummy data can be any values TM6CBX x 00FE3A 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 TM6 TM6 TM6 TM6 CBX15 CBX14 CBX13 CBX12 11 10 CBX9 CBX8 CBX7 CBX6 5 4 CBX3 CBX2 1 CBXO The setup steps after step 6 are the same as steps 5 and 6 in 4 3 1 Event Counter Using 16 bit TM6EN TM6BC 01010101234012340123 k k k k k k k k k k k k k k TM6CA 0004 TM6CB 0001 meo LLL TM6IOB rL 26 Loa 1 Figure 4 3 4 Two phase PWM Timing Chapter 4 Timers Counters When timer n changes the duty of PWM output waveforms dynamically the PWM output waveforms and interrupts may corrupt at the timing of changing the TMnCB value in the single buffer mode In the double buffer mode the corrupt of PWM output waveforms and interrupts does not occur at any timing of changing the TMnCB value This corruption does not occur even when the output waveforms consist of 1 and 0 TMnEN TMnCB Write TMnBC 0 1 2 3 4 1 2 3 4 0
69. mem24 A3 An gt PC 0 01 lt lt 2 PC 1 PC mem24 A3 gt PC 4 mem16 A3 gt PSW mem24 A3 2 gt PC A346 A3 Reading the instruction set Symbols used in tables Dn Dm Di An Am MDR PSW PC imm8 imm16 imm16 l imm16 h imm24 imm24 l imm24 m imm24 h d8 416 d16 l d16 h 924 d24 l d24 m d24 h abs16 abs16 l abs16 h abs24 abs24 l abs24 m abs24 h mem8 abs16 mem8 abs24 mem16 An mem16 abs16 mem16 abs24 24 mem24 abs16 mem24 abs24 bp Isb msb 8 1 lt lt VX CX NX ZX VF CF NF ZF temp OP EX Operand Extensions 0 Zero extension S Sign extension Not applicable Cycle Minimum cycle count is shown Units machine cycles a b acycles if branch taken b cycles if branch not taken Notes Ver 2 2 2002 03 31 Data register Address register Multiply Divide Register Processor Status Word Program Counter Constant Displacement Absolute address 8 bit memory data which is determined by the address inside parentheses 16 bit memory data which is determined by the address inside parentheses 24 bit memory data which is determined by the address inside parentheses Bit specification Logical AND logical OR exclusive OR Bit inversion bit shift Extended overflow flag carry flag negative flag zero flag 24 bit data Over
70. to either 8 bit data bus width or 16 bit data bus width in processor mode or memory expan sion mode Bus width of internal ROM RAM and special function registers are always 16 bit width Setting this pin to L level selects 16 bit data bus width and Setting this pin to level selects 8 bit data bus width In processor mode and memory expansion mode always use this pin as data bus width input pin If bus width is changed during operation proper operation is not guaranteed 1 14 Pin Description Chapter I Overview Table 1 4 1 List of Pin Functions 3 9 Pin Name Input Output Shared Pin Function Description P54 I O BREQ General purpose Port 5 These pins can be used as general purpose in Input Bus request put output ports Chapter 8 Ports BREQ P55 I O BRACK General purpose Port 5 and BRACK pins operate bus arbitration Pull Output Bus request enable ing low suspends the execution of the output current instruction releases bus and sets BRACK to L level While the chip is accessing the bus the chip releases the bus after the bus access is completed and sets BRACK to L level Pulling BREQ high at the level detector restores the bus Chapter 2 2 2 Example of External Memory Connection P62 Em General porpose These pins can be used as general purpose in Output WEL Lower Byte Write put output ports Chapter 8 Ports Enable Output T
71. 21 22 OSCI J 23 OSCO 24 50 50 4 gt 5 P52 CS2 c7 P53 CS3 lt 8 WORD P20 A00 P54 BREQ 9 P22 A02 lt P23 A03 lt P60 WAIT lt 1 51 51 lt 6 P55 BRACK P56 BSTRE lt P21 A01 Figure 2 1 4 Memory Expansion Mode Address Data Separated Pin Configuration II 28 Bus Interface PAO IRQO lt PA1 IRQ1 lt gt PA2 IRQ2 lt PA3 IRQ3 lt 4 4 MN102LF61G L610B gt TOP VIEW s 100 LQFP 9565099 eo e D on o oH gt gt 5883 Bee hao eg P258 000000 dmmmummmo2z22202222220222 z gt lt lt lt lt 4 gt OWN aar SVRRRKRO OOo 889598805845 885 76 50 77 49 78 48 79 47 80 46 81 45 82 44 83 43 84 42 85 41 lt lt TM21O P82 TM1IO P81 gt TMOIO P80 A23 WDOUT AN7 P47 22 5 6 46 A21 A20 lt Vss 19 A18 A17 A16 4 8 P37 a P36 __ P35 lt gt P34 P33 4 P32 lt P31 30 P27 26 P25 P24 100 26
72. Chapter 4 Timers Counters b Data Bus 8 8 8 00 12 Timer 2 Base Register TM2BR Reload gt 8 4 Serial I F 00 02 Controller Timer 2 Binary Counter mn t nterrup z Controller Underflow got Timer 2 cascade signal Y 1 2 Y Reset 2 pin 2 pin 0 Timer 1 cascade 1 Timer 0 2 SYSCLK 3 Selector Figure 4 1 16 Timer 2 Block Diagram Data Bus 8 8 8 x 00FE13 Timer 3 Base Register TM3BR Reload alt Serial x 00FE03 Controller E Timer 3 Binary Counter ini m TM3BC nterrup z Underflow Controller Count Timer 3 cascade signal Y gt 1 2 Reset TM3IO TMSIO 0 Timer2cascade 1 Timer 0 2 SYSCLK 3 Selector Figure 4 1 17 Timer 3 Block Diagram IV 76 Timers Data Bus 8 8 00 14 Timer 4 Base Register TM4BR Reload x00FE04 Timer 4 Binary Counter AL Underflow Interrupt Controller TM4BC zum
73. Fosc1 22 6 MHz E2 external clock input high pulse width 2 External clock input low pulse width Fig 9 1 2 Reset Input Timing IX 172 Electrical Characteristics Chapter 9 Appendix Vp 4 5 V to 5 5 V Input Timing Conditions Vss 0 V 40 C to 85 Capacitance Parameter Symbol Conditions Unit Ie Data Transfer Signal Input Timing Data acknowledge signal setup time WAIT Data acknowledge signal hold time WAIT Data Transfer Signal Input Timing Read data setup time D15 00 E10 Read data hold time D15 00 Bus Authority Request Input Timing Bus authority request signal setup time BREQ Bus authority request signal hold tonen E12 rime BREQ Interrupt Signal Input Timing Nonmaskable interrupt signal t pulse width NMI Fig 9 9 14 External interrupt signal pulse t width IRQ4 0 Note An interrupt may occur when the noise of the specified time or less is input Electrical Characteristics IX 173 Chapter 9 Appendix Vpp 4 5 V to 5 5 V Input Timing Conditions Vss 0 V Ta 40 C to 85 C Capacitance Parameter Symbol w Unit HEIE Serial Interface Related Signal Timing Synchronous Serial Reception E16 Data reception hold time SBI1 0 25 ns Fig 9 13 Serial clock input high pulse width E17 1 EET tscu 100 ns Timer Counter Signal Input Timing Timer external input clock low E19 pulse
74. Laguna 4026 PHILIPPINES Tel 63 2 520 8615 Fax 63 2 520 8629 India Sales Office National Panasonic India Ltd NPI E Block 510 International Trade Tower Nehru Place New Delhi 110019 INDIA Tel 91 11 629 2870 91 11 629 2877 e Indonesia Sales Office P T MET amp Gobel M amp G JL Dewi Sartika Cawang 2 Jakarta 13630 INDONESIA Tel 62 21 801 5666 _ Fax 62 21 801 5675 Sales Office Panasonic Industrial Shanghai Co Ltd PI SH Floor 6 Zhong Bao Mansion 166 East Road Lujian Zui PU Dong New District Shanghai 200120 CHINA Tel 86 21 5866 6114 86 21 5866 8000 Panasonic Industrial Tianjin Co Ltd PI TJ Room No 1001 Tianjin International Building 75 Nanjin Road Tianjin 300050 CHINA Tel 86 22 2313 9771 Fax 86 22 2313 9770 Panasonic SH Industrial Sales Shenzhen Co Ltd PSI SZ 107 International Bussiness amp Exhibition Centre Futian Free Trade Zone Shenzhen 518048 CHINA Tel 86 755 359 8500 86 755 359 8516 Panasonic Shun Hing Industrial Sales Hong Kong Co Ltd PSI HK 11th Floor Great Eagle Center 23 Harbour Road Wanchai HONG KONG Tel 852 2529 7322 Fax 852 2865 3697 e Taiwan Sales Office Panasonic Industrial Sales Taiwan Co Ltd PIST Head Office 6F 550 Sec 4 Chung Hsiao E RD Taipei 110 TAIWAN Tel 886 2 2757 1900 886 2 2757 1906 Kaohsiung Office 6th Floor Hsin Kong Bldg No 251 Chi Hsien 1st Road Kaohsiung 800 TAIWAN Tel
75. NORTH AMERICA U S A Sales Office Panasonic Industrial Company PIC New Jersey Office Two Panasonic Way Secaucus New Jersey 07094 U S A Tel 1 201 348 5257 1 201 392 4652 Chicago Office 1707 Randall Road Elgin Illinois 60123 7847 U S A Tel 1 847 468 5720 1 847 468 5725 Milpitas Office 1600 McCandless Drive Milpitas California 95035 U S A Tel 1 408 942 2912 1 408 946 9063 Atlanta Office 1225 Northbrook Parkway Suite 1 151 Suwanee GA 30024 U S A Tel 1 770 338 6953 1 770 338 6849 San Diego Office 9444 Balboa Avenue Suite 185 San Diego California 92123 U S A Tel 1 619 503 2903 1 858 715 5545 e Canada Sales Office Panasonic Canada Inc PCI 5770 Ambler Drive 27 Mississauga Ontario LAW 2T3 CANADA Tel 1 905 238 2101 Fax 1 905 238 2414 LATIN AMERICA e Mexico Sales Office Panasonic de Mexico S A de C V PANAMEX Amores 1120 Col Del Valle Delegacion Benito Juarez C P 03100 Mexico D F MEXICO Tel 52 5 488 1000 Fax 52 5 488 1073 Guadalajara Office SUCURSAL GUADALAJARA Av Lazaro Cardenas 2305 Local G 102 Plaza Comercial Abastos Col Las Torres Guadalajara Jal 44920 MEXICO Tel 52 3 671 1205 OG Brazil Sales Office Panasonic do Brasil Ltda PANABRAS Caixa Postal 1641 Sao Jose dos Campos Estado de Sao Paulo Tel 55 12 335 9000 Fax 55 12 331 3789 EUROPE OG Europe Sales Office Panasonic Industrial Europe GmbH PIE U K Sa
76. PC F CX ZX 0 PC 3 PC F5 E7 d8 BCCX label F CX 0 PC 3 d8 label F CX 1 PC 3 PC F5 E6 d8 BHIX label F CX ZX 0 PC 3 d8 label gt PC F CX ZX 1 3 gt F5 E5 d8 BVCX label F VX 0 PC 3 d8 label gt PC F VX 1 F5 EC d8 BVSX label F VX 1 PC 3 d8 label gt PC F VX 0 3 F5 ED d8 BNCX label F 0 PC 3 d8 label NX 1 3 gt F5 EE d8 BNSX label F NX 1 F NX 0 3 PC 3 d8 label gt PC F5 EF d8 Notes IX 254 JMP label16 PC 3 d16 label16 PC FC d16 I d16 h JMP label24 PC 5 d24 label24 PC F4 E0 d24 1 d24 m d24 h JMP An 33 src gt dest 734 src2dest 735 srcxdest 36 src dest 737 src gt dest 738 src2dest 89 srcxdest 40 src dest 41 VX 0 42 VX 1 43 NX 0 44 NX 1 An gt PC 24 bits signed 24 bits signed 24 bits signed 24 bits signed 24 bits unsigned 24 bits unsigned 24 bits unsigned 24 bits unsigned Instruction Set FO An lt lt 2 Instruction Mnemonic Operation JSR label16 A3 4 A3 3 24 PC 3 d16 label16 gt PC Chapter 9 Appendix Machine Code FD d16 I d16 h JSR label24 4 gt PC 5 mem24 A3 PC 5 d24 label24 PC F4 E1 d24 1 d24 m d24 h PC 2
77. SO 0 0 0 0 0 0 1 1 0 0 0 0 1 1 TM7CA is captured on the rising edge of TM7IOA and TM7CB is captured on the rising edge of TM7IOB The setup steps after step 2 are the same as steps 3 to 7 in 4 3 4 One phase Capture Input Using 16 bit Timer The Figure 4 3 7 shows 000A 0007 0003 or 3 cycles Chapter 4 Timers Counters TM7EN 40 ee 2 TM7BC 001 213 4 5 6 7 8 9 E F 1011 12 SYSCLK io J TM7CB io og i TM7IOA JMN 19002022202 A ibl Clm 00 o iut unc MO Ode d Interrrupts ara a i i du SG 3 Cycles Figure 4 3 7 Two phase Capture Timing 16 bit Timer Setup Examples 99 Chapter 4 Timers Counters Use the MOV instruction to set the data and always use 16 bit write operations Stop TM7BC counting and initial ize clear TM7BC and RS F F IV 100 16 bit Timer Setup Examples 4 3 6 Two phase Encoder Input Using 16 bit Timer 4x The two phase encoder input setup procedures for timer 6 and timer 7 are same In this example timer 7 inputs the two phase encoder 4x and counts up down An interrupt occurs when the TM7BC reaches the set value m Interrupt Enable Setup 1 Enable interrupts At the sam
78. 01 Hi Z at A01 15 P22 A02 CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Zat A02 Hi Z at A02 16 P23 A03 TIL CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Zat A03 Hi Z at A03 18 SYSCLK CMOS No High High High 4 20 X 21 XO High EE High EE High EE 4 22 VDD 23 OSCI 24 OSCO High EE High EE High EE 5 25 MODE 5 Yes No High Input Low Input Low Input MODE MODE 26 P24 A04 CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Zat A04 Hi Zat A04 27 P25 A05 CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Zat A05 Hi Zat A05 28 P26 A06 TIL CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Zat A06 Hi Z at A06 29 P27 A07 CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Zat A07 Hi Zat A07 30 P30 A08 TIL CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Zat A08 Hi Z at A08 31 P31 A09 CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Zat A09 Hi Z at A09 32 P32 A10 CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Zat A10 Hi Zat A10 33 P33 A11 CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Zat A11 Hi Zat A11 34 VDD 35 P34 A12 CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Z at A12 Hi Z at A12 36 P35 A13 TIL CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Zat A13 Hi Zat A13 37 P36 A14 CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Zat A14 Hi Zat A14 38 P37 A15 TIL CMOS Yes Programmable Hi Z Hi Z Hi Z Hi Zat A15 Hi Zat A15 39 P40 A16 CMOS Yes Programmable Hi Z Hi Z Undefined Hi Z at A16 Hi Z at A
79. 12 11 10 9 8 7 6 5 4 3 2 1 0 GN4 GN3 GN2 GN1 GNO RI RI RI RJ RI R R R R R RY RIR 0 0 0 0 0 0 0 0 0 0 0 51 Group Number of Accepted Interrupt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WAIT WAIT 1 0 R R R R R R R RW R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Wait Cycle Block 0 00 No Wait 01 1 Wait Cycle 10 2 Wait Cycles 11 Handshake Chapter 9 Appendix IAGR x 00FCOE Interrupt Accept Group Register 8 16 bit access register IAGR is a read only register MEMMDO x 00FC30 Memory Mode Control Register 0 16 bit access register Set any values when block 0 is unused Data Appendix IX 193 Chapter 9 Appendix 15 14 13 12 11 10 9 7 6 5 4 3 2 1 RESHT BMOD WAIT WAIT 1 0 RW R R 0 0 0 0 0 0 0 0 0 0 0 0 0 fon on 15 Block 1 RE pulse width 0 Disable shortening 1 Enable 8 Bus Mode for Block 1 0 16 bit Bus Mode 1 8 bit Bus Mode 1 0 Wait Cycle for Block 1 00 No Wait 01 1 Wait Cycle 10
80. 12 11 10 9 8 7 5 4 2 1 0 HSWT NWAIT WAIT ARB WAIT WAIT WAIT WAIT WAIT IOE IOE SET SZ IO1 IO0 2 1 0 RI R R R R RW R RW RW R RW 0 0 0 0 0 1 1 1 0 0 1 1 0 1 1 1 0 0 0 0 O01 0 1 10 Peripheral Fixed Wait Cycle 0 No Wait Enable Flag 1 Peripheral Fixed Wait Cycle During Handshake Mode Always set 1 in this series 9 Peripheral Fixed Wait Cycle Enable Flag 0 Enable 1 Disable Always set 0 in this series 8 Fixed Wait Mode Handhsake 0 Handshake Mode Mode Switch 1 Fixed Wait Mode Always set 0 in this series 7 Bus Width Setup Flag 0 Based on WORD pin for Fixed Area x 040000 to 1 8 bit Bus Access regardless of x 07FFFF WORD pin 5 4 Peripheral Fixed Wait Cycle 00 No wait 01 1 wait cycle 10 2 wait cycles 11 3 wait cycles Always set 01 in this series 2 0 Fixed Wait Cycle 000 No wait cycle 001 1 wait cycle 010 2 wait cycles 011 3 wait cycles 100 4 wait cycles 101 5 wait cycles 110 6 wait cycles 111 7 wait cycles Don t care in this series 192 Data Appendix MEMCTR x 00FCO2 Memory Control Register 16 bit access register Q In this series set MEMCTR to x 0410 or x 0490 15 14 13
81. 2 1 0 RESHT BSMOD WAIT WAIT 1 0 RE pulse width shortening 0 1 2 WAIT cycle 1 1 4 WAIT cycle The MEMMDS register sets the wait cycles and bus mode for Block 00 6 15 14 13 12 11 10 9 8 7 6 2 1 0 RESHT BSMOD WAIT WAIT 1 0 TU RE pulse width shortening 0 1 2 cycle 1 1 4 WAIT cycle Wait Cycle Setting for Block 2 00 None 01 1 cycle 10 2 cycles 11 Handshake Bus Width Setting for Block 2 0 16 bit Bus Width 1 8 bit Bus Width Wait Cycle Setting for Block 3 00 None 01 1 cycle 10 2 cycles 11 Handshake Bus Width Setting for Block 3 0 16 bit Bus Width 1 8 bit Bus Width II 33 Bus Interface Chapter 2 Bus Interface 2 See 2 1 3 ROM Burst Mode Timing for the penalty availability of burst mode ROM burst mode without penalty is not allowed dur ing processor mode 1 Setting the WESHT bit to 1 makes the rising edge of WEH and WEL 1 4 cycle 25 ns with a 20 MHz oscillator forward and the hold time of address data longer 34 Bus Interface EXMCTR x 00FD00 The EXMCTR register sets the burst mode for ROM the polarity of ALE signal during the address data shared mode and the pulse width of WEH signal and WEL signal WE SHT NALE EN BREN ROM Burst Mode 2 00 Disable 01 Reserved 10 Enable Witho
82. 250000 250000 00 Available with Timer 0 in case of the divisor of 256 or greater Table 5 1 8 Baud Rate Setup Example in Asynchronous Mode External Oscillator at 12 MHz Baud Rate Divisor Real Time 1200 1201 92 2400 2403 85 4800 4807 69 9600 9615 38 19200 18750 00 28800 28846 15 31250 31250 00 38400 37500 00 48000 46875 00 57600 53571 43 76800 75000 00 153600 125000 00 187500 187500 00 Available with Timer 0 in case of the divisor of 256 or greater Table 5 1 10 Baud Rate Setup Example in Asynchronous Mode External Oscillator at 8 MHz Real Time 1201 92 2403 85 4807 69 9615 38 19230 77 27777 78 31250 00 35714 29 50000 00 62500 00 83333 33 125000 00 Serial Interface 115 Chapter 5 Serial Interface Setting timer is required during se rial reception in asynchronous mode V 116 Serial Interface Setup Examples 5 2 Serial Interface Setup Examples 5 2 1 Serial Transmission in Asynchronous Mode Using Timer 2 This section describes the example of serial interface 0 transmission asynchronous mode with the following settings 20 MHz oscillation Baud Rate 9600 bps SYSCLK 65 by timer 2 Bit Order LSB 8 bit data transfer Two stop bits Odd The next data is transmitted when a transmission end interrupt oc Curs Serial Interface 8 bit Timer eee Divicer PEREN 2 Divided by 65 Div
83. 5 4 3 2 1 0 _ 61 G1 5 TMO IRQO TM5 IRQO 5 TMO IRQO LV2 LV1 IE IE IR IR ID ID ID Group interrupt level Interrupt enable Interrupt demand flag Interrupt detective IENn IRFn flag Setup of interrupt level Setup of interrupt Occurrence of IDTn permission interrupt factor Detection of interrupt demand Please refer to 2 5 Interrupt Controller in the MN102L Series LSI User s Manual for detail operations and the MN102L Series Instruction Manual for interrupt han dling flow and handler programming Set the interrupt enable flags IEN 3 2 bits 11 10 of the G7ICR always to O Interrupt Groups 1 57 Chapter 3 Interrupts III 58 External Interrupts 3 2 External Interrupts 3 2 1 External Pin Interrupts Group 1 to Group 5 control external pin interrupts The EXTMD register sets the interrupt conditions The EXTMD register sets the interrupt levels and timing of external interrupts and specifies each pins level or edge EXTMD x 00FC56 15 14 13 12 11 10 9 8 7 6 5 4 3 2 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0 TGO TG1 TGO TG1 TGO TG1 TGO TG1 TGO EIRQ4 EIRQ3 EIRQ2 ElRQ1 EIRQ0 00 An interrupt occurs at low level 01 An interrupt occurs at high level 10
84. 501 1 TBSY RBSY SPS STS FE OE R R R 0 0 0 0 0 0 0 1 7 Transmission Busy Flag 6 Reception Busy Flag 5 PC Stop Sequence Detect 4 Received Data 3 PC Start Sequence Detect 2 Framing Error 1 Parity Error 0 Overrun Error 0 Transmission in progress 0 Ready to transmit Ready to receive Reception in progress Undetected 1 Detected No received data Received data Undetected Detected No error Error No error Error No error Error Chapter 9 Appendix SC1STR x 00FD93 Serial 1 Status Register 8 bit access register 16 bit access is possible from even address A framing error occurs when the stop bit is 0 Framing error data is updated whenever the stop bit is received A parity error occurs when the parity bit is 1 although it is set to 0 when the parity bit is O al though itis setto 1 when the par ity bit is odd although it is set to even and when the parity bit is even although it is set to odd Parity error data is updated whenever the parity bit is re ceived An overrun error occurs when the next data is received com pletely before the CPU reads the received data SC1TRB Over run error data is updated when ever the last data bit seventh or eighth bit is received Data Appendix IX 211 Chapter 9 Appendix
85. 7 capture B oc curs W Timer 7 Setup 2 Set the operating mode to the timer 7 mode register TM7MD Verify that counting is stopped and an interrupt is disabled Select up counting or down counting Set TM7LP to 0 to count the loop of 0 to x FFFF Select SYSCLK as the timer 7 clock source TM7MD 40 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM7 TM7N TM7 7 7 7 7 7 7 7 7 7 7 7 EN LD UD1 UDO TGE ONE MD1 MDO ECLR LP ASEL 52 51 SO 0 0 i 0 0 0 0 1 0 0 0 0 0 1 1 3 Set TM7NLD and TM7EN of the TM7MD register to 1 and 0 respectively This enables TM7BC T F F and RS F F 4 Set both TM7NLD and TM7EN to 1 This starts the timer 7 Counting starts at the beginning of the next cycle Compare Capture Register Setup 5 When TM7MD 1 0 10 the capture is selected TM7CA and TM7CB are reserved for read operations When setting TM7CA and TM7CB is required first set TM7MD 1 0 to 00 TM7CA x 00FE44 TM7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 CA15 CA14 CA13 CA12 11 10 CA9 CA8 CA6 5 CA4 2 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 CB15 CB14 CB13 CB12 1
86. A10 A09 gt A07 A06 05 A04 RE 12 4 50 lt 5 51 6 52 4 17 A00 lt 113 01 24 14 XO lt _ 21 22 OSCI 23 OSCO 24 CS3 4 3 8 P54 BREQ gt 9 BSTRE 2 11 WORD 12 P60 WAIT lt 1 P55 BRACK 3 10 SYSCLK Figure 2 1 6 Processor Mode Address Data Separated Pin Configuration Chapter 2 Bus Interface Pin configurations of MN102L 610B are Figure 2 1 5 and 2 1 6 ALE is not generated during pro cessor mode Bus Interface II 29 Chapter 2 Bus Interface fM R ek R Q i0 pit 8 E 8 5 8 900000 ETHER 858 3 58 9 5858855 5 PAO IRQO 76 50 lt TM2IO P82 PA1 IRQ1 gt 77 49 81 2 1802 78 48 lt TMOIO P80 lt 79 47 a WDOUT AN7 P47 PA4 IRQ4 80 46 lt STOP AN6 P46 81 45 AN5 P45 RST 82 44 a AN4 P44 83 43 lt Vss POO lt 84 42 P43 85 41 P42 P41 ZE MN102LF61G 1 2 P04 lt 88 38 P37 ros le TOP VIEW per POG 90 36 lt P35 P07 91 35 w P34 Vss 92 34 4
87. An interrupt occurs at negative edge 11 An interrupt occurs at positive edge 3 2 2 NMI Pin Interrupts This series supports an NMI interrupt The NMI interrupt occurs on the negative edge of NMI pin NMI does not occur when microcontroller is in bus release status Chapter 3 Interrupts External Interrupts 1 59 Chapter 3 Interrupts In this example the interrupt level is 4 III 60 Interrupt Setup Examples 3 3 Interrupt Setup Examples 3 3 1 External Pin Interrupt Setup An interrupt occurs on the negative falling edge from the external interrupt pin IRQO PAO The external interrupt edge specification register EXTMD is set to the interrupt request generation at low level after reset release and the IRQOIR bit of the maskable interrupt control register 1 G1ICR becomes 0 E Interrupt Enable Setup 1 Set the interrupt conditions of the interrupt pin IRQO PAO In this case set the IRQOTG of the EXTMD register to 2 bit string 10 negative edge EXTMD 50 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQO IRQO TG1 TG1 TGO TGO TGO TG1 TGO 5 0 0 0 0 1 0 2 Enable interrupts At this point clear all prior interrupt requests do this set G1LV 2 0 IRQOIR and IRQOIE of the maskable interrupt control regis ter 1 G1ICR
88. Appendix repe IX 189 9 2 1 List of Special Registers IX 189 9 2 2 Address acie ette tiere pete IX 246 9 2 3 List of Pin Functions IX 248 MN102L SERIES INSTRUCTION SET IX 250 MN102L SERIES INSTRUCTION MAP eee IX 256 Initialization Program IX 260 EEPROM Version retener thee IX 262 9 6 1 ees IX 262 9 6 2 Reprogramming Flow 22 IX 263 9 6 3 PROM Writer Programming Mode IX 263 9 6 4 Onboard Serial Programming Mode IX 264 9 6 5 Hardware requirements eese IX 264 9 6 6 Pin Configuration in Onboard Serial Programming IX 268 9 6 7 Configuring the System for Onboard Serial Programming peo tete pos eoe pai IX 269 9 6 8 On board Programming Mode Setup IX 271 9 6 9 Branching to the User Program IX 273 9 6 10 Serial Interface for Onboard Programming IX 274 9 6 11 PROM Writer Onboard Serial Programming IX 276 V Contents vi Contents List of Figures Chapter 1 Figure 1 1 1 Figure 1 1 2 Figure 1 1 3 Figure 1 3 1 Figure 1 4 1 Figure 1 4 2 Figure 1 4 3 Figure 1 4 4 Figure 1 4 5 Figure 1 5 1 Chapter 2 Figure 2 1 1 Figure 2 1 2 Figu
89. Burst ROM read enable signal fall t delay time BSTRE PREDR enable signal pulse width time 1 RE F37 Read enable signal pulse width time t 2 RE REPW2 Read enable signal pulse width time F RE ig 9 TAN Read enable signal pulse width time ig 9 F zx tcyc 4 e Write enable signal fall delay time 1 Fig 9 3 WEL Fig 9 4 Write enable signal fall delay time 2 Fig 9 5 WEH WEL Fig 9 6 uns enable fall delay time 3 Write enable s width time 1 WEL 4 Write enable pulse width time 2 WEL 45 Write enable pulse width time 3 t 6 Write enable pulse width time 4 WEH WEL is standaard value no wait cycle It is listed value N tCYC in wait cycle IX 178 Electrical Characteristics Chapter 9 Appendix Vpp 4 5 V to 5 5 V Output Signal Characteristics Vss 0 V Ta 40 C to 85 C 70 pF Capacitance Parameter Symbol Conditions Unit EXC Serial Interface Signal Output Timing Synchronous Serial Transmission SBO1 0 tooo Fi 2 Fig 9 11 Fig 9 12 2 teyex2 Transfer data hold time transfer in F48 Fig 9 1 Transfer data hold time Transfer end timing at SBT input Fig 9 11 ns SBO1 0 2 Transfer data hold time tsch tscr Transfer end timing at SBT output x 2 ns SBO1 0 Electrical Characteristics IX 179 Chapter 9 Appendix AC Timin
90. CPUM 00 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WD OSC stop HALT 5 1 8 2 m Watchdog Timer Clear 3 Set the WDRST flag of the CPUM register to 1 and then immediately clear to 0 The watchdog timer is cleared to 0 when the WDRST flag is 1 B Interrupt Handling The program branches to x 080008 when an interrupt is generated and accepted 4 Specify the interrupt group by reading the interrupt accept group register IAGR during interrupt prehandling 5b Verify a watchdog interrupt by reading the nonmaskable interrupt control register GOICR Check the WDIF with the bit test instruction BTST If WDIF is 1 execute the interrupt service routine Chapter 3 Interrupts 6 Clear the WDIF flag of the GOICR register 7 Return to the main program with the interrupt return instruction RTI after the interrupt handling ends The watchdog timer and the oscillation stabilization wait counter are shared The watchdog timer operates as the oscillation stabilization wait counter when the CPU returns from the STOP mode Because of this the WDIF flag is cleared to 0 when the CPU moves to the STOP mode The WDIF flag is cleared to 0 again after the CPU moves to the normal mode 2 6 Standby Function in the MN102L Series LSI User s Manual Overflow WDRST CPUM if WDIF GOICR RST Pin Inte
91. Dn imm16 l imm16 h 15 F3 E4 Dn 15 F3 38 Dn 15 olooojeooojleoooceveeeeeooe 0 0 00 0 o m o s s m o r o Joo o o 2 v s Notes 15 16 bit computation 16 Performed under the conditions of bus lock and disabled interrupts 17 src dest lower 16 bits 18 srczdest lower 16 bits 19 src gt dest lower 16 bits signed IX 252 Instruction Set Chapter 9 Appendix Mnemonic Operation Machine Code BLE label IF VF NF ZF 1 PC 2 d8 label gt PC IF VFANF ZF 0 PC 23PC BGE label IF VF NF 20 PC 2 d8 label gt PC IF 1 PC 23PC BGT label IF VFANF ZF 0 PC 2 d8 label gt PC IF VFANF ZF 1 PC 23PC BCS label IF CF 1 PC 2 d8 label gt PC IF CF 0 PC 23PC BLS label IF CF ZF 1 PC 2 d8 label gt PC IF CF ZF 0 2 BCC label IF 0 PC 2 d8 label gt PC IF 1 PC 23PC BHI label IF CF ZF 0 PC 2 d8 label gt PC IF CFIZF 1 PC 23PC BVC label IF VF 0 F5 FC d8 PC 3 d8 label gt PC IF VF 1 PC 33PC BVS label IF VF 1 F5 FD d8 PC 3 d8 label gt PC IF VF 0 3
92. External Interrupt IRQ4 ATC Completion Timer Counter 6 Compare Capture B Timer Counter 6 Compare Capture A Timer Counter 6 Underflow Reserved Timer Counter 7 Compare Capture B Timer Counter 7 Compare Capture A Timer Counter 7 Underflow Non maskable Interrupt Control Register 0 GOICR x00FC40 Maskable Interrupt Control Register 1 G1ICR x00FC42 Maskable Interrupt Control Register 2 G2ICR x00FC44 Maskable Interrupt Control Register 3 G3ICR x00FC46 Maskable Interrupt Control Register 4 G4ICR x00FC48 Maskable Interrupt Control Register 5 G5ICR x00FC4A Maskable Interrupt Control Register 6 G6ICR 4 Maskable Interrupt Control Register 7 G7ICR x00FC4E Chapter 3 Interrupts The control registers are assigned to each corresponding interrupt group except Group 0 and control the assigned interrupt vectors For example in the MN102LF 53G when timer 0 becomes underflow the interrupt request flag IRF1 TMOIR of the maskable interrupt control register 1 G1ICR becomes 1 At this point an interrupt request is output to the CPU core if the corresponding interrupt enable flag IEN1 TMOIE is 1 Comparing the interrupt mask level IM2 to 0 of the processor status word PSW with the group interrupt level ILVn G1LV 2 0 of the G1ICR register and the interrupt enable flag IE of PSW determine whether the CPU core receives the interrupt or not G1ICR x 00FC42 15 14 13 12 11 10 9 8 7 6
93. F3 C1 Dn lt lt 2 6 EXTX Dn Dn bp15 0 Dn amp x 00FFFF gt Dn F Dn bp15 1 Dn x FF0000 gt Dn EXTXU Dn Dn amp x 00FFFF gt Dn EXTXB Dn F Dn bp7 0 Dn amp x 0000FF Dn F Dn bp7 1 Dn x FFFF00 Dn EXTXBU EXTXBU Dn Dn amp x 0000FF Dn BC Dn ADD DD Dn Dm Dm Dn gt Dm 90 Dn lt lt 2 Dm DD Dm An An Dm gt An F2 00 Dm lt lt 2 An DD An Dm Dm An gt Dm F2 C0 An lt lt 2 Dm DD An Am Am An gt Am F2 40 An lt lt 2 Am DD imm8 Dn Dn imm8 Dn D4 Dn imm8 DD imm16 Dn Dn imm16 Dn F7 18 Dn imm16 l imm16 h DD imm24 Dn Dn imm24 Dn F4 60 Dn imm24 l imm24 m imm24 h DD imm8 An 8 D0 An imm8 DD imm16 An 16 F7 08 An imm16 l imm16 h DD imm24 An An imm24 An F4 64 An imm24 l imm24 m imm24 h DDC Dn Dm Dm Dn CF Dm F2 80 Dn lt lt 2 Dm A A A A A A A A A A A A DDNF imm8 An An imm8 gt An F5 0C An imm8 11 SUB Dn Dm Dm Dn 5Dm A0 Dn lt lt 2 Dm SUB Dm An An DmAn 2 10 lt lt 2 SUB gt F2 D0 An lt lt 2 Dm SUB An Am Am An gt Am F2 50 An lt lt 2 Am SUB imm16 Dn Dn imm16 Dn F7 1C Dn imm16 l imm16 h SUB imm24 Dn Dn imm24 Dn F4 68 Dn imm24 l imm24 m imm24 h SUB imm16 An An imm16 4An F7 0C An imm16 l imm16
94. Figure 9 6 8 Timing Waveform during Serial Programming Flash EEPROM Version IX 271 Chapter 9 Appendix e To set up the serial writer interface 1 At timing A serial interface writer supplies and at this time it outputs NRST SBD Low 2 Through the serial writer drive the NRST pin from timing B when SBT goes high on microcontroller power up for T2 cycles The microcontroller initializes 3 Through the serial writer drive the NRST pin Low from time C when SBD goes high on microcontroller power up for T3 cycles This signals the microcontroller that it is connected to the serial writer 4 Make T3 long enough to allow the microcontroller oscillator to stabilize eStart routine for the load program Reset start SBT pin High amp amp pin Low Wait tWAIT1 SBT pin High SBD pin Low Yes Wait tWAIT2 SBT pin High SBD pin High Start serial writer Execute user load program program Figure 9 6 9 Start Routine for the Load Program Conditions 1 After the load program initiates a reset start SBD must be low and SBT high 2 Wait 3 SBD must be low and SBT high 4 Within tWAIT2 both SBD and SBT must be high If any of these conditions is not met control returns to the user program IX 272 Flash EEPROM Version Chapter 9 Appendix 9 6 9 Branching to the User Program 1 Branching to the reset start routine Reset start Serial writer
95. Input Output Shared Pin Function Description P46 General purpose Port 4 When this pin is used general purpose input output ports I O direction control is in bit unit Input ANG A D converter input This is a input pin for A D converter t Chapter 6 Analog interface Output STOP STOP status signal In STOP or HALT mode This pin becomes H level Output A22 Address output This pin outputs memory address A22 in memory expansion mode and processor mode and is connected to memory address pin or ad dress decoder circuit Address output at the tim ing when this pin does not access to the memory is indifined it outputs some fixed value During bus request when BREQ is L STOP mode or HALT mode this pin will be in a high impedance state but this pin does not become high impedance state when used as ports 47 I O General purpose Port 4 When this pin is used as general purpose input output ports direction control is in bit unit Input 7 A D converter input This is a input pin for A D converter Chapter 6 Analog interface Output WDOUT Watchdog Timer When the watchdog timer is overflowed pulse is Overflow Signal output Output A23 Address output This pin outputs memory address A23 in memory expansion mode and processor mode and is connected to memory address pin or ad dress decoder circuit Address output at the tim ing when this pin does not access to the memory is in
96. Input SBI1 0 Serial Interface output port 4 Chapter 8 Ports Data Input These are data input output pins for serial in terface When these pins are unused fix the P75 P72 I O General purpose Port 7 input pin to level and leave the output pin Output SBT1 0 Serial Interface open Data Output Chapter 5 serial interface P70 General purpose Port 7 This can be used as general purpose input SBTO Serial Interface 0 output port Chapter 8 Ports Clock Input output When used with serial interface these pins pro vide synchronous transfer clock signal When P73 I O General purpose Port 7 these pins are unused fix the input pin to H VO SBT1 Serial Interface 1 level and leave the output pin open Clock Input output 4 Chapter 5 serial interface 1 20 Pin Description Chapter I Overview Table 1 4 1 List of Pin Functions 9 9 Pin Name Shared Pin Function Description P85 P80 I O General purpose Port 8 When these pins are used as general purpose input output ports direction control is in I O TMBIO Timer 5 0 Input output bit unit Chapter 8 Ports TMOIO They are input ouput pins for timer 5 0 P86 I O This pin can be used as general purpose in put output port TM6IOA Timer 6A Input output This pin serves as timer input capture input pin and ouput compare output pin P87 This pin can be used as general purp
97. MOV instruction to set the data and always use 16 bit write operations Stop TM7BC counting and initial ize clear TM7BC and RS F F Do not output athe first one shot pulse when TM7CB is set to 0 If this step is omitted TM7BC may not count during the first cycle TM7EN is substitute for the BUSY flag for one shot pulse IV 102 16 bit Timer Setup Examples 4 3 7 One shot Pulse Output Using 16 bit Timer The one shot pulse setup procedures for timer 6 and timer 7 are same In this example timer 7 generates a one shot pulse The pulse width is 2 cycles of SYSCLK m Timer 7 Setup 1 Set the operating mode to the timer 7 mode register TM7MD Verify that counting is stopped and an interrupt is disabled Select up counting Se lect SYSCLK as the timer 7 clock source TM7MD 00 40 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pe ms ae p py EN LD UD1 UDO TGE ONE MD1 MDO ECLR LP 52 51 SO 0 0 i 0 0 0 1 0 0 0 1 0 0 1 1 2 Set the timer 7 pulse width to TM7CA The valid range is 1 to x FFFF Since the timer 7 pulse width is 2 cycles of SYSCLK write 3 to TM7CA TM7BC counts from 0 to 3 and TM71OA outputs high while TM7BC counts from 2 to 3 7 x 00FE44 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 TM7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 CA15 CA14 CA13 CA12
98. Mode Access Timing Bus Interface 37 Chapter 2 Bus Interface II 38 MN102LF61G A23 00 D15 00 RE WEH WEL CSO CSn MN102LF61G A23 00 I I D15 00 OE Note D A D A D A D ROM RAM ROM RAM OE CE OE WR CE OE CE OE WR CE 5 e RE WEH WEL cso CSn Bus Interface Note When using ROM with longer output data hold time you may need to equip the 3 state buffer for example 74ALS541 in the broken line Figure 2 1 10 Access Timing Memory Connection Example During ROM Burst Mode As Figure 2 1 10 shows the access is fast but RE signal BSTRE for burst ROM is required when access without penalty cycle is selected In addition the exter nal 3 state buffer for example 74ALS541 may be required when the ROM data hold time is long Chapter 2 Bus Interface Bus Interface II 39 Chapter 2 Bus Interface 2 2 External Memory Connection Examples 2 2 1 Memory Expansion Mode Address Data Separated Mode In this LSI series the control registers for address or data setting need to be set as follows during address data separated mode See Chapter 8 Ports
99. Note Note Note Note Note Buffer 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note Undefined 8 bit access register 16 bit access is possible 7 0 Conversion Result of Ch 5 AN5 Pin from even address ANSBUF is a read only buffer IX 214 Data Appendix Chapter 9 Appendix 6 5 4 3 2 1 0 AN6BUF AN6 AN6 6 6 6 AN6 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUFO x OOFDAE A D 6 Conversion Data Note Note Note Note Note Note Buffer 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note Undefined 8 16 bit access register 7 0 A D Conversion Result of Ch 6 6 Pin AN6BUF is a read only buffer 7 6 5 4 3 2 1 0 AN7BUF AN7 AN7 AN7 AN7 AN7 AN7 AN7 AN7 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUFO x OOFDAF OR RR A D 7 Conversion Data Note Note Note Note Note Note Note Buffer 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note Undefined 8 bit access register 16 bit access is possible 7 0 Conversion Result of Ch 7 7 Pin from even address AN7BUF is a read only buffer Data Appendix IX 215 Chapter 9 Appendix 7 6 5 4 3 2 1 0 TMO
100. TM2MD 00 22 7 6 5 4 3 2 1 0 2 2 EN LD i 61 so Qr A lt lux GE 3 Enable interrupts At the same time clear all prior interrupt requests Set G3LV 2 0 bits of the maskable interrupt control register G3ICR to the interrupt level of 6 to 0 TM2IR and 21 to 0 and 1 respectively For example write x 4200 to the G3ICR register Thereafter an interrupt oc curs when timer 2 underflows G3ICR x 00FC46 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 63 G3 SCORSCOT TM2 IRQ2 SCORSCOT TM2 IRQ2 SCORSCOT TM IRQ2 LV2 LV1 LVO IE IR IR IR IR ID ID ID ID 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Chapter 4 Timers Counters 4 Set the timer divisor Since timer 2 divides the TM2IO pin by 4 set the timer 2 base register 2 to 3 The valid range for TM2BR is 1 to 255 TM2BR x 00FE12 7 6 5 4 83 2 1 0 2 TM2 TM2 2 2 2 2 2 7 5 BR2 BR1 BRO 0 0 0 0 0 0 1 1 5 Load the TM2BR value to the TM2BC register To do this set TM2LD and TM2EN of the TM2MD register to 1 and 0 respectively At the same time select the clock source Set TM2S 1 0 to 00 Changing the clock source while controlling count operation will 6 Set both TM2LD and TM2EN of the TM2MD register to O If this setting is cor
101. TM7 TM7 TM7 7 TM7 TM7 7 TM7 TM7 UD1 UDO TGE ONE MDO ECLR LP ASEL S2 51 50 x 00 40 R W RAW R R R W R W R W RW R W R W R W R W R W R W RW R W Timer 7 Mode Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 04 01 01 16 bit access register 15 TM7BC Count 0 Disable 1 Enable 14 TM7BC T F F RS F F 0 Set 7 T F F RS F F to 0 Operation 1 Operate TM7BC RS F F 11 10 Up Down Counter Mode 00 Up counter Selecting up down counting Selection Ignored when two 01 Down counter mode is ignored when two phase phase encoding is selected 10 Up when TM7IOA pin is high encoding is slected down when pin is low 11 Up when TM7IOB pin is high down when 7 pin is low Counting starts on the falling 9 Count Start External Trigger 0 Disable 1 Enable edge of TM7IOB pin Enable Clear TM7EN when TM7BC matches TM7CA 8 Counter Operating Mode 0 Repeat 1 One shot counting During repeat counting hold the Select TM7EN flag state During one 76 TM7CA TM7CB Operating 00 Compare register single buffer shot counting set the TM7EN Mode Selection 01 Compare register double buffer flag to 0 when TM7BC TM7CA 10 Capture A when pin is high Capture B when pin is low
102. Timing Address Data Share Mode Without Wait IX 184 Data Transfer Signal Timing Address Data Share Mode With Wait IX 185 Data Transfer Signal Timing Burst ROM Interface IX 186 Bus Authority Request Signal IX 187 Interrupt Signal Timing IX 187 Serial Interface Signal Timing 1 Synchronous Serial Transmission Transfer in Progress IX 187 Serial Interface Signal Timing 2 Synchronous Serial Transmission Transfer End Timing at SBT Input IX 187 Serial Interface Signal Timing 3 Synchronous Serial Transmission Transfer End Timing at SBT Output IX 188 Serial Interface Signal Timing 2 Synchronous Serial Reception IX 188 Timer Counter Signal Timing IX 188 Memory Map of Internal Flash EEPROM eee IX 262 Internal EEPROM Programming IX 263 8 bit Serial Interface Block Diagram see IX 264 Internal flash EEPROM address Space asss IX 265 Pin Configuration for Serial Programming eee IX 268 Configuring System for Onboard Serial Programming IX 269 Pin Configuration on the Target Board esse IX 269 Timing Waveform during Serial Programming eee IX 271 Start Routine for the Load Pr
103. W ATC Binary Counter eo 0 0 0 0 0 0 01 8 16 bit access register 9 0 ATC Transfer Address Set the ATC start address the lower 10 bits of the internal RAM area Read the internal RAm address where the chip accesses next during ATC operation Data Appendix IX 205 Chapter 9 Appendix 15 14 13 12 11 10 9 8 7 5 14 2 1 4 SCO SCO SCO SCO SCO SCO SCO SCO SCO SCO SCO 520 SCO SCO SCO TEN REN BRE I2CS PTL OD I2CM LN PTY2 PTY1 PTYO SB POD 51 So R W RW RW RW R RAW RAW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 04 Oft Oft OA 15 Transmit Enable 0 Disable 1 Enable 14 Receive Enable 0 Disable 1 Enable 13 Break Transmission 0 Don t break 1 Break Set SBO to 0 0 Stop sequence output when changing this 12 PC Start or Stop Sequence bit from 1 to O 1 Start sequence output when changing this bit from O to 1 0 Asynchronous mode 11 Protocol Selection 1 Clock synchronous mode IC mode 0 LSB first 9 Bit Order Selection 1 MSB first select only when the charact
104. a timer 0 underflow interrupt request occurs m Timer 2 and Timer 3 Setup 8 Verify that counting is stopped using the timer 2 mode register TM2MD and the timer 3 mode register TM3MD TM2MD 22 TM3MD x 00FE23 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 _ TM2 TM2 _ EN LD 51 50 EN LD 51 50 0 0 O 0 0 0 1 9 Set the timer divisor Since the divisor is 40000 9 407 set the timer 2 base register TM2BR and the timer 3 base register to x 3F and x 9C The valid range is 1 to 255 TM2BR x 00FE12 TM3BR x 00FE13 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 TM2 2 2 2 TM2 TM2 TM2 TM2 BR7 BR6 BRA BRA BR2 1 BRO BR7 BR6 BR5 BR4 BR3 BR2 BR1 BRO 0 0 1 1 1 1 1 1 1 0 0 1 1 1 0 0 10 Load the TM2BR value to TM2BC and the TM3BR to To do this set both TM2LD and TM3LD to 1 and both TM2EN and TM3EN to 0 At the same time select the clock sources Select timer 0 for the timer 2 clock source and timer 2 cascade for the timer 3 clock source Chapter 4 Timers Counters 11 Set both TM2LD and TM3LD to 0 and both TM2EN and to 0 If this setting is omitted the
105. acceptance it sets the branch address or ALU operation results Instruction Queue The instruction queue saves up to 4 bytes of prefetched instructions Instruction Decoder The instruction decoder decodes the instruction queue content generates con trol signals needed for the instruction execution and executes the instruction by controlling each block in the CPU Instruction Execution Controller The instruction execution controller controls the operations of each CPU function based on results from the instruction decoder and interrupt requests ALU The ALU calculates the operand addresses for arithmetic operations logic opera tions shift operations register relative indirect indexed addressing and register indirect addressing mode Internal ROM Internal RAM Internal ROM and internal RAM are allocated as the execution program data and stack areas Address Registers An The address registers An store the addresses of memory accessed during data transfer They also store the base addresses in the register relative indirect indexed addressing and register indirect addressing mode Operation Registers The data registers Dn store the operation results and transfer the data to memory Dn MDR They also store the offset addresses in indexed addressing and register indirect addressing mode The multiplication division register MDR stores the data for multiplication divi sion operati
106. bytes NOP Extended code 4 bytes MOV imm16 Dn JMP label16 2 BSET Dm An 3 BCLR Dm An MOVB Di An Dm Di An Dm MOVB Dnm Di An IX 256 Instruction Map Chapter 9 Appendix 2 byte instructions Byte 1 F1 Second byte Upper Lower 0 MOV Di An Dm MOV Dnm Di An 2 byte instructions Byte 1 F2 Second byte Upper Lower 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 ADD Dm An 1 SUB Dm An 2 CMP Dm An 3 MOV Dm An 4 ADD An Am 5 SUB An Am 6 CMP An Am 7 MOV An Am 8 ADDC Dn Dm 9 SUBC Dn Dm A B ADD Dm D SUB An Dm E CMP An Dm F MOV An Dm IX 257 Instruction Map Chapter 9 Appendix 2 byte instructions Byte 1 F3 Second byte Upper Lower 1 2 3 5 6 9 A D E F 0 AND Dn Dm 1 OR Dn Dm 2 XOR Dn Dm 3 ROL Dn 4 MUL Dn Dm 5 MULU Dn Dm 6 DIVU Dn Dm 7 8 9 CMP Dn Dm A B D E MOV MDR Dn E MOV PSW Dn 5 byte instructions Byte 1 F4 Second byte Upper Lower 0 1 2 3 0 MOV Dm d24 An 1 MOV Am d24 An 2 MOVB 424 An 3 MOVX Dm d24 An 4 MOV Dn abs24 MOVB Dn abs24 5 MOV An abs24 6 ADD imm24 Dn ADD imm24 SUB imm24 SUB imm24 7 MOV imme24 Dn
107. data and always use 16 bit write operations Stop TM7BC counting and initial ize clear TM7BC and RS F F IV 98 16 bit Timer Setup Examples 4 3 5 Two phase Capture Input Using 16 bit Timer The two phase capture input setup procedures for timer 6 and timer 7 are same except the up down counting selection In this example timer 7 divides SYSCLK by 65536 and measures the width from positive edge of the TM7IOA input to the positive edge of TM7IOB input An interrupt occurs on the capture B and the width is calcu lated by the instruction TMnCB TMnCA m Interrupt Enable Setup 1 Enable interrupts At the same time clear all prior interrupt requests Set G7LV 2 0 bits of the G7ICR to the interrupt level of 6 to 0 TM7BIR and TM7BIE to 0 and 1 respectively For example write x 4400 to the G7ICR register Thereafter an interrupt occurs when the timer 7 capture B oc curs W Timer 7 Setup 2 Set the operating mode to the timer 7 mode register TM7MD Verify that counting is stopped and an interrupt is disabled Select up counting or down counting Set TM7LP to 0 to count the loop of 0 to x FFFF Select SYSCLK as the timer 7 clock source TM7MD 40 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TW 7 _ _ TM7 TM7 TM7 TM7 7 7 7 7 TM7 EN LD UD1 UDO TGE ONE MD1 MDO ECLR LP ASEL 52 51
108. data is read when an interrupt occurs or the SCORXA flag of the SCOSTR registeris 1 In 7 bit transfer the MSB bit 7 becomes 0 Data Appendix IX 207 Chapter 9 Appendix 7 6 5 4 3 2 1 0 SCO SCO SCO SCO sco sco sco SCO TBSY RBSY SPS STS OE RCR B UT RB 0 0 0 0 0 0 0 0 7 Transmission Busy Flag 6 Reception Busy Flag 5 PC Stop Sequence Detect 4 Received Data 3 PC Start Sequence Detect 2 Framing Error 1 Parity Error 0 Overrun Error IX 208 Data Appendix 0 Transmission in progress 0 Ready to transmit Ready to receive Reception in progress Undetected 1 Detected No received data Received data Undetected Detected No error Error No error Error No error Error SCOSTR x 00FD83 Serial 0 Status Register 8 bit access register 16 bit access is possible from even address A framing error occurs when the stop bit is 0 Framing error data is updated whenever the stop bit is received A parity error occurs when the parity bit is 1 although it is set to 0 when the parity bit is O al though itis setto 1 when the par ity bit is odd although it is set to even and when the parity bit is even although it is set to odd Parity error data is updated whenever the parity bit is re ceived An overrun
109. describes one or more registers Each page lists the register name address register access bit map flag explanation of each bit number and supple mentary explanation The following is the layout and definition of this section Bit Map Bit Number Flag Name Access R Read only 15 13 12 as q s ala ijo i W Write only EN MDI MD0 BW DB8 DI 88 SI 103 IQ2 101 100 R W Read Write R W RAW R W R W R W R W R W R W RW Value at reset Read value 0 Always 0 1 Always 1 Bit Number Flag Description IX 190 x S 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 15 Transfer Busy Start Flag 14 13 Transfer Mode 12 10 9 8 3 0 Trapsfer Units Destination Bus Width Destination Pointer Increment Source Bus Width Source Pointer Increment ATC Activation Factor Setup 0 Disable 1 Transfer start transfer in progress 00 One byte word transfer 01 Burst transfer 10 Two bytes words transfer 11 Reserved 0 Byte 1 Word 0 16 bit 1 8 bit 0 Fixed 1 Increment to 0 by the ATC3 transfer end 0 16 bit 1 8 bit 0 Fixed 1 Increment 0000 Software Initialization 0001 DMAREQ1 p
110. gt label IF NF 0 F5 FE d8 PC 3 d8 label gt PC IF NF 1 3 gt BNS label IF 1 F5 FF d8 PC 3 d8 label PC IF NF 0 BRA label PC 2 d8 label EA d8 BEQX label IF ZX 1 F5 E8 d8 PC 3 d8 label gt PC IF ZX 0 3 gt BNEX label IF ZX 0 25 29 48 PC 3 d8 label IF ZX 1 3 gt Notes 20 src2dest lower 16 bits signed 21 srcxdest lower 16 bits signed 22 src dest lower 16 bits signed 23 src gt dest lower 16 bits unsigned 24 src2dest lower 16 bits unsigned 25 srcxdest lower 16 bits unsigned 26 src dest lower 16 bits unsigned 27 VF 0 28 1 29 NF 0 30 NF 1 31 src dest 24 bits 82 srczdest 24 bits Instruction Set IX 253 Chapter 9 Appendix Instruction Mnemonic BLTX label Operation VX NX 1 PC 3 d8 label PC F VX NX 0 3 gt Machine Code F5 E0 d8 BLEX label F VXANX ZX 1 PC 3 d8 label gt PC F VX4NX ZX 0 3 gt F5 E3 d8 BGEX label F VXANX 0 PC 3 d8 label gt PC F VXANX 1 PC 3 PC F5 E2 d8 BGTX label F VXANX ZX 0 PC 3 d8 label PC F VXANX ZX 1 PC 3 PC F5 E1 d8 BCSX label CX 1 PC 3 d8 label gt PC F CX 0 PC 3 PC F5 E4 d8 BLSX label F CX ZX 1 PC 3 d8 label
111. imm16 Dn AND imm16 PSW PSW amp imm16 5PSW Dn Dm Dm Dn amp x 0OOFFFF Dm OR imm8 Dn Dn imm8 Dn OR imm16 Dn Dn imm16 Dn OR imm16 PSW PSW imm16 PSW XOR Dn Dm Dm x 00FFFF amp Dn Dm XOR imm16 Dn Dn imm16 Dn NOT Dn Dn x O0FFFF Dn ASR Dn Dn Isb gt CF Dn bp Dn bp 1 bp15 1 Dn bp15 Dn bp15 Dn Isb gt CF Dn bp Dn bp 1 bp15 1 0 gt Dn bp15 Dn Isbotemp F3 34 Dn Dn bp Dn bp 1 bp15 1 CF Dn bp15 temp gt CF Dn bp15 temp F3 30 Dn Dn bp gt Dn bp 1 bp14 0 CF Dn Isb temp CF BTST imm8 Dn Dn amp imm8 PSW F5 04 Dn imm8 BTST imm16 Dn Dn amp imm16 PSW F7 04 Dn imm16 l imm16 h BSET mem8 An amp Dm PSW F0 20 An lt lt 2 Dm meme8 An Dm mem8 An BCLR mem8 An amp Dm PSW F0 30 An lt lt 2 Dm mem8 An amp Dm gt mems An BEQ label IF ZF 1 E8 d8 PC 2 d8 label gt PC ZF 0 PC 23PC BNE label F ZF 0 PC 2 d8 label gt PC F ZF 1 PC 23PC BLT label F VFANF 1 PC 2 d8 label PC F 0 2 F3 90 Dn lt lt 2 Dm F2 20 Dm lt lt 2 An F2 E0 An lt lt 2 Dm 2 60 lt lt 2 D8 Dn imm8 F7 48 Dn imm16 l imm16 h F4 78 Dn imm24 l imm24 m imm24 h EC An imm16 l imm16 h F4 7C An imm24 l imm24 m imm24 h F3 00 Dn lt lt 2 Dm 15 F5 00 Dn imm8 15 F7 00 Dn imm16 l imm16 h 15 F7 10 imm16 l imm16 h 715 F3 10 Dn lt lt 2 Dm 715 F5 08 Dn imm8 15 F7 40 Dn imm16 l imm16 h 15 F7 14 imm16 l imm16 h 15 F3 20 Dn lt lt 2 Dm 15 F7 4C
112. improves the system architecture in speed and function to meet the require ments in user systems including miniaturization and low power consumption The MN102LF61G series contains sufficient peripheral equipments four CS sig nals and a memory interface that supports burst ROM and realize high efficiency real time control in variety of systems such as printer electric musical instru ments audiovisual equipments home electric appliances cars robots and com puter peripherals The MN102L series adapts a load store architecture method for computing within registers and a harvard architecture method for separating instructions bus and operand bus Using one byte one machine cycle basic instructions minimizes code size and improves compiler efficiency Model Explanation MN102 L F 61 ROM RAM sizes 128 k 4 k OB OKAKk Model number Internal ROM P OTP F Flash None Mask ROM L Core version 16 bit 102 series 1 1 2 Features The MN102L series contains a flexible and optimized hardware architecture as well as a simple and efficient instruction set It obtains economical efficiency and high speed 1 Linear Addressing for Large Systems The MN102L series contains up to 16 Mbytes of linear address space The CPU provides an effective development environment without detecting borders be tween address spaces The hardware architecture is also optimized for large Systems The memory is not divided
113. into instruction space and data space so that operations can share instructions 2 Single byte Basic Instruction Length The MN102L series has replaced general registers with eight internal CPU registers divided four address registers 0 to and four data registers DO to D3 The register specification fields are four bits or less and the code sizes of the frequently used basic instructions in cluding register to register operations and load store operations are one byte 3 High speed Pipeline Processing The MN102L series executes instructions in a 3 stage pipeline fetch decode and execute This allows the MN102 series to execute in structions of single byte in one machine cycle 100 ns at 20 MHz 4 Simple Instruction Set Chapter I Overview Conventional register assignment 15 8 7 0 1 1 11 ____ V specification field 7 0 Register specification field New register assignment 1 cycle Instruction 1 Fetch r gt Decode Address gt Execute calculation Instruction 2 Fetch gt Decode The MN102L series uses an instruction set of 36 instructions designed specially for the programming model for embedded applications To compress size instructions have a variable length of one byte to five bytes The most fre quently used instructions in C language compiler are single byte 5 High speed Interrupt Response
114. is unused 8 Bus Mode for Block 3 0 16 bit Bus Mode 1 8 bit Bus Mode 1 0 Wait Cycle for Block 3 00 No Wait 01 1 Wait Cycle 10 2 Wait Cycles 11 Handshake 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GOICR UNIF WDIF NMIF x 00FC40 R R R RJ RIR R R Nonmaskable Interrupt 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Control Register 0 8 16 bit access register 2 Nonmaskable Interrupt 0 No interrupt requested Request Flag by Executing Interrupt requested Undefined Instruction 1 Nonmaskable Interrupt 0 No interrupt requested Request Flag by Overflowing Interrupt requested Watchdog Timer 0 Nonmaskable Interrupt 0 No interrupt requested Request Flag by NMI Pin Interrupt requested Data Appendix IX 195 Chapter 9 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 G1 G1 Gi 5 TMO IRQO 5 TMO IRQO TM5 TMO IRQO LV2 LV1 LVO IE IE IE IR IR IR ID ID ID R RW R W RW R RW RW R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 14 12 Group 1 Interrupt Priority Level 10 Timer 5 Underflow Interrupt Enable Flag 9 Time
115. is invalid See 2 2 1 Memory Expansion Mode Address Data Separated Mode and 2 2 3 Memory Expansion Mode Address Data Shared Mode for port setting during memory expansion mode ALP Address Data Output Control Bus Controller P2DIR4 P2DIRO P2MD4 P2MD0 P271024 P2OUT7 to 0 0 A07 1004 Address Data Output Control I Bus Controller o 00 P2IN7 to 0 Pots VIII 143 Chapter 8 Ports Table 8 1 1 Port Functions 3 of 8 Port Pin Function Shared Pin P37 to P30 Port 3 is used as the port 3 general purpose port or address output At reset this A15 to A08 port operates as a general purpose port input during other modes except processor mode and as A15 to 08 pins during processor mode During processor mode P3MD is invalid See 2 2 1 Memory Expansion Mode Address Data Separated Mode and 2 2 3 Memory Expansion Mode Address Data Shared Mode for port setting during memory expansion mode AMP Address Data Output Control Bus Controller P3DIR7 to 0 7 to 0 P3OUT7 to 0 0 P37 to 30 Address Data 1 A15 to 08 Bus Controller H 7 to 0 P43 to P40 Port 4 is used as the port 4 general purpose port address output A D converter A19 to A16 input pin or C
116. more detailsd infomation required for your design purchasing and applications If you have any inquiries or questions about this book or our semiconductors please contact one of our sales offices listed at the back of this book About This Manual This manual is intended for assembly language programming engineers It describes the internal configuration and hardware functions of this microcontroller by block basis Configuration Each section of this manual consists of a title summary main text key information precautions and warnings and references The layout and definition of each section are shown below Su btitle Seriallnterface Sub subtitle 5 2 Serial Interface Setup Examples The smallest block in this manual 5 2 1 Serial Transmissidn Asynchronous Mode This section describes the example of serial interface transmission in asynchronous mode with the following settings Main text Baud rate 19200 set transmit clock by timer 5 8 bit data transmission two stop bits odd parity The next data is transmitted when a transmission end interrupt occurs P2 CORE ROM RAM P6 Interrupt Bus Control P5 PC Timer 0 Timer 15 Serial I F 5800 16 20 AD Converter P8 ED Timer 21 ATC Figure5 2 1 Asynchronous
117. same as those No 16 Up to 4M bytes 8bit All Spaces in the above 8 bit bus width of No 10 Use D07 to D00 as general purpose ports A20 to A00 015 to D08 P4DIR P4MD ofofifififif1 Use A23 to 22 as general purpose ports PODIR to P3DIR and POMD to P3MD are same as those 16bit in the above 16 bit bus width of No 10 Use A23 to A22 as general purpose ports D15 to D00 and P4MD are same as those in the above 8 bit bus width PODIR to P3DIR and POMD to P3MD are same as those No 17 Up to 8M bytes 8bit All Spaces in the above 8 bit bus width of No 10 Use D07 to D00 as general purpose ports A21 to A00 D15 to D08 Or P4DIR P4MD In addition use A22 as general purpose CS2 to CSO port when the address is determined by A21 to A00 P6MD 151 CS2 to CSO PODIR to P3DIR and POMD to P3MD are same as those 16bit in the above 16 bit bus width of No 10 Use A23 as a general purpose port D15 to DOO P4DIR and P4MD are same as those in the above 8 bit In addition use A22 as a general purpose bus width port when the address is determined by CS2 to CSO PODIR to P3DIR and POMD to P3MD are same as those No 18 Up to 16M bytes 8bit All Spaces in the above 8 bit bus width of No 10 Use D07 to D00 as general purpose ports A23 to A00 Or 83 to 80 A23 to A00
118. source Set both TM2LD and TM2EN to 0 Set TM2LD and TM2EN to 0 and 1 respectively This starts timer 2 m Serial Interface 0 Setup 6 Enable interrupts At this point clear all prior interrupt requests Set the GSICR register to the interrupt level level 6 to 0 SCOTIR and SCOTIE to 0 and 1 respectively For example write the G3ICR register to 44000 Thereafter a serial transmission end interrupt occurs when the data writ ten to the serial transmit receive register is transferred G3ICR x 00FC46 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 G3 G3 SCORSCOT TM2 IRQ2 SCORSCOT 2 IRQ2 SCOR SCOT TM IRQ2 LV2 LV1 LVO IE IE IR IR IR IR ID ID ID ID 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Chapter 5 Serial Interface This verification is unnecessary immediately after a reset 1 Do not change the clock source once you have selected it Chang ing the clock source while control ling count operation will corrupt the binary counter value If this step is omitted TM2BC may not count during the first cycle Serial Interface Setup Examples V 117 Chapter 5 Serial Interface 7 Setthe operating control conditions to the serial 0 control register SCOCTR Set asynchronous mode LSB for bit order timer 2 16 8 bit data transfer 2 stop bits and odd parity SCOCTR 00 080 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
119. the OSCO pin with the external cir cuit is not allowed Select the SYSCLK pin as a synchronous signal XI Input Output Low speed Oscillator Input 32 kHz to 200 kHz Low speed Oscillator Output 32 kHz to 200 kHz For a self excited oscillator configuration con nect crystal or ceramic oscillator across these two pins They have a built in feedback resistor between them For stability insert capacitor of 100 pF to 200 pF between the XI pin or the XO pin and the Vss pin For the exact capacitance consult the oscillator manufacturer Figure 1 4 3 For an external oscillator configuration connect the XI pin to an oscillator with an amplitude of 32 kHz to 200 kHz and the width between Vpp and Vss Leave the XO pin open Figure 1 4 3 If the XI pin is not used connect it to Vss or If the XO pin is not used leave it open Select the SYSCLK pin for a synchronous signal Pin Description I 13 Chapter 1 Overview Table 1 4 1 List of Pin Functions 2 9 Pin Name Input Output Shared Pin Function Description RST Input Reset Input This pin resets the chip With a 20 MHz oscilla tor reset starts when the low level is input to this pin for more than 400 ns Reset may start even when the noise is input to this pin for less than 400 ns so please pay highly attention to noise Reset is released when the high level is input to the pin The oscilla
120. the addresses of x 800000 to x 807FFF Beacuse of this the CS2 signal is generated even though the program accesses the address of x 000000 to x 007FFF shown in Figure 2 1 1 The CS1 pin CS2 pin and CSS pin are allocated into Block1 Block2 and Block 3 respectively and these pins become low level 010000 10 x3FFFFF 50 signal is not generated in the internal ROM area CS1 x 400000 to x 7FFFFF CS2 x 000000 to x 007FFF x 800000 to x BFFFFF CS3 x C00000 to x FFFFFF Table 2 1 1 CS Signal Generation This series has two modes of address data shared mode and address data sepa rated mode The ADSEP pin selects each mode Figure 2 1 3 to Figure 2 1 7 show the pin configuration in each mode The CS0 signal is generated even in the internal ROM area during processor mode Accessing the logical addresses of x 000000 to x 007FFF means accessing the addresses of x 800000 to x 807FFF II 27 Bus Interface Chapter 2 Bus Interface e 558 5888 588988 ce cio zx 85858 58 5 8885885885 76 50 TM2IO P82 77 49 lt 81 2 2 78 48 80 PA3 IRQ3 lt 79 a A23 WDOUT AN7 P47 PA4 IRO4 80 46 lt A22 STOP AN6 P46 81
121. to 85 C Capacitance Parameter Symbol Conditions Unit Input Output Pins 3 Output pushpull Input TTL level schmitt trigger Programmable pullup gt WAIT WEL WEH CS3 to 50 ALE A19 to AO IRQ4 to IRQO 5 0 V 5 0 V Input Output Pins 4 Output pushpull Input TTL level schmitt trigger gt BREQ BRACK WORD 5 0 V Output high voltage baz NS 5 0V Output low voltage 40 mA IX 166 Electrical Characteristics Chapter 9 Appendix Vpp 4 5 V to 5 5 V Vss 0 V Ta 40 C to 85 C Capacitanoe 0 Parameter Symbol Conditions Unit a Input Output Pins 5 Output pushpull Input TTL level schmitt trigger Programmable pullup gt D15 to DO 5 0 V Voo 5 0 V Input Output Pins 5 Output pushpull Analog Input ANS to AN1 5 0 V 5 0 V Electrical Characteristics IX 167 Chapter 9 Appendix Vpop 4 5 V to 5 5 V Vss 0 V Ta 40 C to 85 C Parameter Symbol Conditions Unit HIP Input Output Pins 7 Output pushpull Analog Input Programmable pullup A23 to A20 5 0 V Vos 5 0 V Input Output Pins 8 lt Input CMOS level schmitt trigger Output open drain Pullup gt RST IX 168 Electrical Characteristics 45 V to 5 5 V Vss 0 V Ta 40 C to 85 C Capacitance Parameter Symbol Conditions w Unit Pin 9 lt Output pushpull Input TT
122. width TMnlO 5 0 ns TMnIOA TMnIOB TMnIC 6 7 Fig 9 14 Serial clock input low pulse width E1 1 EE ES Beer bel Timer external input clock high E20 pulse width n 5 0 TMnIOA TMnIOB TMnIC 6 7 ENH IX 174 Electrical Characteristics Chapter 9 Appendix F AC Characteristics Output Vpp 4 5 V to 5 5 V Output Signal Characteristics Vss 0 V Ta 40 C to 85 C 70 pF Parameter Symbol Conditions Unit System Clock Output Timing System clock output cycle time F1 SYSCLK eye 199 e System clock output low pulse width SYSCLK System clock output high pulse width SYSCLK rige 22 System clock output rise time SYSCLK F5 System clock output fall time SYSCLK for Electrical Characteristics IX 175 Chapter 9 Appendix Vpp 4 5 Vto 5 5 V Output Signal Characteristics Vss 0 V Ta 40 C to 85 C 70 pF Data Transfer Signal Output Timing 1 on vee Pur 1 DS delay time 2 d d 9 5 tc EE Capacitance Parameter Symbol Conditions Unit wee Address hold time 1 A23 0 A23 16 Address hold time 2 t A23 0 A23 16 BUR Address hold time 3 F1 F11 Address Data hold time 1 t AD15 0 AM F12 Address Data hold time 2 t AD15 0 ADAS F13 Data delay time 1 t Fig 9 3 D15 0 PBI Fig 9 4 Wm delay time 2 Fig 9 5 bs time 3 1 Data hold time 1 D15 0 Data hold time 2
123. x 00FE34 a gt R sou TM6IOA 6 Capture x 00FE36 8 e gt aL 5 Sn 5 I 5 capture TM6CB x 00FE38 Match J 9 gt TM6IOB TM6CBX 1 R MD INLD mE ONE Y TM6MD x 00FE30 Figure 4 1 20 Timer 6 Block Diagram TM7IC ECLR Timer4 5 gt TM7BC x 00FE42 SYSCLK EN L N dE U D m Control Load When 7 0 LP ASEL S UD 7 00 44 R e TM7IOA gt TM7CAX 4 gt gt Capture xooFE46 5 e gt R Sz E 1 Capture TM7CB x 00FE48 Match Q TM7IOB TM7CBX gt T xO0FE4A 9 R MD NLD 3 ONE y TGE gt TM7MD x 00FE40 Figure 4 1 21 Timer 7 Block Diagram Chapter 4 Timers Counters Timers IV 79 Chapter 4 Timers Counters This verification is unnecessary immediately after a reset IV 80 8 bit Timer Setup Examples 4 2 8 bit Timer Setup Examples 4 2 1 Event Counter Using 8 bit Timer The event counter setup procedures for Timer 0 to Timer 5 are the same In this example timer 2 counts the rising edge of the 2 pin input four times and generates an interrupt at underflow 1 Set the interrupt enable flag IE of the processor status word PSW to 1 2 Verify that counting is stopped using the timer 2 mode register TM2MD
124. x 00FFE5 Port 5 Input Output Control Register 8 bit access register 16 bit access is possible from even address Setting 1 to bits 7 6 and bits 3 0 of this register is not allowed dur ing processor mode P6DIR x OOFFE6 Port 6 Input Output Control Register 8 16 bit access register Setting 1 to bits 3 1 of this regis ter is not allowed during proces sor mode P7DIR x OOFFE7 Port 7 Input Output Control Register 8 bit access register 16 bit access is possible from even address P8 P8 P8 P8 PB P8 PB DIR6 DIRS DIR4 DIRS DIR2 DIR1 DIRO R W R W R W R W R W RW R W 0 1 0 1 7 0 Each Pin Input Output of Port 8 0 Input 1 Output P9 P9 P9 P9 P9 P9 P9 P9 DIR6 DIRS DIR4 DIRS DIR2 DIR1 DIRO R W R W R W R W R W R W R W R W 04 0 1 7 0 Each Pin Input Output of Port 0 Input 1 Output PA DIRS DIR4 DIR3 DIR2 DIR1 DIRO R R R W R W R W RW RW R W 5 0 Each Pin Input Output of Port 0 Input 1 Output Chapter 9 Appendix P8DIR x 00FFE8 Port 8 Input Output Control Regist
125. 0 15 14 13 12 11 10 9 8 6 5 2 1 0 In the MN102L series the data is VR input to the upper pins of D15 to D08 1 0 MEMMD 1 x 00FC32 15 14 13 12 11 10 9 8 6 5 2 1 0 WAIT1 WAITO 1 0 1 MEMMD3 x 00FC36 15 14 13 12 11 10 9 8 6 5 2 1 0 BMOD WAIT1 WAITO External Memory Connection Example II 43 Chapter 2 Bus Interface B ROM RAM Access Timing with 16 bit Bus Width OSCI SYSCLK A23 00 Dotted lines WEH and WEL show waveforms when WE width short D15 08 ening bit15 is set D07 00 AG0 H 00 CS RE WEH WEL OSCI SYSCLK 23 00 D15 08 D07 00 cs RE WEH WEL II 44 External Memory Connection Example gt m Read 16 bit Write 8 bit Write 8 bit Write High Side Low side Figure 2 2 3 No Wait Access Timing with 16 bit Bus Width
126. 0 timer 0 divides SYSCLK by 250 and timer 2 and timer 3 divide SYSCLK by 40 000 8 bit Timer 16 bit Timer MEE Timer 0 gt Timer2 3 gt Interrupt Request 2 Divided by 250 Divided by 40000 Figure 4 2 4 Clock Output Configuration 2 1 Set the interrupt enable flag IE of the processor status word PSW to 1 2 Enable interrupts At the same time clear all prior interrupt requests Set GA4LV 2 0 bits of the maskable interrupt control register 4 G4ICR to the interrupt level of 6 to 0 TM3IR and to 0 1 respectively For example write x 4200 to the G4ICR register Thereafter an interrupt oc curs when timer 3 underflows G4ICR x 00FC48 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 G4 G4 5 5 IRQ3 SC1RISC1T SC1R SC1T LV2 LV1 LVO IE IE IE IR IR IR IR ID ID ID ID 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Timer 0 Setup 3 Verify that timer 0 counting is stopped using the timer 0 mode register TMOMD TMOMD x 00FE20 7 6 5 4 3 2 1 0 TMO TMO TMO TMO EN LD 61 so 1 0 2 timer 0 divisor Since timer 0 divides SYSCLK by 250 set the timer 0 base register TMOBR to 249 The valid range for TMOBR is 1 to 255 TMOBR 00 10 7 6 5 4 3 2 1 0 0 0 0
127. 0 Input 1 Output Setting 1 is allowed only when port 0 is used 7 6 5 4 3 2 1 0 P1 DIR 5 5 P1 Port 1 Input Output o o 10 oA Control Register 8 bit access register 16 bit access is possible 0 All Pin Input Output of Port 1 0 Input from even address 1 Output Setting 1 is allowed only when port 1 is used IX 236 Data Appendix P DIR4 DIRO R R RW R R R R W 0 0 0 0 1 0 0 0 0 1 4 Bits 7 4 Input Output of Port 2 0 Input 1 Output 0 Bits 3 0 Input Output of Port 2 0 Input 1 Output DIR6 DIRS DIR4 DIRS DIR2 DIR1 DIRO R W R W R W R W RW R W RW R W 0 1 7 0 Each Pin Input Output of Port 3 0 Input 1 Output P4 DIR7 0186 DIRS DIR4 DIRS DIR2 DIR1 DIRO R W R W R W R W R W RW R W 01 0 1 0 1 7 0 Each Pin Input Output of Port 4 0 Input 1 Output Chapter 9 Appendix P2DIR x O0FFE2 Port 2 Input Output Control Register 8 16 bit access registe
128. 1 2 3 4 0 1 2 3 Clock Output CLRBC TMnCB 3 1 S R TMnIOA TMnIOB me mind Figure 4 3 5 Two phase PWM Timing in Double Buffer Mode L 16 bit Timer Setup Examples IV 95 Chapter 4 Timers Counters Use the MOV instruction to set the data and always use 16 bit write operations Stop TM7BC counting and initial ize clear TM7BC and RS F F If this step is omitted TM7BC not count during the first cycle IV 96 16 bit Timer Setup Examples 4 3 4 One phase Capture Input Using 16 bit Timer The one phase capture input setup procedures for timer 6 and timer 7 are same except the up down counting selection In this example timer 7 divides SYSCLK by 65536 and measures how long the TM71OA input is high An interrupt occurs on the capture and the width where the TM71OA input is high is calculated by the instruction TMnCB TMnCA W interrupt Enable Setup 1 Enable interrupts At the same time clear all prior interrupt requests Set G7LV 2 0 bits of the G7ICR to the interrupt level of 6 to 0 TM7BIR 7 and TM7BIE to 0 and 1 respectively For example write x 4400 to the G7ICR register Thereafter an interrupt occurs when the timer
129. 1 Use D07 to D00 as general purpose ports A15 to A00 015 to D08 P3DIR P3MD Use A23 to A16 as general purpose ports PODIR to P2DIR P4DIR and POMD to P2MD P4MD are 16bit same as those in the above 16 bit bus width of No 1 Use A23 to A16 as general purpose ports D15 to D00 P3DIR and P3MD are same as those in the above 8 bit bus width PODIR to P3DIR and POMD to P3MD are same as those No 11 Up to 128k bytes 8bit All Spaces in the above 8 bit bus width of No 10 Use D07 to D00 as general purpose ports A16 to A00 D15 to D08 P4DIR 0 P4MD Use A23 to A17 as general purpose ports PODIR to P3DIR and POMD to P3MD are same as those 16bit in the above 16 bit bus width of No 10 Use A23 to A17 as general purpose ports 215 to DOO P4DIR and P4MD are same as those in the above 8 bit bus width PODIR to P3DIR and POMD to P3MD are same as those No 12 Up to 256k bytes 8bit All Spaces in the above 8 bit bus width of No 10 Use D07 to D00 as general purpose ports A17 to A00 015 to D08 P4DIR T To o P4MD Use A23 to A18 as general purpose ports PODIR to P3DIR and POMD to P3MD are same as those 16bit in the above 16 bit bus width of No 10 Use A23 to A18 as general purpose ports 015 to D00 P4DIR and P4MD are same as those in the above 8 bit bus width PODIR to P3DIR and POMD to P3MD are same as those No 13 Up to 512k bytes 8bit Al
130. 10 9 CB8 CB7 6 5 2 1 TM7CA is captured on the rising edge of TM7IOA and TM7CB is captured on the falling edge of Interrupt Processing and Width Calculation 6 Execute interrupt processing The interrupt processing specifies the inter rupt group and vector and clears IRFn 7 Calculate the width Store the TM7CA value and TM7CB value to the data register and subtract TM7CA from TM7CB Ignore C and V flags The width is calculated correctly even though the TM7CA value is greater than the TM7CB value by setting TM7LP to 0 The following figure shows 000A 0007 0003 or 3 cycles TM7EN 7 0 0 1213 4 5 6 7 8 9 10 11 12 SYSCLK tit tt 66196 619 TWA 25902202122 TWeB io GA i PT FRA an TM7IOA Shy doc biel ATE i mm 3 Cycles Figure 4 3 6 One phase Capture Timing Chapter 4 Timers Counters Load the 7 value and TM7CB value during interrupt pro cessing The width is calculated by ignor ing flags even though the TM7CA value is greater than the TM7CB value 16 bit Timer Setup Examples IV 97 Chapter 4 Timers Counters Use the MOV instruction to set the
131. 16 40 P41 A17 TTL CMOS Yes Programmable Hi Z Hi Z Undefined Hi Z at A17 Hi Z at A17 41 P42 A18 CMOS Yes Programmable Hi Z Hi Z Undefined Hi Z at A18 Hi Z at A18 42 P43 A19 TTL CMOS Yes Programmable Hi Z Hi Z Undefined Hi Z at A19 Hi Z at A19 44 P44 A20 AN4 Analog CMOS No Programmable Hi Z Hi Z Undefined Hi Z at A20 Hi Z at A20 45 P45 A21 AN5 CMOS No Programmable Hi Z Hi Z Undefined Hi Z at A21 Hi Z at 21 46 P46 A22 STOP AN6 Analog CMOS No Programmable Hi Z Hi Z Hi Z Hi Z at A22 Hi Z at A22 47 P47 A23 WDOUT AN7 CMOS No Programmable Hi Z Hi Z Hi Z Hi Z at A23 Hi Z at A23 48 P80 TMOIO CMOS Yes No Hi Z Hi Z Hi Z 8 49 P81 TM1IO CMOS Yes No Hi Z Hi Z Hi Z 3 50 P82 TM2IO TIL CMOS Yes No Hi Z Hi Z Hi Z x IX 248 Data Appendix Chapter 9 Appendix 51 83 TIL CMOS Yes No Hi Z Hi Z Hi Z 52 P84 TM4IO TTL CMOS Yes No Hi Z Hi Z Hi Z 53 P85 TMSIO CMOS Yes No Hi Z Hi Z Hi Z 54 VDD 55 86 6 CMOS Yes No Hi Z Hi Z Hi Z 56 P87 TM6IOB TTL CMOS Yes No Hi Z Hi Z Hi Z B 57 90 6 CMOS Yes No Hi Z Hi Z Hi Z 58 P91 TM7IOA CMOS Yes No Hi Z Hi Z Hi Z t 59 P92 TM7IOB CMOS Yes No Hi Z Hi Z Hi Z gt 60 P93 TM7IC TIL CMOS Yes No Hi Z Hi Z Hi Z b 61 vss 62 P94 AN0 Analog CMOS No No Hi Z Hi Z Hi Z 63 P95 AN1 CMOS
132. 2 Wait Cycles 11 Handshake 15 14 13 12 1 10 9 8 7 5 4 83 2 1 1 RESHT BMOD WAIT WAIT 1 0 RW R R R R R R R R R R RWI R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 o 0 0 0 o 01 15 Block 2 RE pulse width 0 Disable shortening 1 Enable 8 Bus Mode for Block 2 1 0 Cycle for Block 2 IX 194 Data Appendix 0 16 bit Bus Mode 1 8 bit Bus Mode Select the same bus width as the bus width set by WORD pin 00 No Wait 01 1 Wait Cycle 10 2 Wait Cycles 11 Handshake MEMMD1 x 00FC32 Memory Mode Control Register 1 16 bit access register Set any values when block 1 is unused MEMMD x 00FC34 Memory Mode Control Register 2 16 bit access register Set any values when block 2 is unused Chapter 9 Appendix 15 14 13 12 8 7 5 3 2 MEMMD3 REHT Bob has x 00FC36 RW R R R R R R RW R R R R R R R W Mode Control EE EE o EEE NESE Register 3 o Loa egister 16 bit access register 15 Block 3 RE pulse width 0 Disable shortening 1 Enable Set any values when block 3
133. 2 pins to the serial writer Connect and Vss to 5 V 0 V power supply Output and Vss to the writer which determines the voltage level Set OSCI and OSCO to self excited or separately externaly excited Input pins without connection instruction are Don t care pins and fix these pins to Vpp or Vss Leave output pins without connection instruction to OPEN IX 268 Flash EEPROM Version Chapter 9 Appendix 9 6 7 Configuring the System for Onboard Serial Programming 1 Entire system configuration Target board AC adapter power source Target board RS232C EF Serial writer Figure 9 6 6 Configuring System for Onboard Serial Programming pc containing the program data sends the program to the serial writer through RS 232C Through serial communication the serial writer programs the flash memory inside the microcontroller on the target board VDD source is necessary only when it supplied to the target board 2 Target board serial writer connection Target board Serial writer Vpp 5 V G O SCL1 ERE SDA1 Microcontroller Figure 9 6 7 Pin Configuration on the Target Board 3 Pins eVDD 4 5 V to 5 5 V power supply External power eVpp level detection Target board VDD level detection pin eRST Reset Clock supply for se
134. 2BC Count 0 Disable 1 Enable 6 TM2BR Setup 0 Disable 1 Load TM2BR to 2 Reset the 1 2 divisor circuit Fix TMIO output to O 1 0 Clock Source Selection 00 TM2IO pin clock Event timer 01 Timer 1 cascade 10 Timer 0 output clock 11 System clock 7 6 5 4 3 2 1 0 TM3 TM3 TM3 EN LD 51 80 R W RW R R W RW 0 0 0 0 0 0 0 0 01 01 0 0 0A 7 Count 0 Disable 1 Enable 6 TM3BR Setup 0 Disable 1 Load TM3BR to TM3BC Reset the 1 2 divisor circuit Fix TMIO output to 0 1 0 Clock Source Selection 00 TM3IO pin clock Event timer 01 Timer 2 cascade 10 Timer 0 output clock 11 System clock Chapter 9 Appendix TM2MD x 00FE22 Timer 2 Mode Register 8 16 bit access register TM3MD x 00FE23 Timer 3 Mode Register 8 bit access register 16 bit access is possible from even address Data Appendix IX 221 Chapter 9 Appendix TMAMD TM4 TM4 EN LD 51 50 x 00FE24 RW R R R R R W RW Timer 4 Mode Register 0 1 0 1 0 0 0 0 0 1 0 1 7 TM4BC Count 6 TM4BR Setup 1 0 Clock Source Selection TMS 5 5 5 EN LD 1 50 R W R R R R R W RW 0 1 0 1 0 0 0 0 0 1 0 1 7 TM5BC Count 6 TM5BR Setup 1 0 Clock Source Selection IX 222 Data Appendix 8 16 bit access
135. 45 4 gt 21 5 45 RST 82 44 gt A20 AN4 P44 E 83 43 4 Vss ADOO lt 84 42 w A19 P43 AD01 85 41 A18 P42 AD02 lt 86 40 A17 P41 AD03 87 O2LF61 G 39 A16 P40 AD04 88 38 P37 05 gt 89 TOP VI EW 37 P36 90 36 w P35 AD07 lt 91 35 P34 4 esa 100 pim LQFP AD09 94 32 gt P32 AD10 95 31 1 AD11 96 P30 AD12 97 29 P27 4 P26 P25 AD13 lt 98 AD14 99 AD15 100 26 P24 0 1 e 3 4 5 6 4 25 P50 CS0 5 XI 20 XO 21 22 OSC 23 OSCO 24 RE lt 2 P62 WEL lt Vss 19 ALE ALE 51 51 lt 6 P52 CS2 7 P54 BREQ 9 P55 BRACK lt SYSCLK lt 18 53 053 lt 8 P60 WAIT 1 Figure 2 1 3 Memory Expansion Mode Address Data Shared Pin Configuration 72 SBO1 P75 74 70 SBT1 P73 69 SBOO P72 68 SBIO P71 67 SBTO P70 66 lt 65 4 AN3 P97 64 lt AN2 P96 63 lt AN1 P95 62 ANO P94 61 4 Vss
136. 6 5 4 3 2 1 0 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 PB DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIRO MD7 MD6 MD5 MD4 MD3 MD2 1 MDO Timer 1 Setup 7 Verify that timer 1 counting is stopped using the timer 1 mode register TM1MD TM1MD 21 7 6 5 4 3 2 1 0 1 TM1 1 TM1 EN LD i 51 so 0 0 1 0 8 Set the timer 1 divisor Since timer 1 divides timer 0 output by 3 set the timer 1 base register to 2 The valid range for TMOBR is 1 to 255 TM1BR x O0FE11 7 6 5 4 3 2 1 0 1 TM1 1 1 TM1 TM1 TM1 7 5 BR2 BR1 BRO 0 0 0 0 0 0 1 0 9 Load the TM1BR value to TM1BC To do this set TM1LD and TM1EN to 1 and 0 resepctively At the same time select the clock source Chapter 4 Timers Counters If selecting 1 of divisor set 0 to the timer 0 base register TMOBR once again after step 5 The first count is the value set in step 2 but the second count becomes 1 For example if 0 is setto TMOBR in step 2 the first count is 257 and the second count becomes 1 This verification is unnecessary immediately after a reset 1 Changing the clock source while controlling count operation will corrupt the binary counter value 8 bit Timer Setup Examples IV 83
137. 60 TM7IC P93 59 7 92 58 lt 7 91 57 TM6IC P90 56 TM6IOB P87 55 TM6IOA P86 54 4 yoo 53 TMSIO P85 52 TM4IO P84 91 9 TM3IO P83 AMIN AMIN 75 r T 2 m 76 a TM210 P82 PA1 IRQ1 lt 77 TM110 P81 PA2 IRQ2 78 TMOIO P80 PA3 IRQ3 79 A23 WDOUT AN7 P47 PA4 IRQ4 1 80 a gt A22 STOP AN6 P46 81 A21 AN5 P45 S RST 82 44 lt gt A20 AN4 P44 83 43 Vss P00 D00 lt 84 42 4 h A19 P43 85 41 w 18 42 02 002 lt 86 40 A17 P41 P03 D03 lt 8 M N 1 O2LF61 G 9 4 A16 P40 e P04 D04 88 38 lt A15 P37 pos Dos rj TOP VIEW vem P06 D06 lt 90 36 A13 P35 P07 D07 lt 91 35 a A12 P34 4 100 pin LQFP Dog 94 32 4 A10 P32 010 95 31 A09 P31 011 lt 96 4 gt A08 P30 012 97 29 4 A07 P27 013 98 lt A06 P26 014 lt 99 4 M A05 P25 015 t 100 26 gt A04 P24 ND 0 1 2 3 4 5 6 7 8 9 25 gt T RE lt 2 XI 20 P62 WEL 3 4 344 VoD SYSCLK XO lt
138. 8 D 7 0 Ka 160 D15 D00 17 00 07 0 16 00 SRAM ASIC WAIT CS WEL Figure 2 2 10 Memory Connection Example with 16 bit Bus Width Address Data Shared Mode MEMMDO x 00FC30 15 14 18 12 11 10 8 Ac 10 WAIT1 WAITO 0 1 MEMMD1 x 00FC32 15 14 13 12 11 10 8 5 4 3 1 BMOD WAIT1 WAITO 1 0 1 x 00FC36 15 14 13 12 11 10 8 5 WAIT1 WAITO II 50 External Memory Connection Example Chapter 2 Bus Interface B Memory System with 8 bit Bus Width in All Areas The following is the example of connecting the 4 Mbit ROM 512 kilo words x 8 bits the 1 Mbit SRAM 128 kilo words x 8 bits and the ASIC with 8 bit bus width to the CSO area 2 wait cycles fixed the CS1 area 1 wait cycle fixed and the CS3 area handshake respectively A18 A16 AD15 AD08 AD07 AD00 18 16 15 8 ALE 7 0 18 0 CSO 07 0 A18 A00 ROM C81 1 07 0 A16 A00 SRAM WAIT 53 ASIC WAIT CS OE WE WEH
139. 8 bit Write High Side Low Side Figure 2 2 12 Fixed Wait Access Timing with 16 bit Bus Width OSCI SYSCLK A23 A16 AD15 AD08 AD07 AD00 ALE cs RE WEH WEL WAIT Figure 2 2 13 II 52 External Memory Connection Example i Address Data i Address Data ddress Data Address I id ra Read DES d Write m Handshake Access Timing with 16 bit Bus Width Chapter 2 Bus Interface B ROM RAM Access Timing with 8 bit Bus Width pinnin SYSCLK A23 A16 Address Data Address Data Address Data Address Data AD15 AD08 I 55 Address Address SS AD07 AD00 AD00 0 000 1 AD00 1
140. 81808 8 bytes Reset start 0x81810 8 bytes Interrupt address 0x81818 User program area Figure 9 6 4 Internal flash EEPROM address space 1 Serial writer load program area These 6 KB of ROM starting at address 0x80000 holds the load program for the serial writer This area is write erase protected in the hardware 2 Branch instruction to reset service routine Normally reset servicing starts at address 0x80000 but the soft branch instruction in the serial writer load program branches to 0x81808 This adress must hold a JMP instruction pointing to the real start address for the reset service routine 3 Branch instruction to interrupt service routine Normally interrupt servicing starts at address 0x80008 but the soft branch instruc tion in the serial writer load program branches to 0x81810 This adress must hold a JMP instruction pointing to the real start address for the reset service routine 4 User program area This area holds user program Flash EEPROM Version IX 265 Chapter 9 Appendix 4 Internal flash EEPROM address space iFlash serial programming control register Register FCREG Address x 00FF70 Use Control of internal flash EEPROM programming Bino 15 1211 18 7 e 12 10 Bit Access Rw Rw k RAV RAW R W Atreset 0 1 2 3 4 5 5 6 Res
141. 886 7 346 3815 886 7 236 8362 e Korea Sales Office Panasonic Industrial Korea Co Ltd PIKL Kukje Center Bldg 11th Fl 191 Hangangro 2ga Youngsan ku Seoul 140 702 KOREA Tel 82 2 795 9600 Fax 82 2 795 1542 050402 Printed in JAPAN
142. 9 P9DIR4 P9OUTA P94 ANO P9IN4 To A D Converter P9MD3 P9DIR3 P9DIR7 to 4 P9OUT7 to 4 1 P97 AN3 P9IN7 to 4 P96 AN2 P95 AN1 To A D Converter PA5 Port A is used as the port A general purpose port or interrupt related signal pins ADSEP ADSEP IRQ4 to IRQO At reset this port operates as a general purpose port 4 to input This port can read the level of NMI pin by operating as the port input pin IRQ4 to IRQO PAIN6 and verify an error due to chattering using software PA4P PA3P PA2P PA1P PAOP PADIRS to 0 PAOUTS to 0 4 does not have a pull up resistor ADSEP 4 to 0 IRQ4 to 0 PAINS to 0 IRQ4 to 0 ADSEP Pots 149 Chapter 8 Ports 8 1 2 Control Registers This section describes the port control registers Table 8 1 2 List of Port Control Registers Port 0 Output Register Port 0 Input Register Port 0 Input Output Control Register Port 0 Output Mode Register Port 1 Output Register Port 1 Input Register Port 1 Input Output Control Register Port 1 Output Mode Register Port 2 Output Register Port 2 Input Register Port 2 Input Output Control Register Port 2 Output Mode Register Port 3 Output Register Port 3 Input Registe
143. Address B 8 ATC Transfer End Interrupt ATGEND p Main Program v gt su 7 2 ATC Transfer A Interrupt Service Routine g 4 Serial Interrupt Service Routine Identify that both a serial 2 interrupt and z transfer end interrupt occur ial I Serial Interrupt g Serial Interrupt p ternal FAM 8 SCOTRB O lt gt 5 ATC Transfer End Interrupt Main Program ATCBC Value i S ATC Transfer A 5 gt Interrupt Service Routine End Address ATCEND mg ATC Transfer End Interrupt Service Routine The value of C is invalid Figure 7 1 1 ATC Operations VII 137 Chapter 7 ATC Set the value of the internal address for ATC end greater than the value of the ATCBC counter VII 138 7 1 2 Control Registers The ATC contains the ATC control register ATCCTR and the ATC binary counter ATCBC Table 7 1 2 List of ATC Control Registers Control Register ATC Control Register ATCCTR x 00FD10 Counter ATC Binary Counter ATCBC x00FD12 The ATC control register ATCCTR sets the transfer direction the internal RAM address for the ATC end and ATC enable In addition the ATC monitors the overrun error generation Overrun Error An overrun error occurs when a next serial 0 reception end interrupt occurs be fore the ATC operation is completed after the serial O
144. Address Data Separate Mode Without Wait IX 182 Electrical Characteristics Chapter 9 Appendix Nis wait cycle N 3 1 x N 1 1 l SYSCLK A23 00 tAD1 01 lt tAH2 CS3 0 tcspR1 tcspF1 tcsHi mi tcsH2 WAIT tWAITS tWAITH twaITS tWAITH twaITS read dios lt tREPWI TREDF1 RE RE short mode E gt write REPNA D15 00 Data gt 1 1 lt 2 WEL WEH Normal WEL WEH twerwi E WE short mode tweDF1 Fig 9 1 4 Data Transfer Signal Timing Address Data Separate Mode With Wait Electrical Characteristics IX 183 Chapter 9 Appendix c mc gt SYSCLK Z ter m Im lt 23 16 01 01 CS3 0 ALE gt tALEDF 2 AD07 00 8bit bus mode lt read gt An Address Dat t 16bit bus mode AT lt 805 4 gt at tREPW3 tREDF2 RE RE short mode LY gt tREPW4 lt write gt AD15 08 AD07 00 16bit bus mode tAp2 Address tADH1 taDH2 WEL WEH Normal WEL WEH WE short mode Fig 9 1 5 Data Transfer Signal Timing Address Data Share
145. An Am the assembler will generate a bit pattern for d8 0 3 This instruction is supported by the assembler For MOV Am d8 An the assembler will generate a bit pattern for d8 0 4 This instruction is supported by the assembler The assembler generates bit patterns for the two instructions MOVBU An Dm and 5 This instruction is supported by the assembler The assembler generates bit patterns for the two instructions MOVBU abs16 Dn and EXTXB Dn IX 250 Instruction Set Instruction Mnemonic MOVB Dn abs16 Operation Dnmeme abs16 Chapter 9 Appendix Machine Code C4 Dn abs16 l abs16 h MOVB Dn abs24 Dn mem8 abs24 F4 44 Dn abs24 l abs24 m abs24 h MOVBU An Dm mem8 An gt Dm 30 An lt lt 2 Dm MOVBU d8 An Dm mem8 An d8 gt Dm F5 30 An lt lt 2 Dm d8 MOVBU d16 An Dm mem8 An d16 gt Dm F7 50 An lt lt 2 Dm d16 l d16 h MOVBU d24 An Dm F4 90 An lt lt 2 Dm d24 l d24 m d24 h mem8 An Di gt Dm F0 80 Di lt lt 4 An lt lt 2 Dm MOVBU abs16 Dn mem8 An d24 gt Dm mem8 abs16 Dn CC Dn abs16 l abs16 h MOVBU Di An D MOVBU abs24 Dn mem8 abs24 Dn F4 C8 Dn abs24 l abs24 m abs24 h EXT Dn Dn bp15 0 x 0000 2MDR F Dn bp15 1 INJA
146. BX are valid only when the timer 6 compare capture register is set to double buffer mode IV 94 16 bit Timer Setup Examples 4 Set the phase difference of timer 6 Since the phase difference is two cycles of prescaler 0 set 1 to the timer 6 compare capture register B TM6CB The valid range for TM6CB is 1 TM6CB TM6CA TM6CB x 00FE38 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6 6 TM6 TM6 TM6 6 6 6 TM6 6 6 6 6 6 6 6 CB15 CB14 CB13 CB12 1 10 9 CB8 CB7 CB6 5 2 CB1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 In the double buffer mode compare TM6BC to TM6CAX The TM6CAX is updated when TM6CAX TM6BC so that TM6CAX remains 0000 be fore TM6BC starts counting Therefore to load the TM6CA value to TM6CAX write the dummy data to TM6CAX The dummy data can be any values TM6CAX x 00FE36 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6 TM6 TM6 TM6 CAX15 CAX14 CAX13 CAX12 11 10 9 CAX8 6 5 CAX3 CAX2 1 6 In the double buffer mode compare TM6BC to 6 The 6 is updated when TM6CBX TM6BC so that TM6CBX remains x 0000
147. DIR1 DIRO MD7 MD6 5 4 MD3 2 MD1 MDO 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Timer 6 Setup 2 Set the operating mode to the timer 6 mode register TM6MD Verify that counting is stopped and an interrupt is disabled Select up counting or down counting Select TM6IOB as the timer 6 clock source TM6MD 00 0 Chapter 4 Timers Counters This verification is unnecessary immediately after a reset Use the MOV instruction to set the data and always use 16 bit write operations 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6 TM6 TM6 6 TM6 6 6 6 6 TM6 6 6 6 6 EN NLD UD1 UDO TGE ONE MD1 MDO ECLR LP ASEL 2 51 SO 0 0 0 0 0 0 0 1 0 1 0 0 1 0 3 Set the timer 6 divisor Since timer 6 divides TM6IOB pin input by 5 set 4 to the timer 6 compare capture register A TM6CA The valid range for TM6CA is 1 to x FFFE TM6CA x 00FE34 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 6 6 6 6 TM6 TM6 6 6 TM6 6 6 6 6 TM6 6 6 CA15 CA14 CA13 CA12 11 10 CA9 CA6 5 CA4 CAO 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Stop TM6BC counting and initial ize clear TM6BC and RS F F 16 bit Timer Setup Examples IV 93 Chapter 4 Timers Counters TM6CAX and TM6C
148. F17 ipu IX 176 Electrical Characteristics Chapter 9 Appendix Vpp 4 5 V to 5 5 V Output Signal Characteristics Vss 0 V Ta 40 C to 85 C 70 pF Data Transfer Signal Output Timing 2 Chip select signal fall delay time 1 lcspr Fig 9 3 to CS3 0 CS3 1 Fig 9 7 select signal rise delay time CS3 0 53 1 Chip select signal fall delay time 2 50 LEE select signal rise delay time 2 50 Capacitance Parameter Symbol Conditions NUM 2 Chip select signal hold time 1 t CS3 0 SSmi 22 signal hold time 2 F2 4 Address latch signal fall delay time ALE F25 Address latch signal pulse width ALE taLerw Address latch signal hold time 1 Address latch signal hold time 2 taLeDF Electrical Characteristics IX 177 Chapter 9 Appendix Vpp 4 5 V to 5 5 V Output Signal Characteristics Vss 0 V Ta 40 C to 85 C CL 70 pF Parameter Symbol Conditions Unit Data Transfer Signal Output Timing 3 Read enable signal fall delay time 1 Fig 9 3 F2 Read enable signal fall delay time 2 Fig 9 5 9 6 Read enable signal fall delay time 3 25 Fig 9 7 20 on Read enable signal rise delay time 1 trena Fig 9 3 to Fig 9 6 15 RE Read enable signal rise delay time 2 tove 0 iREDR2 RE Read enable signal hold time F33 9 RE Fig 9 7 Burst ROM read enable signal fall t dala time BSTRE
149. I O General purpose Port 5 When these pins are used as general purpose Output CS3 CSO Chip Select Output input output ports I O direction control is in bit unit Chapter 8 Ports When connect ROM and SRAM connect CS3 010 CS pin in the memory For memory of CS3 0 in address space refer to 6 Chapter 2 Bus Interface Note that CS0 is not output during internal ROM access During a bus request when BREQ is L level STOP mode or HALT mode these pins will be in a high impedance state but they do not become high impedance state when used as ports PA5 General purpose Port These pins can be used as general purpose input or output port only in single chip mode Input ADSEP Address data separate Chapter 8 Ports or share mode setup In processor mode or memory expansion mode this pin selects address data separate mode or address data share mode Setting this pin to selects address data sepa rate mode and setting this pin to L selects ad dress data share mode Use this pin always as address data separate mode or address data share setup pin in processor mode or memory expansion mode If the setup is changed during operation proper operation is not guaranteed Pin Description I 19 Chapter 1 Overview Table 1 4 1 List of Pin Functions 8 9 Pin Name Input Output Shared Pin Function Description P56 I O General purpose P
150. ITM6BITM6AITM6U LV2 LV1 LVO IE IE IE IE IR IR IR IR ID ID ID ID 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 m ATC Setup 2 Set the lower 10 bits of the internal RAM start address for ATC destination to the ATC binary counter ATCBC ATCBC x 00FD12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATCBC ATCBC ATCBC ATCBC ATCBC ATCBCATCBC ATCBC ATCBC ATCBO 9 8 7 6 8 4 3 2 1 0 0 0 1 0 1 0 0 0 0 0 3 Set the internal RAM end address x 00E0A4 and the transfer direction serial internal RAM and clear the overrun error flag ATCCTR 00 10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATC B EN EF DR 9 8 7 6 8 4 3 2 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 4 Set ATCEN to enable Keep the same setting as step 3 ATCCTR x 00FD10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _ ATC DIR END9 END8 END7 ENDe END5 END4 END3 END2 END 1 ENDO 1 0 0 0 0 1 0 1 0 0 1 0 0 Chapter 7 ATC When a serial reception end in terrupt is enabled a serial recep tion end interrupt occurs each time the 1 word tran
151. Interrupt Enable Flag 000 level 0 to 110 level 6 0 Disable 0 Disable 1 Enable 1 Enable 8 IRQ1 Interrupt Enable Flag 6 A D Conversion End Interrupt Request Flag 5 Timer 1 Underflow Interrupt Request Flag 4 IRQ1 Interrupt Request Flag 2 A D Conversion End Interrupt Detect Flag 1 Timer 1 Underflow Interrupt Detect Flag 0 IRQ1 Interrupt Detect Flag 0 Disable 1 Enable 0 No interrupt requested 1 Interrupt requested 0 No interrupt requested 1 Interrupt requested 0 No interrupt requested 1 Interrupt requested 0 No interrupt detected 1 Interrupt detected 0 No interrupt detected 1 Interrupt detected 0 No interrupt detected 1 Interrupt detected Chapter 9 Appendix G2ICR x 00FC44 Maskable Interrupt Control Register 2 8 16 bit access register Set 1 when the A D conversion ends Set 1 when timer 1 underflows Set 1 when an external interrupt occurs from IRQ1 pin Data Appendix IX 197 Chapter 9 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 G3 5 0 5 TM2 IRQ2 SCOR SCOT TM2 IRQ2 SCOR SCOT 2 IRQ2 LV2 LV1 LVO IE IE IE IE IR IR IR IR ID ID ID ID R R W RW RW R W RW RW RW RW RW R W R W R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 0 1 01 01 0A 0 1 0 1 0 0 1 0 1 0 1 14 12 G
152. L level shumitt gt TM7IC 5 0 V 2 5 0 V e LED ouput C52 Output low voltage2 VDD 5 0V V 34 0 mA leak current Pin 10 Output pushpull Analog input gt ANO as 5 0 V Ms 5 0 V ai LED ouput C58 Output low voltage2 VDD 5 0 V V lou 2 34 0 mA current Chapter 9 Appendix Electrical Characteristics IX 169 Chapter 9 Appendix Vop24 5Vto5 5V Vss 0V Ta 40 C to 85 C Capacitance Parameter Symbol Conditions V Unit Output Pin Output pushpull gt SYSCLK i Voo 5 0 V Output high voltage loH 4 0 MA 5 0 V Output low voltage 40 m Input Pins lt Input CMOS level schmitt trigger gt MODE 155 5 5 V Input Pins 2 lt Input TTL level schmitt trigger gt NMI um 5 5 V OSCI pin XI pin at external clock TUE crystal ceramic self excited oscillation See Figure 1 4 2 to Figure 1 4 3 Pin Capacitance Input output pin IX 170 Electrical Characteristics Chapter 9 Appendix D A D Converter Characteristics Vpp 5 0 V Vss 0 V 25 Symbol Conditions P LL D2 AD conversion relative precision 4 Electrical Characteristics IX 171 Chapter 9 Appendix E AC Characteristics Vpp 4 5 V to 5 5 V Input Timing Conditions Vss 0 V Ta 40 C to 85 C Parameter Symbol ww Unit pap External Clock Input Timing
153. M6CB is not compared to TM6BC the TM6CB value is set 0 1 IV 88 16 bit Timer Setup Examples 4 3 16 bit Timer Setup Examples 4 3 1 Event Counter Using 16 bit Timer The event counter setup procedures for Timer 6 and Timer 7 are same except the up down counting selection In this example timer 6 counts TM6IOB pin input SYSCLK 2 or less 5 MHz or less with 20 MHz oscillaor and generates an interrupt on the second cycle and fifth cycle W interrupt Enable Setup 1 Enable interrupts At the same time clear all prior interrupt requests Set G6LV 2 0 bits of the G6ICR to the interrupt level of 6 to 0 TM6AIR and TM6BIR to 0 TM6AIE and TM6BIE to 1 For example write 046000 to the G6ICR register Thereafter an interrupt occurs when the timer 6 capture A and the timer 6 capture B occur m Timer 6 Setup 2 Set the operating mode to the timer 6 mode register TM6MD Verify that counting is stopped and an interrupt is disabled Select up counting or down counting Select TM6IOB as the timer 6 clock source TM6MD x 00FE30 15 14 13 12 111 10 9 8 7 5 4 2 1 6 TM6 6 6 6 TM6 6 6 6 TM6 TM6 TM6 6 TM6 EN NLD UD1 UDO TGE ONE MD1 MDO ECLR LP 52 51 So 1 1 O 3 Set the timer 6 divisor Since timer 6 divides TM6IOB pin input by 5 set 4 to the timer 6 compare capture registe
154. M6IOB input is sampled on SYSCLK When SYSCLK stops in STOP mode TM6BC counts on the TM6IOB input Select the oscillation clock 4 5 MHz with a 20 MHz oscil lator or less as the event counter clock Figure 4 3 1 shows the example of generating an interrupt during up counting TM6CA 0004 TM6CB 0001 TM6BC 0000 0001 0002 0003 0004 0000 0001 0002 0003 0004 i TM6IOB B A Figure 4 3 1 Event Counter Timing Chapter 4 Timers Counters If this step is omitted TM6BC may not count during the first cycle Do not change other bits in the TM6MD register at the same time 16 bit Timer Setup Examples 89 Chapter 4 Timers Counters Use the MOV instruction to set the data and always use 16 bit write operations Stop TM6BC counting and initial ize clear TM6BC and RS F F IV 90 16 bit Timer Setup Examples 4 3 2 PWM Output Using 16 bit Timer The PWM output setup procedures for Timer 6 and Timer 7 are same except the up down counting selection In this example timer 6 divides SYSCLK by 5 and outputs PWM signal on the fifth cycle The duty is 2 3 Therefore set the divisor of 5 the set value is 4 to the timer 6 compare capture register A and the cycle of 2 the set value is 1 to the timer 6 compare capture m Pin Setup 1 Set the TM6IOA pin to output using the p
155. M7EN to 1 and 0 respectively This enables TM7BC and RS F F Do not change other bits of the TM7MD register 4 Set both TM7NLD and TM7EN to 1 This starts timer 7 Counting starts at the beginning of the next cycle Chapter 4 Timers Counters Thereafter timer 7 is reset asynchronously when is high This allows external synchronization easily It can be used to adjust the motor or to initialize the timer by hardware TM7BC 0000 0001 0002 0003 0004 e e e 9998 Secus T s E saa TM7IC Figure 4 3 11 External Reset Control Timing 16 bit Timer Setup Examples IV 107 Chapter 4 Timers Counters IV 108 16 bit Timer Setup Examples Chapter 5 Serial Interface Chapter 5 Serial Interface 5 1 Serial Interface 5 1 1 Overview This LSI series contains two serial interfaces Each serial interface transmits and receives the data in the synchronous mode asyn chronous mode and mode The maximum baud speed in syn chronous mode is SYSCLK 4 The maximum baud speed in asyn chronous mode is 312 500 bps with a 20 MHz oscillator The baud speed can be set to 312 500 bps or more by changing the oscillation frequency Timer 2 Underflow Timer 3 Underflow Transmis
156. MOV imm24 An imm24 Dn imm24 8 024 An Dm 9 024 An Dm MOVB 424 Dm 424 abs24 Dn MOVB abs24 Dn MOVBU abs24 Dn D MOV abs24 An JMP JSR E label24 label24 F MOV d24 An Am IX 258 Instruction Map Chapter 9 Appendix 3 byte instructions Byte 1 F5 Second byte Upper Lower 0 1 2 3 4 5 6 7 8 9 A B D E F 0 imm8 Dn BTST imm8 Dn OR imm8 Dn ADDNF imm8 An 1 MOVB Dm d8 An 2 MOVB d8 An Dm 3 MOVBU d8 An Dm 5 MOVX Dm d8 An 7 MOVX d8 An Dm 4 byte instructions Byte 1 F7 Second byte Upper Lower 1 2 3 4 5 6 7 8 9 A B D E F 0 AND imm16 Dn BTST imm16 Dn ADD imm16 An SUB imm16 An 1 ADD imm16 Dn SUB imm16 Dn 2 MOV An abs16 3 MOV abs16 An 4 OR imm16 Dn imm16 Dn XOR imm16 Dn 5 MOVBU 416 An Dm 6 MOVX Dm d16 An 7 MOVX d16 An Dm 8 MOV Dm d16 An 9 MOVB Dm d16 An A MOV Am d16 An B 416 An Am C MOV d16 An Dm D MOVB d16 An Dm E F Ver 2 1 2001 03 15 Instruction Map 259 Chapter 9 Appendix Setting the MEMMDO register and the MEMCTR register must follow this step If this step is not fol lowed writing to the MEMCTR register cannot be guaranteed
157. Mode Without Wait IX 184 Electrical Characteristics x N 1 Chapter 9 Appendix Nis wait cycle N21 SYSCLK er tALEPW lt tALEDF sl ER TALEH2 AD07 00 Address 8 bit bus mode lt read gt AD15 08 AD07 00 16 bit bus mode tAD2 twaITS tWAITH tAH2 uto ag 2 Dat a gt taps lt WE short mode write AD15 08 AD07 00 16 bit bus mode WEL WEH Normal WEL WEH WE short mode twepr md tREDR tREDF2 i gt Data 2 gt twePve gt Fig 9 1 6 Data Transfer Signal Timing Address Data Share Mode With Wait Electrical Characteristics IX 185 Chapter 9 Appendix SYSCLK With Penalty X KK K ROM read Penarty cyc NotROM read 50 tcspFa CS3 1 Without Penalty ROM read 50 1 5 CS3 1 BSTRE read RE write D15 00 tBREDF ROM read ROM read tcspR2 tREDR2 tcspF1 icspF1 tcspRi tREDR NotROM ac ess tee 0 94 gt CSDR2 tcspR1
158. NO 1 128164 32 16 8 AN2 ANS 5 AN6 AN7 zx gt x c lt gt O gt O gt gt O VDD Vss Storage for Dat Conversion EH Shift Registers t r State Information Von Sie ANCTR Data Bus vss x AN7BUF ANOBUF x SYSCLK Divider Eight 8 bit INC Registers f Figure 6 1 7 Analog Interface Block Diagram VI 128 AnalogInterface 6 1 2 Control Registers The A D converter contains the A D conversion control register ANCTR and the A D conversion data buffers ANnBUF correspond ing to channel 7 to channel 0 AN7 pin to ANO pin Table 6 1 2 List of A D Conversion Control Registers Control Register A D Conversion Control Register ANCTR 00 0 Data Buffers A DO Conversion Data Buffer A D4 Conversion Data Buffer ANOBUF x 00FDA8 ANA4BUF x00FDAC38 A D1 Conversion Data Buffer A D5 Conversion Data Buffer AN1BUF x 00FDA9 ANSBUF x 00FDAD A D2 Conversion Data Buffer A D6 Conversion Data Buffer AN2BUF x 00FDAA AN6BUF x 00FDAE A D3 Conversion Data Buffer A D7 Conversion Data Buffer AN3BUF x 00FDAB AN7BUF x 00FDAF The A D conversio
159. No No Hi Z Hi Z Hi Z 64 P96 AN2 Analog CMOS No No Hi Z Hi Z Hi Z 65 P97 AN3 CMOS No No Hi Z Hi Z Hi Z d 66 VDD VPP 67 P70 SBTO CMOS Yes Programmable Hi Z Hi Z Hi Z n 68 P71 SBIO TTL CMOS Yes Programmable Hi Z Hi Z Hi Z 69 72 5800 CMOS Yes Programmable Hi Z Hi Z Hi Z d 70 73 5 CMOS Yes Programmable Hi Z Hi Z Hi Z d 71 P74 SBI1 CMOS Yes Programmable Hi Z Hi Z Hi Z 72 P75 SBO1 TTL CMOS Yes Programmable Hi Z Hi Z Hi Z n 73 Pull up 74 Pull up 75 NMI Yes No NMI NMI NMI NMI NMI 76 TTL CMOS Yes Hi Z Hi Z Hi Z 77 PA1 iRQ1 CMOS Yes Programmable Hi Z Hi Z Hi Z 78 PA2 IRQ2 TTL CMOS Yes Hi Z Hi Z Hi Z T 79 PA3 IRQ3 CMOS Yes Programmable Hi Z Hi Z Hi Z t d 80 PA4 IRQ4 TTL CMOS Yes Programmable Hi Z Hi Z Hi Z n 81 PA5 ADSEP CMOS Yes No Hi Z Highinput Low Input L 82 RST CMOS Yes Always Low Input Low Input Low Input High High 83 VDD 84 P00 D00 AD00 TIL CMOS No Programmable Hi Z Hi Z Hi Z Hi Z except 00 2 except 85 P01 D01 AD01 CMOS No Programmable Hi Z Hi Z Hi Z Hi Z except Hi Z except P01 86 P02 D02 AD02 TIL CMOS No Programmable Hi Z Hi Z Hi Z Hi Z except 2 Hi Z except P02 87 P03 D03 AD03 CMOS No Programmable Hi Z Hi Z Hi Z Hi Z except Hi Z except 88 P04 D04 AD04 TIL CMOS No Programm
160. OD 2 LN 2 1 SB POD 51 SO 1 1 0 1 1 5 1 1 1 1 0 1 0 1 1 1 Data Transmission 3 Load the data to the serial 0 transmit receive register This allows the data to output The SBO pin output changes with 1 8 cycles delay of the falling edge of the SBT pin output Chapter 5 Serial Interface When selecting P70 and P72 to IC mode by the serial 0 control register these pins becomes out put mode Therefore they should be to input when they are used as ports In this example select the slave response Set both the transmission enable flag and the reception enable flag to 1 After transmission both SBO pin output and SBT pin output stay low Serial Interface Setup Examples V 121 Chapter 5 Serial Interface An interrupt a serial 0 transmis sion end interrupt or a serial 0 re ception end interrupt or polling the serial status register identifies the transmission end Polling the reception state flag during PC mode is prohibited An interrupt a serial 0 transmis sion end interrupt or a serial 0 re ception end interrupt or polling the serial status register identifies the reception end Polling the reception state flag during PC mode is prohibited 4 After transmission ends read the dummy data of the serial 0 transmit receive register SCOTRB 5 Read the serial 0 status register and verify the parity error If a parity error occurs the response is obtained f
161. PU status signal pin At reset this port operates as a general purpose 45 to P44 port input during other modes except processor mode and as A21 to A16 pins P47 A21 to A20 and P46 operate as general purpose input during processor mode During proces 5 to sor mode P4MD of P45 to P40 is invalid See 2 2 1 Memory Expansion Mode P46 Address Data Separated Mode and 2 2 3 Memory Expansion Mode Address A22 6 Data Shared Mode for port setting during memory expansion mode STOP P47 AMP A23 AN7 Address Data Output Control WDOUT Bus Controller P4DIR3 to 0 P4MD3 to 0 P4OUT3 to 0 P43 to 40 Address Data 19 16 Bus Controller P4IN3 to 0 VIII 144 Ports Chapter 8 Ports Table 8 1 1 Port Functions 4 of 8 Pin Shared Pin Function AHP Address Data Output Control Bus Controller P4DIR5 to 4 P4MD5 to 4 P40UT5 to 4 P45 to 44 Address rRl T A21 to 20 AN5 to 4 P4IN5 to 4 To A D Converter AHP Address Data Output Control Bus Controller P4DIR7 to 6 P6MD7 to 6 P4MD7 to 6 P40UT7 to 6 P47 to 46 Address _ A23t0 22
162. Status Register Serial 1 Status Register SCOSTR x 00FD83 SCISTR x 00FD93 The serial control register SCnCTR sets the operating conditions for serial inter face This register controls clock source selection parity bit selection protocol selection and transmit receive enable The transmit data is written to the serial transmit receive register SCnTRB while the receive data is written to the SCnTRB register The transmission starts at the end of the first cycle or second cycle of the transfer clock timer 2 underflow or timer 3 udnerflow after the data is written to SCnTRB The serial transmission is operated in double buffer mode After the reception is completed the data is set to the SCnTRB register The receive data is loaded when an interrupt occurs or the SCnRXA flag of the SCnSTR register is 1 The serial status register SCnSTR reads the status of error detection of serial interface An overrun error occurs when the next data is received before the received data is loaded by SCnTRB An error does not occur on the next cycle by reading the SCnTRB register The overrun error data is updated when the last bit the 7th bit or the 8th bit of the data is received A parity error occurs when the parity bit is 1 although it is supposed to 0 when the parity bit is O although it is supposed to 1 when the parity bit is odd although it is even and when the parity bit is even although it is supposed to set odd The parity error data is
163. The MN102L series can respond quickly to interrupt handling even dur ing the execution of the instruction with long execution cycles by sus pending it After an interrupt occurs the program moves to the interrupt handler within 11 cycles or less The MN102 series enhances real time control performance using the interrupt handler which adjusts interrupt handling speed depending on user requirements Address calculation Execute the code Mainprogram Interrupt Instruction 1 processing program Instruction 2 Interrupt request Instruction 3 Instruction 4 Overview I 3 Chapter 1 Overview Overview 6 Flexible Interrupt Control Structure The interrupt controller is divided into eight groups Group 0 is reserved for NMI and supports a maximum of four vectors for each group in total of 26 vectors Each group can be set to one of seven priority levels This provides the software design flexibility and accurate control The CPU is compatible with software from previous Panasonic peripheral modules 7 High speed high functionality external interface The MN102L series provides DMA handshaking bus arbitration and other func tions that ensure a fast efficient interface with other devices 8 C Language Development Environment The MN102L series contains highly efficient C compiler and simple hardware optimized for C language programming With this advantage this series improves development environment for C lan
164. Timer 7 Set A TM7CB x 00FE48 RW Timer 7 Compare Capture Register B TM7CBX x 00FE4A Timer 7 Compare Capture Register Set B 4 1 3 Timer Block Diagram This section describes block diagrams of timer O to timer 7 Data Bus M 8 8 lt 00 10 Timer 0 Base Register TMOBR Load gt Reload lt 00 20 lt 00 00 2 2 Zig Timer 0 Binary Counter 55 1908 TMOBC Interrupt z o pepe Controller TMOMD 7 Clock Source for Timer1 to Timer 5 Y 1 2 Y Reset 4 pin pin 0 SYSCLK 128 1 SYSCLK 2 Low speed clock 4 l h Selector Figure 4 1 14 Timer 0 Block Diagram Data Bus 8 8 X 00FE11 Timer 1 Base Register TM1BR Load Reload A D Conversion lt 8 Controller x 00FE01 2 Timer 1 Binary Counter d L i mop TM1BC 4 nterrup 210 Underflow Controller gt 1 Y gt 1 2 Y Reset ITM1IO TM1IO pin h 0 Low speed 4 gt 1 Timer 0 Y 2 SYSCLK 3 Selector Figure 4 1 15 Timer 1 Block Diagram Chapter 4 Timers Counters IV 75 Timers
165. Transmission Block Diagram Key information Summary Introduction to the section Precautions and warnings 1 Use a 8 bit timer to set the transmit clock t Chapter 5 2 3 Serial Clock Operation Example Important information from the text then the next data is written to the SCOTRB register If polling the data must be written to the SCOTRB register after verifying that the SCOTBY flag of the serial O status register SCOSTR is 0 References References for the main text MN1021617 F1617 161 About This Manual 1 Precautions are listed in case Be sure to read these of lost functionality or damage Finding Desired Information This manual provides four methods for finding desired information quickly and easily 1 An index for the front of the manual for finding each section 2 Atable of contents at the front of the manual for finding desired titles 3 Alist of figures at the front of the manual for finding illustrations and charts by names 4 Achapter name is located at the upper corner of each page Related Manuals B MNIO2L Series LSI User s Manual Describes the MN102L series specifications B MNIO2L Series Instruction Manual Describes the instruction set MN10200 Series Liner Addressing Version C Compiler User Manual Usage Guide Describes the installation commands and options for the C complier B MN10200 Ser
166. W RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 15 0 Pointer Data Byte Swap During read operations the upper 8 bits Data are remain and the lower 8 bits of PBSWPH are read out in the lower 8 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP 23 22 21 20 19 18 17 16 RW RW RW RW RW RW RW RW 01010101 0 PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP 7 6 5 4 3 2 1 0 7 0 Pointer Data Byte Swap During read operations the lower 8 bits of Data PBSWPL are read out in the upper 8 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24 15 0 Long word Data Byte Swap During rea
167. able Hi Z Hi Z Hi Z Hi Z except P04 Hi Z except P04 89 P05 D05 AD05 CMOS No Programmable Hi Z Hi Z Hi Z 2 except except 90 P06 D06 AD06 TIL CMOS No Programmable Hi Z Hi Z Hi Z Hi Z except P06 2 except P06 91 P07 D07 AD07 CMOS No Programmable Hi Z Hi Z Hi Z Hi Z except P07 Hi Z except P07 92 vss 93 P10 D08 AD08 CMOS No Hi Z Hi Z Hi Z 2 except P10 Hi Z except P10 94 11 009 009 TIL CMOS No Programmable Hi Z Hi Z Hi Z Hi Z except P11 Hi Z except P1 1 95 P12 D10 AD10 CMOS No Programmable Hi Z Hi Z Hi Z Hi Z except 12 Hi Z except P12 96 P13 D11 AD11 TIL CMOS No Programmable Hi Z Hi Z Hi Z Hi Z except P13 Hi Z except P13 97 P14 D12 AD12 CMOS No Programmable Hi Z Hi Z Hi Z Hi Z except 14 2 except 14 98 P15 D13 AD13 TIL CMOS No Programmable Hi Z Hi Z Hi Z Hi Z except P15 Hi Z except P15 99 P16 D14 AD14 CMOS No Programmable Hi Z Hi Z Hi Z Hi Z except P16 Hi Z except P16 100 P17 D15 AD15 TIL CMOS No Programmable Hi Z Hi Z Hi Z Hi Z except P17 Hi Z except P17 Depends on pin setting 71 Single chip mode 2 Processor mode Address Data separated mode 3 Processor mode Address Data share mode 4 High during STOP mode 5 High during STOP and HALT 1 mode Data Appendix IX 249 Chapter 9 Appendix 9 3 Instruction Set MN102L SERIES INSTRUCTION SET
168. analog signal cannot be set to 8 kO or less 3 To prevent the power potential fluctuation do not change the chip output level from high level to low level or vice verse or do not switch the periph eral load circuit on off during A D conversion Equivalent Circuit Block Outputs Analog Signal Microcontroller N N A D Input Pin C AVss R lt 8 KO Or C2 2000 pF Connect to Vss in the chip model which has no AVss Chapter 6 Analog Interface Table 6 1 1 A D Converter Functions Conversion 8 bit 3 LSB ANS to ANO Resolution 8 bit 4 LSB 7 to The A D converter converts the voltage between VDD and Vss divided into 256 and this converted result is tored in AN7BUF to ANOBUF Conversion Time 4 8 us or more per channel sample time of 400 ns with a 20 2 oscillator Clock Source Internal System Clock SYSCLK divided by 1 2 4 8 Operating Mode 30 operating modes Single conversion of single channel channel to channel 7 Single conversion of multiple channels channel 0 to channel 1 channel o to channel 2 channel to channel 3 channel to channel 4 channel to channel 5 channel to channel 6 channel to channel 7 Continuous conversion of single channel channel to channel 7 Continuous conversion of multiple channels channel 0 to channel 1 channel o to channel 2 channel to channel 3 channel to channel 4 channel to channel 5 channel to channel 6 chann
169. and b 11 are available At under 5 MHz oscillation all of these are available 00 Single channel single conversion 01 Multiple channels single conversion 10 Single channel continuous conversion 11 Multiple channels continuous conversion Chapter 9 Appendix A 7 6 5 4 3 2 1 0 ANOBUF ANO ANO ANO BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 x 00FDA8 R R R R R R R R A D 0 Conversion Data Note Note Note Note Note Note 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Buller Note Undefined 8 16 bit access register 7 0 Conversion Result of Ch 0 ANO Pin ANOBUF is a read only buffer 6 5 4 3 2 1 0 AN1 BU F 1 1 AN1 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUFO x 00FDA9 Be RR ORs RB RR A D 1 Conversion Data Note Note Note Note Note Note 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Buffer Note Undefined 8 bit access register 16 bit access is possible 7 0 Conversion Result of Ch 1 AN1 Pin from even address AN1BUF is a read only buffer 7 6 5 4 3 2 1 0 AN2BUF AN2 AN2 AN2 AN2 AN2 AN2 AN2 AN2 i BUF7 6 BUF5 BUF4 BUF3 BUF2 BUF1 BUFO x 00FDAA A D 2 Conversion Data Note Note
170. binary counter may not start at the first cycle 12 Set TM2LD and TM3LD to 0 and TM2EN and TMSEN to 1 This starts the timer Counting starts at the beginning of the next cycle When the TM2BC value and the TM3BC value reache 0 timer 3 underflow interrupt request occurs as soon as TM2BR value x 3F and the value x 9C are loaded N Ve ULL rn Nn Nn n nu TMOBR h ji FN 00 Fo re F7 Fe Fa Fa W oo F7 TMO Output NE f f es mr 7 7 ni oo JE I I F o Fr lo FF 00 Cascade Signal TM3BR 00 9C D T I 11 YA TRES 00 9 01 00 00 9C M 1 2 3 4 5 6 7 8 9 40 11 12 Figure 4 2 5 Interval Timer Timing 8 bit Timer Setup Examples IV 87 Chapter 4 Timers Counters Use the MOV instruction to set the data and always use 16 bit write operations Stop TM6BC counting and initial ize clear TM6BC and RS F F In the single buffer mode both 6 and TM6CB are com pared to TM6BC The TM6CB value is set to 1 by writing x to TM6CB When T
171. bit 2 Open drain Control 0 Off 1 On for PC pin 1 0 Serial 1 Clock Source 00 5 pin Selection 01 Timer 2 underflow 16 10 Timer 2 underflow 2 11 Timer 3 underflow 16 Chapter 9 Appendix SC1CTR x 00FD90 Serial 1 Control Register 8 16 bit access register When 7 bit transfer is selected the bit order is set only to LSB first The stop bit is set only during asynchronous mode Data Appendix IX 209 Chapter 9 Appendix 7 6 5 4 3 2 1 0 SC1 SC1 SC1 SC1 SC1 SC1 SC1 SC1 TRB7 TRB6 TRB5 TRB4 TRB3 TRB2 TRB1 TRBO R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 01 ot 0 1 T 0 Serial Transmit Receive Data IX 210 Data Appendix SC1TRB x 0O0FD92 Serial 1 Transmit Receive Buffer 8 bit access register Transmission starts by writing the data into this register The transmission starts after 1 cycle or 2 cycles of the transmission clock In 7 bit transfer the MSB bit 7 is ignored Writing to SC1TRB register must be oper ated after verifying that the trans mission is not in progress The data is received by reading this register The data is read when an interrupt occurs or the SCARXA flag of the SC1STR registeris 1 In 7 bit transfer the MSB bit 7 becomes 0 7 6 5 4 3 2 1 0 SC1 SC1 1 SC1 SC1 SC1
172. cessor mode ees E E Note Set only in 4 bit unit VIII 152 Ports Chapter 8 Ports m P37 to P30 Pins Selection P3DIRn P3MDn Description Port Input Port Input Port Output mode during processor mode sea T j m P43 to P40 Pins Selection P4DIRn P4MDn Description Pen to 0 n 98 to 0 Port Port Input Do not select the port input or the port output during processor mode Do not select the port input or the port output in address data separated Port P45 to P44 Pins Selection P4DIRn PAMDn Description 5 4 5 4 Port Input Do not select the port input or the port output during processor mode AN5 4 ANS 4 Input m P46 Pin PADIR6 P4MD6 PeMD6 Port Input Port Input AN6 Input 3 9 nes 3 1 Pots 153 Chapter 8 Ports P47 Pin Port Input Port Input AN7 Input o ne m P53 to P50 Pins Selection P5DIRn P5MDn Description to 0 n 0 Port Input Port Input Do not select the port input or the port output during processor mode Port rd m P54 Pin m P55 Pin Selection PSMDS Reserved Reserved P56Pin Port Input Do not select the port input or the po
173. chmitt and pull up resistor availability TTL in the input level column means that the input is determined at TTL level CMOS in the input level column means that the input is determined at CMOS level The column with yes sign shows Schmitt while the column with no mark shows no Schmidt Pull up resistors are in the column with yes The column with programmable can be set by pull up control registers PPLU Please see Chapter 8 Ports for details Table 1 4 1 List of Pin Functions 1 9 Pin Name Input Output Shared Pin Function Description Vpp Power There are six Vpp pins Connect these six pins to a power supply of 4 5 V to 5 5 V Vss Power Ground There are four Vss pins Connect these four pins to a power supply of 0 V OSCI 5 Input Output High speed Oscillator In put 4 to 22 6 MHz High speed Oscillator Output 4 to 22 6 MHz For a self excited oscillator configuration connect crystal or ceramic oscillator across these two pins They have a built in feedback resistor between them For stability insert capacitor of 20 pF to 33 pF between the OSCI or OSCO pin and Vss pin For the exact capacitance consult the oscillator manufacturer 4 Figure 1 4 2 OSCI and OSCO Connection Example For an external oscillator configuration connect the OSCI pin to an oscillator with an amplitude of 4 to 22 6 MHz at the width between Vpp and Vss Leave the OSCO open Connecting
174. cle with penalty and without penalty when the chip accesses to devices except ROM after it accesses to ROM during the burst mode Figure 2 1 9 shows their timings and Figure 2 1 10 shows the connection ex ample The ROM burst mode is used only during the address data separated mode and the WAIT pin is ignored even though handshake mode us selected Figure 2 1 9 shows the timing of 8 bytes page during the 16 bit bus mode With Penalty LL UU LII ULU 0 SYSCLK 2 0 000 2 0 010 2 0 100 2 0 110 A2 0 000 Penarty Not ROM A23 00 End D15 00 50 CSn RE WEH WEL Without Penalty oser SYSCLK 1 2 0 000 2 0 010 2 0 100 2 0 110 2 0 000 Not 2 0 010 A23 00 015 00 When the access without penalty is selected accessing x 010000 Y cs x to x 07FFFF and 100000 to i u x SFFFFF is not allowed CSn BE J Y d 6 d WEL Figure 2 1 9 ROM Burst
175. control registers Table 4 1 2 List of Timer Control Registers Register Address R W Function TMOMD x 00FE20 RW Timer 0 Mode Register TimerO TMOBC x 00FE00 R Timer 0 Binary Counter TMOBR 10 RW Timer 0 Base Register TM1MD 21 RW Timer 1 Mode Register Timer 1 TM1BC R Timer 1 Binary Counter TM1BR x00FE11 RW Timer 1 Base Register TM2MD x 00FE22 RW Timer 2 Mode Register 2 TM2BC x 00FE02 R Timer 2 Binary Counter TM2BR x00FE12 RW Timer 2 Base Register TM3MD x00FE23 R W Timer 3 Mode Register Timer 3 TM3BC R Timer 3 Binary Counter TM3BR x00FE13 RW Timer 3 Base Register TM4MD x 00FE24 RW Timer 4 Mode Register 4 4 x 00FE04 R Timer 4 Binary Counter TM4BR x00FE14 RW Timer 4 Base Register TM5MD x 00FE25 RW Timer 5 Mode Register Timer5 TM5BC x 00FE05 R Timer 5 Binary Counter TM5BR x00FE15 RW Timer 5 Base Register TM6MD x 00FE30 RW Timer 6 Mode Register TM6BC x 00FE32 R Timer 6 Binary Counter TM6CA x00FE34 RW Timer 6 Compare Capture Register A TM6CAX x 00FE36 Timer 6 Compare Capture Register Timer 6 SetA TM6CB x 00FE38 RW Timer 6 Compare Capture Register B TM6CBX Timer 6 Compare Capture Register Set B TM7MD x00FE40 RW Timer 7 Mode Register TM7BC x 00FE42 R Timer 7 Binary Counter TM7CA x 00FE44 RW Timer 7 Compare Capture Register A TM7CAX x 00FE46 Timer 7 Compare Capture Register
176. cted Interrupt Detect Flag 1 Interrupt detected 2 Timer 6 Compare Capture 0 No interrupt detected Interrupt B Detect Flag 1 Interrupt detected 1 Timer 6 Compare Capture 0 No interrupt detected Interrupt A Detect Flag 1 Interrupt detected 0 Timer 6 Underflow 0 No interrupt detected Interrupt Detect Flag 1 Interrupt detected Chapter 9 Appendix G6ICR x O0FCAC Maskable Interrupt Control Register 6 8 16 bit access register Set 1 when ATC transfer ends Set 1 when a timer 6 underflow interrupt or compare capture in terrupt occurs Data Appendix IX 201 Chapter 9 Appendix 15 14 13 12 11 8 7 6 5 4 3 2 1 G7ICR I TM7BITM7AITM7U TM7B TM7ATM7U TM7B TM7A TM7U LV2 LV1 LVO IE IE IE IR IR ID ID ID x 00FC4E TRAV R R Maskable Interrupt o Jot Oft ot ort ort Control Register 7 8 16 bit access register 14 12 Group 7 Interrupt 000 level 0 to 110 level 6 Priority Level 10 Timer 7 Compare Capture 0 Disable 1 Enable Interrupt B Enable Flag 9 Timer 7 Compare Capture 0 Disable 1 Enable Interrupt A Enable Flag 8 Timer 7 Unde
177. d operations the lower 8 bits of Data LBSWPH are read out in the upper 8 bits and the upper 8 bits of LBSWPH are read out in the lower 8 bits Chapter 9 Appendix WBSWP x 00FFAO Word Data Byte Swap Register 8 16 bit access register PBSWPL x 00FFA2 Pointer Data Byte Swap Register Lower 8 16 bit access register PBSWPH x 00FFA4 Pointer Data Byte Swap Register Upper 8 16 bit access register LBSWPL x OOFFA6 Long word Data Byte Swap Register Lower 8 16 bit access register Data Appendix IX 227 Chapter 9 Appendix 15 14 13 12 11 10 9 8 z 6 5 4 3 2 1 0 LBSWPH E LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP 81 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 x 00FFA8 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Long word Data Byte LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP LBSWP Swap Register Upper 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 8 16 bit access register 15 0 Long word Data Byte Swap During read operations the lower 8 bits of Data LBSWPL are read out in the upper 8 bits and the upper 8 bits of LBSWPL are read out in the lower 8 bits IX 228 Data Appendix Chapter 9 Appendix
178. d using the timer 0 mode register TMOMD TMOMD x 00FE20 7 6 5 4 3 2 1 0 TMO TMO TMO TMO EN LD _ 61 so 0 1 1 0 2 Set the timer 0 divisor Since timer 0 divides SYSCLK by 2 set the timer 0 base register to 1 The valid range for TMOBR is 1 to 255 TMOBR 00 10 7 6 5 4 3 2 1 0 TMO 0 0 0 TMO 0 TMO BR7 BRe BR5 BR4 BR2 BR1 BRO 0 0 0 0 0 0 0 1 3 Load the TMOBR value to TMOBC To do this set TMOLD and TMOEN to 1 and 0 resepctively TMOMD 20 7 6 5 4 3 2 1 0 i TMO TMO LD St So 0 1 1 0 4 Set both TMOLD and TMOEN of the TMOMD register to O If this setting is omitted the timer 0 binary counter may not start at the first cycle b Set TMOLD and TMOEN to 0 and 1 respectively This starts timer 0 Count ing starts at the beginning of the next cycle When the timer 0 binary counter value reaches 0 and loads the value of 1 from the timer 0 base register TMOBR a timer 0 underflow interrupt request occurs Pin Setup 6 Select the TM1IO pin to output using the port 8 I O control register P8DIR and the port 8 output mode register P8MD The set value is 2 P8DIR x 00FFE8 P8MD x O0FFF8 6 5 4 3 2 1 0 7
179. describes the example of serial interface O transmis sion reception in mode explaining start sequence transmis sion data transmission data reception stop sequence trans mission in order m Pin Setup Set P70 pin and P72 pin to serial clock input and port input respectively If P70 pin and P72 pin do not equip a pull up resistor externally set the pull up resistor by the pull up control register See Chapter 8 Ports m Serial Interface 0 Setup Initial Setup 1 Set the operating conditions to the serial 0 control register SCOCTR In IC mode select open drain 8 bit data transfer MSB as the bit order In the system with the response from slave set parity bit to 1 In the system without ACK select no parity Select timer 3 underflow 16 as the clock source SCOCTR 00 080 1 1 5 14 12 11 10 5 SCO 500 SCO SCO TEN BRE 225 PTL 1 1 0 1 3 0 6 5 4 3 2 1 0 9 8 7 5 0 SCO SCO SCO SCO SCO SCO SCO SCO SCO OD 2 LN PTYa PTY1 PTYO SB 51 SO 1 1 1 1 0 1 0 1 1 1 Start Sequence 2 Set the IPC sequence output bit of the serial 0 control register SCOCTR to 1 This makes the SBO pin output low and generates the start sequence SCOCTR 00 080 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 5 SCO SCO SCO SCO 5 0 SCO SCO SCO 5 0 SCO SCO SCO SCO SCO TEN BRE 225 PTL
180. difined some fixed value During a bus request when BREQ is L STOP mode or HALT mode this pin will be in a high impedance state but this pin does not become high impedance state when used as ports Pin Description I 17 Chapter 1 Overview Table 1 4 1 List of Pin Functions 6 9 Pin Name Input Output Shared Pin Function Description P37 P30 I O Output A15 A08 General purpose Port 3 Address output When these pins are used as general purpose input output ports direction control is in bit unit 6 Chapter 8 Ports These pins output memory address A15 A08 in memory expansion mode and processor mode and are connected to memory address pin or address decoder circuit Address output at the timing when these pins do not access to the memory is indifined it outputs some fixed value In processor mode these pins serve as A15 08 cannnot be used as general purpose in put output ports During a bus request when BREQ is L level STOP mode or HALT mode these pins will be in a high impedance state but they do not become high impedance state when used as ports P27 P20 I O Output A07 A00 General purpose Port 2 Address output When these pins are used as general purpose input output ports direction control is in bit unit Chapter 8 Ports These pins output memory address 07 00 in memory expansion mode and pr
181. ding of serial transmission reception data a SFT SFT SFT SFT SFT SFT Bit RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO Atreset Description Transmission reception buffer 8 bits Fixed length serial status register Register SFSTR Address x00FD73 Use Display of serial transmission reception status BiNo 7 6 5 14 13 1211 10 SFT SFR SFB SFT SFR SFT SFR Bit EN EN SY XA XA OE OE Access RwW RWiR R R R R Atreset Description With without reception overrun error With without transmission overrun error With without reception data With without untransmission data Transfer status flag transfer enable transfer in progress Reserved Reception disable enable Transmission disable enable Flash EEPROM Version IX 275 Chapter 9 Appendix 9 6 11 PROM Writer Onboard Serial Programming B Reprogramming flow IX 276 Flash EEPROM Version START Voo 5 0 V All 0 Program User Data Program Figure 9 6 13 Reprogramming Flow MN102L610B F61G LSI User s Manual May 2002 1st Edition 1st Printing Issued by Matsushita Electric Industrial Co Ltd Matsushita Electric Industrial Co Ltd Semiconductor Company Matsushita Electric Industrial Co Ltd Nagaokakyo Kyoto 617 8520 Japan Tel 075 951 8151 http www panasonic co jp semicon SALES OFFICES
182. dress pin or address decoder circuit Address output at the timing when these pins do not access to the memory is indifined it outputs some fixed value In processor mode these pins serve as A19 A16 cannnot be used as general purpose in put output ports During a bus request when BREQ is L STOP mode or HALT mode these pins will be in a high impedance state but they do not become high impedance state when used as ports P45 P44 I O Input Output 5 4 21 20 General purpose Port 4 A D converter input Address output When these pins are used as general purpose input output ports direction control is in bit unit These serve as input pins for A D converter a Chapter 6 Analog interface These pins output memory address A21 A20 in memory expansion mode and processor mode and are connected to memory address pin or address decoder circuit Address output at the timing when these pins do not access to the memory is indifined it outputs some fixed value In processor mode these pins serve as A21 A20 cannnot be used as general purpose in put output ports During a bus request when BREQ is L STOP mode or HALT mode these pins will be in a high impedance state but they do not become high impedance state when used as ports I 16 Pin Description Chapter 1 Overview Table 1 4 1 List of Pin Functions 5 9 Pin Name
183. dress Data Separated Mode x 00FC30 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WAIT1 WAITO MEMMD1 x 00FC32 15 14 13 12 11 10 9 8 7 6 5 4 2 1 0 BMOD WAIT1 WAITO x 00FC36 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BMOD 42 External Memory Connection Example Memory System with 8 bit Bus Width in All Areas The following is the example of connecting the 4 Mbit ROM 512 kilowords x 8 bits the 1 Mbit SRAM 128 kilowords x 8 bits and the ASIC with 8 bit bus width to the CSO area 2 wait cycles fixed the CS1 area 1 wait cycle fixed and the CS3 area handshake respectively Chapter 2 Bus Interface i 18 0 16 0 158 7 158 158 7 A23 M9 15 000 18 00 7 0 16 00 D A 1 007 000 mE TM SRAM 50 cs Me cs LY ETE ASIC ed OE WE ADSEP WAIT WAIT CS3 CS WORD OE WE RE WEH Figure 2 2 2 Memory Connection Example with 8 bit Bus Width Address Data Separated Mode MEMMDO x 00FC3
184. e 001 Timer 5 output next cycle regardless of this bit 010 TM6IOB pin clock setting if TM6BC becomes 0 011 SYSCLK 100 Two phase encoder 4x of TM6IOA pin TM6IOB pin 101 Two phase encoder 1x of TM6IOA pin TM6IOB pin 11 Reserved Data Appendix 223 Chapter 9 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6 TM6 6 6 6 6 6 6 TM6 TM6 6 6 6 6 6 BC15 BC14 BC13 BC12 11 BC10 BC8 BC7 BC6 BC5 BC4 BC2 BC1 BCO 01 01 0 1 0 1 0 1 15 0 Timer 6 Count Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6 TM6 TM6 6 6 6 6 6 6 TM6 6 6 6 6 6 6 CA15 CA14 13 12 11 CA9 CA8 CA6 CA5 CA4 CA2 CA1 CAO R W R W R W R W R W R W R W R W R W R W R W R W R W RW R W 01 01 01 01 0 1 0 1 0 1 0 1 0 1 15 0 Timer 6 Count Cycle Set the count cycle minus 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6 6 TM6 6 6 6 6 6 6 6 6 6
185. e time clear all prior interrupt requests Set G7LV 2 0 bits of the G7ICR to the interrupt level of 6 to 0 TM7BIR and TM7BIE to 0 and 1 respectively For example write x 4400 to the G7ICR register Thereafter an interrupt occurs when the timer 7 capture B oc curs W Timer 7 Setup 2 Set the operating mode to the timer 7 mode register TM7MD Verify that counting is stopped and an interrupt is disabled Select up counting or down counting Set TM7LP to 1 when TM7BC starts loop counting from the TM7CA value Set TM7LP to 0 when TM7BC counts the loop of 0 to Select two phase encoder 4x as the timer 7 clock source TM7MD 40 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TW 7 _ _ TM7 TM7 TM7 7 7 7 7 7 7 TM7 EN LD UD1 UDO TGE ONE MD1 MDO ECLR LP ASEL 52 51 SO 0 0 i 0 0 0 0 0 0 0 1 0 1 0 0 3 Set the timer 7 looping value the valid range is 1 to When writing x 1FFF to TM7CA The TM7BC counts from 0 to x 1FFF TM7CA x 00FE44 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 CA15 CA14 CA13 CA12 11 10 CA9 CA6 5 4
186. ed 0 IRQ3 Interrupt Detect Flag 0 No interrupt detected 1 Interrupt detected Chapter 9 Appendix G4ICR x 00FC48 Maskable Interrupt Control Register 4 8 16 bit access register Set 1 when the serial 1 reception ends Set 1 when the serial 1 trans mission ends Set 1 when timer 3 underflows Set 1 when an external interrupt occurs from IRQ3 pin Data Appendix IX 199 Chapter 9 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 G5 G5 G5 Note Note TM4 IRQ4 Note Note TM4 IRQ4 TM4 IRQ4 LV2 LV1 LV0 IE IE IR IR ID ID R R W RW R W RW RW RW RW R W RW R W R W R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 14 12 Group 5 Interrupt Priority Level 9 Timer 4 Underflow Interrupt Enable Flag 8 IRQ4 Interrupt Enable Flag 5 Timer 4 Underflow Interrupt Request Flag 4 IRQ4 Interrupt Request Flag 1 Timer 4 Underflow Interrupt Detect Flag 0 IRQ4 Interrupt Detect Flag IX 200 Data Appendix 0 Disable 0 Disable Note Always set 0 000 level 0 to 110 level 6 1 Enable 1 Enable 0 No interrupt requested 1 Interrupt requested 0 No interrupt requested 1 Interrupt requested 0 No interrupt detected 1 Interrupt detected 0 No interrupt detected 1 Interrupt detected G5ICR x 00FC4A Maskable Interrup
187. el to channel 7 Conversion Start Timer 1 underflow or register setting Interrupt An interrupt occurs each time the conversion sequence ends Ch stands for channel ANn pin corresponds to the channel num ber For example the ANS pin cor Selecting the A D Converter Clock Source responds to channel 3 A D converter clock source is selected to SYSCLK SYSCLK 2 SYSCLK 4 or SYSCLK 8 as the conversion time is 4 8 us or more Select the A D converter clock source as follows SYSCLK frequency divisor lt 5 MHz For example select the A D converter clock source as SYSCLK 4 the conver sion speed of 4 8 us or SYSCLK 8 the conversion time of 9 6 us with a 20 MHz oscillator Select SYSCLK 2 SYSCLK 4 or SYSCLK 8 with a 10 MHz oscillator Select SYSCLK SYSCLK 2 SYSCLK 4 SYSCLK 8 with a 5 MHz oscillator or less The conversion time is 12 cycles of the A D converter clock source as Figure 6 1 2 shows For example the conversion time is calculated as follows when SYSCLK A is selected SYSCLK cycle s x 4 divisor x 12 cycle State S H bit7 bit6 bit5 bit4 bit3 bit2 biti transfer A D Conversion Clock 1 1 f 1 1 1 Start Figure 6 1 2 A D Conversion Timing Analog Interface 1 125 Chapter 6 Analog Interface VI 126 AnalogInterface W One Channel Single Conversion The A D converter conv
188. en two phase phase encoding is selected 10 Up when pin is high encoding is slected down when TM6IOA pin is low 11 Up when pin is high down when TM6IOB pin is low Counting starts on the falling 9 Count Start External Trigger 0 Disable 1 Enable edge of TM6IOB pin Enable Clear TM6EN when 6 matches TM6CA 8 Counter Operating Mode 0 Repeat 1 One shot counting During repeat counting hold the Select TM6EN flag state During one 76 6 TM6CB Operating 00 Compare register single buffer shot counting set the TM6EN Mode Selection 01 Compare register double buffer flag to 0 when TM6BC TM6CA 10 Capture A when TM6IOA pin is high Capture B when TM6IOA pin is low 11 Capture A when TM6IOA pin is high Capture B when TM6IOB pin is high 5 TM6BC Clear When TM6IC 0 Don t clear 1 Clear Clear TM6BC synchronizing is 1 externally 4 TM6BC Clear TM6CA Reload When 6 6 while up counting 0 Don t clear TM6BC 1 Clear TM6BC Clear TM6BC when PWM is When TM6BC 0 while down counting output 0 Don t reload TM6CA 1 Reload TM6CA when TM6LP is 1 and up counting is selected TM6BC is 3 TM6IOA Pin Output 0 RS F F output one phase PWM cleared to 0 on the next cycle if 1 T F F output two phase PWM TM6BG counts until T MBPS matches TM6CA or x FFFF When down counting is selected 2 0 Clock Source Selection 000 Timer 4 output is set to TM6CA on th
189. ends Set AN1CH 2 0 bits to the channel number to be converted Set ANTM1 flag and the ANEN flag to 0 and 1 respectively when the conversion starts using the ANEN flag Setting the ANEN flag to 0 ends the conversion forcibly Interrupt Chn Chn Chn State Conversion Conversion Conversion ANEN Figure 6 1 5 One Channel Continuous Conversion Timing m Multiple Channels Continuous Conversion The A D converter converts A D input signals of continuous channels from chan nel 0 continuously An interrupt occurs each time the continuous conversion ends Set AN1CH 2 0 bits to channel 0 and the ANNCH flag to the last channel to be converted The conversion starts from channel 0 Set the ANTM1 flag and the ANEN flag to 0 and 1 respectively when the conversion starts using the ANEN flag The ANEN flag becomes 1 during the conversion and 0 when the conversion sequence ends Setting the ANEN flag to 0 ends the conversion forcibly The AN1CH 2 0 bits are set to the channel number during the conversion and chan nel 0 after the conversion sequence ends Interrupts State cho Ch Cho Chi Che Cho Conversion Conversion Conversion Conversion Conversion Conversion Conversion ANEN Figure 6 1 6 Multiple Channels Continuous Conversion Timing Chapter 6 Analog Interface Analog Interface VI 127 Chapter 6 Analog Interface A
190. er 8 16 bit access register P9DIR x 00FFE9 Port 9 Input Output Control Register 8 bit access register 16 bit access is possible from even address PADIR x 00FFEA Port A Input Output Control Register 8 16 bit access register Data Appendix IX 239 Chapter 9 Appendix PO MDO R R R RI RI R RW 0 0 0 Port 0 Output 7 6 51 4 8 2 1 0 P1 MDO R R R R W 1 1 0 Port 1 Output 7 6 5 4 3 2 1 0 2 2 MD4 MDO R R RN R R W eo 0 1 4 Port 2 Output 0 Port 2 Output IX 240 Data Appendix 0 P07 to P00 Output 1 D7 to DO AD7 to ADO I O 0 P17 to P10 Output 1 D15 to D8 AD15 to AD8 I O 0 P27 to P24 Output 1 A07 to A04 Output 0 P23 to P20 Output 1 A03 to A00 Output POMD x OOFFFO Port 0 Output Mode Register 8 16 bit access register POMD is valid and used as a port when WORD pin H and MEMMDn 8 1 to 3 H P1MD x 00FFF1 Port 1 Output Mode Register 8 bit access register 16 bit access is possible from even address P1MD is invalid during processor mode P2MD x 00FFF2 Port 2 Output Mode Register 8 16 bit access register P2MD is in
191. er length is 8 bit 0 2 mode off 1 PC mode on 8 mode Selection 0 7 bit 1 8 bit 7 Character Length 000 None 6 4 Parity Bit Selection 100 0 output low 101 1 output high 110 Even 1s are even 111 Odd 1s are odd Others Reserved 0 1 bit 1 2 bit 3 Stop Bit Selection 0 Off 1 On 2 Open drain Control for PC pin 00 1 0 Serial 0 Clock Source 01 Timer 2 underflow 16 Selection 10 Timer 2 underflow 2 11 Timer 3 underflow 16 IX 206 DataAppendix SCOCTR x 00FD80 Serial 0 Control Register 8 16 bit access register When 7 bit transfer is selected the bit order is set only to LSB first The stop bit is set only during asynchronous mode 5 0 7 5 0 TRB6 5 0 TRB5 SCO TRB4 SCO TRB3 SCO TRB2 SCO TRB1 SC0 TRB0 R W R W R W R W R W R W R W R W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 Serial Transmit Receive Data Chapter 9 Appendix SCOTRB 00 082 Serial 0 Transmit Receive Buffer 8 bit access register Transmission starts by writing the data into this register The transmission starts after 1 cycle or 2 cycles of the transmission clock In 7 bit transfer the MSB bit 7 is ignored Writing to SCOTRB register must be oper ated after verifying that the trans mission is not in progress The data is received by reading this register The
192. error occurs when the next data is received com pletely before the CPU reads the received data SCOTRB Over run error data is updated when ever the last data bit seventh or eighth bit is received 15 14 13 12 11 110 9 8 7 5 4 1 SC1 501 SC1 SC1 SC1 SC1 501 501 SC1 501 501 SC1 SC1 SC1 SC1 TEN REN BRE I2CS PTL OD I2CM LN PTY2 PTY1 PTYO SB POD 51 So R W RW RW RAW RW R RAW RA RW RAW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 on on 15 Transmit Enable 0 Disable 1 Enable 14 Receive Enable 0 Disable 1 Enable 13 Break Transmission 0 Don t break 1 Break Set SBO to 0 12 PC Start or Stop Sequence 0 Stop sequence output when changing this bit from 1 to O 1 Start sequence output when changing this bit from O to 1 11 Protocol Selection 0 Asynchronous mode 1 Clock synchronous mode mode 9 Bit Order Selection 0 LSB first 1 MSB first select only when the character length is 8 bit 8 PC mode Selection 0 2 mode off 1 PC mode on 7 Character Length 0 7 bit 1 8 bit 6 4 Parity Bit Selection 000 None 100 0 output low 101 1 output high 110 Even 1s are even 111 Odd 1s are odd Others Reserved 3 Stop Bit Selection 0 1 bit 1 2
193. ersion Conversion starts on the falling edge of the A D conversion clock source after ANEN is set to 1 The conversion time is 12 cycles of the A D conversion clock source 4 8 us 4 8 us to 5 2 us after ANEN is set 4 Wait for the conversion to end Set the ANEN flag to 1 during the conver sion and 0 after the conversion ends The program waits until the ANEN flag is cleared to 0 b Read the A D 2 conversion data buffer AN2BUF The converter divides 0 V to 5 V into 256 and the conversion result is the value from 0 to 255 AN2BUF x 00FDAA AN2 AN2 AN2 AN2 AN2 AN2 AN2 2 BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUFO Chapter 6 Analog Interface Setthe ANEN flag to 1 when start ing the conversion by software The CPU can read the conversion result by generating an interrupt In this case the CPU does not need to wait until the ANEN flag is set because an interrupt occurs after the conversion result is stored in AN2BUF Analog Interface Setup Examples VI 131 Chapter 6 Analog Interface 6 2 2 Multiple Channels A D Conversion Using AN2 to ANO pins The AN2 AN1 and ANO pins input the analog voltage of 0 V to 5 V and obtains the A D conversion results The converter performs periodically using timer 1 Volume 1 10 5 0 Volume 2 10 r Volume 3 7 Thi
194. erts one A D input signal of 1 channel once An interrupt occurs as soon as the conversion ends Set the channel to be converted to AN1CH 2 0 bits Set the flag and the ANEN flag to 0 and 1 respectively when the conversion starts using the ANEN flag The ANEN flag becomes 1 during the conversion and 0 when the conversion ends Interrupt Chn State Conversion ANEN Figure 6 1 3 One Channel Single Conversion Timing m Multiple Channels Single Conversion The A D converter converts A D input signals of continuous channels from chan nel 0 once An interrupt occurs as soon as the conversion for all channels ends Set AN1CH 2 0 bits to channel 0 and the ANNCH flag to the last channel to be converted Set the ANTM1 flag and the ANEN flag to 0 and 1 respectively when the conversion starts using the ANEN flag The ANEN flag becomes 1 during the conversion and 0 when the conversion sequence ends In addition the AN1CH 2 0 bits are set to the channel number during the conversion and channel 0 after the conversion sequence ends Interrupt Cho Ch2 Ch3 Ch4 Ch5 State Conversion Conversion Conversion Conversion Conversion Conversion ANEN Figure 6 1 4 Multiple Channels Single Conversion Timing W One Channel Continuous Conversion The A D converter converts one A D input signal continuously An interrupt oc curs each time the conversion
195. es TM6CBX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6 6 TM6 TM6 TM6 TM6 TM6 TM6 TMe TM6 TM6 TM6 TM6 TM6 TM6 TM6 12 CBX11 CBX10 CBX8 CBX7 CBX6 CBX5 2 CBX1 CBXO The setup steps after step 6 are the same as steps 5 and 6 in 4 3 1 Event Counter Using 16 bit Timer Chapter 4 Timers Counters The TM6CB value is setto 1 by writing x FFFF to TM6CB When TM6CB is not compared to TM6BC the TM6CB value is set to 1 TM6CAX and TM6CBX are valid only when the timer 6 compare capture register is set to double buffer mode 16 bit Timer Setup Examples IV 91 Chapter 4 Timers Counters TM6EN 0 0 0 011121314101112 3 4 0 1 2 3 0 TM6CA 0004 TM6CB 0001 B ER Figure 4 3 2 PWM Timing When timer n changes the duty of PWM output waveforms dynamically the PWM output waveforms and interrupts may corrupt at the timing of changing the TMnCB value in the single buffer mode In the double buffer mode the corrupt of PWM output waveforms and interrupts does not occur at any timing of changing the TMnCB value This corrupt does not occur even
196. ess and branches to that address During interrupt service routine the IM and IE of PSW become the interrupt level and 0 respectively The multiple interrupts are not al lowed It means that other inter rupts except the non maskable in terrupt are not accepted during in terrupt service routine unless the PSW is set Interrupt Setup Examples 61 Chapter 3 Interrupts When the watchdog timer counts 65536 cycles of SYSCLK 6 5536 ms with a 20 MHz oscillator a watchdog interrupt occurs Normally clear the watchdog timer before an interrupt occurs Normally the program generates the interrupt start address and branches to that address The IM of PSW becomes the high est level during interrupt handling and other interrupts are not ac cepted III 62 Interrupt Setup Examples 3 3 2 Watchdog Timer Interrupt An interrupt occurs by using the watchdog timer When the watchdog fanction is used operation is started by setting the WDRST flag of the CPU mode control register CPUM to enable 0 after reset The watchdog timer needs to be cleared during the main program because a non maskable interrupt occurs when the watchdog counter overflows E Interrupt Enable Setup 1 Enable interrupts by setting the interrupt enable flag IE of the processor status Word PSW to 1 and the interrupt mask level IMn to 7 bit string 111 2 Clear the WDRST flag of the CPUM register This starts the watchdog timer
197. eved 15 6 Reserved mFlash serial programming enable register Register FBEWER Address x 00FF78 Use Enabling of internal flash EPROM programming 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O BEWE BEW PENIS PE En Bit Access RC S R W RIW At reset fee ER ER EA ERE FER o osos on on on o5 on Description Serial programming is enable when 01001011 is set Serial programming is disable with other than this setup Unpopulated IX 266 Flash EEPROM Version Chapter 9 Appendix iFlash address register Register FAREG Address x 00FF74 Use Addressing register for internal flash EEPROM serial programming It addresses erase block Bit No 15114113112111101 91817 16151413121 110 FAR FAR FAR FAR FAR FAR FAR FAR FAR FAR Bit EG15 EG14 EG13 EG15 EG11 EG10 EG9 EG8 EG7 EG6 EG5 EG4 EG3 EG2 RIN Raw a reset o o o o o o o o o o o o os os ws on o or or os on on on on Unppuated Register FAREGEX Address x 00FF76 Use Addressing register for internal flash EEPROM serial programming 15114118 12 11 9 8 71 615 41312 1 0 Bit No s popa Access R R R R R R R Rw RAR Rw RAV RW Atreet
198. flow flag carry flag negative flag zero flag 16 bit data CPU internal temporary register Substitution reflects calculation results Flag Code Size e Changes Unit bytes No change 0 Always 0 1 Always 1 Undefined Machine Code indicates a delimiter between bytes lt lt 2 indicates a 2 bit shift Dn Dm Di An Am Register numbers 00 00 00 01 01 1 01 02 10 2 10 03 11 11 16 bit or 24 bit access instruction must not access odd memory addresses 8 bit displacements d8 and 16 bit displacements 416 are all sign extended Instruction Set IX 255 Chapter 9 Appendix 9 4 Instruction Map MN102L SERIES INSTRUCTION MAP EXTXU Dn EXTXB Dn EXTXBU Dn MOVB Dn abs16 MOV abs16 Dn MOVBU abs16 Dn ADD imm8 Dn CMP imm8 Dn MOV imm16 An BHI BCC First byte Upper Lower 1 2 3 4 0 MOV 1 MOVB Dm An 2 MOV An Dm 3 MOVBU An Dm 4 MOV Dm d8 An 5 MOV Am d8 An 6 MOV d8 An Dm 7 MOV d8 An Am 8 MOV Dn Dm when src dest MOV imm8 Dn 9 ADD Dn Dm A SUB Dn Dm B EXTX Dn C MOV Dn abs16 D ADD imm8 An BLT BGT BGE BCS E label label label label label label BLS label BNE BRA label label CMP imm16 An Extended code 5 bytes F Extended code 2 by 2 byte instructions Byte 1 FO Second byte Upper Lower 1 2 3 4 Extended code 3
199. g Voltage Level Cycle Time V 0 9 Vppx 0 9 t Si DA 0 Voox 0 1 0 1 0 1 x 0 1 Pulse Width High 1 Pulse Width Low gt a gt lt lt niu kalime Rise Time Cycle Time V 0 9 Voo x 0 9 7 Output Signal im etna Naenda ppx 0 9 0 1 1 1 Pulse Width Low gt aqa Fall Time Rise Time Vpp x 0 5 Output Signal Delay Time Vpp x 0 5 Both setup time and hold time Vpp x 0 5 IX 180 Electrical Characteristics Chapter 9 Appendix lt tEXCH gt a gt gt gt tEXCR I m gt SYSCLK tor gt i 4 tor M 14 tor Fig 9 1 1 System Clock Timing RST Z RSTW Fig 9 1 2 Reset Timing Electrical Characteristics IX 181 Chapter 9 Appendix pa SYSCLK m r tcH 23 00 01 lt tAD1 pi tAH1 taH2 CS3 0 lt gt CSDR1 tcspF1 tes d tcsH2 lt reaq gt 01500 bad tRDS RE EN tREDF1 Ta lt i RE RE short mode write 015 00 Dat lt ipH 1001 lt iDH2 WEL WEH Normal gt WEL WEH WE short mode a twEPW2 Fig 9 1 3 Data Transfer Signal Timing
200. guage embedded applications without expand ing the program size The PanaXSeries development tools support the MN102 series devices 9 Outstanding Power Savings The MN102L series contains separate buses which distribute and reduce load capacitance This greatly reduces overall power consumption compared to our conventional models The MN102L series also supports three modes of SLOW HALT and STOP for power savings 1 1 3 Overview This section describes the basic configuration and function of this series B Address Space The memory contains up to 16 MB linear address space The instruction space and data space are not separated so that internal RAM and special function registers for internal peripheral functions are allocated into the first 64 KB in memory as the basic configuration Table 1 1 1 shows three memory modes that supports each model and size of user program x 000000 External memory x 008000 Internal RAM Max 31 KB I O control register 1KB x 010000 External memory Program start address x 080000 16 x 080000 gt Interrupt handler gt start address 080008 Internal ROM 496 KB External memory xFFFFFF Y Figure 1 1 1 Address Space Table 1 1 1 Memory Modes Address bit width Internal ROM capacity Single chip mode 16 KB or more Memory expansion mode Up to 24 bits Chapter I Overview This is a general examp
201. h SUB imm24 An 24 gt F4 6C An imm24 l imm24 m imm24 h SUBC Dn Dm Dm Dn CF2Dm N IN 65 2 90 lt lt 2 MUL Dn Dm Dm Dm gt gt 16 0101010 0000 0101010 0101010 01010 ol 00 0 0 0 N N O IN N sN F3 40 Dn lt lt 2 Dm 712 MULU Dn Dm Dm Dn gt Dm Dm Dn gt gt 163MDR F3 50 Dn lt lt 2 Dm 713 Notes DIVU Dn Dm MDR lt lt 16 Dm Dn gt Dm MDR 6 32 bit sign extended word data 7 24 bit sign extended word data 8 24 bit zero extended word data 9 24 bit sign extended byte data F3 60 Dn lt lt 2 Dm 10 24 bit zero extended byte data 11 Addition without changing flag 12 16x16 32 signed 13 16x16 32 unsigned 14 32 16 16 16 unsigned IX 251 Instruction Set Chapter 9 Appendix Instruction Mnemonic Operation Machine Code Dn Dm Dm Dn CMP Dm An An Dm An Dm Dm An CMP An Am Am An CMP imm8 Dn Dn imm8 CMP imm16 Dn Dn imm16 CMP imm24 Dn Dn imm24 CMP imm16 An An imm16 CMP imm24 An An imm24 AND Dn Dm Dm amp x FF0000 Dn 2Dm AND imm8 Dn Dn amp x FF0000 imm8 Dn AND imm16 Dn Dn amp x FF0000
202. hese pins provide a control signal for the P63 NEN General porpose porte memory read write _When connecting SRAM Output WEH Upper Byte Write and ROM connect RE to OE in memory RE Enable Output outputs low level during read and read out the P61 I O T General porpose porte data of memory m Output RE Read Enable Output When connecting SRAM connect WEL and WEH to WE in memory WEL and WEH output low level during write and write the data to memory WEH controls write to 015 008 WEL controls write to 007 000 WEL is invalid when 8 bit bus width is selected in memory expansion mode so that it can be used as a general purpose port In processor mode these pins serve as WEL WEH and RE cannnot be used as general pur pose ports During a bus request when BREQ is L STOP mode or HALT mode these pins will be in a high impedance state but they do not become high impedance state when used as ports t Chapter 2 2 2 2 2 4 Example of External Memory Connection Pin Description I 15 Chapter 1 Overview Table 1 4 1 List of Pin Functions 4 9 Pin Name Input Output Shared Pin Function Description P43 P40 I O Output A19 A16 General purpose Port 4 Address output These pins can be used as general purpose in put output ports Chapter 8 Ports These pins output memory address A19 A16 in memory expansion mode and processor mode and are connected to memory ad
203. his series can transfer the data of serial interface 0 and internal RAM speedily without using the CPU Table 7 1 1 ATC Functions Start A serial 0 transmission end interrupt or serial 0 reception end interrupt RAM Serial 0 Transmit Receive Buffer SCOTRB Transfer Direction RAM The address for Internal RAM is x008000 to x0083FF 1 One word Transfer Bye 600 ns byte with a 20 MHz Oscillator Transfer Mode The following is four serial interface 0 modes that the ATC can operate 1 Synchronous Transmission Internal Clock Master when this LSI series generates the synchronous clock Synchronous Reception External Clock Master when this LSI series receives the synchronous clock externally 3 Asynchronous Transmission 4 Asynchronous Reception Setting bi direction of transmission and reception does not allow Chapter 7 ATC a 5 Serial Interrupt Serial Interrupt a Transfer End Interrupt a 2 Main Program E gt Z Transfer e A 8 E Interrupt Service Routine Internal RAM s SCOTRB 2 gt ATC Transfer End Interrupt Service Routine A Serial Interrupt Serial Interrupt End
204. ic Specifications I 9 Chapter 1 Overview 1 3 Block Diagram Figure 1 3 1 shows the block diagram including the CPU core and Table 1 3 1 describes the block functions Address Registers Data Registers A D Clock Clock Source A1 D1 T2 Generator A2 D2 Multiplication Division Register A3 D3 MDR Instruction Execution A Controller B Instruction Decoder Program Counter Increment Nf Instruction Interrupt Queue Controller Y 1 Program Address Operand Address Interrupt Bus Y Y Bus Controller ROM Bus RAM Bus Peripheral Extension Bus kara Y Y External Interface Internal ROM Internal RAM 1 Internal Peripheral Function External Expansion gt Bus Y BREQ BRACK Figure 1 3 1 Block Diagram I 10 Block Diagram Chapter 1 Overview Table 1 3 1 Block Functions Block Functions Clock Generator The clock generator contains the clock oscillation circuit connected to an external crystal and supplies the clock to all CPU blocks It has a built in 4x speed circuit Program Counter The program counter generates addresses for instruction queues Normally it gets increments based on the sequencer indication but for branch instructions and interrupt
205. ided by 16 Figure 5 2 1 Aynchronous Transmission Configuration The transmission starts when the data is written to the SCOTRB register The transmission starts synchronizing with timer 2 underflow An interrupt occurs after the transmission is completed and the new data is written to the SCOTRB register during the interrupt service routine The SCOTBSY flag of the SCOSTR register polls if an interrupt does not occur The serial interface generates the serial transfer baud rate with timer 2 or timer 3 divided by 16 With a 20 MHz oscillator SYSCLK is 10 MHz and 9600 bps 10 MHz 16 9600 65 10 Therefore set the timer 2 or timer 3 underflow to 65 m Pin Setup Set P72 pin to data output of serial interface 0 See Chapter 8 Ports m Timer 2 Setup 1 Verify that counting is stopped with the timer 2 mode register TM2MD TM2MD x 00FE22 7 6 5 4 3 2 1 0 TM2 TM2 TM2 TM2 LD _ 51 0 0 1 1 2 Set the timer 2 divisor Since the timer 2 divisor is SYSCLK 65 set the timer 2 base register 2 to 64 The valid range is 1 to 255 TM2BR 00 12 7 6 5 4 3 2 1 0 TM2 BR7 2 2 2 2 2 2 2 BR6 BR5 BR4 BR2 BR1 BRO 3 4 S Load the TM2BR value to TM2BC To do this set TM2LD and TM2EN to 1 and 0 respectively At the same time select the clock
206. ies Liner Addressing Version C Compiler User Manual Language Description Describes the syntax for the C complier MN10200 Series Liner Addressing Version C Compiler User Manual Library Reference Describes the standard libraries for the C complier MNIO2L Series Cross Assembler User Manual Language Description Describes the assembler syntax and notation B MN10200 Series Liner Addressing Version C Source Code Debugger User Manual Describes the use of the C source code debugger B MNIO2L Series PanaXSeries Installation Manual Describes the installation of the C complier cross assembler and C source code debugger and the procedures for using the in circuit emulator About This Manual 2 Chapter 0 Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Contents List of Figures and Tables Overview Bus Interface Interrupts Timers Counters Serial Interface Analog Interface ATC Ports Appendices d EIS DS I Chapter 0 Contents List of Figures and Tables ii Contents Contents Chapter 1 1 1 1 2 1 3 1 4 Chapter 2 2 1 2 2 Chapter 3 3 1 3 2 3 3 Overview ERR 1 2 1 1 1 IntroduGctiOfi s s terree 1 2 1 1 2 Features nues Nash ORE ep UE 1 2 1 1 3 OVerVIeW p EH I 5 Specifications
207. imm24 m imm24 h MOVX d8 An Dm mem24 An d8 gt Dm 3 3 F5 70 An lt lt 2 Dm d8 MOVX d16 An Dm mem24 An d16 gt Dm 4 3 F7 70 An lt lt 2 Dm d16 l d16 h MOVX d24 An Dm mem24 An d24 gt Dm 5 4 F4 B0 An lt lt 2 Dm d24 1 d24 m d24 h MOVX Dm d8 An Dm mem24 An d8 3 3 F5 50 An lt lt 2 Dm d8 MOVX Dm d16 An Dm mem24 An d16 4 3 F7 60 An lt lt 2 Dm d16 l d16 h MOVX Dm d24 An Dm mem24 An d24 5 4 F4 30 An lt lt 2 Dm d24 l d24 m d24 h MOVB MOVB An Dm mem8 An gt Dm S 2 2 30 An lt lt 2 Dm B8 Dm 4 MOVB d8 An Dm mem8 An d8 5 Dm S 3 2 F5 20 An lt lt 2 Dm d8 MOVB d16 An Dm mem8 An d16 5Dm s 4 2 F7 D0 An lt lt 2 Dm d16 l d16 h MOVB d24 An Dm mem8 An d24 gt Dm s 5 3 F4 A0 An lt lt 2 Dm d24 1 d24 m d24 h MOVB Di An Dm mem8 An Di gt Dm S 2 2 F0 40 Di lt lt 4 An lt lt 2 Dm MOVB abs16 Dn mem 8 abs16 Dn S 4 2 CC Dn abs16 l abs16 h B8 Dn 75 MOVB abs24 Dn mem8 abs24 gt Dn S 5 3 F4 C4 Dn abs24 l abs24 m abs24 h MOVB Dm Dm mem8 An 1 1 10 Dm lt lt 2 An MOVB Dm d8 An Dm gt mem8 An d8 3 2 F5 10 An lt lt 2 Dm d8 MOVB Dm d16 An Dm mem8 An d16 4 2 F7 90 An lt lt 2 Dm d16 l d16 h MOVB d24 An 8 924 5 3 24 20 lt lt 2 0 424 424 24 MOVB Dm mems8 An Di 2 2 F0 C0 Di lt lt 4 An lt lt 2 Dm Notes 1 Itis not possible to specify that 2 This instruction is supported by the assembler For MOV d8
208. in input 0010 External interrupt 2 0011 External interrupt 3 0100 Timer 2 underflow interrupt 0101 Timer 6 underflow interrupt 0110 Timer 8 capture B interrupt 0111 Timer 10 underflow interrupt 1000 Timer 11 capture A interrupt 1001 Timer 12 capture B interrupt 1010 Serial 2 transmission end interrupt 1011 Serial 2 reception end interrupt 1100 Serial 3 transmission end interrupt 1101 Serial 3 reception end interrupt 1110 A D conversion end interrupt 1111 Key interrupt Chapter 9 AT3CTR Register Address x 00FD30 ATC 3 Control Register Register Access 16 bit access register Sets the ATC3 operating control conditions Selecting the two bytes words transfer mode is valid only in byte access The LSB of the Supplemental address in the first word forcibly becomes 0 and the LSB of the address in the second word forcibly becomes 1 Selecting word as the unit is not allowed when 8 bit bus width is allowed in the external memory space Selecting 8 bit desitination bus width or 8 bit source bus width is allowed only when 8 bit bus width is selected in the external memory space When destination pointer incre ment or source pointer incre ment is selected the pointer in crements by 1 in byte access and by 2 in word access The AT3IQO 3 bits are cleared interrupt MN102H55D 55G F55G 9 69 Data Appendix Explanation Chapter 9 Appendix
209. ins are used as general purpose input output ports direction control is in Input TRQ4 0 External Interrupt bit unit Chapter 8 Ports Pin Description I 21 Chapter 1 Overview OSCI OSCO 4 MHz to 20 MHz 20pF 20 to33pF to33pF 7777 777 Note Capacity varies depending on the crystal osc illator OSCO Figure 1 4 2 OSCI and OSCO Connection Example x xo 32 kHz 200 kHz dd 100 pF 200 pF __ 100 pF 200 pF T 77 OSCI 4 MHz to 20 MHz Oscillation Circuit XI 32 kHz to 200 kHz Figure 1 4 3 XI XO Connection Example 7 2 10 ka to 50 ka RST zr gt 10 uF to 100uF SW 77 77 Figure 1 4 4 Reset Connection Example H z m RESET Delay circuit Do Oscillating Circuit 7777 Figure 1 4 5 WAIT Signal Control Circuit Example I 22 Pin Description Chapter I Overview 1 5 Package Dimension Package Code LQFP100 P 1414 unit mm 16 00 20 20 14 00 0 10 1 76 14 00 5070 16 00 2020 100 1 00 9 207008 SEATING PLANE 4040 0 59 Body Material Epoxy Resin Lead Material Cu Alloy Lead Finish Method Pd Plating Figure 1 5 1 100 LQFP 14 mm square The package dimension is subject to change Before using this prod
210. ion When P6MD6 is High 0 A22 output 3 Port 6 Output 0 P63 output 2 Port 6 Output 0 P62 output 1 Port 6 Output 0 P61 output IX 242 Data Appendix BRACK output BREQ Input CS3 output S2 output 1 output CS0 output P6MD x 00FFF6 Port 6 Output Mode Register 8 16 bit access register 1 WDOUT output 1 STOP output Bits 3 1 of P6MD are invalid dur ing processor mode 1 WEH output 1 WEL output 1 RE output 7 6 5 4 3 2 1 0 P7MD P7 P7 P7 P7 MD5 MD3 MD2 MD0 x 00FFF7 R R R RW R W R Port 7 Output Mode Reaister on 9 8 bit access register 16 bit access is possible 5 Port 7 Output 0 P75 output 1 SBO1 output from even address 3 Port 7 Output 0 P73 output 1 SBT1 output 2 Port 7 Output 0 P72 output 1 5800 output 0 Port 7 Output 0 P70 output 1 SBTO output Chapter 9 Appendix 7 6 5 4 3 2 1 0 P8MD ps Pa PB PB i x 00FFF8 RAW RAW RW RAW RW Rw RW Port 8 Output Mode on on Register 8 16 bit access register 7 Port 8 Output 0 P87 output 1 TM6IOB output 6 Port 8 Output 0 P86 outpu
211. ion is down when TM71OA is 0 Select SYSCLK as the timer 7 clock source 3 Set the timer 7 looping value the valid range is 1 to x FFFF When writing X1FFF to TM7CA The TM7BC counts from 0 to x 1FFF The up or down counter reaches the TM7CA value a compare capture A interrupt occurs at the beginning of the next cycle TM7MD 40 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM7 7 TM7 7 7 TM7 7 7 7 7 7 7 7 7 EN LD i I UD1 UDO TGE ONE MDO ECLR LP 52 1 S0 4 Set the value for a timer 7 interrupt when the interrupt occurs at the TM7CB value The valid range is 0 to TM7CA When the up or down counter reaches this value a compare capture B interrupt occurs at the beginning of the next cycle Set the value for timer 7 interrupt when the TM7BC counts from to X FFFF The valid range is 0 to x FFFF TM7CA x 00FE44 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 TM7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 CA15 CA14 CA13 CA12 11 10 CA9 CA8 CA6 5 4 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 b Set TM7NLD and TM7EN to 1 and 0 respectively This enables TM7BC and RS F F Do not cha
212. l Interface 0 Setup 1 Set the operating control conditions to the serial 0 control register SCOCTR Set synchronous mode MSB for bit order the external clock source 8 bit data transfer and even parity SCOCTR 00 080 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 SCO 500 500 8500 _ SCO SCO 5 SCO SCO 500 SCO SCO 500 SCO BRE 225 PTL OD l2CM LN PTY2 PTY1 PTYO SB POD 51 SO 1 1 0 0 1 1 0 1 1 1 0 0 0 0 0 2 Enable interrupts At this point clear all prior interrupt requests Set the GSICR register to the interrupt level level 6 to 0 SCORIR and SCORIE to 0 and 1 respectively For example write the G3ICR register to 48000 Thereafter a serial reception end interrupt occurs when the data is trans ferred to the serial transmit receive register G3ICR x 00FC46 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 G3 G3 SCORSCOT TM2 IRQ2 SCORSCOT 2 IRQ2 SCORSSCOT TM IRQ2 LV2 LV1 LVO IE IR IR IR IR ID ID ID ID After specifying the interrupt group and vector and clearing 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 IRFn program the interrupt ser vice routine Thereafter an interrupt occurs when the serial data is received V 120 Serial Interface Setup Examples 5 2 3 Serial Transmission Reception in PC Mode Using Timer 3 This section
213. l Spaces in the above 8 bit bus width of No 10 Use D07 to D00 as general purpose ports A18 to A00 D15 to D08 P4DIR o o o P4MD 0 0 0 0 0 1 1 Use A23 to A19 as general purpose ports PODIR to P3DIR and POMD to P3MD are same as those 16bit in the above 16 bit bus width of No 10 Use A23 to A19 as general purpose ports D15 to D00 and P4MD are same as those in the above 8 bit bus width PODIR to P3DIR and POMD to P3MD are same as those No 14 Upto 1M bytes 8bit All Spaces in the above 8 bit bus width of No 10 Use D07 to D00 as general purpose ports A18 to A00 015 to D08 P4DIR P4MD Use 23 to A20 as general purpose ports PODIR to P3DIR and POMD to P3MD are same as those 16bit in the above 16 bit bus width of No 10 Use A23 to A20 as general purpose ports D15 to D00 and P4MD are same as those in the above 8 bit bus width PODIR to P3DIR and POMD to P3MD are same as those No 15 Up to 2M bytes 8bit All Spaces in the above 8 bit bus width of No 10 Use D07 to D00 as general purpose ports A19 to A00 D15 to 008 P4DIR o o o o o P4MD 0 0 0 1 11111 Use A23 to A21 as general purpose ports PODIR to P3DIR and POMD to P3MD are same as those 16bit in the above 16 bit bus width of No 10 Use A23 to A21 as general purpose ports D15 to D00 and P4MD are same as those in the above 8 bit bus width PODIR to P3DIR and POMD to P3MD are
214. l timers 8 bit Timer Timer 2 gt Clock Synchronous Divided by 2 to 256 Serial 8 bit Timer 8 bit Timer SYSCLK 0 1 gt Timer Output 10 MHz Divided by 2 to 256 Divided by 2 to 256 16 bit Timer Timer 3 Timer 4 Long term Interval Divided by 2 to 65536 Timer 8 bit Timer fxi 4 gt Timer 5 gt Clock 8 kHz Divided by 2 to 256 Figure 4 1 13 Timer Configuration Each timer n 2 to 5 cascade inputs cascade output of timer n 1 Therefore timer does not function as a 8 bit counter but it functions as a 16 bit counter SYSCLK is a signal of dividing the clock from OSCI pin by 2 10 MHz with a 20 MHz oscillator during normal mode or HALTO mode SYSCLK becomes a sig nal of dividing the clock from XI pin by 2 16 kHz with a 32 kHz oscillator during SLOW mode HALT1 mode SYSCLK stops during STOPO mode or STOP1 mode SYSCLK outputs to the external SYSCLK pin The fxi 4 means a signal of dividing the clock from XI pin by 4 18 kHz with a 32 KHz oscillator during modes except STOPO and STOP1 modes fxi 4 stops during STOPO or STOP1 mode Timers IV 73 Chapter 4 Timers Counters The TM6CAX register the TM6CBX register the TM7CAX register and the TM7CBX regis ter are dummy registers to specify the double buffer mode when the PWM is output IV 74 Timers 4 1 2 Control Registers The following table shows timer
215. le of the memory expansion mode Both the start address and the end adaress of internal RAM are changed within x 008000 to on models The start address of internal ROM is fixed at x 080000 while the end address of internal ROM is changed depending on sizes of in ternal ROM The end address in this example is 496 KB Overview I 5 Chapter 1 Overview B Internal Registers Memory and Special Function Registers m TVU 9 3 o ez a o o 2 c o Memory Special Registers Ports Overview gt o o Qo O gt m D D e D gt gt gt lt o 3 I g lt 5 2 e D o o a CPUM IAGR SCnCTR SCnTRB SCnSTR ANCTR ANBUF TMnMD TMnBC TMnBR MEMMDn EXMCTR ATCBC ATCCTR RAM PnOUT PnIN PnDIR The program counter specifies the address 24 bits of the program during the execution The address registers specify the data location on the memory A3 is assigned as the stack pointer The data registers perform all arithmetic and logic operations When the byte 8 bit data or the word 16 bit data is transferred to memory or another register the instr
216. ler Group 1 G1ICR lt 3 Maskable Interrupt Controller Group 7 G7ICR la Figure 1 1 2 Interrupt Controller Configuration The CPU checks the processor status word to determine whether an interrupt request is accepted or not When an interrupt is accepted automatic servicing by hardware starts and the program counter and PSW are pushed to the stack Next the program moves to the interrupt After specifying the interrupt vector it branches to the entry address of the interrupt service for that interrupt Interrupt preprocessing Push registers branch to entry address etc Main Program x 080008 IN Hardware processing Push PC PSW MD JMP etc s Interrupt a Max of 4 machine cycles 7 machine cycles Figure 1 1 3 Interrupt Servicing Sequence Chapter 1 Overview Reset Non maskable Interrupts Watchdog Timers Execution of Undefined Instructions External Pin NMI Maskable Interrupts 26 Vectors External Pin Interrupts Peripheral Interrupts etc Interrupt handling routine Reset interrupt vectors at the beginning Overview I 7 Chapter 1 Overview 1 2 Basic Specifications This section describes the basic specification of this series Please refer to Product Standards for details Table 1 2 1 Basic Specifications 1 2 CPU Structure Load store architecture Eight registers Fou
217. les Office Willoughby Road Bracknell Berks RG12 8FP THE UNITED KINGDOM Tel 44 1344 85 3671 44 1344 85 3853 Germany Sales Office Hans Pinsel Strasse 2 85540 Haar GERMANY Tel 49 89 46159 119 49 89 46159 195 ASIA e Singapore Sales Office Panasonic Semiconductor of South Asia PSSA 300 Beach Road 16 01 The Concourse Singapore 199555 THE REPUBLIC OF SINGAPORE Tel 65 6390 3688 Fax 65 6390 3689 e Malaysia Sales Office Panasonic Industrial Company M Sdn Bhd Head Office Tingkat 16B Menara PKNS Petaling Jaya No 17 Jalan Yong Shook Lin 46050 Petaling Jaya Selangor Darul Ehsan MALAYSIA Tel 60 3 7951 6601 Fax 60 3 7954 5968 Fax 52 3 671 1256 Matsushita Electric Industrial Co Ltd 2002 Penang Office Suite 20 07 20th Floor MWE Plaza No 8 Lebuh Farquhar 10200 Penang MALAYSIA Tel 60 4 201 5113 Fax 60 4 261 9989 Johore Sales Office Menara Pelangi Suite8 3A Level8 No 2 Jalan Kuning Taman Pelangi 80400 Johor Bahru Johor MALAYSIA Tel 60 7 331 3822 Fax 60 7 355 3996 Oe Thailand Sales Office Panasonic Industrial THAILAND Ltd PICT 252 133 Muang Thai Phatra Complex Building 31st FI Rachadaphisek Rd Huaykwang Bangkok 10320 THAILAND Tel 66 2 693 3428 Fax 66 2 693 3422 OG Philippines Sales Office PISP Panasonic Indsutrial Sales Philippines Division of Matsushita Electric Philippines Corporation 102 Laguna Boulevard Bo Don Jose Laguna Technopark Santa Rosa
218. lues and a timer 7 capture A interrupt is gen erated when capture occurs When compare is selected set the PWM cycle When this regis ter matches the timer 7 binary counter a timer 7 capture A inter rupt occurs TM7CB x 00FE48 Timer 7 Compare Capture Register B 16 bit access register When capture is selected TM7CB reads the captured values and a timer 7 capture B interrupt is gen erated when capture occurs When compare is selected set the PWM cycle When this regis ter matches the timer 7 binary counter a timer 7 capture B inter rupt occurs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP WBSWP 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 15 0 Word Data Byte Swap Data During read operations the upper 8 bits and the lower 8 bits are swapped 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP PBSWP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RW RW RW R
219. ming with 8 bit Bus Width 2 2 22 2 2 1 II 53 Handshake Access Timing with 8 bit Bus Width II 53 Access Timing during Bus Request Address Data Shared Mode II 54 Chapter 3 Interrupts Figure 3 3 1 Figure 3 3 2 Chapter 4 Figure 4 1 1 Figure 4 1 2 Figure 4 1 3 Figure 4 1 4 Figure 4 1 5 Figure 4 1 6 Figure 4 1 7 Figure 4 1 8 Figure 4 1 9 Figure 4 1 10 Figure 4 1 11 Figure 4 1 12 Figure 4 1 13 Figure 4 1 14 Figure 4 1 15 Figure 4 1 16 Figure 4 1 17 Figure 4 1 18 Figure 4 1 19 Figure 4 1 20 Figure 4 1 21 Figure 4 2 1 Figure 4 2 2 Figure 4 2 3 Figure 4 2 4 Figure 4 2 5 Figure 4 3 1 Figure 4 3 2 Figure 4 3 3 Figure 4 3 4 External Pin Interrupt Timing 61 Watchdog Timer Interrupt III 63 Timers Counters Event Counter Timing Timer 0 to Timer 5 IV 68 Timer Output Interval Timer Timing Timer 0 to Timer 5 IV 68 PWM Output Timing Timer 6 and Timer 7 asss IV 68 PWM Output Timing Data Write Timer 6 and Timer 7 IV 69 Two phase Timer Output Timing Timer 6 and Timer 7 IV 69 One shot Pulse Output Timing Timer6 and Timer 7 IV 69 One phase Capture Input Timing Timer6 and Timer 7 IV 70 Two phase Capture Inpu
220. n control register ANCTR sets the A D conversion operating conditions The A D conversion results for channel 7 to channel 0 are input to the A D conver sion data buffers ANnBUF Chapter 6 Analog Interface Analog Interface 1 129 Chapter 6 Analog Interface ANNCH 2 0 are ignored 6 2 Analog Interface Setup Examples 6 2 1 One Channel A D Conversion Using AN2 Pin This section describes the one channel A D conversion setup by software The 2 pin inputs the analog voltage 0 V to 5 V and obtains the A D conversion result This LSI Series 5 V ED HET P96 AN2 pF 0 V Figure 6 2 1 One Channel A D Conversion m Pin Setup 1 Set AN2 pin P96 of the port 9 to input P9DIR6 0 W A D Conversion Control Register Setup 2 Setthe operating conditions to the A D conversion control register ANCTR Set ANMD to 1ch single conversion and select the clock source to SYSCLK 4 10 MHz 4 with a 20 MHz oscillator Set ANEN to 0 and AN1CH 2 0 to the channel number to be converted ANCTR x 00FDA0 AN AN AN _ AN AN AN AN AN _ NCH2NNCH1INCHO 1CH2 1CH1 1CH0 EN 1 MD1 MDO 0 0 0 0 1 0 0 0 1 0 0 0 VI 130 Analog Interface Setup Examples 3 Set the ANEN flag to 1 to start the conv
221. nd alone programming Onboard programming mode which the CPU controls programming of a microcontroller on a target board The 128 KB flash EEPROM is divided into two main areas Load program area 6 KB 40x80000 to 40x817FF This area stores a load program for onboard programming mode This area is overwritten only in PROM writer mode This area is write erase protected in the hardware during onboard programming mode User program area 122 0x81800 to 0x9FFFF This area stores an user program It is overwritten in both programming modes Normal operation is guaranteed with up to ten programmings f PS Block 6 K Load Program Area Block2 10 K Block3 8K Block4 8K N Block5 16 K W Block6 15 K Block7 1 K Block8 1K NN Block 15K Block10 16 K Block11 32 K User Program Area Figure 9 6 1 Memory Map of Internal Flash EEPROM Chapter 9 Appendix 9 6 2 Reprogramming Flow Figure 9 6 2 shows the flow for reprogramming erasing and programming the flash memory Write Os to entire memory Erase routine Reverse Write user program Figure 9 6 2 Internal EEPROM Programming Flow As the figure shows the write occurs after the memory is completely erased The erase routine consists of three steps first writing all zeros to the entire memory space next erasing the memory and finally reversing 9 6 3 PROM Writer Programming Mode In PROM writer mode the CPU i
222. nge other bits of the TM7MD register 6 Set both TM7NLD and TM7EN to 1 This starts timer 7 Counting starts at the beginning of the next cycle Interrupt Processing 6 Execute interrupt processing The interrupt processing specifies the inter rupt group and vector and clears IRFn The following figure shows the count direction Timer 7 controls the count direction using TM71OA or TM7IOB The count direc tion becomes the opposite edge of the count edge shown as O in Figure 4 3 10 Figure 4 3 10 shows the external count direction control timing and the example of becoming down counting from up counting and generating an inter rupt TM7CA 1FFF Y TM7CB 1000 TM7BC 0000 1FFF 1FFE 1FFD 1FFE 1FFF 0000 0001 0002 0003 1000 1001 Y Y LN j TAS JOT gt gt E gt TM7IOA G i i i X4 i i B Interrupts 222244050192 Count Direction Down Down Up Up Up Up Up Up Up Up Figure 4 3 10 External Count Direction Control Timing Chapter 4 Timers Counters If this step is omitted TM7BC may not count during the first cycle 16 bit Timer Setup Examples IV 105 Chapter 4 Timers Counters Use the MOV instruction to set the data and always use 16 bit write operation
223. ns 00 Low level for IRQ2 Pin Interrupt 01 High level 10 Negative edge 11 Positive edge 3 2 Set Trigger Conditions 00 Low level for IRQ1 Pin Interrupt 01 High level 10 Negative edge 11 Positive edge 1 0 Set Trigger Conditions 00 Low level for IRQO Pin Interrupt 01 High level 10 Negative edge 11 Positive edge Chapter 9 Appendix EXTMD x 00FC50 External Interrupt Edge Setup Register 8 16 bit access register When this is used at STOP L level or R level should be set At STOP edge interrupt is not available Even if edge is set in terrupt occurs by level Data Appendix IX 203 Chapter 9 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WE NALE BRPG BRPG BRENBREN SHT EN 1 0 1 0 RW R R R RW R RWI RW RW R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 WEH WEL Pulse Width 0 Disbale 1 Enable Shortening 8 ALE Signal Polarity 0 Positive logic 1 Negative logic No wait cycle in handshake 0 Disbale mode is forbidden address 1 Enable data separate mode 5 4 Page Size of ROM Burst 00 4 bytes Mode 01 8 bytes 10 16 bytes 11 Reserved 1 0 ROM Burst Mode 00 Disable 01 Reserved 10 Enable without penalty 11 Enable with penalty 15 14 13 12 11 10
224. nsmitted in half duplex mode both SBT pins be come input so that they need pull up resistors The SBT pins connect a pull up resistor externally or a built in pull up resistor by the PPLU register V 113 Serial Interface Chapter 5 Serial Interface The mode is used only as the master transmission reception in the single master system cause mode do not control the protocol setting the transfer baud rate and controlling the transfer start are required to function the slave transmission reception V 114 Serial Interface m C Mode The serial interface can connect to the devices which can slave transmit and receive The SBO pin and SBT pin connect pull up resistors externally or inter nally 5 5 SBO i 25 gt 5 3 SBT This LSI Series y y Slave Slave Transmit Receive Transmit Receive Figure 5 1 5 Mode Connection The acknowledge ACK bit is substituted for a parity bit In the system requiring the fix the parity bit to 1 SCnPTY 2 0 101 when this LSI master trans mits the data In that case a parity error occurs when the ACK low level returns from the slave Therefore the parity bit of the SCnSTR register becomes 1 when the transmission is completed normally On the other hand when this LSI master receives the data fix the parity bit to 0 SCnPTY 2 0 100 if the returns from the slave and set the pa
225. o 0 Port Input Port Input Operate as a timer input pin when selecting the timer closk source to the Timer Input pin m P90 Pin Port Input EM Operate as a serial data input pin when selecting the 16 bit timer binary Serial Serial Input counter clear condition 2 Sth bit of TM6MD m P92 and P91 Pins Selection P9DIRn P9MDn Description n 2 1 n 2 1 Port Input Port Input Operate as a timer input pin when setting the timer closk source capture Timer Input trigger and encoder W P93 Pin Port Input Port Input Operate as a serial data input pin when selecting the 16 bit timer binary Timer Input counter clear condition 2 5th bit of TM6MD OFF Port Output Output reser Lu LED drive is enabled when P9MD3 is set to 1 P9OUT3 selects light ON or LED Output 156 Ports Chapter 8 Ports m P93Pin P9DIR4 Pp Pm 7 Port Input Port Input Timer Input Port Output Port Output LED drive is enabled when P9MDA is set to 1 P9OUT4 selects light ON or LED Output B P97 to P95 Pins m PA4 to PAO Pins n 7 to 4 AN3 to 0 AN3to 0 Input LN m PA5Pin Port Input Operate as the port input only during single chip mode Otherwise operate as the Selection PADIRn 4 to 0 Port Input Interrupt Input Port Output ADSEP Input ADSEP input Port Output 1 Operate as the port output only during single chip mode This ope
226. ocessor mode and are connected to memory address pin or address decoder circuit Address output at the timing when these pins do not access to the memory is indifined it outputs some fixed value In processor mode these pins are A07 A00 cannnot be used as general purpose input out put ports During a bus request when BREQ is L level STOP mode or HALT mode these pins will be in a high impedance state but they do not become high impedance state when used as ports I 18 Pin Description Chapter I Overview Table 1 4 1 List of Pin Functions 7 9 Pin Input Output Shared Pin Function Description P17 P10 General purpose Port When these pins are used as general purpose P07 P00 1 0 input output ports I O direction control is in 015 000 Data address data bit unit Chapter 8 Ports AD15 Input output In processor mode or memory expansion AD00 mode these pins provide data input or output during address data separate mode and pro vide memory address output lower 16 bit and data input or output in time sharing in address data share mode These pins serve as input pins when the external memory is not ac cessed t Chapter 2 2 2 2 2 4 Example of Exter nal Memory Connection During a bus request when BREQ is L level STOP mode or HALT mode these pins will be in a high impedance state but they do not be come high impedance state when used as ports P53 P50
227. ogram sse IX 272 Branching to the reset start routine IX 273 Branching to the interrupt start routine sese IX 273 Data Tr nstet Timing usay aan amam asus IX 274 Reprogramming 1 IX 276 Contents X Contents Chapter 1 Table 1 1 1 Table 1 2 1 Table 1 2 1 Table 1 3 1 Table 1 4 1 Table 1 4 1 Table 1 4 1 Table 1 4 1 Table 1 4 1 Table 1 4 1 Table 1 4 1 Table 1 4 1 Table 1 4 1 Chapter 2 Table 2 1 1 Table 2 1 2 Chapter 3 Table 3 1 1 Chapter 4 Table 4 1 1 Table 4 1 1 Table 4 1 2 Chapter 5 Table 5 1 1 Table 5 1 2 Table 5 1 3 Table 5 1 4 Table 5 1 5 Table 5 1 6 Table 5 1 7 Table 5 1 8 Table 5 1 9 Table 5 1 10 Overview Memory Modes n I 5 Basic Specifications 1 2 ee etr u ik Q puya suu I 8 Basic Specifications 2 2 Prevent 1 9 Basic F nctions ue eere nie eai recedet I 11 List of Pin Funactions 1 9 u e enne ener enne I 13 List of Pin Funactions 2 9 I 14 List of Pin Funactions 3 9 I 15 List of Pin Funactions 4 9 eene ener enne I 16 List of Pin Funactions 9 9 I 17 List of Pin Funactions 6 9 I 18 List of Pin Funaction
228. ons PSW The processor status word PSW stores the flags that indicate the status of the CPU interrupt controller and operation results Interrupt Controller The interrupt controller detects the interrupt requests from the peripheral func tions and requests the CPU to move to the interrupt handling Bus Controller The bus controller controls the connection between the CPU internal bus and the CPU external bus It also contains the bus arbitration function Internal Peripheral Function This series contains the peripheral functions including timers serial interface A D converter and so on Block Diagram I 11 Chapter 1 Overview 1 4 Pin Description et on co 858 BREE 085986 699 2118353838 22228 e282 eases e 88 585858885885 00506 PAO IRQO 76 50 TM2lIO P82 PA1 IRQ1 77 49 PA2 IRQ2 78 48 lt 80 PA3 IRQ3 79 47 a A23 WDOUT AN7 P47 PA4 IRQ4 80 46 gt 22 5 6 46 PA5 ADSEP t 81 45 4 gt 21 5 45 AST Bs 44 a A20 ANA P44 83 43 4 Vss P00 D00 AD00 lt 84 42 4 19 43 PO1 DO1 ADO1 t 85 41 18 42 P02 D02 ADO2 86 40 4 9A17 P41 P03 D03 AD03 4 gt 87 1 O2LF61 G L61 OB 39 w A16 P40 P04 D04 AD04 gt 88 38 m gt A15 P37 P05 D05 AD05
229. ort 5 This pin can be used as general purpose input output port 4 Chapter 8 Ports Output BSTRE Read Enable Output In memory expansion mode this port provides ALE ALE for Burst ROM RE signal for burst ROM in address data sepa address latch enable rate mode Note that this pin does not need to output be connected to burst ROM with penalty as nor mal RE pin instead can be connected to the burst ROM with penalty t Chapter 2 1 3 ROM Burst Mode Timing In address data share mode this pin outputs the timing that address output to AD15 0 is latched outside Note that ALE is positive logic at reset release and can be switched to negative logic with register setting thus negative logic cannot be used in processor mode Note that ALE could be output even in the cycle that does not access to external device During a bus request BREQ is L level STOP mode or HALT mode this pin will be in a high impedance state but it does not become high impedance state when used as ports P60 General purpose Port 6 This can be used as general purpose input output port 4 Chapter 8 Ports Input WAIT Bus Cycle Wait Input When external memory is in handshake mode this pin provides signal that extend the access cycle to the external memory When L level is input to this signal external memory access ends t Figure 1 4 5 P74 P71 I O General purpose Port 7 This can be used as general purpose input
230. ort 8 I O control register P8DIR and the port 8 output mode register P8MD P8DIR x 00FFE8 P8MD x 00FFF8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 DIR DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIRO MD7 MD6 5 MD4 MD3 MD2 MDO 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 m Timer 6 Setup 2 Set the operating mode to the timer 6 mode register TM6MD Verify that counting is stopped and an interrupt is disabled Select up counting or down counting Select SYSCLK as the timer 6 clock source Select the double buffer operating mode TM6MD 00 0 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6 TM6 TM6 6 6 TM6 6 6 6 TM6 6 EN NLD UD1 UDO TGE ONE 01 MDO ECLR LP ASEL 52 51 SO 0 0 0 0 0 0 0 1 0 1 0 0 1 1 3 Set the timer 6 divisor Since timer 6 divides SYSCLK by 5 set 4 to the timer 6 compare capture register A TM6CA The valid range for TM6CA is 1 to XFFFE TM6CA x 00FE34 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 6 TM6 6 TM6 6 6 6 6 6 CA15 CA14 CA13 CA12 11 10 CA9 CA6 5 4 1
231. ose in put output port TM6IOB Timer 6B Input output This pin serves as timer input capture input pin and ouput compare output pin P90 I O This pin can be used as general purpose in put output port Input TM6IC Timer 6 Counter Clear This pin serves as timer 6 counter clear a Chapter 4 Timer Counter P91 I O This pin can be used as general purpose in put output port 7 Timer 7A Input output This pin serves as timer input capture input pin and ouput compare output pin 92 I O This pin can be used as general purpose in put output port TM7IOB Timer 7B Input output This pin serves as timer input capture input pin and ouput compare output pin P93 I O This pin can be used as general purpose in put output port and when used as general Input TM7IC Timer 7 Counter Clear Purpose port it can be used as LED driver port This pin serves as timer 7 counter clear a Chapter 4 Timer Counter P97 P94 General purpose Port 9 When these pins used as general purpose input output ports direction control is in Input AN3 ANO A D Converter Input bit unit These are A D converter input pins t Chapter 6 Analog Interface When P94 is used as a general purpose port it can be used as LED driver port NMI Input NMI An NMI interrupt occurs on the falling edge to low level at negative logic When reading the PortA the pin value can be monitored at bit 6 4 0 General purpose Port A When these p
232. r Selecting 1 is not allowed in ad dress data separated mode dur ing processor mode P3DIR x 00FFE3 Port 3 Input Output Control Register 8 bit access register 16 bit access is possible from even address Selecting 1 is not allowed in ad dress data separated mode dur ing processor mode P4DIR x 00FFE4 Port 4 Input Output Control Register 8 16 bit access register Selecting 1 is not allowed in ad dress data separated mode dur ing processor mode Data Appendix IX 237 Chapter 9 Appendix 5 P5 5 5 P5 P5 P5 DIR6 DIRS DIR4 DIRS DIR2 DIR1 DIRO R W R W R W R W R W R W R W R W 0 1 7 0 Each Pin Input Output of Port 5 0 Input 1 Output Pe P6 DIR3 DIR2 DIR1 DIRO R R R R R W RW RW RW 0 0 0 0 0 1 0 1 0A 0 1 3 0 Each Pin Input Output of Port 0 Input 1 Output 7 6 5 4 3 2 1 0 Note Note P7 P7 P7 P7 P7 P7 0185 DIR4 DIRS 0182 DIR1 DIRO R R W RW RW RW 0 0 0 0 0 0 0 1 01 01 O 1 0 1 0 1 Note Always set 0 5 0 Each Pin Input Output of Port 0 Input 1 Output IX 238 Data Appendix P5DIR
233. r Port 3 Input Output Control Register Port 3 Output Mode Register Port 4 Output Register Port 4 Input Register Port 4 Input Output Control Register Port 4 Output Mode Register Port 5 Output Register Port 5 Input Register Port 5 Input Output Control Register Port 5 Output Mode Register Port 6 Output Register Port 6 Input Register Port 6 Input Output Control Register Port 6 Output Mode Register Port 7 Output Register Port 7 Input Register Port 7 Input Output Control Register Port 7 Output Mode Register VIII 150 Ports Port 8 Output Register Port 8 Input Register Port 8 Input Output Control Register Port 8 Output Mode Register Port 9 Output Register Port 9 Input Register Port 9 Input Output Control Register Port 9 Output Mode Register Port A Output Register Port A Input Register Port A Input Output Control Register Port Pull up Control Register Word Data Byte Swap Register Pointer Data Byte Swap Register L Pointer Data Byte Swap Register H Long word data Byte Swap Register L Long word data Byte Swap Register H x 00FFC8 x 00FFD8 x 00FFE8 x 00FFF8 x 00FFC9 x00FFD9 x 00FFE9 9 x00FFDA x 00FFBO 2 4 6 x 00FFA8 Chapter 8 Ports Ports 151 Chapter 8 Ports The port output register PnOUT sets the data to be output The port input register PnIN reads the pin val
234. r 0 Underflow Interrupt Enable Flag 8 IRQO Interrupt Enable Flag 6 Timer 5 Underflow Interrupt Request Flag 5 Timer 0 Underflow Interrupt Request Flag 4 IRQO Interrupt Request Flag 2 Timer 5 Underflow Interrupt Detect Flag 1 Timer 0 Underflow Interrupt Detect Flag 0 IRQO Interrupt Detect Flag IX 196 Data Appendix 000 level 0 to 110 level 6 0 Disable 1 Enable 0 Disable 1 Enable 0 Disable 1 Enable 0 No interrupt requested 1 Interrupt requested 0 No interrupt requested 1 Interrupt requested 0 No interrupt requested 1 Interrupt requested 0 No interrupt detected 1 Interrupt detected 0 No interrupt detected 1 Interrupt detected 0 No interrupt detected 1 Interrupt detected G1ICR x 00FC42 Maskable Interrupt Control Register 1 8 16 bit access register Set 1 when timer 5 underflows Set 1 when timer 0 underflows Set 1 when an external interrupt occurs from IRQO pin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 G2 G2 G2 2 TM1 IRQ1 AN TM1 IRQ1 AN TM1 IRQ1 LV2 LV1 LVO IE IE IE IR IR IR ID ID ID R R RW RW RW R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 14 12 Group 2 Interrupt Priority Level 10 A D Conversion End Interrupt Enable Flag 9 Timer 1 Underflow
235. r 24 bit data registers Four 24 bit address registers Others 24 bit program counter 16 bit processor status word 16 bit multiplication division register Instruction 36 instructions 6 addressing modes One byte primitive instruction length Code assignment 1 to 2 bytes Basic 0 to bytes Extension Basic Performance 10 MHz internal operating frequency with a 20 MHz oscillator and internal 4x speed Clock cycles For instruction execution minimum 1 cycle 100 ns For register to register operations minimum 1 cycle For load store operations minimum 1 cycle For conditional branching operations 1 to 3 cycles Pipeline 3 stages Instruction fetch decode execute Address Space 16 MB linear address space External Bus Address 24 bits 4CS signals Data 8 16 bit Minimum bus cycle 1 cycle at 100 ns 20 MHz Bus width and wait cycle is set in 4 MB unit Selectable from handshake or fixed bus wait mode ROM burst mode support Selectable from either address data separate pin or address data share pin Low power Mode SLOW mode STOP mode HALT mode Frequency Circuit High speed max 22 6 MHz Low speed 32 kHz I 8 Basic Specifications Chapter 1 Overview Table 1 2 1 Basic Specifications 2 2 Interrupt 26 vectors 3 non maskable interrupts 23 maskable interrupts 7 interrupt priority level settings External interrupts 5 external interrupts individual IRQ edge
236. r A TM6CA The valid range for TM6CA is 1 to x FFFE TM6CA x 00FE34 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 6 6 6 TM6 TM6 6 6 6 6 6 6 6 6 6 6 6 CA15 CA14 CA13 CA12 11 10 CA9 CA6 5 CA4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 Set the phase difference for timer 6 Since the phase difference is 2 cycles set 1 to the timer 6 compare capture register B TM6CB The valid range for TM6CB is 1 2 TM6CB lt TM6CA TM6CB 00 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 6 6 TM6 6 TM6 6 TM6 6 6 6 6 CB15 CB14 CB13 CB12 1 10 9 CB8 CB7 CB6 5 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 Set TM6NLD and TM6EN of the timer 6 mode register TM6MD to 1 and 0 respectively This enables TM6BC T F F and RS F F TM6MD x 00FE30 15 14 13 12 is EN NLD UD1 UDO TGE ONE MD1 MDOJECLR LP ASEL S2 51 SO 04 ve 6 Set both TM6NLD and TMGEN to 1 This starts the timer 6 Counting starts at the beginning of the next cycle When SYSCLK operates in normal and halt modes the external T
237. r at 17 2032 MHz Baud Rate Divisor Real Time 1200 448 1200 00 2400 2400 00 4800 4800 00 9600 9600 00 19200 19200 00 28800 28294 74 31250 31623 53 38400 38400 00 48000 48872 73 57600 59733 33 76800 76800 00 153600 179200 00 268800 268800 00 0 00 Available with Timer 0 in case of the divisor of 256 or greater Table 5 1 7 Baud Rate Setup Example in Asynchronous Mode External Oscillator at 14 MHz Baud Rate Divisor Real Time 1200 1188 86 2400 2377 72 4800 4755 43 9600 9510 87 19200 19021 74 28800 29166 67 31250 31250 00 38400 39772 73 48000 48611 11 57600 54687 50 76800 72916 67 153600 145833 33 218750 218750 00 Available with Timer 0 in case of the divisor of 256 or greater Table 5 1 9 Baud Rate Setup Example in Asynchronous Mode External Oscillator at 10 MHz Real Time 1201 92 2403 85 4807 69 9469 70 19531 25 28409 09 31250 00 39062 50 44642 86 62500 00 78125 00 156250 00 156250 00 0 00 Available with Timer 0 in case of the divisor of 256 or greater Available with Timer 0 in case of the divisor of 256 or greater Table 5 1 6 Baud Rate Setup Example in Asynchronous Mode External Oscillator at 16 MHz Baud Rate Divisor Real Time 1200 417 1199 04 2400 208 2403 85 4800 104 4807 69 9600 9615 38 19200 19230 77 28800 29411 76 31250 31250 00 38400 38461 54 48000 50000 00 57600 55555 56 76800 71428 57 153600 166666 67
238. ration is not guaran teed in other modes Ports 157 Chapter 8 Ports 8 2 Byte Swap Registers 8 2 1 Overview This LSI series contains a word byte swap register point byte swap registers and long word swap registers The data is swapped and read as Figure 8 2 1 shows Word Byte Swap Register Point Byte Swap Register WBSWP x 00FFA0 All initial values are 0 PBSWPH xOOFFA4 PBSWPL xOOFFA2 All initial values are 0 bp15 8 7 0 bp23 16 15 87 0 A B WRITE A B C WRITE B A READ C B A READ Long word Byte Swap Register LBSWPH xOOFFA8 LBSWPL x OOFFA6 All initial values are 0 bp31 24 23 16 15 87 0 A B C D WRITE D C B A READ Figure 8 2 1 Byte Swap Register VIII 158 Byte Swap Registers Chapter 8 Ports 8 3 Pull up Control Register 8 3 1 Overview This LSI series contains a pin which sets a pull up resistor using the program See 9 2 3 List of Pin Functions Table 8 3 1 Pull up Control Register Corresponded us 007 to DOO ADO7 to ADOO P07 to 01510 008 AD15 to AD08 P17 to P11 13 to 16 26 to 29 A07 to A00 P27 to P20 30 to 33 35 to 38 A15 to A08 P37 to P30 39 to 42 44 to 47 A23 to A16 P47 to P40 WAIT P60 RE WEH WEL BSTRE P63 to P61 P56 CS3 to CS0 P53 to P50 0 1 2 3 4 5 6 7 8 9 SBT1 SBI1 SBO1 P75 to P73 Always set to 0 Pull up Control Register VIII 159 Chapter 8 Ports
239. re 2 1 3 Figure 2 1 4 Figure 2 1 5 Figure 2 1 6 Figure 2 1 7 Figure 2 1 8 Figure 2 1 9 Figure 2 1 10 Figure 2 2 1 Figure 2 2 2 Figure 2 2 3 Figure 2 2 4 Figure 2 2 5 Figure 2 2 6 Figure 2 2 7 Figure 2 2 8 Figure 2 2 9 Figure 2 2 10 Figure 2 2 11 Figure 2 2 12 Figure 2 2 12 Overview Address Space e pt e HU eR EE EE ERR UR IEEE I 5 Interrupt Controller Configuration 7 Interrupt Serving Sequence I 7 Block Diagram y te ERR bie nidi iet etes I 10 Pin Configuration eet tette de ere t badass Bees I 12 OSCI and OSCO Connection Example 1 22 XI XO Connection 1 22 Reset Connection Example oret ne dpi dcin 1 22 WAIT Signal Control Circuit Example 2 1 22 100 pin LQFP 14 mm square 1 23 Bus Interface Address Space ete ned e eet etu II 26 Bus Controller su sce tete i nte tb n ee II 27 Memory Expansion Mode Address Data Shared Pin Configuration II 28 Memory Expansion Mode Address Data Separated Pin Configuration II 28 Processor Mode Address Data Shared Pin Configuration II 29 Processor Mode Address Data Separated Pin Configuration II 29 Smgle chip MOde eri e nep re ido e Petre II 30 ROM Timing for Burst Mode 4 bytes for Page Size
240. reception end interrupt occurred during the serial 0 reception ATCDIR 0 When this error occurs setting bit 14 OVREF of the ATCCTR register to 1 as well as negating bit 15 ATCEN ends the ATC operation forcibly At this point the data stored in the address which subtracted by 1 from the internal RAM address the counter shows is invalid No data is stored in the address the ATCBC counter shows First the ATC binary counter ATCBC sets the start address of internal RAM Next the ATCBC counter shows the RAM address to write or read during ATC operation The internal RAM area where the ATC can transfer the data is 1 k byte of x 008000 to x 0083FF The upper 14 bits are fixed at 00000000111000 Therefore the lower 10 bits are read when the ATCBC counter is read The address in the ATCCTR register or the ATCBC counter is set to only lower 10 bits 7 2 ATC Setup Examples 7 2 1 Serial Reception The ATC transfers the serial transmit receive buffer contents to inter nal RAM automatically after the serial reception is completed The ATC generates an ATC transfer end interrupt after the ATC transfers 5 times and starts software processing The start address of the ATC destination is 0 m Serial Interface 0 Setup 1 Enable an ATC transfer end interrupt G6ICR x 00FC40 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 G6 G6 G6 ITM6BITM6AITM6U TMeB TMeA TM6U
241. register 0 Disable 1 Enable 0 Disable 1 Load TM4BR to TM4BC Reset the 1 2 divisor circuit Fix TMIO output to 0 00 TM4IO pin clock Event timer 01 Timer 3 cascade 10 Timer 0 output clock 11 Low speed clock 32 kHz 4 TM5MD x 00FE25 Timer 5 Mode Register 8 bit access register 16 bit access is possible 0 Disable from even address 1 Enable 0 Disable 1 Load TM5BR to TM5BG Reset the 1 2 divisor circuit Fix TMIO output to 0 00 5 pin clock Event timer 01 Timer 4 cascade 10 Timer 0 output clock 11 Low speed clock 32 kHz 4 Chapter 9 Appendix 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM6MD 6 TM6 6 TM6 6 6 6 6 6 6 6 TM6 6 TM6 EN NLD UD1 UDO TGE ONE MDO ECLR LP S2 51 50 x 00 30 R W RAW R R R W R W R W RW R W R W R W R W R W RW R W Timer 6 Mode Register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 04 01 01 16 bit access register 15 TM6BC Count 0 Disable 1 Enable 14 TM6BC T F F RS F F 0 Set TM6BC T F F RS F F to 0 Operation 1 Operate TM6BC RS F F 11 10 Up Down Counter Mode 00 Up counter Selecting up down counting Selection Ignored when two 01 Down counter mode is ignored wh
242. rflow 0 Disable 1 Enable Interrupt Enable Flag Set 1 when a timer 7 underflow 6 Timer 7 Compare Capture 0 No interrupt requested interrupt or compare capture in Interrupt B Request Flag 1 Interrupt requested terrupt occurs 5 Timer 7 Compare Capture 0 No interrupt requested Interrupt A Request Flag 1 Interrupt requested 4 Timer 7 Underflow 0 No interrupt requested Interrupt Request Flag 1 Interrupt requested 2 Timer 7 Compare Capture 0 No interrupt detected Interrupt B Detect Flag 1 Interrupt detected 1 Timer 7 Compare Capture 0 No interrupt detected Interrupt A Detect Flag 1 Interrupt detected 0 Timer 7 Underflow 0 No interrupt detected Interrupt Detect Flag 1 Interrupt detected IX 202 Data Appendix 15 14 13 12 11 10 9 8 7 5 4 3 2 1 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQO IRQO TG1 TGO TGO TGO R R R W RW RW RW RAW RW RW RW 0 0 0 0 0 9 8 Set Trigger Conditions 00 Low level for IRQ4 Pin Interrupt 01 High level 10 Negative edge 11 Positive edge 7 6 Set Trigger Conditions 00 Low level for IRQ3 Pin Interrupt 01 High level 10 Negative edge 11 Positive edge 5 4 Set Trigger Conditio
243. rial interface eSBD Data input pin for serial interface eGND Ground When VDD is too low serial writer supplies power to the target board for programming When level 15 too low serial writer generates error message NRST pin outputs microcontroller reset signal Connect pull up resistors on the target board to NRST SBT SBD pins which are connected to the power supply The pull up resistance should be 4 7 0 47 min to 10 1 max NRST SBT SBD pins are output from the serial writer through an open connection Flash EEPROM Version 269 Chapter 9 Appendix 4 Microcontroller clock on the target board For the clock supply to the microcontroler on the target board use the existing target board clock Therefore each user uses different oscillator frequency for the microcontroller clock Following table shows maximum minimum rating of the oscillator frequency for the microcontroller clock Clock frequency Clock frequency Target power Max Min 4 5 V to 5 5 V Table 9 6 1 Maximum minimum rating of the Oscillator Frequency IX 270 Flash EEPROM Version Chapter 9 Appendix 9 6 8 On board Programming Mode Setup 1 Onboard programming mode setup To enter serial programming mode the microcontroller must be in write mode This section describes the pin setup for the serial writer interface Normal timing waveform Timing waveform during serial programming
244. ring the initialization program The MEMMDO register sets the wait cycle for the device connected to Block 0 The bits for selecting bus mode do noe exist in the MEMMDO register like other MEMMDn registers because the bus width for Block 0 is selected using the pin Setting the WAIT 1 0 is ignored in the burst ROM support area when using burst ROM MEMMDO x 00FC30 15 14 13 12 11 10 9 8 ri 6 5 4 3 2 1 0 WAIT1 WAITO Wait cycle for Block 0 00 No wait 01 1 wait 10 2 wait 11 Handshake The MEMMD register sets the wait cycles and bus mode for Block 1 MEMMD1 x 00FC32 Chapter 2 Bus Interface 15 14 13 12 11 10 9 8 7 6 2 1 0 RESHT BSMOD WAIT1 WAITO Wait cycle for Block 1 00 No wait RE pulse width shortening Bus mode for Block 1 01 1 wait 0 1 2 wait cycle 0 16 bit bus mode 10 2 wait 1 1 4 wait cycle 1 8 bit bus mode 11 Handshake The MEMMD register sets the wait cycles and bus mode for Block 2 When using the address converted area x 000000 to x OODFFP set the bus width for block 2 as the same as the bus width for block O MEMMD 2 x 00FC34 15 14 13 12 11 10 9 8 7 6
245. rity bit to 1 SCnPTY 2 0 101 if the ACK does not return During transmission reception the transmit state flag of the SCnSTR register shows the transmission reception in progress m Asynchronous Serial Transfer Speed In asynchronous mode set the serial transfer clock to 16 times of transfer baud rate The following is the baud rate calculation Baud Rate OSCI OSCO x 1 32 x 1 timer divisor The transmission is possible if the baud rate error is within 2 Table 5 1 3 to Table 5 1 10 show the baud rates with frequently used oscillators Table 5 1 3 Baud Rate Setup Example in Asynchronous Mode External Oscillator at 20 MHz Baud Rate Divisor Real Time 1200 520 1201 92 2400 2403 85 4800 4807 69 9600 9615 38 19200 18939 39 28800 28409 09 31250 31250 00 38400 39062 50 48000 48076 92 57600 56818 18 76800 78125 00 153600 156250 00 307200 312500 00 5 312500 312500 00 0 00 Max Available with Timer 0 in case of the divisor of 256 or greater Table 5 1 5 Baud Rate Setup Example in Asynchronous Mode Chapter 5 Serial Interface Table 5 1 4 Baud Rate Setup Example in Asynchronous Mode External Oscillator at 19 6608 MHz Baud Rate Divisor Real Time 1200 520 1181 54 2400 2363 08 4800 4726 15 9600 9452 31 19200 19200 00 28800 29257 14 31250 30720 00 38400 38400 00 48000 47261 54 57600 55854 55 76800 76800 00 153600 153600 00 307200 307200 00 0 00 Max External Oscillato
246. rocessor mode 1 A22 output or STOP output Selection is determined by set ting with P6MD 5 Port 4 Output 0 5 output 1 A21 output 4 Port 4 Output 0 4 output 1 A20 output 3 Port 4 Output 0 output 1 A19 output 2 Port 4 Output 0 42 output 1 A18 output 1 Port 4 Output 0 P41 output 1 A17 output 0 Port 4 Output 0 40 output 1 A16 output Data Appendix IX 241 Chapter 9 Appendix P5MD x 00FFF5 Port 5 Output Mode Register 8 bit access register 16 bit access is possible from even address 1 BSTRE output address data separated Bits 6 3 0 of P5MD are invalid during processor mode 1 ALE ALE output address data shared 7 6 5 4 3 2 1 0 P5 P5 MD6 MD5 MD4 MD2 1 MDO R W RAW RW RW RW RW 0 0 0 0 on or ort 6 Port 5 Output 0 P56 output mode 0 P56 output 5 Port 5 Output mode 4 Port 5 Output 0 P55 output 3 Port 5 Output 0 P54 output 2 Port 5 Output 0 P53 output 1 Port 5 Output 0 P52 output 0 Port 5 Output 0 P51 output 0 P50 output 7 6 5 4 3 2 1 0 P6 P6 P6 P6 P6 MD7 MD6 MD3 MD2 MD1 R R RW RW R 0 0 0 0 0 0 on o 7 Selection When P6MD7 is High 0 A23 output 6 Select
247. rom the slave correctly If a parity error does not occur the response is not obtained from the slave This step is not required in the system without ACK When the data is transmitted continuously repeat the steps 3 to 5 Data Reception 6 Load the dummy data x FF to the serial 0 transmit receive register SCOTRB This allows the SBO pin to output resistive high because the SBO pin is an open drain pin and input low when the slave outputs low 7 After reception ends retrieve the received data by reading the serial 0 transmit receive register SCOTRB When the data is received continuously repeat the steps 6 and 7 Stop Sequence gt 8 Set the IPC sequence output bit of the serial 0 control register SCOCTR to 0 This makes the SBT pin output high and generates the stop sequence SCOCTR 00 080 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCO 5 0 500 500 8500 SCO SCO SCO SCO SCO SCO SCO SCO 5 0 SCO BRE 225 PTL OD l2CM LN PTY2 PTY1 PTYO SB POD 51 SO 1 1 0 0 1 1 1 1 1 0 1 0 1 0 1 9 Disable the reception enable flag once immediately after the stop sequence is generated 1 C Sequence Output Bit Write to SCOTRB Register SBO Pin Output Transmitting the dummy data for reception 1 b6 b5 64 63 b2 61 bo Jack
248. roup 3 Interrupt Priority Level 11 Serial 0 Reception End Interrupt Enable Flag 10 Serial 0 Transmission End Interrupt Enable Flag 9 Timer 2 Underflow Interrupt Enable Flag 8 IRQ2 Interrupt Enable Flag 7 Serial 0 Reception End Interrupt Request Flag 6 Serial 0 Transmission End Interrupt Request Flag 5 Timer 2 Underflow Interrupt Request Flag 4 IRQ2 Interrupt Request Flag 3 Serial 0 Reception End Interrupt Detect Flag 2 Serial 0 Transmission End Interrupt Detect Flag 1 Timer 2 Underflow Interrupt Detect Flag 0 IRQ2 Interrupt Detect Flag IX 198 Data Appendix 000 level 0 to 110 level 6 0 Disable 1 Enable 0 Disable 1 Enable 0 Disable 1 Enable 0 Disable 1 Enable 0 No interrupt requested 1 Interrupt requested 0 No interrupt requested 1 Interrupt requested 0 No interrupt requested 1 Interrupt requested 0 No interrupt requested 1 Interrupt requested 0 No interrupt detected 1 Interrupt detected 0 No interrupt detected 1 Interrupt detected 0 No interrupt detected 1 Interrupt detected 0 No interrupt detected 1 Interrupt detected G3ICR x 00FC46 Maskable Interrupt Control Register 3 8 16 bit access register Set 1 when the serial 0 reception ends Set 1 when the serial 0 trans mission ends Set 1 when timer 2 underflows Set 1 when an external interrupt occurs from IRQ2 pin
249. rrupt Handling Registers R W CPUM W CPUM W CPUM W GOICR R W Procedure 1 2 3 3 4 5 6 7 Figure 3 3 2 Watchdog Timer Interrupt Timing Interrupt Setup Examples III 63 Chapter 4 Timers Counters Chapter 4 Timers Counters 4 1 Timers 4 1 1 Overview This LSI series contains six 8 bit timers timer 0 to timer 5 and two 16 bit timers timer 6 and timer 7 Table 4 1 1 Timer Function 1 2 Timer 8 bit Timer Function Timer 0 Timer 1 Timer 2 Timer 3 Interrupt Request Destination Group 1 G1ICR Group 2 G2ICR Group 3 G3ICR Group 4 G4ICR TMOIR TM2IR TM3IR Interrupt Source Timer 0 underflow Timer 1 underflow Timer 2 underflow Timer 3 underflow Clock Source TMOIO pin TM1IO pin TM2IO pin 128 1 fxi 4 Timer 1 Timer 2 2 Timer 0 Timer 0 Timer 0 fxi 4 3 9 o 0 Counting Method Down counting Down counting Down counting Down counting Interval Timer Event Counter Timer Output PWM Two phase Timer Output 2 i One shot Pulse Output S One phase Capture Input Two phase Capture Input E Two phase Encoder External Count Direction Control 2 E External Count Reset Control E Serial Interface Transfer Clock Genera tion A D Conversion Timing Generation
250. rt 3 Output from even address IX 230 Data Appendix Chapter 9 Appendix 7 6 5 4 3 2 1 0 P 40 U T P4 i OUT7 OUT6 OUT5 OUT4 OUT3 OUT OUT x 00FFC4 RW RAW Rw Rw Rw Rw RW Port 4 Output on on on on on on Register 8 16 bit access register 7 0 Port 4 Output 7 2 P5OUT P5 P5 ouT7 oure ours our4 oura oure ourt ouro x 00FFC5 RAW RAW RW RW RW RW Rw RW Port 5 Output eee AG Reaister ot o on on on 9 8 bit access register 16 bit access is possible 7 0 5 Output from even address 7 6 5 4 3 2 1 0 P6OUT P6 P6 P6 P6 OUT3 OUT2 OUT1 x OOFFC6 R Rw RW RW Port 6 Output ololololojlolo o Register o o on g 8 16 bit access register 3 0 Port 6 Output Data Appendix IX 231 Chapter 9 Appendix 7 6 5 4 3 2 1 0 P70 UT w P7 P7 P7 P7 P7 P7 OUT5 OUT4 OUTS OUT2 OUT1 OUTO X 00 FFC7 R R R W RW RW RW RW RW Port 7 Output 0 0 0 0 0 0 0 0 Re ister 0 0 0 1 0 1 g
251. rt output during processor mode Port ALE Select BSTRE during address data separated mode ALE ALE during ad dress data shared mode Reserved P57 Pin Port Input Select the port input during single chip mode Otherwise select WORD input WORD Input VIII 154 Chapter 8 Ports m P60 Port Input Select WAIT input when the clock is set to handshake mode Otherwise select the WAIT Input port input m P63 to P61 Pins Selection P6DIRn P6MDn Description 3 10 1 n 3 to 1 Port Input Do not select the port input or the port output during processor mode WEH WEL RE ar m P73 and P70 Pins Selection P7MDn Description n 3 0 n 3 0 Port Input Operate as a serial clock input pin when setting the serial clock source to the Serial Clock Input SBT pin including mode Serial Clock I O Become output only when this LSI series output during bidirectional syn Half duplex chronous transfer Serial Clock 1 Output 1 P74 and P71 Pins Selection P7DIRn Description 4 1 Port Input Operate as a serial data input pin when the serial reception is enabled Serial Input m P75 and P72 Pins Selection P7DIRn P7MDn Description 5 2 5 2 Port Input Select the port input during mode Ports 155 Chapter 8 Ports P87 to P80 Pins Selection P8DIRn P8MDn Description n 7 to 0 n 7 t
252. rupt the binary counter value omitted the timer 2 binary counter may not start at the first cycle 7 Set both TM2LD and TM2EN to 0 This starts timer 2 Counting starts at the beginning of the next cycle When the timer 2 binary counter value reaches 0 and loads the value of 3 from the timer 2 base register TM2BR a timer 2 underflow interrupt request occurs Interrupt Enable TM2BR 00 03 TM2BC 00 03 02 01 00 03 Timer 2 P ome Underflow Interrupt k TM2IO TM2MD W G3ICRIW TM2BR W TM2MD W TM2MD W TM2MD W Procedure 2 3 4 5 6 7 Figure 4 2 1 Event Counter Timing 8 bit Timer Setup Examples IV 81 Chapter 4 Timers Counters This verification is unnecessary immediately after a reset If setting 1 of divisor write the dummy value for example once IV 82 8 bit Timer Setup Examples 4 2 2 Clock Output Using 8 bit Timer Timer O to timer 5 contain clock output functions The setup proce dures for timer O to timer 5 are same In this example timer 0 and timer 1 output 12 clock cycles SYSCLK 6 8 bit Timer 8 bit Timer SYSCLK Timer 1 m gt Clock Output 1 0 MHz Divided by 2 Divided by 3 Figure 4 2 2 Clock Output Configuration 1 Timer 0 Setup 1 Verify that timer 0 counting is stoppe
253. s eese V 116 5 2 1 Serial Transmission in Asynchronous Mode Using Timer 2 D V 116 5 2 2 Serial Reception in Synchronous Mode Using Timer 2 ah Shu a E V 120 5 2 3 Serial Transmission Reception in PC Mode Using Timer 3 anb AN RS naa ae V 121 lii Contents iv Contents Chapter 6 6 1 6 2 Chapter 7 7 1 7 2 Chapter 8 8 1 8 2 8 3 Analog Interface Analog a oe m SD VI 124 6 1 1 VI 124 6 1 2 Control Registers VI 129 Analog Interface Setup Examples VI 130 6 2 1 One Channel A D Conversion Using AN2 Pin VI 130 6 2 2 Multiple Channels A D Conversion Using AN2 to ANO Pins VI 132 ATC nui VII 136 7 1 1 OVerVvieW cen idi eere eo inei ep VII 136 7 1 2 Control R gist ers eee eet VII 138 Setup Examples 5 re e bere ene VII 139 7 2 1 Serial Reception eee eter VII 139 Ports eee EG VIII 142 8 1 1 OVerVIe Witten ette VIII 142 8 1 2 Control Reglstets ictor eet tri VIII 150 Byte 158 8 2 1 OVERVIEW ices tala EE VIII 158 Pull up Control Register VIII 159 8 3 1 ONE p VIII 159 Chapter 9 9 1 9 2 9 3 9 4 9 5 9 6 Appendices Electrical eerte ao IX 162 9 1 1 Electrical Characteristics 5 2 2 2222 2 2 IX 162 Data
254. s Stop TM7BC counting and initial ize clear TM7BC and RS F F If this step is omitted TM7BC not count during the first cycle IV 106 16 bit Timer Setup Examples 4 3 9 External Reset Control Using 16 bit Timer The external reset control setup procedures for timer 6 and timer 7 are same In this example timer 7 is reset by an external signal while counting up W Timer 7 Setup 1 Set the operating mode to the timer 7 mode register TM7MD Verify that counting is stopped and an interrupt is disabled Select up counting Set TM7ECLR to 1 becuase TM7BC is reset by TM7IC pin asynchronously Select SYSCLK as the timer 7 clock source TM7MD 00 40 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM7 TM7N TM7 7 7 TM7 7 7 7 7 7 7 7 7 EN LD I I UD1 UDO TGE ONE MDO ECLR LP 52 51 S0 2 Set the timer 7 looping value the valid range is 1 to x FFFF When writing x 1FFF to TM7CA The TM7BC counts from 0 to x 1FFF TM7CA x 00FE44 1 12 5 14 13 11 10 9 8 7 6 5 4 3 2 1 0 TM7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 CA15 CA14 CA13 CA12 11 10 CA9 CA6 5 CA4 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 3 Set TM7NLD and T
255. s 7 9 2 2 411 0 0000000000000000000000000000000000 1 19 List of Pin Funactions 8 9 1 20 List of Pin Funactions 9 9 enne enne enne enne 1 21 Bus Interface CS Signal Generation ete ete Gite oe t ineo II 27 List of Bus Interface Control Registers II 32 Interrupts List of Interrupt Control Registers 56 Timers Timer Function 1 2 rrt tit eH I e cut ene IV 66 Timer Function 2 2 au sondere easiest ee hee avec IV 67 List of Timer Control Registers IV 74 Overview Serial Interface Features sasana saa ishu uu V 110 List of Serial Interface Control registers asss 111 Baud Rate Setup Example in Asynchronous Mode 2 2222222 22 V 115 Baud Rate Setup Example in Asynchronous Mode V 115 Baud Rate Setup Example in Asynchronous Mode V 115 Baud Rate Setup Example in Asynchronous Mode V 115 Baud Rate Setup Example in Asynchronous Mode V 115 Baud Rate Setup Example in Asynchronous Mode V 115 Baud Rate Setup Example in Asynchronous Mode V 115 Baud Rate Setup Example in Asynchronous Mode
256. s WEH WEL and RE pins during processor mode During processor mode P6MD3 to PeMD 1 are invalid BIFPO WAITP External memory Interface Signal Output Control Bus Controller P6DIR3 to 0 P6MDS to 0 P6OUTS to 0 M P63 to 60 External memory Interface Signal 1 WEH WEL Bus Controller P60 does not have MUX RE WAIT P6IN3 to 0 i WAIT Bus Controller VIII 146 Ports Chapter 8 Ports Table 8 1 1 Port Functions 6 of 8 Port Pin Function Shared Pin Port 7 is used as the port 7 general purpose port or serial interface signal pins At reset this port operates as a general purpose port input SB1P SBOP Serial Data Enable P7DIR5 P7DIR2 P7MD5 P7MD2 P7OUT5 P7OUT2 Serial I F Data Output _______ P75 5801 P72 5800 P7IN5 P7IN2 SB1P SBOP P7DIR4 P7DIR1 P74 SBI1 P71 SBIO P7OUT4 P70UT1 P7IN4 P7IN1 Serial Data Input SB1P SBOP Serial Clock Enable P7DIR3 P7DIRO A P7MD3 P7MDO B Decoder note P7OUT3 P7OUTO ed 73 8 1 P70 SBTO Serial Clock Output
257. s halted for Internal flash EEPROM to be programed Use the dedicated adaptor socket which connects to the dedi cated PROM writer When the mocrocontroller connects to the adaptor Socket it automatically enters PROM writer mode Flash EEPROM Version 263 Chapter 9 Appendix 9 6 4 Onboard Serial Programming Mode The onboard serial programming mode is primarily used to program the flash EEPROM in devices that are already installed on a PCB board with internal serial interface Use the dedicated serial writer for programming controlled by the load program In this mode load program is write erase protected in the hardware When you use the YDC serial writer follow the instructions Standard onboard serial programming writer comes with load program 9 6 5 Hardware requirements 1 Hardware for flash ROM programming on this LSI are as follows 8 bit serial interface 1 set Data transmission reception Transfer bit LSB first Clock speed over 10 MHz max Input output through positive logic eInput output pin 2 pins and SBD pins for serial I F 2 I F Block Diagram RXD TXD SBD 74pin 8 bit serial RXC TXC SBT 73pin Figure 9 6 3 8 bit Serial Interface Block Diagram IX 264 Flash EEPROM Version Chapter 9 Appendix 3 Internal flash EEPROM address space Address Size Description 0x80000 6 KB Serial writer load program area 0x81800 8 bytes Reserved 0x81807 0x
258. s series chi ch2 A D Conversion Data Buffers f Undertow Timer 1 CPU Figure 6 2 2 Multiple Channel A D Conversion W A D Conversion Control Register Setup 1 Setthe operating conditions to the A D conversion control register ANCTR Set ANMD to multiple channel single conversion and select the ANCK 1 0 bits to SYSCLK 4 10 MHz 4 with a 20 MHz oscillator Set ANEN and ANTM to 0 and 1 respectively Set AN1CH 2 0 to the first channel number to be converted channel 0 and ANNCH 2 0 to the last channel number to be converted channel 2 ANCTR x 00FDAO 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 AN AN AN AN NCH2NNCH1 NCHO 1CH2 1CH1 1CHO EN 1 CK1 MDO VI 132 Analog Interface Setup Examples 0 0 0 0 1 0 0 0 Timer 1 Setup 2 Set the timer 1 divisor Since timer 1 divides SYSCLK by 256 set the timer 1 base register TM1BR to 255 The valid range for TM1BR is 1 to 255 TM1BR x O0FE11 7 6 5 4 3 2 1 0 1 TM1 TM1 1 TM1 TM1 BR7 BR6 5 BR4 BR2 BR1 BRO 3 Load the TM1BR value to TM1BC To do this set TM1LD and TM1EN to 1 and 0 resepctively At the same time select
259. s those in the above 8 bit bus width PODIR to P2DIR P4DIR and POMD to P2MD P4MD are 6 Upto4k bytes 8bit same as those in the above 8 bit bus width of No 1 Use D07 to DOO as general purpose ports All to A00 D15 to D08 P3DIR o o o o P3MD Use A23 to A12 as general purpose ports 16bit PODIR to P2DIR P4DIR and POMD to P2MD P4MD are Use A23 to A12 as general purpose ports D15 to D00 same as those in the above 16 bit bus width of No 1 P3DIR and P3MD are same as those in the above 8 bit bus width PODIR to P2DIR P4DIR and POMD to P2MD P4MD are Upto 8k bytes 8bit same as those in the above 8 bit bus width of No 1 Use D07 to D00 as general purpose ports A12 to A00 D15 to D08 P3DIR o o o o o P3MD Use 23 to A13 as general purpose ports 16bit PODIR to P2DIR P4DIR and POMD to P2MD P4MD are Use A23 to A13 as general purpose ports D15 to D00 same as those in the above 16 bit bus width of No 1 P3DIR and P3MD are same as those in the above 8 bit bus width II 40 External Memory Connection Example PODIR to P2DIR P4DIR and POMD to P2MD P4MD are
260. sfer ends Setup Examples VII 139 Chapter 7 ATC 5 Set the mode of serial interface 0 See 5 2 Serial Interface Setup Ex amples for detail With the above setting when the serial reception is completed the ATC transfer the received data to memory automatically When the ATC transfers repeatedly until the set number of operation is reached an ATC transfer end interrupt occurs and the ATC transfer end interrupt service routine is executed Serial Reception A y B y y ATC Tranfer End Interrupt Processing Transfer Transfer Transfer Transfer Transfer Transfer Destination Memory S A NA x 00E0A0 A A A A A A B C D and E means 1 byte XOOEOAT B B B B kan X 00EOA2 C C C x 00E0A9 D D x 00E0A4 E yr yw J Figure 7 2 1 Serial Reception Data Transfer oser SYSCLK Serial Reception Serial Reception Serial End Interrupt Address PU Y OOEOAA aren 9 O X Bus Authority CPU m ATC CPU gt lt gt lt gt gt
261. sion End Interrupt 0 Transmitter TXD SBOO E TAS gt Reception End Interrupt 0 Receiver z RXD lt SBIO Transmission End Interrupt 0 Transmitter TXD SBO1 E SBT1 Reception End Interrupt 0 lt lt 581 Figure 5 1 1 Serial Interface Configuration Table 5 1 1 Serial Interface Features Synchronous Serial Interface Asynchronous Serial Interface PC Parity None 0 1 Even Odd ME Clock Source Timer 2 16 or Timer 3 16 Timer 2 16 or Timer 3 16 Timer 2 16 or Timer 3 16 External Clock Timer 2 2 Timer 3 2 Ch1 Max Transfer Speed 2 500 000 bps 312 500 bps 100 000 bps with 20 MHz Oscillator with a 20 MHz Oscillator Error Detect Parity Error Parity Error Slave Response Overrun Error Overrun Error Framing Error Buffer Independent Transmit Receive buffer Single Transmit Buffer Double Receive Interrupt Transmission End Interrupt Reception End Interrupt V 110 Serial Interface 5 1 2 Control Registers Three registers control the serial interface serial control register 5 serial transmit receive register SCnTRB and serial sta tus register SCnSTR Table 5 1 2 List of Serial Interface Control registers Serial Interface 0 Serial Interface 1 SCOCTR 00 080 SCICTR x 00FD90 SCOTRB x 00FD82 SCITRB x 00FD92 Serial Control Register Serial Status Register Serial 0
262. specification 1 external non maskable interrupt 20 internal interrupts 12 timer interrupts 4 serial interrupts 1 ATC interrupt 1 A D interrupt 1 watchdog timer interrupt 1 undefined instruction interrupt Timer Counter Six 8 bit timers down counters Reload timer Cascading function serve as 16 to 40 bit timers as well Timer output duty of 1 1 Internal clock source or external clock source Serial interface clock generation Start timing generation for A D converter Two 16 bit timers two up down counters 2 channels compare capture registers Internal clock source or external clock source Timer output duty of 1 1 max 4 PWM one shot pulse output max 2 2 phase encoder input x4 x1 17 bit watchdog timer ATC 1 channel Fixed between serial channel 0 to internal RAM Transfer request serial channel 0 transmission reception interrupt request Transfer rate 600 ns 1 byte data transfer rate at 20 MHz oscillating Serial Interface 2 UART synchronous shared serial interfaces Analog Interface A D converter Eight 8 bit inputs Auto scanning 1 to 8 channel settings Byte Swap Register 2 byte 3 byte and 4 byte swap are available Port 80 I O ports All shared pins except ROM less model 48 ports All shared pins of ROM less model Package 100 pin LQFP pitch 0 5 mm dimension 14 mm square Note ATC stands for Auto Transfer Control Refer to chapter 7 ATC for details Bas
263. ss Timing during Bus Request Address Data Separated Mode External Memory Connection Example II 47 Chapter 2 Bus Interface 2 2 3 Memory Expansion Mode Address Data Shared Mode In this LSI series the control registers for address or data setting need to be set as follows during address data shared mode See Chapter 8 Ports 1 Up to 64 Kbytes 8 16bit PODIR 0 POMD 1 Use A23 to A16 as general purpose ports mm P4DIR o o No 2 Up to 128 Kbytes 8 16bit PODIR to PIDIR and POMD and P1MD are set as same as Use A23 to 17 as general purpose ports those in the above P4DIR 1 P4MD No 3 5 i PODIR to and re set as same as Use A23 to A18 as general purpose ports those in the above P4DIR ofofo o o o No 4 Up to 512 Kbytes i PODIR to PIDIR and re set as same as Use A23 to A19 as general purpose ports those in the above P4DIR No 5 i PODIR to PIDIR and re set as same as Use A23 to A20 as general purpose ports those in the above P4DIR 1 ojojo No 6 i PODIR to and re set as same as Use A23 to A21 as general purpose ports those in the above P4DIR ip o o o
264. t Control Register 5 8 16 bit access register Set 1 when timer 4 underflows Set 1 when an external interrupt occurs from IRQ4 pin 15 14 13 12 10 9 8 7 5 4 3 2 1 G6 G6 G6 TM6B TM6eA TM6U TM6B TM6A TM6U TM6B TM6A TM6U LV2 LV LVO IE IE IE IE IR IR IR IR ID ID ID ID R W R W RAW RAW RW R R R R yo ot on ot ot on ot on on on 14 12 Group 6 Interrupt 000 level 0 to 110 level 6 Priority Level 11 ATC Transfer End 0 Disable 1 Enable Interrupt Enable Flag 10 Timer 6 Compare Capture 0 Disable 1 Enable Interrupt B Enable Flag 9 Timer 6 Compare Capture 0 Disable 1 Enable Interrupt A Enable Flag 8 Timer 6 Underflow 0 Disable 1 Enable Interrupt Enable Flag 7 ATC Transfer End 0 No interrupt requested Interrupt Request Flag 1 Interrupt requested 6 Timer 6 Compare Capture 0 No interrupt requested Interrupt B Request Flag 1 Interrupt requested 5 Timer 6 Compare Capture 0 No interrupt requested Interrupt A Request Flag 1 Interrupt requested 4 Timer 6 Underflow 0 No interrupt requested Interrupt Request Flag 1 Interrupt requested 3 ATC Transfer End 0 No interrupt dete
265. t 1 TM6IOA output 5 Port 8 Output 0 P85 output 1 5 output 4 Port 8 Output 0 P84 output 1 TM4IO output 3 Port 8 Output 0 P83 output 1 output 2 Port 8 Output 0 P82 output 1 2 output 1 Port 8 Output 0 P81 output 1 TM1IO output 0 Port 8 Output 0 P80 output 1 TMOIO output Data Appendix IX 243 Chapter 9 Appendix 71615 4 3 2 P9MD 9 9 MD4 MD2 MD1 x 00FFF9 R R 9 Register o 9 8 bit access register 16 bit access is possible 4 LED Drive Selection 0 Disable 1 Enable from even address 3 LED Drive Selection 0 Disable 1 Enable 2 Port 9 Output 0 P92 output 1 TM7IOB output 1 Port 9 Output 0 P91 output 1 TM7IOA output IX 244 Data Appendix Chapter 9 Appendix Data Appendix IX 245 Chapter 9 Appendix eq jouueo uoneJedo y Duisseooe j jou s sesseJppe Duisseooy pamasa 545 9 4400 pue 2 0400 0 sseooe 1Iq g USAS ue qissod si sseooe 1Iq 9 888008 558999 1Iq 9 O 888006 1Iq 9 8 OGLINL 073400 X o o 989 1 024400 024400 8
266. t Timing Timer 6 and Timer 7 IV 70 Two phase Encoder IV 70 Two phase Encoder 1x Timing Timer 6 and Timer 7 IV 71 External Count Direction Control Timing Timer 6 and Timer 7 IV 71 External Count Reset Control Two phase Encoder Timing Timer 6 and Timer 7 IV 71 Timer Configuration tote IV 73 Timer 0 Block Diagram IV 75 Timer I Block Diagram o Rote ee reet ter nti bees IV 75 Timer 2 Block Diagram u oreet ertet deese IV 76 Timer 3 Block Diagram IV 76 Timer 4 Block Diagrami 25h eror rr ttr ree dt IV 77 Timer Block Diagram IV 77 Timer 6 Block Diagram IV 78 Timer 7 Block Diagram eee eee eter teens IV 78 Event Counter Timing cie etre tbe reete IV 81 Clock Output Configuration 1 IV 82 Clock Output Timing ss pee bebe IV 84 Clock Output Configuration 2 IV 85 Interval Timer TIMIN o eni ge e TERES dete PER eed IV 87 Event Counter Timing n IV 89 PWM Timing ERREUR ea eee IV 92 PWM Timing in Double Buffer Mode eee IV 92 Two phase PWM IV 94 vii Contents viii Contents Figure 4 3 5 Two phase PWM Timing in Double Buffer Mode
267. the clock source TM1MD 21 7 6 5 4 3 2 1 0 TM1 TM1 TM1 TM1 EN LD 61 50 4 Set both TM1LD and TM1EN of the TM1MD register to O b Set TM1LD and TM1EN to 0 and 1 respectively This starts timer 1 Count ing starts at the beginning of the next cycle When the timer 1 binary counter TM1BC reaches 0 and loads the value of 255 from the timer 1 base register TM1BR a timer 1 underflow interrupt request occurs The A D converter converts each AN2 AN1 and ANO once when timer 1 underflows Timer 1 Underflow Conversion Cho Chi Ch2 Cho Chi Ch2 Interrupt Figure 6 2 3 A D Conversion Timing Single Conversion of Channel 2 to Channel 0 Chapter 6 Analog Interface Do not change the clock source afterthis step Changing the clock Source while controlling count op eration will corrupt the binary counter value If this setting is omitted the timer 1 binary counter may not start at the first cycle The periodical conversion saves the power consumption compared to the continuous conversion Analog Interface Setup Examples VI 133 Chapter 6 Analog Interface VI 134 Analog Interface Setup Examples Chapter 7 ATC Chapter 7 ATC 136 7 1 7 1 1 Overview This series contains an Auto Transfer Control which activates by an interrupt request T
268. timer 1 and timer 2 can form as a 16 bit timer cascading timer 3 timer 4 and timer 5 can form as a 24 bit timer Cascading these timers can form a 40 bit timer at most An underflow interrupt occurs only when these timers are down counting IV 72 Timers Timer 0 to Timer 5 Timer 0 to Timer 5 are 8 bit timers They are down counting and are divided by the 8 bit value set in the base register TMnBR plus one Do not set 0 to TMnBR An interrupt occurs when each timer underflows the binary counter changes from x 00 to the 8 bit value They can function as interval timers event counters clock output base clock for serial interface and A D conversion start timing Timer 6 and Timer 7 Timer 6 and Timer 7 are 16 bit timers They are up down counting Each timer has two compare capture registers TMnCA and TMnCB These registers cap ture and compare the up down counter value generate PWM and interrupts The PWM contains the double buffer mode that changes the cycle and transition from the next cycle This prevents the PWM waveform losses and distorts during timing changes These timers can function as interval timers event counters at clock oscillation one phase PWM two phase PWM two capture input dual two phase encoders one shot pulse generators and external count direction con trollers Chapter 4 Timers Counters Figure 4 1 13 shows the timer configuration Combining timers serves as various interva
269. tion 5 5 1 System Clock 10 MHz with a 20 MHz ocillator 128 2 System Clock 10 MHz with a 20 MHz ocillator 8 Low speed Clock 32 kHz 4 Timers 67 Chapter 4 Timers Counters TMnBC Value asss Za Value TMnIO Input Figure 4 1 1 Event Counter Timing Timer 0 to Timer 5 TMnBC Value TMnBR Value Interrupts TMnlO Output Figure 4 1 2 Timer Output Interval Timer Timing Timer 0 to Timer 5 TMnBC Value TMnCA TMnCB TMnIOA Output Figure 4 1 3 PWM Output Timing Timer 6 and Timer 7 IV 68 Timers Chapter 4 Timers Counters TMnBC Value Rewrite the TMnCB Keep in the current cycle Reflect the result from the next cycle value Time Output Figure 4 1 4 PWM Output Timing Data Write Timer 6 and Timer 7 TMnBC Value TMnOA LL Output TMnOB Output Figure 4 1 5 Two phase Timer Output Timing Timer 6 and Timer 7 TMnBC Value TMnIB Input TMnOA Hi Output Figure 4 1 6 One shot Pulse Output Timing Timer6 and Timer 7 Timers IV 69 Chapter 4 Timers Counters TMnBC Value FREF
270. tion waits of the high speed oscillation pin OSCI are performed approxi mately 6 ms to 7 ms with a 20 MHz oscillator After that the chip starts executing the instruc tion from x 080000 Figure 1 4 4 Reset Connection Example SYSCLK Output System Clock Output This pin provides the system clock After reset release the oscillation waits of OSCI are always performed and this pin outputs the clock of 10 MHz at a 20 2 oscillation Please keep in mind that this pin holds the high level until the oscilla tion waits are released after the RST pin becomes the low level MODE Input Memory Mode Input This pin sets either processor mode or single chip mode memory expansion mode Pulling the pin low sets the processor mode In proces sor mode internal ROM becomes the external memory area Pulling the pin high sets the single chip mode memory expansion mode t Chapter 2 1 1 2 2 3 Memory expansion mode Do not change the mode setting in this pin dur ing operation When the setting is changed proper operation is not guaranteed For ROM less model set this pin to L 57 WORD General purpose port 5 Data Bus Width Input This pin can be used as a general purpose in put output port only in single chip mode t Chapter 8 Ports This pin sets the data bus size of block 0 x 010000 to x3FFFFF which ob tained by dividing 16 byte space into four 0 to 3
271. to an interrupt level 0 and 1 respectively G1ICR x 00FC42 G1 G1 G1 TM5 TMO IRQ0 5 0 IRQO TM5 TMO IRQO LV2 LV1 LVO IE IE IE IR IR IR ID ID ID 3 Enable interrupts by setting the interrupt enable flag IE of the processor status Word PSW to 1 and the interrupt mask level IMn to 7 bit string 111 Thereafter an interrupt occurs when the negative falling edge is generated on the interrupt pin IRQO PAO The program branches to x 080008 when the inter rupt is accepted B Interrupt Handling 4 Specify the interrupt group by reading the interrupt accept group register IAGR during interrupt prehandling 5 Specify the interrupt vector in the group by reading the G1ICR register Check the IRQOID with the bit test instruction BTST If IRQOID is 1 execute the interrupt handling 6 Clear the IRQOIR bit of the G1ICR register 7 Return to the main program with the interrupt return instruction RTI after the interrupt handling ends EXTMD Low Level eds Edge HEN IRQOIR Interrupt Handling Registers R W EXTMD W GIICR R GIICR R W G1ICR R W Procedure 1 2 3 4 5 6 7 4 5 6 7 Figure 3 3 1 External Pin Interrupt Timing Chapter 3 Interrupts Normally the program generates the interrupt start addr
272. ts See 4 2 8 bit Timer Setup Examples for details Data Appendix IX 219 Chapter 9 Appendix 7 es s j TMOMD TMO TMO TMO TMO EN LD 51 50 x 20 RON E Timer 0 Mode Register 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 8 16 bit access register 7 TMOBC Count 0 Disable 1 Enable 6 TMOBR Setup 0 Disable 1 0 Clock Source Selection TM EN LD 1 80 R RW RW 0 1 0 1 0 0 0 0 0 1 0 1 7 TM1BC Count 6 TM1BR Setup 1 0 Clock Source Selection IX 220 Data Appendix 1 Load TMOBR to TMOBC Reset the 1 2 divisor circuit Fix TMIO output to O 00 TMOIO pin clock Event timer 01 System clock 128 10 System clock 11 Low speed clock 32 kHz 4 TM1MD 21 Timer 1 Mode Register 8 bit access register 16 bit access is possible 0 Disable from even address 1 Enable 0 Disable 1 Load TM1BR to Reset the 1 2 divisor circuit Fix TMIO output to O 00 TM11O pin clock Event timer 01 Low speed clock 32 kHz 4 10 Timer 0 output clock 11 System clock 7 6 5 4 3 2 1 0 TM TM2 TM TM2 EN LD S1 S0 RW RW R R R R RW RW 0 0 0 0 0 0 0 0 01 01 0 0 0A 7 TM
273. uction adds a zero or a sign extension The multiplication division register stores the upper 16 bits of the 32 bit product of the multiplication operations In division operations this reg ister stores the upper 16 bits of the 32 bit dividend before the execution and the 16 bit remainder of the quotient after the execution The processor status word indicates the CPU status This register stores the operation result flags and interrupt mask levels Memory special registers for controlling peripheral functions and ports are assigned to the same address space Internal Control Registers Interrupt Control Registers Serial Interface A D Converter Timers Counters Memory Control Registers ATC Control Registers I O Ports E Interrupt Controller The interrupt controller group 0 to group 7 allocated to the outside of the CPU controls all nonmaskable interrupts and maskable interrupts except reset Each group contains up to four interrupt vectors and specifies any of seven priority levels CPU Core Maskable Interrupt Non maskable Interrupt Reset Receive Receive Receive Interrupt Controller Interrupt Enable p Interrupt Mask Non maskable Interrupt Controller 3 14 1 Group 0 GOICR MT FER or 6 3 2 1 0 lt 3 Ples Maskable Interrupt Control
274. ues The port input output control register PnDIR sets the input or output of all bits or each bit The output mode register PnMD The pullup resistor is approxi selects the port output The port pull up control register PPLU selects on off of mately 30 See the product specifications for the exact value each pin m 07 POO Pins Port Input Select the port input or the port output only when 8 bit bus width for all spaces is selected during single chip mode or address data separated mode the word pi Port Output is high and all 8th bits of the to MEMMD 1 registers are high 007 to 000 Select 007 to DOO during address data separated mode AD07 to ADOO during 007 to AD00 address data shared mode Note Set only in 8 bit unit m P17 to P10 Pins Port Input L Select the port input or the port output only when single chip mode is se Port Port Output 1 lected 01510 008 Select D15 to D08 during address data separated mode AD15 to ADO8 AD15 to AD08 during address data shared mode Reserved Note E only in 8 bit unit m P23 to P20 Pins Port Input Do not select the port input or the port output in address data separated Port Output mode during processor mode om D T Note Set only in 4 bit unit m P27 to P24 Pins Port Input o o Do not select the port input or the port output in address data separated Port Output mode during pro
275. updated when the bit is received A framing error occurs when the stop bit is 0 The framing error data is updated when the stop bit is received Figure 5 1 2 shows the timing when each bit of the serial status register SCnSTR Chapter 5 Serial Interface Igonore MSB bit 7 in the 7 bit transmission Write the data to the serial trans mit receive register after verifying the data is not in transmission by checking the SCnTBSY of the SCnSTR register or transmis sion end interrupt The serial transmission may not occur if writ ing to the serial transmit receive register during the transmission is operated The MSB bit 7 becomes 0 in the 7 bit reception Serial Interface 111 Chapter 5 Serial Interface Asynchronous Synchronous Timing Transmission SBO bt b2 bs b4 bs be Write Data to SCnTRB Reset even when SCnTBSY F transmission is disabled Transmission Interrupt Reception SBI bO 61 b2 b3 b4 b5 be ST Reset even when SCnRBSY L reception is disabled Reception Interrupt Reset even when reception is disabled Read Data of SCnTRB SCnOE Overrun Error SCnPE Parity Error Update Update SCnFE Framing Error Update
276. us Width OSCI SYSCLK A23 00 10050 A00 1 D15 08 cs RE WEH 16 bit Read 8 bit Write Figure 2 2 7 1 Wait Access Timing with 8 bit Bus Width osci TU UL LI SYSCLK A23 00 015 08 cs WE 2 16 bit Write Figure 2 2 8 Handshake Access Timing with 8 bit Bus Width 46 External Memory Connection Example Chapter 2 Bus Interface m Access Timing during Bus Request Address Data Separated Mode OSCO SYSCLK A23 16 FLOATING 01500 D FLOATING A D TSn FLOATING mm BRE FLOATING RE FLOATING WEH WEL FLOATING WAIT BRACK x n Bus Master CPU External Device Figure 2 2 9 Acce
277. ut penalty 11 Enable With penalty Page Size of ROM Burst Mode 00 4 bytes 01 8 bytes 10 16 bytes 11 Reserved ALE Siganl Polarity 0 Pogitive logic 1 Negative logic No Wait cycle is forbidden in handshake mode address data separate mode 0 Disable 1 Enable WEH WEL Pulse Width Shortening 9 0 Disable 1 Enable Chapter 2 Bus Interface Bus Interface II 35 Chapter 2 Bus Interface 1 Use burst mode only during the address data separated mode Do not use burst mode during the address data shared mode Access area for burst mode is x 080000 to x OFFFFF The ac cess cycle in x 080000 to X OFFFFF is 1 wait cycle outside the page and no wait cycle in the page Bits 1 0 of the MEMMDO register are ignored II 36 Bus Interface 2 1 3 ROM Burst Mode Timing This LSI series supports interface for ROM corresponding to burst mode accesses The burst mode is a mode which reads the data of consecutive few bytes only few lower bits are changed at high speed access twice faster than normal access This series supports the lower 2 bits 4 bytes for page size the lower 3 bits 8 bytes for page size and the lower 4 bits 16 bytes for page size An A02 o 01 00 007 00 Figure 2 1 8 ROM Timing for Burst Mode 4 bytes for Page Size Chapter 2 Bus Interface This series has the access cy
278. valid in address data separated mode during proces sor mode Chapter 9 Appendix T 6 5 4 3 2 1 0 P3MD x 00FFF3 RAW RAW RW RAW RW RW RW Port 3 Output Mode o jojo 0 on on on on on Register 8 bit access register 16 bit access is possible 7 Port 3 Output 0 P37 output 1 A15 output from even address 6 Port 3 Output 0 P36 output 1 A14 output P3MD is invalid in address data Separated mode during proces 5 Port 3 Output 0 P35 output 1 A13 output sor mode 4 Port 3 Output 0 P34 output 1 A12 output 3 Port 3 Output 0 P33 output 1 A11 output 2 Port 3 Output 0 P32 output 1 A10 output 1 Port 3 Output 0 P31 output 1 A09 output 0 Port 3 Output 0 P30 output 1 A08 output SI PAMD P4 x 00FFF4 R W R W RAW RAW RW RW RW Port 4 Output Mode 0 0 x ot on Register 8 16 bit access register 7 Port 4 Output 0 P47 output 1 A23 output or WDOUT output Bits 5 0 of PAMD are invalid dur 6 Port 4 Output 0 P46 output ing p
279. when the output waveforms consist of 1s and Os TMnEN TMnCB Write TMnBC 0 0 1 2 3 4 1 2 3 4 0 1 2 3 4 1 2 3 SYSCLK CLRBC TMnCB 3 1 S R cr qoe q NR FN ETR B ae BRUM gt mt Figure 4 3 3 PWM Timing in Double Buffer Mode IV 92 16 bit Timer Setup Examples 4 3 3 Two phase PWM Output Using 16 bit Timer The two phase PWM output setup procedures for Timer 6 and Timer 7 are same except the up down counting selection In this example timer 6 divides SYSCLK by 5 and outputs two phase PWM signal on the fifth cycle The phase difference is 2 cycles Therefore set the divisor of 5 the set value is 4 to the timer 6 compare capture regis ter and the cycle of 2 the set value is 1 to the timer 6 compare capture B Pin Setup 1 Set the TM6IOA pin to output using the port 8 I O control register P8DIR and the port 8 output mode register P8MD P8DIR x 00FFE8 P8MD x O0FFF8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Ps P8 P8 P8 P8 P8 P8 P8 P8 PB DIR6 5 DIR4 DIR3 0182

MN102L610B/F61G LSI User`s Manual

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