Home

RCC User Manual - ADI Engineering

1. 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 39 of 42 D ADI Engineering The Open IP ODM ENGINEERING 5 Open FlashPro program 6 Select New Project button FP FlashPro DER File Edit View Tools Programmers Configuration Customize Help ED oF ld E BE j im E Men Project ih Open Project a Microsemi Gs FlashPro Version 10 1 3 1 Release v10 1 SP3 Checking for software updates DAAI A Errors A Warnings A Info ees No project loaded Figure 42 FlashPro New Project 7 Enter name for new project and select location Single device should be selected New Project Project Name CC update Project Location TitempiFPaalroc update Programming mode Single device chain Figure 43 FlashPro New Project Name 8 Select Configuration gt Load Programming File September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 40 of 42 ADI Engineering The Open IP ODM FDI ENGINEERING File Edit View Tools Programmers Memis e Customize Help D oa bh CN REH Select Action Serialization Load Programming File Unload Programming File Create PDE Select Target Device Chain Parameter Figure 44 FlashPro Load Programming File 9 Select PROGRAM button 10 Wait for program to Erase Program and then Verify update FP FlashPro rcc_upd
2. Pci x16 8x0 USB Ox 0x0 USB Gx1 6x8 Press ESC in 3 seconds to skip any other key to continue Figure 36 Indentify USB flash drive in EFI shell 8 Goto USB flash drive by typing fs1 followed by ENTER September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 35 of 42 ADI Engineering The Open IP ODM ENGINEERING 9 Goto the folder with the BIOS update utility and BIOS binary 10 Type the command AfuEfix64 efi filename rom p b n to update the BIOS filename rom is the BIOS file 11 Wait for utility to complete DO NOT CYCLE POWER DURING UPDATE H5 23 19 12 86p 6 291 456 GACCNOB4 61 R0H 0 File s 30 350 950 bytes Diris AHI Firmware Update Utility v3 04 02 Copyright C 2012 American Megatrends Inc All Rights Reserved Reading flash EES checksums Erasing Boot Block Updating Boot Block Verifying Boot Block Erasing Main Block Updating Hain Block Verifying Main Block Erasing N RAM Block Updating N YRAM Block Verifying NYRAH Block Figure 37 BIOS Update Complete 12 Once update is complete cycle power 2 5 Updating Rangeley GbE EEPROM 1 Download the latest Intel Network Connection Tools from the Intel Business Portal IBP Document 348742 Copy the EFIx64 tools to a USB flash drive Copy the Rangeley EEPROM update file to the USB flash drive File should be in test format Insert USB flash drive into RCC system Power on RCC system Pres
3. 2 SF100 connected to 16MB SPI 3 2 SF100 connected to 8MB SPI 2 SF100 CS_N 8 SF100_103 6 MOSI 4 CLK 2 GND Figure 28 Jumper for SPI Flash programming 4 Connect Dediprog to the RCC board Pay attention that pin 1 on the board lines up with the red wire on the adapter cable September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 30 of 42 D ADI Engineering The Open IP ODM ENGINEERING US PATENT 7241181 amp 696251 OO Pulsedack JCO OS5 NL 98 1207 C0C P1 CHINA Figure 29 DediProg connected to board Do DediProg 5 Start DediProg Engineering software Bau 6 The software should auto detect the flash Select W25Q64CV for the 8MB device September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 31 of 42 D ADI Engineering The Open IP ODM ENGINEERING Memory Type Ambiguity By reading the chip ID the chip applies to S2oFLO6 4k We SOL Wy Se Ww SO64By TT A5 L ei A KE dr 1 be De WA Figure 30 DediProg Flash Detection 8MB 7 Select File icon in the tool bar and select the binary file to be programmed into the flash Select Raw Binary Select OK DediProg Software 6 0 4 13 File View Help lt E ODOYe e Detect File Blank Erase Prog Verify Batch Edit Config Load Prj Save Prj Currently working on Application Memory Chip 1 Application Memory Chip
4. 34 of 42 ADI Engineering The Open IP ODM ENGINEERING Aptio Setup Utility Copyright Cl 2012 American Hegatrends Main Advanced IntelRCSetup Event Logs Securit ifm save amp Exit Save Changes and Exit Discard Changes and Exit Save Changes and Reset Discard Changes and Reset Save Options Save Changes Discard Changes Restore Defaults Save as User Defaults Select Screen Restore User Defaults Select Item Enter Select Boot Override Change Opt UEFI H amp CT 32H4SSD3 Fi General Help PO M amp CTAS2H4SSD3 F2 Previous Values EI Optimized Defaults UEFI KingstonDatalraveler 2 PMAP IF4 Save amp Exit KingstonDatalraveler 2 8PHMAP FIESC Exit Version 2 15 1236 Copyright C 2012 American Megatrends Inc Figure 35 BIOS boot Built in EFI Shell 7 USB flash drive will be identified as a fs device and labeled as a Removable HardDisk In this example the USB flash drive is fs1 Current running mode 1 1 2 HardDisk cii Ge Dag n 6x0 ZGotal Ha Bh ZHDIT HBR D 76780547 Bt xFBOQ3 Removable HardDisk Ali PeciRoot 0x0 Pcil xi ei USEL 6x6 USB 0x1 8x6 HD 1 HBR x05A795F8 Ox3F 8791701 HardDisk 1 Ge TT RTS 0x0 Sata Ox 6x0 HD 1 MER 6x 76780547 6x3F ER EUR Removable HardDisk Ali PciRoot 0x0 Pci x16 Dea E aT HH USB x1 0x0 HD 1 MBR 0x05AF9SF8 Hat Bu 791701 BlockDevice Ali GT apen ug EE 0x0 Removable BlockDevice Ali PciRoot x0
5. EE 18 1 5 12 RTE 18 1 6 CONNECTOR AND JUMPER REFERENCE scciccancantusiicnntoanaiienapamadiantineasiseamasiecatecad dance iaaiapamcannwanedetaatsandionamadseetaiensiness 20 101 PowerConnect CR RE 20 1 6 2 Fan Connecters J3 SCID veccccccsecccccceececccccceseccscceccececceeeecceccueeeccsceueeeessecueeecseeaueeecsseueeecssseuseessssaueeeeeees 20 1 6 3 USB Front Panel Connector Uli 20 164 VRI2I2C Connector d EE 21 1 6 5 Jumper 10G Enable Disable OU32l 21 L66 TPM EE 22 16 7 In Cir it SPI Connector J25 and Jumper J24 ett ege 22 Toa FPOAJTCG TONCO E EEN 23 1 6 9 RS232 UART Connector J13 PECI Connector J18 UART PECI Jumper J20 23 1 6 10 Jumper 88E1112 CONFIGS J23 E 24 1 6 11 NCSI Connector J9 Front Panel Connector J16 NCSI Jumper OTA 24 1 6 12 SMBus Connector J31 Redundant Boot Jumper J3BO cccccseeeeccecceeeeecccceeceecsccecceeceseeeeeecssseeeeees 25 DR ee Te US E EA 27 2 1 SERIES 27 2 2 RONNING I OCTO LINUX EE 27 2 3 lege 28 2 4 JPOATING BI eet EE 29 2 4 1 Updating Flash with a SPI Drogrommer 29 DAZ GA BIOS deeg 34 2 5 UPDATING RANGELEY Eege 36 2 6 UPDATNG 82599 EEPROM sereni a EEES E E 38 2 7 UPDATING MANAGEMENT FPO ee 39 Zia Updating d ER EE TEE 39 Ke UDOGUNG E ee 41 A E N EESE eee a ae cae ceed A E AE AA E eis es E AE AE A EA E 42 September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 3 of 42 ADI Engineering The Open IP ODM ENGINEERING 1 RANGELEY
6. flash image It contains a BIOS and descriptor which is used for normal operation and can be updated with new versions There is an 8MB device that is used as a failsafe SPI flash image to provide redundant boot functionality This device cannot be updated and is used only when the main device fails The redundant boot function is controlled by the FPGA and can be enabled disabled by a jumper or configuring the board management settings over the management console SPI_CLK RES Rangeley k a Avoton 8MB SPI SoC Le S Flash R SPI CS N vr p gt 3 3V AA ER A 1 8 8 8 Ea ce ee ie SE A 3 v S S S B i 16MB SPI O 12 Jp Flash A a lt a ia gt Io 3 gt TT Sp CS SELECT FPGA Figure 12 Redundant SPI FLash 1 5 9 Management FPGA The board management FPGA performs the following functions e Power Sequencing e Redundant SPI e Board Settings September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 16 of 42 ADI Engineering The Open IP ODM ENGINEERING e Analog Measurements Temperature Voltage Current e Monitors Critical Signals e Manufacturing Information The FPGA can report status and the user can change settings using the UART connected to the USB to UART bridge Refer to section 2 3 for operation details The hardware could support the following featu
7. 013 Jun 18 21 30 06 1 2013 Jun 18 21 30 06 2013 Jun 18 21 30 06 Current Type W25O64Cy Loading T projects Intel Rangeley Software BIOS AMI_RCCOACCNO04 04CCNO04_wD bin T projects Intel Rangeley Software BIOS AmMI_RCCiOACCNOO4 04CCNO04_wD bin Loaded Operation completed 0 312 seconds elapsed Erasing a whole chip 4 whole chip erased Operation completed 26 25 seconds elapsed Programming parameters Source File OACCNO04_wD bin O0x800000 bytes Target Memory Region 0 0x800000 Spare Memory Region leave as being erased Truncate File To Fit Memory Disabled Programming OK Operation completed 40 015 seconds elapsed Programming parameters Source File OACCNO04_wD bin O0x800000 bytes Target Memory Region TO 0x800000 Spare Memory Region leave as being erased Truncate File To Fit Memory Disabled Reading From Address TO Ox800000 Finished reading From memory Checksum Identical Original File checksum 0x800000 bytes CRC 32 a83e32ef Downloaded bytes checksum Ox800000 bytes CRC 32 a83e32ef Chip checksum 0 Ox800000 of total Ox800000 bytes chip size CRC 32 a83e32ef The downloaded checksum could be different From that of the original file if it s downloaded partially Operation completed 33 297 seconds elapsed v Powered DL Programmer Info Type F W Version CC Status PP Acc SPI Clock Dual Quad IO Isolation Free Memory Info Type Manufa
8. 1600MT s ECC 1 35V 18 total devices e Channel B Is a SODIMM Supported SODIMM is a 4GB Dual Rank 1600MT s ECC 1 35V A requirement of the SOC is that channel B must be equal to channel A for density rank speed ECC and type i e UDIMM SODIMM etc The BIOS gets this information by reading and comparing the SPD EEPROMs for each channel A SPD EEPROM was placed on the board for channel A Channel A was routed as a UDIMM to simplify the layout so the starting SPD was based on Micron MT18KSF51272AZ 1G6 That SPD was then modified to change the type byte 0x3 in SPD EEPROM from a UDIMM 0x2 to a 72b SO UDIMM 0x8 The CRC for the SPD was then recalculated The RCC system ships with 8GB of memory The board could support up to 16GB of memory by changing the memory down devices SPD and SODIMM September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 14 of 42 ADI Engineering The Open IP ODM ENGINEERING 1 5 3 82599ES Dual 10G Controller The 10Gb Ethernet controller is connected to the SOC with a PCle x8 Gen2 interface It provides access to two SFP slots There is a configuration EEPROM 32KB which configures the device for SFI with no management There is also an optional flash device currently no used that could hold an option ROM for PXE boot This device and its surrounding circuits can be completely powered down by setting a jumper on the board or configuring the boar
9. 2 Update Stand Alone Project 4 Currently working region Region 1 Region 2 Region 3 Region 4 Region 5 i 2013 Jun 18 21 17 51 Welcome to DediProg 6 0 4 13 i 2013 Jun 18 21 17 51 Start logging 4 2013 Jun 18 21 17 51 Checking USB connection Powered b H sw 2013 Jun 18 21 17 51 USB OK Programmer Info Load File KA SE SM 5 1 9 File Path T projects Intel Rangeley Software BIOS AMI_RCC OACCNOO4 0A v g Se Not Applicable 4 2013 Jun 18 21 17 51 0 4695 elapsed t i 2013 Jun 18 21 19 20 Current Type Program as 3 MHz Single IO Data Format RawBinary O Intel Hex Motorola 519 ORM ZE C Truncate file to Fit in the target area W25Q64C Winbond Electronics Corp 8192 OxeF4017 File Info Name Size Checksum File size Checksum Chip size CRC32 Checksumi file size CRC32 Checksum chip size Batch Config setting gt Full Chip update Partial Update and i 4 b No operation on going Ed Figure 31 Loading Dediprog SPI File September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 32 of 42 ADI Engineering The Open IP ODM ENGINEERING 8 Select Erase icon in the tool bar to erase flash contents File View Help e e OPUF 0D amp Detect File Blank Frase Prog Verify Patch Edit Config Load Prj Save Pry Figure 32 DediProg Erase Flash 9 Select Prog icon in the tool bar to write file to flash e OFV D D ei SS i
10. 3 If not change boot option 1 to mSATA 7 Goto Save amp Exit and select Save Changes and Exit System should boot Yocto Linux Type root when at command prompt There is no password 2 3 Management Console The RCC board has a management console which is connected to the on board FPGA over the USB to UART bridge The initial version of this management console provides board status information to the user This console is still under development and will provide the following features in the future e User configurable settings for on board jumpers i e Redundant SPI 10G Power etc e FPGA update over UART e Additional board status i e Information from Rangeley PECI Manufacturing Information More advanced features that are under consideration e BMC IPMI Support e Serial OverLAN e FAN Monitoring and Control Instructions to access management console 1 Follow instructions in section 2 1 for connecting to serial port Management console is the first UART Power on RCC system You should see management console displayed September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 28 of 42 ADI Engineering The Open IP ODM ENGINEERING ADI ENGINEERING RANGELEY MANAGEMENT CONSOLE VERSION 1 00 SETTINGS TEMP1 627 070 12A_I 01880m 12A_I V Hun V PJA 63911m H SP3 O3914m CPU_TERR_N 1 YOH Bob32m 9754 1 YNN HIH am 3 1 TEMP2 034 09C PROCHOT_N 1
11. COMMUNICATIONS COLLATERAL REFERENCE DESIGN PLATFORM DESCRIPTION 1 1 Overview The Rangeley Communications Collateral RCC platform is based on the Intel Rangeley SOC Rangeley is a multi core up to 8 Intel Atom based SOC product featuring high levels of I O integration and an Intel QuickAssist hardware acceleration engine Rangeley is targeted for the routers and security communications market segment This platform will demonstrate Rangeley in an embedded lower power and small form factor solution The RCC block diagram is shown in Figure 1 SATA USB Connector Type A x2 SATA SATA Connector Connector USB eSATA mSATA Header x2 Drive 2 x2 4 4 RJ45 w 1347 AT4 Mag QUAD WW e 72 CH A 4GB Memory Down Dual Rank x8 w ECC P 88E1112 Mag 1G SFP SC 82599ES 10 GbE Dual PECI HEADER Mini B UART to USB USB Bridge CH B SODIMM dual rank support x8 PCle Slot uServer nie Se GE FPGA TPM BMC 12V Fash Power 8 MB Regulators Flash 8 MB Figure 1 RCC Block Diagram September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 4 of 42 ADI Engineering The Open IP ODM ENGINEERING 1 2 Feature Summary Feature Description Board Form Factor 12 layer Mini ITX 6 7 X 6 7 Supports all SKU s of Rangeley and Avoton CPU Memory e Dual Channel e Channel A Memory Down 4GB DDR3L 1600 Dual Rank with ECC Channel B SODIMM with ECC 1DPC Du
12. Confidential page 23 of 42 ADI Engineering The Open IP ODM ENGINEERING J18 PECI 3 PECI CLK 2 GND 1 PECI DATA J13 RS232 UART J20 PECI R5232 UART MUX JUMPER 3 RS232_TXD 3 GND 1 2 SOC connected to UART2 2 GND a PECI SEL N 2 3 SOC connected to PECI 1 RS232_RXD 1 NG Figure 23 Connector RS232 J13 PECI J18 Jumper PECI RS232 J20 1 6 10 Jumper 88E1112 CONFIG3 J23 1 PHY 1G STATUS ee ee iran E 1 2 TWSI is 12C 2 PHY_1G_CONFIG3 AS 3 2 TWSI is MDC MDIO 3 GND Figure 24 Jumper 88E1112 TWSI Configuration J23 1 6 11 NCSI Connector J9 Front Panel Connector J16 NCSI Jumper J14 September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 24 of 42 ADI Engineering The Open IP ODM ENGINEERING J14 NCSI MDIO MUX JUMPER 1 2 SOC connected to MDIO MDC 2 3 SOC connected to NCSI 2 NCSI_SEL_N 3 GND NCSI HEADER J9 dl A Front Panel Connector J16 10 GND 9 NCSI_ARB OUT p Ze Dy 1 V3P3A 2 GND 8 GPIO_CPU_SUS1 7 GBE_CPU_SPDO_1 ed a 3 Power Button 4 GND 6 GBE_CPU_WOL 5 SMB_GBE CPU_ALERT_N ER KI 5 Reset Button 6 GND 4 NCSI_TXD1 3 SMB_GBE_CPU_CLK oe 7 PWR LED Cathode 8 PWR LED Anode 2 NCSI_TXDO 1 SMB_GBE_CPU_DATA lt 9 HDDLEDCathode 10 HDD LED Anode Figure 25 Connector NCSI Header J9 Front Panel J16 Jumper NCSI MDIO J14 Schematic Signal NCSI Function NCSI Pi
13. Config Load Frj Save Frj Detect File Blank Erase Prog Verify Bath Edit Figure 33 DediProg Program Flash 10 Select Verify icon in the tool bar to compare flash contents with binary file Verify that tool reports Checksum Identical September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 33 of 42 DI ENGINEERING File view Help ADI Engineering The Open IP ODM DediProg Software 6 0 4 13 Detect File Currently working on Currently working region 4 ZE Blank Erase C Verify TERR Prog Batch Edit Config Load Prj Save Prj Application Memory Chip 1 Application Memory Chip 2 Region 1 Region Region 3 Region 4 i 2013 Jun 18 21 19 20 i 2013 Jun 18 21 24 45 w 2013 Jun 18 21 24 45 1 2013 Jun 18 21 24 45 1 2013 Jun 18 21 24 45 i 2013 Jun 18 21 24 50 i 2013 Jun 18 21 25 17 2013 Jun 18 21 25 17 1 2013 Jun 18 21 25 17 i 2013 Jun 18 21 27 32 i 2013 Jun 18 21 27 32 i 2013 Jun 18 21 27 32 i 2013 Jun 18 21 27 32 i 2013 Jun 18 21 27 32 wi 2013 Jun 18 21 28 12 1 2013 Jun 18 21 28 12 11 2013 Jun 18 21 28 12 i 2013 Jun 18 21 29 32 i 2013 Jun 18 21 29 32 i 2013 Jun 18 21 29 32 i 2013 Jun 18 21 29 32 i 2013 Jun 18 21 29 32 i 2013 Jun 18 21 29 32 i 2013 Jun 18 21 30 06 bg 2013 Jun 18 21 30 06 i 2013 Jun 18 21 30 06 i 2013 Jun 18 21 30 06 i 2013 Jun 18 21 30 06 i 2
14. NICs should be selected in the update command Below is an example of the update command 13 Wait for command to complete and verify it reports successful DO NOT CYCLE POWER DURING UPDATE 2 6 Updating 82599 EEPROM 1 Follow steps 1 through 11 for updating Rangeley EEPROM 2 82599 ports are identified by Vendor Device 8086 10FB To update the 82599 EEPROM one of its NICs should be selected in the update command Below is an example of the update command 3 Wait for command to complete and verify it reports successful DO NOT CYCLE POWER DURING UPDATE September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 38 of 42 ADI Engineering The Open IP ODM ENGINEERING 2 7 Updating Management FPGA 2 7 1 Updating FPGA over JTAG The Management FPGA can be updated over JTAG The tools required to update the FPGA over JTAG are below e Microsemi FlashPro4 programmer http www microsemi com fpga soc design resources programming flashpro overview e Host computer with Windows OS and FlashPro software installed http www microsemi com fpga soc design resources programming flashpro downloads e FPGA bitfile Provided from Intel and ADI in the form of stp file Instructions 1 Turn off power to RCC system 2 Remove enclosure cover Held on by two screws 3 Connect FlashPro4 adapter to RCC system Figure 41 Connect FlashPro4 Cable 4 Turnon power to RCC system September 3
15. Ox 6x0 HD 1 MER 6x 76780547 6x3F ER EUR Removable HardDisk Ali PciRoot 0x0 Pci x16 Dea E aT HH USB x1 0x0 HD 1 MBR 0x05AF9SF8 Hat Bu 791701 BlockDevice Ali GT apen ug EE 0x0 Removable BlockDevice Ali PciRoot x0 Pci x16 8x0 USB Ox 0x0 USB Gx1 6x8 Press ESC in 3 seconds to skip any other key to continue Figure 39 Indentify USB flash drive in EFI shell 9 Goto USB flash drive by typing fs1 followed by ENTER September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 37 of 42 ADI Engineering The Open IP ODM ENGINEERING 10 Go to the folder with the eeupdate64e efi update utility and EEPROM text file 11 Type eeupdate64e efi followed by ENTER Using Intel R PRO Network Connections SDK v2 21 1 FEUPDATE v5 21 61 03 Copyright C 1995 2013 by Intel R Corporation Intel R Confidential and not for general distribution Warning No Adapter Selected NIC Bus Dev Fun Yendor Deyvice Branding string 8H86 LBFB Intel R 82599 10 Gigabit Dual Port Network Conn 8686 16FB Intel R 82599 10 Gigabit ee pori Network Conn 8H86 1F 41 Intel R SH86 LF4l Intel R Ethernet Connection SH86 1F41 Intel R Ethernet Connection SH86 LF4l Intel R Ethernet Connection Ethernet Connection Figure 40 eeupdate64e efi Adapter Identification 12 Rangeley ports are identified by Vendor Device 8086 1F41 To update the Rangeley EEPROM one of its
16. The Open IP ODM ENGINEERING Intel Rangeley Communications Collateral RCC Reference Design Platform User Manual Revision 1 00 ADI Engineering Inc 1758 Worth Park Charlottesville VA 22911 www adiengineering com Phone 434 978 2888 Fax 434 978 1803 ADI Engineering The Open IP ODM ENGINEERING Revision History Date Remarks 06 12 2013 Initial Draft 06 24 2013 Initial feedback updates 06 26 2013 Remove optional wording for battery 07 12 2013 Change temperature specification for A step silicon 09 03 2013 Official release September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 2 of 42 ADI Engineering The Open IP ODM ENGINEERING Table of Contents 1 RANGELEY COMMUNICATIONS COLLATERAL REFERENCE DESIGN PLATFORM DESCRIPTION ccscceeees 4 1 1 eee tiec eae gerc ses pace E rut mecsese pia cuecious oka AE EE A E AE A 1 2 FEATURE OIA EE E 5 1 3 BC CURE Fete Ia i ae EE E E E TEE ETE geo ne nates eae ene see ante ees 7 1 4 COMPONENT LAYOUT REFERENCE genee 11 1 5 SEENEN Eege 14 LSA Rangeley e 14 ee VIO EE 14 1 5 3 G2Z599ES Dual 10G Controller sissinsissnsansavioassaerroaartessndansaneneontsanssenessanciadaesadeavebsoasevaceesunedboonta esiaadeeseate 15 1 5 4 1347 AT4 Q ad GBE Oe A EEN 15 D550 GEFILII Single GBE PAY EE 15 15 6 CP2105 Dual USB 10 UART Bridge EEN 15 E OO E 16 158 E ee Re RE 16 i is Mandden en E 16 1 5 10 EEN 17 1 5 11
17. V12A 11760mY THERMTRIP_N 1 VDDO 81358mY PORTO xaa VIPO O100OmY YCCP 01102m SP3_106 83306m Figure 26 FPGA Management Console 4 Youcan navigate console with arrow keys and select or toggle an item with the ENTER key 2 4 Updating BIOS 2 4 1 Updating Flash with a SPI Programmer Both the 16MB and 8MB SPI flash devices can be updated using an external programmer The tools required to update the flash devices are below e Dediprog SF100 http www dediprog com SPI flash in circuit programming SF100 e 1 27mm Cable Adapter http www dediprog com SPI flash in circuit programming ISP Cable Adaptor e Host computer with Windows OS and Dediprog software installed Dediprog software is located at http www dediprog com SPI flash in circuit programming SF100 under Software Download tab e SPI Flash binary with descriptor and BIOS Available from Intel and ADI September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 29 of 42 ADI Engineering The Open IP ODM ENGINEERING Figure 27 DediProg SF100 with 1 27mm Adapter Instructions for updating SPI Flash 1 Turn off power to RCC system No external power is required for updating SPI flash Remove enclosure cover Held on by two screws 3 Set the jumper J24 to the SPI flash you want accessible to the external programmer This example starts with the 8MB device 1 16MB CS_N Jumper Settings 1
18. al Rank Clocking IDT 9VRS4420 for Atom based microservers IDT 9ZXL0651 for PCle clock distribution Hard Drive Local mSATA Gen3 port Two eSATA Gen2 ports One internal SATA Gen3 port Two internal SATA Gen2 ports BIOS Redundant SPI Boot Flash 16MB for main device 8MB for failsafe device USB Two back panel USB 2 0 ports Two front panel USB 2 0 ports through cable SOC UART One console port to CPU through a mini USB to UART bridge Silicon Labs CP2105 Optional RS232 UART through motherboard header LAN support Four 10 100 1000Base TX Ethernet Ports o Three per Intel 1347 AT4 quad PHY Controller o One per Marvell 88E1112 PHY Two 1G 10G SFP Ports per Intel 82599ES controller One 100 1G SFP per Marvell 88E1112 PHY Debug Interface e XDP 60 pin debug interface Expansion Ports e One PCle x8 Gen2 Slot e TPM Header e Coin cell battery CR2032 for RTC On Board Management e SmartFusion FPGA Power Sequencing Accessible through 2 UART on CP2105 Board Option Setting Redundant SPI 10G Power etc September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 5 of 42 ADI Engineering The Open IP ODM ENGINEERING Enclosure Power Supply Monitor Critical Signals PORT80 Display Fan Management Future feature BMC IPMI Support Future feature 8 9 X 3 5 X 8 3 Steel Enclosure with Aluminum bezel Power and Reset Buttons Power and HDD LED s Support for one PC
19. ate File Edit view Tools Programmers Ose 2 tion Customize Help 4 oc pa ER Open Project Jee Configure Device View Programmers e NI Programmer 1 mmm Refresh Rescan for Programmers programmer 75884 Erase programmer 75884 Completed erase programmer 75864 Programming FPGA Array programmer 75884 Verifying FPGA Array programmer 75884 Verifying FPGA Array pass programmer 75884 Program System Init and Boot Clients programmer 75864 Program Embedded Flash Memory Module ALL programmer 75884 Verify System Init and Boot Clients programmer 75864 Verify Embedded Flash Memory Module ALL programmer 75884 Finished Tue Jun 18 22 45 41 2013 Elapsed time 00 00 40 programmer 75864 Executing action PROGRAM PASSED 1 x Programmer List window H ee gef e Ets 6 All A Errors A Warnings A Info Programmer Cerl ShiFk 4 Cbrl ShiFE L Ctrl Shirt P Chrl ShiFk D Ctrl Shift H DOD i a gt Lo ml Port DS Programmer Enabled usb75884 USB 2 0 RH HI Ready T projects Intel Rangeley FPGA release 20130521 INTEL_RCC_FPGA_X100_20130521 stp SINGLE Figure 45 FlashPro FPGA Update Complete 11 Disconnect FlashPro4 programmer 12 Power cycle RCC system 2 7 2 Updating FPGA over console This is a future feature not currently s
20. ct Size KB Manu ID JEDEC ID File Info Name Size Checksum File size Checksum Chip size CRC32 Checksum ffile size SF100 5 1 9 3 54 ON Not Applicable 3 MHz Single 10 Disable W25Q064C Winbond Electronics Corp 6192 Oxef OxeF4017 O0ACCNOO4_wD bin 0x800000 Ox70907BE0 Ox70907BE0 OxA83E32EF CRC32 Checksum chip size 0xA83E32EF Batch Config setting Full Chip update Partial Update and No operation on going Le Figure 34 DediProg Verify 11 If updating the 16MB device set jumper J24 to 16MB and repeat steps The device selected should be N25Q128A13 12 2 4 2 Disconnect DediProg from RCC board Updating BIOS from EFI Shell 1 Download AMI BIOS update utility a E E Under o po 0 o Go to htt Select Technical Support ami com support AMIBIOS select Aptio then SUBMIT download utility 2 Place this utility on a USB flash drive along with the BIOS binary NOTE BIOS binary will be smaller than the 8MB or 16MB images and does not have descriptor September 3 2013 Insert USB flash drive into RCC system Power on RCC system Intel Rangeley Reference Platform User Manual 45700 0004 Confidential Press ESC when requested by the BIOS to enter the BIOS setup screen Go to Save amp Exit and under Boot Override select UEFI Built in EFI Shell Select AMIBIOS amp Aptio AMI Firmware Update Utility and follow instructions to page
21. d management setting over the management console 1 5 4 347 AT4 Quad GBE PHY The SOC is connected to the Intel 1347 AT4 quad PHY over SGMIl It configures the PHY using a MDC MDIO interface Three of the SOC MAC interfaces are connected to this PHY e SGMII O e SGMII 2 e SGMII 3 The PHY is then connected to an RJ45 with integrated magnetics SoC Port 0 ER SoC Port 3 Figure 11 SoC Ethernet port mapping 1 5 5 88E1112 Single GBE PHY The SOC is connected to the Marvell 88E1112 over SGMII 1 It configures the PHY using a MDC MDIO interface This PHY is connected to an RJ45 with integrated magnetics and to an SFP slot It supports Auto Media Detection between the two interfaces 1 5 6 CP2105 Dual USB to UART Bridge The RCC board has a CP2105 which is a dual USB to UART bridge One UART is connected to the console port on the SOC and the second UART is connected to the management FPGA SW Driver is still under development to support Auto Media Detection feature September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 15 of 42 ADI Engineering The Open IP ODM ENGINEERING 1 5 7 SOC EEPROM The SOC uses an EEPROM to configure the Ethernet MAC interfaces Please refer to Intel representative for the latest EEPROM image for the RCC board 1 5 8 SOC SPI Flash Devices There are two SPI Flash devices connected to the SOC There is 16MB device which is used for the main SPI
22. le Card Support for two 2 5 HDD One 80mm fan Flex ATX Power Supply Internal to Enclosure 220W Max 100 240 VAC 50 60Hz 5 3 Amp Temperature is 20 C to 35 C ambient outside enclosure t RCC system operating range for the Alpha silicon stepping should be within 20 C to 35 C during normal operation The operating temperature for future stepping s is predicted to increase to meet NEBS level 3 qualification September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 6 of 42 ADI Engineering The Open IP ODM ENGINEERING 1 3 Enclosure Reference POWER BUTTON Controls ATX Supply POWER LED BLUE LATCHING SYSTEM RESET HDD LED BUTTON RED Figure 2 Enclosure Front Panel September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 7 of 42 ADI Engineering The Open IP ODM ENGINEERING AC Input 90 264V PCle Expansion Slot Yellow 1G Green 100M Green Link OFF 10M Blink Activity Green 10G Dual 10G 1G SFP eSATA 3Gb 1G 100 SFP Green Link Blink Activity Dual USB 2 0 Quad 1G 100 10 Console USB to Dual UART Figure 3 Enclosure Back Panel September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 8 of 42 D ADI Engineering The Open IP ODM ENGINEERING Figure 4 Inside Enclosure September 3 2013 Intel Rangeley Reference Platfo
23. m console to the host computer Verify that host computer can see two additional serial ports The first serial port added to the host computer will connect to the FPGA management console The second serial port will connect to the CPU console The user will need to use a terminal emulator i e Hyperterminal PuTTy to connect to the consoles The settings for the terminal should be the following Speed 115 200 Data Bits 8 Parity None Stop Bits 1 Flow Control None Preferred emulation mode is ANSI 2 2 Running Yocto Linux The RCC system comes with a mSATA drive with a custom Yocto Linux installation and is ready to use out of the box For instructions on how to create Yocto Linux with Rangeley patches and drivers please refer to Intel documentation 1 Connect User Interface Two options a CPU console port over USB to UART bridge b Graphics Card in PCle slot USB Keyboard Connect AC power cable Press power button on front panel If using the CPU console port debug messages should be displayed as the BIOS boots IF using a graphics card nothing will be displayed until the BIOS splash screen Press ESC when requested by the BIOS to enter the BIOS setup screen September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 27 of 42 ADI Engineering The Open IP ODM ENGINEERING 6 Goto Boot menu and verify that Boot Option 1 is set to boot MSATA i e UEFI M4 CT032M4SSD
24. n Direction SMB _ GBE CPU DATA SMB GBE CPU CLK SMB GBE CPU ALERT N GBE CPU SDPO 1 NCSI_TXD1 NCSI_TXD1 GPIO_CPU_SUS1 NCSI_RXDO GBE_CPU_WOL NCSI_RXD1 NCSI_ARB_OUT NCSI_ARB_OUT Table 1 NCSI Connector 1 6 12 SMBus Connector J31 Redundant Boot Jumper J30 September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 25 of 42 ADI Engineering The Open IP ODM ENGINEERING J30 Redundant Boot Enable 1 2 Enable 2 3 Disable 1 SMB_3V3A_HOST_CLK Va 1 NG 2 GND Lag 2 REDUNDANT_BOOT 3 SMB_3V3A_HOST_DATA WRU 3 GND Table 2 Connector Main SMB J31 Jumper Redundant Boot J30 September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 26 of 42 ADI Engineering The Open IP ODM ENGINEERING 2 RCCSETUP AND USE 2 1 Serial Port Drivers The RCC has a USB to UART bridge for the CPU console and FPGA management console The device used is a Silicon Labs CP2105 Before connecting the RCC system the host computer will need to install drivers for the CP2105 Follow these instructions 1 Set a EE Go to the following address http www silabs com products interface usbtouart Pages usb to uart bridge aspx Select Tools tab Select drivers for your OS For Windows select CP210x_VCP_Windows zip Download and following instructions for installing driver Use the provided USB Mini B cable and connect the RCC syste
25. nal Connectors September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 12 of 42 ADI Engineering The Open IP ODM FDI ENGINEERING Front Panel Jumper J14 Controls Mux for NCSI PECI l f l l ETICO CEOTTO Jumper J20 Controls Mux for PECI and 2 UART Jumper J23 88E1112 12C for 88E1112 Config3 Setting EEPROM Figure 8 Component Layout Internal Connectors cont EEN iy Brin Tie On 16MB topside P Jet ci v iP a Off 8MB bottomside LEJI S en wm em a z Ra EEE Figure 9 Component Layout Port80 and Debug LEDs September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 13 of 42 ADI Engineering The Open IP ODM ENGINEERING 1G 100 10 To 1347 AT4 1G 100 10 To 88E1112 1G 100 SFP ole 1G 100 10 To 1347 AT4 To 88E1112 Cons 10G SFP USB 2 0 Dual UART Figure 10 Front Panel Connectors 1 5 Component Overview 1 5 1 Rangeley SOC The RCC system ships with the highest core count SKU of the Rangeley SoC Please refer to the latest Intel documentation on the SoC for the SKU features The RCC system has been designed to be compatible with all other Rangeley SKUs as well inclusive of lower core count SKUs 1 5 2 Memory The RCC supports two channels of DDR3 These channels are configured as follows e Channel A Is memory down soldered to board configured as 4GB Dual Rank
26. nnector J4 Figure 18 Connector VR12 12C J4 1 6 5 Jumper 10G Enable Disable J32 September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 21 of 42 ADI Engineering The Open IP ODM ENGINEERING Jumper Settings R 1 2 10G Disabled 2 106 _DISABLE Sia 3 2 10G Enabled 1 NC 3 GND Figure 19 Jumper 10G Enable Disable J32 1 6 6 TPM Connector J11 20 Pull Up 18 NC 16 SERIRQ 14 NC 12 GND 19 NC 17 GND 15 3 3V 13 NC 11 LPC_LADO SEET 7 LPC_LAD3 5 LPC_RST_N 10 LPC_LAD1 8 LPC_LAD2 6 NC 4 Keyed Pin 2 GND ILR 3 LPC_FRAME 1 LPC_CLK Figure 20 Connector TPM J11 1 6 7 In Circuit SPI Connector J25 and Jumper J24 September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 22 of 42 ADI Engineering The Open IP ODM ENGINEERING 1 16MB CS N Jumper Settings 1 2 SF100 connected to 16MB SPI 3 2 SF100 connected to 8MB SPI 2 SF100 CS_N z Ka O ei m 8 SF100_103 6 MOSI 4 CLK 2 GND Figure 21 Connector SPI J25 Jumper SPI J24 1 6 8 FPGA JTAG Connector J22 2 GND 4 JTAGSEL 6 3 3V 8 TRST_N 10 GND Figure 22 Connector FPGA JTAG J22 1 6 9 RS232 UART Connector J13 PECI Connector J18 UART PECI Jumper J20 September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004
27. ort site Support Phone amp Email Support during warranty and support period 1 business day response Up to 40 hours of support problem solving and hardware software engineering assistance during the support period Hourly Support e Up to 8 hours of support problem solving and engineering assistance over 1 year HSP 008 Packages e Up to 16 hours of support problem solving and engineering assistance over 1 year HSP 016 e Up to 40 hours of support problem solving and engineering assistance over 1 year HSP 040 e Up to 100 hours of support problem solving and engineering assistance over 1 year HSP 100 e Up to 400 hours of support problem solving and engineering assistance over 1 year HSP 400 e Up to 1000 hours of support problem solving and engineering assistance over 1 year HSP 1000 Table 3 ADI Support Plans For questions related to the Intel SoC silicon please contact your Intel representative September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 42 of 42
28. res with a firmware upgrade e BMC IPMI Support e Serial Over LAN e FAN Monitoring and Control e Remote FPGA updates 1 5 10 PCIe Slot The RCC board has a PCle x8 expansion card The chassis supports a full height half length PCle x16 card The board is designed to support up to a 75W card A x8 to x16 riser card is supplied with the kit to mount the card in the enclosure Thermal testing has only been completed with a 15W card September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 17 of 42 ADI Engineering The Open IP ODM ENGINEERING The RCC board contains a standard CR2032 coin cell battery to support the RTC The RCC board has 2x7 connector for a TPM module D ADI Engineering The Open IP ODM ENGINEERING t ki Il San Figure 14 TPM Module September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 19 of 42 ADI Engineering The Open IP ODM ENGINEERING 1 6 Connector and Jumper Reference 1 6 1 Power Connector J1 Figure 15 Connector Power J1 1 6 2 Fan Connecters J3 amp J2 Figure 16 Connector Fan J3 amp J2 1 6 3 USB Front Panel Connector J7 September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 20 of 42 ADI Engineering The Open IP ODM ENGINEERING Figure 17 Connector USB Front Panel J7 1 6 4 VR12 I2C Co
29. rm User Manual 45700 0004 Confidential page 9 of 42 D ADI Engineering The Open IP ODM ENGINEERING e 2 e rm ge bd AF 7 S668 Ww CE sy sivecta reese er iO s OG 3 l S i tr me pass sia SHEI Figure 5 Enclosure Cover HDD Mount HDD not provided with kit September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 10 of 42 D ADI Engineering The Open IP ODM ENGINEERING 1 4 Component Layout Reference DDR3 RANK1 RANKO on Back iov ei rekt HE 20 ETS Ca AA K E K Ze 7 Zi An Ce UI ei zk RR KR rb ae hij j 4 q aaj t Jel a a Ad ae nggftrtrtiggn mr A af d DU NM y ri mt H wm en io amp hey i ap a i WELL 0 O IL S o ss LC 88E1112 PHY 1347 AT4 PHY Figure 6 Component Layout Major ICs September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 11 of 42 ADI Engineering The Open IP ODM DI ENGINEERING SODIMM With ECC 12V Input Bottom Connector Only Top will not be used t at ef 7 7 H e i e Al ie H 8 KKK v m it ane R 2 ep R CR CR Li Jumper J24 to Select SPI Device for Programming a e Dediprog Connector Programming SP gt L Jumper J29 Enable I2C MDC to SFP Figure 7 Component Layout Inter
30. s ESC when requested by the BIOS to enter the BIOS setup screen Go to Save amp Exit and under Boot Override select UEFI Built in EFI Shell E AE EE e September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 36 of 42 ADI Engineering The Open IP ODM ENGINEERING Aptio Setup Utility Copyright Cl 2012 American Hegatrends Main Advanced IntelRCSetup Event Logs Securit ifm save amp Exit Save Changes and Exit Discard Changes and Exit Save Changes and Reset Discard Changes and Reset Save Options Save Changes Discard Changes Restore Defaults Save as User Defaults Select Screen Restore User Defaults Select Item Enter Select Boot Override Change Opt UEFI H amp CT 32H4SSD3 Fi General Help PO M amp CTAS2H4SSD3 F2 Previous Values EI Optimized Defaults UEFI KingstonDatalraveler 2 PMAP IF4 Save amp Exit KingstonDatalraveler 2 8PHMAP FIESC Exit Version 2 15 1236 Copyright C 2012 American Megatrends Inc Figure 38 BIOS boot Built in EFI Shell 8 USB flash drive will be identified as an fs device and labeled as a Removable HardDisk In this example the USB flash drive is fs1 Current running mode 1 1 2 HardDisk cii Ge Dag n 6x0 ZGotal Ha Bh ZHDIT HBR D 76780547 Bt xFBOQ3 Removable HardDisk Ali PeciRoot 0x0 Pcil xi ei USEL 6x6 USB 0x1 8x6 HD 1 HBR x05A795F8 Ox3F 8791701 HardDisk 1 Ge TT RTS 0x0 Sata
31. upported September 3 2013 Intel Rangeley Reference Platform User Manual 45700 0004 Confidential page 41 of 42 D ADI Engineering The Open IP ODM ENGINEERING 3 SUPPORT Support related to the RCC system i e Hardware BIOS Firmware etc will be provided by ADI Engineering Each kit comes with a standard support package which includes free technical support up to 3 hours from the engineering team and unlimited access to ADI s web based support forums and download site Some customers may need extra support to handle hardware or software development tasks such as system level design issues when integrating an ADI product into a larger system thermal regulatory mechanical etc software porting debug or testing efforts or design customization Customers may also require design review or consulting services to quickly ramp up their engineering and manufacturing teams For these customers ADI offers a variety of support packages to meet their specific requirements Support Package Key Features ADI Part Number Standard 90 day standard kit warranty DKSS Development Kit Unlimited access to ADI s web based support site Support Phone amp Email Support during warranty and support period 3 business day response Up to 3 hours of support problem solving during the support period Premium Extends product warranty and support period to 1 year DKPS 040 Development Kit Unlimited access to ADI s web based supp

RCC User Manual - ADI Engineering

Contents

Download Pdf Manuals

Related Search

Related Contents