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Hynix HMS9xC7132, HMS9xC7134 User`s Manual

1. Mnemonic Description Bytes Cycles Hex Code MOV direct Ri move indirect RAM to direct byte 2 2 86 87 MOV direct data move immediate data to direct byte 3 2 75 MOV Ri A move A to indirect RAM 1 1 F6 F7 MOV Ri direct move direct byte to indirect RAM 2 2 A6 A7 Qhi data move immediate data to indirect RAM 2 1 76 77 MOV DPTR data16 load data pointer with a 16 bit constant 3 2 90 MOVC A QA DPTR move code byte relative to DPTR to A 1 2 93 MOVC A A C move code byte relative to PC to A 1 2 83 Ri move external RAM 8 bit address to 1 2 E2 E3 MOVX A DPTR_ move external RAM 16 bit address to 1 2 EO MOVX Ri A move A to external RAM 8 bit address 1 2 F2 F3 MOVX DPTR A_ move Ato external RAM 16 bit address 1 2 FO PUSH direct push direct byte onto stack 2 2 CO POP direct pop direct byte from stack 2 2 DO XCH A Rn exchange register with A 1 1 Cx XCH A direct exchange direct byte with A 2 4 C5 XCH A ORi exchange indirect RAM with A 1 1 C6 C7 XCHD Ri exchange LOW order digit indirect RAM with A 1 1 D6 D7 Boolean variable manipulation Mnemonic Description Bytes Cycles Hex Code CLR C clear carry flag 1 1 C3 CLR bit clear direct bit 2 1 C2 SETB C set carry flag 1 1 D3 SETB bit set direct bit 2 1 D2 CPL C complement carry flag 1 1 B3 CPL bit complement direct bit 2 1 B2 ANL bit AND direct bit to carry flag 2 1
2. 8112 8309 CCL IL 01 80q qo A 514 201 14 8 N 04 SIO UWI J 1218024 19 91 2224 1 VIVIX SSA TIOS was ISSA 100 OLNI 3109 6508 May 2001 ver1 1 hynix 3 PIN ASSIGNMENT 3 1 40PDIP pinning 40DIP Top View Open drain option Open drain type pin 40DIP Top View Open drain option Open drain type pin May 2001 ver1 1 PWMO P2 2 4 gt DPWMO P2 1 4 DPWMO P2 0 lt gt RESET Vppi gt Vss gt XTAL2 XTAL1 gt SDA2 P1 7 gt SCL2 P1 6 P0 7 4 P0 6 4 P0 5 gt P0 4 4 INTO VPP P0 3 P0 2 4 P0 1 lt gt P0 0 4 1 5 PWMO P2 2 4 gt DPWMO P2 1 lt gt DPWMO 2 0 lt gt RESET Vpp1 Vss gt XTAL2 XTAL1 SDA2 P1 7 gt SCL2 P1 6 4 P0 7 4 P0 6 4 P0 5 P0 4 gt INTO VPP P0 3 P0 2 gt P0 1 lt gt P0 0 4 1 5 4
3. Nd 1 40 2 39 3 38 4 37 5 36 6 35 7 T 34 8 2 33 9 o 32 10 31 11 5 30 12 1 29 13 28 14 e 27 15 26 16 25 17 24 18 23 19 22 20 21 ee 1 40 2 39 3 38 4 37 5 36 6 35 7 I 34 8 33 9 o 32 10 31 11 5 30 12 51 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 HAUT SLICE PE HMS9xC7132 HMS9xC7134 Vsync IN Hsync IN PWM1 P2 3 PWM P2 4 PWM3 P2 5 PWM4 P2 6 PWM5 P2 7 Hsync OUT P3 2 Vsync OUT P3 3 PWM6 INT1 P3 4 CLAMP PWM P3 5 PADOUT P3 6 SOG P3 7 Vpp2 Vss2 SCL1 P1 0 SDA1 P1 1 ACHO P1 2 ACH P1 3 ACH P1 4 Vsync IN Hsync IN PWM1 P2 3 PWM P2 4 PWM3 P2 5 PWM4 P2 6 PWM5 2 7 Hsync OUT P3 2 Vsync OUT P3 3 PWM6 INT1 P3 4 CLAMP PWM P3 5 PADOUT P3 6 SOG P3 7 P3 0 P3 1 SCL1 P1 0 SDA1 P1 1 ACHO P1 2 ACH P1 3 ACH P1 4 HMS9xC7132 HMS9xC7134 3 2 42SDIP pinning 42SDIP Top View Open drain option Open drain type pin 42SDIP Top View Open drain option Open drain type pin PWMO P2 2 DPWMO P2 1 DPWMO P2 0 gt 1 4 P3 0 Vppi gt Vss XTAL2 4 XTAL
4. Specifications Parameter Symbol Condition Unit Min Max Supply Voltage 12 2 4 5 5 5 V Operating Frequency Vpp 4 5 5 5V 10 16 MHz Operating Temperature Topr 0 70 7 3 DC Electrical Characteristics 0 70 C Vpp 4 5 5 5V Vgg 0V Specifications Symbol Parameter Condition Unit Min Typ Max SUPPLY VDD power supply voltage 4 5 5 0 5 5 V IDD power supply current Fosc 12MHz TBD mA VLVR low voltage reset 3 3 3 7 4 1 V OTP SUPPLY VDD power supply voltage 4 5 5 0 5 5 V VPP programming voltage 12 75 V IDDP power supply current Fosc AMHz TBD mA IPP programming current Fosc 2 TBD mA RESET IRST RESET input pull up resistance VIN OV 33 HA input leakage current VIN VDD 0 1 VIL1 LOW level input voltage VSS 0 5 0 3VDD V VIH1 HIGH level input voltage 0 7VDD VDD 0 5 V XTAL VOP open bias voltage 2 5 V IFR feedback resistor current VIN 5V 10 HA VIL1 LOW level input voltage VSS 0 5 5 0 3VDD V VIH1 HIGH level input voltage 0 7VDD VDD 0 5 V INTO HSYNCIN VSYNCIN input leakage current VIN VSS 1 0 input leakage current VIN VDD 0 1 VIL LOW level input voltage 5 VSS 0 5 0 3VDD V May 2001 ver1 1 HMS9xC7132 HMS9xC7134 hynix
5. 11 7 2 Recommended Operating Conditions 11 7 3 DC Electrical Characteristics 11 7 4 AC Characteristics 13 8 MEMORY ORGANIZATION 16 8 Registers REY 16 8 2 Program Memory 17 8 3 Data memory 17 98 4 Eistof SERS wt eaten dee AS y put 20 8 5 Addressing Mode 22 9 INTERRUPTS 24 9 1 Interrupt Sources 24 9 2 Interrupt Enable structure 26 9 3 Interrupt Priority structure 27 9 4 How Interrupt are handled 29 10 POWER SAVING MODE 30 10 1 Power control register 30 10 2 Idle mode 31 10 3 Power down mode 31 11 32 11 1 Pin function selection 33 12 OSCIALLTOR 36 IS IBESET S see wA 37 13 1 External reset 37 May 2001 ver1 1 HMS9xC7132 HMS9xC7134 13 2 Watchdog timer overflow 37 13 3 Low VDD voltage reset 37 14 WATCHDOG TIMER 38 15 TIMER 39 15 1 0 and Timer1 39 15 2 TIMER2 bv dab eS 40 16 DDC INTERFACE 42 16 1 The S
6. Specifications Symbol Parameter Condition Unit Min Typ Max VIH HIGH level input voltage 2 0 VDD 0 5 V SOG P3 7 IIL1 input leakage current VIN 0 45V 55 3 10 ITL input transition current VIN 2 0V 650 65 input leakage current VIN VDD 0 1 VIL LOW level input voltage VSS 0 5 0 8 V VIH HIGH level input voltage 5 2 0 2 VDD 0 5 V VOL LOW level output voltage IOL 5mA 0 0 4 V VOH HIGH level input voltage IOH 5mA 3 5 gt VDD V P0 0 to P0 5 IIL input leakage current VIN VSS 1 0 input leakage current VIN VDD 0 1 VIL 1 LOW level input voltage VSS 0 5 0 3VDD V VIH1 HIGH level input voltage 0 7VDD VDD 0 5 V VOL LOW level output voltage IOL 5mA 0 0 4 V P0 6 to 0 7 input leakage current VIN VSS 1 0 5 input leakage current VIN VDD 0 1 VIL 1 LOW level input voltage VSS 0 5 0 3VDD V VIH1 HIGH level input voltage 0 7VDD E VDD 0 5 V VOL1 LOW level output voltage IOL 10mA 0 0 4 V P2 0 to P2 7 BP2 0 to BP2 7 input leakage current VIN 0 45V 55 10 ITL1 input transition current VIN 3 5V 650 65 HA input leakage current VIN VDD 0 1 VIL 1 LOW level input voltage VSS 0 5 0 3VDD V VIH1 HIGH level input voltage 0 7VDD VDD 0 5 V VOL LOW level output voltage IOL 5mA 0 0 4 V VOH HIGH level input voltage IOH 5mA 3 5 2 VDD V P1 0 to P1 7 P3 0 P3 1 P3 4 P3 6 P3 7 input leakag
7. OR register to 1 1 4x ORL A direct OR direct byte to A 2 1 45 ORL A Ri OR indirect RAM to A 1 1 46 47 ORL A data OR immediate data to A 2 1 44 ORL direct A OR A to direct byte 2 1 42 ORL direct data OR immediate data to direct byte 3 2 43 XRL A Rn exclusive OR register to A 1 1 6x direct exclusive OR direct byte to A 2 1 65 XRL A QRi exclusive OR indirect RAM to A 2 1 66 67 XRL A data exclusive OR immediate data to A 2 1 64 XRL direct exclusive OR A to direct byte 2 1 62 XRL direct data exclusive OR immediate data to direct byte 3 2 63 CLR A clear A 1 1 E4 CPL A complement A 1 1 F4 RL A rotate A left 1 1 23 RLC A rotate A left through the carry flag 1 1 33 RR A rotate A right 1 1 03 RRC A rotate A right through the carry flag 1 1 13 SWAP A swap nibbles within A 1 1 C4 Data transfer Mnemonic Description Bytes Cycles Hex Code MOV A Rn move register to A 1 1 Ex MOV A direct move direct byte to A 2 1 E5 MOV A Ri move indirect RAM to A 1 1 E6 E7 MOV A data move immediate data to A 2 1 74 MOV Rn A move A to register 1 1 Fx MOV Rn direct move direct byte to register 2 2 Ax MOV Rn data move immediate data to register 2 1 7X MOV direct A move A to direct byte 2 1 F5 MOV direct Rn move register to direct byte 2 2 8x MOV direct direct move direct byte to direct byte 3 2 85 May 2001 ver1 1 83 HMS9xC7132 HMS9xC7134 hynix
8. 0 012 5o 0 15 0 015 1 DIMENSIONS DO NOT INCLUDE MOLD FLASH AND DAMBAR PROTRUSION ALLOWABLE MOLD FLASH IS 0 010 INCH 2 CONTROLLING DIMENSION INCH 0 140 0 120 MOM MS MS 0 045 0 070 BSC 0 035 0 190 c g IS c c May 2001 ver1 1 5 HMS9xC7132 HMS9xC7134 5 PIN FUNCTION Vpp1 Supply voltage Digital Circuit ground Digital 2 Supply voltage Analog Circuit ground Analog RESET Reset the MCU XTAL1 Input to the inverting oscillator amplifier and input to the internal main clock operating circuit XTAL2 Output from the inverting oscillator amplifier HSYNCyn Horizontal sync input VSYNCjn Vertical sync input INTO Vpp External Interrupt input Programming supply volt age during OTP programming PORT The HMS9xC7132 has four 8 bit ports Port0 Port1 Port2 and Port3 Port0 Port3 are the same as in the 80C51 with the exception of the additional functions of Port1 Port2 and Port3 Each has latch SFR P0 P3 output driver and input buffer 0 0 0 7 PO is an 8 bit CMOS bidirectional I O port PO pins have not pull up resister and open drain port It has the capability of drive LED However while the alternative function is per
9. 5 The access conflicting can be avoided because access is done by the interrupt service routine However the EDID transferring from the RAM buffer should be finished within 40 us 48 May 2001 ver1 1 hynix Example Program DDC Interface Initial amp Interrupt part Initial mov DDCCON 01h SWENB 0 mov DDCADR 0 mov DDCCON 00100100b 128 6 DDC1_Int 5 DDC1_enable 1 mov S1CON 47h 100kHz 011 ENI1 1 ACK_enable 1 mov SIADRO 0 DDC2B Slave address mov SIADRI 41h Factory Alignment Host DDC Interface 2F 22 9 AF St LISR LO AI SISTAS XL 91001 SIDAT2I DIAICH 2 ISR 418 SICONS PCA Refresh El c SCH 3 Slaver Receive Address match Il SIDATS 812 SiSTAQ _ Dummy Writing Ct 01 Slave Receive l DDC interrupt Service Control amp Status Peripheral re db 00 0FFh OFFh OFFh OFFh OFFh OFFh 00 DDC_Isr push PSW push DPH E push DPL push ACC push 00 push 01 B mov A DDCCON A 00001000b 1 DDCIINT request bit3 1 jz DDC2 svc DDC1_mode mov A mIICFlag anl A 0000001 1b bUserSoftDDC 1 bDDC IEnable 0 cjne 03h DDClEnable mov A fOFFh 2 mov DDCDAT A DDC Int end DDCIEnable mov A mDDCData mov DDCDAT A mov A mDDCAddress d cjne A 80h DDC1_Sve mov DDCCON 01h DDC1 Disable DDC2 Mode DDCI Svc clr B subb A 8 NormalDDC1 mov DPTR 4DDC Header
10. 2 If BBUSY 1 then go to stepl Else then write slave address to SXDAT and set both ENI and STA reset AA in SxCON Wait for interrupt 4 Read SxSTA If BLOST 1 or ACK REP 1 then write dummy data to SxDAT Go to stepl Else then clear STA Perform required service routines If this datum LAST then set STO in SxCON and write last data to SxDAT Go to step 6 Else then write next data to SxDAT Go to step3 Wait for interrupt Write dummy data to SXDAT 1 If the master don t receive the acknowledge from the slave it generates the STOP condition and returns to the IDLE state 1 This action should be the last in service routine Slave transmitter mode Write slave address to SxADR set AA and in SxCON Wait for interrupt Read SxSTA and write the first data to SXDAT Reset AA in SxCON Wait for interrupt Read SxSTA If ACK_REP 1 then Go to step7 Else then write the next SxDAT Go to step5 Write dummy data to SxDAT 1 These actions should be the last 1 If the master want to stop the current data requests it don t have to acknowledge to the slave transmitter 2 If the slave don t receive the acknowledge from the master it releases the SDA and enters the IDLE state so if the master is to resume the data requests it must regenerate the START condition 54 May 2001 1 1 hynix Master rece
11. 5 2 42SDIP Pin Description Table 5 1 Port Function Description 40DIP The 42SDIP type pin description is the same as The 40DIP type pin description except for adding two pins P3 1 P3 0 to it between pin no 4 and 5 May 2001 ver1 1 hynix HMS9xC7132 HMS9xC7134 6 PORT STRUCTURES P0 0 0 5 6 0 7 P1 0 P1 1 P1 6 1 7 2 0 7 P3 0 P3 1 P3 4 P3 6 P1 2 P1 5 data CMOS P3 2 P3 3 P3 5 P3 7 oen internal reset data May 2001 ver1 1 9 hynix HMS9xC7132 HMS9xC7134 HSYNCIN VSYNCIN INTO VPP TTL VPP detector RESET XTAL1 XTAL2 CMOS pdb 10 May 2001 1 1 hynix 7 ELECTRICAL CHARACTERISTICS 7 1 Absolute Maximum Ratings Supply voltage sese 0 5 to 46 5 V Storage Temperature sss 65 to 150 C Voltage on pin with respect to Ground DE EAT 0 5 to Vpp 0 5 Note Stresses above those listed under Absolute Maxi 7 2 Recommended Operating Conditions HMS9xC7132 HMS9xC7134 mum Ratings may cause permanent damage to the de vice This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for ex tended periods may affect device reliability
12. Parity flag P This flag reflect on number of Accumulator s 1 If number of Ac uumulator s 1 is odd 0 otherwise 1 Sum of adding Acu umulator s 1 to P is always even R0 R7 General purpose register Data Pointer Register Data Pointer Register is 16 bit wide which consists of two 8bit registers DPH and DPL This register is used as a data pointer for the data transmission with external data memory MSB PSW CARRY FLAG AUXILIARY CARRY FLAG GENERAL PURPOSE FLAG REGISTER BANK SELECT FLAG 1 0 0 P RESET VALUE LSB PARITY FLAG NOT ASSIGNED BIT OVERFLOW FLAG REGISTER BANK SELECT FLAG to select Bank0 3 with RSO to select Bank0 3 with RS1 Figure 8 4 PSW Program Status Word Register 8 2 Program Memory The program memory consists of ROM 32K bytes HMS91C7132 and 32K bytes HMS97C7132 8 3 Data memory The internal data memory is divided into four physically separat ed part 256 bytes of RAM 256 bytes of XRAMO and 128 bytes of Special Function Registers SFRs areas 2001 ver1 1 RAM Four register banks each 8 registers wide occupy locations 0 through 31 in the lower RAM area Only one of these banks may be enabled at a time The next 16 bytes locations 32 through 47 17 HMS9xC7132 HMS9xC7134 contain 128 directly addressable bit locations The stack depth is only limited by the available internal RAM space of 25
13. Program Verify algorithms HMS9xC7132 HMS9xC7134 the program memory the encryption table and the security bits The circuit configuration and waveforms for quick pulse pro gramming are shown in Figure 21 1 and Figure 21 2 Figure 21 3 shows the circuit configuration for normal program memory verification Any algorithm in agreement with the conditions listed in Table 21 1 and which satisfies the timing specifications is suitable P3 5 INTO P3 2 ae Program Code Data Verify Code Data Program Encryption Table Program Lock Bit 1 Program Lock Bit 2 Table 21 1 EPROM programming modes Note 1 0 Valid low for that pin 17 Valid high for that pin 2 VPP 12 75V 025V 3 VDD 5V 10 during programming and verification 4 P3 5 PROG receives 10 programming pulses while VPP is held at 12 75V Each programming pulse is low for 100 zs 10s and high for a minimum of 10 15 Program Memory Lock Bits The two level Program Lock system consists of 2 Lock Bits and a 64 bytes Encryption Array which are used to protect the program mem ory against software piracy No program lock features Further programming of the EPROM is disabled EXE Same as mode 2 also verify is disabled U unprogrammed programmed Table 21 2Lock Bit Protection Modes 2001 ver1 1 73 HMS9xC7132 H
14. mov A RO 2 movc A DPTR sjmp DDCI Save i NormalDDC1 mov A EDID_DATA add A RO data post mov RO A 2 movx A GRO E DDCI Save mov DDCDAT A inc mDDCAddress DDC Int end mov A DDCCON E anl A 00000010b 2 SWHINT SCLLow bit1 1 SCL activity jz DDC_I2C_sve mov mDDCAddress 00h gt DDCI Disable DDC2 Mode DDCCON 000000016 mov DDC DC svc mov A SISTA 3 i2C abnormal by G call Stop Arbitration and Acknowledge mov mI2C_status A 2 anl A 811000110b 1100 0 1 1 0 jnz DDC Abnormal GC STOP INTR TX_MODE BUSY BLOST ACK_REP SLV mov A SICON anl A 00001000b 4 Host address matched jnz ADDR_Match E DDC2B svc 5 1 byte data access by DDC2B format Addr Match mov DDCCON 01h DDC1 Disable DDC2 Mode setb bI2C_Dir TX mov A SIDAT E anl A 0FEh LSB BIT MASKING cjne 60h DDC2B_mode_ 60h Factory Host 2001 ver1 1 HMS9xC7132 HMS9xC7134 49 HMS9xC7132 HMS9xC7134 50 Factory mode setb bFactoryMode Factory Alignment Host matched 40h setb bService mov A mI2C status anl A 106 A jz Align_Add_Rx Slave Receive command ljmp Align_I2C_Tx Slave Transmit command Align_Add_Rx clr bI2C Dir RX MCU lt Host mov A 0 mov mlICBuffertpSave A mov mlICBuffertpRead A mov S1DAT 0FFh Dummy write mov 01000111b 12 enable Ack out when own slave address in ljmp DDC_Int_end Fa
15. An automatic reset can be obtained by switching on VDD if the 13 2 Watchdog timer overflow RESET pin is connected to GND via a capacitor and to the VDD via resistor The capacitor should be at least 10uF The increase of the RESET pin voltage depends on the capacitor The voltage must remain below the higher threshold for at mini mum the oscillator start up time plus 2 machine cycles The length of the output pulse from the WDT is over 2048 machine cycles In chapter 14 the watchdog timer is described in more detail 13 3 Low VDD voltage reset When VDD is below 3 7V the built in low voltage detector generates an internal reset signals The reset signal will be LOW during 2ms 12MHz after the voltage is higher than 3 7V May 2001 ver1 1 37 HMS9xC7132 HMS9xC7134 14 WATCHDOG TIMER The hardware watchdog timer WDT resets the HMS9xC7132 when it overflows The WDT is intended as a recovery method in situations where the CPU may be subjected to a software upset To prevent a system reset the timer must be reloaded in time by the application software If the processor suffers a hardware soft ware malfunction the software will fail to reload the timer This failure will result in a reset upon overflow thus preventing the processor running out of control In the idle mode the watchdog timer and reset circuitry remain ac tive The WDT consists of a 19 bit counter the watchdog timer reset WDTRST SFR and watchdog key regis
16. HMS9xC7134 16 5 The RAM Buffer application hynix RAM Buffer RAMBUF the RAM buffer can be shared as the system RAM or DDC RAM buffer MODE EX DAT SWENB XRAM 0 to 127 XRAM 128 to 255 Normally reserved for DDC1 EDID data Note 1 Note 2 Note 3 Normally reserved for DDC1 EDID data Note 1 Note 2 Normally reserved for DDC1 EDID data Note 3 Note 5 Normally reserved for DDC1 EDID data Note 5 Normally reserved for DDC2 EDID data Note 3 Normally reserved for DDC2 EDID data Available for the system access Note 2 Normally reserved for DDC1 EDID data Note 1 Note 2 Note 4 Available for the system access Normally reserved for DDC1 EDID data Note 4 Note 5 Available for the system access Normally reserved for DDC2 EDID data Note 4 Table 16 3 Description of the EX DAT and SWENB Note 1 READ WRITE through MOVX instruction might conflict with the access from DDC1 hardware So the access from CPU by using MOVX instruction is forbidden 2 READ WRITE through DDCADR and RAMBUF registers has the conflicting problem also Even the content of DDCADR which should be employed by DDC1 hardware will be damaged So it is inhibited to use this type of access 3 If DDCADR reaches 127 it will automatically wrap around to 0 after the access is done 4 If DDCADR reaches 255 it will automatically wrap around to 0 after the access is done
17. HPRES To detect the presence of the valid HSYNC sig nal Detector measures the time interval between five sync pulses 4 period time No active sync is coming in if the counter reaches a value of FFOH 4080 HCHG The HCHG flag will be set if a change is detected in either the polarity or the period time To avoid unintended setting of the HCHG flag a small deviation in the period time is allowed The allowed deviation is approximately 167ns per line sync The 1 4 value of incoming VSYNC value will be latched for VPOL VPRES To detect the presence of the valid VSYNC sig nal Detector measures the time interval between two con secutive rising edges of the input signal No active sync is coming in if the counter reaches a value of FFOH 4080 VCHG The VCHG flag will be set if a change is detected in either the polarity or the period time To avoid unintended setting of the VCHG flag a small deviation in the period time is allowed The allowed deviation is approximately 32us per line HSYNC input 12 KHz Table 19 2 Threshold frequencies of the presence detector 62 May 2001 ver1 1 hynix uuu wt 2nd field ppg Ist field Ist field 2nd field Figure 19 2 Standard composite sync signals Figure 19 3 Non standard composite sync signals May 2001 ver1 1 HMS9xC7132 HMS9xC7134 63 HMS9xC7132 HMS9xC7134 hynix Both the HCHG and the VCHG signals are combined and con Due to th
18. May 2001 ver1 1 mode The interrupt is serviced and following return from interrupt instruction RETI the next instruction to be execut ed will be the one which follows the instruction that wrote a logic 1 to PCON O External hardware reset the hardware reset is required to be active for two machine cycle to complete the reset op eration Internal watchdog reset the microcontroller restarts after 3 machine cycles in all cases The power down mode can be terminated by an external RESET in the same way as in the 80C51 but SFRs are cleared due to RE SET 31 HMS9xC7132 HMS9xC7134 11 PORTS The HMS9xC7132 has four 8 bit ports PortO Port2 and Port3 PortO Port3 are the same as in the 80C51 with the ex ception of the additional functions of Port2 and Port3 ports are bidirectional and Pins of which the alternative function Enable Data is not used may be used as normal bidirectional I Os except Special Data Gnd Port3 2 Port3 3 and Port3 5 These Pins can be only used as the QUU output t Special Function Select The use of Port1 Port3 pins as alternative functions are carried Input Data out automatically by the HMS9xC7132 provided the associated SFR bit is set HIGH PortO is the type of open drain I O Port0 6 and Port0 7 have the capability to drive LED Fig 11 1 shows the port structure The alternative function for Porti Port2 and Port3 be descri
19. 5194 HPGI Horizontal pulse output modes ui 00 free running HPGO 01 missing insertion 10 reserved 11 the same pulse as the incoming horizontal sync 2 VOPOL Select polarity of the vertical output pulse 0 positive polarity 1 negative polarity 1to0 VPGI Vertical pulse output modes 00 free running VPGO 01 missing insertion 10 reserved 11 the same pulse as the incoming vertical sync Table 19 18 Description of the HVGEN bits 2001 ver1 1 HMS9xC7132 HMS9xC7134 69 7 6 5 4 3 2 1 0 Table 19 19 Vsync free running output high byte register VFH T 6 5 4 3 2 1 0 vom vorw2 vorwi vow Table 19 20 Vsync free running output low byte register VFL OFCH 7 6 5 4 3 2 1 0 Table 19 21 Hsync free running output high byte register HFH OFDH 7 6 5 4 3 2 1 0 sors sons worn Table 19 22 Hsync free running output low byte register HFL OFEH 7 6 5 4 3 2 1 0 COPOL CPW2 CPWI CPWO 1 PATSI PATSO Table 19 23 Clamping and Pattern control register CPGEN SYMBOL FUNCTION 7 COPOL Select the polarity or level of the clamping pulse 0 positive polarity when enabled static low level when disabled 1 negative polarity when enabled static high level when disabled CFB Select the trigger moment of the clamping output pulse 0 clamp pulse after FRONT porch of horizontal sync 1 clamp pulse after BACK porch of horizonta
20. ACH1 P1 3 ACH 1 4 1 5 Vsync IN Hsync IN PWM1 P2 3 PWM2 P2 4 PWMS P2 5 PWM4 P2 6 PWMS P2 7 Hsync OUT P3 2 Vsync OUT P3 3 PWM6 INT1 P3 4 CLAMP PWM P3 5 PADOUT P3 6 SOG P3 7 P3 0 P3 1 SCL1 P1 0 SDA1 P1 1 ACHO P1 2 ACH1 P1 3 ees ACH2 P1 4 May 2001 ver1 1 hynix HMS9xC7132 HMS9xC7134 4 PACKAGE DIMENSIONS 4 1 40 PDIP DJ ae ee Le KES ba ek ea a ea E 2 075 2 045 0 MIN 0 015 0 200 s 4 2 42 SDIP 0 022 0 015 U U U U U U U 0 065 0 045 0 100 BSC a ea 5 a U 0 140 0 120 0 600 BSC 0 550 0 530 2 0 008 x 05415 1 DIMENSIONS DO NOT INCLUDE MOLD FLASH AND DAMBAR PROTRUSION ALLOWABLE MOLD FLASH IS 0 010 INCH 2 CONTROLLING DIMENSION INCH 0 600 BSC 0 550 0 530 Lu 1 470 1 450
21. DDC2B host Host is master monitor 1 always slave DDC2B DDC2AB ACCESS bus host May 2001 ver1 1 hynix The monitor where HMS9xC7132 resides is always both DDC1 and DDC2 capable with DDC2 having the higher priority The display shall start transmitting DDC1 signals whenever it is pow ered on and the vertical sync signal is applied to it from the hostfor the first time The display shall switch to DDC2 within 3 system clocks as soon as it sees a high to low transition on the clockline SCL indicating that there are DDC2 devices connect ed to the bus Under that condition the mode flag MO will be changed from the default setting 0 to 1 Accordingly the inter rupt will be invoked by setting flag SWHINT as high Monitor Power on Is VSYNC present EDID sent continuously using Communication is idle HMS9xC7132 HMS9xC7134 Fig 16 2 illustrates the concept and interaction between the mon itor and the host After power on the DDCIEN bit is set by S W to act as a DDC1 device Therefore the mode flag MO is set as 0 Following VSYNC as clock the monitor will transmit EDID data stream to the host However if DDC2 clock SCL clock is present the monitor will be switched to DDC2B device with the mode flag setting as 1 Software will judge it is a DDC2B DDC2B or DDC2AB protocol VSYNC as clock Is DDC2 clock present Stop sending of EDID Switch to DDC2 communication mode Is command DDC2B command D
22. INTO Vpp 20 External interrupt 0 Programming supply voltage during OTP programming P0 3 21 General I O port P0 3 P0 2 22 General I O port P0 2 PO 1 23 General I O port PO 1 P0 0 24 General I O port P0 0 BP2 3 25 External Access Emulation port2 3 BP2 2 26 External Access Emulation port2 2 P1 5 27 General port P1 5 ADC channels input ACH2 P1 4 28 General I O port P1 4 ADC channel2 input P1 3 29 General I O port P1 3 ADC channel input ACHO P1 2 30 General I O port P1 2 ADC channel0 input SDA1 P1 1 31 General I O port P1 1 12 serial data port for DDC interface SCL1 P1 0 32 General I O port P1 0 serial clock I O port for DDC interface N C 33 No connection N C 34 No connection Vss2 35 Ground2 VDp2 36 Power supply2 5V RSTOUT 37 O RESET or Internal reset out EH IC reset signal active High SOGin P3 7 38 General I O port P3 7 Sync on Green input May 2001 ver1 1 Table 21 4 Port Function Description 64MQFP 79 HMS9xC7132 HMS9xC7134 hynix PINNAME Pin ater abut Alternate No nate Basic Alternate PATOUT P3 6 39 General port P3 6 Pattern out CLAMP PWM7 Sele LOUIE Clamp out 8 bit Pulse Width Modulation P3 5 PROG 40 e input during OTP 2 1 41 External A
23. the data memory can be read out for program verification The address of presented at port 0 will be the exclusive NOR of the program byte the program memory location to be read is applied to port 1 2 and with one of the encryption bytes The user will have to know the VSYNCIN as shown in Figure 21 4 The other pins are held at encryption table contents in order to correctly decode the verifi the Verify Code Data levels indicated in Table 21 1 The con cation data The encryption table itself cannot be read out tents of the address location will be emitted on port 0 for this P2 5 P2 6 P2 7 P3 2 EA P3 3 PSEN P3 5 PROG P3 6 P3 7 INTO VPP Figure 21 3 Verification Configuration 76 May 2001 ver1 1 hynix HMS9xC7132 HMS9xC7134 EPROM Programming and Verification Characteristics TA 21 to27 C Vec 5V 10 Vss 0V Parameter Symbol 1 Programming supply voltage VPP Programming supply current IPP 50 10 Address setup to PROG low tavar 48 Oscillator frequency Address hold after PROG 48 n 59 0 0 0 2 4 VPP setup to PROG GL 1 1 VPP hold after PROG SL 48 Data float after ENABLE 2 Address to data valid ENABLE low to data valid PROG width 1 PROGRAMMING VERIFICATION P1 0 P1 7 P2 0 P2 5 K amp ADDRESS K ADDRE
24. us DDC1 Mode tH vcLk VCLK high time 20 usV VCLK low time 20 us VCLK to output valid fosc 12MHz 680 us tSU DDC1 DDC1 mode setup time TBD us tNC IN cancelled noise input fosc 12MHz 300 us DDC2 Mode scL SCL clock frequency 0 100 kHz tHD SDA Start condition hold time 4 0 us tsU STO Stop condition setup time 4 0 us Data hold time 300 us tsu sTa Rstart 1 condition setup time 4 7 us tu scL SCL high period 4 0 gt us SCL low period 5 47 us HSYNCin f HSYNC HSYNC input frequency 12 120 kHz tw HSYNC HSYNC input pulse width 0 25 8 us d HSYNC HSYNC duty cycle 5 25 VSYNCin VSYNC input frequency 32 200 Hz tw VSYNC VSYNC input pulse width 1 24 VSYNC duty cycle 25 SOGin May 2001 1 1 13 hynix HMS9xC7132 HMS9xC7134 Specifications Symbol Parameter Condition Unit Min Typ Max equalizing pulse period 0 5 3 tw EQ equalizing pulse width 0 5 n EQ equalizing pulse interval 30 HSYNCout VSYNCout ID HSYNC HSYNC input to output 100 Hs TRAE o m om tb HSYNC VSYNC input to output 5 180 ns VSYNC input to output _ 1 ae after missing VSYNCin p CLAMP HSYNCin to CLAMP z 100 m 14 May 2001 ver1 1 hynix HMS9xC7
25. 0D7H RESET VALUE x00x0000B BIT SYMBOL FUNCTION 7 Reserved This bit defines the size of the EDID data It is related to the function of the post increment of the address pointer DDCADR When the upper limit is reached the DDCADR will wrap around to 00H 6 EX DAT f EX DAT is R W 1 The data size is 256 byte 0 The data size is 128 byte The addressing range for the EDID data buffer is mapped from 0 to 127 the rest 128 to 255 can still be used by the system This bit indicates if the software CPU is needed to take care of the operation of DDC1 protocol If SWENB is 1 DDC1 protocol CPU is interrupted during the period of the 9th transmitting bit so that the SWENB S W service routine can update the hold register of transmitter by moving new data from appro R W priate area it is not necessary to be the RAM buffer which is pointed by DDCADR to the register DDCDAT This transmitting must be done within 40us 0 The hold register of the transmitter will be automatically updated from the RAM buffer without the intervention of CPU 4 2 Reserved Interrupt Request Bit This bit is only valid in DDC1 protocol while S W handling is enabled This DDC1INT bit is set by H W and should be cleared by S W in interrupt service routine R W 1 Interrupt request is pending 0 No interrupt request DDC1 enable control bit If DDC1EN is DDC1EN 2 R W 1 DDC1 is enabled 0 DDC1 is disabled The activi
26. 21 4 Development Tools 81 22 INSTRUCTION 82 Muspcrie 1 0 May 2001 ver1 1 hynix HMS9xC7132 HMS9xC7134 HMS9xC7132 HMS9xC7134 CMOS SINGLE CHIP 8 BIT MICROCONTROLLER FOR MONITOR 1 OVERVIEW 1 1 Description The HMS9xC7132 4 is a single chip microcontroller of the 80C51 family which is dedicated for monitor application It is particularly suitable for multi sync computer monitor controller This contains DDC interfaces to the PC host sync detector and sync processor for auto sync application ADC static PWM dynamic PWM and 12 bus interface for control of the video and deflection functions of the monitor Device name ROM Size SEC Package 32K bytes 30 42DIP 40DIP HMS91C7132 4 MMS917132 4 Mask ROM 912 bytes 32 42801 597071324 425DIP HMS91C7132 4K 1 2 Features 80 51 core 32K bytes of ROM for HMS91C7132 4 82K bytes of OTP ROM for HMS97C7132 4 256 bytes of RAM and 256 bytes of XRAM for DDC operation Uses an external crystal of 12 MHz One DDC compliant interface Fully supports DDC1 with dedicated hardware DDC2B DDC2AB and DDC2B compliant dedi cated hardware based on 2 bus interface RAM buffer with programmable size 128 bytes or 256 bytes which can be used for DDC opera tion or shared as system RAM On chip sync processor HSYNC frequency with 12
27. 82 ANL bit AND complement of direct bit to carry flag 2 2 OR bit OR direct bit to carry flag 2 2 72 OR OR complement of direct bit to carry flag 2 2 0 MOV bit move direct bit to carry flag 2 1 A2 bit C move carry flag to direct bit 2 2 92 JC rel jump if carry flag is set 2 2 40 JNC rel jump if carry flag is not set 2 2 50 JB bit rel jump if direct bit is set 3 2 20 JNB bit rel jump if direct bit is not set 3 2 30 JBC bit rel jump if direct bit is set and clear bit 3 2 10 Note This command is not available under OTP Emulation Mode 84 May 2001 ver1 1 hynix HMS9xC7132 HMS9xC7134 Program branching Mnemonic Description Bytes Cycles Hex Code ACALL addri1 absolute subroutine call 2 2 1 LCALL addri6 long subroutine call 3 1 12 RET return from subroutine 1 2 22 RETI return from interrupt 2 2 32 AJMP 6 absolute jump 2 2 21 LJMP addr16 long jump 3 2 02 SJMP addri 6 short jump relative address 2 2 80 JMP A DPTR jump indirect relative to the DPTR 1 2 73 JZ rel jump if A is zero 2 2 60 JNZ rel jump if A is not zero 2 2 70 CJNE direct rel compare direct byte to A and jump if not equal 3 2 B5 CJNE A data rel compare immediate data to A and jump if not equal 3 2 B4 CJNE Rn data rel compare immediate data to register and jump if not 3 2 Bx equal CJNE rel compa
28. CLAMP or PWM7 interface line push pull P3 6 is combined with the PATOUT interface line push pull P3 7 is combined with the SOG interface line pull up 32 hynix Q VO PIN Figure 11 1 Standard output with the open drain port May 2001 ver1 1 hynix HMS9xC7132 HMS9xC7134 11 1 Pin function selection Special function selection Registers PxSFS Several SFR P1SFS P2SFS P3SFS s are used to select the port function or the alternative function of the external pin P1SFS Port1 special function selection register 7 6 5 4 3 2 2 0 P1SFS7 P1SFS6 P1SFS5 P1SFS4 15 5 P1SFS2 P1SFS1 P1SFS0 Table 11 1 P1SFS bits 91H BIT SYMBOL FUNCTION RESET The selection of the pin function 7 P1SFS7 0 pin 9 has P1 7 function 0 1 pin 9 has SDA2 function The selection of the pin function 6 P1SFS6 0 pin 10 has P1 6 function 0 1 pin 10 has SCL2 out function The selection of the pin function 5 P1SFS5 0 pin 20 has P1 5 function 0 1 pin 20 has out function The selection of the pin function 4 P1SFS4 0 pin 21 has P1 4 function 0 1 pin 21 has ACH out function The selection of the pin function 3 P1SFS3 0 pin 22 has P1 3 function 0 1 pin 22 has 1 out function The selection of the pin function 2 P1SFS2 0 pin 23 has P1 2 function 0 1 pin 23 has ACHO out function The selection of the pin function 1 P1SFS1 0 pin 24 has P1 1 func
29. D conversion is completed cleared when A D conversion is in process The con version time takes maximum 13us 9 12MHz Successive Approximation Circuit Figure 20 1 A D block diagram 2001 ver1 1 71 hynix HMS9xC7132 HMS9xC7134 7 6 5 4 3 2 1 0 Table 20 1 ADC control register ACON 97H SYMBOL FUNCTION me mem 5 ADEN ADC enable bit 0 ADC shut off and consumes no operating current 1 enable ADC ADS1 ADSO Analog channel select Channel0 ACHO Channell ACHI Channel2 ACH2 Channel3 ACH3 ADC start bit 0 force to zero 1 start an ADC after one cycle bit is cleared to 0 ADC status bit 0 A D conversion is in process 1 A D conversion is completed not in process Table 20 2 Description of the ACON bits 7 6 5 4 3 2 1 0 ADAT6 5 ADAT4 ADAT3 ADAT2 ADATI ADATO Table 20 3 ADC data register ADAT 96H SYMBOL FUNCTION to ADATO A D conversion result bit7 to bitO Table 20 4 Description of the ADAT bits 72 May 2001 ver1 1 hynix 21 OPERATION MODE 21 1 OTP MODE The HMS97C7132 is programmed by using a modified Quick Pulse Programming algorithm The HMS97C7132 contains two signature bytes that can be read and used by an EPROM program ming system to identify the device The signature bytes identify the device as an manufactured by HME Table 21 1 shows the logic levels for reading the signature byte and for programming
30. DPWMO out function 34 Table 11 4 Description of the P2SFS bits May 2001 ver1 1 hynix HMS9xC7132 HMS9xC7134 e PSSFS Port3 special function selection register 7 6 5 4 3 2 2 0 P3SFS7 P3SFS6 P3SFS5 P3SFS4 P3SFS3 P3SFS2 P3SFS1 P3SFSO Table 11 5 P3SFS bits 93H BIT SYMBOL FUNCTION RESET The selection of the pin function 7 P3SFS7 0 pin 28 has P3 7 function 0 1 28 has SOG input function The selection of the pin function 6 P3SFS6 0 pin 29 has P3 6 function 0 1 pin 29 has PATOUT out function The selection of the pin function 5 P3SFS5 0 pin 30 has P3 5 function 0 1 pin 30 has CLAMP or PWM7 out function The selection of the pin function 4 P3SFS4 0 pin 31 has P3 4 function 0 1 pin 31 has PWM6 out function The selection of the pin function 3 P3SFS3 0 pin 32 has P3 3 function 0 1 pin 32 has VSYNCout function The selection of the pin function 2 P3SFS2 0 pin 33 has P3 2 function 0 1 pin 33 has VSYNCout function The selection of the pin function 1 P3SFS1 0 reserved The selection of the pin function 0 P3SFSO 0 reserved Table 11 6 Description of the P3SFS bits May 2001 1 1 35 hynix HMS9xC7132 HMS9xC7134 12 OSCIALLTOR The oscillator circuit of the HMS9xC7132 is a single stage invert from an external source and XTAL2 left open circuit ing amplifier in a Pierce oscilla
31. LVREN LVRLS GF1 GFO PD IDL Table 10 1 Power control Register PCON 87H RESET VALUE xx000000B BIT SYMBOL FUNCTION 7106 Not used 5 LVREN Enable low voltage reset 4 LVRLS Select low VDD level 3 7V or 3 5V 3 GF1 General purpose flag bit 2 GFO General purpose flag bit 1 PD Activate Power down mode 0 IDL Activate Idle mode 30 Table 10 2 Description of the PCON bits May 2001 ver1 1 hynix HMS9xC7132 HMS9xC7134 MODE MEMORY PORTO 3 SYNC PWM 2 DDC Idle Intenal Data on High High Z on Power down Intenal Data High High High Z High Z Table 10 3 External Pin Status During Idle and Power down modes 10 2 Idle mode The instruction that sets PCON O is the last instruction executed in the normal operating mode before idle mode is activated Once in the idle mode the CPU status is preserved in its entirety Stack pointer Program counter Program status word Accumulator RAM and other registers maintain their data during idle mode There are three ways to terminate the idle mode Activation of any enabled interrupt TO X1 T1 etc will cause 0 be cleared by hardware terminating Idle 10 3 Power down mode The instruction that sets PCON 1 is the last executed prior to go ing into the Power down mode Once in Power down mode the oscillator is stopped The contents of the on chip RAM and the Special Function Register are preserved
32. Register 0B3H R W 1111111111111 IPA Interrupt Priority Register 0B6H R W 0 0 IP Interrupt Priority Register 0B8H R W 0000000 T2CON Timer2 Control Register 0C8H R W 0 RC2L Reload Low Register R W 100000000 RC2H Reload High Register OCBH R W 00000000 PSW Program Status Word Register R W 00000000 RAMBUF RAM Buffer Interface Register R W 2001 ver1 1 hynix HMS9xC7132 HMS9xC7134 Register Description Address R W value 76543210 DDCDAT Data Shift Register for DDC1 OD5H R W 00000000 DDCADR DDC Address Pointer Register OD6H R W 00000000 DDCCON DDC Mode Status and DDC1 Control Register 0D7H R W x S1CON Serial Control Register for DDC2 0D8H R W 00000000 S1STA Serial Status Register for DDC2 OD9H R 0 0 0 S1DAT Data Shift Register for DDC2 ODAH R W 100000000 S1ADRO Serial AddressO Register for DDC2 ODBH R W 0 0 0 0 0 0 0 x S1ADR1 Serial Address1 Register for DDC2 0D3H R W 0 0 0 0 0 0 0 x S2CON Serial Control Register ODCH R W 00000000 S2STA Serial Status Register ODDH R 0 S2ADR Serial Address Register for 2 ODFH R W 0 0 0 0 0 0 0 x S2DAT Data Shift Register for 2 ODEH R W 00000000 ACG Accumulator OEOH R W 00000000 EXCON Ext
33. Table 15 1 Timer Mode Control register TMOD RESET VALUE 00000000B BIT SYMBOL FUNCTION Gating control when set Timer x is enabled only while pin is high 7 3 and control bit is set When cleared Timer x is enabled whenever TRx control bit is set Timer or Counter selector 6 2 C T 0 Timer 1 Counter not supported M1 MO Operating modes 0 0 8 bit Timer THx with TLx as 5 bit prescaler 0 1 16 bit Timer THx and TLx are cascaded there is no prescaler 10 8 bit auto reload Timer holds a value which is to be reloaded into TLx each time it overflows 7100 1 1 0 TLO is an 8 bit Timer controlled by the standard Timer 0 control bit THO is an 8 bit timer only controlled by Timer 1 control bit Timer1 Timer 1 stopped Table 15 2 Description of the TMOD bits 2001 ver1 1 39 7 6 5 4 3 2 2 0 TF1 TR1 TFO TRO IE1 IT1 IEO ITO Table 15 3 Timer Control register TCON RESET VALUE 00000000B BIT SYMBOL FUNCTION 7 Timer1 overflow flag Set by hardware on Timer oveflow Cleared by hardware when processor vectors to interrupt routine 6 TR1 Timer1 run control bit Set cleared by software to turn Timer on off 5 TFO 0 overflow flag Set by hardware on Timer oveflow Cleared by hardware when processor vectors to interrupt routine 4 TRO Tim
34. VSYNCout P3 4 PWM6 P3 5 CLAMP PWM7 P3 6 PATOUT P3 7 SOG May 2001 ver1 1 hynix 5 1 40DIP Pin Description HMS9xC7132 HMS9xC7134 Pin dou F ncuon Alternate No nate Basic Alternate PWMO P2 2 1 General I O port P2 2 8 bit Pulse Width Modulation outputO DPWMO P2 1 2 General I O port P2 1 8 bit Dynamic Pulse Width Modulation outputO DPWMO P2 0 3 General I O port P2 0 8 bit Dynamic Pulse Width Modulation output1 RESET 4 Reset input 5 Power supply1 5V Vss1 6 Ground1 XTAL2 7 Oscillator output pin for system clock XTAL1 8 Oscillator input pin for system clock SDA2 P1 7 9 General port P1 7 12 serial data port SCL2 P1 6 10 General I O port P1 6 2 serial clock I O port P0 7 11 General I O port 0 7 adapted for LED driver P0 6 12 General I O port P1 6 adapted for LED driver P0 5 13 General I O port P0 5 P0 4 14 General I O port P0 4 INTO Vpp 15 External interrupt input0 Programming supply voltage during OTP programming P0 3 16 General I O port P0 3 P0 2 17 General I O port P0 2 PO 1 18 General I O port PO 1 P0 0 19 General I O port P0 0 1 5 20 General I O port P1 5 ADC channels input ACH2 P1 4 21 General I O port P1 4 ADC channel2 input P
35. formed the port type will remain the same In case of application to extention of external memory PO outputted Write Read byte and lower byte of external memory address Therefore when it is used as normal I O port PO is open drain driver and when it used as bus port PO is 3 state driver Port pin Alternate function P0 0 No Only for I O function No Only for I O function P0 2 No Only for function P0 3 No Only for I O function P0 4 No Only for I O function P0 5 No Only for I O function P0 6 No Only for I O function P0 7 No Only for function 6 hynix P1 0 P1 7 P1 is an 8 bit CMOS bidirectional I O port Because P1 pins have pull up resister it is called as Quasi Bidirectional port Port pin Alternate function P1 0 SCL1 DDC SCL P1 1 SDA1 DDC SDA P1 2 ACHO P1 3 ACH1 P1 4 ACH2 P1 5 P1 6 SCL2 I2C SCL P1 7 SDA2 2 5 P2 0 P2 7 P2 is an 8 bit CMOS bidirectional I O port Because P2 pins have pull up resister it is called as Quasi Bidirectional port Port pin Alternate function P2 0 DPWMO P2 1 DPWM1 P2 2 PWMO P2 3 PWM1 P2 4 PWMe2 P2 5 PWMS P2 6 PWM4 P2 7 PWM5 P3 0 P3 7 P3 is an 8 bit CMOS bidirectional I O port Because P3 pins have pull up resister it is called as Quasi Bidirectional port Port pin Alternate function P3 0 Reserved P3 1 Reserved P3 2 HSYNCout P3 3
36. lt RAM 3E 2 Indirect addressing In indirect addressing the instruction specifies a register which contains the address of the operand Both internal and external RAM can be indirectly addressed The address register for 8 bit addresses can be RO or of the selected register bank or the Stack Pointer The address register for 16 bit addresses can only be the 16 bit data pointer register DPTR Example mov R1 40H R1 lt 40H 3 Register addressing The register banks containing registers RO through R7 can be accessed by certain instructions which carry a 3 bit register spec ification within the opcode of the instruction Instructions that ac cess the registers this way are code efficient since this mode eliminates an address byte When the instruction is executed one of four banks is selected at execution time by the two bank select bits in the PSW 4 Register specific addressing Some instructions are specific to a certain register For example some instructions always operate on the Accumulator or Data 22 PROG MEMORY 04 gt A PROG MEMORY 40 55 R1 55 mov PSW 0001000B select BankO mov 30H mov Example Pointer etc so no address byte is needed to point it The opcode itself does that May 2001 ver1 1 hynix 5 Immediate constants addressing The value of a constant can follow the opcode in Pro
37. pop 01 pop 00 pop ACC pop DPL pop DPH pop PSW reti i2C enable stop out Ack out Initial hangup check counter normal I2C hardware interface SWENB 0 128 6 DDCI Int 5 DDCI enable 1 100kHz 011 ENI1 1 ACK_enable 1 DDC2B Slave address Factory Alignment Host gt Receive Transmit i2C enable Ack out when own slave address in hynix May 2001 ver1 1 17 12C INTERFACE In the Monitor MCU are two I2C interfaces implemented The first one is used by the DDC protocols The second one is dedicated for internal connection With this one it s possible to control the video deflection conver gence and some other functions of the monitor The serial port supports the twin line I2C bus consists of a data line SDAx and a clock line SCLx SDA1 SCL1 the serial port line for DDC Protocol SDA2 SCL2 the serial port line for Internal Connection In both 2 interfaces these lines also function as I O port lines as follows e SDA1 P1 1 SCL1 P1 0 SDA2 P1 7 SCL2 P1 6 The system is unique because data transport clock generation address recognition and bus control arbitration are all controlled by hardware The I2C serial I O has complete autonomy in byte handling and operates in 4 modes e Master transmitter e Master receiver e Slave transmitter Slave receiver These functions are controlled by the SFRs SxCON the control of byte handling and the operation of
38. 1 SDA2 p1 7 gt SCL2 P1 6 gt P0 7 P0 6 P0 5 lt gt P0 4 INTO VPP P0 3 P0 2 P0 1 4 P0 0 NC PWMO P2 2 4 gt DPWMO 2 14 DPWMO P2 0 _ RESET gt Vpp1 gt Vssi gt XTAL2 lt XTAL1 SDA2 P1 7 4 SCL2 1 6 gt P0 7 4 P0 6 4 P0 5 lt 4 INTO VPP P0 3 gt P0 2 4 0 1 lt P0 0 gt 1 5 4 1 42 2 41 3 40 4 39 5 38 6 37 7 T 36 8 2 35 9 o 34 10 33 11 5 32 12 M 31 13 30 14 9 29 15 28 16 27 17 26 18 25 19 24 20 23 21 22 P 1 42 2 41 3 40 4 39 5 38 6 37 7 T 36 8 35 9 o 34 10 33 11 5 32 12 J 31 13 30 14 9 29 15 28 16 27 17 26 18 25 19 24 20 23 21 22 hynix Vsync IN Hsync IN lt gt PWM1 P2 3 lt gt 2 P2 4 PWMS P2 5 PWM4 P2 6 PWM5 P2 7 Hsync OUT P3 2 Vsync OUT P3 3 PWMe INT1 P3 4 CLAMP PWM P3 5 PADOUT P3 6 SOG P3 7 Vpp2 Vss2 SCL1 P1 0 SDA1 P1 1 ACHO P1 2
39. 1 3 22 General I O port P1 3 ADC channel1 input ACHO P1 2 23 General I O port P1 2 ADC 10 input SDA1 P1 1 24 General I O port P1 1 serial data port for DDC interface SCL1 P1 0 25 General I O port P1 0 2 serial clock I O port for DDC interface Vsse2 26 Ground2 Vpp2 27 Power supply2 5V SOGin P3 7 28 General I O port P3 7 Sync on Green input PATOUT P3 7 29 General I O port P3 6 Pattern out LAMP PWM7 General outDUP OQ Clamp out 8 bit Pulse Width Modulation Ee PROC 30 input during Rs 4 31 o General I O port P3 4 E Modulation output6 External VSYNCout P3 3 32 General I O port P3 3 Vertical sync output HSYNCout P3 2 33 General I O port P3 2 Horizontal sync output PWM5 P2 7 34 General I O port P2 7 8 bit Pulse Width Modulation output5 PWMA P2 6 35 General I O port P2 6 8 bit Pulse Width Modulation output4 PWMG3 P2 5 36 General I O port P2 5 8 bit Pulse Width Modulation output3 PWMe P2 4 37 General I O port P2 4 8 bit Pulse Width Modulation output2 May 2001 ver1 1 Table 5 1 Port Function Descripti on 40DIP HMS9xC7132 HMS9xC7134 hynix PIN NAME Pin In Out Function Alternate No Alter i nate Basic Alternate PWM1 P2 3 38 General I O port P2 3 8 bit Pulse Width Modulation output1 HSYNCin 39 Horizontal sync input VSYNCin 40 Vertical sync input
40. 132 HMS9xC7134 it tD SDA gt 44 gt Mt tsupa n H 506 gt e DN ES tsu sTO Figure 7 1 timing on the I2C bus E tWHSYNC HSYNCout gt gt itt c gt D CLAMP HH CLAMP front porch CLAMP 4 2 totam back porch VSYNCout gt it Figure 7 2 SYNC timing May 2001 ver1 1 15 HMS9xC7132 HMS9xC7134 8 MEMORY ORGANIZATION The HMS91C7132 has separate address spaces for Program memory Data Memory Program memory can only be read not written to It can be up to 32K bytes of Program memory OPT type HMS97C7132 32K bytes hynix Data memory can be read and written to up to 256 bytes including the stack area Internal RAM and 256bytes External RAM 256bytes of XRAMO Indirect only Gri 32K ROM Direct mov or Indirect Qri 4 Direct mov Indirect Indirect Qri Gri or movx dptr XRAMS 0 program memory data memory Figure 8 1 Memory map and address spaces 8 1 Registers This device has several registers that are the Program Counter PC Accumulator A B register B the Stack Pointer SP the Program Status Word PSW General purpose regis ter RO R7 and DPTR Data pointer register ACCUMULATOR B REGISTER STACK POINTER P
41. 14 2 Description of the WDTKEY bits 7 6 5 4 3 2 2 0 WDTRST7 WDTRST6 WDTRST5 WDTRST4 WDTRST3 WDTRST2 WDTRST1 WDTRSTO Table 14 3 Watchdog timer clear register WDTRST 0A6H RESET VALUE 00000000B BIT SYMBOL FUNCTION WDTKEY7 Enable or disable watchdog timer 7100 to 01010101 55 disable watchdog timer WDTKEYO others enable watchdog timer Table 14 4 Description of the WDTRST bits Example Program Watch Dog Timer Reset amp WDT refresh Part Reset WDT refresh clr EA mov WDTRST 1Eh Watchdog timer reset mov PSW 00 mov WDTRST Watchdog timer reset mov SP STACK DATA mov WDTKEY 0F0h Watchdog start mov WDTKEY 55h Watchdog stop ret 38 May 2001 ver1 1 hynix 15 TIMER HMS9xC7132 HMS9xC7134 HMS9xC7132 has two 16 bit timers counters Timer0 Timer to be placed in 80C51 core and one 16 bit auto reload timer Timer2 for dynamic PWM 15 1 0 and Timer1 The external input pin that the Timer CounterO and Timer Counter in 80C51 core have is eliminated In the timer function timer register is incremented every machine cycle Thus you can think of it as counting machinecycles Since a machine cycle con sists of 12 oscillator periods the count rate is 1 12 of the oscilla 7 6 5 4 tor frequency Timer 0 Timer 1 have four operating modes These modes is se lected by bit pairs M1 MO in TMOD 3 2 2 0 GATE C T M1 MO GATE C T M1 MO
42. 4 mode e SxSTA the contents of its register may also be used as a vector to various service routines SxDAT data shift register SxADR slave address register Slave address recognition is performed by On Chip H W 7 0 i Slave Address 7 0 Shift Register Arbitration Sync Logic Bus Clock Generation 7 H Control Register 7 0 3 c n Status Register Figure 17 1 The block diagram of the I2C bus serial I O May 2001 ver1 1 51 hynix HMS9xC7132 HMS9xC7134 17 1 The Special Function register for Interface Serial Control Register SXCON S1CON S2CON 1 6 3 4 3 2 1 0 Table 17 1 Serial control register SXCON S1CON OD8H S2CON EUN SYMBOL FUNCTION This bit along with bits CRland CRO determines the serial clock frequency when SIO is in the Master mode Enable When 0 the is disabled SDA and SCL outputs are in the high impedance state START flag When this bit is set the SIO H W checks the status of the I2C bus and generates a START condition if the bus free If the bus is busy the SIO will generate a repeated START condition when this bit is set STOP flag With this bit set while in Master mode a STOP condition is generated When a STOP condition is detected on the I2C bus the SIO hardware clears the STO flag This bit is set when address byte was received Must be cleared by software Acknowledge enable signal If
43. 6 bytes XRAMO The 256 bytes of XRAMO used to support DDC interface is also available for system usage by indirect addressing through the ad dress pointer DDCADR and data I O buffer RAMBUF The ad dress pointer DDCADR is equipped with the postincrement capability to facilitate the transfer of data in bulk for details refer to DDC Interface part However it is also possible to address the DRAM through MOVX command as usually used in the internal BYTE ADDRESS HEX BIT ADDRESS HEX hynix RAM extension of 80C51 derivatives XRAMO 0 to 255 is direct ly addressable as external data memory locations 0 to 255 via MOVX DPTR instruction or via MOVX Ri instruction when the EXCON s LSB is zero Since external access function is not available any access to XRAMO 0 to 255 will not affect the ports 7 6 5 4 3 2 1 0 XRAMS Table 8 1 Extended control Register EXCON BYTE ADDRESS DECIMAL B ANEN FFH AAAA Cer oe f es perpe pe Fere pao pao p ee pa p 8 pe Fw oo 9 9s 99 oe oo oe pos e or 2 BANK1 s 7 BANKO 255 Figure 8 5 RAM ADDRESS 18 May 2001 ver1 1 hynix SFR The SFRs can only be addressed directly in the address range from 128 to 255 Table 8 2 gives an overview of the Special Func tion Registers space Sixteen address in the SFRs space are both HMS9xC7132 HMS
44. 9xC7134 byte and bit addressable The bit addressable SFRs are those whose address ends in OH and 8H The bit addresses in this area are 80H to FFH F8 HVGEN CPGEN VFH VFL HFH HFL FO B MDCON MDST VPH HPH VHPL E8 EXCON E EO D8 S1CON S1STA S1DAT S1ADRO S2CON S2STA S2DAT S2ADR DO PSW S1SDR1 RAMBUF DDCDAT DDCADR DDCCON C8 RC2L RC2H CO B8 BO P3 DPWMCON DPWMO DPWM1 IPA A8 IE PWM4 PWM5 PWM6 PWM7 WDTKEY AO P2 PWMCON PWMO PWM1 PWM2 PWM3 WDTRST IEA 98 90 P1 P1SFS P2SFS P3SFS ADAT ACON 88 TMOD TLO TL1 THO TH1 80 PO SP DPL DPH PCON May 2001 ver1 1 Table 8 2 SFR Memory Map Note The register that can be bit addressing FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87 19 HMS9xC7132 HMS9xC7134 8 4 List of SFRS 20 hynix Register Description Address R W 76543210 0 Register 80H R W 111111111 SP Stack Point register 81H R W 0 0 00 0 1 1 1 DPL Data Pointer Low byte Register 82H R W 00000000 DPH Data Pointer High byte Register 83H R W 00000000 PCON Power Control Register 87H R W 000000 TCON Timer Counter Control Register 88H R W 00000000 TMOD Timer Counter Mode Control Regist
45. 9xC7134 free running output sync pulse equals 12 x 106 HF with about 12 KHz as lower boundary When HPG is 01 the input sync pulse is followed and a substitution pulse is inserted In case HPG equals 11 the inputsync pulse is followed but a substitution pulse is disabled while the incoming sync is missing HPG 1 0 Selected mode Free running mode Period time of horizontal pulse generator HF The same pulse as the input horizontal sync Substitution pulse insertion in case of a missing sync pulse The same pulse as the input horizontal sync No substitution pulse insertion in case of a missing sync pulse Table 19 4 Modes of the horizontal pulse generator 11101 31x 83 ns 11110 32 x 83 ns 11111 33x 83 ns Table 19 5 Free running horizontal sync pulse width Example Program Freerun mode SetFreeRunning Icall SetVcp SetFreeRunningl mov A 01000100b mov MDCON A mov HFH 00101110b mov HFL 01010000b mov VFH 01000010b mov VFL 11001000b mov CPGEN 11100000b mov A 01000000b mov HVGEN A Icall DpmsHLinearity May 2001 ver1 1 rising Edge Interrupt Hf 64 6 kHz HOPW 10000 Vf 60 Hz VOPW 1000 White Picture Clamping and Pattern Negative Hsync Positive Vsync free run 65 HMS9xC7132 HMS9xC7134 19 8 Vertical sync generator This block generates vertical sync pulses with positive polarity This can be done in 3 modes selectable with VPG When VPG is 00 the generator ope
46. A data add immediate data to A 2 1 24 ADDC add register to A with carry flag 1 1 3x ADDC A direct add direct byte to A with carry flag 2 1 35 ADDC A Ri add indirect RAM to A with carry flag 1 1 36 37 ADDC add immediate data to A with carry flag 2 1 34 SUBB Rn subtract register from A with borrow 1 1 9x SUBB A direct subtract direct byte from A with borrow 2 1 95 SUBB A Ri_ subtract indirect RAM from A with borrow 1 1 96 97 SUBB data subtract immediate data from A with borrow 1 1 94 INC A increment A 1 1 04 INC Rn increment register 1 1 Ox INC direct increment direct byte INC Ri increment indirect RAM 1 1 06 07 DEC A decrement A 1 1 14 DEC Rn decrement Rn 1 1 1x DEC direct decrement direct byte 2 1 15 DEC decrement indirect RAM 1 1 16 17 INC DTPR increment data pointer 1 2 A3 MUL AB multiply A and B 1 4 A4 DIV AB divide A by B 1 4 84 DA A decimal adjust A 1 1 D4 82 May 2001 ver1 1 hynix Logical operations HMS9xC7132 HMS9xC7134 Mnemonic Description Bytes Cycles Hex Code ANL AND register to 1 1 5x ANL A direct AND direct byte to A 2 1 55 ANL A Ri AND indirect RAM to A 1 1 56 57 ANL A data AND immediate data to A 2 1 54 ANL direct AND A to direct byte 2 1 52 ANL direct data AND immediate data to direct byte 3 2 53 ORL
47. AS TONLNOD AANLdYO LNIA LNIGIN JOd 96 1 TASA TASH 5 250 Figure 19 1 Block diagram of sync processor 61 May 2001 ver1 1 HMS9xC7132 HMS9xC7134 19 5 Horizontal sync detection This block extracts the following parameters from the incoming horizontal or composite sync HPER The number of clock cycles fSH 12 2 be tween five sync pulses 4 period time thus the 12 bits val ue HPER will be equal to 4 x 12 x 106 fH 1 where fH is the horizontal sync frequency in Hz HPOL The polarity of the sync signal HPOL will be reset in case of a positive polarity and set in case of a negative polarity The 1 4 point value of HSYNC period time will be latched for HPOL 19 6 Vertical sync detection This block extracts the following parameters from the incoming vertical sync VPER Either the number of clock cycles fSV 125kHz sampling between two sync pulses period time In case the period time is measured this 12 bits VPER will be equal to 125 x 103 fV where fV is the vertical sync frequency in Hz VPOL The polarity of the sync signal VPOL will be reset in case of a positive polarity and reset in case of a negative polarity It should be noted here that in case of a composite sync signal at the input the parameter VPOL will be set al ways disregarding the polarity of the incoming composite hynix
48. DC2B command DDC2 communication is idle Monitor is waiting for a command Has a command been received Is 2 command detected Is monitor DDC2B DDC2AB capable Respond to DDC2B DDC2AB command Figure 16 2 Host type detection May 2001 ver1 1 45 HMS9xC7132 HMS9xC7134 16 2 DDC1 protocol DDC1 is primitive and a point to point interface The monitor is always put at Transmit only mode In the initialization phase 9 clock cycles on VSYNC pin will be given for the internal syn chronization During this period the SDA pin will be kept at high impedance state If DDCI hardware mode is used the following procedure is rec ommended to proceed DDC1 operation Stepl Reset DDCIEN by default DDCIEN is cleared as low after power on reset Step2 Set SWENB as high the default value is zero Step3 Depending on the data size of EDID data set EX DAT as low 128 bytes or high 256bytes Step4 By using bulky moving commands DDCADR RAM BUF involved to move the entire EDID data to RAM buffer Step5 Reset SWENB to low DDCIINT DDCIEN Hi Z tsu pc1 4 hynix Step6 Reset DDCADR to 00H Step7 Set DDC1EN as high In case SWENB is set as high interrupt service routine must be finished within 40 machine cycles in 12 MHz system clock Note If EX_DAT equals to low it is meant the lower part is oc cupied by operation and the upper part i
49. FRs for DDC Interface 43 16 2 DDC1 46 16 3 DDC2B 46 16 4 DDC2AB DDC2B protocol 47 16 5 The RAM Buffer and DDC application 48 17 12C INTERFACE 51 17 1 SFRs for 2 Interface 52 17 2 Programmer s Guide for 2 and DDC2 54 18 PULSE WIDTH MODULATION 57 18 1 Static 57 18 2 Dynamic 58 19 SYNC PROCESSOR 60 19 1 Sync input signals 60 19 2 Horizontal polarity correction 60 19 3 Vertical polarity correction 60 19 4 Vertical sync separation 60 19 5 Horizontal sync detection 62 19 6 Vertical sync detection 62 19 7 Horizontal sync 65 19 8 Vertical sync 66 19 9 HSYNC VSYNC output driver 66 19 10 Clamp pulse generator 67 19 11 Pattern generator 67 19 12 Suspend mode 67 20 AD CONVERTOR ADC 71 21 OPERATION MODE 73 213 OTP MODE lt 73 21 2 64MQFP pinning and Package Dimensions 78 21 3 6 Pin Description 79
50. IMETER 28 THIS OUTLINE CONFIRMS TO JEDEC PUBLICATION 95 RESISTRATION MO 112 14 0 7 e SEE DETAIL 1 03 a 2 a 0 73 slo m 1 95 REF Uu 050 100 BSC JE TAIL 0 35 DN V 78 May 2001 1 1 hynix 21 3 64MQFP Pin Description HMS9xC7132 HMS9xC7134 Pin alee Funeten Alternate No nate Basic Alternate N C 1 No connection N C 2 No connection 3 Power supply1 45V Vsst 4 Ground1 XTAL2 5 Oscillator output pin for system clock XTAL1 6 Oscillator input pin for system clock BP2 7 7 External Access Emulation port2 7 BP2 6 8 External Access Emulation port2 6 SDA2 P1 7 9 General port P1 7 12 serial data I O port SCL2 P1 6 10 General I O port P1 6 2 serial clock I O port BP2 5 11 External Access Emulation port2 5 BP2 4 12 External Access Emulation port2 4 P0 7 13 General I O port 7 adapted for LED driver P0 6 14 General I O port P0 6 adapted for LED driver P0 5 15 General I O port P0 5 P0 4 16 General I O port P0 4 N C 17 No connection N C 18 gt No connection N C 19 No connection
51. MS9xC7134 Encryption Array Within the EPROM array are 64bytes of Encryption Array that are initially unprogrammed all 1s Every time that a byte ad dressed during a verify address line are used to select a byte of the Encryption array This byte is then exclusive NOR ed XNOR with the code byte creating an Encrypted Verify byte Reading the Signature Bytes hynix The algorithm with the array in the unprogrammed state all 1s will return the code in its original unmodified form It is recom mended that whenever the Encryption Array is used at least one of the Lock Bits be programmed as well The HMS97C7132 signature bytes in location 30H and 20H To read these bytes follow the procedure for EPROM verify except that P3 6 and P3 7 need to be pulled to a logic low 30H HMS97C7132 20H ADH Manufacturer ID Table 21 3 The Value Quick pulse programming The setup for micro controller quick pulse programming is shown in Figure 21 2 Note that the HMS97C7132 is running with a 4 to 6MHz oscillator The reason the oscillator needs to be running is that the device is executing internal address and pro gram data transfers The address of the EPROM location to be programmed is applied to port 1 2 and VSYNCIN as shown in Figure 21 1 The code byte to be programmed into that location is applied to port 0 RE SET PSEN and pins of port2 and 3 in Table 21 1 are held at the Program Code Data levels indicated in Tab
52. May 2001 verl 1 8 BIT SINGLE CHIP MONITOR MICROCONTROLLERS HMS9xC7132 HMS9xC7134 User s Manual Semiconductor Version 1 1 Published by MCU Application Team bjinlim hynix com blackjoe hynix com 2001 HYNIX Semiconductor All right reserved Additional information of this manual may be served by HYNIX Semiconductor offices in Korea or Distributors and Representatives listed at address directory HYNIX Semiconductor reserves the right to make changes to any information here in at any time without notice The information diagrams and other data in this manual are correct and reliable however HYNIX Semicon ductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual hynix 1 OVERVIEW 1 1 1 Description sco 1 We 2 EeatUles ute ue be iius 1 2 BLOCK DIAGRAM 2 3 PIN ASSIGNMENT 3 3 1 40PDIP pinning 3 3 2428DIP pinning 4 4 PACKAGE DIMENSIONS 5 4 140 PDIP EMI 5 4 242 S8DIP 1 51 Lid RE 5 5 6 5 1 40DIP Pin Description 7 5 2 42SDIP Pin Description 8 6 PORT STRUCTURES 9 7 ELECTRICAL CHARACTERISTICS 11 7 1 Absolute Maximum Ratings
53. N Mode 1 Mode 1 Mode 0 DDC2B DDC2AB command received SWENB 1 DDC2B command received DDC2B DDC2AB DDC2B DDCI Utilities Utilities Utilities DC Transmitter Service Routines i i I2C Interface Figure 16 4 The conceptual structure of DDC Interface 16 4 DDC2AB DDC2B protocol DDC2AB DDC2B 4 is a superset of DDC2B Monitors that im plement DDC2AB DDC2B are full featured ACCESS bus de Command Information sequence between host and monitor must conform to the specification of ACCESS bus Timing rules vices Monitor that implement DDC2B uses the same command set as DDC2AB but cannot use Access bus device Essentially they are similar to DDC2B I2C interface forms the fundamental layer for both protocols The default address for monitors is assigned as 6EH other than DDC2B Monitors and hosts can play both the roles of master and slave Under this kind of protocol it is easy to extend the support for hosts to read VDIF VESA Video Display Information Format and remotely control monitor functions 2001 ver1 1 specified in ACCESS bus such as maximum response time to RESET message 250 ms form host maximum time to hold SCL low 2ms etc can be satisfied through software check and built in timers such as TimerO Timerl In DDC2AB DDC2B monitor itself can act as a monitor to ac tivate the transaction The default address assigned for host is 50H 47 HMS9xC7132
54. ROGRAM STATUS PSW WORD GENERAL PURPOSE REGISTER BANKO 3 DPTR DPH DPTR DPL DATA POINTER REGISTER Figure 8 2 Configuration of Registers Accumulator The Accumulator is the 8 bit general purpose reg ister used for data operation such as transfer temporary saving and conditional judgement etc The Accumulator can be used as a 16 bit register with B Register as shown below Two 8 bit Registers can be used as a BA 16 bit Register Figure 8 3 Configuration of BA 16 bit Registers B Register The B Register is the 8 bit purpose register used for an arithmatic operation such as multiply division with Accumu lator Stack Pointer The Stack Pointer is an 8 bit register used for oc currence interrupts and calling out subroutines Stack Pointer identifies the location in the stack to be access save or re store The stack can be located at any position within 0000g to 007 of the internal data memory The SP is not initialized by hardware requiring to write the initial value the location with May 2001 ver1 1 hynix which the use of the stack starts by using the initialization rou tine Normally the initial value of 7 is used and the stack area is 00y to 7 Stack Area 30 7Fy Bit 15 87 Bit 0 00 7 Hardware fixed SP Stack Pointer could be in 004 7Fy Program Counter The Program Counter is a 16 bit wide which consists of two 8 bit re
55. SS VSYNCN PORTO DATA IN y torva gt Lions lt lt 10 PULSES lt gt taux X DATA OUT gt P3 5 PROG 504 9 4 4 tote INTO VPP NEN cmm gt i m op P2 7 ENABLE Figure 21 4 EPROM Programming and Verification May 2001 1 1 71 hynix HMS9xC7132 HMS9xC7134 21 2 6 pinning and Package Dimensions sof_ PWMo P2 2 s3 PWM1 P2 3 s2 2 2 4 ssf 61 bPwMo P2 0 DPWM1 P2 1 55 1 VSYNG 54 1 HSYNG P3 1 ALE sof PSENN 2 e a m N C PWM3 P2 5 N C N C VDD1 N C VSS1 N C XTAL2 PWM4 P2 6 XTAL1 PWM5 P2 7 2 7 2 BP2 6 VSYNC oy P3 3 SDA2 P1 7 PWM6 P3 4 INT1 597 7132 SCL2 P1 6 BP2 0 2 5 YYWNW BP2 1 BP2 4 CLAMP PWM7 P3 5 PROG 0 7 PATOUT P3 6 P0 6 SOG P3 7 P0 5 RSTOUT P0 4 VDD2 N C VSS2 N C N C N C N C tn a E 4 ffs mcm E m ge ee asa222r2 z Q O O lt lt N N A 2415 23 65 20 10 19 90 i NOTE 1 DIMENSIONS DO NOT INCLUDE MOLD PROTRUSION AND i DAMBAR PROTRUSION ALLOWABLE MOLD PROTRUSION IS 0 254mm ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 08mm TOTAL AT MAXIMUM MATERIAL CONDITION 2 FORMED LEAD SHALL BE PLANAR WITH RESPECT ANOTHER WITHIN 0 10mm 3 CONTROLLING DIMENSION MILL
56. ach interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable special function hynix register IE and IEA All interrupt source can also be globally dis abled by clearing bit EA in IE 7 6 5 4 3 2 2 0 EA EVSYNC ET2 ES ET1 EX1 ETO EXO Table 9 1 Interrupt Enable Register IE 0A8H RESET VALUE 00000000B BIT SYMBOL FUNCTION Disable all interrupts 7 EA 0 no interrupt will be acknowledged 1 each interrupt source is individually enabled or disabled by setting or clear ing its enable bit 6 EVSYNC Enable Vsync interrupt 5 ET2 Enable timer2 interrupt 4 ES Not used 3 ET1 Enable timer1 interrupt 2 EX1 Enable external interrupt INT1 1 ETO Enable timerO interrupt 0 EXO Enable external interrupt INTO Table 9 2 Description of the IE bits 7 6 5 4 3 2 2 0 EDDC EI2C EMD Table 9 3 Interrupt Enable Register IEA 0A7H RESET VALUE 0xxxxx00B BIT SYMBOL FUNCTION 7 EDDC Enable DDC interrupt 6 EX6 Not used 5 EX5 Not used 4 EX4 Not used 3 EX3 Not used 2 EX2 Not used 1 EI2C Enable I2C interrupt 0 EMD Enable MD interrupt 26 Table 9 4 Description of Enable Register IEA 0A7H May 2001 ver1 1 hynix 9 3 Interrupt Priority structure Each interrupt source can be assigned one of two priority levels Interrupt priority levels are defin
57. are to turn Timer on off 1100 TRO Reserved Table 15 6 Description of the TCON bits 40 May 2001 ver1 1 hynix HMS9xC7132 HMS9xC7134 7 6 5 4 3 2 2 0 RC2H7 RC2H6 RC2H5 RC2H4 RC2H3 RC2H2 RC2H1 RC2H0 Table 15 7 Reload Capture high register RC2H OCBH RESET VALUE 00000000B BIT SYMBOL FUNCTION RC2H7 7to0 to Reload low register bit7 to bitO RC2H0 7 6 5 4 3 2 2 0 RC2L7 RC2L6 RC2L5 214 RC2L3 RC2L2 RC2L1 RC2LO Table 15 8 Reload Capture low register RC2L OCAH RESET VALUE 00000000B BIT SYMBOL FUNCTION RC2L7 7100 to Reload low register bit7 to bitO RC2LO Example Program Timer initial Initial amp Timer1 Interrupt part i mov IP 00h Interrupt Priority mov PCON 400 mov TCON 01010000B TO enable mov TMOD 00010001B 16 bit timer set mov 11001000 Global En 7 Vsync 6 Timer1 3 2001 ver1 1 Isr push push push push push push push mov mov PSW PSW DPH DPTR DPL ACC A 00h RO Olh 02h R2 0F0h F060h to Generate 4mSec TL1 60h 41 HMS9xC7132 HMS9xC7134 16 DDC INTERFACE The monitor typically includes a number of user controls to set picture size position color balance brightness and contrast Fur thermore to optimize some internal setting for different display modes the timing characteristics should be acquir
58. bed as follows Port 0 No alternative function e Port 1 P1 0 is combined with the SCL 1 interface line open drain P1 1 is combined with the SDA1 interface line open drain P1 2 is combined with the ACHO interface line high z P1 3 is combined with the ACH1 interface line high z P1 4 is combined with the 2 interface line high z P1 5 is combined with the interface line high z P1 6 is combined with the SCL2 interface line open drain P1 7 is combined with the SDA2 interface line open drain Port 2 P2 0 is combined with the dynamic PWMO interface line open drain or push pull P2 1 is combined with the dynamic PWM1 interface line open drain or push pull P2 2 is combined with the static PWMO interface line open drain or push pull P2 3 is combined with the static PWM 1 interface line open drain or push pull P2 4 is combined with the static PWM2 interface line open drain or push pull P2 5 is combined with the static PWMS interface line open drain or push pull P2 6 is combined with the static PWMA interface line open drain or push pull P2 7 is combined with the static interface line open drain or push pull Port 3 P3 0 has not alternative function P3 1 has not alternative function P3 2 is combined with the HSYNCout interface line push pull P3 3 is combined with the VSYNCout interface line push pull P3 4 is combined with the PWM6 interface line open drain or push pull P3 5 is combined with the
59. bit resolution VSYNC frequency with 12 bit resolution HSYNC and VSYNC polarity HSYNC and VSYNC presence detection Composite sync separation Free running sync generation Clamping pulse output Pattern generation May 2001 ver1 1 Separate input for a SOG signal Missing pulse insertion option HSYNC VSYNC change interrupt One multi master slave 2 interface up to 400K bit s for control of other system IC s Eight 8 bit Static PWM outputs for digital con trol applications Two 8 bit Dynamic PWM outputs for various waveform generation One 8 bit ADC with 4 input channels LED driver port two port lines with 15 mA drive capability One 8 bit port only for I O function 24 derivative ports configurable for alterna tive functions Watchdog timer 524ms max On chip low VDD voltage detect and reset reset period 524ms Operating temperature 0 C to 70 C Special idle and power down modes with low power consumption Single power supply 4 5V to 5 5V hynix HMS9xC7132 HMS9xC7134 2 BLOCK DIAGRAM TIN MdG 0 0WMdG 0 OW Md 112 IVs t 190 1000NASA WONASH moJNASH WONASA A as 04 19894 q 93v 0 A 07 W Ad onus Wg 8xg odd 5592014 72146 10112919 1 2065 sng 5194 perd
60. ccess Emulation port2 1 BP2 0 42 External Access Emulation port2 0 P3 4 43 lO General port P3 4 1 Modulation output6 External VSYNCout P3 3 44 General I O port P3 3 Vertical sync output HSYNCout P3 2 45 General I O port P3 2 Horizontal sync output PWM5 P2 7 46 General I O port P2 7 8 bit Pulse Width Modulation output5 PWMA P2 6 47 General port P2 6 8 bit Pulse Width Modulation output4 N C 48 No connection N C 49 No connection N C 50 No connection PWM3 P2 5 51 General port P2 5 8 bit Pulse Width Modulation output3 PWMe P2 4 52 General I O port P2 4 8 bit Pulse Width Modulation output2 PWM1 2 3 53 General I O port P2 3 8 bit Pulse Width Modulation output1 HSYNCin 54 Horizontal sync input VSYNCin 55 Vertical sync input PSENN 56 Program Store Enable Not Emulation PSEN ALE 57 Address Latch Enable Emulation ALE EAN 58 External Access Not Emulation EA PWMO P2 2 59 General I O port P2 2 8 bit Pulse Width Modulation outputO DPWMO P2 1 60 General I O port P2 1 8 bit Dynamic Pulse Width Modulation outputO DPWMO P2 0 61 General I O port P2 0 8 bit Dynamic Pulse Width Modulation output1 P3 1 62 General I O port P3 1 P3 0 63 General port P3 0 RESET 64 Reset input Table 21 4 Port Function Description 64MQFP 80 May 2001 ver1 1 hynix 21 4 Development Tools The HMS9xC7132 is supported by a full featured macro assemb
61. ck generates a clamping pulse with programmable pulse be set with COPOL CPW 2 0 Clamping pulse width 010 11 13 x 83ns Table 19 8 Clamping pulse width 19 11 Pattern generator This generator is used for test pattern generation when in free run burn in test or e g for quick servicing without the need of a video ning mode Four picture can be selected a white a cross hatch a source The displayed pattern might look different in the different balck and inverted cross hatch pictures When not in free running timing modes symmetric display is not guaranteed mode the output is disabled The pattern output can be used for 19 12 Suspend mode The complete Sync processor can be set into a suspend mode for lowering the power consumption by means of signal MDDN Sync processor is running default Sync processor is disabled Table 19 9 Suspend mode 7 6 5 4 3 2 1 0 MDDN CLMPEN PATEN mf VINTE HSEL VSEL Table 19 10 Mode detection control register MDCON 2001 ver1 1 67 hynix HMS9xC7132 HMS9xC7134 BER SYMBOL FUNCTION MDDN 0 hardware mode detection operating normally default 1 hardware mode detection disabled low power consumption CLMPEN 0 clamp pulse out disabled default 1 clamp pulse out enabled PATEN 0 pattern out disabled default pattern out enabled pe 2 VINTE Vsync rising or falling edge interrupt select 0 Vsync rising edge interrupt 1 Vsync falling e
62. ctory Slave Receive start DDC2B_mode clr bFactoryMode Factory Alignment Host matched cjne A 0A0h DDC Abnormal AOh DDC2B Host mov A mI2C status 5 anl A 106 2 jnz DDC DC Tx Slave Transmit clr bI2C Dir 2 mov S1DAT 0FFh Dummy write mov 01000111b i2C enable Ack out when own slave address in DDC Int end DDC Slave Receive start DDC2B svc 1 byte data handling jb bFactoryMode Line svc mov A 2 status anl A 106 jnz DDC DC Tx Slave Transmit DDC_I2C_Rx mov A SIDAT Slave Receive mov mDDCAddress subaddress catch sjmp DDC_I2C_ref gt DDC DC Tx mov A mDDCAddress Slave Transmit anl A 7Fh 2 mov ROA clr C subb A 8 mov A RO H jnc mode svc mov DPTR 4DDC Header Header load movc A DPTR E sjmp Tx Mode out Tx_mode_sve add A EDID_DATA 0x80 OxFF mov RO 2 movx A GRO Tx Mode out mov SIDAT A EDID data store at SIDAT inc mDDCAddress E mov SICON 47h clear ADDR bit3 1 1 15 edit mov nI2C_Abn_Cnt 80h Ack within 128 mSec P1SFS 1 port sjmp DDC_Int_end 2 DDC Abnormal mov SICON 34000001115 mov nI2C_Abn_Cnt 0 mov PISFS 00001111b clr bFactoryMode mov DDCCON 01h mov DDCADR 0 mov DDCCON 00100100b mov S1CON 47h mov SIADRO 40AIh mov SIADRI 41h jnz DDC DC sTx DDC DC sRx mov A SIDAT sjmp DDC DC ref DDC DC sTx mov S1DAT 0FFh DDC DC ref mov SICON 01000111b DDC Int end
63. dge interrupt 0 HSYNCin 0 VSYNCin VSEL 1 separated VSYNC Table 19 11 Description of the MDCON bits 7 6 5 4 3 1 0 VINT HPRES VPRES HPOL VPOL HCHG VCHG Table 19 12 Mode detection status register MDST 2 SYMBOL FUNCTION VINT Vsync interrupt flag Indicate the presence of Hsync 0 not present Hfreq 12 kHz 1 present Hfreq gt 12 kHz Indicate the presence of Vsync 0 not present Vfreq 30 Hz 1 present Vfreq gt 30 Hz Indicate the polarity of Hsync Csync 0 positive polarity 1 negative polarity Indicate the polarity of Vsync 0 positive polarity negative polarity Indicate a change in horizontal period and or polarity 0 no change 1 change detected Indicate a change in vertical period and or polarity 0 no change 1 change detected Table 19 13 Description of the MDST bits 68 May 2001 ver1 1 hynix 7 6 5 4 3 2 1 0 Table 19 14 Vsync period low byte register OF3H jh 6 3 4 3 2 1 0 Table 19 15 Hsync period low byte register HPH 7 6 5 4 3 2 1 0 Table 19 16 Vsync and Hsync period low high register VHPL 7 6 5 4 3 2 1 0 HOPOL HPGI HPGO mE VOPOL VPGI VPGO Table 19 17 Hsync and Vsync generation control register HVGEN OF9H SYMBOL FUNCTION CECI 3 HOPOL Select polarity of the horizontal output pulse 0 positive polarity 1 negative polarity
64. e current VIN 0 45V 55 10 ITL1 input transition current VIN 3 5V 650 65 HA input leakage current VIN VDD 0 1 VIL 1 LOW level input voltage 2 VSS 0 5 0 3VDD V VIH1 HIGH level input voltage 0 7VDD 5 VDD 0 5 V VOL LOW level output voltage IOL 5mA 0 0 4 V VOH HIGH level input voltage IOH 5mA 3 5 S VDD V P3 2 to P3 3 P3 5 112 input leakage current VIN 0 45V 960 320 ITL2 input transition current VIN 2 0V 1240 350 input leakage current VIN VDD 0 1 VIL LOW level input voltage VSS 0 5 0 8 V VIH HIGH level input voltage 2 0 VDD 0 5 V 12 May 2001 vert hynix HMS9xC7132 HMS9xC7134 Specifications Symbol Parameter Condition Unit Min Typ Max VOL LOW level output voltage IOL 5mA 0 0 4 V VOH HIGH level input voltage 5mA 3 5 VDD V 7 4 AC Characteristics 0 709 Vpp 5 0V Vss 0V Symbol Parameter Condition Unit Min Typ Max XTAL fosc oscillator frequency VDD 5V 10 12 16 MHz C1 xtal1 external Cap 20 pF C2 xtal2 external Cap 20 pF A D Converter VAIN analog input voltage VSS VDD V NAOFF zero offset error TBD LSB Nes full scale error 20 TBD LSB overall accuracy TBD LSB tconv conversion time fosc 12MHz 13
65. ed by the con hynix face A transmitter clocked by incoming VSYNC is dedicated for operation An I2C interface hardware logic forms the ker nel of DDC2B DDC2B and DDC2AB An address pointer with post increment capability is employed to serve DDCI trol side In these days it is getting popular for these controls to DDC2B DDC2B and DDC2AB modes go to PC host Therefore the communication between monitor and host becomes issue DDCI DDC2B DDC2B and DDC2AB ACCESS bus emerge as a standard for monitor inter The conceptual block diagram is illustrated in Fig 16 1 i DDC2B DDC2AB DDC2B Interface Monitor Address SIADRO Monitor Address SIADRI Shift Register Arbitration Logic Bus Clock Generator a 3 ea iso o E DDC1 DDC2 Detection transmitter Initialization synchronization Ex sw ppci swH DDCCON INT Address Pointer DDCADR INTR From SISTA Figure 16 1 DDC Interface block diagram 42 May 2001 ver1 1 hynix HMS9xC7132 HMS9xC7134 16 1 The Special Function register for DDC Interface Eight SFR SICON SISTA SIDAT SIADR RAMBUF DDCCON DDCADR DDCDAT 1 SISTA SIDAT SIADR are just the copies of the corresponding registers in general I2C bus interface 7 6 5 4 3 2 2 0 EX_DAT SWENB DDCINT DDC1EN SWHINT MO Table 16 1 DDC mode status and DDC1 control register DDCCON
66. ed by the interrupt priority spe cial function register IP and IPA 0 low priority 1 high priority A low priority interrupt may be interrupted by a high priority in HMS9xC7132 HMS9xC7134 terrupt level interrupt A high priority interrupt routine cannot be interrupted by any other interrupt source If two interrupts of dif ferent priority occur simultaneously the high priority level re quest is serviced If requests of the same priority are received simultaneously an internal polling sequence determines which request is serviced Thus within each priority level there is a sec ond priority structure determined by the polling sequence This second priority structure is shown in Table 9 5 The Priority within level structure is only used to resolve simultaneous requests of the same priority level The MD interrupt needs a higher priority then ALL the oth er interrupts This is to avoid that a mode change will not be 7 6 5 4 SOURCE PRIORITY WITHIN LEVEL INTO MD 1 highest TimerO 2 1 DDC Timer1 1 VSYN SYNC Timer2 9 lowest Table 9 5 Priority levels Note serviced in time and that the setting of the S curve is not up dated in time When the S curve settings are not updated in time after a mode change the monitor may be damaged 3 2 2 0 PVSYNC PT2 PS PT1 1 Tab
67. ended Control Register R W 0 B Register OFOH R W 100000000 MDCON Mode Indication Register OF1H R W 0 0 0 x x 0 0 0 MDST Mode Status Register OF2H R 0000000 VPH Vertical scan period High byte Register OF3H R W 100000000 HPH Horizontal scan period High byte Register OF4H R W 00000000 VHPL V H scan period High byte Register OF5H R W 100000000 HVGEN H V pulse Control Register OF9H R W CPGEN Clamping pulse and Pattern Control register R W VFH Vertical free running output pulse period High byte OFBH Rw register VEL Vertical free running output pulse period Low byte OFCH Rw 0000 0 1 0 10 register HFH bee output pulse period High OFDH Rw 0 1 1 0 0 0 00 HFL De a output pulse period Low OFEH Rw 0 0 1 1 1 1 1 2001 ver1 1 21 HMS9xC7132 HMS9xC7134 8 5 Addressing Mode The addressing modes in HMS9xC7132 instruction set are as follows Direct addressing Indirect addressing Register addressing hynix Register specific addressing Immediate constants addressing Indexed addressing Note that refer to Chapter 22 Instruction Set those addressing modes and related instructions 1 Direct addressing In a direct addressing the operand is specified by an 8 bit address field in the instruction Only internal Data RAM and SFRs 80 FFH RAM can be directly addressed Example mov
68. er 89H R W 100000000 TLO Timer CounterO Low byte Register 8AH R W 100000000 TL1 Timer Counter1 Low byte Register 8BH R W 100000000 THO Timer CounterO High byte Register 8CH R W 100000000 TH1 Timer Counter1 High byte Register 8DH R W 100000000 P1 Port1 Register 90H R W 111111111 P1SFS Port1 Special Function Selection Register 91H R W 100000000 P2SFS Port2 Special Function Selection Register 92H R W 100000000 P3SFS Port3 Special Function Selection Register 93H R W 100000000 ADAT ADC Data Register 96H R W 00000000 ACON ADC Control Register 97H R W 10 00 01 2 Port2 Register R W 1111111111111 PWMCON PWM Control Register OA1H R W 00000000 PWMO PWMO Output Register 0A2H R W 1111111111111 PWM1 PWM 1 Output Register R W 1111111111111 PWM2 PWM Output Register 4 R W 1111111111111 PWM3 PWM3 Output Register 0A5H R W 111111111 PWM4 PWM4 Output Register R W 1111111111111 PWM5 PWM5 Output Register R W 1111111111111 PWM6 PWM6 Output Register R W 111111111 PWM7 PWM7 Output Register OADH R W 1111111111111 WDTKEY Watchdog Key Register OAEH R W 00000000 WDTRST Watchdog Timer Reset Register 0A6H R W 00000000 IEA Interrupt Enable Register 0A7H R W 00 IE Interrupt Enable Register 0A8H R W 00000000 P3 Port3 Register RAW 111111111 DPWMCON Dynamic PWM Control Register 0B1H R W 0 00 DPWMO Dynamic PWMO Output Register 0B2H R W 1111111111111 DPWM1 Dynamic PWM1 Output
69. erO run control bit Set cleared by software to turn Timer on off P E Interrupt1 edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed 5 Interrupt1 type control bit Set cleared by software to specified falling edge low level triggered external interrupts 7 Ed InterruptO edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed 4 ITO InterruptO type control bit Set cleared by software to specified falling edge low level triggered external interrupts Table 15 4 Description of the TCON bits 15 2 TIMER2 Timer2 is a 16 bit auto reload timer The 16 bit capture mode The interval between interrupt baud rate generation mode and an event counter function that the Timer Counter2 in 80C52 core has are eliminated Since the clock of this timer comes from the system oscillator Timer2 can The maximum interrupt period be used to count a time period more accurately comparing with 65536 x 2 x tOSC TimerO and Timerl but the longest period is limited as 65536 x 65536 x 2 x tOSC RC2H x 256 RC2L x 2 x tOSC tOSC 2 7 6 5 4 3 2 2 0 TF2 TR2 Table 15 5 Timer2 control register T2CON 0C8H RESET VALUE 0xxxx0xxB BIT SYMBOL FUNCTION 7 Timer2 overflow flag Set by hardware on Timer overflow Must be cleared by software 6 to 3 Reserved 2 TR2 Timer2 run control bit set cleared by softw
70. es from where it left off Note that a simple RET instruction would also return execution to the interrupted program but it would have left the interrupt control system thinking an interrupt was still in progress making future interrupts impossible SOURCE VECTOR ADDRESS INTO 0003H MD 004BH 0 000 2 0043 0013 DDC 003BH Timer1 001BH VSYNC 0033H Timer2 002BH Table 9 10 Vector addresses 2001 ver1 1 29 hynix HMS9xC7132 HMS9xC7134 10 POWER SAVING MODE Two software selectable modes of reduced power consumption are implemented Idle mode Power down mode The following functions are switched off when the microcontroller enters the Idle mode CPU halted 2C interface halted PWMO to PWM7 and DPWMO to DPWMe reset output High 8 bit ADC aborted if conversion in progress The following functions remain active during Idle mode These functions may generate an interrupt or reset and thus terminate the Idle mode 0 Timer1 and Timer2 Watchdog timer DDC interface External interrupt Mode detection In Power down mode the system clock is halted Both the oscillator will be stopped after setting the bit PD in PCON 10 1 Power control register The modes Idle and Power down are activated by software via the PCON register 7 6 5 4 3 2 2 0
71. gisters PCH and PCL This counter indi cates the address of the next instruction to be executed In reset state the program counter has reset routine address PCq 0FFg PC 0FEg Program Status Word The Program Status Word PSW con tains several bits that reflect the current state of the CPU and se lect Internal RAM 00H 1FH Bank0 Bank3 The PSW is described in Figure 8 4 It contains the Carry flag the Auxiliary carry flag the Half Carry for BCD operation the General pur pose flag the Register bank select flags the Overflow flag the undefined flag and Parity flag Carry flag CY HMS9xC7132 HMS9xC7134 This flag stores any carry or not borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift In struction or Rotate Instruction Auxiliary carry flag AC After operation this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU Register bank select flags RSO RS1 This flags select one of four bank 00 07H bankO 08 0fH bank1 10 17H bank2 17 1FH bank3 in Internal RAM Overflow flag OV This flag is set to 1 when an overflow occurs as the result of an arithmetic operation involving signs An overflow occurs when the result of an addition or subtraction exceeds 127 7Fy or 128 80 The CLRV instruction clears the overflow flag There is no set instruction When the BIT instruction is executed bit 6 of memory is copied to this flag
72. gram mem ory 6 Indexed addressing Only Program memory can be accessed with indexed addressing and it can only be read This addressing mode is intended for reading look up tables in Program memory A 16 bit base register either DPTR or PC points to the base of the table and the Ac cumulator is set up with the table entry number The address of the table entry in Program memory is formed by adding the Ac cumulator data to the base pointer Example move A DPTR May 2001 ver1 1 Example ACC 3A a DPTR PROG MEMORY 1 73 gt Lon EU e eoe HMS9xC7132 HMS9xC7134 mov A 4 100H 1 23 HMS9xC7132 HMS9xC7134 9 INTERRUPTS There are interrupt requests from 9 sources as follows INTO external interrupt INT1 external interrupt TimerO interrupt Timer1 interrupt Timer2 interrupt 9 1 Interrupt sources INTO external interrupt The INTO can be either level active or transition active depend ing on bit ITO in register TCON The flag that actually generates this interrupt is bit in TCON When an external interrupt is generated the corresponding re quest flag is cleared by the hardware when the service routine is INT1 external interrupt The INTI can be either level active or transition active depend ing on bit IT1 in register TCON The flag that actually generates this interrupt is bit IE1 in TCON Whe
73. hen if RESTART is required then set STA in SxCON and write last data to SxDAT Go to step6 Else then set STO in SxCON and write last data to SXDAT Go to step7 Else then write next data to SXDAT Go to step3 Wait for interrupt Write slave address to SxDAT Go to step3 Wait for interrupt Write dummy data to SxDAT This action should be the last in service routine hynix 2001 ver1 1 hynix 18 PULSE WIDTH MODULATION 18 1 Static PWM There are eight static PWM in the HMS9xC7132 These channels provide output pulses of programmable duty cy cle and polarity The duty cycle is defined by a counter The 8 bit counter of a PWM counts modulo 256 i e from 0 to 255 inclusive The value held in the 8 bit counter is compared to the contents of the Special Function Register PWMn of the cor responding PWM The polarity of the PWM outputs is program mable and selected by the PWMLVL bit in PWMCON register Provided the contents of a PWMn register is equal to or greater than the counter value the corresponding PWM output is set HIGH with PWMLVL 0 If the contents of this register is less than the counter value the corresponding PWM output is set LOW with PWMLVL 0 The pulse width ratio is therefore HMS9xC7132 HMS9xC7134 defined by the contents of the corresponding Special Function Register PWMn of a PWM By loading the corresponding Spe cial Function Register PWMn with ei
74. is fast interrupt the S correction can be set to a safe level nected to the internal interrupt Interrupt will be issued when before any damage to the deflection circuitry will occur change is continuously detected like following table HPnew x 61 to 4 x HPnew x 15 n x HPpre Period 4 x HPnew x 3 n x HPpre 4 x HPnew x 3 n x HPpre Polarity NEG gt POS 60 HSYNC lines VPnew lt VPpre VPnew x 2 VPprev to Vnew x 3 Period VPnew gt VPpre VPnew to VPnew x 2 POS gt NEG 3 VSYNC lines Polarity NEG gt POS 2 VSYNC lines Table 19 3 Time interval between mode change and interrupt Internally there are two 12 bit counter for HSYNC and VSYNC 125KHz clock For HSYNC static state that HSYNC frequency period check HSYNC counter count up from 0 to 4096 for 4 is under 12KHz counter value is more than 4080 value and for HSYNC lines according to 12MHz clock and VSYNC counter VSYNC static state that VSYNC frequency is under 32Hz count up from 0 to 4096 for one VSYNC line according to counter value is more than 4080 value 64 May 2001 ver1 1 hynix 19 7 Horizontal sync generator This block generates horizontal sync pulses with positive polari ty This can be done in 3 modes selectable with HPG When HPG is 00 the generator operates in the free running mode and the gen erated pulse repetition period equals HF x 1 12 MHz clock peri od where HF is a 10 bit value As a result the frequency of the HMS9xC7132 HMS
75. iver mode Read SxSTA If BBUSY 1 then go to stepl Else then write slave address to SXDAT and set both and STA reset AA in SxCON Wait for interrupt Read SxSTA If BLOST 1 1 then write dummy data to SXDAT Go to stepl Else then clear STA and write FFH to SxDAT Set AA in SxCON Wait for interrupt Read SxSTA If this datum LAST then reset and read SxDAT Go to step7 Else then read SxDAT Go to step5 Wait for interrupt Read SxSTA Read SxDAT 1 If the master want to terminate the current data requests it don t have to acknowledge to the slave This action should be the last Slave transmitter mode 1 Write slave address to SXADR set AA ENI in SxCON 2 Wait for interrupt 3 Read SxSTA and write FFH to SxDAT 5 Wait for interrupt 6 Read SxSTA If STOP 1 then Go to step7 Else then read data from SxDAT Go to step5 7 Read dummy data from SxDAT 1 This action should be the last May 2001 ver1 1 HMS9xC7132 HMS9xC7134 56 Master restart transmitter Read SxSTA If BBUSY 1 then go to stepl Else then write slave address to SXDAT and set both and STA in SxCON Reset AA in SxCON Wait for interrupt Read SxSTA If BLOST 1 or ACK REP 1 then write dummy data to SxDAT Go to stepl Else then clear STA Perform required service routines If this datum LAST t
76. l sync CPW2 to CPWO Clamp pulse width 1100 PATSI to PATSO Select one of the following patterns 00 white picture 01 cross hatch picture 10 black picture 11 inverse cross hatch picture Table 19 24 Description of the CPGEN bits 70 May 2001 ver1 1 hynix 20 ANALOG TO DIGITAL CONVERTOR ADC The analog to digital converter A D allows conversion of an an alog input to a corresponding 8 bit digital value TheA D module has four analog inputs which are multiplexed into one sample and hold The output of the sample and hold is the input into the converter which generates the result via successive approxima tion The analog supply voltage is connected to VDD2 of ladder resistance of A D module The A D module has two registers which are the control register ACON and A D result register ADAT The register ACON shown in Table 17 1 controls the operation of the A D converter module To use analog inputs I O is selected by PISFS register Ladder Resistor Decoder HMS9xC7132 HMS9xC7134 The processing of conversion starts when the start bit ADST is set to 1 After one cycle it is cleared by hardware The register ADAT contains the results of the A D conversion When conver sion is completed the result is loaded into the ADAT the A D conversion status bit ADSF is set to 1 The block diagram of the A D module is shown in Fig 17 1 The status bit ADSF is set automatically when A
77. le 21 1 The P3 5 PROG is pulsed low 10 times as shown Figure 21 2 To program the encryption table repeat the 10 pulses program ming sequence for address 0 through H using the Program 74 Encryption Table levels Do not forget that after the encryption table is programmed verification cycle will produce only en crypted data To program the security bits repeat the 10 pulses programming sequence using the Program Security Bit levels After one se curity bit is programmed further programming of the code mem ory and encryption table is disabled However the other security bit can still be programmed Note that INTO VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time Even a narrow glitch above that voltage can cause permanent damage to the device The VPP source should be well regulated and free glitches and overshoot May 2001 ver1 1 HSYNC VSYNC P2 0 P2 5 P2 6 P2 7 P3 2 EA P3 3 PSEN P3 5 PROG P3 6 DATA gt po 521 VDD2 1275 iNTO VPP VSS2 P1 Figure 21 1 Programming Configuration 10 PULSES P3 5 PROG 0 Min 10us 100usx 10 3 i gt 100510 E c Enlarged View Figure 21 2 PROG Waveform May 2001 1 1 75 hynix HMS9xC7132 HMS9xC7134 Program Verification If Lock Bit 2 has not been programmed the on chip program eration If the encryption table has been programmed
78. le 9 6 Interrupt Priority Register IP OB8H RESET VALUE x0000000B BIT SYMBOL FUNCTION 7 Reserved 6 PVSYNC Vsync interrupt priority level 5 PT2 Timer2 interrupt priority level 4 PS Not used 3 PT1 Timer1 interrupt priority level 2 PX1 External interrupt INT1 priority level 1 PTO 0 interrupt priority level 0 External interrupt INTO priority level Table 9 7 Description of the IP bits 2001 ver1 1 27 HMS9xC7132 HMS9xC7134 hynix 7 6 5 4 3 2 2 0 PDDC 2 PMD Table 9 8 Interrupt Priority Register IPA 0 6 RESET VALUE 0xxxxx00B BIT SYMBOL FUNCTION 7 PDDC DDC interrupt priority level 6 PX6 Not used 5 PX5 Not used 4 PX4 Not used 3 PX3 Not used 2 PX2 Not used 1 PI2C 12C interrupt priority level 0 PMD MD interrupt priority level 28 Table 9 9 Description of the IPA bits May 2001 ver1 1 hynix 9 4 How Interrupt are handled The interrupt flags are sampled at SSP2 of every machine cycle The samples are polled during following machine cycle If one of the flags was in a set condition at S5P2 of the preceding cycle the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine provided this H W generated LCALL is not blocked by any of the following condi tions An interrupt of equal pri
79. ler linker an in circuit emulator MetaICETM Product Developer An agency in Korea In Circuit Emulators MetalCE zeusemtek www emtek co kr Compiler C51 Compiler 51 251 Assembler Linker Hankook MDS www hkmds com Debugger XHP3051 exe Source level Debugging HMS9xC7132 HMS9xC7134 PC MetaLink Monitor iceMASTER SF Board Emulator Figure 21 5 Developement system Hardware Blockdiagram May 2001 ver1 1 HMS9xC7132 HMS9xC7134 22 INSTRUCTION SET The HMS9xC7132 uses a powerful instruction set which permits the expansion of on chip CPU peripherals and optimizes byte ef ficiency and execution speed Assigned opcodes add new high power operation and permit new addressing modes The instruction set consists of 49 single byte 46 two byte and 16 three byte instructions When using a 12MHz oscillator 64 in Arithmatic operations hynix structions execute in lus and 45 instructions execute in 2us Mul tiply and divide instructions execute in 4 us For the description of the Date Addressing modes and Hexadeci mal opcode cross reference see Boolean variable manipula tion Program brranching Mnemonic Description Bytes Cycles Hex Code ADD add register to 1 1 2x ADD A direct add direct byte to 2 1 25 ADD A Ri add indirect RAM to A 1 1 26 27 ADD
80. n an external interrupt is generated the corresponding re quest flag is cleared by the hardware when the service routine is MD interrupt A MD interrupt is generated by the hardware mode detector in case of mode change horizontal or vertical VSYNC interrupt The changing of the VSYNC level can generate an interrupt This depends on the setting that is programmed in the MDCON SFR Via this register it is possible to enable the edge of the VSYNC signal that should generate the interrupt Both edges DDC interrupt The DDC interrupt is generated either by bit INTR in the SISTA register for DDC2B DDC2AB DDC2B protocol or by bit DDC int in the DDCCON register for DDCI protocol or by bit SWHINT bit in the DDCCON register when DDC protocol is 2 interrupt The interrupt of the second I2C is generated by bit INTR in the register S2STA 24 hynix DDC interrupt MD interrupt VSYNC interrupt e 2C interrupt vectored to only if the interrupt was transition activated If the interrupt was level activated then the interrupt request flag remains set until the requested interrupt is actually generated Then it has to deactivate the request before the interrupt service routine is completed or else another interrupt will be generated vectored to only if the interrupt was transition activated If the interrupt was level activated then the interrupt request flag remains set until the requested interrupt i
81. of PWMs in one video frame One hynix video frame can be divided to any number of blocks according to the register RC2H value within 256 blocks and here the RC2L will be 00H for 8 bit PWM resolution The dynamic PWM outputs DPWMO to DPWMI register share the same pins as Port2 0 Port2 1 respectively The repetition frequency fDPWM at a DPWM output is given by in case of RC2L 00H fDPWM fOSC 2 x 256 J 6 5 4 3 2 1 Q Table 18 3 Dynamic PWM control register DPWMCON 0B1H SYMBOL FUNCTION 7 DPWMLVL Polarity selection of the DPWMs 0 DPWM outputs are not inverted 1 DPWM outputs are inverted DPWMICFG to DPWMOCFG 0 open drain type Output type selection of the DPWMs 1 push pull type Table 18 4 Description of the DPWMCON bits Table 18 5 DPWM application circuit 58 May 2001 ver1 1 Using one Dynamic PWM to compensate the following H size distortion 1 Pincushion PCC amplitude 2 Trapezoid Keystone 3 CBOW Quarter Width 4 PCC corner 5 S Curve JONDE Using one Dynamic PWM to compensate the following H center distortion 1 Pin Balance Bow 2 Key Balance Tilt 3 Corner Balance DUE May 2001 1 1 59 HMS9xC7132 HMS9xC7134 19 SYNC PROCESSOR The characteristics of Sync processor are as follows hynix Automatic mode detection by hardware to capture the following signal characteristics Hsync and Vsync frequency measured wi
82. ority or higher priority level is al ready in progress The current machine cycle is not the final cycle in the ex ecution of the instruction in progress The instruction in progress is RETI or any access to the interrupt priority or interrupt enable registers The polling cycle is repeated with each machine cycle and the values polled are the values that were present at S5P2 of the pre vious machine cycle Note that if an interrupt flag is active but be ing responded to for one of the above mentioned conditions if the flag is still inactive when the blocking condition is removed the HMS9xC7132 HMS9xC7134 denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remem bered Every polling cycle is new The processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate service routine The hardware generated LCALL pushes the contents of the Pro gram Counter on to the stack but it does not save the PSW and reloads the PC with an address that depends on the source of the interrupt being vectored to as shown in Table 9 10 Execution proceeds from that location until the RETI instruction is encountered The RETI instruction informs the processor that the interrupt routine is no longer in progress then pops the top two bytes from the stack and reloads the Program Counter Exe cution of the interrupted program continu
83. rates in the free running mode and the gen erated pulse repetition period equals VF x HF x 1 12 MHz clock period where VF is a 12 bit value As a result the frequency of hynix the free running output sync pulse equals 12 x 106 HF VF When VPG is 01 the input sync pulse is followed and a substitu tion pulse is inserted In case VPG equals 11 the input sync pulse is followed but a substitution pulse is disabled while the incom ing sync is missing VPG 1 0 Selected mode Free running mode Period time of vertical pulse generator VF The same pulse as the input horizontal sync Substitution pulse insertion in case of a missing sync pulse The same pulse as the input vertical sync No substitution pulse insertion in case of a missing sync pulse Table 19 6 Modes of the vertical pulse generator Eo omo Table 19 7 Free running vertical sync pulse width 19 9 HSYNC VSYNC output driver This is output stage for HSYNCout and VSYNCout It offers out put selection output enabling disabling and output polarity selec 66 tion With HOPOL and VOPOL the output is selected May 2001 ver1 1 hynix 19 10 Clamp pulse generator The clamp pulse is generated by setting CLMPEN and always ac width determined by CPW It can be started at the front porch companies the HSYNCout pulse even in the free running mode CFB reset or at the back porch CFB set and the polarity can This blo
84. re immediate data to indirect RAM and jump if 3 2 B6 B7 not equal DJNZ rel decrement register and jump if not zero 2 2 Dx DJNZ direct rel decrement direct byte and jump if not zero 3 2 D5 NOP no operation 1 1 00 Data addressing modes Mnemonic Description Rn working register RO R7 direct 128 internal RAM locations and any special function register SFR Ri indirect internal RAM location addressed by register by register RO or R1 of the actual register bank data 8 bit constant included in instruction data16 16 bit constant included as bytes 2 and 3 of instruction bit direct addressed bit in internal RAM or SFR addr16 16 bit destination address Used by LCALL and LUMP the branch will be anywhere within the 64 kbytes Program Memory address space addr1 1 111 bit destination address Used and AJMP the branch will be within the same 2 kbytes page of Program Memory as the first byte of the following instruction rel signed two s complement 8 bit offset byte Used by SUMP and all conditional jumps range is 128 to 127 bytes relative to first byte of the following instruction 2001 ver1 1 85 HMS9xC7132 HMS9xC7134 Hexadecimal opcode cross reference hynix Mnemonic Description x 8 9 y 1 3 5 7 9 B D 2 0 2 4 6 8 86 May 2001 ver1 1
85. s actually generated Then it has to deactivate the request before the interrupt service routine is completed or else another interrupt will be generated This flag has to be cleared by the software be controlled separately The interrupt flag has to be cleared by the software changed from DDC1 to DDC2 Flags except the INTR have to be cleared by the software INTR flag is cleared by hardware This flag is cleared by hardware May 2001 ver1 1 hynix HMS9xC7132 HMS9xC7134 0 and Timer1 interrupt 0 and Timer interrupts are generated by and TF1 These flags are cleared by the internal hardware which are set by an overflow of their respective Timer Counter registers except for Timer0 in mode3 Timer2 interrupt Timer2 interrupt is generated by TF2 which is set by an overflow This flag has to be cleared by the software of Timer2 All of the bits that generate interrupts can be set or cleared by software with the same result as though it had been set or cleared by hardware That is interrupts can be generated or pending interrupts can be cancelled in software Interrupt IE IEA IP IPA Priority Sources N Timer1 o o o 5 c o n en A gt 5 o gt VSYNC Not used Timer2 Global Enable Figure 9 1 Interrupt system May 2001 1 1 25 HMS9xC7132 HMS9xC7134 9 2 Interrupt Enable structure E
86. s still free to the system Nevertheless the effect of the post increment just ap plies to the part related to DDC1 operation In other words the system program is still able to address the lo cations from 128 to 255 in the RAM buffer through MOVX com mand but without the facility of the post increment ex In case of accessing 200 of the RAM Buffer MOV 200 MOVX A RO Figure 16 3 Transmission protocol in DDC1 interface 16 3 DDC2B protocol DDC2B is constructed base on Philips I2C interface However in the level of DDC2B PC host is fixed as the master and the mon itor is always regarded as the slave Both master and slave can be operated as a transmitter or receiver but the master device deter mines which mode is activated In this protocol address pointer 18 also used According to DDC2B specification AO for write mode and Al for read mode are assigned as the default address of moni 46 tors The reception of the incoming data in write mode or the updating of the outgoing data in read mode should be finished within the specified time limit If software in the slave s side cannot react to the master in time based on I2C protocol SCL pin can be stretched low to inhibit the further action from the master The transaction can be proceeded in either byte or burst format May 2001 ver1 1 hynix HMS9xC7132 HMS9xC7134 DDC Interrupt vector address SWENB 0i 003BH i Check Mode flag in DDCCO
87. ssing in the following stages the HSYNC polarity correction circuit is able to convert the input sync signals to positive polarity signals in all situations This cor rection is achieved by the aid of HPOL and HP 19 3 Vertical polarity correction The purpose of the vertical polarity correction is similar to the horizontal polarity correction To get the correct resultafter pow 19 4 Vertical sync separation This block separates the vertical sync from a composite sync sig nal At approximately 1 4 of each HSYNC line the logical level is latched This yields a slightly delayed vertical sync signal Special precautions have been taken to suppress equalizing puls 60 HPOL and HP are only settled down in several horizontal scan ning lines or a few milliseconds after power on or timing mode change er on or a timing mode change at least 5 frames is needed es when present and to allow both polarities of the composite sig nal The format of the composite sync signal can be standard as given in Figure 19 2 or can be one of the non standard format as given in Figure 19 3 May 2001 ver1 1 HMS9xC7132 HMS9xC7134 hynix OONASA LINOLVd 2 OONASH JONXLNOO AAS NOLLOH LHd ONASA TOdOA H dA SH3dA TOdA dA TOdOH AH dH TOdH dH YOLVAANAD NOILOAL4A ONASH ONASH osueyo ONASA ONASH SH3dH TOdA TOdH dA dH W
88. t flag This bit is set when the master loses the bus contention Otherwise this bit is reset ACK REP Acknowledge response flag This bit is set when the receiver transmits the not acknowledge signal This bit is reset when the receiver transmits the acknowledge signal Slave mode flag This bit is set when the SIO plays role in the slave mode Otherwise this bit is reset BBUSY Bus busy state flag This bit is set when the bus is being used by another master Otherwise this bit is reset Table 17 5 Description of SXSTA Data Shift Register SXDAT S1DAT S2DAT SxDAT contains the serial data to be transmitted or data which has just been received The MSB bit7 is transmitted or received first Le data shifted from right to left 7 6 5 4 3 2 1 0 SxDAT7 SxDAT6 SxDAT5 SxDAT4 SxDAT3 SxDAT2 SxDATI SxDATO Table 17 6 Serial data shift register Addressing Register SXADR This 8 bit register may be loaded with the 7 bit slave address to which the controller will respond when programmed as a slave receive transmitter 7 6 5 4 3 2 1 0 SLA6 SLAS SLA4 SLA3 SLA2 SLA1 SLAO ER Table 17 7 Address register SLA6 to SLAO Own slave address May 2001 1 1 53 hynix HMS9xC7132 HMS9xC7134 17 2 Programmer s Guide for 12C and DDC2 The serial I O and DDC Interface has operates in 4 modes Master transmitter Slave transmitter Master receiver Slave receiver 17 2 1 Master transmitter mode 1 Read 5 5
89. ter WDT KEY Since the WDT is automatically enabled while the proces sor is running the user only needs to be concerned with servicing it The 19 bit counter overflows when it reaches 524288 3FFFH The WDT increments once every machine cycle hynix This means the user must reset the WDT at least every 524288 machine cycles 524ms 12MHz To reset the WDT the user must write 01EH and then to WDTRST WDTRST is a write only register The WDT count cannot be read or written The watchdog timer is controlled by the watchdog key register WDTKEY Only pattern 01010101 55 disables the watch dog timer The rest of pattern combinations will keep the watch dog timer enabled This security key will prevent the watchdog timer from being terminated abnormally when the function of the watchdog timer is needed In Idle mode the oscillator continues to run To prevent the WDT from resetting the processor while in Idle the user should always set up a timer that will periodically exit Idle service the WDT and re enter Idle mode 7 6 5 4 3 2 2 0 WDTKEY7 WDTKEY6 WDTKEY5 WDTKEY4 WDTKEY3 WDTKEY2 WDTKEY1 WDTKEYO Table 14 1 Watchdog timer key register WDTKEY RESET VALUE 00000000B BIT SYMBOL FUNCTION WDTKEY7 Enable or disable watchdog timer 7100 to 01010101 55 disable watchdog timer WDTKEYO others enable watchdog timer Table
90. th 12 bit accuracy fSH 12MHz fSV 125 2 Hsync and Vsync polarity Hsync and Vsync presence needed for implementing the VESA DPMS standard Integrated composite sync separation Integrated signal generators for generating Free running horizontal and vertical sync pulses Clamping pulse Back porch Front porch Pattern signal white picture black picture cross hatch and inverse cross hatch Special option Missing sync pulse insertion measured parameters are stored in Special Function Register such that the data is available at any time The block diagram of the complete sync processor is given in Figure 19 1 19 1 Sync input signals The sync inputs are able to handle standard TTL level sync sig nals From Figure 19 1 it can be seen that both the HSYNCin and SOGin inputs accept composite sync signals The HSYNCin and VSYNCin input is meant to be connected to the Hsync and Vsync of the VGA cable while SOGin input is meant to be connected to a sync slicer in order to handle Sync On Green at the video input This last signal should have a TTL level also The selection be tween the HSYNCin and the SOGin inputs as well as the selec tion between the VS YNCin and separated Vsync can be done via software Select Flag Signal to detector HSEL 0 HSYNCin 1 SOGin VSEL 0 VSYNCin 1 Separated VSYNC Table 19 1 Sync Input selection 19 2 Horizontal polarity correction In order to simplify the proce
91. ther 00H or FFH the PWM output can be retained at a constant HIGH or LOW level respectively with PVMLVL 0 The PWM outputs PWMO to PWM7 register share the same pins as Port2 2 Port2 7 Port3 4 and Port3 5 respectively Selection of the pin function as either a PWM output a Port line or the other function is achieved by using the appropriate value of P2SF register The repetition frequency fPWM at a PWM output is given by fPWM fOSC 2 x 256 1 6 4 3 2 1 0 PWMLVL PWM6CFG PWMSCFG PWM3CFG PWM2CFG PWMICFG PWMOCFG Table 18 1 PWM control register PWMCON 0A1H SYMBOL FUNCTION 7 PWMLVL Polarity selection of the PWMs 0 PWM outputs are not inverted 1 PWM outputs are inverted PWM6CFG to PWMOCFG 0 open drain type 1 push pull type Output type selection of the PWMs Table 18 2 Description of the PWMCON bits May 2001 ver1 1 57 HMS9xC7132 HMS9xC7134 18 2 Dynamic PWM There two dynamic PWMs in the HMS9xC7132 The DP WMs can be used to generate various waveform by software pro gramming and are used to achieve geometric compensation by generating a parabola output waveform which is synchronized with VSYNCin signal for pin trap bow tilt vertical linearity or focus compensation in monitor system This is achieved by utilizing timer2 The low 8 bit in timer2 is used as 8 bit counter for PWM signal and the high 8 bit in timer2 is used to decide the number
92. this bit is set an acknowledge low level SDA is returned during the acknowledge clock pulse on the SCL line when Own slave address is received A data byte is received while the device is programmed to be a Master Receiver A data byte is received while the device is a selected Slave Receiver When this bit is reset no acknowledge is returned SIO release SDA line as high during the acknowledge clock pulse These two bits along with the CR2 bit determine the serial clock frequency when SIO is in the Master mode Table 17 2 Description of the SxCON bits Table 17 3 Selection of the serial clock frequency SCL in Master mode of operation 52 May 2001 ver1 1 hynix Serial Status Register SXSTA SxSTA is a read only register The contents of this register may be used as a vector to a service routine This optimized the response time of the software and consequently that of the I2C bus The status codes for all possible modes of the I2C bus interface are given Table 1 6 5 4 3 2 1 0 5 INTR TX MODE BBUSY BLOST ACK REP Table 17 4 Serial status register SXSTA S1STA 0D9H S2STA 0DDH SYMBOL FUNCTION ES General Call flag STOP STOP flag This bit is set when a STOP condition was received INTR Interrupt flag This bit is set when a SIO interrupt is requested TX MODE Transmission mode flag This bit is set when the SIO is a transmitter Otherwise this bit is reset BLOST Bus los
93. tion 0 1 pin 24 has SDA1 out function The selection of the pin function 0 P1SFSO 0 pin 25 has P1 0 function 0 1 pin 25 has SCL1 out function Table 11 2 Description of the P1SFS bits May 2001 1 1 33 HMS9xC7132 HMS9xC7134 P2SFS Port2 special function selection register 7 6 5 4 hynix 3 2 2 0 P2SFS7 P2SFS6 P2SFS5 P2SFS4 P2SFS3 P2SFS2 P2SFS1 25 50 Table 11 3 P2SFS bits 92H BIT SYMBOL FUNCTION RESET P2SFS7 The selection of the pin function 0 pin 34 has 2 7 function 1 pin 34 has PWMB function P2SFS6 The selection of the pin function 0 pin 35 has P2 6 function 1 pin 35 has PWMA out function P2SFS5 The selection of the pin function 0 pin 36 has P2 5 function 1 36 has PWM3 out function P2SFS4 The selection of the pin function 0 pin 37 has P2 4 function 1 pin 37 has PWM2 out function P2SFS3 The selection of the pin function 0 pin 38 has P2 3 function 1 pin 38 has PWM1 out function P2SFS2 The selection of the pin function 0 pin 1 has P2 2 function 1 1 has PWMO out function P2SFS1 The selection of the pin function 0 pin 2 has P2 1 function 1 2 has DPWM out function 25 50 The selection of the pin function 0 pin 3 has P2 0 function 1 3 has
94. tor configuration The circuitry between XTAL1 and XTAL2 is basically an inverter biased to the transfer point Either a crystal or ceramic resonator can be used as m the feedbackel T deren Main clock Minimum instruction cycle time e feedback element to complete the oscillator circuit Both are ain ex NOP fex 12clock is needed operated in parallel resonance 12MHz 105 XTALI is high gain amplifier input and XTAL2 is the out put To drive the HMS9xC7132 externally XTAL1 is driven 10 16MHz External clock Figure 12 1 Oscillator configuration ideal standard 10 C 10uF Recommanded reset IC lt R 42V reset Vy reset ZZ CZ 36 May 2001 ver1 1 hynix 13 RESET There are three ways to invoke a reset and initialize the HMS9xC7132 Via the external RESET pin Via the Watchdog Timer overflow Via low VDD voltage reset HMS9xC7132 HMS9xC7134 Each reset source will cause an internal reset signal active The CPU responds by executing an internal reset and puts the internal registers in a defined state RSTOUT Figure 13 1 The reset mechanism 13 1 External reset The reset pin RESET is connected to a Schmitt trigger for noise reduction A reset is accomplished by holding the RESET pin LOW for at least 2 machine cycles 24 system clock while the oscillator is running
95. ty on VSYNC is ignored Interrupt Request Bit This bit is set by H W when DDC interface switches from DDC1 to DDC2 i e The voltage transient from high to low is observed on SCL1 pin This bit should be cleared 1 SWHINT by S W in interrupt service routine R W 1 Interrupt request is pending 0 No interrupt request DDC mode indication bit This bit will be set by H W when the voltage transient from high to low is observed on SCL1 pin Once mode changes into DDC2 mode the mode is reserved until pow 0 MO er is off R W 0 DDC1 is set 1 DDC2 is set Table 16 2 Description of the DDCCON bits May 2001 1 1 43 HMS9xC7132 HMS9xC7134 DATA register for transmission DDCDAT 0D5H 8bit read and write register Indicates DATA BYTE to be transmitted in DDC1 proto col Address pointer for DDC interface DDCADR 0D6H 8bit read and write register Address pointer with the capability of the post incre ment After each access to RAMBUF register either by software or by hardware DDC1 interface the content of this register will be increased by one It s available 44 hynix both in DDC1 DDC2 DDC2B DDC2B and DDC2AB and system operation Host type detection The detection procedure conforms to the sequences proposed by VESA Monitor Display Data Channel DDC specification The monitor needs to determine the type of host system DDC1 or OLD type host

Hynix HMS9xC7132, HMS9xC7134 User`s Manual

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