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Example User Manual

1. Device 240 gt xc6vix240t 2ffg1156 365 gt xc6vlx365t 2ffg1156 64 www acromag com XMC 6VLX USER S MANUAL Special note regarding the SG projects SG stands for Scatter Gather and is a feature of the Xilinx AXI CDMA core Because of a limitation in the Xilinx AXI Interconnect it is not possible to connect buses larger than 32 bits to the PCle control bus where PCle registers reside AXI PCle control bus is an AXI4 Lite protocol and can only support single 32 bit transactions The AXI CDMA bus is an AXI4 Full protocol capable of bursts of various lengths see AMBA AXI Protocol Specification for further details For some users it may be desirable to use Scatter Gather mode in which case a descriptor list can be set up in QDR memory to move data to or from host memory In order for the AXI CDMA core to move data from the QDR memory to or from host memory it must first write the base address translation registers in the AXI PCle core with an address translation In this mode the AXI CDMA would need to be connected to the AXI PCle Control Bus but the data width of the CDMA bus must be set to 32 bits However if Scatter Gather is not essential it can be disabled and the data width of the AXI CDMA can be set to 64 bits or larger to improve through put Acromag includes both Scatter Gather and no Scatter Gather versions of the projects to illustrate both examples Acromag Inc Tel 248 295 0310 65
2. Make Target Radek memory_config h memory_ranges struct memory_range_ n_memory_ranges int Es system xml This file is automatically generated ba a include memory config h O 6 6 struct memory range_s memory ranges microblaze 0 d bram cntlr memory wi 1 DDR3_SDRAM axi_v6_ddrx 0x80000000 1073741824 int n memory ranges 1 m J El Problems A Tasks E Console 8 E Properties ro Terminal 1 C Build lwip_echo_server_dual Copyrignt cy 1995 2012 XILINX 2 05 Dry ALL Tignts reservea INC R Command Line elfcheck hw EDK_hw_platform system xml pe microblaze_0 lwip_echo_server_dual elf ELF file lwip_echo_server_dual elf elfcheck passed Finished building lwip_echo_server_dual elf elfcheck 97 www acromag com XMC 6VLX USER S MANUAL Run the Acromag PCle6VLX demo program Enter 2 to Locate Choose board E E PCle6VLXDemo exe GULX Main Menu Demo instructions Locate Choose board Exit Enter selection PCIe 6ULX Demonstration Program Enter the appropriate number to select the XMC V6 variant that you have installed a PCle6VLXDemo exe Demo instructions Locate Choose board Exit Enter selection 2 1 6ULK246F 2 6ULX365F 3 6ULR365 Select board to open PCIe 6ULX Demonstration Program Acromag Inc Tel 248 295 0310 98
3. www acromag com XMC 6VLX USER S MANUAL Enter Y to indicate the FPGA is configured with the Acromag example design Y a PCle6VLXDemo exe l oy xX 1 6ULK246F 2 6ULX365F 3 6ULK365 Select board to open 1 1 6ULK24 F board lt s gt found 6ULR246F board opened Is the FPGA configured with an Acromag example design CY Select function 4 Flash commands a 1 6ULK24 F board lt s gt found 6ULR246F board opened Is the FPGA configured with an Acromag example design CY 6ULK Main Menu Demo instructions Locate Choose board Interrupt Configuration Flash commands Raw memory access View status information Example Design Board ID code BBBBBBA3 QDRII SRAM menu DMA transfers Front Rear and P16 1 0 menu Display PCI configuration registers Exit Enter selection Acromag Inc Tel 248 295 0310 99 www acromag com XMC 6VLX USER S MANUAL If BPI is not the currently selected FLASH then select function 1 Toggle selected flash device Select 8 Write code file to flash T PCle6VLXDemo ex Example Design Board ID code BBBBBBA3 QDRII SRAM menu DMA transfers Front Rear and P16 1 0 menu 99 Exit Enter selection 4 6ULK Flash menu Toggle selected flash device Flash status details Clear flash status Read flash word Read flash block Write flash word Write flash block Write code file to flash Erase flash block E
4. m El console Errors 13 Warnings TQ Findin Fies Results Acromag Inc Tel 248 295 0310 85 www acromag com XMC 6VLX USER S MANUAL After the place and route process is completed the hardware definition files used by SDK will need to be updated Click on system_i in the Heirarchy pane and notice the processes available in the process pane Double click on Export Hardware to SDK without Bitstream E File Edit View Project Source Process Tools Window Layout Help E i ee 7 z E al a DRA xobxio cana AASB Aiae naler eer Design D0Sx o e pr ea O e 3 e E Summary Be MESA Seien al E 10B Properties fencevexzsorxise a Hierarchy o B Module Level Utilization E XMC 6VLX240F v E Timing Constraints E lp a o ut Report ice xc vinoaot 211156 EN o a E Clock Report si 5 E h aurora_8b10b_i aurora_8b10b_v5_3_example_design MAPPED C XN h Flash_comp FLASH FLASH_arch C XMC V6 source flash vhd e h Rear 1O RearLVDS RearLVDS_arch C XMC V6 source RearLVDS vhd E fh Front_IO FrontLVDS FrontLVDS_arch C XMC V6 source FrontLVDS E 1 P16_10 P16_LVDS P16_LVDS_arch C XMC V6 source P16_LVDS vhi Fig sysmon_wiz_inst sysmon_wiz_v2_1 xilinx CAXMC V6 sourcelsys Fa C XMC V6 source system ucf m P gt T NoProcesses Running PY Processes system_i system gje Design
5. Silicon Labs provides royalty free virtual COM port drivers which permit the CP2103GM USB to UART bridge to appear as a COM port to host computer communications application software for example HyperTerm or TeraTerm The COM port device driver must be installed on the host PC prior to establishing communications with the XMC 6VLX With power to the XMC 6VLX board install the CP2103GM COM port Drivers from www silabs com On the host system set the device manager properties My Computer gt Properties gt Device Manager Right select on USB to UART Bridge gt select Properties Under the Port Setting tab gt Select Advanced gt Set the COM port to an open Com Port setting Using HyperTerm or TeraTerm select the same COM port and set the Baud rate to 9600 16MB Platform Flash A 16 MByte 128Mb Xilinx XCF128X FTG64C Platform Flash XL device is used with an onboard 48 MHz oscillator to configure the Virtex 6 FPGA in less than 100ms from power valid This is required by the PCI Express Card Electromechanical Specification This allows the PCle interface to be recognized and enumerated when plugged into a host PC To achieve the fastest configuration speed the FPGA mode pins are set to Slave SelectMap MO 0ff M1 On M2 On and the onboard 48 MHz clock source external to the FPGA is used for configuration Configuration DIP switch 1 switch 4 controls the 48 MHz oscillator enable switch 4 Off enables the oscillator Also see t
6. Acromag Inc Tel 248 295 0310 14 www acromag com XMC 6VLX USER S MANUAL SFP Module Connector Table 2 4 Board Front SFP Module Contact definition in Symbol Pin Description P 1 VeeT Module Transmitter Ground 2 Tx_Fault Module Transmitter Fault 3 Tx_Disable Transmitter Disable 4 SDA 2 wire Serial Interface Data Line 5 2 wire Searil Interface Clock 6 Module Absent 7 Rate Select 8 Receive Loss of Signal Indication 9 Module Receiver Ground 10 Module Receiver Ground 11 Module Receiver Ground 12 RD O Receiver Inverted Data Output 13 Receiver Non Inverted Data Output 14 Module Receiver Ground 15 Module Receiver 3 3 V Supply 16 Module Transmitter 3 3 V Supply 17 Module Transmitter Ground 18 TD Transmitter Non Inverted Data Input 19 TD Transmitter Inverted Data Input 20 VeeT Module Transmitter Ground Non Isolation Considerations The board is non isolated since there is electrical continuity between the logic and field I O grounds As such the field I O connections are not isolated from the system Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections Acromag Inc Tel 248 295 0310 15 www acromag com XMC 6VLX USER S MANUAL 3 0 PROGRAMMING INFORMATION This Section provides the specific information necessary to program and operate the board GETTING STARTED
7. FUNCTION Register 0 This bit is reserved for future definition and will always return zero Indicates tail pointer mode is enabled to the Scatter Gather Engine This bit is fixed to 1 and always read as 1 when Scatter Gather is included If the CDMA is built with Scatter 1 Gather disabled Simple Mode Only the default value of the port is 0 O Tail Pointer Mode is Disabled Tail Pointer Mode is Enabled Soft reset control for the AXI CDMA core Setting this bit to a T causes the AXI CDMA to be reset Reset is accomplished gracefully Committed AXI4 transfers are then completed 2 Other queued transfers are flushed After completion of a soft reset all registers and bits are in the Reset State O Reset Not in Progress Reset in Progress This bit controls the transfer mode of the CDMA Setting this bit to a 1 causes the AXI CDMA to operate in a Scatter Gather mode Note This bit must only be changed when the CDMA engine is IDLE CDMA Status bit 1 1 Changing the state of this bit at any other time has undefined results Note This bit must be set to a O then back to 1 by the software application to force the CDMA Scatter Gather engine to use a new value written to the CDMA Current Descriptor Pointer register Note This bit must be set prior to setting Bit 13 of this CDMA Control register 0 Simple DMA Mode Scatter Gather Mode 11 4 Reserved Interrupt on Complete Interrupt Enable When set to 1 it al
8. Float this tab above or dock it within the main main window Configuration Platform Cable USBI 6 MHz usb hs Acromag Inc Tel 248 295 0310 90 www acromag com XMC 6VLX USER S MANUAL Double click on Generate File in the iMPACT Processes pane This process will create the file XMC 6VLX240F mcs DO Bas 2 iMPACT Flows cy dal Boundary Scan 0x0000_0000 EA SystemACE Revision z BPI Parallel Daisy Chain Create PROM File PROM File Formatter WebTalk Data xef128x xc6vix240t system_top bit b erations are m Generate File 0x007F_FFFF PROM File Formatter Auto Selcet false Number of Revisions 1 Number of PROMs 1 PROM Name xcf128x PROM Size 16777216 Bytes Revision 0 0 1 device s chain Device 0 pn xc6v1x240t fn system_top bit END of Report Project C XMC V6 XMC 6VLX240F iMPACT XMC 6VLX240F ipf loaded m 4 8 Errors E Warnings Acromag Inc Tel 248 295 0310 91 www acromag com XMC 6VLX USER S MANUAL Click on the Boundary Scan tab File Edit View Operations Output Debug Window Help DOHA BEY Sa FN iMPACT Flows O x Sa Boundary Scan SystemACE 3 Create PROM File PROM File Formatter a WebTalk Data 0x0000_0000 T Revision xcf128x IMPACT Processes COVALI system_top bit Available Operations are Gene
9. Acromag Inc Tel 248 295 0310 The XMC 6VLX board is shipped with the user programmable Xilinx FPGA code stored in the Platform Configuration flash memory U1 Upon power up the XMC 6VLX will automatically configure the FPGA with the example design code stored in flash As a first step become familiar with the XMC 6VLX with the example code supplied by Acromag The board will perform all the functions of the example design as described in this manual The Example Design Memory Map section gives a description of the I O operations performed by the example design It will allow testing of PCle interface read write of QDRII SRAM all digital I O ports interrupts testing of both SFP Ports P16 Aurora loopback and DMA operation It is strongly recommended that you become familiar with the board features by using the example design as provided by Acromag CAUTION Do not attempt to reconfigure the flash memory until after you have tested and become familiar with the XMC 6VLX as provided in the example design After you are familiar with the XMC 6VLX and have tested it using the example design you can move on to step 2 Here you will modify the example design VHDL code slightly The Xilinx Platform Configuration flash must be overwritten to test your code Once the flash is erased you will not be able to go back to the example design by simply powering down and restarting the board If your code does not function as desired you may need to
10. PIN 18 E PIN 36 CHAMP 0 8mm PLUG CONNECTOR TYCO AMP 787131 2 PIN 26 SHIELDED BACKSHELL Acromag Inc Tel 248 295 0310 110 www acromag com XMC 6VLX USER S MANUAL GROUND SHIELD ON CABLE CONNECTS TO P1 AND P2 OF SHIELDED BACKSHELLS BROWN GRA VIOLET BROWN BROWN VIOLET Bi BROWN BROWN BLUE GREEN BROWN BROWN GREEN OWIBROWN BROWN YELLOW ORANGE BROWN BROWN ORANGE PINK BROWN PINK BROWN BROVN PINK gt a O A BROVYN PINK GRAY TAN GRAY TAN AN GRA Ce ee ee RS AN GRA VIOLET TAN ANMIOLE A A A A A AN VIO BLUE TAN BLUE TAN ANIB gt ENS AREY ED LES AN B GREEN TAN GREEN TAN AN GREEN lt gt gt a gt gt lt a AN GR YELLOW TAN YELLOWI TAN AN YELLOW AN YELLOW ORANGE TAN ORANGE TAN dl j WHITEIGRAY KK MVHITE GRAY NHITE GRA NHITE GRA BLUE WHITE BLUE WHITE WHITE BLUE A MITE BLUE WHITE GREEN A _WHITE GREEN WHITE YELLOW le E gt A a al X nN aB aS af v8 ORANGE WHITE ORANGE WHITE WHITE ORANGE a WHITE ORANGE WHITE PINK KO EK WWHITE PINK BROWN WHITE BROWN WHITE WHITE BROWN WHITE BROWN TAN WHITE ANTE WHITE TAN PO WHITE TAN Acromag Inc Tel 248 295 0310 111 www acromag com XMC 6VLX USER S MANUAL SFP to SFP Cable Acromag provides a 1 meter cable that connects one SFP to another SFP The cable is copper Twin ax and connects one SFP module to another The Acromag part number is 5028 449 SPECIFICATIONS Cable Length 1 0meter Gender Male
11. CPU write of 1 clears this bit to O o No Delay Interrupt Delay Interrupt Active Interrupt on Error When set to 1 this bit indicates an interrupt event has been generated due to an error condition If the Interrupt on Error bit 14 of the CDMA Control register 14 1 an interrupt is generated from the AXI CDMA A CPU write of 1 clears this bit to 0 o No Error Interrupt 1 Error Interrupt Active 15 Reservered Interrupt Threshold Status This field reflects the current interrupt threshold value in the Scatter Gather Engine Interrupt Delay Time Status This field reflects the current interrupt delay timer value in the Scatter Gather Engine 12 23 16 31 24 Acromag Inc Tel 248 295 0310 30 www acromag com XMC 6VLX USER S MANUAL CDMA Current Descriptor Pointer Register Read Write BARO 0x000A0008 This register provides the Current Descriptor Pointer for the AXI CDMA Scatter Gather Descriptor Management Table 3 11 COMA Current Bit s FUNCTION Descriptor Pointer Register Writing to these bits has no effect and they are always read as zeros 5 0 Current Descriptor Pointer This register field is written by the software application in Scatter Gather Mode to set the starting address of the first transfer descriptor to execute for a Scatter Gather operation The address written corresponds to a 32 bit system address with the least significant 6 bits truncated This r
12. Table 3 15 CDMA Bytes to Bit s FUNCTION Transfer Register Bytes to Transfer This register field is used for Simple DMA transfers and indicates the desired number of bytes to DMA from the Source Address to the Destination Address A maximum of 8 388 606 bytes of data can be specified by this field for the associated transfer Writing to this register also 22 0 initiates the Simple DMA transfer Note A value of zero 0 is not allowed and causes a DMA internal error to be set by AXI CDMA The software application should only write to this register when the AXI CDMA is Idle 31 23 Writing to these bits has no effect and they are always read as zeros Simple CDMA Programming Example 1 Verify the CDMA is idle Read CDMA Status register bit 1 and logic 1 2 Program the CDMA Control register bit 12 to the desired state for interrupt generation on transfer completion 3 Write the desired transfer source address to the Source Address register at 0xA0018 The transfer data at the source address must be valid and ready for transfer If we were to select the QDR memory as the source and wanted to start a move of data from the beginning of QDR we would write 0x30000000 to the Source Address register at OxA0018 4 Write the desired transfer destination address to the Destination Address register at OxA0020 If the destination is the system memory then the following is required a Given physical address
13. 13 DP12 DP12 S6_P DP13 DP13 S7_P 14 GND GND S4_N GND GND S5_N 15 DP14 DP14 s4 P DP15 DP15 S5_P 16 GND GND S2_N GND GND S3_N 17 DP16 DP16 s2 P DP17 DP17 S3_P 18 GND GND SOG_N GND GND S1_N 19 DP18 DP18 SOG_P DP19 DP19 S1_P As LVDS signal pairs the signals can be grouped to match the ANSI VITA 46 0 X38s pattern map A total of 19 differential signal pairs are provided These differential signal pairs connect to column C and F of the P16 XMC connector as shown in the following table For example S3_P and S3_N form a signal pair There are two global clock differential pairs available SOG_P SOG_N and S18G_P S18G_N The P identifies the Positive input while the N identifies the Negative input This XMC P16 Secondary connector is a 114 pin Samtec ASP 103614 05 connector The connector complies with the ANSI VITA 42 3 2006 Acromag Inc Tel 248 295 0310 12 www acromag com XMC 6VLX USER S MANUAL Rear P4 Field I O Connector Table 2 2 Board Rear Field I O Pin Connections The example design implements 2 5volt LVCMOS I O to the rear connector Alternatively 2 5volt LVDS I O can be used on the rear connector The rear I O P4 connector connects directly to the user programmable FPGA The VCCO pins are powered by 2 5 volts and thus will support the 2 5 volt lOStandards The IOSTANDARD attribute can be set in the user constraints file UCF The example design defines the Rear P4 I O to LVCMOS25 low vo
14. Bus RON 108 AMC 6VLX BLOCK DIAGRAM si isscsseccistscccoaisessedswedsecacicbachessnncedesceusnedcntbavcoscssacessevestess thers 109 ACCESSORIES 0 neta nica 110 VA DEI Cable oss coincida 110 SEP t0 SEP Call E E E EE EE A E EE E E EE E 112 1000BASE T Copper SFP Transceiver sssssosessssesosssosssessessssessssosssosssossesosssosesesssessssessso 113 2 125 Gb s Short Wavelength SFP Transceiver ooooconcccnonononononononononononononononononononanonos 114 CERTIFICATE OF VOLATILOY iii 116 REVISION HISTORY usina Riaan 117 Acromag Inc Tel 248 295 0310 4 www acromag com XMC 6VLX USER S MANUAL All trademarks are the property of their respective owners IMPORTANT SAFETY CONSIDERATIONS You must consider the possible negative effects of power wiring component sensor or software failure in the design of any type of control or monitoring system This is very important where property loss or human life is involved It is important that you perform satisfactory overall system design and it is agreed between you and Acromag that this is your responsibility The information of this manual may change without notice Acromag makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current th
15. Front Panel Field I O Connector The front panel provides access to a 36 pin VHDC connector and two SFP port connectors The VHDCI connector provides interface to JTAG USB and 26 single ended or 13 differential I O signal pairs Two of the signal pairs are routed to global clock pins on the Virtex 6 device The 26 front I O signals connect directly to the user programmable FPGA The VCCO pins are powered by 2 5 volts and thus will support the 2 5 volt lOStandards The IOSTANDARD attribute can be set in the user constraints file UCF The example design defines the Front I O to LVCMOS25 low voltage CMOS in the user constraints file The tables included in the Front Input Data Register and Front Output Data Register sections can be used to map the LVCMOS signal to the signal names given in the table below The Front I O can alternatively be defined for LVDS_25 Low Voltage Differential Signaling in the user constraints file The 2 5 volt lOStandards available are listed in the Virtex 6 User Guide available from Xilinx Table 2 3 Board Front VHDCI Field I O Pin Connections The example design implements 2 5volt LVCMOS I O to the front connector Alternatively 2 5volt LVDS I O can be used on the front connector FIO9_N FIO11_GCLK_N 33 34 N A USB_VBUS from host sys This connector is a 36 pin female receptacle header SAMTEC VHDCR 36 01 M RA or equivalent which mates to the male connector
16. No CDMA Slave Errors CDMA Slave Error detected CDMA Engine halts DMA Decode Error This bit indicates that an AXI decode error has been received by the AXI DataMover This error occurs if the DataMover issues an address that does not have a mapping assignment to a slave device This error condition causes the AXI CDMA to halt gracefully The CDMA Status register bit 1 is set to 1 when the CDMA has completed shut down A reset soft or hard must be issued to clear the error condition o No CDMA Decode Errors CDMA Decode Error detected CDMA Engine halts 7 Reserved Scatter Gather Internal Error This bit indicates that an internal error has been encountered by the Scatter Gather Engine This error condition causes the AXI CDMA to gracefully halt The CDMA Status register bit 1 is set to 1 when the CDMA has completed shut down A reset soft or hard must be issued to clear the error condition 0 No Scatter Gather Internal Errors Scatter Gather Internal Error CDMA Engine halts Scatter Gather Slave Error This bit indicates that an AXI slave error response has been received by the Scatter Gather Engine during an AXI transfer transfer descriptor read or write This error condition causes the AXI CDMA to gracefully 9 halt The CDMA Status register bit 1 is set to 1 when the CDMA has completed shut down A reset soft or hard must be issued to clear the error condition 0 No Scatter Gather Slave Errors Scatter Gather Slave Err
17. Pairs 16x1 X8 34 1 0 x4 x4 hardware amp hardware hardware example 2 Global example example design Clock design design x4 PCle Pairs Aurora Aurora Gen 1 30 LVDS pairs amp 2 Global Clock Pairs Acromag Inc Tel 248 295 0310 109 www acromag com XMC 6VLX Accessories VHDCI Cable DESCRIPTION SPECIFICATIONS SPRING LATCH SHIELDED BACKSHELL TYCO AMP 749889 3 USER S MANUAL Acromag provides a cable that brings the 36 pins of the VHDCI front I O connector out to a 50 pin SCSI connector The Acromag part number is 5025 921 See Table 2 3 Board Front VHDCI Field I O Pin Connections SCSI 2 to CHAMP 0 8mm Cable Assembly Shielded The cable assembly uses a 25 paired round shielded jacketed flat cable 50 conductors total with a 50 position SCSI 2 male connector with spring latch at one end and a 36 position CHAMP 0 8mm plug connector with screw latch at the other end The cable length is 2 meters 6 56 feet Voltage 30VAC Current 1 5 Amperes for single circuit 0 5 amperes at 10 C 0 3 Ampere 100 energized per Champ 0 8mm Connector Operating Temperature Range 40 C to 85 C CABLE MADISON CABLE CORP 50KBK00004 OR 50KBK00012 OR 50KBK00013 OR PIN 50 HITACHI CABLE MANCHESTER 48711 50 SCSI 2 PLUG CONNECTOR TYCO AMP 749111 4
18. Scatter Gather engine is paused at a tail pointer pause point the Scatter Gather engine restarts descriptor execution at the next sequential transfer descriptor If the AXI CDMA is not idle writing to this register has no effect except to reposition the Scatter Gather pause point Note The software application must not move the tail pointer to a location that has not been updated with valid transfer descriptors The software application must process and reallocate all completed descriptors clear the completed bits and then move the tail pointer The software application must move the pointer to the last descriptor address it has updated 31 6 Acromag Inc Tel 248 295 0310 32 www acromag com XMC 6VLX USER S MANUAL CDMA Source Address Register Read Write BARO 0x000A0018 Table 3 13 CDMA Source Address Register This register provides the source address for simple DMA transfers by AXI CDMA Note if the QDR memory is the source the base address from which QDR memory starts is Ox30000000 If a location in system memory is the source address it must be set with the AXI aperture base address 0x01000000 the least significant 24 bits of the system memory address In addition the physical address of the location in system memory must be set in the Address Translation Register which is described in the PCle AXI Bridge Control section Bit s FUNCTION Source Address Register This
19. Slave le Target lt Initiator WConnected OUnconnected M Monitor YiProduction License paid A lLicense eval Qlocal 2 Pre Production M2Beta Development Superseded Discontinued Design Summary C System Assembly View ole Graphical Design View 08x 4 WARNING EDK 2342 Search path C XMC V6 pcores axi_to_qdr_ mc vi_00 a directly contains drivers direc 4 WARNING EDK 4164 No Processor Interconnect selected in current selection within Bus Interface Tab Show Sub S 4 m E Console aS warnings E Errors Acromag Inc Tel 248 295 0310 80 www acromag com XMC 6VLX USER S MANUAL The cacheable range address parameter of the microblaze configuration must also be updated Select the Bus Interfaces tab and then right click on microblaze_0 and select Configure IP from the pop up menu File Edit View Project Hardware Debug Window Help BS Ohi E E 7 IP Catalog 08x Bus Interfaces B a ES es La ga Name Bus Name IP Type axi_interconnect_O r axi_interconnect EDK Install ax_interconnect_1 Y axi_interconnect Analog 4 axi_interconnect_2 Y axi_interconnect 63 Bus and Bridge microblaze_0_dimb tir Imb_v10 Clock Reset and Interrupt i tir Imb_v10 Communication High Speed microblaze Communication Low Speed t am r bram_block DMA and Timer microblaze_0_d_bram_cntlr r Imb_bram_if_cntlr Debug microblaze_0_i_bram_cntlr Y Imb_bram_if_cntlr 1 FPGA Reconf
20. This connector provides 64 rear I O connections The rear I O P4 PMC connector connects directly to banks 25 and 35 of the FPGA Bank 25 and 35 Vcco pins are powered by 2 5 volts and thus will support the 2 5 volt lOStandards Refer to the Virtex 6 SelectlO User Guide available from Xilinx for more information on the lOStandards available The example design defines the rear I O with 2 5 volt LVDS e Maximum Recommended Clock Rate 150MHz 6 7ns clock period e Veco Supply Voltage oconcninncnicncononncnananos 2 5 volt e VOH Output High Voltage eee 1 602 volt e VOL Output Low Voltage occoccnococinnconnn 0 898 volt e VODIFF Differential Output Voltage 350m volt typical e VOCM Output Common Mode Voltage 1 25 volt typical e VIDIFF Differential Input Voltage 100m volt minimum e VICM Input Common Mode Voltage 0 3 volt min 1 2 volt typical 2 35 volt max Acromag Inc Tel 248 295 0310 106 www acromag com XMC 6VLX VHDCI FRONT I O Board Oscillators DDR3 Memory QDR II SRAM Memory USER S MANUAL This XMC module uses the 36 pin Samtec connector part number VHDCR 36 01 M RA which mates with industry standard VHDCI cable assemblies and the Acromag Virtex 6 EDK module for external USB JTAG and 13 differential I O or 26 single ended user signals Board Crystal Oscillators 125MHz U21 U31 Frequency Stability 0 00315 or 31 5ppm Board Crystal Osci
21. This will enable selection of the Platform flash device and disable selection of the BPI flash device Set DIP switch 2 and 3 to the ON position This will select Slave SelectMAP mode 2 Power Cycle the System with the XMC 6VLX module At power up the configuration file will automatically be loaded into the FPGA provided the DIP switch is set as described in the preceding step for configuration from Platform flash BPI Flash Xilinx Configuration The Byte wide Peripheral Interface BPI flash is recommended for MicroBlaze CPU program code storage The following is the general procedure for reprogramming the BPI flash memory 1 Set DIP switch 5 to the ON position This will enable selection of the BPI flash device and disable selection of the Platform flash device 2 See the Flash Configuration section for a description of the steps required to write new data or program code to the BPI Flash device Registers are provided in the FPGA Programming Memory Map to implement BPI flash erase and reprogram operations Acromag Inc Tel 248 295 0310 17 www acromag com XMC 6VLX USER S MANUAL PCle CONFIGURATION ADDRESS SPACE This board is a PCI Express Base Specification Revision v2 0 compliant PCle bus board The PCI bus is defined to address three distinct address spaces I O memory and configuration space This board can be accessed via the PCle bus memory and configuration spaces The card s configuration registers are initia
22. Utilities Manage Processor Design XPS sa Ga Static Timing E XPS Errors and Warnings E Platgen Messages LD Simgen Messages E Bitinit Messages E XPS Reports E Platgen Log File O Simgen Log File Bitlnit Log File L System Log File Es Errors and Warnings E Parser Messages Synthesis Messages E Translation Messages E Map Messages E Place and Route Messages Timing Messages 2 Bitgen Messages O Timing Report Design Properties Y Enable Message Filtering Optional Design Summary Contents F Show Clock Report E Show Failing Constraints E Show Warnings Show Errors Y Start Console Plataen Log File Thu Sep 2007 34 29 o 36 Warnings 8 new 0 49 Infos 2 2012 filtered new 0 filtered Simgen Log File Bitinit Log File Thu Sep 2009 29 47 o o 29 Infos 0 2012 new 0 filtered System Log File Number of Slice Registers 73 041 301 440 24 Number used as Flip Flops 72 219 Number used as Latches 580 Number used as Latch thrus o Number used as AND OR logics 242 Number of Slice LUTS 64 189 150 720 42 Number used as logic 53 269 150 720 35 voex Generating Report Number of warnings 0 Total time 4 mins 27 secs m Process Generate Post Place amp Route Static Timing completed suc
23. ainda 10 SFP tO SFP Calend iaa 10 1000BASE T Copper SFP Transceiver cococococoncnonononnnononononononononononono nono no nonnnn nono nono nn nono nnnnnnnnnnnnnnnnnnnnnnnnnnnnnns 10 2 125 Gb s Short Wavelength SFP Transceiver c cccssccssssecssecessecessecesesecssecessecessecsseeeessecesseecsuecssesecsaeesaes 10 2 0 PREPARATION FOR USE satis 11 Unpacking and Inspecting is sicisciscicsssccedssctssssavassccvescovossaveessccensesans sdevwssccuecesebdscees sdenessenean ess 11 Card Cage Considerations cccssscccsseeccsseeccssecccsscccsseccasescccsesecaseeccsessussseneeesecsesceasesees 11 BOardilinStallatiO TIN 11 Default Hardware Configuration cccccessccsccecsesssaeceeecscseseeaeseeeeecsesesaeseceesceesesaeeeeeeeceesnsaeseseesseeseaeaeees 11 P16 Secondary XMC CONMECION isien raaa eaa E aia e eaa REE a iiaei eiai 12 Rear P4Fieldl O COMMECKOR Galia nana ea a e A ei E E aor ENA ESS 13 Front Panel Field I O Connector ccccccccccccccssssesccscsseceseeesccseseesecseusecsesescesausesesesesueseseeseeasauseseeasuessnseseesags 14 SEP Module Connector nuiir esaeen enaa Geasase seaneecaaeeannevaeaaendsdeessesesdcheins taleeddgavaensensedsnsawensicacrsese 15 Non Isolation Considerations sssesssesosesesssesssessescsesceeecssecosecesscessessssscsesoseecssesosesosesesss 15 3 0 PROGRAMMING INFORMATION ssssssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nunnana 16 GETTING STARTED sess iu cesses ences
24. bit or 8 bit data transfers All channels of this register are fixed as output channels Table 3 33 BARO P16 Output Data Register Note that any registers bits not mentioned will remain at the default value logic low Acromag Inc Tel 248 295 0310 Register Bit Channel VHDL Name Schematic Name 0 0 P16 SO 0 P16_SIO18_GCLK_N 1 1 P16 SO 1 P16_SIO16 P 2 2 P16 SIO14 P 3 3 P16 SIO12 P 4 4 P16 SIO10 P 5 5 P16 SIO8 P 6 6 P16 SIO6 P 7 7 P16 SIO4 P 8 8 P16 SIO2 P 9 9 P16 SIOO GCLK P 10 10 P16 SIO17_N 11 11 P16 SIO15_N 12 12 P16 SIO13_N 13 13 P16 SIO11_N 14 14 P16 SIO9 N 15 15 P16 SIO7_N 16 16 P16 SIO5_N 17 17 P16 SIO3_N 18 18 P16 _SO 18 P16 SIO1 P 54 www acromag com XMC 6VLX BAR2 MEMORY MAP QDR Memory USER S MANUAL 16MB of QDR memory is provided on the XMC 6VLX board The 16MB QDR memory is provided as 2 Meg x 72 bits The QDR memory connects directly to the Virtex 6 FPGA using a 72 bits This allow for fast data transfer to and from this memory and the user application and the PCle bus This design allows for the user to maximize data throughput between the Field I O s and the controlling processor There is automatic DMA initiator available that will trigger upon a user set condition See AXI CDMA Registers for more information on DMA operation to and from QDR memory QDR Memory Read Write BAR2 0x0000000 to OxOOFFFFFF The QDR memory 16 Mega byte s
25. block Write code file to flash Erase flash block Erase flash chip Return to main menu Enter selection 99 Acromag Inc Tel 248 295 0310 101 www acromag com XMC 6VLX USER S MANUAL To summarize the bitstream in platform FLASH has been updated with the new hardware containing the relocated DDR3 SDRAM and the updated srec_bootloader program The BPI FLASH contains the updated Iwip_echo_server_dual program The srec_booltloader will load the Iwip_echo_server_dual into DDR3 SDRAM and execute it on power up Both programs will report their progress by writing messages to the serial port To view the progress messages displayed on power up a separate PC must be running a terminal emulator program such as hyper terminal connected to COMM3 The serial port parameters in the terminal emulator should be configured for 9600 baud 8 data bits 1 stop bit and no parity A USB cable must be connected from the XMC V6 USB port to the USB port on the separate PC The following progress message will be displayed in the terminal emulator when power is applied to the XMC V6 COMMS HyperTerminal File Edit View Call Transfer Help O a 6 085 Y Testing DDR3 Memory 32 bit test PASSED SREC Bootloader Loading SREC image from flash address 00000000 Executing program starting at address 90000000 lwIP TCP echo server TCP packets sent to port 6001 will be echoed back SFP1 Board IP 192 168 1 10 Netmask 299 299 299 0 Ga
26. bus Each of the devices U12 and U13 are 2 Meg x 36 bit 72Mb is size Both QDR device together total 144Mb or 18MBytes The QDRII interface is implemented in FPGA banks 13 22 23 32 and 33 DCI VRP N resistor connections are implemented on bank 22 DCI functionality in bank 23 is achieved in the UCF by cascading DCI between adjacent banks as follows CONFIG DCI_CASCADE 22 23 Acromag Inc Tel 248 295 0310 57 www acromag com XMC 6VLX Clock Generation USER S MANUAL On board termination devices are provided at the QDRII device for termination of the address and data as received from the FPGA Termination devices are also provided near the FPGA for QDRII data driven signals There are three FPGA fabric clock sources available on the board One 2 5V LVDS differential 200 MHz oscillator U23 is wired to the FPGA global clock input pins D11 and E11 The 200 MHz signal names are clk200_ref_p and clk200_ ref_n Another 2 5V LVDS differential 125 MHz oscillator U21 is wired to the FPGA global clock input pins K13 and K12 The 125 MHz signal names are sys_clk_fO_pandsys clk_f0O_n Another 2 5V LVDS differential 125 MHz oscillator U31 is wired to the FPGA MGT clock input pins H5 H6 and AD6 ADS The 125 MHz signal names are SFP_CLK_P and SFP_CLK_N Multi Gigabit Transceivers GTX MGTs SFP Module Connectors USB to UART Bridge The XMC 6VLX provides access to 18 MGTs e Eight 8 of the MGTs are wir
27. channel is low i e a O in the output channel data register A 1 bit means that an interrupt will occur when the output channel is high i e a 1 in the output channel data register Note that no interrupts will occur unless they are enabled by the Interrupt Enable Register Further the Interrupt Polarity Register will have no effect if the Change of State COS interrupt type is configured by the Interrupt Type Configuration Register The Interrupt Polarity register at the base address offset 0x301010 is used to control differential channels 0 through 3 as mapped in the Interrupt Enable Register For example channel 0 is controlled via data bit 0 Bits 4 to 31 are not used and will always read as 0 All bits are set to 0 following a reset which means that the output will cause interrupts when they are logic low provided they are enabled for interrupt on level Acromag Inc Tel 248 295 0310 50 www acromag com XMC 6VLX USER S MANUAL Rear Input Data Register Read Only BARO 0x301100 The rear I O can also be configured as differential channels with 2 global clock signal pairs Table 3 30 BARO Rear Input Data Register Note that any registers bits not mentioned will remain at the default value logic low The rear input data register is used to access the individual input channels The rear input includes 32 LVCMOS single ended channels Each channel is controlled by a correspon
28. contains the ordinal value of the highest priority enabled and active interrupt input INTO always the LSB is the highest priority interrupt input Each successive input to the left has a corresponding lower interrupt priority If no interrupt inputs are active the Interrupt Vector register contains all 1s This Interrupt Vector register acts as an index for giving the correct Interrupt Vector Address Master Enable Register Read Write BARO 0x0010001C This is a 2 bit read write register The two bits are mapped to the two least significant bits of the location The least significant bit contains the Master Enable bit and the next bit contains the Hardware Interrupt Enable bit Writing a 1 to the Master Enable bit enables the IRQ output signal Writing a 0 to the Master Enable bit disables the IRQ output effectively masking all interrupt inputs The Hardware Interrupt Enable bit is a write once bit At reset this bit is reset to 0 allowing the software to write to the Interrupt Status register to generate interrupts for testing purposes and disabling any hardware interrupt inputs Writing a 1 to this bit enables the hardware interrupt inputs and disables software generated inputs Writing a 1 also disables any further changes to this bit until the device has been reset Writing 1s or Os to any other bit location does nothing When read this register will reflect the state of the Master Enable and Ha
29. did not provide a complete AXI interface in ISE 14 1 to the memory controller when it is configured for a QDR II application Acromag has provided the missing functionality This AXI QDR II pcore has separate 256 bit read and write interfaces It supports continuous simultaneous 125 MHz read and write bursts Fixed a bug in the TCL script that failed to close an output file upon termination in ISE 14 2 The supported devices list was modified to include only the Virtex 6 Modifications to the AXI PCle core were necessary to separate the reset from the rest of the AXI system When resetting the AXI system form example through MicroBlaze the PCle configuration space would also be reset preventing the host from communicating with the FPGA through the AXI PCle core until a power cycle of the board was done The axi_enhanced_pcie core is a Xilinx helper core for the AXI PCle core and was modified to bring the 250MHz clock to the top level which was generated by a MMCM internal to this core Acromag Inc Tel 248 295 0310 69 www acromag com XMC 6VLX Modifications to the util_ds_buf USER S MANUAL Modifications to the MPD Microprocessor Definition file were necessary to this core to allow the frequency of the connected clock to be passed to the Xilinx EDK XPS tool in order to derive timing constraints clocks and signals downstream Changes were done in accordance to Xilinx Answer Record 42642 The Acromag design uses thi
30. register is used by Simple DMA operations as the starting read address for DMA data 31 0 transfers The address value written can be at any byte offset Note The software application should only write to this register when the AXI CDMA is Idle CDMA Destination Address Register Read Write BARO 0x000A0020 Table 3 14 CDMA Destination Address Register This register provides the destination address for simple DMA transfers by AXI CDMA Note if the QDR memory is the destination the base address from which QDR memory starts is Ox30000000 If a location in system memory is the destination address it must be set with the AXI aperture base address 0x01000000 the least significant 24 bits of the system memory address In addition the physical address of the location in system memory must be set in the Address Translation Register which is described in the PCle AXI Bridge Control section Bit s FUNCTION Destination Address Register This register is used by Simple DMA operations as the starting write address for DMA data 31 0 transfers Note The software application should only write to this register when the AXI CDMA is Idle Acromag Inc Tel 248 295 0310 33 www acromag com XMC 6VLX USER S MANUAL CDMA Bytes to Transfer Register Read Write BARO 0x000A0028 This register provides the value for the bytes to transfer for Simple DMA transfers by the AXI CDMA
31. source of this interrupt 0 Disabled 1 Enabled Reserved 31 2 o NA 1 NA Interrupt Enable Register Read Write BARO 0x00100008 This is a read write register Writing a 1 to a bit in this register enables the corresponding Interrupt Status bit to cause assertion of the interrupt output This Interrupt Enable bit set to 0 does not inhibit an interrupt condition from being captured It will still show up in the Interrupt Status register even when not enabled here To show up in the Interrupt Pending register it needs to be enabled here Writing a 0 to a bit disables or masks the generation of interrupt output for the corresponding interrupt input signal Note however that disabling an interrupt input is not the same as clearing it Disabling an active interrupt prevents that interrupt from reaching the IRQ output When it is re enabled the interrupt immediately generates a request on the IRQ output An interrupt must be cleared by writing to the Interrupt Acknowledge Register as described below Reading this Interrupt Enable register indicates which interrupt inputs are enabled where a 1 indicates the input is enabled and a 0 indicates the input is disabled Acromag Inc Tel 248 295 0310 22 www acromag com XMC 6VLX Table 3 6 Interrupt Enable Register USER S MANUAL Bit s FUNCTION This bit when set indicates a Xilinx Fabric interrupt from
32. 0310 48 www acromag com XMC 6VLX USER S MANUAL Table 3 29 PARE TORE OEO Register Bit Channel VHDL Name Schematic Name Data Register 0 0 FO 0 FIOO P 1 1 FO 1 FIO1 P Note that any registers bits not 2 2 FIO2 P mentioned will remain at the 3 3 FIO3_P default value logic low 4 4 FIO4 P 5 5 FIO5_P 6 6 FIO6_P 7 7 FIO7_P 8 8 FIO8_P 9 9 FIO9_P 10 10 FIO10 P 11 11 FIO11_GCLK P 12 12 FO 12 FIO12_GCLK P Front I O Interrupt Enable Register Read Write BARO 0x301008 The Front I O Interrupt Enable Register provides a map bit for each front output write register from 0 to 3 A 0 bit will prevent the corresponding output channel from generating an interrupt A 1 bit will allow the corresponding channel to generate an interrupt The Front I O Interrupt Enable register at the base address offset 0x301008 is used to control front output O through 3 interrupts via data bits O to 3 Bits 4 to 31 are not used and will always read as 0 All channel interrupts are disabled set to 0 following a power on or software reset Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Additional steps required to enable interrupts are described in the Interrupt Controller sections Interrupt Type COS or H L Configuration Register Read Write BARO 0x30100C The Interrupt Type Configuration Register determines the type of output channe
33. 1 1 Use the following DNS server addresses Preferred DNS server Alternate DNS server A Validate settings upon exit a Cms SFP2 G Internet Protocol Version 4 TCP 1Pv4 Properties General You can get IP settings assigned automatically if your network supports this capability Otherwise you need to ask your network administrator for the appropriate IP settings Obtain an IP address automatically Use the following IP address IP address 192 168 1 139 Subnet mask 255 255 255 128 Default gateway 192 166 4s 2 Obtain DNS server address automatically Use the following DNS server addresses Preferred DNS server Alternate DNS server El validate settings upon exit Lo cancel Also the Network Adaptor speed must be set to 1 0Gbps Full Duplex as shown Acromag Inc Tel 248 295 0310 74 www acromag com XMC 6VLX USER S MANUAL Realtek PCle GBE Family Controller Properties l General Advanced About Driver Details Power Management The following properties are available for this network adapter Click the property you want to change on the left and then select ts value on the right Property Value NS Offload a 1 0 Gbps Full Duplex Priority amp VLAN Lies Ful Duelos y Receive Buffers Receive Side Scaling Shutdown Wake On Lan peed 4 Duplex TCP Checksum Offload I
34. 16M byte block of memory BAR2 to access QDRII memory The PCle bus decodes 16M bytes for BAR2 for this memory space Acromag Inc Tel 248 295 0310 19 www acromag com XMC 6VLX BARO MEMORY MAP Table 3 2 BARO Registers Note that any registers bits not mentioned will remain at the default value logic low Acromag Inc Tel 248 295 0310 The BARO memory address space is used to access the PCle interrupt Front USER S MANUAL Rear and P16 I O registers System Monitor registers and Flash memory Note that the base address for the board BARO in memory space must be added to the addresses shown to properly access these registers BARO Base Address Size Description 0x00000000 gt 0x0000FFFF 64K Reserved 0x00010000 gt 0x0001FFFF 64K Reserved 0x00020000 gt 0x0009FFFF 512K Reserved 0x000A0000 gt 0x000AFFFF 64K AXI CDMA DS792 0x000B0000 gt 0x000EFFFF 256K Reserved Ox000FO000 gt 0x000FFFFF 64K PCle AXI Bridge Control DS820 0x00100000 gt 30x010FFFFF 64K PCle Interrupt Controller 0x00110000 gt 0x002FFFFF 2M Reserved 0x00300000 gt 0x0030FFFF 64K dll Es VE MORR 0x00310000 gt 0x003FFFFF 1M Reserved 20 www acromag com XMC 6VLX USER S MANUAL INTERRUPT CONTROLLER The AXI Interrupt Controller concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor using the PCle bus The i
35. 2 5volt LVCMOS I O to the P16 connector Alternatively 2 5volt LVDS I O can be used on the rear connector The P16 secondary XMC connector connects directly to the user programmable FPGA for both high speed Giga bit data signals and standard I O user signals The user I O pins are connected to FPGA banks with VCCO pins powered by 2 5 volts Thus these user I O pins will support the 2 5 volt lOStandards The IOSTANDARD attribute can be set in the user constraints file UCF For example P16 user I O can be defined for LVDS_25 Low Voltage Differential Signaling The example design defines the P16 I O to LVCMOS25 low voltage CMOS in the user constraints file The tables included in the P16 Input Data Register and P16 Output Data Register sections can be used to map the LVCMOS signal to the signal names given in this table The 2 5 volt lOStandards available are listed in the Virtex 6 User Guide available from Xilinx Pin A B C D E F 1 DPOO DPOO S18G_N DPO1 DPO1 S18G_P 2 GND GND S16_N GND GND S17_N 3 DPO2 DPO2 s16_P DP03 DP03 17_P 4 GND GND S14_N GND GND S15_N 5 DP04 DP04 14 P DPO5 DPO5 S15_P 6 GND GND S12_N GND GND S13_N 7 DPO6 DPO6 12_P DPO7 DPO7 S13_P 8 GND GND S10_N GND GND S11_N 9 DPO8 DPO8 S10_P DPO9 DPO9 s11 P 10 GND GND S8_N GND GND S9 N 11 DP10 DP10 S8_P DP11 DP11 s9_P 12 GND GND S6_N GND GND S7_N
36. 300218 flash address set to block O Write 0x1 to address 0x300204 flash block O unlock Write 0x1 to address 0x300210 flash block O erased Write 0x3AA3 to address 0x300214 flash data register set with Ox3AA3 Write 0x1 to address 0x30020C flash data written to flash 10 Write Ox0 to address 0x300218 set flash address back to 0 11 Read address 0x300208 flash data at address 0x0 is Ox3AA3 Acromag Inc Tel 248 295 0310 46 www acromag com XMC 6VLX USER S MANUAL System Monitor Status Control Register Read Write BARO 0x300300 This read write register will access the system monitor register at the address set in the System Monitor Address Register For example the address of the System Monitor Status register that is to be accessed is first set via the System Monitor Address register at BARO plus 0x300304 Next this register at BARO plus 0x300300 is read Bits 22 to 16 of this register hold the address of the system monitor register that is accessed Data bits 15 to 6 of this register hold the ADCcode temperature Vccint or Vccaux value Data bits 5 to O are not used Valid addresses are given in column one of the table below Reading or writing this register is possible via 32 bit data transfers The 10 bits digitized and output from the ADC can be converted to temperature by using the following equation ADCcodex 503 975 Temperatuie C 273 15 a CO 1024 The 10 bits digitized a
37. 8 295 0310 9 www acromag com XMC 6VLX USER S MANUAL Signal Interface Products Accessory cables that interface to the front VHDCI connector and SFP modules are available from Acromag VHDCI Cable Acromag provides a cable that brings the 36 pins of the VHDCI front I O connector out to a 50 pin SCSI connector The Acromag part number is 5025 921 See Table 2 3 Board Front VHDCI Field I O Pin Connections A cable drawing is also provided in the accessories section at the end of this manual SFP to SFP Cable Acromag provides a 1 meter cable that connects one SFP to another SFP The cable is copper Twin ax and connects one SFP module to another The Acromag part number is 5028 449 Drawing provided in the accessories section at the end of this manual 1000BASE T Copper SFP Transceiver Acromag provides Copper SFP Transceiver that is compatible with the Gigabit Ethernet and 1000BASE T standards as specified in IEEE Std 802 3 It has an RJ 45 connector and is RoHS compliant and lead free The Acromag part number is 5028 455 Drawing provided in the accessories section at the end of this manual 2 125 Gb s Short Wavelength SFP Transceiver Acromag provides 2 125 Gb s Short Wavelength SFP Transceiver that is compatible with the Gigabit Ethernet standard as specified in IEEE Std 802 3 and Fibre Channel FC PI 2 Rev 5 0 It is ROHS compliant and lead free Supports up to 2 125 Gb s bi directional data links Use 850nm Oxide VCSEL laser trans
38. 84 www acromag com XMC 6VLX USER S MANUAL Click OK to accept the changes Next exit XPS and return to ISE to compile the updated system Right click on system_top in the Heirarchy pane and then select implement top module from the pop up menu ect Source Proce y ocess Toc 7 F T y x 9 a A a Da H g l de Sano mel se g Design View 8 Implementation E Simulation Hierarchy 5 XMC 6VLX240F a Es E C A XMC V6 XMC 6VLX240F SDK srec_bootloader_0 Debug srec_b E ly aurora 8b10b_i aurora_8b10b_v5_3_example_design MAPPED C XN h Flash_comp FLASH FLASH_arch C XMC V6 source flash vhd h Rear_IO RearLVDS RearLVDS_arch C XMC V6 source RearLVDS vhd E fh Front_1O FrontLVDS FrontLVDS_arch C XMC V6 source FrontLVDS 1 P16_10 P16_LVDS P16_LVDS_arch CAMAS sourceP16 VOS id h sysmon_wiz_inst sysmon_wiz_v2_1 xilinx CAXMC V6 sourcelsysm Fr C KMC V6 source system ucf il m No Processes Running Processes system_top STRUCTURE E User Constraints S 11Q Synthesize XST View RTL Schematic View Technology Schematic C Check Syntax Generate Post Synthesis Simulation Model EO Implement Design amp 00 Translate C Generate Post Translate Simulation Model E Q Map E LIO Place amp Route ad Generate Programming File gt Es A Summary E 108 Properties E Module Level Utilization E Timing Const
39. Acromag THE LEADER IN INDUSTRIAL 1 0 XMC 6VLX Front I O Virtex 6 Based FPGA XMC Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom MI 48393 7037 U S A Tel 248 295 0310 Copyright 2012 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 930E XMC 6VLX USER S MANUAL Table of Contents 1 0 GENERALINEORMATIO NN ascii 6 Ordering IO MEA ON iii A acacia 6 Key Feature vicsicccsscsscsssssessssossssessessscsscoseassscossacassossscsssccsssesssonssoesccssacsscasssccsssssscssssasscasssasaes 7 PCle Interface Features sccicsccceiccc ssescassedesanddacuscedessavsecsacevsecdonssceuvecudsnssecnssecdssvacwssocsosscdensdees 8 SOTMWALE secsicscciccsceesienatensescelesveansicaseseusesvouesSeteunds Ueadvecssedoceseteudessubnssvanetdadsssvccusieee ecdovestensess 9 ENGINEERING DESIGN JKIT tissescsessssscocassestocessctcacessceteersdencndescestne covedendistesdneesceqchsesseydbecscaacnesscgethexsteccadabecesnaas 9 DLLCONTROL SOFTWARE wivvcacccccsescccccessestecinececeacacctcvneeeccccuseestccasecuecessecstceaseesuensseesneesseectonsseecncdbseeceoessteate s 9 VXWORKS SOFTWARE s assisen anian ennaa eaa Ingea did caucesehe ERA ERA eat tag E a chains cn grande cdas a is E aa 9 LIM UXSOPMWARE aire dencia csi 9 Signal Interface Products iis siecsess ceeiecdssiccseiecsntcetusdedcens saceasdusoesvacesscauesvceudvces dvcdeusveosuvecacnstccues 10 WA DG Ca Bless aces io dadas aid
40. B Hardware Memory Map Stack Size 1MB Memory Base Address Size microblaze_0_i_bram_cntlr_micro 0x00000000 16 KB DDR3_SDRAM_S_AXI_BASEADDR 0x80000000 1GB Fixed Section Assignments O A message box will appear Click Yes to overwrite the existing file Linker Script Already Exists 28 Linker Script File C XMC V6 XMC 6VLX240F SDK lwip_echo_server_dual src lscript ld already exists Do you want to overwrite the file EA Acromag Inc Tel 248 295 0310 96 www acromag com XMC 6VLX USER S MANUAL The project will automatically re build and create a new Iwip_echo_server_dual srec file This is the file that will be written to the BPI FLASH C C srec_bootloader_0 src memory_config_g c Xilinx SDK File Edit Source Refactor co fa X Navigate Search Run X Or 2M 6 aA Project Xilinx Tools Window Help 08 0 Q 9 gt ES Debug 7 Bs 2 EDK_hw_platform gt eS hello_world_0 4 5 Iwip_echo_server_dual 32 Binaries Ap Includes Debug 4 Release sre s lwip_echo_server_dual elf none le E lwip_echo_server_dual elf elfcheck 8 makefile objects mk sources mk amp src gt eS srec_bootloader_0 Hb standalone_bsp_0 5 lwip_echo_server_dual Acromag Inc Tel 248 295 0310 ie memory_config_g c 23 Ol Ez Outline 23
41. Control Write Only BARO OX300204 cccccccsscccssssececsseseceesaececeesseceessseeceesaeeccseseeeeeseseceeaas 44 Flash Read Read Only BARO OX300208 c ccccccccssscecesssececessceceessececessseceesseseceesueeecesseeceesseseceeaaes 44 Flash Start Write Write Only BARO OX30020C ccccccccsssceesssceceeseeeceesseceesseseceesueeeceeseeceeseeeceeaaes 45 Flash Erase Block Write Only BARO OX300210 cc cccccssccccsssceceesseeecssssececssseeceesaeeecsesseeeeseseeseaaes 45 Flash Data Register Read Write BARO 0x300214 oooooococcccocnnoonnononcconnnonanononanononoconanoranncnnn nora nncnnnnos 45 Flash Address Read Write BARO 0x300218 oooooooccnoconoconononcnonnnonnononanonanocnnnnononncnnn nono nnonnnnconnncnnnnos 45 Acromag Inc Tel 248 295 0310 2 www acromag com XMC 6VLX USER S MANUAL Simple BPI Flash Programming Example cccccsssccccecsesssssceccceceesesseeesecseseseeaeeseesescseseeaeseesesseesesaeaeeeeeees 46 Simple Platform Flash Programming ExaMple c ccccccccssssssccccecessessseesecsceeseseeaeseescscsesesaeseeeesceeseaeaeeeesees 46 System Monitor Status Control Register Read Write BARO 0x300300 ooooococccococococonoonnoonnnonononoos 47 System Monitor Address Register Write Only BARO 0x300304 oooonoccccconoconocoooconoconnnccoonnnncconnnnnns 47 Front Input Data Register Read Only BARO OX301000 ocoooonccn
42. E memory_config_g c 2 N ih system mss system xml gt B Outline 2 Make Target iS on your he a 12 Y Y o HE Y a EDK_hw_platform cd a R memory_config h ES hello world 0 7 memory_ranges struct memory_range_ a etrucr menory range s menory rangesii i naaa microblaze 0 d bram_cntlr memory will not be tes 1 DDR3_SDRAM axi_v6_ddrx 0x80000000 1073741824 int n memory_ranges 1 y pi m 4 Mo r L 5 lwip_echo_server_dual This file is automatically generated based c El Problems 4 Tasks El Console 22 C Build Iwip_echo_server_dual SECTION ctors UXSUULECUU UX4UUIECU Section fini 0x4 001EBEO Ox4001EBFF Section init 0x4001EBA0 0x4001EBDF Section text 0x40000000 Ox4001EB9F E Properties Y Terminal 1 220 Bla ar Try using the linker script generation tools to generate an ELF that maps correctly to your hardware design Finished building lwip echo _server_dual elf elfcheck NO 94 www acromag com XMC 6VLX USER S MANUAL The base address of the DDR3 SDRAM has been updated automatically but the code data and heap sections are currently located in block RAM PF amp Generate a linker script Generate linker script Control your application s memory map Output Settings Basic Project Iwip_echo_server_dual Output Script Place Cod
43. Help ax z 08 X Bus Interfaces Ports Addresses A 1 Instance Base Name Base Address High Address i Bus Interface Description microblaze_0 s Address Map 5 EDK Install microblaze 0_d_bram_cntlr C_BASEADDR 0X00000000 Ox00003FFF Analog microblaze_0_i bram_cntlr C_BASEADDR 0X00000000 Ox00003FFF Bus and Bridge mb_axi_intc_0 C_BASEADDR 0x00020000 0x0002FFFF Clock Reset and Interrupt microblaze_0_debug_module C_BASEADDR 0x00030000 0x0003FFFF Communication High Speed axi_timer_0 C_BASEADDR 0x00040000 0x0004FFFF Communication Low Speed axi_uartl6550_0 C_BASEADDR 0x00050000 0x0005FFFF DMA and Timer ethernet_SFP1 DMA C_BASEADDR 0x00060000 Ox0006FFFF Debug ethernet_SFP2_DMA C_BASEADDR 0x00070000 0x0007FFFF FPGA Reconfiguration ethernet_SFP1 C_BASEADDR 0x00200000 0x0023FFFF General Purpose 10 ethernet_SFP2 C_BASEADDR 0x00240000 0x0027FFFF 10 Modules axi_ahblite_bridge_0 al 0x00300000 OXDO30FFFF Interprocessor Communication axiZaxi_connector_0 0x00300000 Ox0030FFFF Memory and Memory Controller DDR3_SDRAM AAA Eoxeno00000 oxzerRerEE PCI B Unmapped Addresses Peripheral Controller axi_to_qdr_mc_0 C_BASEADDR 0x30000000 OX30FFFFFF Processor axi_cdma_0 C_BASEADDR OX000A0000 OxO00AFFFF Utility PCle_axi_intc_1 C_BASEADDR 0x00100000 0x0010FFFF Verification P15_PClex4 C_AXIBAR_0 0x01000000 OXO01FFFFFF gt Video and Image Processing P15_PClex4 C_BASEADDR Ox000F0000 OxO00FFFFF Project Loca
44. M Flash etc Size User Modifiable Function Process to Sanitize Flash 16Mbyte m Yes Storage of Code for Clear Flash memory by erasing No FPGA all sectors of the Flash Type EEPROM Flash etc Size User Modifiable Function Process to Sanitize Flash 32Mbyte m Yes Storage of Code for Clear Flash memory by erasing No MicroBlaze all sectors of the Flash Type EEPROM Flash etc Size User Modifiable Function Process to Sanitize Flash 512x8 bit o Yes Storage of Code for Not Applicable m No IPMI Interface Device Device is not populated in default build Acromag Representative Name Title Email Office Phone Office Fax Joseph Primeau Dir of Sales jprimeau acromag com 248 295 0823 248 624 9234 and Marketing Acromag Inc Tel 248 295 0310 116 www acromag com XMC 6VLX USER S MANUAL Revision History The following table shows the revision history for this document Release Date EGR DOC Description of Revision 10 OCT 12 LMP LMP Initial Acromag release 17 DEC 12 LMP LMP Removed reference to extended temperature grade products Added power supply requirements 14 AUG 13 LMP LMP Additional text added to pages 64 65 describing Ethernet and Microblaze 29 JAN 14 LMP LMP Descriptions of accessory VHDCI cable SFP cable and modules were added along with their Acromag part numbers 18 MAR 14 JCL JCL Added detail to section 5 0 Embedded gt SKD gt Iwip_echo_server_dual that de
45. Male Net Weight 96 5 g Wire Cable Type Twin ax Current 0 5A max per contact Voltage 30V max Shielded Yes steer A ds SSS Sr 30 11 26 SEE DETAIL 1 9 20 13 70 pr PAD 20 DETAIL 1 PAD 1 f SCALE 2 1 Acromag Inc Tel 248 295 0310 112 www acromag com XMC 6VLX USER S MANUAL 1000BASE T Copper SFP Transceiver Acromag provides Copper SFP Transceiver that is compatible with the Gigabit Ethernet and 1000BASE T standards as specified in IEEE Std 802 3 It is RoHS compliant and lead free The Acromag part number is 5028 455 DESCRIPTION Up to 1 25Gb s bi directional data links Compact RJ 45 Connector assembly 10 100 1000 BASE T operation SPECIFICATIONS Operating Temperature Range 40 C to 85 C APPLICATIONS 1 25 Gigabit Ethernet over Cat 5 cable ITEM DIM mm TOL mm A 13 55 0 25 B 845 0 2 1320 02 D 13 30 02 E 14 10 03 F 140 02 K 70 20 REF L 420 REF N 2 30 10 15 p ann M1 Q 920 01 5 47 50 02 T 37 15 03 u 43 00 02 v 255 01 Ww 160 REF x 22 70 03 Y 250 02 Zz 0 60 0 15 Acromag Inc Tel 248 295 0310 113 www acromag com XMC 6VLX USER S MANUAL 2 125 Gb s Short Wavelength SFP Transceiver Acromag provides 2 125 Gb s Short Wavelength SFP Transceiver that is compatible with the Gigabit Ethernet standard as specified in IEEE Std 802 3 and Fibre Channel FC PI 2 Rev 5 0 It is ROHS compliant and lead free The Acromag part nu
46. Pv4 TCP Checksum Offload IPv6 Transmit Buffers UDP Checksum Offload IPv4 UDP Checksum Offload IPv6 Wake on Magic Packet Wake on pattem match WOL amp Shutdown Link Speed Si Next run the program either directly from SDK see EDK Concepts Tools and Techniques document from www xilinx com or as described above in the Running a Program from BPI FLASH Memory When the program is running on the Virtex 6 FPGA Ping or Telnet can be used to communicate with the Ethernet cores inside the FPGA Ping requests can be made by typing ping 192 168 1 XXX into a Window CMD terminal This will send out ICMP Internet Control Message Protocol packets and the Ethernet core inside the Xilinx Virtex 6 FPGA will send back acknowledgments Telnet can be used to start the Echo Server program Telnet is a TCP based protocol that will and this test will echo back any information sent to the Ethernet cores See below for an example of how to run the Echo Server and for more information on Ethernet applications see the Xilinx document xapp1026 pdf available at http www xilinx com cx C WINDOWS system32 cmd exe x Microsoft Windows XP Version 5 1 2600 lt C gt Copyright 1985 2001 Microsoft Corp C Documents and Settings Administrator gt telnet 192 168 1 138 7 Acromag Inc Tel 248 295 0310 75 www acromag com XMC 6VLX USER S MANUAL cx Telnet 192 168 1 138 Heelloo TThhiiss iiss wwhhaatt tthhee EECCHHOO
47. SSeerruveerr llooookkssi lliikkeetttttt EDK File Organization The XMC V6 EDK design files are organized by the following directory structure pcore_subdirectory This directory contains the design files for the Acromag modified pcores described in the above section source The source directory contains the VHDL source files for the common peripherals sw_soure The sw_source directory contains the Xilinx SDK library files that were modified by Acromag to suit the XMC V6 product XMC 6VLX240F This directory is the parent for design files that are specific to the particular variant of XMC V6 Subdirectories further organize the design files into Xilinx tool specific folders EDK iMPACT ISE and SDK which include the tool specific project files xmp xise or ipf Example EDK Design Modification Walkthrough This section describes in detail the steps needed to re locate the DDR3 SDRAM in the address space First let s take a look at the original address map Open ISE then navigate to the directory C XMC V6 XMC 6VLX240F ISE XMC 6VLX240F Open the project file XMC 6VLX240F xise In the hierarchy pane right click on system_iand select open from the pop up menu to open the embedded system in the EDK tool Acromag Inc Tel 248 295 0310 76 www acromag com XMC 6VLX USER S MANUAL Hierarchy XMC 6VLX240F S Ed emits 2ff1156 E he system_top Zena acta i ie top vhd hy aurora a 8b10b i i aurora_8b10b_v5
48. Status command is executed by writing logic 1 to bit 2 of this register at base address plus 0x300204 Bit 3 of this register is used to set Platform Flash Asynchronous Mode Write to Flash Control register at 0x300204 with bit 3 set to logic 1 will initiate a set configuration sequence to the Flash device The flash address must first be written to the Flash Address register at 0x300218 with data value 0x8000 to select asynchronous mode Bit s Flash Control Register Description Block Unlock 0 O Write logic low has no effect 1 Write logic high to initiate Block Unlock BPI Flash Reset 1 O0 Write logic low has no effect Write logic high to initiate BPI flash Clear Flash Status 2 O0 Write logic low has no effect Write logic high to initiate Clear Flash Status Platform Flash Asynchronous Mode 3 O0 Write logic low has no effect Write logic high to select Asynchronous Mode Reserved 4 31 O Write logic low has no effect 1 Write logic high has no effect Flash Read Read Only BARO 0x300208 A Flash Read command is executed by reading this register at base address plus 0x300208 Prior to issue of a Flash Read the Flash Address registers must be set with the desired address to be read See the Flash Address registers at base address plus 0x300218 Acromag Inc Tel 248 295 0310 44 www acromag com XMC 6VLX USER S MANUAL Flash Start Write Write Only BARO 0x30020C This
49. Syntax Generate Post Synthesis Simulation Model E PAA Implement Design E ULA Translate C Generate Post Translate Simulation Model gt i a Generate Target PROM ACE File Manage Configuration Project iMPACT Analyze Design Using ChipScope Ex Design Overview Summary E 10B Properties E Module Level Utilization E Timing Constraints E Pinout Report El Clock Report Static Timing E XPS Errors and Warnings E Platgen Messages O Simgen Messages E Bitinit Messages Es XPS Reports E Platgen Log File 2 Simgen Log File B Bitinit Log File O System Log File Errors and Warnings E Parser Messages E Synthesis Messages E Translation Messages E Map Messages E Place and Route Messag E Timing Messages system_top Target eve pesas SS SE 14 1 Balanced Xilinx Default unlocked Platgen Log File Thu Sep 20 07 34 29 36 Warnings 8 new 0 49 Infos 2 2012 filtered new 0 filtered Simgen Log File BitInit Log File Tue Sep 18 14 38 54 2012 29 Infos 0 new 0 filtered System Log File Design Properties Y Enable Message Filtering Optional Design Summary Contents E Show Clock Report Show Failing Constraints Show Warnings Number of Slice Registers 73 041 301 440 E Show Errors Number used as Flip Flops Number used as Latches Number used as Latch thrus Number used as AND OR logic
50. XI BARO Aperture Base Address sisi ccccsssccsesssseccessecneesssntedsecunsinassstenuesvevewetesadancestesdeeessasess 35 PCle AX Bridge Controlan 36 Physical Side Interface Status Control Register Read Write BARO OxXOOOFO144 oooconoccnocccconnconnns 36 AXI Base Address Translation Configuration Register Read Only BARO 0xFO208 0xF020C 37 FPGA Fabric MEMORY MAP lsccisdiscacicecesticcccecivccevaccnsccbscesvleuedeetosedecuuccsancseceoeteu sect slendccedsacves 38 Front Rear and P16 I O Registers Read Write BARO 0x301000 to Ox 301 FFF csccccssecsseceeeees 39 Front I O Interrupt Status Clear Register Read Write BARO Ox300000 oococococccnnoonononononoonnconocnnos 39 DDR Memory Test Status Register Read Write BARO 0x300008 csccccssecsseceescecsseceeseecsseeeseees 40 XMC Board Identification Code Register Read Only BARO Ox30000C cccococnnccococcnococanoconananocanaconos 40 Configuration Control Read Write BARO OX300100 cccccescccssecesssecssecessecessecesseeessecesseeesseceees 40 Aurora Monitor Read Write BARO OX300104 0 0 ccccccccssscesscecssscecseecssseeeseecseeecseecsseeeeseecaeeeeseeses 41 Flash Introductio i cicet tees eeserens Grade sdeserantee de reaceanbtets les aa A EA a een ate EE aE 41 Flash Status Read Only BARO Ox300200 ccccccccssscccsessececsssceceessececeesseceesseseceesaeeeceeseeceeseseceeaaes 43 Flash
51. XMC P16 connector These lanes can be used for Serial RapidlO PCle 10 Gigabit Ethernet or Xilinx Aurora The example design will support an 8 lane Aurora loopback implementation SFP High Speed Interface The Two high speed serial interfaces are routed from the FPGA to two SFP Small Form factor Pluggable module connectors SFP provides a common solution for single channel serial ports including Gigabit Ethernet and fire channel Two MAC IDs are provided for the Ethernet channels Interface to Rear P4 Connector The Virtex 6 FPGA is directly connected to 64 pins of the rear P4 connector All 2 5volt IO standards supported by the Virtex 6 device are available The example design provides LVCMOS single ended signaling Interface to Front VHDCI Connector The Virtex 6 FPGA is directly connected to 36 pins of the front VHDCI connector All 2 5volt IO standards supported by the Virtex 6 device are available on 13 signal pairs or 26 single ended signals JTAG for Virtex 6 configuration and use with Xilinx ChipScope FPGA signal analysis tool USB is provides a 7 www acromag com XMC 6VLX PCle Interface Features Acromag Inc Tel 248 295 0310 USER S MANUAL MicroBlaze debug terminal port Example Design Provided The example VHDL design includes implementation of the PCle bus 4 lane Gen 1 control of digital front and rear I O and QDRII read write interface logic SFP module interface for 1 Gig Ethernet with DDR3 Memor
52. Xilinx Platform Studio Note that the base address for the board BARO in memory space must be added to the addresses shown to properly access these registers Table 3 19 BARO Registers Note that any registers bits not mentioned will remain at the default value logic low Acromag Inc Tel 248 295 0310 rer lana Bit s Description 0x300000 31 0 Interrupt Status Clear 0x300004 31 0 Reserved 0x300008 31 0 DDR Memory Test Status Register 0x30000C 31 0 Board Identification Register 0x300010 gt 0x3000FF 31 0 Reserved 0x300100 31 0 Configuration Control 0x300104 31 0 Aurora Monitor 0x300108 gt 0x3001FF 31 0 Reserved 0x300200 0 Flash Status 0x300204 0 Flash Control 0x300208 0 Flash Read 0x30020C 0 Flash Start Write 0x300210 0 Flash Erase Sector 0x300214 15 0 Flash Data Register 0x300218 24 0 Flash Address Register 0x30021C gt 0x3002FF 31 0 Reserved 0x300300 31 0 System Monitor Status Control Register 0x300304 31 0 System Monitor Address Register 0x300308 gt i 0x300FFF 31 0 Reserved 38 www acromag com XMC 6VLX USER S MANUAL Front Rear and P16 I O Registers Read Write BARO 0x301000 to 0x 301FFF Table 3 20 BARO Registers Note that any registers bits not mentioned will remain at the default value logic low The BARO memory space from 0x301000 to 0x301FFF is used to access the Front Rear and P16 I O register
53. _3_example_design MAPPED C AN 8b10b_v5_3 tg Flash_comp FLASH FLASH_arch C XMC V6 source flash vhd Ma Rear_IO RearLVDS RearLVDS_arch C XMC V6 source RearLVDS vhd hy Front_IO FrontLVDS FrontLVDS_arch C XMC V6 source FrontLVDS vhd a P16_IO P16_LVDS P16_LVDS_arch C XMC V6 source P16_LVDS vhd Mha sysmon_wiz_inst sysmon_wiz_v2_1 xilinx C XMC V6 source sysmon_wiz_v2_1 vhd lr C XMC V6 source system ucf mm Acromag Inc Tel 248 295 0310 77 www acromag com XMC 6VLX USER S MANUAL Click on the address tab to display the address map Edit View Project Hardware Debug Window Help z O8x Bus Name IP Type axi_interconnect_O r axi_interconnect EDK Install axi_interconnect_1 r axi_interconnect Analog 3 axi_interconnect_2 r axi_interconnect Bus and Bridge microblaze_0_dimb ty Imb_vi0 Clock Reset and Interrupt microblaze_0_ilmb Ye Imb_v10 Communication High Speed microblaze_0 r microblaze Communication Low Speed microblaze_0_bram_block r bram_block DMA and Timer microblaze_0_d_bram_cntlr r Imb_bram_if_cntlr Debug microblaze_0_i_bram_cntlr ie Imb_bram_if_cntlr FPGA Reconfiguration DDR3 SDRAM Yi axiv6_ddrx General Purpose 10 axi2axi_connector_O r axi2axi_connector 10 Modules microblaze_0_debug_mo r mdm Interprocessor Communication PCle_axi_intc_1 r axi_intc Memory and Memory Controller mb_axi_intc_0 ty axi_intc PCI axi_
54. ahblite_bridge_0 r axi_ahblite_bridge Peripheral Controller axi cdma_0 r axi_cdma Processor ethernet SFP1 DMA r axi_dma Utility a H ethernet SFP2 DMA ke mi dma Verification ethernet_SFP1 r axi_ethernet Video and Image Processing ethernet_SFP2 r axi_ethernet Project Local PCores P15 PClex4 r axi_pcie Project Peripheral Repository0 E axi to qdr mc 0 r axi_to_qdr_mc ACROMAG XMCV6 E axi_timer_0 r axi_timer axi_uart16550_0 r axi_uart16550 clack nenerntar N de clack nenerator 0000000000000 00 hE Be A 4 m Legend WiMaster Slave Master Slave Target lt Initiator Connected OUnconnected M Monitor Search IP Catalog Yrproduction License paid Blicense eval Qlocal Pre Production M Beta Development Superseded Discontinued P Catalog Design Summary C System Assembly View EJ Graphical Design View C EA AAA rs e s see Bie 4 WARNING EDK 2342 Search path C XMC V6 pcores axi_to_ qdr mc v1 00 a directly contains drivers direc 4 WARNING EDK 4164 No Processor Interconnect selected in current selection within Bus Interface Tab Show Sub S E Console Warnings Errors Acromag Inc Tel 248 295 0310 78 www acromag com XMC 6VLX USER S MANUAL The DDR3 SDRAM is currently located at address 0x40000000 File Edit View Project Hardware Debug Window
55. annel input signal levels are determined by reading this register Channel output signals are set by writing to the P16 output data register at base address plus 0x301204 This P16 input data register is a read only register Channel read operations use 32 bit 16 bit or 8 bit data transfers All channels of this register are fixed as input channels Register Bit Channel VHDL Name Schematic Name 0 0 P16 SI 0 P16 SIO16 _N 1 1 P16 SI 1 P16 SIO14_N 2 2 P16 SIO12_N 3 3 P16 SIO10_N 4 4 P16 SIO8_N 5 5 P16 SIO6_N 6 6 P16 SIO4_N 7 7 P16 SIO2_N 8 8 P16 SIOO GCLK_N 9 9 P16 SIO18_GCLK P 10 10 P16 SIO17_P 11 11 P16_SIO15 P 12 12 P16 SIO13 P 13 13 P16 SIO11 P 14 14 P16 SIO9 P 15 15 P16 SIO7 P 16 16 P16 SIO5 P 17 17 P16 SIO3 P 18 18 P16_SI 18 P16 SIO1_N Acromag Inc Tel 248 295 0310 53 www acromag com XMC 6VLX P16 Output Data Register Write Only BARO 0x301204 The P16 output data register is used to access the individual LVDS output channels This includes 9 differential output channels Each channel is controlled by a corresponding data bit as shown in the P16 Output Data Register Table USER S MANUAL Channel output signal levels are controlled by writing this register Channel input signals are accessed by reading the P16 input data register at base address plus 0x301200 This P16 output data register is a write only register Channel write operations use 32 bit 16
56. are implemented on bank 22 DCI functionality in bank 23 is achieved in the UCF by cascading DCI between adjacent banks as follows CONFIG DCI_CASCADE 22 23 16 MByte 128Mb Xilinx XCF128X FTG64C Platform Flash XL device is used to configure the Virtex 6 FPGA 32 MByte Micron Numonyx PC28F256P30TF Non volatile storage that can be used for MicroBlaze software storage The Linear BPI Flash shares the dual use configuration pins in parallel with the XCF128 Platform Flash XL There are a total 256 addressable blocks each 64 Kwords XMC Compatibility Conforms to PCI Express Base Specification v2 0 and XMC Specification P1386 1 ANSI VITA 42 0 Complies with XMC module mechanicals and connectors ANSI VITA 42 3 XMC module with PCI Express Interface 4M Byte Memory Space Required BARO 64 bit Base Address Register for access to Flash Configuration Registers and System Monitor Registers Front Rear and P16 I O Registers 16M Byte Memory Space Required BAR2 64 bit Base Address Register for access to QDR memory Interrupts Source of interrupt can be from the programmable FPGA Messages are used to assert and de assert virtual interrupt lines on the link to emulate the Legacy PCI interrupt INTA signal Design also supports interrupt requests via message signaled interrupts Acromag Inc Tel 248 295 0310 108 www acromag com XMC 6VLX USER S MANUAL XMC 6VLX Block Diagram 11 LVDS Pairs amp 2 Global Clock
57. cessfully El console Errors Warnings Tat Find in Fies Results Acromag Inc Tel 248 295 0310 86 www acromag com XMC 6VLX USER S MANUAL ISE will ask for confirmation of the SDK workspace path Confirm that the path is C XMC V6 XMC 6VLX240F SDK Click on OK SDK will then launch D Workspace Launcher esl Select a workspace Xilinx SDK stores your projects in a folder called a workspace Choose a workspace folder to use for this session Workspace C XMC V6 XMC 6VLX240F SDK v Browse Use this as the default and do not ask again Acromag Inc Tel 248 295 0310 87 www acromag com XMC 6VLX USER S MANUAL SDK will detect the change in the hardware description files and automatically rebuild all of the software projects Unfortunately the change to the DDR3 SDRAM address is not reflected in all of the places it needs to be The memory_config_g_c c file used by the srec_bootloader program must be updated with the DDR3 SDRAM address In the Project Explorer pane expand the srec_bootloader_0 proejct and then expand the src folder Double click on memory_config_g to open it in the text editor Change the base address constant 0x40000000 to Ox80000000 and save the changes The project will automatically rebuild E Al C C srec_bootloader_0 src memory_config_g c Xilinx SDK loa File Edit Source Refactor Navigate Search Run Project Xilinx Tool
58. ction declaration main c amp implicit declaration of function putnum Wimplicit function declaration bootloader c implicit declaration of function tcp fasttmr Wimplicit function declaration platform c Y m we 0 items selected C Acromag Inc Tel 248 295 0310 88 www acromag com XMC 6VLX USER S MANUAL The srec_bootloader_0 elf program is included in the FPGA bitstream that is loaded into the FPGA on power up A new bitstream must be generated that includes the updates to the FPGA firmware as well as the updated software Click on system_top in the hierarchy pane and then double click on Generate Programming File in the Processes pane E File Diese Ex aanas Design View 0 8 Implementation Hierarchy 8 XMC 6VLX240F Ej l E E ly aurora_8b10b_i aurora_8b10b_v5_3_example_design MAPPED C i Flash_comp FLASH FLASH_arch C XMC V6 source flash vhd alee fa h sysmon_wiz_inst sysmon_wiz_v2_1 xilinx C XMC V6 source sys e C XMC V6 source system ucf Al C XMC V6 XMC 6VLX240F SDK srec_bootloader_0 Debug srec_b 1 Rear_IO RearLVDS RearLVDS_arch C XMC V6 source RearLVDS vhd E u Front_1O FrontLVDS FrontLVDS_arch C XMC V6 source FrontLVDS 1 P16_10 P16_LVDS P16_LVDS_arch C XMC V6 source P16_LVDS vhi AXN No Processes Running Processes system_top STRUCTURE Check
59. ctive Program Suspend active Vpp Status 3 O Vpp Acceptable Vpp Low Program Status 4 O Program Successful Program Error Erase Status 5 O0 Erase Successful Erase Error Erase Suspend Status 6 O Not Suspended Suspended Device Ready Status 7 O0 Device is busy 1 Device is ready SR 6 1 are valid Register The Clear Status Register command is used to clear the Status Register error bits Acromag Inc Tel 248 295 0310 43 www acromag com XMC 6VLX USER S MANUAL Flash Control Write Only BARO 0x300204 Table 3 26 Flash Control Register Note Block Unlock PBI Flash Reset and Clear Flash Status can not be simultaneously set in this register Only one operation can be selected at a time A Flash Control command is executed by writing this register at base address plus 0x300204 Write to Flash Control register at 0x300204 with bit 0 set to logic 1 will initiate a Block Unlock sequence to the Flash device The address of the block that is unlocked must first be written to the Flash Address register at 0x300218 Bit 1 of this register is used to initiate a reset of the BPI flash chip A Flash Reset command is executed by writing logic 1 to bit 1 of this register at base address plus 0x300204 Writing the flash reset command resets the chip to reading data mode Bit 2 of this register is used to clear the Flash Status of the BPI or Platform flash chip A Clear Flash
60. d For example if the system buffer physical address OxS6ABCDEF were given then the AXI Base Address Translation Configuration registers at BARO OxFO208 and OxF020C must be set to 0x0 and 0x56 ABCDEF respectively The least significant 24 bits of this address OxS6ABCDEF must be removed and added to the AXI BARO Aperture Base address The new AXI address is 0x01000000 OxOOABCDEF OxO1ABCDEF These values are then appended by the Virtex 6 hardware to give the final PCle address of the system memory location System Memory Physical Address 0x56XXXXXX l gt 0xF0208 amp 0xF020C Final PCle Address 0x56ABCDEF Intermediate Address AXI BARO Aperture Base Address 0x01000000 OxABCDEF Example of AXI address used to reach system host memory 0x01 ABCDEF Acromag Inc Tel 248 295 0310 35 www acromag com XMC 6VLX PCle AXI Bridge Control Table 3 17 PCle AXI Bridge Control Registers USER S MANUAL The PCle AXI bridge is an interface between the AXI4 and the PCle This bridge provides the translation level between the AXI4 memory mapped embedded system to the PCle system The AXI Bridge for PCle translates the AXI4 memory read or writes to PCle Transaction Layer Packets TLP packets and translates PCle memory read and write request TLP packets to AXI4 interface commands BARBARE nage Bit s Description Saco aan 31 0 See Xilinx DS820 Memory Map 0x000F0144 31 0 Physical S
61. ding data bit as shown in the Rear Input Data Register Table Channel input signal levels are determined by reading this register Channel output signals are set by writing to the rear output data register at base address plus 0x301104 This rear input data register is a read only register Channel read operations use 32 bit 16 bit or 8 bit data transfers All channels of this register are fixed as input channels Register Bit Channel VHDL Name Schematic Name 0 0 RI O RIOO_GCLK_P 1 1 RI 1 RIO1_P 2 2 RIO2_P 3 3 RIO3_P 4 4 RIO4_P 5 5 RIOS_P 6 6 RIO6_P 7 7 RIO7_P 8 8 RIO8_P 9 9 RIO9_P 10 10 RIO10 P 11 11 RIO11_P 12 12 RIO12 P 13 13 RIO13_P 14 14 RIO14 P 15 15 RIO15_P 16 16 RIO16_P 17 17 RIO17 P 18 18 RIO18 P 19 19 RIO19 P 20 20 RIO20 P 21 21 RIO21 P 22 22 RIO22_P 23 23 RIO23_P 24 24 RIO24 P 25 25 RIO25 P 26 26 RIO26 P 27 27 RIO27_P 28 28 RIO28 P 29 29 RIO29 P 30 30 RIO30_P 31 31 RI 31 RIO31_GCLK_P Acromag Inc Tel 248 295 0310 51 www acromag com XMC 6VLX USER S MANUAL Rear Output Data Register Read Write BARO 0x301104 Table 3 31 BARO Rear Output Data Register Note that any registers bits not mentioned will remain at the default value logic low The rear output data register is used to access the individual LVCMOS output channels This includes 32 single ended channels Each channel is controlled by a corresponding data bit as shown in the Rear Output Data R
62. e Sections in microblaze_0_ bram_cntlr_microblaze_0_d_bram_cntlr v CAXMC V6 XMC 6VLX240F SDK Iwip_echo_server_dual src lscript ld Browse Place Data Sections in f microblaze_0_i_bram_cntlrmicroblaze_0_d_bram_cntlr v Modify project build settings as follows Place Heap and Stack inf microblaze_0_i_bram_cntlrmicroblaze_0_d_bram_cntlr v Set generated script on all project build configurations Z Heap Size Hardware Memory Map Stack Size Memory Base Address Size microblaze_0_i_bram_cntlr_micro _ 0x00000000 16 KB DDR3_SDRAM_S_AXI BASEADDR 1GB Fixed Section Assignments o hh Acromag Inc Tel 248 295 0310 95 www acromag com XMC 6VLX USER S MANUAL Select DDR3_SDRAM_S_AXI_BASEADDR from the drop down list for each of code section data section and heap and stack Enter 1048576 for the heap size and the stack size 1 MB will be displayed in the box Click on Generate r Generate a linker script Generate linker script Control your application s memory map Output Settings Basic Advanced Project Iwip_echo_server_dual Output Script Place Code Sections inf DDR3_SDRAM_S_AXI BASEADDR C XMC V6 XMC 6VLX240F SDK Iwip_echo_server_dual src Iscript ld Browse Place Data Sections in DDR3_SDRAM_S_AXI_BASEADDR Modify project build settings as follows Place Heap and Stack i DDR3_SDRAM_S_AXI BASEADDR Set generated script on all project build configurations hd Heap Size 1M
63. e front input includes 13 LVCMOS single ended channels Each channel is controlled by a corresponding data bit as shown in the Front Input Data Register Table Channel input signal levels are determined by reading this register Channel output signals are set by writing to the front output data register at base address plus 0x301004 This front input data register is a read only register Channel read operations use 32 bit 16 bit or 8 bit data transfers All channels of this register are fixed as input channels Register Bit Channel VHDL Name Schematic Name 0 0 FI O FIOO_N 1 1 FI 1 FIO1 N 2 2 FIO2_N 3 3 FIO3_N 4 4 FIO4_N 5 5 FIOS_N 6 6 FIO6_N 7 7 FIO7_N 8 8 FIO8_N 9 9 FIO9_N 10 10 FIO10_N 11 11 FIO11_GCLK_N 12 12 FI 12 FIO12_GCLK_N Front Output Data Register Read Write BARO 0x301004 The front output data register is used to access the individual LVCMOS output channels This includes 13 channels Each channel is controlled by a corresponding data bit as shown in the Front Output Data Register Table Channel output signals are controlled by writing this register Channel input signals are accessed by reading the front input data register at base address plus 0x301000 This front output data register is a read writable register Channel operations use 32 bit 16 bit or 8 bit data transfers All channels of this register are fixed as output channels Acromag Inc Tel 248 295
64. e information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc RELATED PUBLICATIONS The following manuals and part specifications provide the necessary information for in depth understanding of the XMC 6VLX board Virtex 6 Data Book Spec http www xilinx com CY7C1565KV18 400BZC Spec http www cypress com MT41J128M16HA 15EIT Spec http www micron com Acromag Inc Tel 248 295 0310 5 www acromag com XMC 6VLX USER S MANUAL 1 0 GENERAL INFORMATION Ordering Information This XMC 6VLX is an XMC module with the heart of the design being the Virtex 6 reprogrammable FPGA The re configurable XMC 6VLX modules use the Xilinx Virtex 6 XC6VLX FPGA Re configuration of the FPGA is possible via a direct download into the Xilinx Platform Flash over the PCle bus The on board Platform Flash memory loaded with FPGA configuration data allows automatic Xilinx configuration on power up The XMC 6VLX is an XMC module with the following interfaces Eight high speed serial lanes are allocated to the XMC P15 connector These lanes can be used for an 8 lane PCle PCI Express implementation Serial RapidlO or 10 Gigabit Ethernet The example design will support a 4 lane Gen 1 PCle implementation with one DMA channel for data transfer between PCle and on board QDRII memory Eight high speed serial lanes are also allocated to the XMC P16 connector These ei
65. e the development of Windows applications interfacing with Acromag PMC XMC and VPX I O board products PCI and PCle I O Cards and CompactPCl I O Cards This software models PCISW API WIN32 and PCISW API WIN64 consists of low level drivers and Dynamic Link Libraries DLLs that are compatible with a number of programming environments The DLL functions provide a high level interface to boards eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers VxWORKS SOFTWARE Acromag provides a software product sold separately consisting of board VxWorks software This software Model PMCSW API VXW is composed of VxWorks real time operating system libraries for all Acromag PMC XMC and VPX I O board products PCI and PCle I O Cards and CompactPCI I O Cards The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag PCI and PCle boards Linux SOFTWARE Acromag provides a software product consisting of board Linux software This software Model PMCSW API LNX is composed of Linux libraries for all Acromag PMC XMC and VPX I O board products PCI and PCle I O cards and CompactPCI I O cards The software supports X86 PCI bus only and is implemented as library of C functions which link with existing user code to make possible simple control of all Acromag PCI and PCle boards Acromag Inc Tel 24
66. ed to the PCle x8 Endpoint P15 XMC connector e Eight 8 of the MGTs are wired to the P16 XMC connector e Two 2 MGTs are wired to SFP connectors U16 and U17 One 2 5V LVDS differential 125 MHz oscillator U31 is wired to the FPGA MGT clock input pins H5 H6 and AD6 ADS The 125 MHz signal names are SFP_CLK_P and SFP_CLK_N The board contains two small form factor pluggable SFP connectors U16 and U17 and cage assemblies that accept SFP modules The SFP interfaces are connected to MGT Bank 116 on the FPGA The SFP module serial ID interface is connected to the FPGA The control and status signals for the SFP modules are connected to DIP switch and the FPGA The DIP switch position 7 and 8 to control SFP rate select Internal FPGA logic controls the SFP signals including Tx_Fault Rx_LOS and Mod_ABS SFP signal Tx_Disable is hard wired to ground The XMC 6VLX board contains a Silicon Labs CP2103GM USB to UART bridge device U27 which allows connection from the Virtex 6 device to a host Acromag Inc Tel 248 295 0310 58 www acromag com XMC 6VLX USER S MANUAL computer with a USB cable Xilinx UART IP is implemented in the FPGA fabric using the Xilinx platform studio UART Lite IP The FPGA supports the USB to UART bridge using four signal pins Transmit TX Receive RX Request to Send RTS and Clear to Send CTS These signals are driven from pins W32 TX W25 RX Y28 CTS Y27 RTS of bank 14 of the Virtex 6
67. eeeeeees 69 Acromag modified library dei ese 70 Running a Program from BPI FLASH M MO ry ccssssccccecsssscessecccecseseeseececsceesesaeseeeesceeseaasaeseeseeeseauaeees 71 RUNNING EWIPSECHO Veras tdo aa E A T 74 EDK File QFE AMIZATION a aa 76 Acromag Inc Tel 248 295 0310 3 www acromag com XMC 6VLX USER S MANUAL Example EDK Design Modification Walkthrough ccccccccccsssssssecccecsessssssecececeesseaeseeeesceesesasaeseeseeeseasaeees 76 6 0 SERVICE AND REP AUR ida ia acia 103 Service a d Repair ASSIStANCe cuisine 103 Preliminary Service Procedure 15 sic cadciedaeai sievacucdnasdeahateeacaiddesdesiaverdsaidaadavsdivetacsiadevdesiivenees 103 Where to Get Heladio AA A A AA AAN 103 7 0 SPECIFICATIONS aia 104 PHYSIGA EE EEE E E AE E EE E E EEE 104 POWER REQUIREMENTS isisi eaaa A Ea E ES 104 ENVIRONMENTAL waco side cetera bend cas ea teene oake ad iia 104 User Programmable U PG A a a aa a A eare EE E aRar EA EERO aE etia dense 105 B ASEA ABLA EREET A ETA TTA ET 105 E o TN 105 P16 CONNECTOM fice ON 106 SEP GOMMECTONS says eho chic O RN 106 PAREADO erate causa EA T E EE AE E E E 106 V ADCEFRONT Omana A a RR 107 Board Oscillator S aoan aroen iaieiiea AiE AEA Eiaa ANEA aa aE OAA ESAE A aa ie AEA 107 DDRSIMGMONIy a eae ONDA Asa 107 QDR NFE SRAM MeMO aaa a aaa aa aa Aaa aA Did cate cues Sunn gues asian ODA aio EREE EREA Ea EE AEREE EET 107 16MB Platformi Flash RN 108 32MB Linear BPR ASH vas NA 108 PGle
68. efer to the specifications section for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the system boards plus the installed Acromag board within the voltage tolerances specified In an air cooled assembly adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering In a conduction cooled assembly adequate thermo conduction must be provided to prevent a temperature rise above the maximum operating temperature Remove power from the system before installing board cables termination panels and field wiring Default Hardware Configuration The board may be configured differently depending on the application When the board is shipped from the factory it is configured with the Acromag example design as follows e Slave SelectMap using Platform Flash XCF128X with onboard 48 MHz oscillator Acromag Inc Tel 248 295 0310 11 www acromag com XMC 6VLX USER S MANUAL The control registers must be programmed to the desired configuration before starting data input or output operation see section 3 P16 Secondary XMC Connector Table 2 1 Board P16 Secondary XMC Connections The example design implements
69. egister Read Write BARO 0x300008 This read write register is used to determine the Flash BPI memory read and DDR memory read write test status Read of bit 0 reflects the Flash BPI memory read status Read of a 1 indicates a BPI Flash read error Read of bit 1 reflects the DDR memory read write status Read of a 1 indicates a DDR memory read or write error Read of bit 2 reflects that all tests passed Read of a 1 indicates that both the Flash and DDR memory tests passed XMC Board Identification Code Register Read Only BARO 0x30000C The XMC Board Identification Code register at BARO plus Ox30000C stores an ID code that can used to uniquely identify the XMC Virtex 6 card This register will read A3 hex as provided by the Acromag example design The user can change the hardware setting of this register in the programmable FPGA code This ID code can be used to properly assign software drivers to multiple XMC boards that may have the same device and vender ID ina given system Configuration Control Read Write BARO 0x300100 This read write register configuration control register has multiple functions This Configuration Control register is accessed at base address plus 0x300100 The Configuration Control register bit 0 is used to select one of the two flash memory devices for erase or program read write operations The Configuration Control register bit 1 must be set to logic 1 to select Platform flash addre
70. egister Table Channel output signals are controlled by writing this register Channel input signals are accessed by reading the rear input data register at base address plus 0x301100 This rear output data register is a read writable register Channel operations use 32 bit 16 bit or 8 bit data transfers All channels of this register are fixed as output channels Register Bit Channel VHDL Name Schematic Name 0 0 RO 0 RIOO_GCLK_N 1 1 RO 1 RIO1_N 2 2 RIO2_N 3 3 RIO3_N 4 4 RIO4_N 5 5 RIOS_N 6 6 RIO6_N 7 7 RIO7_N 8 8 RIO8_N 9 9 RIO9_N 10 10 RIO10_N 11 11 RIO11_N 12 12 RIO12_N 13 13 RIO13_N 14 14 RIO14_N 15 15 RIO15_N 16 16 RIO16_N 17 17 RIO17_N 18 18 RIO18_N 19 19 RIO19 N 20 20 RIO20_N 21 21 RIO21 N 22 22 RIO22_N 23 23 RIO23_N 24 24 RIO24 N 25 25 RIO25_N 26 26 RIO26_N 27 27 RIO27_N 28 28 RIO28_N 29 29 RIO29_N 30 30 RIO30_N 31 31 RO 31 RIO31_GCLK_N Acromag Inc Tel 248 295 0310 52 www acromag com XMC 6VLX USER S MANUAL P16 Input Data Register Read Only BARO 0x301200 Table 3 32 BARO P16 Input Data Register Note that any registers bits not mentioned will remain at the default value logic low The P16 input data register is used to access the individual LVDS input channels This includes 10 differential channels which include 2 global clock signal pairs Each channel is controlled by a corresponding data bit as shown in the P16 Input Data Register Table Ch
71. egister field must contain a valid descriptor address prior to the software application writing the CDMA Tail Descriptor Pointer register value Failure to do so results in an undefined operation by the CDMA On error detection the Current Descriptor Pointer register is updated to reflect the descriptor associated with the detected error Note The register should only be written by the Software application when the AXI CDMA is Idle 31 6 Acromag Inc Tel 248 295 0310 31 www acromag com XMC 6VLX USER S MANUAL CDMA Tail Descriptor Pointer Register Read Write BARO 0x000A0010 This register provides Tail Descriptor Pointer for the AXI CDMA Scatter Gather Descriptor Management Table 3 12 CDMA Tail Bit s FUNCTION Descriptor Pointer Register Writing to these bits has no effect and they are always read as zeros 5 0 Tail Descriptor Pointer This register field is written by the software application in Scatter Gather Mode to set the current pause pointer for descriptor chain execution The AXI CDMA Scatter Gather Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer When the AXI CDMA is in Scatter Gather Mode a write by the software application to this register causes the AXI CDMA Scatter Gather Engine to start fetching descriptors starting from the Current Descriptor Pointer register value If the
72. er software is also supplied that exercises the peripheral components using the host processor through the PCI Express bus or the embedded Microblaze processer It is expected that an XMC V6 user s project will require a subset of the example project s interfaces in addition to user specific functions Acromag recommends beginning a new user project by copying the Acromag example project deleting any unnecessary peripherals and then adding the user defined functionality The XMC V6 block diagram shows the structure of the example system with peripherals that are accessible from the microblaze processor peripherals that are accessible from the host processor and peripherals that are common to both the microblaze processor and the host processor Master interfaces are shown with a blue square symbol Slave interfaces are shown with a red circle symbol The Acromag EDK delivers prepackaged example designs to program the Xilinx Virtex 6 FPGA The XMC V6 project folder will contain the following subdirectories ab pcore_subdirectory Xb source Xb Sw_source Ly XMC 6VLX240CC y XMC 6VLX240CC SG Li XMC 6VLX240F Li XMC 6VLX240F SG J XMC 6VLX365CC Ly XMC 6VLX365CC SG Lo XMC 6VLX365F Lo XMC 6VLX365F SG The naming convention used for the projects are as follows XMC 6VLX 240 F SG L Scatter Gather SG gt Scatter Gather included lt blank gt gt Scatter Gather not included Board F gt Front 1 0 CC gt Conduction Cooled
73. figuration byte size 9232444 bytes J INFO Bitstream 181 The start address provided has been multiplied by a factor of 2 due to the use of the x16 data width Ox8ce03c 9232444 bytes loaded up from 0x0 Using user specified prom size of 16384K Writing file C XMC V6 XMC 6VLX240F XMC 6VLX240F mcs Writing file C XMC V6 XMC 6VLX240F XMC 6VLX240F prm Writing file C XMC V6 XMC 6VLX240F XMC 6VLX240F cfi J 7 er 8 Errors a Warnings Configuration Platform Cable USBI 6 MHz Acromag Inc Tel 248 295 0310 93 www acromag com XMC 6VLX USER S MANUAL The XMC 6V is delivered with the lwip_echo_server_dual program loaded in the BPI FLASH memory On power up the srec_boot_loader program copies the lwip_echo_server_dual program from FLASH memory to DDR3 SDRAM and then executes the Iwip_echo_server_dual program in DDR3 SDRAM The linker script for the program Iwip_echo_server_dual must be updated to use the new base address assigned to DDR3 SDRAM Right click on the Iwip_echo_server_dual project in the Project Explorer pane and select Generate Linker Script from the pop up menu Fo m Acromag Inc Tel 248 295 0310 amp C C srec_bootloader_0 src memory_config_g c Xilinx SDK File Edit Source Refactor Nav igate Search Run Project Xilinx Tools Window Help m lax EE MECA Gy 4 Br DD OH ES 35 Debug Fig C C il rb Oro E Project Explorer
74. ght serial lanes can be used for Serial RapidlO PCle 10 Gigabit Ethernet or Xilinx Aurora The example design will support an 8 lane Aurora implementation for use of these lanes Two Virtex 6 global clocks and 34 select I O signals will also be provided on the P16 connector Select I O signals are 2 5V Virtex 6 I O pins that can be selected from single ended I O standards LVCMOS HSTL and SSTL and differential I O standards LVDS HT LVPECL BLVDS Differential HSTL and SSTL One P4 rear I O connector will provide two global clock differential pairs and 30 LVDS signal pairs Two high speed serial interfaces are routed from the FPGA to two SFP Small Form factor Pluggable module connectors SFP provides a common solution for single channel serial ports including Gigabit Ethernet and fire wire One front I O 36 pin connector will provide JTAG USB signals two global differential clock pairs 11 LVDS signal pairs and two ground signals The board will provide 2 Meg x 72 bit QDRII SRAM 128 Meg x 64 bit DDR3 SDRAM 4 Meg x 16 bit parallel Flash and Xilinx 128 Megabit Platform Flash The parallel Flash will interface to the FPGA for MicroBlaze CPU program code storage The Xilinx 128 Megabit Platform Flash will contain the power up configuration bit file for the Virtex 6 FPGA The following table lists the orderable models and their corresponding operating temperature range Models XMC 6VLX240F and XMC 6VLX365F are air cooled with fro
75. gt E LTM4602 1 0V_ANA U22 MIC6 1300 U24 1 2V MIC61300 XMC P15 3 3V 3 3V Table 4 2 Power System Reference ao Power Rail Power Devices Device Designator Description Name eas LTM4602 U18 FPGA VCCINT 1 0V 6 0A LTM4602 U19 VCCO DDR3 QDRII 1 5V 6 0A TPS51120 U15 DDR3 Termination 0 75V_DDR 2A TPS51120 U30 QDRII Termination 0 75V_QDR 2A LTM4602 U20 VCCO Flash 2 5V 6 0A LTM4602 U25 Flash MGT 1 8V 6 0A MIC61300 U22 MGT 1 0V_ANA 3 0A MIC61300 U24 MGT 1 2V 3 0A Acromag Inc Tel 248 295 0310 62 www acromag com XMC 6VLX System Monitor Acromag Inc Tel 248 295 0310 USER S MANUAL The System Monitor provides information regarding the Virtex 6 device temperature and power supply conditions via JTAG and the PCle bus interface The system monitor is located in the center of the Virtex 6 die The System Monitor function is built around a 10 bit 200 kilosamples per second Analog to Digital Converter The system monitor is used to measure FPGA physical operating parameters like on chip power supply voltages and die temperature 63 www acromag com XMC 6VLX USER S MANUAL 5 0 XPS Embedded System Xilinx ISE Example Projects Acromag Inc Tel 248 295 0310 The example design consists of a Xilinx ISE project with an embedded XPS project It includes interfaces to all of the peripheral components connected to the FPGA Driv
76. guration Debug Active y Manage Configurations Build Artifact Binary Parsers Q Error Parsers MicroBlaze gcc assembler 3 General MicroBlaze gcc compiler 2 Symbols Warnings 2 Optimization 2 Debugging 3 Profiling 3 Directories 3 Miscellaneous 3 Inferred Options Software Platform 3 Processor Options SH MicroBlaze gcc linker General Libraries 3 Miscellaneous Linker Script Inferred Options Software Platform Processor Options EH MicroBlaze Print Size Xilinx ELF Check 3 Options Command All options mb as mlittle endian Expert settings Command line pattern S COMMAND S FLAGS S OUTPUT_FLAG S OUTPUT_PREFIX S OUTPUT S INPUTS l Restore Defaults Apply E Gees A Enter the highlighted text in the post build command line substituting your project name for lwip_echo_server_dual Acromag Inc Tel 248 295 0310 71 www acromag com XMC 6VLX USER S MANUAL E MN Properties for lwip_echo_server_dual pS type filter ted Settings er Ak Resource Builders C C Build Configuration Debug Active z Manage Configurations Build Variables Discovery Options Environment Y Tool Settings Build Steps Build Artifact lc Binary Parsers Error Parsers Logging Settings Pre build steps Tool C
77. hain Editor Command C C General Project References Do Run Debug Settings aa Post build steps convert ELF to SREC X Restore Defaults Apply o C L d Acromag Inc Tel 248 295 0310 72 www acromag com XMC 6VLX USER S MANUAL Build the project to produce the S record file Use the Acromag PCle 6VLX demo program pertaining to your operation system window link or VxWorks Select the Flash programming menu Within the Flash programming menu Choose the BPI FLASH Enter the path to the program lwip_echo_server_dual srec file you would like to write to the FLASH On the next power cycle the boot loader will copy the program from FLASH to DDR3 memory and execute the program from DDR3 memory Please note a modified version of the Xilinx bootloader code is embedded into the MCS file loaded into the Virtex 6 FPGA The bootloader will move program data from BPI Flash into DDR3 memory to be executed It will check the DDR3 memory for any problems with the S Record and MicroBlaze will begin executing that program If for example the LWIP program is loaded into BPI Flash and a terminal emulation program such as HyperTerminal is running power cycling the board should result in the following being displayed 7 gt O test HyperTerminal a gt i o lea a e a File Edit View Call Transfer Help De 6 0a g Testing DDR3 Memory 32 bit test PASSED SREC Bootloader Loading SREC image fro
78. he Configuration Control register at BARO 0x300100 bit 2 for control of this signal 32MB Linear BPI Flash A Linear BPI Flash memory on the board provides 32 MByte of non volatile storage that can be used for MicroBlaze program code or data storage The Linear BPI Flash shares the dual use flash data address and control pins in parallel with the XCF128 Platform Flash XL The BPI_Flash net is used to select the BPI Flash or the XCF128 Platform Flash Power on configuration is selected by the BPI_Flash net which is tied to DIP switch position 5 and is also wired to an FPGA pin DIP switch position 5 set On closed select the BPI Flash while Off open select the Platform Flash The DIP switch selection can be overridden by the FPGA after configuration by controlling the logic level of the BPI_Flash net Logic Acromag Inc Tel 248 295 0310 59 www acromag com XMC 6VLX USER S MANUAL high on this net pin selects BPI Flash device See the Configuration Control register at BARO 0x300100 bit 0 for control of this signal Configuration Flash Design Considerations JTAG Port After FPGA configuration the FPGA design can disable the configuration flash or access the configuration flash to read write code or data When the FPGA design does not use the configuration flash the FPGA design should drive the FPGA BPI_Flash pin high in order to disable the configuration Platform flash and put this flash into a quiescent low power sta
79. he in Bytes Instruction Cache Line Length Instruction Cache Base Address Instruction Cache High Address Use Cache Links for All Memory Accesses Number of Instruction Cache Streams Number of Instruction Cache Victims Frequency USER S MANUAL Data Cache Feature Size of the Data Cache in Bytes Data Cache Line Length Data Cache Base Address 0x40000000 Data Cache High Address OX4FFFFFFF Use Cache Links for All Memory Accesses Enable Write back Storage Policy Number of Data Cache Victims Area sl Performance Acromag Inc Tel 248 295 0310 83 www acromag com XMC 6VLX USER S MANUAL Set the instruction and data cache base addresses and high addresses to 0x80000000 to Ox8FFFFFFF omponent Instance Name microblaze_0 Page 5 of 6 Caches Instruction Cache Feature Size of the Instruction Cache in Bytes Instruction Cache Line Length Instruction Cache Base Address Ox80000000 Instruction Cache High Address OX8FFFEFFF Use Cache Links for All Memory Accesses Number of Instruction Cache Streams Number of Instruction Cache Victims Data Cache Feature Size of the Data Cache in Bytes Data Cache Line Length Data Cache Base Address Ox80000000 Data Cache High Address OxSFFFFFFH Use Cache Links for All Memory Accesses Enable Write back Storage Policy Number of Data Cache Victims Acromag Inc Tel 248 295 0310
80. ic requirements The following cores are included in the pcore_subdirectory axi_ethernet axi_pcie axi_enhanced_pcie axi_to_qdr_mc util_bufr_core axi_cdma util_ds_buf and util_ds buf_mgtcik These are used in the example design and will take priority over the Xilinx cores because of the Project Peripheral Repository Search Path option in the Project Options menu of the ISE tool points to this repository The AXI Ethernet pcore supplied by Xilinx includes a regional clock buffer instantiated in a lower level of the hierarchy This is okay when a single instance of the pcore is included in the design but the XMC V6 has two Ethernet ports that must be located in the same clock region There is only one regional clock buffer available in a region so instantiating two of the Xilinx supplied axi_ethernet pcores resulted in a map error The regional clock buffer had to be moved from the lower level to the top level so that it could be shared between two instances of axi_ethernet The pcore is configured for a 1000Base X physical interface at 1 Gbs This configuration is compatible with both the 1000Base X and the 1000Base T SFP modules available from Acromag A pcore was created to instantiate a regional clock buffer in XPS This clock buffer was required by the modified axi_ethernet pcore A pcore was created to instantiate an IBUFDS_GTXE1 clock buffer in XPS This clock buffer was required by the modified axi_ethernet pcore Xilinx
81. ide Interface Status oblidat 31 0 See Xilinx DS820 Memory Map 0x000F0208 31 0 a pees Upper Se E ec poc 31 0 See Xilinx DS820 Memory Map Physical Side Interface Status Control Register Read Write BARO 0x000F0144 This register provides the status of the current PHY state as well as control Table 3 18 CDMA Control Register Acromag Inc Tel 248 295 0310 of speed and rate switching for Gen2 capable cores Bit s FUNCTION Reports the current link rate 0 Ho asem 5 0 GT s Reports the current link width x1 1 x2 1 x4 pe 2 1 Oo o 8 3 Reports the current lane reversal mode No reversal as OA E Lanes 1 0 reversed Lanes 3 0 reversed Lanes 7 0 reversed 36 Reports the current Link Training and Status State Machine state Encoding is specific to the underlying Integrated Block www acromag com XMC 6VLX USER S MANUAL Reports the current PHY Link up state Link down AXI Base Address Translation Configuration Register Read Only BARO 0xF0208 0xF020C Example C code The address space for PCle is different than AXI address space To access one address space from another address space requires an address translation process These register are needed for DMA transfers that move data to system memory buffer The location of the system memory buffer is loaded into these registers AXI Base Address Translation C
82. iguration DDR3_SDRAM r axi_v6_ddrx General Purpose 10 axiZaxi_connector_O r axi2axi_connector 10 Modules microblaze_0_debug_mo r mdm Interprocessor Communication PCle_axi_intc_1 r axi_intc Memory and Memory Controller mb_axLintc_0 r axi_intc PCI axi_ahblite_bridge_0 Y axi_ahblite_bridge Peripheral Controller axi cdma_0 r axi_cdma Processor ethernet _SFP1 DMA r axi_dma Utility ethemet_SFP2_DMA ir axi_dma Verification ethernet_SFP1 iy axi_ethernet 4 Video and Image Processing ethernet_SFP2 r axi_ethernet Project Local PCores P15 PClex4 r axi_pcie Project Peripheral Repository0 ax_to_qdr_mcO tir axi_to_qdr_mc ACROMAG XMCV6 axi_timer_0 ty axi timer axi_uart16550 0 r axi_uartl6550 clack nenerntor N de clack nenerator m e 100000000000 E ORJAN a 4 ina l lt ll t Legend WMaster Slave Master Slave le Target lt Initiator Connected OUnconnected M Monitor Search IP Catalog terproduction BlLicense paid A License eval A Local Ukpre Production M Beta ADevelopment _ Superseded Discontinued Project 1P Catalog Design Summary System Assembly View EJ Graphical Design View C Console Ogx 4 WARNING EDK 2342 Search path C XMC V6 pcores axi_to_qdr mc vi_00 a directly contains drivers direc 4 WARNING EDK 4164 No Processor Interconnect selected in current selection withi
83. included C_SG_ENABLE 1 This is used by application software drivers to determine if Scatter Gather Mode can be utilized O Scatter Gather not included Scatter Gather is included DMA Internal Error This bit indicates that an internal error has been encountered by the DataMover on the data transport channel This error can occur if a O value Byte to Transfer register is fed to the AXI DataMover or DataMover has an internal processing error A Bytes to Transfer register value of O only happens if the register is written with zeros in Simple DMA mode or a Bytes to Transfer register value of 4 zero is specified in the Control word of a fetched descriptor is set to O Scatter Gather Mode This error condition causes the AXI CDMA to gracefully halt The CDMA Status register bit 1 is set to 1 when the CDMA has completed shut down A reset soft or hard must be issued to clear the error condition 0 No CDMA Internal Errors CDMA Internal Error detected CDMA Engine halts DMA Slave Error This bit indicates that an AXI slave error response has been received by the AXI DataMover during an AXI transfer read or write This error condition causes the AXI CDMA to gracefully halt The CDMA Status register bit 1 is set to 1 when the CDMA has completed shut down A reset soft or hard must be issued to clear the error condition Acromag Inc Tel 248 295 0310 28 www acromag com XMC 6VLX USER S MANUAL 0
84. includes support for PCle commands including configuration read write and memory read write In addition the PCle interface requester and or completion accesses Payload of up to 256 bytes is supported The logic also implements interrupt requests via message signaled interrupts Messages are used to assert and de assert virtual interrupt lines on the link to emulate the Legacy PCI interrupt INTA signal DDR3 Memory A 128 Meg x 64 bit of DDR3 memory is provided for user applications Four DDR3 memory devices are used to form a 64 bit data bus Each of the devices U8 U9 U10 and U11 are 128 Meg x 16 bit 2Gb in size All four device add to 8Gb or 1GByte total memory The DDR3 interface is implemented in FPGA banks 15 16 26 and 36 DCI VRP N resistor connections are implemented on banks 15 and 36 DCI functionality in bank 15 is achieved in the UCF by cascading DCI between adjacent banks as follows CONFIG DCI_CASCADE 15 16 The memory interface logic requires a set of FPGA No Connect pins These are found in the UCF as CONFIG PROHIBIT pins as follows CONFIG PROHIBIT A16 D34 F33 K16 K26 L15 N28 N33 CONFIG PROHIBIT F31 K14 On board termination devices are provided at the DDR3 device for termination of the address and data as received from the FPGA QDR II SRAM Memory A 2 Meg x 72 bit or 16MB of QDRII SRAM memory is provided for user applications Two QDRII memory devices are used to form a 72 bit data
85. ing the Acromag modified version of the SREC_BOOTLOADER program in the Xilinx SDK tool select the Optimization Level to None O0 in the C C Build Settings of the project as shown below Properties for srec bootloader 0 o aa me a type filter text Settings ea rans Resource Builders C C Build Configuration Release Active y Manage Configurations Build Variables Discovery Options Environment Tool Settings Build Steps T Build Artifact lai Binary Parsers _ Error Parsers Logging _ OO Settings a amp MicroBlaze gcc assembler Optimization Level None 00 Y D Tool Chain Editor i Other optimization flags C C General ze gec compiler I Project References Symbols Run Debug Settings 3 Warnings 3 Optimization 3 Debugging Profiling Directories Miscellaneous peripheral_ tests Runs a basic test on each other peripherals instantiated in the XPS system The results of each test are displayed on the terminal Acromag Inc Tel 248 295 0310 68 www acromag com XMC 6VLX USER S MANUAL Acromag Peripheral Repository Modifications to the AXI Ethernet Core util_bufr_core Core util_buf_ds_mgtclk Core AXI QDRII Memory Controller Modifications to the CDMA Core Modifications to the AXI PCle Core Acromag has modified a few of the Xilinx supplied peripheral cores or created custom cores to support XMC V6 specif
86. ks Figure 3 24 Platform Flash Memory Map The most significant flash address lines A22 to A16 are used to select one of 128 flash 64 Kword blocks as shown in this figure A15 to A14 are used to select one of the four 16 Kword top blocks Acromag Inc Tel 248 295 0310 FFC000 FFFFFF FF8000 FFBFFF FF4000 FF7FFF FF0000 FF3FFF FE0000 FEFFFF 010000 01FFFF 000000 OOFFFF 7FC000 7FFFFF 7F8000 7FBFFF 7F4000 7F7FFF 7F0000 7F3FFF 7E0000 7EFFFF 010000 01FFFF 000000 OOF FFF 16 Kword Block 16 Kword Block 16 Kword Block 16 Kword Block 64 Kword Block e 64 Kword Block 1 64 Kword Block 0 16 Kword Block 16 Kword Block 16 Kword Block 16 Kword Block 64 Kword Block o 64 Kword Block 1 64 Kword Block 0 42 USER S MANUAL t 128 Mbt M 256 Mbi www acromag com XMC 6VLX USER S MANUAL Flash Status Read Only BARO 0x300200 This read only register is used to read the status of the BPI or Platform flash chip The Flash Status register is at base address plus 0x300200 Status Register data is output on DQ 7 0 while 0x00 is output on DQ 15 8 Table 3 25 Flash Status Bit s Status Register Description Buffered Enhanced Factory Programming BEFP 0 BEFP is not available X BEFP is not available Block Lock Status 1 O Block not locked Block locked Program Suspend Status 2 O Program Suspend not a
87. l PCores Project Peripheral Repository ACROMAG XMCV6 G8 G amp G 4 a a A a E 4 Jfa Jla Jl Ja Ja Jl Jla Ja Ja Ja Ja Jl i E B 5 g H jeje ja jt 4 m J Legend WiMaster Slave Master Slave Target Initiator Connected OUnconnected M Monitor YrProduction license paid License eval Local Z Pre Production M2Beta Development Superseded Discontinued E Design Summary 4 System Assembly View EJ 4 Graphical Design View g O Fx 4 WARNING EDK 2342 Search path C XMC V6 pcores axi_to_ qdr mc v1 00 a directly contains drivers direc 4 WARNING EDK 4164 No Processor Interconnect selected in current selection within Bus Interface Tab Show Sub S Acromag Inc Tel 248 295 0310 79 www acromag com XMC 6VLX USER S MANUAL We will move the base address of the DDR3 SDRAM to address 0x80000000 Click in the Base Address column of the DDR3_ SDRAM row and change the 4 to 8 and then click somewhere outside of that cell EDK will calculate the new High Address Bus Interfaces Ports Addresses Instance Base Name Base Address High Address Description E microblaze_0 s Address Map E E EDK Install microblaze_0_d_bram_cntlr C_BASEADDR 0X00000000 Ox00003FFF Analog microblaze_0_i_bra
88. l transition that will generate an interrupt for each of the four possible interrupting channels A 0 bit selects interrupt on level An interrupt will be generated when the output channel level specified by the Interrupt Polarity Register occurs i e Low or High level transition interrupt A 1 bit means the interrupt will occur when a Change Of State COS occurs at the corresponding output channel i e any state transition low to high or high to low The Interrupt Type Configuration register at base address 0x30100C is used to control channels 0 through 3 as mapped in the Interrupt Enable Register For example channel 0 is controlled via data bit 0 Bits 4 to 31 are not used and will always read as O All bits are set to O following a reset which means that if enabled the Acromag Inc Tel 248 295 0310 49 www acromag com XMC 6VLX USER S MANUAL outputs will cause interrupts for the levels specified by the Interrupt Polarity Register Channel read or write operations use 8 bit 16 bit or 32 bit data transfers Note that no interrupts will occur unless they are enabled by the Interrupt Enable Register Interrupt Polarity Register Read Write BARO 0x301010 The Interrupt Polarity Register determines the level that will cause a channel interrupt to occur for each of the channels enabled for level interrupts A 0 bit specifies that an interrupt will occur when the corresponding output
89. lized by system software at power up to configure the card The board is a Plug and Play PCle card As a Plug and Play card the board s base address and system interrupt request are not selected via jumpers but are assigned by system software upon power up via the configuration registers A PCle bus configuration access is used to read write the PCle card s configuration registers When the computer is first powered up the computer s system configuration software scans the PCle bus to determine what PCle devices are present The software also determines the configuration requirements of the PCle card The system software accesses the configuration registers to determine how many blocks of memory space the module requires It then programs the board s configuration registers with the unique memory base address Since this board is relocatable and not fixed in address space its device driver must use the mapping information stored in the board s Configuration Space registers to determine where the board is mapped in memory space The configuration registers are also used to indicate that the board requires an interrupt request The system software then programs the configuration registers with the interrupt request assigned to the board CONFIGURATION REGISTERS The PCle specification requires software driven initialization and configuration via the Configuration Address space This board provides 512 bytes of configuration register
90. llator 200MHz U3 Frequency Stability 0 00315 or 31 5ppm Board Crystal Oscillator 48MHz U3 Frequency Stability 0 0050 or 50ppm 128 Meg x 16 bit Micron Device MT41J128M16HA 15EIT uses a double data rate architecture Four MT41J128M16HA 15EIT memory devices U8 U9 U10 and U11 are used to form a 64 bit data bus 128 Meg x 16 bit 2Gb each device 8Gb 1GB total all four devices together DDR3 memory devices are wired to FPGA banks 15 16 26 and 36 DCI VRP N resistor connections are implemented on banks 15 and 36 DCI functionality in bank 15 is achieved in the UCF by cascading DCI between adjacent banks as follows CONFIG DCI_CASCADE 15 16 The memory interface logic require a set of FPGA No Connect pins These are found in the UCF as CONFIG PROHIBIT pins as follows CONFIG PROHIBIT A16 D34 F33 K16 K26 L15 N28 N33 CONFIG PROHIBIT F31 K14 Two CY7C1565KV18 400BZI memory devices U12 and U13 are used to form a 72 bit data bus 2 Meg x 36 bit Cypress CY7C1565KV18 400BZI memory QDR II are Acromag Inc Tel 248 295 0310 107 www acromag com XMC 6VLX 16MB Platform Flash 32MB Linear BPI Flash PCIe Bus Interface USER S MANUAL synchronous pipelined Burst SRAMs equipped with separate read and write ports 2 Meg x 36 bit 72Mb each device 144Mb 18MB total both devices together QDRII memory devices are wired to FPGA banks 13 22 23 32 and 33 DCI VRP N resistor connections
91. lows an interrupt after completed DMA transfers ds oo Interrupt on Complete Disabled Interrupt on Complete Enabled Interrupt on Delay Timer Interrupt Enable When set to 1 it allows a delayed interrupt out This is only used with Scatter 13 Gather assisted transfers o Delayed Interrupt Disabled Delayed Interrupt Enabled Interrupt on Error Interrupt Enable When set to 1 it allows 14 an error to generate an interrupt out oOo Error Interrupt Disabled Acromag Inc Tel 248 295 0310 26 www acromag com XMC 6VLX USER S MANUAL 1 Error Interrupt Enabled Reserved Interrupt Threshold value This field is used to set the Scatter Gather interrupt coalescing threshold When Interrupt On Complete interrupt events occur an internal counter counts down from the Interrupt Threshold setting When the count reaches zero an interrupt out is generated by the CDMA engine Note The minimum setting for the threshold is 0x01 A write of 0x00 to this register has no effect If the CDMA is built with Scatter Gather disabled Simple Mode Only the default value of the port is zeros Interrupt Delay Time Out This value is used for setting the interrupt delay time out value The interrupt time out is a mechanism for causing the CDMA engine to generate an interrupt after the delay time period has expired This is used for cases when the interrupt threshold is not met after a period of time and the CPU desires a
92. ltage CMOS in the user constraints file The tables included in the Rear Input Data Register and Rear Output Data Register sections can be used to map the LVCMOS signal to the signal names given in the table below The rear I O can alternatively be defined for LVDS_25 Low Voltage Differential Signaling in the user constraints file The 2 5 volt lOStandards available are listed in the Virtex 6 User Guide available from Xilinx As LVDS signal pairs the signals can be grouped as 32 LVDS I O pairs The LVDS pairs are arranged in the same row in table 2 2 For example RIO1_P and RIO1_N form a signal pair The P identifies the Positive input while the N identifies the Negative input z Positive Pin Description Pin Negative Pin Description Pin RIOO_GCLK_P 1 3 RIO1_P 2 4 RIO2_P 5 7 RIO3_P 8 RIO4 N 10 12 13 RIO6N 16 19 RO9 P _ 18 RO9N 20 23 24 27 28 31 32 35 36 39 40 43 44 45 47 R023 P _ E ROR N ES RO24 P a9 ROa4 Nn O51 52 55 56 OSD INI DIWMJBRIWIN R Ola NINININININ IN eB a e fa PR e e je e ajujsjwin i ejo wojojujo jun ajw n eajo N N Acromag Inc Tel 248 295 0310 13 www acromag com XMC 6VLX USER S MANUAL 29 RIO29 P 58 RO N Jeo 31 RIO31_GCLK_P 62 RIO31_GCLK_N 64 This connector is a 64 pin female receptacle header AMP 120527 1 or equivalent which mates to the male connector on the carrier board AMP 120521 1 or equivalent
93. m flash address 00000000 Executing program Sier Hng at address 00000000 lwIP TCP echo server TCP packets sent to port 7 will be echoed back SFP1 Board IP 192 168 1 10 Netmask 255 255 255 128 Gateway 192 168 1 1 SFP2 Board IP 192 168 1 138 Netmask 255 255 255 128 Gateway 192 168 1 1 7 link speed 1000 link speed 1000 TCP echo server started port 7 Connected 1 10 52 Auto detect 9600 8 N 1 NUM es M M 4 Acromag Inc Tel 248 295 0310 73 www acromag com XMC 6VLX Running LWIP Echo Server USER S MANUAL This section describes some helpful tips on how to run the Echo Server program As mentioned above in the lwip_echo_server_dual description of the SDK project the network adaptor settings on the host PC s need to be modified The hardware will support both SFP modules to work at the same time In a Windows OS simply access the Local Area Connection Properties and modify the Internet Protocol Version 4 TCP IPv4 settings to the following SFP1 E Internet Protocol Version 4 TCP 1Pv4 Properties Bs General You can get IP settings assigned automatically if your network supports this capability Otherwise you need to ask your network administrator for the appropriate IP settings 5 Obtain an IP address automatically Use the following IP address IP address 192 168 1 10 Subnet mask 255 255 255 128 Default gateway 192 168
94. m reset Bit s Aurora Monitor Register Aurora Reset Control 0 0 Removed from Reset Held in Reset 1 Reserved Channel UP 2 0 Loopback Channel is down Loopback Channel is up 3 15 Reserved Link 16 23 O Linkis down Link is up Reserved 24 31 o Write logic low has no effect 1 Write logic high has no effect The BPI flash memory has 32M bytes of program code or data storage available The Platform flash memory has 16M bytes of program code storage available The system CPU provides control of all in system read write and erase operations for both the BPI flash and the Xilinx Platform flash devices via the PCle bus The on chip FPGA logic automatically executes the algorithms and timings necessary for block erase and program A Status Register indicates erase or program completion and any errors that may have occurred The BPI flash device has 256 individual erasable memory blocks each 64K words deep The Platform flash device has 128 individual erasable memory blocks each 64K words deep See the memory maps for both flash memory devices below The least significant 16 bits A15 to AO are used to select the 64K words of each block www acromag com XMC 6VLX Figure 3 23 BPI Flash Memory Map The most significant flash address lines A23 to A16 are used to select one of 256 flash 64 Kword blocks as shown in this figure A15 to A14 are used to select one of the four 16 Kword top bloc
95. m_cntlr C_BASEADDR 0X00000000 0x00003FFF Bus and Bridge mb_axi_intc_0 C_BASEADDR 0x00020000 0x0002FFFF Clock Reset and Interrupt microblaze_0_debug_module C_BASEADDR 0x00030000 0x0003FFFF Communication High Speed axi_timer_0 C_BASEADDR 0x00040000 Ox0004FFFF Communication Low Speed axi_uartl6550_0 C_BASEADDR 0x00050000 Ox0005FFFF E DMA and Timer ethernet_SFP1_DMA C_BASEADDR 0x00060000 Ox0006FFFF H Debug ethernet_SFP2_DMA C_BASEADDR 0x00070000 0x0007FFFF FPGA Reconfiguration ethernet_SFP1 C_BASEADDR 0x00200000 0x0023FFFF General Purpose IO ethernet_SFP2 C_BASEADDR 0x00240000 0x0027FFFF amp IO Modules axi_ahblite_bridge_0 C_BASEADDR 0x00300000 Interprocessor Communication axi2axi_connector_0 C_S_AXT_RINGOO Memory and Memory Controller DDR3_SDRAM C_S_AXI_BASEA E PCI E Unmapped Addresses Peripheral Controller axi_to_qdr_mc_0 C_BASEADDR 0x30000000 Processor axi_cdma_0 C_BASEADDR 0x000A0000 0x000AFFFF Utility PCle_axi_intc_1 C_BASEADDR 0x00100000 Ox001 0FFFF Verification P15_PClex4 C_AXIBAR_0 0x01000000 0x01 FFFFFF Video and Image Processing P15_PClex4 C_BASEADDR Ox000F0000 OXDO0FFFFF Project Local PCores E Project Peripheral Repository0 ACROMAG XMCV6 a Ja Ja lle Ja Ja Jia Ja Ja Ja Jia Jia Jia 4 4 4 jajja 4 j r Legend MiMaster Slave Master
96. mber is 5028 452 DESCRIPTION Up to 2 125 Gb s bi directional data links Duplex LC connector SPECIFICATIONS Up to 500m on 50 125um MMF Multi Mode Fiber 300m on 62 5 125um MMF 850nm Oxide VCSEL laser Less than 500mW power dissipation Operating Temperature Range 40 C to 85 C APPLICATIONS 1 25 Gb s 1000Base SX Ethernet Dual Rate 1 063 2 125 Gb s Fibre Channel Acromag Inc Tel 248 295 0310 114 www acromag com XMC 6VLX USER S MANUAL Acromag Inc Tel 248 295 0310 115 www acromag com XMC 6VLX Certificate of Volatility USER S MANUAL Certificate of Volatility Acromag Model XMC 6VLX240F E Manufacturer Acromag Inc XMC 6VLX365F E 30765 Wixom Rd Wixom MI 48393 Volatile Memory Does this product contain Volatile memory i e Memory of whose contents are lost when power is removed m Yes No Type SRAM SDRAM etc size User Modifiable Function Process to Sanitize SRAM m Yes Data storage for Power Down 2 Meg x No FPGA 72 bit Type SRAM SDRAM etc Size User Modifiable Function Process to Sanitize FPGA based RAM 128 Meg x m Yes Data storage for Power Down 64 bit No FPGA Non Volatile Memory Does this product contain Non Volatile memory i e Memory of whose contents is retained when power is removed m Yes No Type EEPRO
97. mitter The Acromag part number is 5028 452 Drawing provided in the accessories section at the end of this manual Acromag Inc Tel 248 295 0310 10 www acromag com XMC 6VLX USER S MANUAL 2 0 PREPARATION FOR USE Unpacking and Inspecting XT Wy CAUTION SENSITIVE ELECTRONIC DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS WARNING This board utilizes static sensitive components and should only be handled at a static safe workstation Card Cage Considerations Board Installation Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power R
98. n Bus Interface Tab Show Sub S lt El console UN Warnings Errors Acromag Inc Tel 248 295 0310 81 www acromag com XMC 6VLX USER S MANUAL Click Next 4 times to arrive at the Caches page Update the instruction and data cache base and high addresses to align with the new address for DDR3 SDRAM omponent Instance Name __ microblaze_0 Micro3laze Configuration Wizard Welcome to MicroBlaze Configuration Wizard e Select a predefined configuration in the list to the left Information about the selected configuration is shown below Fach predefined configuration completely changes the MicroBlaze parameters e To modify the configuration dick on the Mexfbutton dick on Advanced to Q Maximum Performance directly access parameters in a tabbed interface or dick on OK to accept the configuration and dose the dialog AE Maaa Egy E Select implementation to optimize area with lower instruction throughput A Linux with MMU Enable Debug Use Instruction and Data Caches Y Enable Exceptions amp Typical Use Memory Management Minimum Area 6 A Low end Linux with MMU Acromag Inc Tel 248 295 0310 82 www acromag com XMC 6VLX The cacheable address range is currently set to Ox40000000 to Ox4FFFFFFF omponent Instance Name microblaze_0 Page 5 of 6 Caches Instruction Cache Feature Size of the Instruction Cac
99. n interrupt to be 31 24 generated Timer begins counting when the CDMA is IDLE CDMA Status bit 1 1 This generally occurs when the CDMA has completed all scheduled work defined by the transfer descriptor chain reached the tail pointer and has not satisfied the Interrupt Threshold count Note Setting this value to zero disables the delay timer interrupt 15 23 16 Acromag Inc Tel 248 295 0310 27 www acromag com XMC 6VLX USER S MANUAL CDMA Status Register Read Write BARO 0x000A0004 This register provides status of the AXI CDMA Table 3 10 CDMA Status Bit s FUNCTION Register 0 This bit is reserved for future definition and will always return zero CDMA Idle Indicates the state of AXI CDMA operations When set and in Simple DMA mode the bit indicates the programmed transfer has completed and the CDMA is waiting for a new transfer to be programmed Writing to the Bytes to Transfer register in Simple DMA mode causes the CDMA to start not Idle 1 When set and in Scatter Gather mode the bit indicates the Scatter Gather Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed Writing to the tail pointer register automatically restarts CDMA Scatter Gather operations O Not Idle CDMA is Idle 2 Reserved Scatter Gather Included This bit indicates if the AXI CDMA has been implemented with Scatter Gather support
100. n the Interrupt Enable register Table Set Interrupt Enable Register Write BARO 0x00100010 Set Interrupt Enable register is a location used to set Interrupt Enable register bits in a single atomic operation rather than using a read modify write sequence Writing a 1 to a bit location in the Set Interrupt Enable register will set the corresponding bit in the Interrupt Enable register Writing Os does nothing as does wiring a 1 to a bit location that corresponds to a non existing interrupt input The bit locations in the Set Interrupt Enable correspond with the bit locations given in the Interrupt Enable register Table Acromag Inc Tel 248 295 0310 23 www acromag com XMC 6VLX USER S MANUAL Clear Interrupt Enable Register Write BARO 0x00100014 Clear Interrupt Enable register is a location used to clear Interrupt Enable register bits in a single atomic operation rather than using a read modify write sequence Writing a 1 to a bit location in Clear Interrupt Enable register will clear the corresponding bit in the Interrupt Enable register Writing Os does nothing as does wiring a 1 to a bit location that corresponds to a non existing interrupt input The bit locations in the clear Interrupt Enable correspond with the bit locations given in the Interrupt Enable register Table Interrupt Vector Register Read BARO 0x00100018 The Interrupt Vector register is a read only register and
101. nd output from the ADC can be converted to voltage by using the following equation ADC code 1024 Supply Volag amp volts 3V System Monitor Address Register Write Only BARO 0x300304 This write only register is used to set the system monitor address register with a valid address for the System Monitor internal status or control registers Valid addresses are given in the following table Additional addresses can be found in the Xilinx System Monitor document UG370 available from Xilinx Writing this register is possible via 32 bit data transfers The address value written to this register can be read on bits 22 to 16 of the System Monitor Status Control register at BARO plus 0x300300 Table 3 27 System Monitor Address Status Register Register Map 0x00 Temperature 0x01 Vccint 0x02 Vccaux 0x20 Maximum Temperature 0x21 Maximum Vccint 0x22 Maximum Vccaux 0x24 Minimum Temperature 0x25 Minimum Vccint 0x26 Minimum Vccaux Acromag Inc Tel 248 295 0310 47 www acromag com XMC 6VLX USER S MANUAL Front Input Data Register Read Only BARO 0x301000 The front I O can also be configured as differential channels with 2 global clock signal pairs Table 3 28 BARO Front Input Data Register Note that any registers bits not mentioned will remain at the default value logic low The front input data register is used to access the individual input channels Th
102. nnnnos 23 Clear Interrupt Enable Register Write BARO OX00100014 occcocnccnonccnnccoooccnononanoconononoconnnnnoonnnnncnnns 24 Interrupt Vector Register Read BARO OX00100018 cccccescccessececsssseceesececeesaeeecssseeeeesseeeeeeaaes 24 Master Enable Register Read Write BARO OXOO10001C cccesceessecsseceeseecsseceeseecssecesseecsseeeseees 24 AXECDOMA Sara te scaaes concacnees suetes coucucnscwsouaes soucens oa sew tas cosaeneswussaes toucacescasuwtees 25 CDMA Control Register Read Write BARO OXOOOAOOOO ccccccssecesseeessecesseeessecesseecsseceseecsaeeeees 26 CDMA Status Register Read Write BARO OXOOOAQO0A cceccccssecessseessecesseecsseceseecsseceseeeesseceees 28 CDMA Current Descriptor Pointer Register Read Write BARO OxOOOAO008 oooccocccocccoccconocononnnonos 31 CDMA Tail Descriptor Pointer Register Read Write BARO OxOOOA0010 ccsccessseessecesseeessecees 32 CDMA Source Address Register Read Write BARO OXOOOA0018 ooooocococonoccconnnonanoconnnonanoconanonanonnnos 33 CDMA Destination Address Register Read Write BARO OXDODADO20 cescccssecesseeesseceseeeeseeeees 33 CDMA Bytes to Transfer Register Read Write BARO OXOOOA0028 ocoooconcccnocnnonancconanonanocananonanonnnos 34 Simple CDMA Programming Example ccccccccsessscccccecsessssscecceececseesaesecseseseeaseseesceeseseaaeseeseeceeseaaeaeeeeeees 34 A
103. ns is organized into what is referred to as a transfer descriptor chain Each descriptor has an address pointer to the next sequential descriptor to be processed The last descriptor in the chain generally points back to the first descriptor in the chain but it is not required The AXI CDMA Tail Descriptor Pointer register needs to be programmed with the address of the first word of the last descriptor of the chain When the AXI CDMA executes the last descriptor and finds that the Tail Descriptor pointer matches the address of the completed descriptor the Scatter Gather Engine stops descriptor fetching and waits See the Xilinx DS792 data sheet for the AXI Central Direct Memory Access for additional details for Scatter Gather operations BARO Base Addr Bit s Description 0x000A0000 31 0 CDMA Control Register 0x000A0004 31 0 CDMA Status Register 0x000A0008 31 0 Current Descriptor Pointer Register 0x000A000C 31 0 Reserved 0x000A0010 31 0 Tail Descriptor Pointer Register 0x000A0014 31 0 Reserved 0x000A0018 31 0 Source Address Register 0x000A001C 31 0 Reserved 0x000A0020 31 0 Destination Address Register 0x000A0024 31 0 Reserved 0x000A0028 31 0 Bytes to Transfer Register 25 www acromag com XMC 6VLX USER S MANUAL CDMA Control Register Read Write BARO 0x000A0000 This register provides software application control of the AXI CDMA Table 3 9 CDMA Control Bit s
104. nt I O Acromag Inc Tel 248 295 0310 6 www acromag com XMC 6VLX Table 1 1 The XMC 6VLX boards are available in the standard temperature range Key Features USER S MANUAL MODEL OPERATING TEMPERATURE RANGE XMC 6VLX240F 0 C to 70 C XMC 6VLX365F 0 C to 70 C An XMC 6VLX block diagram found at the end of this manual illustrates the key features listed below Acromag Inc Tel 248 295 0310 Reconfigurable Xilinx FPGA In system configuration of the FPGA is performed through flash configuration The PCle bus can be used to change the flash configuration memory This provides a means for creating custom user defined designs The Virtex 6 will configure from the updated Platform flash on the next power cycle QDRII SRAM Provides 2 Meg x 72 bit QDRII SRAM SRAM is linked to the Virtex 6 device for PCle bus and DMA engine access It can also be linked to front rear and high speed data path access DDR3 SDRAM Provides 128 Meg x 64 bit DDR3 SDRAM SDRAM is linked to the Virtex 6 device for MicroBlaze and Ethernet access P15 High Speed Interface The Eight high speed serial lanes are allocated to the XMC P15 connector These lanes can be used for an 8 lane PCle PCI Express implementation Serial RapidlO or 10 Gigabit Ethernet The example design will support a 4 lane Gen 1 PCle implementation P16 High Speed Interface The Eight high speed serial lanes are allocated to the
105. nterrupt controller contains programmer accessible registers that allow interrupts to be enabled queried and cleared under software control over the PCle bus interface BARO Base Addr Bit s Description Table 3 3 Interrupt Controller Registers 0x00100000 31 0 Interrupt Status Register mentioned Wit Eman arme 0x00100008 31 0 Interrupt Enable Register default value logic low 0x0010000C 31 0 Interrupt Acknowledge Register 0x00100010 31 0 Set Interrupt Enable Register 0x00100014 31 0 Clear Interrupt Enable Register 0x00100018 31 0 Interrupt Vector Register 0x0010001C 31 0 Master Enable Register Interrupt Status Register Read Write BARO 0x00100000 This Interrupt Status register ISR at BARO base address offset 0x100000 is used to monitor board interrupts When read the contents of this register indicate the presence or absence of an active interrupt for each of the active interrupting sources Each bit in this register that is set to a 1 indicates an active interrupt signal on the corresponding interrupt input Bits that are O are not active The bits in the ISR are independent of the interrupt enable bits in the Interrupt Enable register Interrupts even if not enabled can still show up as active in the ISR Table 3 4 Interrupt Status Bit s FUNCTION Register This bit when set indicates a Xilinx Fabric interrupt from the Front I O interface See the Front I O i
106. nterrupt section for 0 source of this interrupt Disabled Enabled This bit when set indicates an AXI CDMA interrupt See the CDMA section for source of this interrupt 1 0 Disabled 1 Enabled Reserved 31 2 oO NA 1 NA Acromag Inc Tel 248 295 0310 21 www acromag com XMC 6VLX USER S MANUAL The ISR register is writable by software only until the Hardware Interrupt Enable bit in the MER has been set Given these restrictions when this register is written to any data bits that are set to 1 will activate the corresponding interrupt just as if a hardware input became active Data bits that are zero have no effect This allows software to generate interrupts for test purposes Interrupt Pending Register Read BARO 0x00100004 This Interrupt Pending register IPR at BARO base address offset 0x100004 is used to monitor board interrupts Reading the contents of this register indicates the presence or absence of an active interrupt signal that is also enabled Each bit in this register is the logical AND of the bits in the Interrupt Status register and the Interrupt Enable register Table 3 5 Interrupt Pending Bit s FUNCTION Register This bit when set indicates a Xilinx Fabric interrupt from the Front I O interface See the Front I O interrupt section for 0 source of this interrupt o Disabled Enabled This bit when set indicates an AXI CDMA interrupt See the 1 CDMA section for
107. o comply with EMC Directive 2004 108 EC Class B Radiated Field Immunity RFI Complies with IEC 61000 4 3 with no register upsets Conducted R F Immunity CRFI Complies with IEC 61000 4 6 with no register upsets Surge Immunity Not required for signal I O per IEC 61000 4 5 Acromag Inc Tel 248 295 0310 104 www acromag com XMC 6VLX USER S MANUAL Electric Fast Transient EFT Immunity Complies with IEC 61000 4 4 Level 2 0 5KV at field I O terminals Electrostatic Discharge ESD Immunity Complies with EN61000 4 2 Level 3 8KV enclosure port air discharge Level 2 4KV enclosure port contact discharge Radiated Emissions Meets or exceeds European Norm 61000 6 3 2007 for class B equipment Shielded cable with I O connections in shielded enclosure is required to meet compliance User Programmable U2 FPGA XC6VLX240T 1FF1156 e 241 152 Logic Cells e 3 650 Kbit Distributed RAM e 416 36 Kbit Block RAMs e 768 DSP48E1 Slices e 12 Mixed Mode Clock Managers e 2 Interface Blocks for PCI Express e 4 Ethernet MACs XC6VLX365T 1FF1156 e 364 032 Logic Cells e 4 130 Kbit Distributed RAM e 416 36 Kbit Block RAMs e 576 DSP48E1 Slices e 12 Mixed Mode Clock Managers e 2 Interface Blocks for PCI Express 4 Ethernet MACs EDK Example Design Xilinx XC6VLX240T 1FF1156 Resource Usage e Slice Registers 64 465 Used 301 440 Available 21 Utilization e Slice LUTs 68 276 Used 150 720 Available 45 Utilization e MMCMs 4 Used 12 A
108. ocncoconocnnoconncononononononnnnnoconanononannnccnnnnos 48 Front Output Data Register Read Write BARO 0X301004 ccsccccssecsssceeseecsseceeseecssecesseecsseeeeees 48 Front I O Interrupt Enable Register Read Write BARO OX301008 ooooccnoccnocnnononcconnnononcconanoninncnnnnos 49 Interrupt Type COS or H L Configuration Register Read Write BARO Ox30100C ocooncccnccnoncconnos 49 Interrupt Polarity Register Read Write BARO O0X301010 ccc cescccssccsseceeseecsseceeseecsseceeseecsseeeseees 50 Rear Input Data Register Read Only BARO 0X301100 oocooconcccococcconocnnoconcconononnnoconannncconnnoconononccnnnnos 51 Rear Output Data Register Read Write BARO 0X301104 cceccscccssccsseceeseecssecesseecsseceeseecsseceseees 52 P16 Input Data Register Read Only BARO 0x301200 cccooconcncococcconocnnoconoconononnnccononnncconnncnonononcconanos 53 P16 Output Data Register Write Only BARO 0x301204 ooooocccoccccconccnnoconnnononononcconnnnnconnnncnnnnnnnccnnnnns 54 BAR2 MEMORY MAP sccsccscsscscescsscsccacescncetasscsecscescvactassdeddeces csaetassesececes oseedesdssesscseavaetasesvensss 55 QDR Memory Read Write BAR2 0x0000000 to OXOOFFFFFF cessccessecessseessecesseecssecesseecsseeeees 55 4 0 THEORY OF OPERATION isso OO PCI INTERFACE LOGIC wv ccscssidescossivcccnccscssutecasceocnesssse snes ev vachcesseechessebeSeenestecuentede suse tdeectoltsdesneat
109. of buffer of 0x0000333012345678 b AXIBAR2PCIEBAR_OU lt offset OOOFO208 gt 0x00003330 c AXIBAR2PCIEBAR_OL lt offset OOOFO20C gt 0x12345678 d The least significant 24 bits of this address 0x12345678 must be removed and added to the AXI BARO Aperture Base address The new AXI address is Ox01000000 0x00345678 0x01345678 Write 0x01345678 to OxA0020 5 Write the number of bytes to transfer to the CDMA Bytes to Transfer register OxA0028 Writing this register also starts the transfer 6 Either poll the CDMA Status register bit 1 for logic 1 or wait for the CDMA to generate an interrupt if enabled 7 Clear the interrupt if generated by writing a 1 to bit 12 CDMA Status Acromag Inc Tel 248 295 0310 34 www acromag com XMC 6VLX USER S MANUAL register 8 Ready for another transfer Go back to step 1 AXI BARO Aperture Base Address The AXI BARO aperture base address of 0x01000000 is set as the base address on the AXI bus used to reach system host memory for CDMA transfers The address 0x01000000 is the AXI BARO Aperture Base address In the Xilinx Platform Studio the address map will show that a 16Meg address space for the AXI BARO Aperture Base Address is reserved Table 3 16 AXI BARO Aperture Window into PCle Interface Base Address 0x01000000 gt 0x01FFFFFF 16M AXI BARO Aperture Base Address The following is an example of how the AXI BARO aperture base address is use
110. onfiguration register at BARO OxFO208 must be written with the most significant 32 bits of the address in system memory to which the DMA transfer is to read or write An example of the c code used to set this register with the physical address is shown below AXI Base Address Translation Configuration register at BARO OxFO20C must be written with the least significant 32 bits of the address in system memory to which the DMA transfer is to read or write An example of the c code used to set this register with the physical address is shown below Hdefine AXI2PCIeBAR_0U DWORD u64BaseAddress OxF0208 Hdefine AXI2PCIeBAR_OL DWORD u64BaseAddress 0xF020C Status PCle6VLX_DmaGetBuffPhysAddress iHandle amp u64PhyAddr AXI2PCleBAR_OU DWORD u64PhyAddr gt gt 32 AX 2PCleBAR_OL DWORD u64PhyAddr amp Oxffffffff This sets the system memory physical address which will be appended with the values written into either the DMA source or destination registers at 0xA0018 or OxA0020 respectively See the example in the CDMA section for additional details Acromag Inc Tel 248 295 0310 37 www acromag com XMC 6VLX FPGA Fabric MEMORY MAP USER S MANUAL The BARO FPGA Fabric memory address space is used to access the Flash Configuration Front Rear and P16 I O registers and System Monitor registers This memory space contains FPGA functions implemented in the FPGA fabric All other logic is implemented using
111. or CDMA Engine halts Scatter Gather Decode Error This bit indicates that an AXI decode error has been received by the Scatter Gather Engine during an AXI transfer transfer descriptor read or write This error occurs if the Scatter Gather Engine issues an address that does not have a mapping assignment to a slave device 10 This error condition causes the AXI CDMA to gracefully halt The CDMA Status register bit 1 is set to 1 when the CDMA has completed shut down A reset soft or hard must be issued to clear the error condition 0 No Scatter Gather Decode Errors Scatter Gather Decode Error CDMA Engine halts 11 Reserved Acromag Inc Tel 248 295 0310 29 www acromag com XMC 6VLX USER S MANUAL Interrupt on Complete When set to 1 this bit indicates an interrupt event has been generated on completion of a DMA transfer either a Simple or Scatter Gather If the Interrupt on Complete bit 12 of the CDMA Control register 1 an interrupt is generated from the AXI CDMA A CPU write of 1 clears this bit to O Note When operating in Scatter Gather mode the criteria specified by the interrupt threshold must also be met i oS No IOC Interrupt IOC Interrupt active Interrupt on Delay When set to 1 this bit indicates an interrupt event has been generated on a delay timer time out If the Interrupt on Delay Timer bit 13 of the CDMA Control 13 register 1 an interrupt is generated from the AXI CDMA A
112. pace is used to provide read or write access to on board QDR memory This memory space allows access to the QDR directly from the Virtex 6 FPGA The memory device has a 2 Meg x 72 bits memory configuration Reading or writing to this memory space using DMA access is also possible as 64 bit transfers Acromag Inc Tel 248 295 0310 55 www acromag com XMC 6VLX USER S MANUAL 4 0 THEORY OF OPERATION This section contains information regarding the design of the board A description of the basic functionality of the circuitry used on the board is also provided Refer to the XMC 6VLX Block Diagram shown below as you review this material Figure 4 1 XMC 6VLX Block Diagram 11 LVDS Pairs amp 2 Global Clock Pairs X8 341 0 x4 x4 hardware amp hardware hardware example 2 Global example example design Clock design design Pairs Aurora Aurora JTAG x4 PCle Gen 1 30 LVDS pairs amp 2 Global Clock Pairs www acromag com 56 Acromag Inc Tel 248 295 0310 XMC 6VLX USER S MANUAL PCI INTERFACE LOGIC The Acromag example design PCle bus interface logic on this board provides a 2 5Gbps interface to the carrier CPU board per PCI Express Specification v2 0 The interface to the carrier CPU board allows control of example design board functions The PCle bus endpoint interface logic is contained within the Virtex 6 FPGA This logic
113. raints E Pinout Report E Clock Report Static Timi E XPS Errors and Warnings E Platgen Messages C Simgen Messages El Bitinit Messages B XPS Reports Z Platgen Log File C Simgen Log File E Bitlnit Log File C System Log File Es Errors and Warnings E Parser Messages E Synthesis Messages E Translation Messages E Map Messages E Place and Route Messages E Timing Messages E Design Overview a XMC 6VLX240F xise system_top xc6vlx240t 2fF1156 ISE 14 1 Balanced Xilinx Default unlocked System Settings No Errors Programming File Generated No Errors 3463 Warnings 4 new All Signals Completely Routed All Constraints Met Platgen LogFile Wed Sep 5 13 56 10 2012 Simgen Log File BitInit Log File Tue Sep 18 14 38 54 2012 Design Properties Y Enable Message Filtering Optional Design Summary Contents Show Clock Report Show Failing Constraints E Show Warnings E Show Errors System Log File Number of Slice Registers Number used as Flip Flops Number used as Latches Eg Design C Files Libraries Number used as Latch thrus Launching Design Summary Report Viewer Started XPS to edit system xmp Xilinx Platform Studio Xilinx EDK 14 1 Build EDK P 15xf Copyright c 1995 2012 Xilinx Inc All rights reserved Launching XPS GUI
114. rase flash chip Return to main menu Enter selection 16 Display PCI configuration registers Select 2 Other and enter the path to the lwip_echo_server_dual srec file CAXMC VENXMIC 6VLX240FAISDKAlwip_echo_server_duallReleasellwip_echo_server_dual srec a PCle6VLXDemo ex 6UL amp Flash menu Toggle selected flash device Flash status details Clear flash status Read flash word Read flash block Write flash word Write flash block Write code file to flash Erase flash block Erase flash chip 99 Return to main menu Enter selection 8 WONKA Ly o jt Select code file 1 Example design for 6ULX24 F C Acromag PCISW_API_WIN64 conf ig_f iles 6ULK24 6F srec 2 Other Enter selection 2 se lwip_echo_server_dual srec Acromag Inc Tel 248 295 0310 100 Enter complete file path C RMC U6 RMC 6ULK246F SDK lwip_echo_server_dual Relea www acromag com XMC 6VLX USER S MANUAL After the programming operation is complete enter 99 twice and answer Y to exit the program 2 Enter selection 2 Enter complete file path C XMC U6 KMC 6ULK24QF SDK lwip_echo_server_dual Relea se lwip_echo_server_dual srec Writing file to flash lt This can take several minutes gt Complete 397664 code bytes written 6ULK Flash menu Toggle selected flash device Flash status details Clear flash status Read flash word Read flash block Write flash word Write flash
115. rate File Generate Succeeded 0x007F_FFFF PROM File Formatter Console Total configuration bit size 73859552 bits Total configuration byte size 9232444 bytes J INFO Bitstream 181 The start address provided has been multiplied by a factor of 2 due to the use of the x16 data width Ox8ce03c 9232444 bytes loaded up from 0x0 Using user specified prom size of 16384K Writing file C XMC V6 XMC 6VLX240F XMC 6VLX240F mcs Writing file C XMC V6 XMC 6VLX240F XMC 6VLX240F prm Writing file C XMC V6 XMC 6VLX240F XMC 6VLX240F cfi PROM File Generation Target Parallel PROM 73 859 552 Bits used File XMC 6VLX240F in Locatio Acromag Inc Tel 248 295 0310 92 www acromag com XMC 6VLX USER S MANUAL In this step the updated bitstream will be written to the platform FLASH on the XMC V6 A Platform USB II cable or equivalent must be connected to the JTAG port Right Click on the FLASH device attached to the FPGA in the diagram Select Program from the pop up menu iMPACT will likely report a failure message the first time Select Program a second time fe DOHA BaEaxke aa FN IMPACT Flows EE Right click device to select operations H qe Boundary Scan SystemACE B Create PROM File PROM File Formatter a WebTalk Data iMPACT Processes Available Operations are E ES Console Total configuration bit size 73859552 bits Total con
116. rdware Interrupt Enable bits All other bits will read as Os Table 3 7 Master Enable Bit s FUNCTION Register Master IRQ Enable i All Interrupts Disabled All Interrupts Enabled Hardware Interrupt Enable 1 o Software Interrupts Enabled Hardware Interrupts Only Enabled 31 2 Not Used bits are read as logic 0 Acromag Inc Tel 248 295 0310 24 www acromag com XMC 6VLX AXI CDMA Table 3 8 AXI CDMA Registers Note that any registers bits not mentioned will remain at the default value logic low Acromag Inc Tel 248 295 0310 USER S MANUAL The AXI Central Direct Memory Access CDMA core is a soft Xilinx Intellectual Property core The CDMA provides direct memory access between system memory on the PCle bus and the memory resident on the XMC 6VLX The basic mode of operation for the CDMA is Simple DMA In this mode the CDMA executes one programmed DMA command and then stops This requires that the CDMA registers need to be set up by system software over the PCle bus for each DMA operation required Scatter Gather is a mechanism that allows for automated DMA transfer scheduling via a pre programmed instruction list of transfer descriptors Scatter Gather Transfer Descriptor Definition This instruction list is programmed by the user software application into a memory resident data structure that must be accessible by the AXI CDMA Scatter Gather interface This list of instructio
117. return to use of the Acromag design example You can reload the Acromag example design via the EDK board and the JTAG port using the Xilinx iMPACT tool Upon power up the example design provided by Acromag will again be loaded into the FPGA See the Flash Configuration section for a description of the steps required to write new data or to reprogram the example design code to the Platform flash device Registers are provided in the FPGA Programming Memory Map to implement Platform or BPI flash erase and reprogram operations 16 www acromag com XMC 6VLX USER S MANUAL Virtex 6 Configuration The XMC 6VLX board supports configuration in the following modes e Slave SelectMAP using Xilinx Platform Flash XL with onboard 48 MHz oscillator The Xilinx Platform flash configuration device contains the Acromag example design e Master BPI Up using Linear BPI Flash device A BPI flash device is recommended for MicroBlaze program storage e JTAG using Xilinx external program cable Upon a power up cycle the contents of the Xilinx Platform flash device are downloaded to the FPGA See chapter 4 for DIP switch setting options Platform Flash Xilinx Configuration The Xilinx Platform flash configuration data can be reprogrammed using the PCle bus interface or the JTAG interface The following is the general procedure for reprogramming the Platform flash memory and reconfiguration of the Xilinx FPGA 1 Set DIP switch 5 to the OFF position
118. s RARO Pase Bit s Description 0x301000 31 0 Front Input Data Register 0x301004 31 0 Front Output Data Register 0x301008 3 0 Interrupt Enable 0x30100C 3 0 Interrupt Type 0x301010 3 0 Interrupt Polarity 0x3010145 y 0x3010FF 31 0 Reserved 0x301100 31 0 Rear Input Data Register 0x301104 31 0 Rear Output Data Register 0x301108 gt 0x3011FF 31 0 Reserved 0x301200 31 0 P16 Input Data Register 0x301204 31 0 P16 Output Data Register 0x301208 gt Ox30FFFF 31 0 Reserved Front I O Interrupt Status Clear Register Read Write BARO 0x300000 This read write register is used to determine the pending status of FPGA fabric interrupts and release pending interrupts This interrupt status clear registers reflect the status of each of the front write channel interrupts Read of this bit reflects the interrupt pending status Read of a 1 indicates that an interrupt is pending for the corresponding channel Write of a logic 1 to this bit to release the corresponding channel s pending interrupt Writing 0 to a bit location has no effect a pending interrupt will remain pending Front write channel O interrupt status is identified via data bit 0 while front write channel 3 status is identified via data bit 3 of this register at BARO plus 0x300000 Acromag Inc Tel 248 295 0310 39 www acromag com XMC 6VLX USER S MANUAL DDR Memory Test Status R
119. s estat ag veson O ries O ttrares Design Summary Implemented Number of Slice 11 Ts 150 720 Console Generating Report Number of warnings 0 Total time 4 mins 27 secs Process Generate Post Place Route Static Timing completed successfully H El Console O errors 23 Warnings Tag Find in Files Results Acromag Inc Tel 248 295 0310 89 www acromag com XMC 6VLX USER S MANUAL After the Generate Programming File process has completed launch iMPACT to covert the bit file to a mcs file If IMPACT doesn t automatically open the project file XMC 6VLX640F ipf then click on FILE gt Open and navigate to C XMC V6 XMC 6VLX240F iIMPACT XMC 6VLX640F ipf and select it Next select the PROM File Formatter tab ISE iMPACT P 15 E Eile Edit View Operations Output Debug Window Help D alouax a ao iMPACT Flows Oax cy Ea Boundary Scan SystemACE B Create PROM File PROM File Formatter WebTalk Data Right click device to select operations iMPACT Processes Available Operations are oo ee Auto Selcet false Number of Revisions 1 Number of PROMs 1 PROM Name xcf128x PROM Size 16777216 Bytes Revision 0 0 1 device s chain Device 0 pn xc6v1x240t fn system_top bit END of Report Project C XMC V6 XMC 6VLX240F iMPACT XMC 6VLX240F ipf loaded 4 w Errors EN Warnings
120. s USER S MANUAL Iwip_echo_server_dual echoes TCP IP packets sent to it over the Ethernet ports This program is used to test the Ethernet ports Connect the appropriate copper or fiber Ethernet cable to a host PC and ping the XMC V6 The IP address is 192 168 1 10 subnet mask 255 255 255 128 for port 1 and 192 168 1 138 subnet mask 255 255 255 128 for port 2 Make sure that the host PC subnet address is also 255 255 255 128 and the host PC IP address is in the same subnet as the XMC V6 port that it is attached to The Ethernet MAC IDs mac_ethernet_address1 and mac_ethernet_address2 are defined in the file main c The example program assigns the addresses 00 0A 35 00 01 02 and 00 0A 35 00 01 03 Acromag has reserved two unique MAC IDs for each XMC 6VLX The first of two consecutive MAC IDs is printed on a label attached to the board To prevent network address conflicts replace the default addresses in main c with the MAC ID printed on the label and the next consecutive address srec_bootloader This program is embedded in the example FPGA configuration bitstream It is loaded into block RAM memory at configuration time and begins executing when reset is released It copies a microblaze program stored in BPI FLASH in Motorola S record format to DDR3 memory and then executes the program See section Running a Program from BPI FLASH Memory for instructions on copying a program to FLASH memory IMPORTANT When build
121. s 1 and 2 respectively Figure 4 2 Multi Purpose Select DIP Switch SFP1_Rate_Sel SFP2_Rate_Sel CCLK_EH BPI_Flash 2 5V On disables 48MHz On Select BPI The supported configuration methods Slave SelectMAP Master BPI Up and JTAG are selected by setting M 2 0 options of the 8 position DIP switch as shown in the following table Table 4 1 Configuration Details In JTAG mode switch5 On selects FPGA access to BPI Flash Alternatively set switch5 Off for FPGA access to the Platform Flash Power System Devices switch Name Configuration Mode Slave Switch Name SelectMAP BPI Flash JTAG 1 MO Off Off On 2 M1 On On Off 3 M2 On Off On 4 CCLK_EN Off 48 MHz On FPGA On TCK 5 BPI_Flash Off On On The power to the XMC 6VLX is taken from the XMC P15 connector VPWR_5 12 pins The VPWR_5 12 power is the V in voltage to the four LTM4602 devices U18 U19 U20 and U25 These LTM4602 devices output 1 0V 1 5V 2 5V and 1 8V voltages The 1 5 V supply is input to both Acromag Inc Tel 248 295 0310 61 www acromag com XMC 6VLX USER S MANUAL source sink linear regulators TPS51120 devices U15 and U30 The 1 8 V supply is input to both MIC61300 devices U22 and U24 Figure 4 3 Power Distribution xmc P15 VPWR_5 12 Tm 1 0V LTM4602 U19 1 5V LTM4602 u15 0 75V_DDR TPS51120 U30 0 75 QDR TPS51120 u20 2 5V LTM4602
122. s Window Help az D RM Say AAA Or amp E a E D E ES Debug Eig C C a Hy Gly Gro A memory_config_g c 53 N ih system mss Ez systemxml B Outline 2 Make Target This file is automatically generated based on your hz 4 12 w e include memory config h Y memory_config h memory_ranges struct memory_range_ EDK_hw_platform ES hello_world_0 struct memory range s memory ranges A 15 lwip_echo_server_dual x e a Ie n_memory_ranges int microblaze O d bram cntlr memory will not be test la 15 srec bootloader O i ia a 3 Binaries DDR3_SDRAM ial Includes Maxi v6 ddrx Debug Py a 1073741824 h blconfig h i Le bootloader c R errors h int n memory ranges 1 memory_config h platform_config h platform c portab h srec c 5 B E B D E srec h A Iscript ld standalone_bsp_0 P m El Problems 2 A Tasks El Console El Properties 4 Terminal 1 0 errors 9 warnings 0 others Description Resource 2 Warnings 9 items display_progress defined but not used Wunused function bootloader c amp implicit declaration of function print Wimplicit function declaration bootloader c amp implicit declaration of function print Wimplicit function declaration echo c amp implicit declaration of function print Wimplicit fun
123. s core to buffer the 100MHz differential PCle Reference Clock to the AXI PCle core Acromag modified library files Acromag has modified two of the Xilinx supplied source files used to build a board support package that includes the Lightweight Internet Protocol LWIP library The files are located in the folder C XMC V6 sw_source modified xilinx library The file names are xaxiemacif_dma c and xpqueue c These files have been modified to support multiple instances of the Ethernet interface As delivered by Xilinx the library would only support a single instance of an Ethernet interface These files must be copied to the following directory to overwrite the existing files delivered through the Xilinx installer C Xilinx 14 2 ISE_DS EDK sw ThirdParty sw_services lwip140_v1_02_a src contrib ports xilinx netif Acromag Inc Tel 248 295 0310 70 www acromag com XMC 6VLX Running a Program from BPI FLASH Memory This section describes the steps required to create an S record file that can be loaded into FLASH memory and executed upon initial application of power USER S MANUAL From within SDK open the project properties to display the following window r amp Properties for lwip_echo_server_dual l le ae Resource Builders C C Build Build Variables Discovery Options Environment C C General Project References Run Debug Settings Tool Settings Pa Settings y vw Confi
124. s for this purpose It contains the configuration registers shown in Table 3 1 to facilitate Plug and Play compatibility The Configuration Registers are accessed via the Configuration Address and Data Ports The most important Configuration Registers are the Base Address Registers and the Interrupt Register which must be read to determine the base address assigned to the board and the interrupt request that goes active on a board interrupt request Acromag Inc Tel 248 295 0310 18 www acromag com XMC 6VLX USER S MANUAL Table 3 1 Configuration Reg D31 D24 D23 D16 D15 D8 D7 DO Registers Num 0 Device ID Vendor ID 0x6301 XMC 6VLX240F 0x6302 XMC 6VLX365F 16D5 0x6303 XMC 6VLX240 0x6304 XMC 6VLX365 1 Command 2 Rev 1D 00 3 Cache 4 64 bit Memory Base Address for Memory Accesses to PCle interrupt I O registers System Monitor registers and Flash memory 4M Space BARO 5 64 bit Memory Base Address for Memory Accesses to QDRII memory 16M Space BAR2 6 10 Not Used 11 Subsystem ID Subsystem Vendor ID 0x6301 XMC 6VLX240F 0x6302 XMC 6VLX365F 16D5 0x6303 XMC 6VLX240 0x6304 XMC 6VLX365 12 Not Used 13 14 Reserved 15 Max_Lat Min_Gnt Inter Pin Inter Line This board is allocated a 4M byte block of memory BARO to access the PCle interrupt I O registers System Monitor registers and Flash memory The PCle bus decodes 4M bytes for BARO for this memory space This board is also allocated a
125. scribes assigning MAC IDs Acromag Inc Tel 248 295 0310 117 www acromag com
126. sis svesscvisnsedses en enssss ovdedsvsavecsesssneeieus su eessieensessvsavessasvensessssen ee 16 Virtex 6 CONTI BUPATIO Nisses anie eier a a a EAEE aa E E e a EAE REE 17 Platform Flash Xilinx Configuration coccococonccncconononnnnnonocnnonononononcnnnonenonnnnncnnnnnnnnnnnnnnnnnnnnnnnnnncnncnnnannnnnos 17 BPI Flash Xilinx COnfiQuration sesser ieten EE ise EEr EEEIEE RERE ENE 17 PCle CONFIGURATION ADDRESS SPACE eseseseseseseseseseseseseseseseseseseseseseseseseseseseseseseseseses 18 Acromag Inc Tel 248 295 0310 1 www acromag com XMC 6VLX USER S MANUAL CONFIGURATION REGISTERS aoaeoeaiiai a aa e e455 gue o A a a aaa E aa aaar iaai 18 BARO MEMORY MAP scssccsivscsccccvssectscvscscnseestnctecessecescestectesesteeueeestscieeseseensesedscdoesessaneosasaues s 20 INTERRUPT CONTROLLER Kurrier itra EENAA EAA ENNAST 21 Interrupt Status Register Read Write BARO OxO0100000 ccccccssccsssceeseecsecesseecssececseecsseeeeees 21 Interrupt Pending Register Read BARO 0x00100004 occcoooonccnocnncconoconoconnconononnncnnonanoconnnnnnnnnnnconnnnos 22 Interrupt Enable Register Read Write BARO OXO0100008 ccccccssecssecesseecseceeseecsseceeseecsseeeeees 22 Interrupt Acknowledge Register Write BARO OXOO1LOOOOC cccccccssssceesssceceesseeecesseeceeseeeeeeaaes 23 Set Interrupt Enable Register Write BARO OXDO100010 cccooocnncnonocononocancconononoconnnononononccnnnnnnccnn
127. ss flow though mode This is only required when bit O of this register is set to logic O and Platform flash erase and read write operation using the PCle bus are required Bit 1 of the Configuration Control register must be set to logic O when Configuration of the Platform flash device is implemented using JTAG Table 3 21 Configuration Bit s Configuration Control Register Control Register Flash Memory Select 0 oo Platform Flash Configuration is selected 16M byte 1 BPI Flash Configuration is selected 32M byte Platform Flash Address Flow Through 1 0 Write logic low has no effect 1 Write logic high to select address flow through CCLK Clock Control 2 O Write logic low enables the CCLK Write logic high disables the CCLK Reserved 3 31 o Write logic low has no effect 1 Write logic high has no effect Acromag Inc Tel 248 295 0310 40 www acromag com XMC 6VLX USER S MANUAL Aurora Monitor Read Write BARO 0x300104 Table 3 22 Aurora Monitor Register Flash Introduction Acromag Inc Tel 248 295 0310 41 This read write register Aurora Monitor register is used to monitor eight Aurora loopback lanes that are on the P16 connector This Aurora Monitor register is accessed at base address plus 0x300104 The Aurora Monitor register bit O is used take the Aurora link into and out of reset Set to logic 1 the link is held in reset and set to logic O the link is removed fro
128. ssnsnedaveccheveseecte 57 DORA MY ee eth Pee eae ee eo Ra ese oh Heath ae AT EAS ch samosas 57 QODRIIESRAM Me MO Yassin iii 57 Clock GON ii A bee A a nadie 58 Multi Gigabit Transceivers GTX MGTS cccccccesssscecsssceceessssecsessececsseeceessececeesseceessseceeaaeeecsaseceeseseceesaes 58 SEP Module CONNECtOLS aicen neiii niiae iiin enie a i e a iia cas 58 USB tO UVAREBNOE Cenas aaa e A a sues ene E eaa 58 16MB Plattor a F EI EEEIEE E A E E T E EE TE 59 32MB Linear BPI Flash A cia 59 Configuration Flash Design Considerations cccccccccsssssseccceceesensesecececeeseeesececsceeseseeaesesecessesesaeeeeeeeseesees 60 APATE PONE corres AEA EE E E E E E E E E E E E E E ias 60 DIA TEA naka A AO T TAE A T 61 POWEPSYSTEMIDOVICES stt hienona aee adtetanccbcentiscatecancetvetetagdeatanseeosttitcadavanenmeabetecderanstecentatencase 61 System Monito ico a n an a a E a a a a e a a aiii 63 5 0 XPS EMBEDDED SYSTEM cion 04d Xilinx ISE Example Projects noresi neee o tan ect cessbonuerncdedeesesdastarticeds cebsencdedhsde coovsddnctentsseses 64 MicroblaZ Peripherals sosdscscecccensteivlacecnsven saaducarserscontelteceresesean tad delessensartdoues Wenn na edhe EE e AA EEE a 66 Host Peripherals veccecstes tact a dais 67 Common PeriphReralS cti rincon oran EAE A A AE E RO ae eniassasaen 67 SDKs sciences cgi roca NO 67 Acromag Peripheral Repository ccccsssccccecssssssscecececsesseaseecececeeseeeeeseeecessesesaeseescsceesesaeseesesceeeaaea
129. te Otherwise the Platform Flash XL can continue to drive its array data onto the data bus causing unnecessary switching noise and power consumption To drive the FPGA BPI_Flash pin high set the Configuration Control register at BARO 0x300100 bit 0 to logic high The JTAG port can be used to program the Virtex 6 FPGA and access the device for hardware and software debug The default The JTAG port also allows a host computer to download bitstreams to the FPGA using the Xilinx iMPACT software tool In addition the JTAG port allows debug tools such as the ChipScope Pro Analyzer tool or a software debugger to access the FPGA Through the connection made by the temporary design in the FPGA iMPACT can indirectly program the BPI flash or the Platform Flash XL from the JTAG port Acromag Inc Tel 248 295 0310 60 www acromag com XMC 6VLX DIP Switch USER S MANUAL DIP switch DIP1A is a multi purpose switch FPGA Mode switches 1 2 and 3 control the FPGA mode The supported configuration methods Slave SelectMAP Master BPI Up and JTAG are selected by setting M 2 0 options CCLK_En switch 4 controls the enable pin of the 48 MHz oscillator U3 When switch 4 is open off U3 drives a 48 MHz clock onto the FPGA_CCLK signal BPI_Flash switch 5 is use to select between the Xilinx Platform Flash or the Linear BPI Flash for the FPGA boot memory device SFP_Rate_Sel switch 7 and 8 control the rate select to SFP module
130. technique to isolate a faulty board If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and software information Acromag s application engineers can also be contacted directly for technical assistance via email telephone or FAX through the contact information listed at the bottom of this page When needed complete repair services are also available Acromag Inc Tel 248 295 0310 103 www acromag com XMC 6VLX 7 0 SPECIFICATIONS PHYSICAL POWER REQUIREMENTS Power will vary dependent on the application Power values are given of Acromag Example Design ENVIRONMENTAL Operating Temperature USER S MANUAL Height 13 5 mm 0 531 in Stacking Height 10 0 mm 0 394 in Depth 149 0 mm 5 866 in Width 74 0 mm 2 913 in Board Thickness 2 21 mm 0 08 in Unit Weight 4 2882550z 0 12157Kg 3 3 VDC 5 Typical 50 mA Max 100 mA 12 5 VDC as 12V 5 Typical 1 8A Max 2 0A 12 VDC 5 OmA On Board 1 0V Power to Current Rating Virtex 6 FPGA Maximum available for the user programmable FPGA 1 0V 45 6A Maximum Model Operating Temperature XMC 6VLX240F OTto70T XMC 6VLX365F Relative Humidity 5 95 Non Condensing Storage Temperature 55 C to 100 C Non Isolated PCle bus and field commons have a direct electrical connection Designed t
131. teway 192 168 1 1 SFP2 Board IP 192 168 1 11 Netmask 299 299 299 0 Gateway 192 168 1 1 link speed 1000 link speed 1000 TCP echo server started port Auto detect 9600 8 N 1 Since the lwip_echo_server_dual program is successfully executing out of DDR3 SDRAM we have validated our change to the DDR3 SDRAM base address Acromag Inc Tel 248 295 0310 102 www acromag com XMC 6VLX USER S MANUAL 6 0 SERVICE AND REPAIR Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested before shipment Service and Repair Assistance Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair Preliminary Service Procedure CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS Where to Get Help Before beginning repair be sure that all of the procedures in the Preparation for Use section have been followed Also refer to the documentation of your board to verify that it is correctly configured Replacement of the board with one that is known to work correctly is a good
132. the Front I O interface is enabled See the Front I O interrupt 0 section for source of this interrupt Oo Disabled Enabled This bit when set indicates an AXI CDMA interrupt enable See the CDMA section for source of this interrupt 1 0 Disabled 1 Enabled Reserved 31 2 Oo NA 1 NA Interrupt Acknowledge Register Write BARO 0x0010000C The Interrupt Acknowledge register is a write only location that clears the interrupt request associated with selected interrupt inputs Note that writing one to a bit in Interrupt Acknowledge register clears the corresponding bit in Interrupt Status register and also clears the same bit itself in the Interrupt Acknowledge register Writing a 1 to a bit location in the Interrupt Acknowledge register will clear the interrupt request that was generated by the corresponding interrupt input An interrupt input that is active and masked by writing a O to the corresponding bit in the Interrupt Enable register will remain active until cleared by acknowledging it Unmasking an active interrupt causes an interrupt request output to be generated if the Master Interrupt Enable bit O in the Master Enable register is set Writing Os has no effect as does writing a 1 to a bit that does not correspond to an active input or for which an interrupt input does not exist The bit locations in the Interrupt Acknowledge register correspond with the bit locations given i
133. to get two Ethernet interfaces to work correctly in a single system Some software modifications were also necessary for the same reason Examine the configuration of the hardware components axi_ethernet and axi_dma in Xilinx Platform Studio Knowing how the hardware is configured will allow you to focus on the particular sections of the Xilinx documentation that are pertinent The host processor can access the following peripheral devices and IP blocks through the PCI Express interface common peripherals Central DMA and QDRII SRAM and an interrupt controller The following common peripherals can be accessed from either the host processor through the PCI Express interface or the embedded Microblaze processor Front I O Rear I O P16 I O FLASH Aurora registers and the system monitor The following Microblaze programs are included in the example project hello_world lwip_echo_server_dual and srec_bootloader hello_world transmits the text hello world over the UART interface Connect a USB cable to a host PC that has the USB UART device driver installed see section USB to UART Bridge in the Theory of Operation Chapter Start a terminal emulator program such as hyperlynx and see the text displayed on the terminal The serial interface parameters are 9600 baud 8 data bits one stop bit no parity Acromag Inc Tel 248 295 0310 67 www acromag com XMC 6VLX Iwip_echo_server_dual srec_bootloader peripheral_test
134. tor erase operation will immediately terminate the operation Flash Data Register Read Write BARO 0x300214 This read write register holds the 16 bit data which is sent to the flash chip upon issuing of a flash start write command Flash Address Read Write BARO 0x300218 This read write register holds the address to which the flash chip is written upon issue of a flash start write command Acromag Inc Tel 248 295 0310 45 www acromag com XMC 6VLX USER S MANUAL Simple BPI Flash Programming Example 1 2 3 Write 0x1 to address 0x300100 BPI flash device is selected Read address 0x300200 Status register value 0x80 Write 0x0 to address 0x300218 flash address set to block O Write 0x1 to address 0x300204 flash block O unlock Write 0x1 to address 0x300210 flash block O erased Write 0x3A3A to address 0x300214 flash data register set with 0x3A3A Write 0x1 to address 0x30020C flash data written to flash Write 0x0 to address 0x300218 set flash address back to 0 Read address 0x300208 flash data at address 0x0 is Ox3A3A Simple Platform Flash Programming Example 1 8 9 Write 0x2 to address 0x300100 Platform flash address flow though is selected Write 0x8000 to address 0x300218 Flash Address Bit 15 is set for asynchronous mode Write 0x8 to address 0x300204 Platform flash set to asynchronous mode Read address 0x300200 Status register value 0x80 Write 0x0 to address 0x
135. vailable 33 Utilization Xilinx XC6VLX365T 1FF1156 Resource Usage e Slice Registers 64 465 Used 455 040 Available 14 Utilization e Slice LUTs 68 257 Used 227 520 Available 30 Utilization MMCMs 4 Used 12 Available 33 Utilization P15 Connector 114 pin Samtec ASP 103614 05 connector complies with ANSI VITA 42 3 2006 P15 is the primary XMC connector Acromag Inc Tel 248 295 0310 105 www acromag com XMC 6VLX P16 Connector SFP Connectors P4 REAR I O USER S MANUAL 8 Gigabit differential pairs are provided Operating data rate between 480 Mb s and 6 6 Gbit s System Management XMC provides hardware definition information read by the external controller using IPMI commands and 12C serial bus transactions default build does not use 3 3V power 4 pins at 1A pin 3 3V auxiliary power 1 pin at 1A pin Variable power 5V or 12V 8 pins at 1A pin 114 pin Samtec ASP 103614 05 connector complies with ANSI VITA 42 3 2006 P16 secondary XMC connector 8 Gigabit differential pairs are provided Operating data rate between 480 Mb s and 6 6 Gbit s 38 standard user I O are also available Example design uses as 19 differential LVDS pairs 20 pin TE Connectivity 1888247 1 or equivalent connector complies with SFF 8083 SFP transceiver signals routed directly to Virtex 6 are capable of SFP maximum data rate of 2 5 Gigabit sec P4 Rear I O interface 64 pin female receptacle header AMP 120527 1 or equivalent
136. write only register is used to initiate the write of a 16 bit data value to the flash chip A Flash Start Write command is executed by writing logic 1 to bit O of this register at base address plus 0x30020C Prior to issuing of a Flash Start Write the Flash Data and Address registers must be set with the desired data and address to be written See the Flash Data and Address registers at base address plus 0x300214 and 0x300218 Issuing a Flash Start Write will automatically increment this address after the previously issued Flash Write has completed Thus the address will not need to be set prior to issuing the next Flash Start Write if consecutive addresses are to be written Flash Erase Block Write Only BARO 0x300210 This write only register is used to erase the contents of the addressed flash block A flash bit cannot be programmed from logic 0 to logic 1 Only an erase block operation can convert logic O back to logic 1 Prior to reprogramming of the flash chip a flash erase block command must be performed A flash erase block command is executed by writing logic 1 to bit 0 of this register at base address plus 0x300210 Verify that the flash chip is not busy from a previous operation before beginning a new operation This is accomplished by reading the flash status register Any other flash commands written to the flash chip during execution of the flash erase block operation will be ignored Note that a hardware reset during the sec
137. www acromag com XMC 6VLX USER S MANUAL Figure 4 1 Internal FPGA Functions sjesaydisad pajjosquos azejgossil Front 1 0 interface Rear 1 0 interface P161 0 Interface Flash Interface sjesaydiuad pajjo1uo d Microblaze Peripherals The embedded system consists of the following IP blocks Microblaze processor DDR3 SDRAM two Ethernet SFP ports with supporting DMA controllers UART interrupt controller timer and the common peripherals over the AXI to AHB bridge The embedded MicroBlaze processor is used to echoes packets sent to its Ethernet interface There are three major components within the Acromag Inc Tel 248 295 0310 66 www acromag com XMC 6VLX Host Peripherals Common Peripherals SDK hello_world USER S MANUAL embedded system that make up the Ethernet interface Ethernet core VHDL source axi_ethernet_v3_01_aC XMC V6 pcore_subdirectory pcores axi_ethernet_v3_01_a hdl vhdl DMA controller VHDL source axi_dma_v6_01_aC XMC V6 pcore_subdirectory pcores axi_dma_v6_01_a hdl vhdl And software running on the microblaze lwip_echoserverC XMC 6VLX365F SDK lwip_echo_server_dual src Xilinx provides documentation for each of these XPS core components The Xilinx Documentation Navigator tool can be used to find Xilinx provided documentation The VHDL source for these components has had a few minor changes made to what Xilinx provided These changes were necessary in order
138. y PCle Bus An example design is provided with four lane PCI Express Generation 1 operating at a bus speed of 2 5 Gbps per lane per direction This gives up to 2GBytes sec data rate on the bus FPGA supports Gen1 8 lane x8 or Gen2 4 lane x4 PCle Bus Master The PCle interface logic becomes the bus master to perform DMA transfers DMA Operation The PCle bus interface supports one DMA channel capable of transferring data to and from the on board QDRII SRAM Compatibility PCI Express Base Specification v2 0 compliant PCI Express Endpoint Provides one multifunction interrupt The XMC 6VLX is compatible with XMC VITA 42 3 specification for P15 8 www acromag com XMC 6VLX USER S MANUAL Software The XMC 6VLX products will require support drivers specific to your operating system ENGINEERING DESIGN KIT Acromag provides an engineering design kit for the 6VLX boards sold separately a must buy for first time 6VLX module purchasers The design kit model XMC 6VLX EDK provides the user with the basic information required to develop a custom FPGA program for download to the Xilinx user programmable FPGA The design kit includes a CD containing schematics parts list part location drawing example VHDL source and other utility files The 6VLX modules are intended for users fluent in the use of Xilinx FPGA design tools DLL CONTROL SOFTWARE Acromag provides software products sold separately to facilitat

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