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MOSFET Models

1. The figures show the depletion of the SOI MOSFET s channel region in red color Non Fully Depleted NFD Gate SiO2 CL ddddddddddddddssddddisdisaa Substrate Backgate Partially Depleted PD 291 MOSFET Models G ate S D 10 2 IILI LLL LLL LLLLLLLLLL LLL LLL LLL LLL LLL LLL Substrate Back gate Fully Depleted FD devices G ate S D 10 2 KiLLllllllllilldlldligledeggijlidllll Substrate Back gate Differences between Non Fully Depleted Partially Depleted and Fully Depleted Categories The following table summarizes the differences among the Non Fully Depleted Partially Depleted and Fully Depleted categories Non fully depleted Partially depleted Fully depleted NFD PD FD Backgate coupling strong Not coupled Partially coupled Coupled inversion Backgate coupling sub threshold Not coupled Not coupled Not coupled coupled Bulk charge effect on Id Similar to bulk MOSFET between FD and NFD constant bulk charge Source to body junction Conventional Conventional Fully depleted diode Drain to body junction Conventional Fully depleted diode Fully depleted diode The NFD device has almost identical characteristics as a bulk MOSFET device Therefore the NFD model is a modified bulk MOSFET model with added SOI specific effects like parasitic bipolar effect self heating and body contact resistance The FD device in contrast has very different characteristics as mentioned
2. Li 5 i 5 1 4 r r Oo i E 4 a O a vk CLE Peripheral sidewall capacitance Cw along the field oxide Cow PD Were Cjodsw where PD total perimeter of pn junction given as SPICE model parameter Wer effective gate width of transistor calculated in SPICE C capacitance per unit length jbdsw Cibdsw is calculated according to the following equation and is shown in the following figure For Vps lt 0 V i y fisw C bdsw 7 Cisw P j j bsw For Vps 2 0 f Y y z bs C ibdsw 7 C isn l M owe i bsn Sidewall Capacitance Cjbdsw as a Function of Vg 141 MOSFET Models m S r 1 b i Lil Ld i i g i 1 r D i O 4 E D 6 L Mw i O 2 0 L 5 1 0 0 5 6 6 8 5 vk LE re Peripheral sidewall capacitance Cswg along the gate oxide Cowe Weer Cjbaswa where Were uScve gate width of transistor calculated in SPICE jbdswg capacitance per unit length c Cibdswg is calculated according to the following equation and is shown in the following figure For Vps lt 0 M Vs g jswg C ibs E a oe i i bsw g For Vps 2 0 f V bs Cibs jwg 1 Mjewg r Sidewall Capacitance Cjbdswg Along the Gate Oxide as a Function of Vg mo 14 8 Wn ed i i Ll 130 t t 0 5i 128 O i i i O i ej ue t f i D M i i i 0 10G G L i L g Extrinsic Capacitance As mentioned in the introduct
3. Initial Values Parameters Flags NPO 6E 026 DC NOYO 5E 025 SWIGATE 1 s WARO 4 905E 011 LVARL 1 531E 017 SWIMPACT 1 w LV AR VY 2 022E 020 SWIGIDL 1 LAP 2 574E 011 PE WVARO 1 018E 009 E _ WVARL 1 497E 018 SWIUNASYM 0 WARY 1 01797E 019 QMC 1 a WOT 4 965E 010 The Initialize menu contains a field to Set Initial Values to Circuit Defaults Inside the Initial Values Model Parameters section enter process related parameters like the relative dielectric constant of the gate oxide EPSROX Advanced CMOS process generations are more and more making use of high k gate dielectrics Therefore you can specify the relative dielectric constant of your process by changing EPSROX from 3 9 default value for SiO gate dielectric There are other process parameters to be specified on this folder including electrical process or measured gate oxide thickness TOXE TOXP TOXM junction depth doping concentrations and sheet resistances You will find a description of the model parameters and model flags for the BSIM4 model in Main Model Parameters mosfet and for the PSP model in Parameters for the PSP model mosfet See also the manual from UC Berkeley Appendix A Complete Parameter List for more details on 101 MOSFET Models model parameters as well as the PSP manual Entering values into the fields and selecting the Save button starts a routine to check the values entered This routine will flag an error me
4. Param Name Min Opt Min Value Opt Max Max EPSROX 1 000 1 000 3 900 5 000 TOXE 1 000E 021 1 000n 2 950n 10 00n TOXP 1 000E 021 1 000n 2 950n 10 00n TOXM 1 000E 021 1 000n 2 950n 10 00n DTOX 1 000n 1 000n 0 000 1 000n 1 000n XJ 1 000E 021 10 00n 150 0n 300 0n 7 NDEP 1 000E 021 1 000T 3 225E4 017 1 000E 021 NGATE 0 000 1 000E 018 5 483E 020 1 000E 022 NSD 0 000 1 000E 018 1 000E 020 1 000E 022 XT 0 000 1 000n 155 0n 300 0n RSH 0 000 0 000 0 000 50 00 RSHG 0 000 100 0m 100 0m 300 0 VTHO 2 000 696 5m 2 000 On the left side you can see the parameters to be optimized The following columns display the minimum for the named parameter the parameter s reasonable physical minimum an optimizer minimum and maximum column followed by the parameter s maximum if a reasonable one exists The white fields let you enter optimizer settings fitting your process needs You can Save these settings for future extractions using the File menu You can restore boundaries by clicking Boundaries gt Set to Default from the menu The parameters and min max values are taken from the IC CAP Model Parameters folder Related Topics DC Notes mosfet DC Information mosfet DC Initialize mosfet DC Binning mosfet DC Extract mosfet DC HTML mosfet DC Options mosfet Back to Extraction of DC and CV Parameters mosfet 51 MOSFET Models DC Extract
5. tH C_Overlap_G_DS C_Overlap_G_DSB C_Intrinsic _ DC _Diode Diode_BD t Diode_BS __Data_Templates tl Transistor_1 t Transistor_2 t Transistor _3 tl Transistor_4 _ Configurations t Configuration Calculate Model __Display_Templates___ t Cycle_Device Cycle_Plots t Display _Transistor Display_C_Overlap_G Measure Simulate H Yth_Idsat_vs_Devices Display Plot Cox_vg Display all COx1 Close All Instrument Options Plot Finder Seles Setup variables Extract Optimize og Cox vg XY GRAPH vg Vgb fe Be Oo Plot Cox XY GRAPH vg Vgb a O Active Setup PSP_DC_CV_Extract C_Oxide cg_vq Status 67 MOSFET Models The added plot will be used only for optimization if the checkbox Use Plot in Optimizer Show Region in Plot is checked see the following figure Otherwise the plot will be used to display data during optimization Freshly added plot can be used during optimization Configuration Wizard for Extraction Functions 12 Configuration Edit Options Help SER EE Available Extractions Overview Customized Functions Default Extraction Flows Available Extractions B oba 5 JF Capacitance Oxide E TOXO l 0 TOXO NSUBO YFBO Function Custom Defined Function Parameters 0 TOXO NSUBO VFBO DLQ Type Optimization Tuner TOXO
6. 3 Capacitance Overlap NSUBO E Loy Name 0 Toxo NSUBO YFBO DLO VFBO DLO LOY NOVO DLO CGBOVL Setup C_Oxide cg_vg DPHIBO YFBO NSUBO NPO O NPO NPL CGBOYL DLO DWQ 1 Data Selection O VFBx Caption O VFBO YFBL LOY NOVO CFR P optional O DPHIBx C_Oxidefcg_vg DPHIBx VFBx NSUBx FOLx O NSUBx FOLx NPCKx LPCKx WSEGx Target Setup O LWARx WYARx DWOQ 0 All C Overlap L Scaling Capacitance Junction Diode Large Vth Mobility Saturation Velocity Large Gate Current Large Impact Ionization and GIDL Only SAref Selection Policy Default Size Category Large Narrow Only WPEref Sort Devices by L W WF Short Small W Scale C Allow Multiselection of Devices Additional Length Scaling Yth Mobility Saturation velocity Width Scaling amp Corner Length Width Scaling Temperature Global Optimizations STI Stress Effect Well Proximity Effect Finetuning Plots Transforms For Prepare Data C_Oxide cg_va setPlotOptions Hl H E H ee H E Be Se Spe ee E ee Se ee ee SAG sly jE pE l Ee ee Transforms For Simulations O New Main Group Local Capacitance Cgg Local Long Wide Local Length Dependence Wide Local Long Width Dependence C_Oxide cg_vo Cox_vg PHAM Local Length Width Dependence PSP Scale
7. Cross Section of a Multifinger RF MOS Transistor The substrate resistance network parameters RBPB RBPD RBPS RBDB and RBSB are derived using 4 new model parameters e RSHB sheet resistance of the substrate e DSCB distance between the source contact and the outer source area e DDCB distance between the drain contact and the outer drain area e DGG distance between two gate stripes Relevant Model Equations for Substrate Resistance Parameters o MESE tactor even odd Sfi NF 2 in ZE j 9 RBPB 1x10 RBPD RBPS SEB L DGG 2W 212 MOSFET Models RBSB sees TE EE SIRE RBSD Vase 2 EE EE Substrate contact resistance scaling Due to different layouts of RF multifinger MOS transistors BSIM4 3 0 has been enhanced with a new flag to model the substrate resistance according to the substrate contacts used The flag RSUB_EQ can have two values e RSUB_EQ 0 symmetric substrate contacts e RSUB_EQ 1 horseshoe substrate contact For the horseshoe contact a new dimension has been defined as can be seen in 3 dimensional view of a horseshoe substrate contact with Source connected to Substrate e DHSDBC distance between Drain or Source edge and substrate contact of the horseshoe Inside the Modeling Package temporary parameters are used to calculate the values for the five resistances used inside BSIM4 Symmetric substrate contacts top view as well as Horseshoe substrate contacts top view are
8. MOSCV_ T _cap cwrosw MJ CJISW cjdp3erimeter ma PB LEVEL 3 model ft large idvg vg vb vd vs extract c ud Wa large sua uo THETA UO THETA VTO optimize NSUB UO THETA VTO narrow idvg extract MOSDC_lev3_lin_narrow DELTA WD optimize DELTA WD short idvg extract MOSDC_lev3_lin_short LD RD RS XJ optimize LD RD RS XJ short idvd vd vg vb vs lid omt MOSDC_lev3_satshort lev3_sat_short STA KAPPA ETA KAPPA optimize ETA KAPPA eae cjdarea E vd gt m CJ o ao zero bias CJ extract Optimize CJ MJ PB L cbd2 vb vd extract swat E T MJ CJSW cjdperimeter MJSW PB 375 MOSFET Models Test Instruments The HP 4141 HP Agilent 4142 or HP 4145 can be used to derive DC model parameters from measured DC voltage and current characteristics The HP 4271 HP 4275 HP 4280 HP Agilent 4284 or HP 4194 can be used to derive capacitance model parameters from measured capacitance characteristics at the device junctions Instrument to Device Connections When the device is installed in a test fixture verify the correct connection of device nodes by checking the inputs and outputs for the DUTs The following table is a cross reference of connections between the terminals of a typical MOSFET device and various measurement units These connections and measurement units are defined in the model file Input and output tables in the various setups use abbreviations D drain G g
9. MOSFET Models Getting Started with MOS Modeling IC CAP provides example files with the Modeling Packages which you can load and experiment with the settings of different modules like DC_CV_Measurement Extraction or RF Measurement and Extraction Opening a MOS Modeling Example To open a MOS Modeling example 1 Choose File gt Examples gt model_files gt mosfet from the IC CAP Main window to open a MOS model file For example BSIM4_DC_CV_Extract mdl file in the BSIM4 folder The Model icon is displayed in the IC CAP Main window fa IC CAP Main Sel File Edit Tools Measure Windows Help Obed 9 amp 50 hoes 2 Double click the BSIM4_DC_CV_Extract model icon to start the measurement module The BSIM4_DC_CV_ Extract Model window is displayed s BSIM4_DC_CV_Extract 7 Sele File Initialize Binning Extract Plots HTML Options Boundaries Tools gt eG F FSS s tt amp KE gt Notes _Informa Save Setup Entries Binning Extract HTML Options 4 gt Currently no project is loaded First load a project Project Project direct Status 3 Choose File gt Examples in the BSIM4 _DC_CV_Extract Model window The Copy Example Project dialog box is displayed ean Copy Example Project Select Example Project Path c Agilent ICCAP_2011_04 examples model_files mosfet bsim4 examples de_projects Example bsim4 _For_experts Select target directory and name of project to which the Exam
10. MOSFET Models voltage The primary measurement is at port 1 and the port 2 measurement is synchronized to the port 1 measurement You set the measurement parameters by defining the instrument state and the DC input values as explained in the next pages The software calculates the series resistances from the outputs of the bias networks to the inputs of the device under test The resistance values are then incorporated into the model file and their effects are removed from the device response during the modeling process The default port resistance for both port 1 and port 2 is 0Q Note that the first part of the procedure differs for probe station and in fixture measurements Setting Up for the Measurement 1 If you are using a probe station position an impedance standard substrate ISS on the chuck Place both the port 1 and port 2 probes on a short circuit standard 2 If you are using a fixture insert the short from the in fixture calibration kit 3 From the DUT Setup panel select the r_series setup Renaming the SMUs Use this procedure any time you change device types such as from FET to BJT or from BJT to FET so that the measurement setups can properly communicate with the bias Supplies When you run the IC CAP software it initially identifies the plug in SMUs according to the numbers of the Agilent 4142 slots in which they are installed A medium power SMU occupies one slot A high power SMU occupies two slots and i
11. This method is described in detail in the IC CAP demo_features See the file ICCAP_ROOT examples demo_features 4extraction deemb_short_open md It is assumed that the parasitics can be modeled using the following equivalent circuit Detailed equivalent circuit of MOS Transistor The transistor is located between nodes Gate 222 Drain 111 Source Bulk 333 Regarding the two test structures OPEN and SHORT and their equivalent circuits it is assumed that there are ONLY parallel parasitics followed by serial parasitics If this pre requisite is valid the measured data of the SHORT device and the measured data from the DUT have to be de embedded from the outer parallel parasitic elements first after a conversion of S to Y parameters Zdut_without_open Z Ytotal Yopen Zshort_without_open Z Yshort Yopen The subsequent step is to de embed the measured data of the DUT from the serial parasitic elements and convert them back to S parameters Sdut S Zdut_without_open Zshort_without_open The typical behavior of the OPEN _SHORT structure is shown in the two figures below 11 22 of the OPEN_SHORT structure 173 MOSFET Models S m 22 S m 11 S12 21 of the OPEN_SHORT structure Lil ad 8 5 O Ea 4 0J 8 8 E On CW 9 5 E in 1 6 1 0 REAL CE e 4 3 USER_DEFINED This setup can be used to implement user specific de embedding procedures with other test structures tha
12. With respect to current JUNCAP includes two mechanisms diffusion and generation These are described separately for each sub region so that for the DUT gate the current flow at any voltage V is given by I V ID_AREA V IG_AREA V AB3 ID_LOCOS V IG_LOCOS V AL3 ID_GATE V IG_GATE V AG3 where ID_AREA V and IR_AREA V are the normalized contributions of the diffusion current and generation current respectively for the area sub region at voltage V with similar notation being used for the locos and gate sub regions Once the three DUTs have been measured a set of simultaneous equations can be solved that allows the contributions of the area locos and gate sub regions to be separated and normalized Parameter extraction then proceeds by optimizing the relevant parameters to each of the sub region contributions in turn Finally the model parameters may be fine tuned by optimization with respect to the directly measured data in the area locos and gate DUTs 368 MOSFET Models For the case of a well diode you should specify that there is no gate test structure by setting the variable AB3 to zero With AB3 0 the gate device will be ignored during measurements and optimizations 369 MOSFET Models New Features in AMOS Modeling Toolskits for ICCAP 2012 10 For IC CAP 2012 10 there is a model update for HiSIM HV HiSIM HV 2 01 released by the University of Hiroshima in April 2012 has been added The
13. e DC Binning mosfet e DC Extract mosfet e DC HTML mosfet e DC Options mosfet e DC Boundaries mosfet e Back to Extraction of DC and CV Parameters mosfet DC Options 102 MOSFET Models The folder Options lets you define some environmental conditions used in extraction You can set the Simulator used by selecting the Change Simulator and Circuits button from the Options menu You will see a window like the following one nay Configure Simulator and Circuits Te Ioj xj m ctual Simulator Settings Smic TEE SIMULATOR hpeesofsim Resat Circu Path Juss defauk in 1CCAP_ROOT directory Set Resat Test Circuk Path use defauk in ICCAP_ROOT drectory Set Reset All Simietor Configurations Orcutt Path Test Cireutt Path use def aut in SICCAP_ROOT drectory use dafauk in ICCAP_ ROOT directory se default in ICCAP_ROOT drector ise default in ICCAP_ROOT directo 5a del use dafauk in ICCAP_ ROOT Simadator SIMULATOR ADS hpeesofsir PICE spice itin ICCAP_ROOT dractor You can select which simulator to use from a pull down list of ADS SPICE3 Spectre or HSPICE and you can select a SIMULATOR variable You can also select the path to the appropriate circuit files respective the test circuit files Usually you will find those files in ICCAP_ROOT examples model_files mosfet bsim3 or bsim4 or psp circuits SIMULATOR cir tci Note If you would
14. subvt_optz2 is an optimization call for subthreshold region fitting for all Vbs for the parameter VSBT limit_check is called at the end of each miniset optimization to check the parameters with respect to the miniset limits It is used by the macros extract_one_miniset and extract_all_minisets extract scaled_ext contains the optimization sequences necessary for scaled maxiset extraction at the nominal temperature The variable table of this setup contains the parameter MIN and MAX limits that will be used during optimization The scaled_ext setup contains the following transforms sim_all cause the currents in all the DUTs at the nominal temperature to be resimulated i e evaluated with the MM9 C transform sca_opt controls the sequence for maxiset optimizations For more information refer to the discussion on sca_opt in the section Optimization Transforms and Macros mosfet read_sca_opt_files reads the definitions of the optimization transforms from the UNIX file system When you execute SETUP the number of devices may change and the optimization tables for maxiset extraction need to be rebuilt This is performed by the C transform SETUP which writes the new optimization definitions to the file system This transform then reads these new definitions back into IC CAP sca_lin_opt1 is an optimization call for linear region fitting at Vbs O for the parameters VTOR SLVTO SL2VTO SWVTO BETSQ THE1R SLTHE1R and SWTHE1 s
15. 2 POP Wey eeN f 7 EN f jipu TEN AL ps LVARO 1 LVARL 1 LVARW E 5 aa j ae Len We N WE W AW p 2WoT AWop WVARO 1 WVARL 1 WvaRW The parameter LAP in the first equation is defined as the effective channel length reduction the parameter WOT in the second equation as the effective channel width reduction due to lateral diffusion of channel stop implant ions In contrast to BSIM4 the model parameters of the binned PSP model originate from 2 different sources The local and the global model The table below describes the source of the final binning parameters and whether an extension PO PL PW PLW is to be added Name Parameter name in Parameter name in Comment local or global model final binned circuit Simulator specific parameter Level 1020 Level 1021 Parameter from a local circuit which is VFB POVFB PLVFB binned PWVFB PLWVFB Parameter from a local circuit which VFB POVFB only the constant could be binned but is actually identical part will be in all local devices calculated Parameter from a local circuit which is NSUB PONSUB not binned but changes his name Parameter from a local circuit which CJORBOT CJORBOT JUNCAP2 parameter cannot be binned and doesn t change his name Parameters taken from a global circuit LVARO KUO LVARO KUO Process or STI parameters Generation Process for a Binned Simulation Model The PSP Modeling Package comes with an example model file called _psp_binnin
16. 2 100 for the measurement and simulation conditions given in Different Components of the Extrinsic Capacitance this results in the overlap capacitance a0 overlap C ed overlap OF gs The model parameter CGDO in Overlap Capacitance Equation can be calculated by the following equation CGDO DLC Cpy CGDL where DLC represents the channel length reduction in the BSIM3v3 capacitance model Please see the next section for more details about DLC Intrinsic Capacitance a Geometry for Capacitance Model The BSIM3v3 model uses different expressions for the effective channel length Lepp and the effective channel width W for the I V and the C V parts of the model The aula dependence for the intrinsic capacitance part is given as the following AW DWC ean win WW L WwW i L LN y LL P LW LWL N iN LWN pLt Wen LEN W AL DLC Loctive and W are the effective length and width of the intrinsic device for capacitance calculations The parameter AL is equal to the source drain to gate overlap length plus the difference between drawn and actual poly gate length due to processing gate printing etching and oxidation on one side The L 4 parameter extracted from the capacitance active method is a close representation of the metallurgical junction length physical length Woo Wa KAW active Drawn L active l Dra wn 242 Dimensions of a MOSFET Gate Source While the authors of the
17. 5 and the kink and floating body effects are negligible If it is less than Vdd the device operates as NFD Turn on characteristics of the devices are influenced by both back gate and external biases The external bias contacts the body and hence controls V if the device is PD i e Vos gt Visoers By increasing Ves or decreasing Vps Vps lt Vbsoeff the device becomes more and more FD and back gate bias controls Vth The sub threshold swing S is non ideal for Vi coer lt V the device becomes FD and ps therefore Vps Vi coer For short channel devices Vpso can be increased by source and drain junction depletion and hence show different V For this reason the channel length dependency of V lt 9 is modeled in BSIMSOI Temperature Modeling This section lists some temperature effects modeled in BSIMSOI 293 MOSFET Models Built in Temperature Dependencies The BSIMSOI model uses some physically based built in temperature dependencies as listed below e Temperature voltage e Intrinsic carrier concentration Unfortunately the surface potential F which is a very important model parameter from a physical point of view is not temperature dependent in BSIMSOI Temperature Effects In addition to the built in temperature dependencies the following temperature dependencies are modeled in BSIMSOI e Threshold voltage Carrier mobility Saturation of carrier velocity Drain source resistance Saturati
18. Back to BSIMSOI4 Characterization mosfet 294 MOSFET Models IV Characterization Threshold Voltage The threshold voltage is one of the most important parameters of deep sub micron SOI MOS transistors and is affected by many different effects when the devices are scaled down into the region of 0 1 microns The different parts of the complex threshold voltage equation are explained in the UCB BSIMSOI manual See Threshold Voltage mosfet under BSIM3v3 Characterization for in depth information on effects common in BSIMSOI4 and BSIM3v3 The following effects are taken into account for BSIMSOI modeling e Ideal Threshold Voltage valid only for long and wide devices e Non Uniform Vertical Channel Doping The doping concentration is usually higher near the silicon to silicon dioxide interface than deeper inside the silicon film Approximatio Xt Doping profile Xs ubstrate In BSIMSOI either the model parameters K1 and K2 or NCH NSUB VBM or XT can be used to model this effect The following figure shows the threshold voltage Vth as a function of the applied bulk voltage for a transistor with a large channel length and a wide channel width LARGE EBA B wii A E EBA B WTH m Sito Be calc VIHIs d ak B FES CECE e Non Uniform Lateral Channel Doping The doping concentration Nys near the drain and the source is higher than the concentration N in the middle of the channel This is referred
19. C_Gate_ Gate parallel D_m poly Si switched LDD Overlap MOS gate transistors drain e g 2 with transistors with applied L 0 25um and DC bias W 10um which can be used for reliable CV measurements and do not overload the between drain and source Use of a Network Analyzer is also possible For very small capacitance values an additional OPEN calibration structure on the chip is necessary to compensate the capacitance of the pads and the lines to the transistor Test Structures for RF Measurements To extract RF Parameters you will need Teststructures to measure S Parameters Structures which fulfill the requirements are described in Test Structures for S parameter Measurements mosfet Back to BSIMSOI4 Characterization mosfet 313 MOSFET Models SPICE Model Parameters The first table in this section contains flags to select certain modes of operations and user definable model parameters For more details about these operation modes refer to the BSIMSOI manual 4 The model parameters of the BSIMSOI model can be divided into several groups The main model parameters are used to model the key physical effects in the DC and CV behavior of submicron MOS devices at room temperature Here they are grouped into subsections related to the physical effects of the MOS transistor The third table contains process related parameters They should only be changed if a detailed knowledge of a c
20. DVT2 DVT2W DSUB ETAO ETAB NDEP NSD EPSROX MOSFET Models Description long channel threshold voltage at Vbs 0 first order body effect coefficient second order body effect coefficient narrow width coefficient Body effect coefficient of K3 narrow width parameter lateral non uniform doping parameter at Vbs 0 lateral non uniform doping effect on K1 Boltzmann s constant kp 1 3807x10 22 Ais absolute temperature in Kelvin charge of an Electron 4 1 60210 Pc channel length as drawn on mask channel width as drawn on mask number of gate fingers electrical gate equivalent oxide thickness Gate oxide thickness at which parameters are extracted first coefficient of short channel effect on VTH first coefficient of narrow width effect on VTH for small channel length second coefficient of short channel effect on VTH second coefficient of narrow width effect on VTH for small channel length body bias coefficient of short channel effect on VTH body bias coefficient of narrow width effect on VTH for small channel length DIBL coefficient exponent in subthreshold region DIBL coefficient in the subthreshold region body bias for the subthreshold DIBL effect channel doping concentration at X dero the depletion edge at V 0 doping concentration of the S D diffusions relative dielectric constant of silicon gate isolators relative dielectric constant silicon dioxide surface potential
21. E 6 id s id m The setups previously described cover the required standard measurement procedure and represent the minimal configuration necessary The purpose of sweep type LIN Vt is to reduce measurement time by excluding areas of the output diagram that are not relevant for extraction The following figures should help clarify this case Output characteristic of the same device measured at different values of bulk voltage left vb 0 right vb 1 2V 20 MOSFET Models 0 Ha E 3 mis id m s E 3 a 2 f The gate voltage vg in the diagrams shown above has a fixed sweep from 0 6 to 1 8V Because the bulk voltage changed the threshold voltage changes which in turn changes the output characteristic too The curves marked with a red arrow are measurements at low current levels and therefore need a considerable amount of time due to the integration of noisy currents Therefore the lowest gate voltage consumes a lot of time with minimal benefit for the extraction For example it would be better to start the left hand diagram at vg 0 7V and the right hand diagram at vg 0 8V This can be achieved by making the gate voltage sweep starting points dependent on Vth of this device The LIN f Vth sweep is a linear sweep using a starting value dependent on an extracted threshold voltage value from another Vg type sweep This sweep needs a reference to another sweep of type vg The stop c
22. NMOS 1 PMOS 1 1 1 TR Reference temperature oc 21 273 Switch parameters SWIGATE Flag for gate current 0 off 0 0 1 278 MOSFET Models SWIMPACT Flag for impact ionization current 0 0 SWGIDL Flag for GIDL GISL current 0 off 0 0 SWJUNCAP Flag for JUNCAP O off 0 0 QMC Quantum mechanical correction factor 1 0 Process Parameters LVARO Geometry independent difference between actual m 0 and programmed polysilicon gate length LVARL Length dependence of difference between actual and 0 programmed polysilicon gate length LVARW Width dependence of difference between actual and 0 programmed polysilicon gate length LAP Effective channel length reduction per side due to m 0 lateral diffusion of source drain dopant ions WVARO Geometry independent difference between actual m 0 and programmed field oxide opening WVARL Length dependence of difference between the actual 0 and the programmed field oxide opening WVARW Width dependence of difference between actual and 0 programmed field oxide opening WOT Effective reduction of channel width per side due to m 0 lateral diffusion of channel stop dopant ions DLQ Effective channel length reduction for CV m 0 DWQ Effective channel width reduction for CV m 0 POVFB Coefficient for the geometry independent part of the V 1 flat band voltage at TR PLVFB Coefficient for the length dependence of the flat V 0 band voltage at TR PWVFB Coefficient fo
23. Project bsim4 _for_experts Project directory g users default The folder shows fields named Extraction Flow Extraction Function Flow and Available Functions The Extraction Flow field shows the name for the selected extraction step There is the option to change a predefined extraction name If you select a main group using the right mouse button you are able to Rename those group The renaming function is possible only for main groups not for the steps in a main group see the red arrows in the following figure 52 MOSFET Models B qb Capacitance Oxide y E TOXE ACDE Q T TOXE ACDE E 4 Large Basic Yth Mobility Under Function Flow the functions used for the selected extraction flow are listed The Available Functions field shows a list of functions to be used for a selected extraction flow Mark the desired function and click the arrow in between the Function Flow and Available Functions fields to add the function to the flow list The letters in front of the function name explain the extraction method used for this function E represents extraction O stands for optimization and T for tuning The extraction list inside the field Extraction is organized into two main groups to provide a better overview when using a large number of steps or devices for extraction This is done by introducing extraction groups for Global or Binning extraction and hiding or expanding the list of extraction groups for
24. Short om idvg va CE e 4 With this enhancement the Drain Current Equation can be rewritten Enhanced Drain Current Equation Tiso o ds We Rqsldso V aseff The influence of the parasitic resistance on the drain current is demonstrated for a SHORT and a SMALL transistor in the following figure Influence of Drain Source Resistance on Drain Current 132 MOSFET Models without parasitic resistance Short Transistor CE 3 9 id s id m o with car parasitic resistance without parasitic Small Transistor resistance o gt CE 6 id s id m 9 9 with 4 r parasitic ee 9S e 1s e s resistance va ve CE e Output Resistance a Early Voltage The drain current in the saturation region of submicron MOSFETs is influenced by the effects of channel length modulation CLM drain induced barrier lowering DIBL and substrate current induced body effect SCBE These effects can be seen clearly looking at the output resistance R of the device which is defined as In the following figure the measured drain current and the output resistance of an n type MOS transistor with a channel length of 0 5 um are shown Drain Current and Output Resistance in Linear and Saturation Region 7 10 0 inear Saturation Region i 8 0 6 0 las a o MA 2 8 0 0 o a 1 0 2 0 2 0 41 0 Vas V The left most region in the figure above is the linear region in which carrier velocity is
25. VSAT Saturation velocity 8 0E6 cm s AO Bulk charge effect coefficient 1 0 Al First non saturation factor 0 0 23 1 V A2 Second non saturation factor 1 0 0 08 AGS Gate bias coefficient of Abulk 0 0 1 V BO Bulk charge effect coeff for channel width 0 0 m B1 Bulk charge effect width offset 0 0 m KETA Body bias coefficient of the bulk charge effect 0 047 1 V Subthreshold region VOFF Offset voltage in the subthreshold region 0 11 V NFACTOR Subthreshold swing factor 1 0 CIT Interface trap density 0 F m2 CDSC Drain Source to channel coupling capacitance 2 4E 4 F m2 CDSCB Body bias coefficient of CDSC 0 F Vm2 CDSCD Drain bias coefficient of CDSC 0 F Vm2 Drain source resistance RDSW Parasitic resistance per unit width 0 Qu m WR Width offset from Weff for RDS calculation 1 0 PRWB Body effect coefficient of RDSW 0 y 0 5 PRWG Gate bias effect coefficient of RDSW 0 1 V Channel geometry WINT Channel width reduction on one side 0 m WL Coeff of length dependence for width offset 0 m WLN Power of length dependence for width offset 1 WW Coeff of width dependence for width offset 0 m 162 MOSFET ie ran Power of width dependence for width offset Coeff of length and width cross term for width O o cia none oo a Channel Channel length reduction on one side reduction on one side LINT LL Coeff of length dependence for length offset oe mo IL LLN p Power of length dependence for length offset 1 woo
26. VTHO K1 Part1 K2 Part2 i EES aT N A W eget WoO Ps Part3 V Part4 tole The equation above contains some shortcuts for better readability Part1 Part2 Part3 and Part4 Expanded they read _LPEB TOXE _ F _ le Pa fl Kl e i l Lay TOXM i NPs Vo sept IPs TOXE LPE0 Js 1 1 r j 5 if TOXM i _ TOXE Part FoxM bseff Part3 DVTOW 0 Dio l L W fF f cosh DVTIW 8M 1 cosh DYTI 1 l tw l l l i V Part4 _ _____ ETA0 ETAB Vy 49 cosh DSUB 1 t0 To set an upper boundary for body bias during simulations the effective body bias has been introduced 7 7 1 7 7 Vosepp Voet 5 Vos Voe 731 m E has 5 d og 5 Wos Foe 91 481 Fpo 3 where 1 10 J and Voc is the maximum allowable Vos and is calculated from d Vy y d V s 0 to be 9 K1 V o bc S 7 10 4 K2 Furthermore there are some shortcuts used to make the Threshold Voltage Model equation more readable built in voltage of the Source Drain regions _kg T nDEP NsSD Vy 2 h Ni characteristic length l 192 MOSFET Models a 2 Esil Vps s1 TOXE lL J i 1 DVT2 V tN EPSROX bs E ra Tr a aid e TOXE i to N EPSROX C 2 s ls TOXE si 5 si Nq NDEP 1 TS 61 zDVTIW
27. as well as from the gate to the source and drain diffusion regions Igs Toads as is shown in the following figure Cross section of a MOSFET with gate tunneling current components G Two model selectors are used to turn on or off tunneling current components IGBMOD and IGCMOD Setting IGBMOD 1 turns on Igb IGCMOD 1 turns on Igc Igs and Toa Setting IGBMOB IBGCMOD 0 turns off modeling of gate tunneling currents The BSIM4 3 0 Version of the model allows the modeling of Gate Current Tunneling through Multiple Layer Stacks by use of a tunneling attenuation coefficient Gate to Bulk Current 197 MOSFET Models This current consists of two parts tunneling of e ectrons from the conduction band and from the valence band The first part is significant in the accumulation region the second one during device inversion The accumulation region tunneling current is dominated by electron tunneling from the conduction band and is given by TOXREP NTOX A _ lobace eff eff j g gb TOXE TOXE V__ _ exp B TOXE AIGBACC BIGBACC V _ auxl oxacc 1 CIGBACC V__ oxacc Inside this equation the auxiliary voltage is Auxiliary Voltage Equation V ix1 NIGBACC v V Vp b Vm log 1 ex i og 1 exP NIGBACC v The constants in this equation are e A 4 97232E 7 A V e B 7 45669E11 g F s2 0 gt Tunneling Current Equation The tunneling current dominating t
28. bsb OV 5 ov gt The 9 transcapacitances previously introduced are shown in the following three plots for a simulation setup as shown in the following figure 145 MOSFET Models Simulation and Measurement Setup for Overlap Capacitances G Terminal charges Qg Qb and Qd mo uw Boo i Li LJ i EOG r y a 400 fa A x 200 ay E 5 a FE m m 208 o E 4aa x J 600 T 3 0 2 0 1 5 6 1 6 2 6 3 6 vo CE e 4 Partial derivatives of Qg Qb and Qd with respect to Vdb Vgb and Vsb a E 1 E 112 ctud v cgdb m cddb m wn sb cdsb n Q cqgp m cdgb m 000 0 3 de codbd m m sosb cbgo 7n s i i cooo f ralia raada rel it 3 0 0 1 0 gt 6 1 0 3 0 9 F The Overall Capacitance in BSIM3 In previous sections the three components of the BSIM3 capacitance model were introduced Now when an AC simulation is performed the capacitance which can be measured at the terminals is composed of different parts of junction capacitances extrinsic capacitances and intrinsic capacitances The following figure shows as an example the capacitance components for the overlap capacitance between gate and bulk source drain as simulated according to the following circuit description Different Parts of Overlap Capacitance C_Gate_SDB 146 MOSFET Models 408 388
29. of STI edge component CBBTGAT L G Band to band tunneling prefactor AV 3 1E 18 0 of gate edge component FBBTBOT L G Normalization field at the V m 1E 9 reference temperature for band to band tunneling of bottom component FBBTSTI L G Normalization field at the V m 1E 9 reference temperature for band to band tunneling of STI edge component FBBTGAT L G Normalization field at the V m 1E 9 reference temperature for band to band tunneling of gate edge component STFBBTBOT L G Temperature scaling parameter 1 K 1E 3 for band to band tunneling of bottom component STFBBTSTI L G Temperature scaling parameter 1 K 1E 3 for band to band tunneling of STI edge component STFBBTGAT L G Temperature scaling parameter 1 K 1E 3 for band to band tunneling of gate edge component Avalange and Breakdown Parameters VBRBOT L G Breakdown voltage of bottom V 10 0 1 component CBBTSTI L G Breakdown voltage of STI edge V 10 0 1 component CBBTGAT L G Breakdown voltage of gate edge V 10 0 1 component PBRBOT L G Breakdown onset tuning V 4 0 1 parameter of bottom component PBRSTI L G Breakdown onset tuning V 4 0 1 parameter of STI edge component PBRGAT L G Breakdown onset tuning V 4 0 1 z parameter of gate edge component Binning Model Parameters used for binning model Parameter Description Unit Default Min Max LEVEL Model selection parameter 1011 TYPE Channel type parameter 1
30. um um E Device List 3H Capacitance Transistor DE Diode WSu0_L5u0_543u0 W5Su0_L5u0_543u0_ WPE2 WS5u0_L5u0_SA3u0_WPE3 WS5u0_L5u0_SA3u0_WPE4 W5u0_LSu0_SA3u0_WPE1 wWOu18_LSu0_SA3u0_WPE4 WOu16_L5u0_SA43u0_WPES WOu18_L5u0_543u0 WOu18_LSu0_SA3u0_WPE2 WOu18_LSu0_SA3u0_WPE1 W5u0_LOu13_SA3u0_WPE1 W5u0_LOu13_SA3u0_WPE3 Nh J 127 Set ID wW JL Set2 Seti Seti Seti Seti Seti Seti Set2 Seti wi gt 4D AS PD PS 5 11 11 11 11 11 1 36 1 36 1 36 1 36 Setl 1 36 Seti 11 Setl 11 S ISIS S S S S S S S S 53 Conon on on ono aN jan _ uw e e e ee ee e e e ae ae ea Co 9 9 9 9 9 9 www DIO 00O OOO O00010 um uw Oo LI 2 Project bsim4_for_experts Project directory g users default Status The column named Measure shows the allocation of measurement sets to the devices For each device you have to select a measurement set to be used for this device Using the Device List you can define which set will be used for which device Select Configuration gt Configure Measurement Set to display a list of devices to be measured Select a device then select one of the available measurement sets you wish to assign to this device and click OK 9 Note Selecting Configuration gt Configure Measurement Set from the menu actually has two different meanings depending on the subfolder selected from the tree If the Measurement subfolder is selected Configure Measurement Set means to a
31. 0 Large idvg Setup to which the data will be loaded F_DataSourceType ist Listed type of DUTs see attached list Only one dc_idvg kind can be used F_DataSourceDefault_Func ist Large Default selection of DUTs More types can be used see attached list F_DataSourceDefault_STI ist SA ref Default selection of DUTs More types can be used see attached list F_DataSourceAllowMulti ist O Allow multiple selection of DUTs 0 1 Scaling for example uses 1 F_DataSourceSortDUT ist If multiple selection is allowed sort data by values of the content of the array in model variables To sort by length use F_DataSourceSortDUT 0 DUT_L because the length is stored in the model variable array DUT_L 2 1 3 Parameters The parameters must always be specified for Extractions Optimizer Tuners For an extraction F_ParRef ParameterSet Shows the model parameters F_ParName ICCAP_ARRAY 2 Array of the parameter names F_ParName 0O PARAMETER 1 Parameter which is shown F_ParName 1 PARAMETER 2 Parameter which is shown For an optimization F_ParRef execute_VTHO_K12_DVTx_LPEx_opt Points to an optimizer Without specifying the path to the optimizer the setup which is configured in the variable F_Setup is used The configured variables in the optimizer are overwritten from these configurations F_ParName ICCAP_ARRAY 2 Array of the parameter names F_
32. 0 11 KT1L Smpar KTLL 0 KT2 Smpar KT2 0 022 UTE Smpar UTE 1 5 echo UAt Smpar UA1 4 31E 9 UB1 Smpar UB1 7 6E 18 UC1 Smpar UC1 5 6E 11 echo AT Smpar AT 3 3E4 echo PRT Smpar PRT 0 XTI Smpar XTI 3 0 TPB Smpar TPB 0 TPBSW Smpar TPBSW 0 echo TPBSWG Smpar TPBSWG 0 TCJ Smpar TCJ 0 TCJSW mpar TCUSW 0 TCUSWG Smpar TCJSWG 0 echo echo AF Smpar AF 1 5 EF Smpar EF 1 5 KF Smpar KF 1e 17 EM Smpar EM 4 1E7 echo NOTA Smpar NOITA 2e29 NOIB Smpar NOIB 5e4 NOIC Smpar NOIC 1 4e 12 Pose Parasitic diode model Cards Sas Hse wate ss eee aah SSP Ee TS See R een Se echo MODEL bsim_diode_area D echo CJO Smpar CJ 5E 4 Vd Smpar PB 1 M Smpar MJ 0 5 echo IS Smpar JS 1 0E 4 N Smpar NJ 1 echo MODEL bsim_diode_perim D echo CJO Smpar COUSW 5E 10 VJ Smpar PBSW 1 M Smpar MdJSW 0 33 echo IS Smpar JSW 1 0E 12 N dpar CALC NJSW 1 Additional model parameters necessary for scalability scalable external capacitors and inductors to account for cross coupling in the metal stripes and additional delay due to large sizes a scalable substrate network a scalable channel length reduction echo CGDEXT0 Smpar CGDEXT0 1e 9 ext cap gate drain per gate width and finger F m echo CGSEXT0 Smpar CGSEXT0 1e 9 ext cap gate source per gate width and finger F m echo CDSEXT0 Smpar CDSEXT0 1e 9 ext cap drain sou
33. 2 000 1 815 500 0m 1 413m VSBTR Limiting voltage of the VSB dependence of M and GAMO SLVSBT Coefficient of the length dependence of VSBT AiR Factor of the weak avalanche current STA1 Coefficient of the temperature dependence of Al SLA1 Coefficient of the length dependence of Al SWA1 Coefficient of the width dependence of A1 A2R Exponent of the weak avalanche current SLA2 Coefficient of the length dependence of A2 SWA2 Coefficient of the width dependence of A2 A3R Factor of the drain source voltage above which weak avalanche occurs SLA3 Coefficient of the length dependence of A3 SWA3 Coefficient of the width dependence of A3 TOX Thickness of the oxide layer COL Gate overlap per unit channel width NTR Coefficient of the thermal noise NFR Coefficient of the flicker noise MOSFET Models Model Variables The following table describes the MOS Model 9 model variables MM9 Variables Variable Name VP_large L_large SETUP_LIST_SIZE MACRO_LIST_SIZE VAR_ROW_SIZE PARAM_ROW_SIZE VSUP NUMDUT DUT COMGATE COMSOURCE COMBULK MATADD MATNAME DUT_LARGE YLOW YHIGH KFACTOR YLOW_SUB YHIGH_SUB LIN_VGSSTEP VBS1 VBS2 VBS3 SAT_DELVGS SAT_VGS2 SAT_VGS3 SAT_VGS4 SAT_VDSSTEP SVT_DELVGS1 SVT_DELVGS2 SVT_VGSSTEP SUB_VDS1 SUB_VDS2 SUB_VDS3 SUB_VGSSTEP SVT_VDS1 SVT_VDS2 SVT_VDS3 LIN_VDS NUMLPLOT NUMWPLOT NUMRPLOT IMIN EQNTYPE Description VP of large device in dataset Length of large
34. 228 MOSFET Models Introduction to HiISIM2 Characterization This section describes the measurement and extraction of parameters for the HiSIM2 model developed by AdMOS The Modeling Packages use similar Graphic User Interfaces GUI Performing the measurement and extraction tasks using one of the Modeling Packages is similar and therefore described only once at Using the MOS Modeling Packages mosfet HiSIM is a complete Surface Potential Based model to simulate new generation MOSFETs developed by Hiroshima University The web address listed in HiSIM References Point 1 mosfet points to the website of the HiSIM research center This short documentation lists the effects of modern MOSFETs using 45nm technology or smaller and the SPICE parameters used It is based on HiSIM 2 5 1 released March 2010 respective on HiSIM_HV 1 2 1 released Nov 2010 Back to HiSIM2 Characterization mosfet 229 MOSFET Models HiSIM_HV Model The HiSIM_HV model topic is based on HiSIM_HV Version 1 2 1 released in November 2010 This part of the documentation is dedicated to the HISIM high voltage model As this model is based on the HISIM2 model the HV part only describes the differences between those models The high voltage model uses some additional parameters not present in HISIM2 Commonly following two types of structures for high voltage MOSFET s are used e Laterally diffused asymmetric structure usually called LDMOS e Symmetric st
35. 266 166 I I I I i r B I I I t I I res errr cgg 2 cagb embegdo mtcgso mt egbo m cggb m cgdo m cgza m cgka m CE 15 The overlap capacitance C_Gate_SDB consists of T C Cii i b FG Z bs P intrinsic capacitance Cod overlap C overlap capacitance between gate and drain gs overlap overlap capacitance between gate and source C overlap capacitance between gate and bulk gb overlap Other capacitances can be calculated in the same way Please refer to the BSIM3 manual for more details Back to BSIM3v3 Characterization mosfet 147 MOSFET Models High Frequency Behavior Macro Model for High Frequency Application Using the BSIM3v3 model for the simulation of high frequency applications requires a major change in the model structure A new concept of a SPICE simulation model for deep submicron devices based on the standard BSIM3v3 3 0 model was found which is able to satisfy a correct DC simulation and the representation of the RF behavior of the MOS devices The following figure shows the subcircuit used for RF simulation using the BSIM3 model together with an explanation of the physical structure responsible for each element of the subcircuit Equivalent Circuit for the SPICE Macro Model The model itself is implemented as the macro m
36. 90 MOSFET Models F_ParName 1 PARAMETER 2 Parameter which is shown Special data handling and simulation Transforms to be executed after data is loaded F_Prepare ICCAP_ARRAY 0 No transform is executed F_Prepare ICCAP_ARRAY 2 More transforms are executed ordered from 0 up to x F_Prepare O 7RANSFORM Name of the transform in the setup where F_Setup points to F_Prepare 1 DUT SETUP TRANSFORM Begin with DUT if a transform is not in this setup Transforms to be executed instead of simulation F_Simulate ICCAP_ARRAY 0 The setup specified in variable F_Setup will be simulated F_Simulate ICCAP_ARRAY 2 F_Simulate O 7RANSFORM Name of the transform in the setup where F_Setup points to F_Simulate 1 DUT SETUP TRANSFORM Start with DUT if a transform is not used in this setup Plots F_UsedPlot ICCAP_ARRAY 4 Number of displayed plots Counting starts at the upper left corner filling up a row first before going to the next row F_UsedPlot 0 log_id_vg Plot displayed top left Plot is specified inside the setup by F_Setup F_UsedPlot 1 Large idvg id_vg Plot displayed top right F_UsedPlot 2 log_id_vd Plot displayed bottom left Plot is in the setup specified by F_Setup F_UsedPlot 3 Large idvg id_vd Plot displayed bottom right Region PEL code F_RegionPEL_default If empty no region PEL code is used no user defined code
37. Available Functions S TOXO TOXO NSUBO VFBO TOXO NSUBO VFBO TOXO NSUBO VFBO DLQ TOXO NSUBO VFBO DLO Group and Function ID s Export and Import of Customized Extractions Identifikation 71 MOSFET Models Each item has a unique ID This ID will be used to identify functions in a poroject Menu Options Display ID s Export To export a configuration use the menu Configuration gt Export Model Configuration The Configuration will be exported using the IC CAP dut format Import It is possible to import configurations created using the Configuration Wizard This will be necessary if IC CAP updates are installed eOpen PSP_DC_CV_ Extract for example eOpen a project necessary to modify the functions eOpen the Configuration Wizard Menu Tools Configuration Wizard eImport the previously exported configuration see Export Menu Configuration Import Model Configuration 9 Exported configurations cannot be imported into other MOS models e g a PSP configuration cannot be imported into BSIM3 Exported configurations cannot be merged because their ID s are not unique To get a model which provides all Customized Functions it is necessary to import the Model Configuration first before using the Configuration Wizard for further modifications when working with newly installed default models e Back to DC Extract mosfet e Back to Extraction of DC and CV Parameters mosfet Overvi
38. DVT2W Body bias coefficient of narrow channel effect on VTH 0 032 l1 1 V le ETAO DIBL coefficient in the subthreshold region ETAB Body bias for the subthreshold DIBL effect 0 07 l1 v es ee E 2 2 2 2 Mobility Mobility at T TNOM NMOS 670 marn PMOS 250 5 UA F First order mobility degradation coefficient 2 25E 9 m V UB Second order mobility degradation coefficient 5 87E 19 m v luc Body effect of mobility degradation 0 0465 Jam Loo M i 2 3 Drain current VSAT Saturation velocity 8 0E4 m s ao Bulk charge effect coefficient 1 0 E Al First non saturation factor 0 1 V A2 Second non saturation factor 1 0 AGS Gate bias coefficient of Abulk 0 0 1 V BO Bulk charge effect coeff for channel width 0 0 im B1 Bulk charge effect width offset 0 0 Im KETA Body bias coefficient of the bulk charge effect 0 0 1 V KETAS Surface potential adjustment for bulk charge effect 0 Vv ff 2 4 Gate current 946 NTOX Power term of gate current o TOXQM effective oxide thickness for Igb calculation TOX om ALPHAGB1 First VOX dependent parameter for gate current in inversion 0 35 1 V BETAGB1 Second VOX dependent parameter for gate current in inversion 0 03 1 V2 VGB1 Third VOX dependent parameter for gate current in inversion 300 Vv ALPHAGB2 First VOX dependent parameter for gate current in accumulation 0 43 1 V BETAGB2 Second VOX dependent parameter for gate current in 0 05 1 V2 accumulation VGB2 Third VOX depen
39. F_UsedPlot 2 see figure above It is irrelevant whether Plot2_x1 Plot2_y1 is lower than Plot2_x2 Plot2_y1 or not the boundaries will be corrected automatically Now select the transform execute_UO_UA_UB_EU_UC_opt and change to the Inputs tab Add the target and simulated data as well as the boundaries for the x and y range by writing into the third column Don t forget to enter the y boundaries in the Target Min Max field located above x Min Max Optimizer definition for opt_UO_UA_UB_EU_UC Select Transform extr_VTH_rough tr_UO extr _VOFF_NFACTOR Algorithm Levenberg Marquardt v Error Relative v extr_VTHO S extr_K1_K2_NDEP Inputs Parameters Options extr_UA UB_EU extr_UC extr_AIGBINY_BIGBINY Target id m derivative vg id m 1 extr_AIGBACC_BIGBACC Simulated id s derivative vg id s 1 extr_UA UB_UD_EU Weight 1 00000 1 00000 1 00000 opt_All_Idvg Target Min Ploto yi 0 00000 opt_UO_U amp UB_EU_UC opt_YOFF_NFACTOR Target Max PlotO y2 0 00000 opt_VTHO_K1_K2 opt AIGBINV BIGBINV_CI xX Min PlotO x1 0 00000 opt_AIGBACC BIGBACC x Max PlotO x2 0 00000 opt_All_Igate opt_UO UA UB_EU UC _U execute _UO UA UB EUL F execute_vO Fe Curve Min Curve Max X Data Ref Parameters defined on the Parameters tab will be overwritten by those defined in transform opt_U0O_UA_UB_EU_UC when opening the tuner optimizer in the GUI window The plo
40. File Initialize Binning Extract Plots HTML Options Boundaries Help SiD Bele le lariat ee Alea ae el Notes Information Initialize Binning n a Extract HTML Options Boundaries Extraction Flow Extraction Intermediate Results a My Scale Extraction Group Function Flow Available Functions E NPO NPL User defined NPO NPL NPO NPL TOXO LVARO LVARL DLO TOXO LVARO LVARL DLO VFBO VFBL VFBW VFBLW VFBO VFBL VFB VFBLW VFBO VFBL VFBW VFBLW My Scale Extraction Group lt The selected extraction starts wath the result not yet avaiable Messages Tuners M Test Mode W Diagrams Project psp_nmos Project directory d ICCAP_Examples User_defined_Functions PSP Status Getting Started In the Main window edit model_files mosfet PSP PSP_DC_CV_Extract mdl from your IC CAP example folder Open the DUT C_Oxide and add a new setup named User_cg_vg to the DUT You can use any name for the setup according the IC CAP conventions Adding a user defined function to a global main group Copy the existing transforms opt_TOXO_NSUBO_VFBO and 79 MOSFET Models execute_TOXO_NSUBO_VFBO_opt from the setup cg_vg to the new setup Rename the transform to opt_TOXO_VFBO and execute_TOXO_VFBO_ opt All transforms managing an optimizer must begin with opt_ while all transforms managing an extraction step must begin with extr_ Do
41. HiSIM_HV solves the Poisson equation iteratively including the highly resistive drift region effects depending on the structure of the MOS transistor to be modeled The following figure cross section through a LDMOS and a HVMOS structure shows the drift region resistance parameters and their usage 247 MOSFET Models Asymmetrical LDMOS Channel Symmetrical HV MOS Ldrift2 Ldrift Loverld Channel Asymmetrical HV MOS Ldrift2s Ldriftis Lovers Novers Channel With Version 1 1 1 of the HiSIM_HV model you have the choice of using an asymmetrically structured HVMOS transistor The lower part of the figure above shows the geometrical meaning of parameters of the asymmetrical model Version HiSIM_HV 1 2 0 includes LDMOS devices with additional substrate node Therefore additional parameters have been introduced to cover this situation VBISUB RDVDSUB RDVSUB DDRIFT and NSUBSUB Larita Drift Region N Channel Region N subsub V sub s Cross Sections and Drift Resistance Parameters There is a limit for the bulk voltage considered to model the bias dependency of the drift region resistance This limit is set per default to Vbs min 10 5V However there is a parameter that can be used to override this default setting called VBSMIN Resistance Modeling in HiSIM_HV The most critical aspect of modeling a high voltage MOS transistor is the drift region resistance m
42. If you do there will be an error stating that there is a variable array not to be found This is a problem with the IC CAP tree GUI element There is a workaround to this problem If you move the New Main Group to the end of the tree by using the right mouse menu Move Down it will be empty Adding a new group works in the same way Right click on a Main Group select Add Group and rename the new group to the desired name The inserted group will be marked with a green triangle to show that this group can be modified see Figure 9 below Editable group marked with a green triangle ern Configuration Wizard for Extraction Functions 12 Configuration Edit Options Help 660 EH Available Extractions Overview Customized Functions D Available Extractions O Global ia Local Capacitance Cgg l gt Local Long Wide lt gt Local Length Dependence Wide Adding functions to new groups An easy and convenient way to create modified functions is the Copy and Paste menu item Using this item you are able to copy existing functions from default extraction steps to your newly created groups Select any extraction step use the right mouse menu to copy that step Copying of an existing extraction step Available Extractions Overview Customized Functions Available Extractions H O Global CH ia Local Capacitance Cgg gt Local Long Wide gt Local Length Dependence
43. Improved sub threshold temperature dependence Improved thermal noise model tnoiMod 2 Limiting of diode ideality factor NJS NJD New parameter mtriCompatMod to ensure consistent results of mtriMod 0 versus mtriMod 1 BSIM4 6 5 bug fix e Source and Drain diode current shows unrealistic high values for Aseff Pseff Adeff Pdeff 0 although it shows correct prediction for positive values of Aseff Pseff Adeff and Pdeff BSIM4 6 2 brings some bug fixes and enhancements In detail these are Bug Fixes Output conductance model VASCBE Thermal noise model tnoiMod 0 Negative thermal noise tnoiMod 1 Source Drain bulk junction capacitance Derivative issue in capacitance model capMod 0 Toxpcalculation in MTRLMOD 1 Divide by zero in Rend Typo in SC Drain Body breakdown voltage SCEFF calculation Enhancements Width dependent TAT model High k mobility model The BSIM4 6 2 source code BSIM4 6 2 user manual BSIM4 5 0 new enhancement document and testing examples can be downloaded at http www device eecs berkeley edu bsim page BSIM4_ Arc see also BSIM4 References mosfet 1 This section provides information on the following topics Whats new inside the BSIM4 Modeling Package mosfet Basic Effects Modeled in BSIM4 mosfet Key Features of the BSIM4 Modeling Package mosfet BSIM4 DC Behavioral Modeling mosfet BSIM4 CV Modeling mosfet The BSIM4 RF Simulation Model mosfet Test structures for
44. Path Browse Project TT Proiccts in Path Import Cancel Enter the name and location of the new BSIM3 project to be created and choose Import After the data is imported you will get a message stating that the BSIM3v3 data has been successfully imported and you should go to the DC Transistor DUTs folder which looks like the following figure Imported MASTER_MEAS_nmos mdl from a former BSIM3v3 project 6SIM3_DC CV Measure New Open Savers Dewe Pret Help irio Demo _mpot BSIM3 3 Notes Meceusemert Corone Temperature Senp Swatch Matix OC Transist BUTs Capactance DUT OC Diode DUTE Options Senp DUT 200 wW L aD AS PO P NWF Comment Soe Sen IK lum hm pa a um furs Caaguy Laige_m M 10 10 10 t0 22 22 1 Large Marrow _m M 04 0 OF Os 23 28 1 Addnona DUT Nasow_rt M 09 10 os 09 36 36 1 Addhona Add Hanom m M 12 10 12 12 44 44 1 Adona Delete ami M 10 aa 10 10 22 Addhona 1e Sht M 10 os WwW 10 22 22 Addhonal Temp Mess Shut m M 0 OF 0 0 2 2 1 Addhonal anes Shat m3 M w0 oF 0 WwW 2 2 1 Adanona Bita Ciao Strot_md M w 1 0 wWw 2 2 1 Adona Smam M ta o5 of os 28 28 1 Adona m Smam M w of o8 os 36 36 1 Addhond Daplay Smal m M 12 O28 12 2 6 u 1 Adabond The DUT names already contain the functionality This may be confusing but you can change the names after the import procedure iol xi Lage w 12 ws Fi Soae os isc H 04 mal Narrow lum 0 2
45. RBSB References mosfet 7 8 The substrate resistance can be seen in the reverse reflection coefficient S22 at the output of the transistor Together with the resistance network the internal drain bulk and source bulk junction diodes of the BSIM3v3 3 0 model are replaced by the external elements Djdb_area Djdb_perim Djsb_area and Djsb_perim The decoupling diodes account for the same voltage dependant values of the bottom and the sidewall capacity as the internal junction capacitances This replacement is the prerequisite for a correct modeling of the substrate resistance With this approach the model is valid for both the DC and the RF behavior of the transistor Influence of gate resistance on input reflection S11 148 MOSFET Models L 6 25um Wringer 1Gum Nfinger 16 S11 with gate resistance y gt tu S deemb S 11 a Pee eee eee mw S deemb M 11 11 without gate resistance TttiTIitTititititt Single Subcircuit Model for BSIM3v3 RF Transistors The macro model approach results in a subcircuit for single RF MOS transistors which the following circuit file shows Subcircuit for RF modeling of single transistors using the BSIM3 model BSIM3 RF Subcircuil L Pidareo a Djdb_peri Rbpd 40 41 SOURCE Following is part of the SPICE netlist used for single transistors in BSIM3v3 RF modeling LINK CIRC Circuit data Circuitdeck OPTIONS GMIN 1 0E 14 Single s
46. See Also DC and CV Measurement mosfet Extraction of DC and CV Parameters mosfet Extraction of Parameters for the RF Models mosfet Using the MOS Modeling Packages mosfet De embedding Pad Structures The De embedding Pad Structures folder enables you to select the type of pad structure used for de embedding the parasitics of the measurements Measurement of the transistors for parameter extraction requires connecting the devices to the instruments Therefore the basic transistor element to be measured must be connected using pads and metal connections on the wafer In order to get the parameters of the basic transistor without metal connections and pads the parasitics must be de embedded from measurement results A device library should contain only the basic transistor element The connections to other elements in a circuit have to be modeled separately since this is part of the interconnection between elements on a chip Basically you perform error correction of your network analyzer in order to eliminate measurement errors resulting from cable connections used to interface the analyzer to the wafer prober and up to the probe tips Your test chip design must contain structures to eliminate the parasitics as a result of connecting prober needles via metal lines to transistor terminals This folder is intended to define the structures used to de embed the transistor parameters from measured ones Additional icons are visible when c
47. Set parameters to circuit default values Choosing the Set to Circuit Default Values menu item restores the defaults You can Add or Remove Parameters from the Initial Values list in the middle of the Initialize folder using the Initialize menu Select the type of model to be extracted There are two selections possible Sing e or Scalable Transistor Model For a detailed explanation see Single Transistor Model mosfet or Fully Scalable Device mosfet You can set initial parameter values manually To do so enter the desired values into the parameter fields provided for several parameters High Frequency Model Flag Selection for the BSIM3 left and for the BSIM4 right RF models Part of Initialize Folder r Model Flags Model Flags m High Frequency Model Flags r High Frequency Model Flags RGATEMOD gt RGATEMOD f gt ud ET RBODYMOD RBODYMOD iz i TRNOQSMOD TRANGSMOD 0 m 0 ACNOSMOD fn ACNOSMOD fn The BSIM3 model only uses one flag for RF modeling the NQSMOD flag non quasi static model see Non Quasi Static Model Parameters mosfet Set high frequency Model Flags for the extraction of BSIM4 PSP parameters by using the arrows provided to change the flag value The process is limited to allowed flag values of the respective RF model The flags can have values as listed in the following table High Frequency Model Flags for BSIM4 Values Meani
48. The ratio of Qd to Qs is the charge partitioning ratio Existing charge partitioning schemes are 0 100 50 50 and 40 60 _ _given by the model parameter XPART 0 0 5 and 1 which are the ratios of Qdto Qs in the saturation region The exact formulation is described inside the BSIMSOI4 manual Back Gate Charges Typically the buried oxide thickness of SOI devices lies in a range from 400 nm down to about 100 nm Compared to channel inversion and depletion charges back gate charge along the channel has not much influence However to achieve a proper back gate coupling factor and a continuous gate charge the back gate charge model is important Back gate charge has two components One component is coupled to the body the other component is coupled directly to the gate Back to BSIMSOI4 Characterization mosfet 305 MOSFET Models High Frequency Model This paragraph describes the high frequency model used for the BSIMSOI4 Modeling Package Macro Model for High Frequency Application Using the BSIMSOI model to simulate high frequency applications requires a major change in the model structure A new concept of a SPICE simulation model for deep sub micron devices based on the standard BSIM3v3 2 model was found to be able to satisfy a correct DC simulation and the representation of the RF behavior of the MOS device The model itself is implemented as a macro model and no changes are made to the BSIM3v3 2 model code itself This is the ul
49. Vz rw N EPSROX bs effective channel length and width Loge and Wee Loff E ae 2dL W an dW eff NF Well Proximity effect modeling With BSIM4 5 0 the calculation of influences from the so called we l proximity has been introduced Deep buried layers possible by using high energy implanters affect devices located near the mask edge Ions scattered at the edge of the photo resist film can influence the threshold voltage of those edge devices A threshold voltage shift in the order of around 100 mV have been observed BSIM4 References mosfet 1 The following figure shows the effect BSIM4 References mosfet 7 high energy ions BSIM4 5 0 considers the variations of threshold voltage mobility and body effect through newly introduced parameters SCA SCB SCC SC WEB WEC KVTHOWE K2WE KUOWE SCREF and WPEMOD The relevant model equations are Vtho VthO orig KVTHOWE SCA WEB SCB WEC SCC K2 K2 K2WE SCA WEB SCB WEC SCC Hoff Hef orig 1 KVTHOWE SCA WEB SCB WEC SCC Variables and parameters used in modeling threshold voltage 193 Equation Variable VTHO Ki K2 K3 K3B WO LPEO LPEB kB T q Ldrawn Wdrawn NF TOXE TOXM DVTO DVTOW DVT1 DVT1W DVT2 DVT2W DSUB ETAO ETAB NDEP NSD Si EPSROX Ds Vbs Vds BSIM4 Parameter VTHO Ki K2 K3 K3B WO LPEO LPEB NF TOXE TOXM DVTO DVTOW DVT1 DVT1W
50. Wide Now navigate to any editable group any group other than default groups and select that group using the right mouse menu Paste Paste the extraction step to an editable group Available Extractions O Global 3 O Ney Main Group f ra New Group eg Local Capacitance Cag You are able to add spaces to organize the extraction flow making it more readable by 65 MOSFET Models pressing Insert Space from the right mouse menu You can move the spaces up and down to suit your needs Spaces have been inserted to enhance readabilit Configuration Wizard for Extraction Functions 1 2 Configuration Edit Options Help a eS 7 oH EE Available Extractions Overview Customized Functions Default Extraction Flows Available Extractions Global a New Main Group PEL Defined Function not editable F i 4 New Group Local Capacitance Cag Function C Calculate Parameter Type extraction E Parameter Initial Values SER Name E NEFF mana QR COX_NP TRAINEE COX NP 1 Data Selection Generate Customized Function Caption Default Size Category Insert Space lt ie Ble g te Bile D le B oeonmonomonmaonm Move Down Sort Devices by t Local cay amp Local tec Ras lt gt Local Length Width Dependence PSP Scale Parameters m s a sem 8 i f f Move Up Selection Policy f j Plots L ocal co dsb vajco verlap vg LO
51. Ws Kcm RTHOW 0 Ee e RTHOWP o o a RTHONF o ooo POwRAT dho bo oOo hao O DO E E E U E XLDLD ie 6 im LOVERLD l1e 6 im NOVER 3E16 FE NOVERS 0 lem 3 VFBOVER 0 5 Vv CVDSOVER o 0 1 0 For modifying Cag spikes Qovsm 0 2 For smoothing of Qover LDRIFT1 lo Length of the lightly doped driftregion m o LDRIFT2 1E 6 Length of the heavily doped drift region mo o LDRIFTIS 0 Length of the lightly doped driftregion im LDRIFTIS 1E 6 Length of the heavily doped drift region m RDVG11 loom a e E RovGi2 000 RDVD e2 foo O OwA Rovs b Po ooo DoS o S Eo Ros bo To O Po Do S Eoo Rose Woo ooo Po ooo S Eoo Rovot b oZ Po Doo S Eoo Rovor Wo Poo DoS o S Eo o Rovos b oOo DS s S Eoo Rovose tt S S S oO Rozo b o Z Po Do S Eoo Rozi Wo Poo Po ooo S Eoo m RD22D 0 0 2 0 RD23 0 5 c RD23L 0 RD23LP 1 RD23S 0 rr o RD23SP 3 3 33 nia RD25 0 RDOV11 0 cover dependent reatence Lover dependent resistance RDOV12 1 0 L Lover dependent resistance RDOV13 0 1 0 1 0 Lover dependent resistance RDSLP1 0 Ldrift1 dependent resistance RDICT1 1 0 Ldrift1 dependent resistance RDSLP2 1 0 Ldrift2 dependent resistance g RDICT2 0 Ldrift2 dependent resistance RDTEMP1 0 Temp dependent resistance m K RDTEMP2 0 Temp dependent resistance m K2 RDVDTEMP1 0 Temp dependent resis
52. a Fs g m V CIGSD CIGSD Parameter for Igs and Igd NMOS 0 075 PMOS 0 03 V NIGC NIGC Parameter for Igcs Igcd Igs and Igd 1 0 PIGCD PIGCD Vgs dependence of Igcs and Igcd 1 0 Drain Current Model Bulk Charge If a drain source voltage other than zero volts is applied the depletion width along the channel will not be uniform Therefore the threshold voltage VTH will vary along the channel This phenomenon is known as the Bulk Charge Effect Inside BSIM4 the bulk charge effect is formulated as follows 200 MOSFET Models 1 A iL e bulk 1 KETA V seff JL LPEB L oe Kioy lia K ox 2 fe y e N S bseff i TOXE I n P Wage T S Lofft 24AT Xdep Leff 7 1 AGS V age Ae a B51 AT gt 2 T Xep eff Note Abulk is about 1 for small channel lengths and increases with increasing channel length Drain Current Parameters Equation Variable BSIM4 Parameter Description Default Value Abulk Bulk charge effect AO AO Bulk charge effect coefficient 1 0 x XJ Source Drain junction depth 150E 9 m Xdep depletion depth AGS AGS Coefficient of Vgs dependence of bulk charge effect 0 0 1 V BO BO Bulk charge effect coeff for channel width 0 0 m Bi B1 Bulk charge effect width offset 0 0m KETA KETA Body bias coefficient of the bulk charge effect 0 047 1 V Unified Mobility Model Mobility of carriers depends on many process parameters and bias conditions Modeling mobil
53. extract Settings project_name dc_meas settings set measure extract project_name rf_meas settings set measure extract project_name lwc model name settings set extract extract MOSFET Models Bou ndaries lwc model name boundaries set extract extract default for export ee project_ MS csecincimodelameympe name mps measure measure E forataled mode scaled model ete project_name DUT project_name DUT_name lwc model name mps name mps 5 extract for for single model gt model MIB project_name DUT_name Simulator Iwc model name lib extract for single model project_name Simulator lwc model name lib extract extract for scaled model Logfile project_name lwc model name log_fail txt extract extract MDMs project_name DUT_name dc_idvg TempkK mdm measure extract project_name DUT_namewdc_idvd TempkK mdm measure extract project_name DUT_name c_bd_area TempK mdm measure extract project_name DUT_name c_bd_perim TempkK mdm measure extract project_name DUT_name c_bd_perim_gate TempK mdm measure extract project_name DUT_name c_bs_area TempK mdm measure extract project_name DUT_name c_bs_perim TempK mdm measure extract project_name DUT_name c_bs_perim_gate TempK mdm measure extract project_name DUT_name c_d_g TempK mdm measure extract project_name DUT_name c_g_ds TempK mdm measure extract project_name DUT_name c_g_dsb TempK mdm measure extract project_name DUT_na
54. like a THROUGH device can be used to verify the de embedding strategy In general the complexity of the de embedding procedure depends on the frequency range of the measurements and the design of the test structures However a proper de embedding is the absolute pre requisite for an accurate AC modeling of the MOS transistor OPEN SHORT and THROUGH structure without MOS transistor Test Structures for S parameter Measurements 170 MOSFET Models Test Top View Input in Structure __Define DUT No of gates No of drains No lof sources AD IL W Area AS drain Area PD source Per PS drain Per source gue One single transistor Fme In parallel transistors No of gates 3 No of 3 drains No W of sources AD L W Area AS drain Area PD source Per PS drain Per source BSIM3 BSIM4 PERMOD W WNF 5 AD no_dran a b5 AS no_source a b PD no_drain 2 a b PS no_source 2 a b BSIM4 PERMOD 0 PD no_inner drain 2a no_outer_drain 2 a b PS no_inner_source 2c no_outer_source 2 b c No of gates 6 4 multifinger transistors drains No wt lof sources Ap L W Area drain Area i source Per PD drain Per PS source ff IA A ay ain HB cate p Si De embedding procedures The DUT Deembedding gt Calculation contains five different setups two for general purposes and three
55. the measurements You can modify these examples by changing the low and high connection of the CV meter Test Structures for CV Measurements DUT Shape Applied bias n type Comment Area diode a Drain source with a large i n area a small perimeter Vea and the doping Bulk pP concentration nt of the drain source region C_Area_m pn junction shown here for an n type C_Perim_m pn junction 167 MOSFET Models C_Perim_m pn Finger diode junction Drain source with a large n perimeter a Via small area and the Bulk p doping concentration n of the drain source region shown here for an n type device Q AD PD NF a b NF 2 a b Finger diode with a large perimeter a C_Perim_Gate_m n junction gt pn j Drain source 1 small area Via and the doping Bulk p concentration n of the LDD region shown here for an n type BSIM3 BSIM4 PERMOD 1 AD NF a b PD NF 2 a b W WNF 2 6 BSIM4 PERMOD 0 PD NF 2 a W NF 2 b C_Oxide_m Gate oxide Large area C_Gate_SD_m Overlap gate drain source A large number of BSIM3 BSIM4 PERMOD 1 168 bulk drain source C_Gate_SDB_m Overlap gate MOSFET Models W WNF 5 AD no_dran a b AS no_source a b PD no_drain 2 a b PS no_source 2 a b BSIM4 PERMOD 0 PD no_inner drain 2a no_outer_drain 2 a
56. the model is generated without the usual need for simulation and optimization as required by all previous empirical models The Root MOS model captures the nonlinear device behavior for any MOSFET device for which measured data can be taken but for which there are no good physical or empirical models Based on your inputs the data acquisition system sets the DC bias levels and controls the system hardware to measure DC and S parameters The model generator processes the measured data and generates the lookup tables required by a circuit simulator It produces data files that are directly readable by the Agilent RF and Microwave Design System MDS Both IC CAP and MDS can run simultaneously in the X Windows environment During simulation the tabular state function data from the generated Agilent Root MOS model is interpolated using multidimensional spline functions to emulate the terminal characteristics of the device Prerequisites Before getting started with this tutorial ensure the following e The system is set up and switched on e The calibration standards are removed from their containers to allow them to reach ambient room temperature e IC CAP is properly installed on the computer e IC CAP is configured to recognize the system hardware and the SMUs are renamed to following o Rename a medium power SMU connected to the device base as SMUL o Rename a high power SMU connected to the collector as SMU2 o Rename the GNDU unit which
57. tmp rsb2 Pea RAR tmp rsb1 tmp rsb2 In addition the channel length variation inside a multifinger device is not constant BSIM4 References mosfet 4 This behavior is taken into account using a variable channel length variation as a function of the number of gate fingers Using the parameters DLO DL1 and DL2 this channel length variation can be set Channel Length Reduction Difference DLO DL1 DL2 Channel Length Reduction Difference inside a Multifinger Device 214 MOSFET Models Channel length variation set with DLO DL1 DL2 Effective new channel length reduction Original channel length reduction from DC parameters No A im ger The implementation of these enhancements requires the fully scalable model defined in a subcircuit The following example shows the netlist implemented into the ADS simulator LINK CIRC Circuit data circuitdeck Fully scalable subcircuit model for BSIM4 5 0 RF n type devices Simulator Agilent Advanced Design System Model BSIM4 Modeling Package Date 09 02 2006 Origin ICCAP_ROOT bsim4 circuits hpeesofsim cir rf_nmos_scale cir Information for model implementation In ADS call the sub circuit model as follows with the actual values of L W etc BSIM4 RF_Extract x_rf_transistor n1 n2 n3 n4 tmp_l 0 25u tmp_w 80u Please note that according to the BSIM4 model definition the parameters tmp_w tmp_ad tmp_as t
58. 0 Test Mode vgb E Extraction Step Capacitance Oxide Function O TOXO NSUBO VFBO DLQ Save Starting Values gt 9 If a modified project is loaded using the default PSP_DC_CV_Extract model a message will appear that the project is using functions which are not available in this modelfile Warning when opening a project using a modelfile not containing required customized functions st Some required Functions are not not avilable in this model The extraction flow of this project contains the following Functions which are not available in this IC CAP modelfile CUSTOM_G0001 used in Capacitance Oxide The reason is that this project was modified in another modelfile which had those Functions available The actual results may no longer fit the measured devices To use this Function please quit the actual project without saving it and load the customized functions through the menu Tools Configuration Wizard If the actual project is saved or any extraction is executed this Function will be removed from the extraction flow If you would like to remove the unavailable functions store the project All used functions other than default functions factory settings of IC CAP will be removed If you would like to use the customized functions with this project close it without saving Load the modelfile containing the required functions into the IC CAP Main Window PSP_DC_CV_Extract for exa
59. 000u ldsat 1 024m 1E 4 Idsat LOG oo 1E 5 1E 7 1E 6 1E 5 Ldes LOG A check for the consistency of measured data can be activated by choosing Configuration gt Check Data Consistency This check is only possible when the Measurement subfolder is selected in the tree view You will get a message if the rules of strict consistency are observed otherwise you will get an error message See Consistency Check of DC measurement data for multiple measured devices mosfet for details 29 MOSFET Models If the Device List subfolder is activated you can check the DUT configuration by selecting Configuration gt Check DUT Configuration from the menu A window opens up to show misconfigured devices in detail You can dump the contents of this window to the IC CAP status window for reference Capacitance Click on the sign in front of Capacitance in the tree view to open the Measurement definitions and the Device List for preparing capacitance measurements Select Measurement to enter the polarity of the device the measuring voltages and connections of the instrument as shown in the following figure Physically Connecting Test Structures to your Capacitance Measurement Device The following figure shows how to connect the CV instrument to measure oxide and overlap capacitances See also the paragraph on test structures for CV measurement In Test Structures for CV Measurements mosfet you ll find recommended test struct
60. 075 PMOS 0 03 DLCIG ls Source Drain overlap length for Igs IL LINT DLCIGD ls Source Drain overlap length for Igd LINT NIGC Parameter for Igcs Igcd Igs and Igd 1 0 POXEDGE Factor for gate oxide thickness in t o 222 PIGCD NTOX TOXREF VFBSDOFF IJTHSREV IJTHDREV IJTHSFWD IJTHDFWD XJBVS XJBVD BVS BVD JSS JSD JSWS JSWD JSWGS JSWGD CJS CJD MJS MJD MJSWS MJSWD CJSWS CJSWD CJSWGS CJSWGD MJSWGS MJSWGD PBS PBD PBSWS PBSWD PBSWGS PBSWGD JTSS JTSD JTSSWS JTSSWD JTSSWGS JTSSWGD NJTS NTJSD NJTSSW NJTSSWD NJTSSWG NTJISSWGD XTSS XTSD XTSSWS XTSSWD XTSSWGS XTSSWGD VTSS VTSD VTSSWS VTSSWD VTSSWGS VTSSWGD TNITS TNITSSW TNITSSWG XPART CGSO source drain overlap regions Vgs dependence of Igcs and Igcd Exponent for the gate oxide ratio Nominal gate oxide thickness for gate direct tunneling model Flatband Voltage Offset Parameter Diode Characteristics Source Limiting current in reverse bias region Drain Source Limiting current in forward bias region Drain Source Fitting parameter for diode breakdown Drain Source Breakdown voltage Drain Source Bottom junction reverse saturation current density Drain Isolation edge sidewall reverse saturation current density Gate edge sidewall reverse saturation current density Bottom junction capacitance per unit area at zero bias Bottom junction capacitance grating
61. 1 Parasitic Resistances Parameters Parameter Name Default Range min Range max Description Unit RS 0 0 10m source contact resistance in LDD Ohm m region RD 0 0 10m drain contact resistance in LDD region Ohm m RSH 0 0 lim source drain sheet resistance Ohm square RSHG 0 0 100y gate sheet resistance Ohm square GBMIN 1E 12 substrate resistance network p RBPB 50 substrate resistance network Ohm RBPD 50 substrate resistance network Ohm RBPS 50 substrate resistance network Ohm RBDB 50 substrate resistance network Ohm RBSB 50 substrate resistance network Ohm Binning Model Parameters Parameter Name Default Range min Range max Description Unit LBINN 1 power of Ldrawn dependence e WBINN 1 power of Wdrawn dependence eo ma wo maximum length of Ldrawn valid um LMIN 5 minimum length of Ldrawn valid um WMAX maximum length of Wdrawn bm valid WMIN minimum length of Wdrawn valid um Additional and avn HISM 2 5 1 Parameters with respect to HISIM 2 4 1 243 Parameter Name Default Model Control Flags ICOQOVSM 1 CORECIP 1 COQY 0 Process Parameters NPEXTW 0 NPEXTWP 1 0 Velocity Saturation SC4 0 PTL 0 PTLP 1 0 PTP 3 5 PT2 0 PT4 0 PT4P 1 0 GDL 0 GDLP 0 GDLD 0 NSUBPL 0 001 NSUBPFAC 1 0 removed IPTHROU 0 Mobility Model MUEPHL2 0 MUEPLP2 1 0 MU
62. AGS 0 BO mpar B0 0 echo B1 Smpar B1 0 KETA Smpar KETA 0 047 A1l Smpar A1 0 A2 Smpar A2 1 echo RDSW Smpar RDSW 0 PRWB Smpar PRWB 0 PRWG Smpar PRWG 0 WR Smpar WR 1 echo WINT Smpar WINT 0 WL Smpar WL 0 WLN Smpar WLN 1 WW Smpar WW 0 echo WWN Smpar WWN 1 WWL Smpar WWL 0 DWG Smpar DWG 0 DWB Smpar DWB 0 echo LINT mpar LINT 0 LL Smpar LL 0 LLN mpar LLN 1 LW mpar LW 0 echo LWN Smpar LWN 1 LWL Smpar LWL 0 echo VOFF Smpar VOFF 0 08 NFACTOR Smpar NFACTOR 1 CIT Smpar CIT 0 echo CDSC mpar CDSC 2 4E 4 echo CDSCB Smpar CDSCB 0 CDSCD Smpar CDSCD 0 PCLM Smpar PCLM 1 3 echo PDIBLC1 Smpar PDIBLC1 0 39 echo PDIBLC2 Smpar PDIBLC2 0 0086 PDIBLCB mpar PDIBLCB 0 0 DROUT Smpar DROUT 0 56 echo PSCBE1 Smpar PSCBE1 4 24E8 echo PSCBE2 Smpar PSCBE2 1 0E 5 PVAG Smpar PVAG 0 VBM Smpar VBM 3 echo ALPHAO Smpar ALPHA0 0 ALPHA1 Smpar ALPHA1 0 BETAO Smpar BETA0 30 echo JS 1e 20 JSW 1 0E 20 NJ 1 IJTH mpar IJTH 0 1 echo CJ 0 MJ 0 5 PB 1 CJSW 0 echo MJSW 0 33 PBSW 1 CJUSWG Smpar CUSWG 5E 10 MJSWG Smpar MISWG 0 33 echo PBSWG Smpar PBSWG 1 CGDO mpar CGDO 0 CGSO Smpar CGSO 0 echo CGBO Smpar CGBO 0 echo CGBO mpar CGBO 0 CGSL Smpar CGSL 0 CGDL mpar CGDL 0 echo CKAPPA Smpar CKAPPA 0 6 CF Smpar CF 0 echo NOFF Smpar NOFF 1 VOFFCV Smpar VOFFCV 0 ACDE S
63. Adjustment of Local and Global Parameters 0 0000 Binning of PSP Models saa si ca vee ie te ee de Ae Oe ke ee a ROS A aS Parameters for the PSP model a ites dsi 2 et ae Ad Bae eS Swe E ed we Extraction of Parameters using the Local Global approach 0 cee es BSIMSOI4 Characterization aaoo a oe oa Se ie ee RoE eae ie ee earl ge Se eee ee Introduction to BSIMSOI Model ens asada wot ted pees Heese Aes ty eg Ae ad SS Se 2 TV Characterization su gata Bide Meteor ee hae Bed ee Sedan et wee wat ae Oe eee Gear St Shi ans ew a Binning of Model Parameters in BSIMSOI4 1 0 es CVC aracleriZallOn lt 5 a ani ea hi Pea SG gS Slee eee eee we SG ee ae idea ae High Frequency Model i ie Gs aine ecu iat a Ea as cet a ea a ae gh a ee a ee a Test Structures for SOL MOSFET 2120 554 528 235 Sse bee ee bee Bee AES oe eae SPICE Model Parameters areires iesind Sas Be ee eh cde aia Sa ee a BB aie eed he Agilent Root MOSFET Model Generator 1 00 0c ce es MOS Model 9 Characterization a n noosa ached dow Se eee oe eek OR BG OR Sew eee oa Ge Introduction to MOS Model 9 2 s06 ae a Sew eae Ge Sid Meee Oe Re OR er eave Seed Mhe IMIS WGC Filesi dais een Oe aah ts apr u an be cd alae Be se le i eh das di ee es al ae a nO ad a hay a oe Be de ieee Parameter EXUracti n uni a et inves ce Gites tay dat sn it op he aM he ae eral Site eal ay Nay Me mA a Gite ac eae es Swe Optimizing MOS Model 9 20 scales as co artes use sete eed He cde a
64. Bulk Source voltage Drain Source voltage Default Value NMOS 0 7 V PMOS 0 7 V 0 5 Jr 0 80 0 0 0 1 V 2 5E 6 m 1 74e 7 OV 300 3E 9m TOXE oO 0 53 5 3E6m 0 032 1 V 0 032 1 V DROUT 0 08 0 07 1 V 1E17 cm 3 1e20 cm 11 8 3 9 The following sections provide equations for effects modeled in the complete equation above Threshold Voltage Model Starting from the basic equation for long and wide channels the effects of shrinking dimensions and substrate doping variations are modeled step by step Basic Threshold voltage equation For long and wide channels the following equation is valid V Vent fth D y 5 N le Naza N VTHO si 7 C oxe f bs substrate S The equation above is valid under the following assumptions e constant substrate channel doping e long and wide channel Model parameters used for the equation above are listed in the table below BSIM4 model parameters used in the basic threshold voltage equation Equation Variable BSIM4 Parameter Description Y Nsubstrate Coxe VFB GAMMA NSUB VFB body bias coefficient Default Value uniform substrate doping concentration 6E16 cm 3 flatband voltage 1 0 V If the substrate doping is not constant or if the channel is short and or narrow the basic 194 MOSFET Models equation should be modified The following sections show modifications to
65. CAP In the second step the existing files are imported to IC CAP The necessary device information L W e t c is taken from the device list and is added to the file Furthermore different checks are performed to make sure that the file is correct If necessary settings are corrected or added In particular these are e node numbers G is associated to vg e t c e name of inputs vg must be in lower case After these modifications the files are saved in the new project directory Example Export Import Procedure Export a csv Sheet as a Template Open the DC_CV_Measurement module using the model you would like to import data into e g BSIM4_DC_CV_Measure Open a project e g BSIM4_for_experts Choose File gt Export gt DC device list or Capacitance device list or Diode device list A window opens for you to enter the name and path for the file Once the entries are made click Save A cSv file will be saved with the specified name and path The following figure shows the file Via Export generated csv sheet Subsite Device Name AdMOS_Proj Polarity SizeCategory STI VYPE COMMD G 5 B E Node6 Y urL um NF M AD um2 PD um AS um2 PS um NRD NRS LDRIFT1 um Mod_T1 W 5u0_L5u0_ bsim4_for_ex N Large SA ref VPE ref 1 2 31 32 5 571 1 5 11 5 11 0 D0 1 Mod _T1 W5u0 L5u0_ bsim4_for_ex N Large SA ref 3 4 31 32 5 5 1 1 5 11 5 11 0 D 1 Mod_T1 W 5u0_L5u0_ bsim4_for_ex N Large SA ref 5 6 31 32 5 1 1 5 11 5 11 0 D0 1 Mod_T1
66. Deep Submicron CMOS Processes mosfet SPICE Model Parameters for BSIM4 6 2 mosfet References 1 BSIM4 6 2 Manual University of California at Berkeley Copyright 2008 The Regents of the University of California See the web site of the device research group at UCB You can download the manual from the Internet using the following Web address http www device eecs berkeley edu bsim page BSIM4 Arc 2 Characterization System for Submicron CMOS Technologies JESSI Reports AC41 94 1 through 94 6 3 C Enz MOS Transistor Modeling for RF IC Design Silicon RF IC Modeling and Simulation Workshop Lausanne 2000 4 T Gneiting BSIM4 BSIM3v3 and BSIMSOI RF MOS Modeling RF Modeling and Measurement Workshop European Microwave Week Paris 2000 5 William Liu Mosfet Models for Spice Simulation Including BSIM3v3 and BSIM4 John Wiley amp Sons January 2001 6 M J Deen Ed T A Fjeldly CMOS RF Modeling Characterization and Applications Worldscientific Co authors F Sischka and T Gneiting 7 List of Bug Fixes and Enhancements for the BSIM4 6 2 model BSIM4 6 2 September 2008 to be found at the following Web address http www device eecs berkeley edu bsim page BSIM4 Arc Acknowledgements The BSIM4 model was developed by the UC Berkeley BSIM Device Research Group of the Department of Electrical Engineering and Computer Science University of California 187 MOSFET Models Berkeley and is copyrighted by the
67. F_ParName ICCAP_ARRAY 5 Parameter for optimizer tuner T O UO UA UB EU UC Measure Simulate Instrument Options Setup Variables Extract Optimize Select Transform Tune Fast extr_ TH_rough extr_UO Tune Slow extr_VOFF_NFACTOR extr_K1_K2_NDEP extr_UA_UB_EU extr_UC extr_AIGBINY_BIGBINY extr_AIGBACC BIGBACC View extr_UA_UB_UD_EU Rename ant A opt_UO_UA4 UB EU UC Store Par UPC YIP NFAL PZR opt_ THO_K1_K2 Recall Par opt_AIGBINY_BIGBINY_CI opt_AIGBACC_BIGBACC_ Undo Optim opt_All_Igate opt_UO_UA_UB_EU_UC_U execute_UO UA UB EU L execute_VOFF_NFACTOR execute_VTHO_K1_K2_opl execute_AIGBINY_BIGBIN execute_AIGBACC BIGBA execute_All_Idvg_opt execute_All_Igate_opt Yth vth2 vbs Optimizer O UOQ_UA_UB_EU_UC showing the newly introduced parameter TI MOSFET Models InteractiveP lot 1 2 File Options Optimizer Plots Windows Help id f V g Vb low Vd E 25 20 Ssesseseae Functions Devices Optimizer Region Boundaries show Calculate and show regions Hae Edit Calculation of regions Optimizer Features Algorithm Levenberg Marquardt Error LSA idam id s E 6 oo nn gm m s E 6 o 0A h Relative sim meas imeas 0 0 1 0 0 5 00 05 10 15 20 1 0 0 5 00 05 10 15 20 x Parameters vg E 0 vg E 0 v Y 348 IN_ 9 000 xb 0 000 V g1800 d2id_ 0000 fy ma Lee L Haetrae ane Name Min Value Max ia uo 1 0000
68. Files Delete All Files C Id d is Lin T or List T Imported data will be stored in MDM files which can be loaded as project Starting the measurement of the devices You will find an appropriate icon inside the row of icons or you can use Data gt Measure from the menu e To start measurement of the devices Click the Measure icon or Data gt Measure from the menu and select the DUT or Module to be measured using the dialog box that opens You can select a measurement temperature if there is a temperature other than TNOM defined in the temperature setup folder as well as a specific DUT or a Module containing all DUTs to be measured at a specific temperature If you select a temperature other than TNOM must be defined under TemperatureSetup only the devices set up for measurement at that temperature are selectable for measurement Start measurement with Measure or MeasureDUT in BSIM4 PSP on that dialog box If measuring at elevated temperatures be sure to wait until your devices are heated up or cooled down to the desired temperature 28 MOSFET Models Note For your convenience you will find a supplemental model file called prober_control mdl which is suitable to be used with automatic temperature measurements under the directories ICCAP_ROOT examples modelFiles mosfet BSIM3 4 examples waferprober Tailor this model file to your specific Thermochuck model and requirements Otherwise be sure to s
69. Fo Yr ideal V ho j FB o H Ky De N 2V in 4 a r T S tm0 N59 nom ee V tmo q where Vihideal ideal threshold voltage Vep flatband voltage surface potential nj 1 45 10 Tgm 7300 15 21 5566 Egg Vimo E40 1 16 7 02 e 1074 Taom Tnhom 1108 This equation had been implemented into the first MOS simulation models assuming long and wide channels and uniform substrate doping The following sections describe the effects that overlay this basic equation Non Uniform Vertical Channel Doping The substrate doping concentration N is not constant in the vertical direction of the channel as shown in the following figure Vertical Doping Profile in the Channel 121 MOSFET Models Approximatio Xt Doping profile Xsubstrate It is usually higher near the silicon to silicon dioxide interface than deeper in the substrate This higher doping concentration is used to adjust the threshold voltage of the device The distribution of impurity atoms inside the substrate is approximately a half Gaussian distribution which can be approximated by a step function with NCH for the peak concentration in the channel near the Si SiO interface and Nsub in the deep bulk XT is the depth where the approximation of the implant profile switches from NCH to NSUB The non uniform vertical channel doping affects the threshold voltage when a bulk source voltage is applied to the device and is represented he
70. For ft calculation 6 06E 009 Smallest gate voltage for S parameter simulations fi should be gt Yth Smallest drain voltage z o s for S parameter simulations e x Within this window select some DC and frequency settings for the extraction process Transit frequency fT of a transistor is being calculated using the standard procedure of measuring the gain at a predefined frequency and extrapolating fT from the gain bandwidth product of one Enter the frequency to be used for extraction into the PreSelection window Only frequencies defined in the measurement section using the Measurement Conditions folder are allowed Inside this folder you ve entered Start and Stop Frequency as well as Number of Frequencies to be measured Frequency sweep divided by number of frequency points results in specific frequencies to be measured Those are the frequencies you are able to select as constant frequency for fT calculation Be aware of the network analyzer s accuracy at lower frequencies when selecting the calculation frequency You can further specify the smallest gate and drain voltages to be used for S parameter simulations Choose the minimum gate voltage to be greater than the threshold voltage to ensure that the device is operating inside the active region Otherwise there will be a problem in extracting Rout This resistance is very high if the transistor is turned off resulting in large errors during extrac
71. Fringing field capacitance EPSROX 9 T e 4e 4 e 7 TOXE CLC Constant term for the short channel 0 1E 7 m model CLE Exponential term for the short channel 0 6 model DLC Length offset fitting parameter for CV LINT m model Width offset fitting parameter for CV WINT model VFBCV Flatband voltage parameter for CAPMOD 0 NOFF CV parameter in Vgsteff CV for weak to 1 0 strong inversion VOFFCV CV parameter in Vgsteff CV for weak to 0 0 V strong inversion ACDE Exponential coefficient for charge 1 0 m V thickness in accumulation and depletion regions in CAPMOD 2 MOIN Coefficient for the gate bias dependent 15 0 surface potential Temperature Modeling Parameters log 1 Temperature Modeling Parameters Parameter Description Default Value Unit TNOM Parameter extraction temperature 27 C UTE Mobility temperature coefficient 1 5 KT1 Threshold voltage temperature coefficient 0 11 Vv KT1L Channel length dependence of KT1 0 0 vm kr Threshold voltage temperature coefficient 0 022 ao Temperature coefficient for UA l1 1E 9 Im UB1 Temperature coefficient for UB 1E 18 an m V 2 Temperature coefficient for UC MOBMOD 1 0 056 MOBMOD 0 1 V m V and 2 0 056E 9 Temperature coefficient for UD 0 1 m 2 are Temperature coefficient for RDSW 0 0 2 m AT Saturation velocity temperature coefficient 3 3E4 m s a Emission coefficient for Source Ennion oho re 0 NJD Emis
72. GUI opens again and the project just created is now ready to open 37 MOSFET Models Using DC and CV Measurement Module with WaferPro IC CAP Wafer Professional WaferPro is a measurement application that is fully integrated into the IC CAP platform WaferPro is a solution to real customer characterization needs It takes advantage of IC CAP s powerful measurement and programming environment to enable a library of efficient measurement routines built in and user defined such as adaptive measurement algorithms that can greatly reduce the overall measurement time An introduction to WaferPro is available at WaferPro Introduction waferpro You must be familiar with WaferPro to utilize the features with the MOS Modeling Tools Setting the WaferPro Root Environment Variable Before you begin using DC and CV Measurement Module with WaferPro ensure to set the environment variable ICCAP_WPRO_ROOT to insta l_path waferpro where install_path is your IC CAP installation directory The following screenshot shows an example if IC CAP is installed in C agilent ICCAP_2011_04 waferpro path Edit User Variable variable name ICCAP_WPRO_ROOT Variable value I lagilentiICCAP 2011 O4 waferprol Exporting Measurements Routines There is an option from the MOS Modeling Tools to export measurements defined in the MOS Modeling Packages Device Definition folder to an open WaferPro project The following figure shows the Routin
73. IEEE IEDM 1997 8 C Enz MOS Transistor Modeling for RF IC Design Silicon RF IC Modeling and Simulation Workshop Lausanne Switzerland 2000 9 M Jamal Deen Ed T A Fjeldly CMOS RF Modeling Characterization and Applications Worldscientific Co authors F Sischka and T Gneiting 10 W Liu MOSFET Models for SPICE Simulation including BSIM3v3 and BSIM4 Wiley Interscience 2001 ena How to get the BSIM3v3 manual from University of Berkeley California University of Berkeley California provides an easy way to get a free copy of the BSIM3v3 manual and the BSIM3v3 source code from their world wide web home page http www device EECS Berkeley EDU bsim3 Other useful internet addresses Advanced Modeling Solutions http www admos de Agilent EEsof homepage http www agilent com find eesof Copyright BSIM3 has been developed by the Device Research Group of the Department of Electrical Engineering and Computer Science University of California Berkeley and is copyrighted by the University of California 186 MOSFET Models BSIM4 Characterization This section provides a theoretical background for the BSIM4 model It is based on the model revision BSIM7 released by the University of California at Berkeley on April 08 2011 Using the Modeling Packages is described in Using the MOS Modeling Packages mosfet BSIM4 7 enhancements Imporoved DIBL Rout model from BSIMSOI Improved GIDL GISL model from BSIMSOI
74. Models 5 WaferPro Warning Message You are about to synchronize Routines and Measurement Conditions to the IC CAP Routine file WaferPro will attempt to transfer current Measurement and Routine information to the new Routines However if Routines have been modified or deleted it is possible to lose data in the Measurement Conditions Table Please Note that this operation has no Undo Select Save to save this project before continuing Cancel to exit and OK to continue 7 Select an appropriate option in the Routine and Measurement Condition warning dialog box After the WaferPro is updated with the new measurement routines the measurement routines defined in your MOS Modeling Toolkit gets added to the default routines and additional device type definitions are imported The following screenshot shows the imported measurement routines Routine Routine DC_Transistor idvp is Active 7 Fie EGR Measure Extract Smua Optimize Data Tools Macros Windows Help SHIX 0 FORST o EBO DUTs Setups Crout Model Parameters Model Variables Macros Select OUT Setup t RoutreMy SOOO t Central titiss Setup Variables Extract Optimke Plots fiy MOS_DC_ basic gt try DIODE _DC_ CV basic esses GROUND SMU2 Compliance LIN a 1 idvg_VGstart Type idvg_VGstop Type T idvg_WGpts ee eee eee ee ee le is craig i ENE o PEHE Active Setup Routine _ Transistor iidvg Along with the measurement routines the addition
75. NFS W Input LD or LDEL WD or WDEL RD RS XJ DELTA NWM SCM CJ MJ Parameter PB CJISW MJISW HSPICE LEVEL 6 Model Setup Attributes 383 MOSFET Models DUT Setup Inputs Outputs Tranform Function Extractions large idvg vg vb id extract MOSDC_lev6_lin_large PHI VT GAMMA vd vs LGAMMA VBO LAMBDA UB NFS optimize Optimize PHI VT GAMMA LGAMMA VBO F1 F3 opt_NFS Optimize NFS narrow idvg _ extract MOSDC_lev6_lin_narrow NWM WD EL DELTA optimize Optimize NWM WDEL short idvg extract MOSDC_lev6_lin_short SCM XJ LD EL optimize Optimize SCM XJ LDEL RD RS short idvd vd vg id optimize Optimize KU MAL LAMBDA MBL vb vs cbd1i cjdarea vb vd cbd set_C Program initial zero bias CJ extract Optimize CJ MJ PB cbd2 vb vd cbd extract MOSCV_total_cap CJ MJ CISW MJISW PB cjdperimeter Measurement The measurement setups are identical to the UCB MOS LEVEL 2 and LEVEL 3 model example files However to obtain accurate GAMMA and LGAMMA parameters for ion implanted devices the measured data must clearly express the body effects Therefore the bulk voltage should be set broadly on the Large IdVg measurement The following sequence for DC measurements is recommended 1 Large IdVg 2 Narrow IdVg 3 Short IdVg 4 Short IdVd Extraction and Optimization All DC parameters are extracted and optimized with the DCExtraction macro Alternately extractions and optimizations can be performed
76. Name field Datei Bearbeiten Ansicht Favoriten Extras Quia GC BB Po suchen gt ordner Adresse D users default WaferPro frie Gr e Typ Ge ndert am Dateiordner 15 04 2011 11 18 9KB Microsoft Office Exc 15 04 2011 11 20 E MdmList_AdMOS_DC_Transist 9KB BCK Datei 15 04 2011 11 19 fih OffLine Simu AdMOS_DC_Tr 2 SKB Microsoft Office Exc 15 04 2011 11 20 lt amp u Objekt e 52 2 KB Eigener Computer Depending on your configuration of projects subsites dies and devices a number of sub directories are created which store the IC CAP mdm files Additionally there is a sub directory called as AdMOS where you can find the created measurement data files as well as a project settings file converted into a format to be opened by the MOS Modeling Packages These files are the measurement files created by the WaferPro measuring routines Importing Measured Data in the MOS Modeling Toolkit You can import the measurement files created by the WaferPro measuring routines into the MOS Modeling Toolkit Follow the steps below to import the measurement files 1 Open the DC_CV_Measurement module for the measurements created with WaferPro 2 In the Model window of the DC_CV_Measurement module choose File gt Open The Project Open dialog box is displayed 3 Browse to the location where the generated Measurement files are placed The following example uses the D users default WaferPro path and a lo
77. PDITSD Vds dependence of drain induced Vth 0 0 yi shift on Rout ALPHAO First impact ionization parameter 0 0 Am V ALPHA1 Length dependent substrate current 0 0 A V parameter BETAO First VDS dependent parameter of 0 1 V impact ionization current BETA1 Second VDS dependent parameter of i impact ionization current BETA2 Third VDS dependent parameter of 0 1 V impact ionization current VDSATIIO Nominal drain saturation voltage at 0 9 V threshold for impact ionization current Ti Temperature dependent parameter for 0 221 ig a MOSFET Bri impact ionization current Channel length dependent parameter at 5 threshold for impact ionization current E channel electric field for a impact ionization current SIIO First VGS dependent parameter for 0 5 1 V impact ionization current SII1 Second VGS dependent parameter for 0 1 1 V impact ionization current SII2 Third VGS dependent parameter for 0 impact ionization current SIID VDS dependent parameter of drain 0 1 V saturation voltage for impact ionization current Unified Current Saturation LAMBDA Velocity overshoot coefficient If not 2 0E 5 m s given or 40 velocity overshoot will be turned off VTL Thermal velocity If not given or lt 9 2 0E 5 m s source end thermal velocity limit will be turned off LC Velocity back scattering coefficient 0 0 m 5E 9m at room temperature Second velocity back scattering ere uced pisin Leskage moder Gate Induced Dra
78. PSP specific values You can use different area and perimeter values as well as Number of Squares for the Drain and Source regions of the transistors to be measured AS AD PS PD NRD NRS Further on you can set stress effect parameters SA SB SD See Stress Effect Modeling mosfet for details If you deactivate one of the Configuration menu points AS AD PS PD for example additional columns appear in the Device List table Now you can enter STI related parameters Refer to Shallow Trench Isolation mosfet for details on these parameters Well Proximity Effect Taken from P G Drennan M L Kniffin D R Locascio Implications of Proximity Effects for Analog Design to be found at http www ieee cicc org 06 8 6 pdf Highly scaled bulk CMOS technologies make use of high energy implants to form the deep retrograde well profiles needed for latch up protection and suppression of lateral punch 23 MOSFET Models through During the implant process atoms can scatter laterally from the edge of the photoresist mask and become embedded in the silicon surface in the vicinity of the well edge as illustrated in Figure 12 The result is a well surface concentration that changes with lateral distance from the mask edge over the range of 1um or more This lateral non uniformity in well doping causes the MOSFET threshold voltages and other electrical characteristics to vary with the distance of the transistor to the edge of the
79. Parameters lt gt Local Short Wide P i a Aanand m t te Default Optimizer Settings H E Algorithm Levenberg Marquardt Overview Customized Functions On this tab all generated Customized Functions are listed If the tree node is opened by clicking the sign you can see where a function is used Generated Customized Functions and their use on the Available Extractions tab 68 MOSFET Models en Diagrams 1 Fie Options Optimizer Plots Windows Help Cox f gb M 4 INDEX 31 00 Vgb 1 400 V cox m 205 0p aS a E N_Cox_VW200u0_L100u0_NF20 W 200 Ou L 100 0u NF 20 00 C_Oxidefcg_vg Cox_vq 250 lt r Add Plot C_Oxide cg_ vg wr 3 I w n gt 5 oO E gt 5 o 0 Vgb E 0 The functions can be modified on this tab too Default Extraction Flows The third tab Default Extraction Flows shows all Available Extractions Configure the Extraction Flow in the DC_CV_Extract window using the menu Extract gt Extraction Flow gt Default Extraction Flow Configuration of the Default Extraction Flow 69 men Diagrams 20 File Options Optimizer Plots Windows Help MOSFET Models Cox f gb M 33 INDEX 31 00 Vgb 1 500 V cox m 23 93p il Wooo DOL ODOM fz IAEI 200 nn Co cox m cox s E 12 m 50 E jH cox m cox s E 12 Oo Oo Cox f gb M 9 INDEX 31 00 gb 9
80. Pin D tobe entered into the appropriate field of the DC Transistor DUTs folder SMU SMU3 SMU4 Measurement of the Devices Once all DUTs are entered with their respective geometries switch matrix pin connection and measurement temperatures the actual measurement of devices can take place For this purpose you can use predefined measurement sets if you use the standard measurements called idvg and idvd If you ve designed a specific measurement for your purposes you can also define a Measurement Set for those measurements Select the Measurement subtree and Configuration gt Configure Measurement Set from the menu A window opens where you can define a name for the new measurement set and the measurement for which this set should be used Iy Configure Measurement Sets o a la H ti ct idvd_vbm in O O After selecting OK the newly defined set appears in the list of available measurement sets Now you can assign the measurement sets to your devices For this purpose select the Device List inside the tree view then select Configuration gt Configure Measurement Set from the menu A window opens for you to select the appropriate measurement set to use for each of your devices to be measured The following figure shows the Assign Measurement Sets to Devices window Select a device then select one of the available Measurement Sets to use for this device The list and the appropriate co
81. Qover is calculated with an analytical equation including the inversion charge HV 1 1 1 original no overlap charges capacitances are added to intrinsic ones overlap charges capacitances are added to intrinsic ones constant overlap capacitance bias dependent overlap capacitance model at drain side constant overlap capacitance bias dependent overlap capacitance model at source side no self heating self heating considered no substrate current calculated substrate current is calculated no gate current gate current is calculated no GIDL current GIDL current is calculated no STI leakage current STI leakage current is calculated no quasi static mode quasi static mode is invoked gate contact resistance not included gate contact resistance is included no substrate resistance network included substrate resistance network is invoked no 1 f noise calculated 1 f noise is calculated no thermal noise considered thermal noise is calculated RD T 0T RDVD VMAX NINVD TO RD RDVD VMAX NINVD TO RD RDVD VMAX NINVD T 0T RD RDVD T 060T VMAX NINVD TO and COTHRML O no induced gate and cross correlation noise and COTHRML 1 ind gate and cross corr noise are calculated previous calculated s is not used for next iteration previous calculated is used for iteration parameter variations for DFM support not considered parameter variations for DFM support is considered Back to MOSFET Models mosfet 232 MOSF
82. RBDB n12 n40 R abs factor_even_odd tmp_nf DDBC RSHB tmp_w Noise 1 R RBSB n32 n40 R abs factor_even_odd tmp_nf DSBC RSHB tmp_w Noise 1 R RBPD n12 n41 R abs 0 5 RSHB tmp_1 DGG tmp_w Noise 1 R RBPS n32 n41 R abs 0 5 RSHB tmp_1 DGG tmp_w Noise 1 L LBULK i4 n40 L LBULKO tmp_w 2 SS SS sSs Ideal mos transistor s cresecosocresse tmp_nqsmod Smpar NQSMOD 0 tmp_acnaqsmod Smpar ACNQSMOD 0 hsim2_mos MAIN n10 n21 n30 n41 Length Leff Width tmp_w tmp_nf Ad tmp_ad tmp_nf As tmp_as tmp_nf Pd tmp_pd tmp_nf Ps tmp_ps tmp_nf Nrd tmp_nrd tmp_nf Nrs tmp_nrs tmp_nf Nqsmod tmp_nqsmod Acnqsmod tmp_acngqsmod _M tmp_nf end hsim2_RF_Extract e Back to HiSIM2 Characterization mosfet 246 MOSFET Models HiSIM_HV Model The HiSIM_HV model topic is based on HiSIM_HV Version 2 01 released in April 2012 The user has the choice between versions 1 21 1 22 or 2 01 This part of the documentation is dedicated to the HISIM high voltage model As this model is based on the HISIM2 model the HV part only describes the differences between those models The high voltage model uses some additional parameters not present in HISIM2 Commonly following two types of structures for high voltage MOSFET s are used e Laterally diffused asymmetric structure usually called LDMOS e Symmetric structure referred to as HV structure The HiSIM_HV model is valid for both the structures It is an extensi
83. SOI technology is only lightly doped The bias dependency of this capacitance might be substantial in devices with large source drain diffusion areas Source Drain Bottom Capacitance Source bottom capacitance Source Area Drain Area The substrate to source bottom capacitance is modeled in BSIMSOI with piece wise expressions e va Chox if V e sfb i 1 f yV V al 5 6 S r r n C EE p T P 4 V I Cbox 4 ia C min V pV a elseif se S V fb A sth sfb Ss sth fb Cesb 7 7 1 C i a Fal 7 i min 1 A box min V V _ elseif lt V h Ss sth sfb Cin else 304 MOSFET Models Choy capacitance of the buried oxide minimum capacitance of the MOS capacitor in depletion no default calculated min A S source bottom area i P source to backgate voltage i fh source flatband voltage no default calculated r th threshold voltage of the source bottom MOS structure no default calculated The necessary physical parameters like flat band voltage as well as threshold voltage and minimal capacitance of the MOS structure can be easily extracted from measurements of appropriate MOS structures on test wafers Intrinsic Capacitance The intrinsic capacitance of the BSIMSOI model has been taken from BSIM3v3 Refer to Intrinsic Capacitance Modeling mosfet for further details Inversion Charge The inversion charges are supplied from source and drain electrodes
84. SWGEO 2 Global Level A global parameter set is used to model a range of geometries that are used in a given process Combined with instance parameters L and W a local model is derived from the global parameter set and processed at the local level for each geometry Local Level A local parameter set is used to simulate one discrete geometry At this level the temperature scaling is included Each parameter of the local parameter set can be derived from electrical measurements Consequently a local parameter set gives a complete description of one device for a specific geometry Most of the local parameters scale with geometry A whole range of geometries that are used in a MOS process can be described by a larger set of parameters that is the global parameter set Hierarchical Structure of the PSP Model PSP also enables you to use binning through an independent parameter set A local set is derived from the binning parameters similar to the use of the global model PSP Model Hierarchy as described by global and local levels Global Level Global Parameter Set Geometry Scaling L W Local Parameter Set SA SB Stress Model Stress Parameters Local Level Local Parameter Set Temperature Scaling Ta Model Equations i Current Charges Noise Local Model Terminal Voltages 253 MOSFET Models PSP Modeling Package The PSP Modeling Package uses Graphical User Interface GUI similar to BSIM3 and BSIM4
85. Sea aS ah hanna a a as ae pda IS eal Aine Pro ramming detalls mu Tandis a i ws rar a a Ea ge iad Soh i a aad Wier at ada Bib Ea isk Sahat Be Eana Wher amp Extraction of Parameters for the RF Models 5 204 suede dee Aiwa ee Sw we Be a de BSIMSavs Characlenizatlon porse Saeed at Bae ee OEE et ee ee es er ned Se BAS es What s New in the BSIM3v3 Modeling Package 0 c eee ee es Introduction to BSIM3 Model 4 sce Met sa Moe Sec Be ahs Wie Bre tas Qos Be Re ikea ed Be anew diese The Unified I V Model of BSIM3V3 exc eo hee e ek re te ee Sa Sh eis ine he Capacitance Model 224 2 it dciven at aye ae oe pee Oe eats oe ae hee ele ee a ee Me eg High Frequency Behavior 3 4 0 9 e409 alas aaa ee eee Gee a eae MS ese A es ee Ge Ge Temperature Dependence 0 cc es NOISE Mod l sa arla ani shoe endo ween ee ees te Ned iste taco ot be io ce aces hed set ed aes end ae eee a Beare a SPICE Model Parameters of the BSIM3v3 Model 0 0 cee es Test structures for Deep Submicron CMOS ProcesseS 2 0 0 cee a Extraction of Model Parameters 42 4 24 44 eese anasto a ewe de eae woe ele Bee Ae Binning of Model Parameters lt 0 wt aasie wy hie Sw ek hp Seah hae Bay Faw ae eae Fee ee a ae Importing older version BSIM3V3 FileS cas 6 44444 444 44 oe eee Re ew References and Copyright Information 0 oea a es BSIM4 Characterizatlon 44 4 0 4eO4vinc tie ote ot BSF a OR eee Rte Oe ERR A SES Ses What s new inside the BSIM4 Modeling P
86. Stop 2o Stop Ro No Pts 5 No Pts 5 The Measurement Conditions folder provides fields to enter conditions for S Parameter measurements Enter Start and Stop frequency choose the desired sweep Lin ear or Log arithmic and enter the number of Frequency Points to be measured during linear sweep or the number of Frequency Points Decade for logarithmic sweep Only the field ahead of the chosen sweep type Lin or Log is enabled allowing data to be entered Use the field Bias Conditions to enter sweep voltage Start Step and Stop values for drain and gate voltages during S Parameter measurements For extraction purposes VD VG steps should lead an integer value Note Be careful not to exceed the maximum DC Input voltage of the Network Analyzer used during measurements Related Topics RF Notes mosfet De embedding mosfet DUTs mosfet RF Options mosfet Back to RF Measurement mosfet RF Measurement Notes The RF measurement module also contains a Notes folder to take notes on the project It has the same look as the Notes folder of the DC CV measurement module see Notes mosfet Related Topics RF Measurement Conditions mosfet De embedding mosfet DUTs mosfet RF Options mosfet Back to RF Measurement mosfet RF Measurement Options Using this folder you can set the size of the plot window to fixed The functionality is the same as in the DC CV Measurement module see Options m
87. Subthreshold fitting at Vbs O subvt_opt1 5 Gds fitting at Vbs 0 normal_gds_opt1 for most devices or Jarge_gds_opt1 for the large device 6 Ids fitting for Vbs O ids_opti 7 Avalanche fitting for Vbs O isub_opt1 8 Repeat steps 2 through 7 9 Subthreshold fitting for all Vbs subvt_opt2 sca_opt The sca_opt transform controls the optimization sequence for maxiset extraction It can be found under the setup scaled_ext N e ea Linear region fitting at Vbs O sca_lin_opt1 Linear region fitting for all Vbs sca_lin_opt2 for the 2 k factor option or sca_lin_opt3 for the 1 k factor option Subthreshold fitting at Vbs 0 sca_subvt_opt1 Gds fitting at Vbs 0 sca_gds_opt1 Ids fitting at Vbs O sca_ids_opt1 Avalanche current fitting at Vbs O sca_isub_opt1 Subthreshold fitting for all Vbs sca_subvt_opt2 single_temp_opt The single_temp_opt transform controls the optimization sequence for the temperature dependent parameters at a single non nominal temperature It can be found under the setup single_temp_extract 360 MOSFET Models Initialize variables temp_par_init Linear fitting at Vbs O single_temp_lin_opt1 Linear fitting at all Vbs single_tep_lin_opt2 Subthreshold fitting at Vbs O single_temp_subvt_opt1 Ids fitting at Vbs O single_temp_ids_opt1 Avalanche current fitting at Vbs 0 single_temp_isub_opt1 Oy Ore optimize_tempe
88. THO E K1 K2 NDEP E UA UB UD EU E VOFF NFACTOR E uc T VOFF NFACTOR y O VTHO K1 K2 amp U0 UA UB EU UC Sy 0 All Idvg F 3b Capacitance Fringing and Overlap ak Length Scaled Yth low Vd 3b Capacitance Yth Shift in Overlap ak Short Rds Subthreshold Behavior gt Extraction will start with Parameters of MPS O VTHO Ki K2 lt gt global O02 07 mps Result is stored in File Messages X Diagrams _ Tuners File lt gt global 02 08 mps Project bsim4_for_experts Project directory g fusers default Status Getting Started In the Main window open model_files mosfet bsim4 BSIM4_DC_CV_Extract mdl from your IC CAP example folder and edit it IC CAP Main window 73 MOSFET Models E interactivePlot 36 Id f Vg Vb low Vd Devices Parameter Tuner ee a NFS 1 000 A m 48108 F200 ty UA Bare sO uc uB 1 000p 255477 0m9 Moo DELTA 1 0001 10 10m 1 000MEG Transistor_A We 5 000u L 5 000u NF 1 000 dvg m s E 6 4 d2id o Extraction Step Direct Execution Funcor T UQUAUB EUUC Evecute Save Stating vaes v gt gt Open the DUT Large found under DC Transistor and select the setup idvg Adding a New Plot Change to the Plots tab and create a new plot by copying the existing plot gm Rename the plot and change the Y Data 0 from the first derivative to t
89. Test Plan Run in the Navigation view and click Run icon gt The Test Plan is simulated and results are displayed as shown in below screenshot Yay snzewe 09 31 50 gt Exo 09 31 50 gt Sequence finished 09 31 50 gt Prober moved to Home position 09 31 50 gt Prober is in No Contact Separate state 09 31 50 gt User abort Test Plan Sequence 09 31 50 gt 1 113 413 315 811 1 Simulated Device N10 0 12 Routine MOS_CV MeasCond YDD18 Comment 09 31 43 gt Fe 1 1 3 413 3 4 8 1 1 Simulated Device N10 0 24 Routine MOS_CV MeasCond YDD18 Comment 09 31 37 gt SE 1 113 413 313 811 1 Simulated Device N10 0 5 Routine MOS_CV MeasCond YDD18 Comment 09 31 29 gt f 1 113 413 312 811 1 Simulated Device N10 1 Routine MOS_CY MeasCond YOO 13 Comment Comment 09 31 23 gt 48 1 113 413 311 811 1 Simulated Device N 10 10 Routine MOS_CV MeasCond VOO18 09 31 16 gt Moved to Die X Y 4 Block BB 1_SVT18 Subsite MOSO3 WaferPro creates a directory using the storage path and name provided in Configuration settings In this example the Storage Path is D users default WaferPro and the lot name is frie After you execute the test plan WaferPro creates a sub directory under D users default WaferPro called as frie The frie sub directory stores the various csv files log files and an additional directory called as FRIE_WAF_1 The FRIE_WAF_1 is the wafer name provided in the Configuration gt Bench gt Wafer
90. The extraction routines are based on BSIMSOI device equations to ensure that the extracted model parameters represent as good as possible the original physical meaning Therefore no or only a minimum of optimization is needed to get a good fit between measured and simulated device behavior This section provides information on the following topics e Introduction to the BSIMSOI Model mosfet IV Characterization mosfet Binning of Floating and Fixed Devices mosfet CV Characterization mosfet High Frequency Model mosfet Test Structures for SOI MOSFET mosfet SPICE Model Parameters mosfet How to get the BSIMSOI manual from University of Berkeley California University of California at Berkeley provides an easy way to get a free copy of the BSIMSOI manual and the BSIMSOI source code from their world wide web home page at http www device eecs berkeley edu bsimsoi Other useful internet addresses e Advanced Modeling Solutions at http www admos de e Agilent EEsof homepage at http eesof tm agilent com Copyright Information BSIMSOIT is developed by the Device Research Group of the Department of Electrical Engineering and Computer Science University of California Berkeley and copyrighted by the University of California at Berkeley References BSIM3SOI University of California at Berkeley August 1997 BSIMSOI3p2 University of California at Berkeley February 2004 BSIM3v3 University of California at Ber
91. Tne JUNCAP Model resa Ste hace ec aaa ae a Se RO we a aa a a ee a New Features in AGMOS Modeling Toolskits for ICCAP 2012 10 ce es UCB MOS Level 2 and 3 Characterization 0 0 aoaaa es Introduction to UCB MOS Level 2 and 3 Characterization 0 a a a UCB MOSFET Model Simulators and Model Parameters 2 0000 eee eee eee ee ees VESEINSUMENTS eae a nasa ah E vase a derbies sa av ete aoe ng Wit fa ase a Se ar even moe Ri Ea Measuring and Extracting ties eh de cert ki lay he he id Bhat pha a Se Ge kk tae Moss ey a ava So Bal Oy a a Extractiom Algorithms arisa Aiea ieee are ue ede ie Sei en wae Ae eet ak a wt The ue E HSPICE LEVEL 6 MOSFET Model lt p tirahacdbs teat A at oe ih hae A Ee oa vale RS af Po hae MOSFET Models Supported Model Versions The following table lists the model versions supported by the MOS Modeling Toolkits for Supported models and simulators Model Circuits ADS 2011_01 Verilog A HSpice F2011 09 MMSIM 11 1 Eldo 2011 1 BSIM3 3 3 2 4 3 3 3 3 2 4 3 3 3 3 2 4 BSIM4 4 7 4 6 5 _ 4 7 4 7 4 7 BSIMSOI4 4 4 0 4 4 4 4 4 4 4 4 HiSIM 2 2 5 1 2 4 1 2 5 1 2 5 1 2 5 1 2 5 1 HiSIM HV 1 2 1 1 2 1 2 1 1 2 1 2 00 1 2 2 1 2 1 PSP 103 1 1 103 1 1 i 103 1 1 103 1 1 103 1 1 MOSFET Models Using the MOS Modeling Packages This section provides information on the following topics Introduction to MOS Modeling Packages mosfet Data Structure in MOS Modeling Packages mosfet Getting Started with MO
92. University of California 188 MOSFET Models What s new inside the BSIM4 Modeling Package This section lists the enhancements and changes made to the Modeling Package New features in the BSIM4 Modeling Package Rev IC CAP 2012 01 Jan 2012 Note The supported model is now BSIM7 released by UCB in April 2011 1 General There are newly modeled effects included into this release of BSIM4 GIDLMOD 1 is introduced to decouple Vd from Vg through new parameters RGIDL KGIDL and FGIDL same for GISL Existing DIBL Rout model in BSIMSOT is proposed to enhance with additional term DVTP5 to better capture Vdseffect in long channel device Improved formulation to capture temperature dependence of Sub threshold Leakage Current New switch mtrlCompatMod introduced to make mtriMod 0 compatibile with mtriMod 1 C V Discrepancy also fixed e Enhanced Thermal Noise Model for BSIM4 2 Bug Fixes e Source and Drain diode current shows unphysical and high values for Aseff Pseff Adeff Pdeff 0 e Redundant toxe term appearing in the Igc formulation Back to BSIM4 Characterization mosfet 189 MOSFET Models Basic Effects Modeled in BSIM4 Short and narrow channel effects on threshold voltage Non uniform doping effects Mobility reduction due to vertical field Bulk charge effect Carrier velocity saturation Drain induced barrier lowering DIBL Channel length modulation CLM Substrate current induced body effect
93. V arrays forward and reverse in the area locos gate and analysis DUTS are updated with the new parameters 367 MOSFET Models opt_all_rev_iv This macro controls the optimization of the generation current parameters with respect to the measured reverse I V data in the area locos and gate DUTs At the end of the extractions the simulated I V arrays forward and reverse in the area locos gate and analysis DUTS are updated with the new parameters simulate_all_curves This macro allows all the curves to be resimulated set_new_TR This macro allows the model parameters to be recalculated for a new reference temperature read_data_from_directory Reads data previously stored in a subdirectory under the current working directory write_data_to_directory Writes the data to a subdirectory under the current working directory General Extraction Methodology The JUNCAP model extraction methodology assumes that the parasitic source and drain regions consist of three sub regions e The area of the source drain o On an IC layout this is the area of the source drain active region This area is labeled AB and has dimensions of m2 e The LOCOS edge o On an IC layout this is the perimeter of the source drain region that is shared with the LOCOS edge This perimeter is labeled LS and has dimensions of m e The gate edge o On an IC layout this is the perimeter of the source drain region that is shared with the gate polysilicon edge This p
94. VOFF 0 08 VOFFL 0 MINV 0 NFACTOR 1 CIT 0 CDSC 2 4e 4 CDSCB 0 CDSCD 0 PCLM 1 3 PDIBLC1 0 39 PDIBLC2 0 0086 PDIBLCB 0 DROUT 0 56 PSCBE1 4 24e8 PSCBE2 1te 5 PVAG 0 DELTA 0 01 FPROUT 0 PDITS im PDITSL 0 PDITSD 0 RDS 200 RDSWMIN 0 RDW 100 RDWMIN 0 RSW 100 RSWMIN 0 PRWG 1 PRWB 0 R 1 LINT 0 WINT 0 DWG 0 DWB 0 L 0 LN 1 WW 0 WWN 1 WWL 0 0 N 1 LW 0 LWN 1 LWL 0 C 0 LWC 0 LWLC 0 N bd Nn WLC 0 WWC 0 WWLC 0 BETAO 15 AGIDL 0 BGIDL 2 3e9 AIGBACC 0 43 BIGBACC 0 054 CIGBACC 0 075 BIGBINV 0 03 CIGBINV 0 006 EIGBINV 1 1 BIGC 0 054 CIGC 0 075 AIGSD 0 43 DLCIG 0 NIGC 1 POXEDGE 1 TOXREF 3e 9 XPART 0 CGSO 0 CGS 0 CGD 0 CKAPPAS 0 6 CLE 1e 7 CLE 0 6 DLC 0 OF F 1 VOFFCV 0 ACDE 1 XRCRG2 1 RBPB 50 RBPD 50 RBSB 50 GBMIN te 12 RBPSO 50 RBPSNF Q RBPDO 50 RBPDL 0 RBPBXO 100 RBPBXL 0 RBPBXW 0 RBPBYL 0 RBPBYW 0 RBPBYNF 0 RBDBXO 100 RBDBYO 100 RBSDBXL 0 RBSDBYL 0 RBSDBYW 0 RBSDBYNF 0 OIC 8 75 EM 4 1e7 AF 1 TNOI 1 TNOIA Leo TNOIB 3 5 DMDG 0 DMCGT 0 DWJ 0 GCON XL 0 XW 0 XJBVS 1 BVS 10 JSS 1e 4 CJS 5e 4 MJS 0 5
95. View Device Type View Subsite Mod_A i Device Type AGMOS_DC Transistor a P Sai X Dx 2V Device Name AdMOS Project Polarity SizeCategory STI WPE 1 _W5u0_L0U13_SA Ibsim4_for_experts N Short SA ref 2 W0u18_L5u0_SA bsim4_for_experts N Narrow SA2 WPE ref 3 W0u18_L5u0_SA bsin4_for_experts N Narrow SA ref 4 WSu0_LOU13_SA bsim4_for_experts N Short SA2 WPE ref 40 MOSFET Models Device Type View in WaferPro Subsite View Device Type View am f Ld Device Type AGMOS_DC_Transistor v lq X ok Fas Subsite Device Name AGMOS Project Polarity SizeCategory si 1 iMod A WSu0_L0u13_SA bsim4_for_experts N Short SAref 2 Mod A Wou18_L5u0_SA bsim4_for_experts N Narrow SA2 3 Mod_A W0u18_L5u0_SA bsim4_for_experts N Narrow SAref 4 Mod_A W5u0_L0u13_SA bsim4_for_experts N Short SA2 You are ready to use WaferPro for the measurement of your devices Enter a path for WaferPro to store the output files and a Lot name if not already entered Choose Configuration in the Navigation View and enter the desired path and lot name and other required information WaferPro stores the output files produced during measurement of dies on wafers in the provided Storage Path Executing the Modified Test Plan To make yourself familiar with the procedure prior to measuring an actual project WaferPro allows you to create files in a test mode To create files in a test mode go to the
96. W 5u0_L5u0_ bsim4_for_ex N Large SA ref 7 8 31 32 5 5 1 1 5 11 5 11 0 O 1 Mod_T1 W 5u0_L5u0_ bsim4_for_ex N Large SA ref 9 10 31 32 5 5 1 1 5 11 5 11 0 0 1 Mod_T1 V 0u18_L5u0 bsim4_for_ex N Narrow SA ref 11 12 31 32 0 18 5 1 10 18 Jan 36 0 16 Jan 36 0 0 1 Mod_T1 WOu18_L5u0 bsim4_for_ex N Narrow SA ref 13 14 31 32 0 18 5 1 10 18 Jan 36 0 18 Jan 36 0 D0 1 Mod_T1 WOu18 L5u0 bsim4_for_ex N Narrow SA ref VWPE ref 15 16 31 32 0 16 5 1 10 18 Jan 36 0 18 Jan 36 0 D0 1 Mod_T1 V Ou165_L5u0 bsim4_for_ex N Narrow SA ref 17 18 31 32 0 16 5 1 10 16 Jan 36 0 16 Jan 36 0 D0 1 Mod_T1 V Ou15_L5u0 bsim4_for_ex N Narrow SA ref 19 20 31 32 0 16 5 1 10 18 Jan 36 0 18 Jan 36 0 D0 1 Mod _T1 W5u0_LOu13 bsim4_for_ex N Short SA ref 21 22 31 32 0 13 1 1 5 11 5 11 0 D0 1 Mod_T1 W5u0_LOu13 bsim4_for_ex N Short SA ref 23 24 31 32 510 13 1 1 5 11 5 11 0 D0 1 Mod_T1 W5u0_LOu13 bsim4_for_ex N Short SA ref 25 26 31 32 10 13 1 1 5 11 5 11 0 D0 1 Mod_T1 V 5u0_LOu13 bsim4_for_ex N Short SA ref VYVPE ref 27 28 31 32 5013 1 1 5 11 5 11 0 D0 1 Mod_T1 W 5u0_LOu13 bsim4_for_ex N short SA ref 29 30 31 32 60 13 1 1 5 11 5 11 0 D0 1 Mod_T2 WOu18_LOu1 bsim4_for_ex N small SA ref YVPE ref 1 2 31 32 0 18 0 13 1 10 18 Jan 36 0 18 Jan 36 0 D0 1 Mod_T2 V 5u0_LOu16 bsim4_for_ex N L Scale SA ref WPE ref 3 4 31 32 50 16 1 1 9 11 5 11 0 D0 1 Mod_T2 W5u0 LOu4_ bsim4_for_ex N L Scale SA ref VVPE ref 5 6 31 32 50 4 1 1 5 11 5 11 0 D0 1 M
97. W Scale LW Scale Capacitance or Diode BD Area BD Perim 92 MOSFET Models BD Perim Gate BS Area BS Perim BS Perim Gate Capacitance Oxide Overlapi1 GDS Overlapx GDS Overlap1 GDSB Overlapx GDSB Intrinsic Example Overlap F_DataSourceDefault_Func 0 Overlap GDSB Overlap1 GDSB Overlap2 GDSB Overlap3 GDSB Overlap4 GDSB Overlap5 GDSB Overlap6 GDSB F_DataSourceDefault_Func 1 Overlap GDS Overlapi GDS Overlap2 GDS Overlap3 GDS Overlap4 GDS Overlap5 GDS Overlap6 GDS Example Transistors F_DataSourceDefault_Func 0 Large Narrow Short Small L Scale W Scale LW Scale Additional Available content of F_DataSourceDefault_STI list Empty disables this section for default selection all DUTs will be selected by default Examples F_DataSourceDefault_STI O F_DataSourceDefault_STI O SA ref F_DataSourceDefault_STI O SA ref SA 1 SA 3 Execution Specials failcode This will be used for error messages see 1 3 Need to be empty if no error occurred Plots _x1 Plot _x2 Plot _y1 Plot _ y2 have to be used if they are set by the RegionPELcode Error Handling The variable failcode is checked after returning from executing a transform If it is not empty the transform will be called again with the parameter error This allows for setting the message variable msg1 msg6 If the variable MESSAGE is activated on the Options page those messages are di
98. XJ LD and RS are extracted during the extraction process Accurate results depend on the sequence of the extraction Follow this DC extraction sequence e Extract the classical parameters from the large device Because length and width effects are not critical for the device used in this step the classical parameters can be extracted very accurately These parameters are used for the remainder of the extractions Extract parameters from a narrow device in which length effects are not important but the width effect and width parameters are Extract length parameters using a short channel device and the classical parameter data acquired in the first extraction RS and RD parameters which predominate in this device are also extracted in this step All of the parameters extracted are used to calculate the saturation parameters for the short channel device The short channel device is used for this procedure because of the predominance of the saturation parameters Do all of the measurements followed by all of the extractions and finally the simulations Extraction usually provides a reasonable fit to the measured data but you can optimize data to attain an increased level of accuracy Execute the optimization after extracting the DC parameters for each setup To perform DC parameter measurements 1 Choose File gt Open gt Examples Select lt filename gt mdl and choose OK Open the model window When the model window appears y
99. amp amp amp amp There are some constraints to the Copy and Paste function Factory settings default extractions cannot be deleted by users This is to protect a working extraction environment from accidentally being destroyed The following table gives an overview over the actions a user is able to perform Action Factory defined Customized Factory defined Customized Groups Groups Functions Functions Copy X X X X Paste X X Delete X X Rename X X Modify X X You are able to copy a factory defined default function but you can only paste into a customized group It cannot be pasted into a factory defined default group A default function cannot be deleted inside the default group it belongs to but in a customized group You cannot accidentally delete a default function or group because the right mouse menu prevents actions not allowed Operations not permitted are not available in the menu You can add a customized function to a default group by selecting any default function using the right mouse menu Generate Customized Function The use of customized groups or functions has been described earlier in Using a new function in a project Modifying Customized Functions Some of the features are only available in Expert Mode Enter Expert Mode through the menu Options gt Expert Mode Example Adding a plot Use the IC CAP Main Window to edit the Model File go to the C_Oxide setup to select
100. and drain junction when the gate is at flat band voltage These different parts of the capacitance of a MOS transistors are shown in the following figure The following three sections explain each type of capacitance and its implementation in the BSIM3v3 model Different Parts of the Capacitance of a MOS Transistor La Tm T ies a Ceno Region of intrinsic T capacitance C Junc Junction Capacitance The source drain bulk junction capacitance can be divided into three components as shown in the following figure The calculation is shown for the drain bulk junction Capacitance The source bulk capacitance is calculated in the same way with the same model parameters The overall junction capacitance Cidb is given by idbs 7 EDO v Watt jabs eat les if PS lt Weft where Carga is the bottom area capacitance Coy is the sidewall or peripheral capacitance along the three sides of the junction s field oxide Cswg is the sidewall or peripheral capacitance along the gate oxide side of the junction Dimensions of Drain Source Region and Different Capacitance Parts Bottom area capacitance CAREA CAREA AD Cing 140 MOSFET Models where AD area of bottom side of pn junction given as SPICE model parameter Ciba Capacitance per unit area of the drain bulk junction Ciba is calculated according to the following equation and is shown in the following figure For Vos lt 0 ul wnnncantannnn m aJ
101. and the measuring instruments Make sure the device is oriented properly with the right ports connected to the right terminals If none of these resolves the problem the device may be defective For example if all the curves are superimposed the gate may be shorted 5 To save the measured data for later comparison with data predicted by the extracted model choose File gt Save As and a filename with the suffix set for example dc_test set Then click OK 6 The following figure illustrates a typical id_vd plot for a PMOS device Example Measured id_vd Data for a PMOS Device slovoed os I i e tu vie 7 Close the plots Calibrating the Network Analyzer It is important to calibrate the network analyzer before you perform any S parameter measurements Good calibration of the network analyzer is critical to a good measurement and model generation The Agilent Root MOS measurement procedures require two network analyzer calibrations a swept broadband cal and a CW cal The broadband cal is used for the S parameter preverification and parasitics measurements The CW cal is used for the main data acquisition For a system with an Agilent 8510 network analyzer this procedure uses the frequency list cal mode for both the broadband and CW calibrations The two calibrations can be done with only one set of standards measurements by making the CW cal a subset of the broadband cal For a system with an Agilent 8753 or 8720 networ
102. appended This is a place holder used during multiple extractions optimizations for this parameter not a real parameter name Extraction Flow of the PSP Toolkit 255 Extraction Group Global Capacitance and Junction parameters Local Long Wide Local Long Width dependence PSP Scale Parameters Long Width dependence Local Short Wide Local Length Dependence Wide Wim 240n 150n 90n 65n Device Configuration i Short Wide Length Dependence Wide Long Wide 45n 60 90n 150n 240n Long Width Dependence Length Width Dependence Short Width Dependence Wim 45n 60n 90n 150n 240n 45n 60n 90n 150n 240n MOSFET Models Local Level Parameters NEFF BETN CS MUE DPHIB VP XCOR THEMU THESAT GCO GC2 GC3 Al A2 etc VFB NP NEFF BETN DPHIB MUE IINV IGOV etc THESATG THESATB RS RSB XCOR ALP ALP1i ALP2 Snax ETC Global Level Parameters VFB TOX TOXOV NP NOV IDSAT VBR etc MUEO MUEW CSO CSW 256 Notes Extraction of Capacitance parameters from the Long Wide device Local parameters fixed for all devices among others VP THEMU GCO GC2 A2 A3 Local parameter extraction of all long devices Global extraction using all the long devices to extract width dependent parameters which do not have a length dependency Local extraction us
103. are not satisfied with a predefined function flow you are able to change the flow by re arranging the functions using the up or down icons or you can add another function to the flow Changed extractions will be marked with an asterisk behind the name of the extraction Gi Extractions are meaningful only if the setup used for measurement will be used for the extraction too If the project will be closed and re opened again the default extraction flow will be loaded You can select the dependency from L W and P L W for some of the parameters using the Extract gt Edit Global Binning Parameter menu A window opens up where you can check parameters and dependencies to acknowledge during the global binning process Predefined extractions or optimizations for global binning parameters are not available You can configure optimizations for global binning parameters in two ways e Generate a plot optimizer and invoke it in the group Finetuning inside the extraction flow e Manually add global binning parameters to predefined optimizers This change is 53 MOSFET Models saved as a user defined customization You can set initial conditions for binning using the Extract gt Extraction Flow gt Initial 37S Conditions menu or clicking the appropriate icon 1 from the icon bar A window opens enabling you to configure full parameter sets for each device from other devices and add single parameters to this global binning extractio
104. at the same temperature are displayed in a normalized representation IDSATnorm Idsat L W see right part of the figure above the values appear in a sorted way They are shown from the transistors having the highest gate width values on top of the lower gate width transistors The transistors having the smallest gate width values are shown at the lowest display position in the diagram If the temperature measurements of the transistors are normalized as well the measured data is again sorted The following diagram shows IDSAT and IDSATnorm for devices with temperature measurements Each color represents one temperature and each value of the x axis represents one device 138 MOSFET Models idsat normalized Idsat LAN M 1 Temp 298 0 X 1 000 Idsat_nomm_T 232 5u E 6 ldsat_norm_T 0 2 4 3 amp of DUT E 0 of DUT E 0 Left part IDSAT f temp device right part IDSATnorm f temp device Threshold voltage Similar normalized data representations are available for the threshold voltage Vth of measured devices see the following figure Vth is determined for each device at Vb 0 and low Vd The following diagram shows Vth as a function of L W left part and temperature right part for those devices Vth is determined using the reference current method Vin VGUpo with W Ibo IDref T I 100nA using 27 Vth Vb 0 Yd min M 14 Temp 233 0 X 6 000 Vth_T 506 8m Vth Vb 0 Vd min M 33 Wde
105. b PS no_inner_source 2c no_outer_source 2 b c Gate A large number of poly Si parallel switched LDD S D MOS transistors see shape BSIM3 BSIM4 PERMOD 1 W WNF 5 AD no_drain a b AS no_source a b PD no_drain 2 a b PS no_source 2 a b BSIM4 PERMOD 0 PD no_inner drain 2a no_outer_drain 2 a b PS no_inner_source 2c no_outer_source 2 b c Test Structures for Intrinsic Capacitance Measurements Applied bias n type Comment OPEN capacitance values an additional OPEN calibration structure on chip is necessary to compensate the capacitance of pads and lines to the transistor Testchips You will find an example for a test chip design which meets most of the requirements of the extraction of BSIM3v3 model parameter in the JESSI 169 MOSFET Models Report AC 41 94 3 Description of parametrized European Mini Test Chip Please check also the test chip design of the Fabless Semiconductor Association in the U S http www fsa org S parameter Test Structures and De embedding procedures Test Structures Performing S parameter measurements with MOS devices on a wafer requires properly designed test structures that meet certain requirements e The test devices must drive enough current for correct measurement results e They should fulfill the specifications for high frequency probes e Additional structures should be available for the mea
106. be selected by default Transistor Large Short Narrow Small L Scale W Scale LW Scale Capacitance or Diode 96 MOSFET Models BD Area BD Perim BD Perim Gate BS Area BS Perim BS Perim Gate Capacitance Oxide Overlap1 GDS Overlapx GDS Overlapi1 GDSB Overlapx GDSB Intrinsic Example Overlap F_DataSourceDefault_Func 0 Overlap GDSB Overlap1 GDSB Overlap2 GDSB Overlap3 GDSB Overlap4 GDSB Overlap5 GDSB Overlap6 GDSB F_DataSourceDefault_Func 1 Overlap GDS Overlapi GDS Overlap2 GDS Overlap3 GDS Overlap4 GDS Overlap5 GDS Overlap6 GDS Example Transistors F_DataSourceDefault_Func 0O Large Narrow Short Small L Scale W Scale LW Scale Additional Available content of F_DataSourceDefault_STI list Empty disables this selection for default selection all DUTs will be selected by default Examples F_DataSourceDefault_STI O F_DataSourceDefault_STI O SA ref F_DataSourceDefault_STI O SA ref SA 1 SA 3 2 2 Execution Specials failcode This will be used for error messages see 1 3 Need to be empty if no error occurred Plots _x1 Plot _x2 Plot _y1 Plot _ y2 have to be used if they are set by the RegionPELcode 2 3 Error The variable failcode is checked after returning from executing a transform If it is not empty the transform will be called again with the parameter error This allows for setting the message variable msg1 m
107. becomes shorter the lateral non uniform doping will cause the threshold voltage to increase strongly because the average doping concentration in the channel becomes higher This part of the threshold voltage is modeled with the parameter NI and is represented by AVin 2 as a part of the overall threshold voltage Lateral Doping Equation T t NE _ AV n 2 iz ez 4 oxm e i where NI 2L Nas Na Na The following figure shows the influence of the non uniform lateral doping on the threshold voltage as a function of gate length Threshold Voltage as a Function of Gate Length Due to Lateral Non Uniform Doping 123 MOSFET Models Theoretical Increase of threshold Voltage with shorter channel lengths due to lateral non uniform doping CE 3 V 8 8 7 0 8 Eo P VTH L m Q e oenoon ao a 8 D cale VTH Lis rn Aer T Ser See e8 Ldes CLOG You can distinguish between the theoretical trace following Lateral Doping Equation and the real world ones with the short channel effect described in the next section Short Channel Effect The threshold voltage of a long channel device is independent of the channel length and the drain voltage as it is shown in the equation of the ideal threshold voltage The decreasing of device dimensions causes the so called short channel effects threshold voltage roll off and degradation of the subthreshold slope that in turn increases the off current leve
108. channel effects o Narrow channel effects e Mobility o Mobility reduction due to vertical fields e Carrier Velocity Saturation e Drain Current o Bulk charge effect o Subthreshold conduction o Source drain parasitic resistance e Bulk Current e Output Resistance o Drain induced barrier lowering DIBL o Channel length modulation CLM o Substrate current induced body effect SCBE e Short channel capacitance model e Temperature dependence of the device behavior For a detailed description of these features refer to the BSIM3 manual from Berkeley University You can order this manual from Berkeley or you can get it over the Internet See References mosfet for details The BSIM3v3 Modeling Package provides a complete extraction strategy for the model parameters of the BSIM3v3 3 0 model The extraction routines are based on the BSIM3v3 3 0 device equations to ensure that the extracted model parameters represent as good as possible the original physical meaning Therefore no or only a minimum of optimization is needed to get a good fit between measured and simulated device behavior The routines of this release refer to version 3 3 0 of the BSIM3 model that was released by University of California at Berkeley in July 2005 Versions of the BSIMS3 Model University of California at Berkeley released four versions of its BSIM3 model The first three versions have differences in some model parameters and the model parameter sets are not compati
109. curves usually two general principles are applied the optimization of the simulated device behavior or the parameter extraction based on the device equation The basis of the optimization process is the simulation of a device with exactly the same inputs voltages currents that are used to measure the device The error between simulated and measured data is the cost function for the optimization algorithms which changes certain model parameters of the device re simulates it and checks whether the error has increased or decreased The advantage of this procedure is that the fitting between the measured curves and the simulated ones can be very good because the optimizer always tries to minimize this difference However in order to achieve this very good fitting the optimization algorithm can give the model parameter physically unreasonable values Another disadvantage is that many optimization algorithms are not able to find the global minimum of the failure function which is the difference between measurement and simulation and the success of the optimization depends on the start values of the model parameters The last difficulty that can arise by using pure optimization algorithms for the model parameter determination is that the boundaries for the optimization process must be set very carefully This means that the user of the optimization algorithm must have good knowledge about the device model and where the different model parameters have
110. defined extraction function in the GUI Extraction Flow Extraction PSP Scale Capacitance Cag Function Flow m Avaiable Functions TOD LVARO LVARL DLQ TOXO LYARO LVARL DLO VFBO VFBL VFB VFBLW VFBO VFBL VFB VFBLW VFBO VFBL VFBW VFBLW NPO NPL NPO NPL NPO NPL WARO WVARW DWO WVARO WVARW DWO _02 N_CoverGDSB_w hw_02 N_CoverGDSB_W S ale Capa lance aA Implementation of a user defined extraction routine into a model file To implement the new extraction groups into a specific model file execute the following steps e Go to the main window and open the GUI by double clicking on the model file e Open the menu item Extract and execute Generate Customer Extractions Confirm the following window with OK e The menu is not available if a project is opened e Implementation of the new extraction groups PSP_DC_CV_Extract 30 a ene SD beled owen at a33 AlelAlaleloie el Extraction Flow Functen Flow TML rva Options irva Bouancharies n a Notes information rva Faire Log The new extraction groups are now implemented in the extraction flow and ready for use 88 MOSFET Models e Global main groups extended by user defined extraction steps Add Extraction Add Extraction PSP Scale Parameters e c C C Binning Extraction Groups Devices Extraction Groups Devices PSP Scale
111. device in dataset Default number of visible setups Default number of visible macros Default number of visible variables Default number of visible parameters Maximum bias voltage Number of devices in dataset Present device being measured extracted Scanner pin connected to common device gate Scanner pin connected to common device source Scanner pin connected to common device bulk Address of scanner as used in SWM_init statement Name of scanner as used in SWM_init statement Index number for the DUT considered to be large Low bound for drain current optimization High bound for drain current optimization Choice of 1 or 2 K factor model Low bound for substrate current optimization High bound for substrate current optimization Vgs step size for linear region curves Vbs bias used for saturation and subthreshold sweeps Vbs bias used for saturation and subthreshold sweeps Vbs bias used for saturation and subthreshold sweeps First saturation region curve in idvg1 is measured for VGS TYPE VTH SAT_DELVGS Vgs value for saturation region curves Vgs value for saturation region curves Vgs value for saturation region curves Vds step size for saturation region curves For the subthreshold curves Vgs is varied from TYPE VTH SVT_DELVGS1 to TYPE VTH SVT_DELVGS2 Vgs step size for subthreshold region curves Vds value for substrate current curves Vds value for substrate current curves Vds value for substrate current curves Vgs
112. documented later 1 In the DUT Setup panel select the S parameter setup you need for example sparm_Ov 2 Select the Instrument Options tab 3 Set the Agilent 4142 instrument state the same as for the DC measurements 4 Set the Agilent 8510 instrument state according to the actual hardware configuration the calibration used and the device to be measured following these guidelines 5 Set Use User Sweep to No to use the instrument s standard internal sweep This is necessary for the network analyzer s calibration to be switched on 6 Hold Time is the time in seconds before the instrument starts a sweep to allow for DC settling Generally no hold time is required 7 Delay Time is the delay in seconds the instrument waits before setting each frequency in user sweep mode The default is 100 0m but the value set will not affect an internal sweep 8 Set Port 1 Atten and Port 2 Atten to the same levels in dB that you set in the network analyzer calibration While the default is 0 dB you may need to add attenuation for measurements of amplifiers or high power devices 9 Source Power is the RF synthesizer output power Set it to the same value in dB that you set in the network analyzer calibration 10 Power Slope is used only if you use power slope in the network analyzer calibration if so set the corresponding value here This is useful to view the response of a device with power dropoff at higher frequencies The units for power sl
113. example shows the measurement of NMOS devices Note All voltages are to be entered for NMOS devices If you would like to measure a PMOS device enter the voltages in the polarity for NMOS devices On selecting the PMOS button the polarity of the voltages will be changed internally so that the correct voltage will be applied to the DUT Compliance DC Compliance settings for the source measurement units SMUs are located at the top of the form You can set different compliance values for each SMU but the values set are valid for all measurements Power Compliance You can specify whether to use a Power Compliance setting for your device There is a Drop Down list to select the method for Pwer Compliance calculation You can select between Constant Power Compliance PC const Scaled vs W PCdut M W PCref using a block multiplier M and device width W together with a reference power compliance value PCref in W m e Scaled vs W Ldrift PCdut M W Ldrift PCref using the drift length PCref in W m A maximum allowable power dissipation per drift region area is assumed e Scaled vs W L PCdut M W L PCref using the channel length PCref in W m2 A maximum allowable power dissipation per channel region area is assumed 18 MOSFET Models e Scaled vs W L PCdut M W L PCref using the channel length PCref in W Simple W L scaling assumed To the right of the drop down menu you will find a field to enter the PC and P
114. extracted are valid only for a specific transistor geometry which means you must have RF parameters for each of your possible device geometries This requires measurement and library creation for every transistor geometry in your design Design engineers often need to have scalable transistors for easy design processes Therefore extensions are made to use a scalable BSIM3 model Those are described in the following section Fully Scalable Subcircuit Model for BSIM3v3 RF Transistors The following figure shows a cross section of a multifinger RF MOSFET with the distances marked from the bulk connection point to the physical transistor connections Distances between the bulk connection and the terminals of a multifinger RF transistor 150 MOSFET Models The distances are e DDCB distance between bulk connection point and drain e DDCS distance between bulk connection point and source e DGG distance between gate stripes Additionally the sheet resistance of the bulk connection RSHB is needed Implementations according to MOS Transistor Modeling for RF IC Design BSIM3v3 References mosfet 8 and our own findings to model a scalable substrate resistance behavior are leading to the following equations which are implemented into the SPICE subcircuit for the fully scalable BSIM3 RF model Using the distances according to the previous figure the resistors are calculated from R D__ SHB gg RBPS RBPD 2 W W P
115. figure below for details Note For the Agilent E5250 the port number to be entered consists of 3 numbers If for example SMU1 is to be connected to Card No 1 Port No 3 Enter the number 103 into the field below the transistor s node name Port No 12 for Card No 4 would have to be entered as 412 Note When using module names to measure devices with probe cards pay attention to the node numbers you are entering Each device uses 4 connections to the switch matrix You have to enter the correct pin numbers for each DUT and must not exceed the total pin count for each port of your matrix Connections to the DUTs The following figure shows an example for a connected device under test DUT to the source measurement units SMUs during DC Transistor measurements The node numbers shown are to be entered into the fields on the Device List folder see Device List tree with entries for the devices to be measured The above mentioned figure shows 0 under all terminal names Those numbers have to be changed to 10 for the gate 12 for the source 11 for the bulk and 9 for the drain terminal to reflect the connections used inside the following schematic Please be careful to use the names SMU1 SMU4 during hardware setup in IC CAP since these are required by the measurement module of the BSIM3 4 and PSP Modeling Packages SMU connections to the device under test 26 MOSFET Models DUT Example of Switch matrix
116. for multiple measured devices You can perform a quick consistency check of the measured data versus gate length gate width and temperature If there are measurement errors they can be easily identified using this additional check of DC measurement data Drain Saturation Current Idsat Displaying the absolute values of IDSAT versus the gate length of all measured devices does not easily show measurement errors because the absolute currents spread all over the diagram as shown in the left part of the following figure In this diagram absolute values of IDSAT versus L and W are displayed IDSAT is determined at max Vg max Vd and Vb 0 for one temperature Each dot represents one transistor and each color a different value of the transistors gate width W The legend is shown to the right of the plot If you select one of the dots at the top of the plot the details of this specific transistor are shown In our example of Idsat the red dot in the middle of the plot is a transistor with W 250nm and L 400nm The actual drain current of this geometry is also shown ldsat x PO Idsat normalized Idsat LAW M 32 Wdes 10 00u Ldes 1 000u Idsat_normalized 180 1u M 2 Wdes 250 0n Ldes 400 0n Idsat 89 41u LIE 1E 3 6 m b E 6 Idsat LOG oo 1E 5 idsat_normalized 1E 6 i 1E7 1E 6 1E 5 Ldes LOG Ldes LOG y Left part IDSAT f W L right part IDSATnorm f W L But if the same values measured
117. for the idvd_vg DC preverification measurement 4 Select the ac_bias setup then Instrument Options 5 Note that the instrument states are different for CW and list frequency measurements Set the instrument states a most the same as you did for the s_vgvdf preverification measurement with the following exceptions because you are now using the CW calibration instead of the broadband frequency list cal e Set Use User Sweep to Yes e Set Cal Set No to the cal set or register where you stored your CW calibration Note If you fail to use the CW calibration and use the broadband cal instead the measurement will take a great deal more time than expected It will measure data at all the bias points at every frequency point The plotted results will be hard to interpret Setting the Variables You set the values that define the main measurement and the model generation in the data_acquisition and model_generator transforms in the create_mdl setup Based on your information IC CAP characterizes the device within a subset range of the bias plane Vd Vg plane This range is typically larger than the normal safe range for long term DC device operation specified in the data sheet In other words the device is briefly pushed beyond its long term normal DC operating range This is required by the model for simulating large signal AC and transient pulsed operation where the instantaneous voltages can temporarily exceed the boundaries of long
118. g F_ParRef cg_vg execute_TOXO_NSUBO_VFBO_ opt Correct the path to the plots and to the data used in the upper and lower limit for the optimizer default region pel F_UsedPlot 0 cg_vg Cox_vg PlotO_x1 min cg_vg vg PlotO_x2 max cg_vg vg PlotO_y2 max cg_vg cox m PlotO_y1 1 5 min cg_vg cox m e Add a Reference SetUp in the optimize transform execute_TOXO_VFBO_opt e In the transform Scaling User_execute extr_NPO_NPL the value of the variables F_Prepare 0 and F_Simulate 0 has to be corrected to execute manageScale e Correct paths of the transform managing the optimizer 81 MOSFET Models ae Function Progam sss execute_TOXO_VFBO_opt e Correct paths of optimize transform i Instrument Options Setup Variables Extract Optimize Plots Setup GUI Items ae Funcion fae opt_TOXO_VFBO Algorithm evenberg Marquardt Enor Relative inputs Parameters Options Target abs cox m set_VFB_NSUB Simulated abs cox s set_VFB_NSUB Veight 1 00000 1 00000 1 00000 Target Min Plot0_y1 0 00000 0 00000 Target Max Plot0_y2 0 00000 0 00000 X Min Plot0_x1 0 00000 0 00000 X Max Plot0_x2 0 00000 0 00000 Curve Min Curve Max X Data Ref Reference SetUp cg_vg 09_Vg Define the Initialize Part Parameters plots default region and data handling are defined in the initialize section of the transform The begin and the end of the initialize section is defined b
119. gate cv setups set_cjbr A transform that makes an initial approximation to the parameter CJBR by setting it to the value of cjbvn at the point where the anode voltage is closest to zero cjbvn_sim A transform that calls JUNCAP to evaluate the area sub region component of capacitance fit_cjbvn An optimization definition that causes the parameters CJBR PB and VDBR to be optimized with respect to the normalized area sub region Capacitance The parameter limits are controlled by the following model variables which you can change in the model variables table CJBR_MIN CJBR_MAX PB_MIN PB_ MAX VDBR_MIN VDBR_MAX The data limits are controlled by the following variables which are also in the model variables table CV_VMIN CV_VMAX cjsvn A transform that extracts and holds the normalized locos sub region contribution to capacitance from the measurements in the area cv locos cv and gate cv setups set_cjsr A transform that makes an initial approximation to the parameter CJSR by setting it to the value of cjsvn at the point where the anode voltage is closest to zero cjsvn_sim A transform that calls JUNCAP to evaluate the locos sub region component of capacitance fit_cjsvn An optimization definition that causes the parameters CJSR PS and VDSR to be optimized with respect to the normalized locos sub region Capacitance The parameter limits are controlled by the following model variables which you can change in the model variables
120. in Differences between Non Fully Depleted Partially Depleted and Fully Depleted Categories Firstly a very strong back gate effect exists The body is not floating as is the case in a NFD device hence the body charge is constant The PD devices have characteristics between NFD and FD devices The device is classified as PD device If in normal operation full depletion at the drain end of the device could occurs There is a difference in modeling the bulk charge effect of FD devices In state of the art SOI devices with a silicon film thickness of around 40nm and buried oxide thickness in the range of 100nm a negative back gate bias with respect to the source terminal drives the back interface into accumulation and therefore turns the device into PD The transitional behavior of a FD SOI device is usually very strong whereas a PD device does not exhibit a strong transition behavior However in future technologies the buried oxide as well as the silicon film thickness could be reduced further to avoid short channel and self heating effects and the transition behavior of PD devices is likely to become stronger In BSIMSOI there is a model selector flag to switch between models 292 MOSFET Models e The flag SOIMOD has value 0 for partially depleted devices default is BSIMPD e Setting SOIMOD 1 switches the model to the unified model for partially and fully depleted SOIMOS whereas for SOIMOD 2 the ideal fully depleted model equati
121. in the Temperature Setup folder and click OK Note You cannot prevent a DUT from being measured at TNOM All DUTs are measured automatically at that temperature If you have entered one or more temperatures on the Temperature Setup folder the DUTs selected for temperature measurement are all measured at those temperatures In other words you cannot select a DUT for measurement at temperature T1 but not at another temperature m2 To start measurement of the devices Click the Measure icon and select the DUTs to be measured on the dialog box that opens You can select measurement temperature if there is a temperature other than TNOM defined in the Temperature Setup folder as well as a specific DUT Start the measurement with Measure on that dialog box If measuring at elevated temperatures be sure to wait until your devices are heated or cooled down to the desired temperature If you would like to clear data of some or all measured DUTs use Clear Data from the Data menu Select whether you would like to clear measured data of some or all DUTs at specified temperatures and click Clear Data to delete measured data files Using Synthesize Measured Data from the Data menu you can simulate data from existing parameters This synthesized data uses the voltages set on the Measurement Conditions folder to generate measurement data from a known set of SPICE parameters To see the diagrams of what has just been measured use the Display Plots
122. increase of the total drain current through hot electrons will be described by the part Vascpe Of the Early voltage which results in a lowering of the output resistance for high 135 MOSFET Models drain voltage following figure 7 SCBE2 Pscpei T ASCBE L V3 Vasat Substrate Current Body Effect SCBE CE 3 rourk s u nh I 43 rout m w 12mm 6 6 0 3 L 1 mn M o n in vo CE aJ Substrate Current In a n channel MOSFET electrons in the channel experience a very large field near the drain In this high field some electrons coming from the source will be energetic enough to cause impact ionization and additional electrons and holes are generated by avalanche multiplication The high energy electrons are referred as hot electrons The generated electrons are attracted to the drain adding to the channel current while holes are collected by the substrate contact resulting in a substrate current which is shown in the following figure Generation of Substrate Current in an n channel MOSFET Gate Source n _ n Drain o holes T electrons lsu Substrate Current Ibs parameterized by Vg t ib s CLOG ib ym va CE e The substrate current is described in BSIM3 by the following equation Bs bia es L A ee Pe i K ds Vaseff es ES Tas aii V eff ds dseff A i 136 MOSFET Models Drain Bulk and Source Bul
123. induced drain leakage currents IGIDL Impact Ionization Model BSIM4 uses the same impact ionization model as was introduced in BSIM3v3 2 The impact ionization current is calculated by ALPHA0 ALPHA1 L O OO ef 7 7 ty Loff ds Vaseff La NF 4 en s anran me h E S ds dseff i ds ds0 cim Asat V dseff i 7 _V f 7 _V Vas V iseff Vas V aseff 44 4s__dseff ds _ dseff apist Yapirs Gate Induced Drain Leakage The GIDL effect is modeled by te V cse EGIDL lampr oO o m 3 TOXE v exp 2 TOXE BGIDL db Vas Vese ECDL oy 4 7 Body Current Model Parameters 205 MOSFET Models Equation Variable Parameter Name Description Default Value ALPHAO ALPHAO First impact ionization parameter 0 0 Am V ALPHA1 ALPHA1 Length dependent substrate current parameter 0 0 A V BETAO BETAO Second impact ionization parameter 30 V AGIDL AGIDL Pre exponential coefficient for GIDL 0 0 mho 1 Ohm BGIDL BGIDL Exponential coefficient for GIDL 2 3e9 V m CGIDL CGIDL Parameter for body bias effect on GIDL 0 5 V3 EGIDL EGIDL Fitting parameter for band bending for GIDL 0 8 V Stress Effect Modeling The scaling of CMOS feature sizes makes shallow trench isolation STI a popular technology To enhance device performance strain channel materials have been used The mechanical stress introduced by using these processes causes MOSFET performance to become a function of the active device area and the locati
124. injection parameter for bipolar current 0 drain side 317 2 10 Capacitance XPART CJSWG CJSWGD MJISWG MISWGD PBSWG PBSWGD TT NDIF LDIFO VSDFB VSDTH CSDMIN ASD CSDESW CGSO CGDO CGEO CGSL CGDL CKAPPA CF CLC CLE DLC DLCB DLBG DWC DELVT FBODY ACDE MOIN Charge partitioning rate flag Source gate side sidewall junction capacitance per unit width normalized to 100nm Si Drain gate side sidewall junction capacitance per unit width normalized to 100nm Si Source gate side sidewall junction capacitance grading coefficient Drain gate side sidewall junction capacitance grading coefficient Source gate side sidewall junction capacitance built in potential Drain gate side sidewall junction capacitance built in potential Diffusion capacitance transit time coefficient Power coefficient of channel length dependency for diffusion capacitance Channel length dependency coefficient of diffusion cap Source drain bottom capacitance flatband voltage Source drain bottom capacitance threshold voltage Source drain bottom minimum capacitance Source drain bottom diffusion smoothing parameter Source drain sidewall to substrate fringing capacitance per unit length Non LDD region gate source overlap capacitance per channel length Non LDD region gate drain overlap capacitance per channel length Gate substrate overlap capacitance per unit channel length Light d
125. instrument waits before setting each frequency No delay is needed here but the default is 100 ms 8 Port 1 Source Power and Port 2 Source Power are used with an analyzer that has an integrated test set Set the power to the same level as in the network analyzer calibration Take care that the power level will not be excessive at the device input or at the input port samplers of the analyzer The default is 10 dBm 9 Port 1 Power Range and Port 2 Power Range are used with an analyzer that has an integrated test set The synthesized source in the analyzer contains a programmable step attenuator with eight power ranges This lets you determine which range is used the default is 0 10 Port 1 and Port 2 Auto Power Range are used with an analyzer that has an integrated test set These settings enable an autoranging power level and attenuation capability The default IC CAP setting is No 11 Coupled Port Power is used with an analyzer that has an integrated test set It couples port 2 to the port 1 power settings ignoring the settings for port 2 The default is Yes to couple the ports together 12 If you calibrate with a power slope set the corresponding value for Power Slope here to better view the response of a device with power drop off at higher frequencies The units for power slope are dB GHz the default value is 0 000 A network analyzer message will caution you that the correction may be invalid but this can be ignored 13 Set th
126. is ignored Electrical Process Saturation Field Factor Used in the level 3 model to control saturation output conductance Intrinsic Transconductance If not specified for the level 2 model KP is computed from Kp u0 Cox In some of the literature KP may be shown as k The default for the LEVEL 1 model is 2x10e 5 LAMBDA Channel Length Modulation Models The finite output conductance of a MOSFET in PHI THETA AD AS NRD saturation It is equivalent to the inverse of Early Voltage in a bipolar transistor Specifying this parameter ensures that a MOSFET will have a finite output conductance when saturated In the level 1 model if lambda is not specified a zero output conductance is assumed In the level 2 model if lambda is not specified it will be computed Surface Potential Models The surface potential at strong inversion If not specified in level 2 and level 3 models it is computed as PHI 2kT g In Nsub ni PHI also may be shown as 2 PHIb Mobility Reduction Used in level 3 to model the degradation of mobility due to the normal field Device Geometry Drawn or Mask Channel Length Physical length of the channel Drawn or Mask Channel Width Physical width of channel Area of Drain Area of drain diffusion Used in computing Is from Js and drain and source capacitance from Cbd CjAd Area of Source diffusion Can be used as described for AD Equivalent Squares in Drain Diffusion Number of equivalent squar
127. li roar ied Drain network o 6 c ee ei ee i i CDSEXT 10 30 0 1f LDRAIN 1 10 1p Be Sei Sone eo Saxe SoS Seo noe aa eee ae eee Se LSOURCE 3 30 1p aS ees SUCST Pete NStWOL hh Se ease Hee Soa Senae essere Soa eee SS eee Diodes are for n type MOS transistors echo Djdb_area 12 10 bsim_diode_area AREA Sdpar x_rf_transistor AD 10e 12 echo Djdb_perim 12 10 bsim_diode_perim AREA Sdpar x_rf_transistor PD 22e 6 echo Djsb_area 32 30 bsim_diode_area AREA Sdpar x_rf_transistor AS 10e 12 echo Djsb_perim 32 30 bsim_diode_perim AREA Sdpar x_rf_transistor PS 22e 6 RBDB 12 40 100 RBSB 32 40 100 RBPD 12 41 100 RBPS 32 41 100 LBULK 4 40 1p Gall single MOSFET sos oc e es i i ie ee iis ee eis echo MAIN 10 21 30 41 BSIM3_HF echo L Sdpar x_rf_transistor L 1u W Sdpar x_rf_transistor W 10e 6 echo AD Sdpar x_rf_transistor AD 10e 12 AS Sdpar x_rf_transistor AS 10e 12 echo PD Sdpar x_rf_transistor PD 22e 6 PS Sdpar x_rf_transistor PS 22e 6 echo NRS Sdpar x_rf_transistor NRS 0 NRD Sdpar x_rf_transistor NRD 0 echo NQSMOD Smpar NQSMOD 0 ends The single BSIM3 RF model represents exactly one measured test device the substrate resistance network uses fixed values for the resistors RBPS RBPD RBDB and RBSB Also the external parasitics L C are fixed and valid only for one measured device Using this approach the parameters
128. minimum and maximum values The instance and switch parameters are listed first followed by the regular parameters Instance parameters for local and global model Parameter Parameter used only for Local Description Unit Default Min Max Global B inning L G B Drawn channel length m 1 0E 6 1E 9 W G B Drawn channel width m 1 0E 6 1E 9 SA L G B Distance between OD edge and m 0 poly at source side SB L G B Distance between OD edge and m 0 poly at drain side ABSOURCE L G B Source junction area m2 1 0E 12 0 LSSOURCE L G B STI edge part of source junction m 1 0E 06 0 perimeter LGSOURCE L G B Gate edge part of source junction m 1 0E 06 0 perimeter ABDRAIN L G B Drain junction area m2 1 0E 12 0 LSDRAIN L G B STI edge part of drain junction m 1 0E 6 0 perimeter LGDRAIN L G B Gate edge part of drain junction m 1 0E 6 0 perimeter AS L G B Source junction area m2 1E 12 0 AD L G B Drain junction area m2 1E 12 0 PS L G B Source STI edge perimeter m 1E 6 0 PD L G B Drain STI edge perimeter m 1E 6 0 MULT L G B Number of devices in parallel 1 JW L Junction Width m 10E 6 0 If SA SB O the stress equations are not computed Switching Parameter SWJUNCAP for Capacitance Calculation global and local level SOURCE DRAIN SWJUNCAP AB LS LG AB LS LG 0 0 0 0 0 0 0 1 ABSOURCE LSSOURCE LGSOURCE ABDRAIN LSDRAIN LGDRAIN 2 AS PS 0 AD PD 0 3 AS PS WE WE AD PD WE W
129. model is an enhanced version of the MOSFET LEVEL 2 model refer to the section HSPICE LEVEL 6 MOSFET Model mosfet for parameter measurement and extraction information The IC CAP MOSFET modeling module provides setups that can be used for general measurement and model extraction for MOS devices Four example files are provided for the MOSFET model the files can also be used as a template for creating custom model configurations nmos2 mdl extracts parameters for the LEVEL 2 N channel model pmos2 mdl extracts parameters for the LEVEL 2 P channel model nmos3 mdl extracts parameters for the LEVEL 3 N channel model pmos3 mdl extracts parameters for the LEVEL 3 P channel model The IC CAP system offers the flexibility to modify any measurement or simulation specification The model extractions provided are also intended for general MOS IC processes If you have another method of extracting specific model parameters you can do so with the Program function or by writing a function in C and linking it to the function list For Program function details or for writing user defined C language routines refer to Transforms and Functions extractionandprog 372 MOSFET Models UCB MOSFET Model Simulators and Model Parameters UCB MOSFET Model The UCB MOSFET model is fully compatible with the UCB model developed for use with the UCB SPICE simulator The model is actually a combination of three models each being specified by an appropriate val
130. model is generated for each available test device A design library based on such models does not enable the circuit designer to modify major device dimensions Only available devices can be used to design circuits A major benefit of this approach is that the accuracy of such a model may be very high because only one certain device behavior has to be fitted by the model parameters Scalable transistor models cover a certain range of major device dimensions In the case of a RF MOS transistor these are the gate length and gate width of a single transistor finger and the number of gate fingers These models have a structure such that a design engineer can change the parameters to get an optimum transistor behavior for a certain application In BSIM4 3 0 there is a newly introduced enhancement to modeling the substrate resistance To take care of different geometric layouts a so called horseshoe contact geometry was added see details below inside the paragraph about Substrate contact resistance scaling The following two sections describe the structure of the single and the scalable model approaches At first the general structure of the BSIM4 RF model is shown Single Transistor Model Schematic for the Single Transistor Model Source For the single transistor model all substrate resistance parameters RBPB RBPD RBPS RBDB and RBSB are set to fixed values for one certain device This is the default 211 MOSFET Models app
131. model parameters extraction therefore for modeling process refer to the Using the MOS Modeling Packages mosfet section e The PSP GUI enables the quick setup of tests and measurements followed by automatic parameter extraction routines e The data management concept allows a powerful and flexible handling of measurement data using an open and easy database concept e The extraction procedure can be adapted to meet different needs Although the extraction procedure is recommended by the model developers and followed by the standard extraction flow however experienced users can change the flow Note Since parameter extraction for the global model depends on the extraction sequence only an experienced user should manipulate the default extraction flow as described in PSP User Manual Parameter Extraction Sequence The following sections describe the extraction sequence of parameters e Extraction of Parameters using the Local Global approach mosfet Parameter Extraction using Global Model mosfet Simultaneous Adjustment of Local and Global Parameters mosfet Binning of PSP Models mosfet Parameters for the PSP model mosfet See Also Using the MOS Modeling Packages mosfet BSIM3v3 Characterization mosfet BSIM4 Characterization mosfet BSIMSOI4 Characterization mosfet 254 MOSFET Models Extraction of Parameters using the Local Global approach Because of correlations you should not derive all local para
132. mosfet single_temp_lin_opt1 is an optimization call to fit linear region data at Vbs O for all the devices at a particular non nominal temperature The variables optimized are xVTOR xBETSQ xTHE1R and xSLTHE1R single_temp_lin_optz2 is an optimization call to fit linear region data for all Vbs for all the devices at a particular non nominal temperature The variables optimized are xXTHE2R and xSLTHE2R single_temp_subvt_opt1 is an optimization call to fit subthreshold data for Vbs O for all the devices at a single non nominal temperature The variable optimized is xMOR single_temp_ids_opt1 is an optimization call to fit ids at Vbs O for all the devices at a single non nominal temperature The variables optimized are XTHE3R and xSLTHE3R single_temp_isub_opt1 is an optimization call to fit the avalanche current at Vbs O for all the devices at a single non nominal temperature The variable optimized is xA1R single_temp_limit_check is called at the end of the parameter optimization for a single non nominal temperature to check the single temperature parameters with respect to their limits It is used by the macro optimize_at_one_temperature extract all_temp_extract contains the extraction sequences needed for optimization of the temperature coefficients of MOS Model 9 for all the devices measured at all non nominal temperatures These parameters are ETABET STVTO STTHE1R STLTHE1 STTHE2R STLTHE2 STMO STTHE3R STLTHE3 an
133. mpar ACDE 1 echo MOIN Smpar MOIN 15 DLC Smpar DLC 0 DWC Smpar DWC 0 echo LLC Smpar LLC 0 LWC mpar LWC 0 LWLC S mpar LWLC 0 echo WLC Smpar WLC 0 WWC Smpar WWC 0 WWLC Smpar WWLC 0 echo CLC mpar CLC 0 1E 6 CLE Smpar CLE 0 6 ELM Smpar ELM 2 echo XPART Smpar XPART 0 5 KT1 Smpar KT1 0 11 KT1L Smpar KT1L 0 echo KT2 Smpar KT2 0 022 UTE Smpar UTE 1 5 UA1 mpar UA1 4 31E 9 echo UB1 Smpar UB1 7 6E 18 UC1 Smpar UC1 5 6E 11 AT Smpar AT 3 3E4 echo PRT Smpar PRT 0 XTI Smpar XTI 3 0 TPB Smpar TPB 0 echo TPBSW Smpar TPBSW 0 TPBSWG Smpar TPBSWG 0 echo TCJ Smpar TCJ 0 TCJSW Smpar TCUSW 0 TCJSWG Smpar TCUSWG 0 ech AF mpar AF 1 5 EF mpar EF 1 5 KF Smpar KF 1e 17 EM Smpar EM 4 1E7 ech NOTA Smpar NOTA 2e29 NOIB Smpar NOIB 5e4 NOTC Smpar NOIC 1 4e 12 Rone Parasitic diode model cards Hoare s Hesse eqss Has reae RN o eens aS re SRS O O O00 0 O O 0 0 OO OO 0 0 O 0 OO 0 40 0 0 0 O 0 CO OO OO OO O O O 0 echo MODEL bsim_diode_area D echo CJO Smpar CJ 5E 4 Vd Smpar PB 1 M Smpar MJ 0 5 echo IS Smpar JS 1 0E 4 N Smpar NJ 1 echo MODEL bsim_diode_perim D CJO mpar CJSW 5E 10 VJ mpar PBSW 1 echo M Smpar MJSW 0 33 IS Smpar JSW 1 0E 12 N Sdpar CCALC NJSW 1 FS See SSE Gate INEEWOrK Serer r Sess ese Sesh bee SSeS ere Seo eee See ees CGDEXT 20 10 0 1f CGSEXT 20 30 0 1f RGATE 20 21 100 LGATE 2 20 1p
134. multiplication of parameters among others as shown here RDVD x LDRIFT1 RDICT1 x LDRIFT2 RDICT2 x saa If either LDRIFT1 and RDICT1 Or LDRIFT2 and RDICT2 are zero the whole expression is zero The following table gives an overview of the different parameters used with each possible CORSRD flag CORSRD Model parameters used for this selection 0 No resistances i RS NRS RSH RDVG11 RDVG12 RDVB RDS RDSP NRD RD RDVD RDVDL RDVDLP RDVDS RDVDSP RDSLP1 RDICT1 RDSLP2 RDICT2 RDOV11 RDOV12 Same as CORSRD 1 but nodes solved internally E RD21 RD22 RD23 RD23L RD23LP RD23S RD23SP RD24 RD25 RD20 This model flag considers both CORSRD 1 and CORSRD 2 RDVG11 RDVB RDVD RDTEMP1 RDTEMP2 RDVDTEMP1 RDVDTEMP2 The flag CORSRD 3 is the most comprehensive using the most model parameters In most cases you should use the CORSRD flag with the value 3 which is the default setting in HiSIM_HV w N e 252 MOSFET Models Additional SPICE Model Parameters for HiSIM_HV The following tables list the model parameters used in the HiSIM_HV MOS model together with the default values and the range possible for that parameter Parameters Introduced for HiSIM_HV 233 MOSFET Models ead pan Ee atv Poserietee uae NSUBCW 1 0 cmNNSUBCWP INSUBCWP 0 SCSTI3 0 p SUBLD1 0 SUBLD2 0 MPHDFM 0 3 E 3 RTHO Ker CTHO 1 1E 7
135. multiplot window named Display Template It is used to store a set of displayed plots under a user specified name This feature is intended to compare plots created with different extraction steps for example Arrange all plots you want to be stored then press the save button and enter a name into the appearing window or accept the given one To open an arrangement already saved simply choose the one to be displayed from the Display Templates pull down menu Folder Cycle Devices Inside the Select Bias Condition area select one or both diagram types IdVg and or IdVd Then click the desired voltages temperatures and outputs for the selected diagram types You are able to mark one or more rows in each of the columns To mark more than one voltage temperature or device press and hold the left mouse button and select the items to be displayed The Select Device area shows the devices with the appropriate type of data according to your choice For example selecting a temperature other than room temperature will show only devices that are measured at those temperatures Press Redisplay after you ve made your choice 57 Cycle Devices El Cycle Plot Types All Diagrams 10 x Device Type IUES Bias Conditions Setup Temperature 27 mdm Type YP 23 fidvd 12 vgivt vb S 0 0 Select Output X Axis Scaling Math vd Linear Axis Scaling Math fid Linear z I 2 A
136. not saturated The output resistance is small because the drain current has a strong dependence on the drain voltage The other three regions belong to the saturation region The three physical effects CLM DIBL and SCBE can be seen in the saturation region and are discussed in the following sections 133 MOSFET Models With the output resistance the equation for the drain current Enhanced Drain Current Equation is enhanced by two additional terms and can be rewritten as I V V V V i ae 1 ds dseff 1 dseff as ds0 dseff A ASCBE The behavior of the output resistance is modeled in BSIM3 in the same way as the Early voltage of a bipolar transistor is modeled in the Gummel Poon model The Early voltage is divided in two parts V due to DIBL and CLM and Vyccp e due to SCBE V is given by v4 iar t Este ee 5 sat eff ACLM ADIBLC where Vasat is the Early voltage at Visat Asa A V Cc 1 bulk dsat E e a A tik v WV l gt sat eff dsat ds sat ox eff gsteff 2P staff 2V im V 27 i Asat 21 14 Annas sat ox eff b Channel length modulation CLM When the drain bias approaches the drain saturation voltage a region of high electric field forms near the drain and the electron velocity in this region saturates In saturation the length AL of the high field region increases by an expansion in the direction of the source with increasing drain source voltage Vys and t
137. not start any other transforms with opt_ or extr_ In contrast you can use any name for the transform containing the optimizer execute_TOXO_VFBO_opt besides opt_xxx or extr_xxx Change the code of the transform opt_TOXO_VFBO e Assign a unique ID F_ID USER_001 e Do not begin the ID with AdMOS_ thus this IDs may be used e Assign a name to be display in the GUI F_Name O TOXO VFBO User defined e The name of an optimizer step must start with O and the name of the extraction step must start with E There must be a blank before and after the dash e Set the variable for the setup to the new setup F_Setup C_Oxide User_cg_vg PSP module with new setup and a user defined function PSP_DC_CV_Extract PSP_DC_CV_Extract C_Oxide User_cg_vg is Active 25 Seed Eile Edit Measure Extract Simulate Optimize Data Tool Macros Windows Help S XID PFs 2 2 S HHO Se Hoaise DUTs Setups Circuit Model Parameters Model Variables Macros Model GUI Items Select DUT Setup __DC_Transistor a Global oe fp Function Pogam e boe Scaling B if Vth_Idsat_vs_Devices __DC_Transistor_STI_ STI Large_SA Nartow_SA Measure Simulate Instrument Options Setup Variables Extract Optimize Plots Setup GUI Items execute_TOXD_VFBO_opt n D LUbebt C_Intrinsic __DC_Diode Diode_BD Diode_BS Display_Templates_ Cycle Device v lt g
138. o The PEL button opens a window showing the default region calculation This is done using the PEL language Use this window to change the calculation by editing the values or changing the formulas used for calculation Within this region calculation window you are also able to reset any changes made using the Default button and or to Accept and Show changes in Plot 0 Using OK the selected or calculated region is accepted and used for this extraction step o The Store button enables you to store intermediate results This is useful for a what if scenario Once you ve stored parameters the selection field to the right of the Store button enables you to select either the stored parameters or the results of the default step to be used for the next extraction step Each parameter set you ve stored will be given an extraction number using the sequence of the extraction e If there is an optimizer step programmed during this extraction the folder name changes from Extract to Optimize and there are fields to select optimizer features like Algorithm or Error The Parameters field now enables you to enter parameter values manually by double clicking the parameter field and entering a value You are also able to change boundaries of the parameters by using Autoset the parameter value will be multiplied by 0 5 and 5 to determine the boundaries or Reset boundaries as have been defined inside IC CAP model parameters window are used Adopt will overwrite the
139. of parameters that can be extracted and will lead to a better fit of the curves over the range of different channel widths Short For the DUT Short_m you should use a device with the shortest designed gate length of your process Using more short devices will increase the number of parameters that can be extracted and will lead to a better fit of the curves over the range of different channel lengths Small For the DUT Sma _m you should use a device with the shortest designed gate length and the smallest designed gate width of your process This small device will incorporate all short and narrow channel effects and will be an indicator of how good your parameter extractions are In general It is recommended to use the designed gate lengths and widths Effects due to 166 MOSFET Models under diffusion or decrease of poly Si gate length are sufficiently covered by the extraction routines and the model itself Drain Source Bulk Diodes for DC Measurements Test Structures for Drain Source Bulk Diodes DUT Shape Comment Diode_Perim_m Finger diode with a large perimeter and a small area shown here for Area diode with a large area and a small perimeter shown here for an n type device Test Structures for CV Measurements The following table provides example test structures for measuring capacitance voltage properties Each test structure includes a description as well as a schematic for setting up
140. of gate fingers multiplication factor number of gate contacts substrate resistance network substrate resistance network substrate resistance network substrate resistance network substrate resistance network diffusion length between gate and STI diffusion length between gate and STI diffusion length between gates device temperature device temperature change substrate impurity concentration substrate current induced in Lyi substrate current induced in Larift Basic Device Parameters Unit 3653 3 09 9 09 D0 o o PIBIS S I W gt gt 23d MOSFET Models Heed Perea rae oe Peete Unit Name min max TOX 30n physical oxide thickness m XL 0 difference between real and drawn gate length m xw 0 difference between real and drawn gate width m XLD 0 0 5 On g ate overlap length xw 0 10n 100n lg ate overlap width TPOLY 2 00E 07 height of the gate poly Si for fringing To Bae LL 0 coefficient of gate length modification LLD 0 coefficient of gate length modification m LLN 0 coefficient of gate length modification WL 0 coefficient of gate width modification WLD 0 coefficient of gate width modification m WLN 0 coefficient of gate width modification NSUBC 0 substrate impurity concentration cm 3 NSUBP 1 00E 17 1E16 1E19 maximum pocket concentration cm 3 LP 15n 0 300n pocket penetration length m NPEXT 5 00E 17 1E16 1E18 maximum conce
141. of the optimizer F_UsedPlot 1 log_Cox_vg Decrease the number of elements in the ICCAP ARRAY F_UsedPlot F_UsedPlot ICCAP_ARRAY 2 The plot will not be considered for optimization until it is added to the Optimizer execute_TOXO_VFBO_opt Change the default region of the optimizer by increasing the upper limit of the y data PlotO_y1 2 min cg_vg cox m Definition of the plots and default region 83 MOSFET Models PSP_DC_CV_Extract C_Oxide User_cg_veg is Active 34 nulate Optimize Data Tools Macros Windows Help P S EA E OGG QS 1 eters Model Variables Macros Model GUI Items Measure Simulate Instrument Options Setup Variables Extract Optimize Plots Setup GUI Items on Progam The function to be executed by the Execute button in the Interactive Plot window is defined by the executing section it will be executed from an automatic extraction as well xecute Select Transform execute_TOXO_VFBO_opt unchons s Define the execution part Begin and end of the executing section is defined by if val action execute then end if In this section you can define our own extraction function A function to fit the curve through the first and the last data point only is presented as an example e User defined extraction function Funcion ogan Define the error handling Select Transform The error message of the failcode set in the execution sectio
142. parasitic values in the variable table do not perform the compute_para transform If you do not wish to make changes to the parasitic values select the compute_para transform in the create_mdl setup and Execute You will probably observe changes in the parasitic values in the table Note You can copy the variable table by selecting Detach to display it in a separate window Resize the window and move it to a convenient place away from the central work area Setting the Starting Point for Contour Integration Note For the modeled nonlinear functions to be valid contour integration must be done in the normal operating range of the device Outside the range the results will be very different and less accurate The further from the operating range the less accurate the model will be 339 MOSFET Models Use the following guidelines to set the starting point of contour integration 1 The starting point should be set at an intersect of Vd and Vg that is within the saturated class A operating range of the device where drain voltage is beyond the knee and less than breakdown and gate voltage is between Vthreshold and Max Vg Example of Appropriate Contour Integration Starting Point em mt ee CS AE RTU ENEI a DID uet whervla Ittt So 2 tLe oF firse sa SE hone sander Ae aque ever 2 If you know Vthreshold and Vbreakdown set e Vthreshold lt vg_start lt vgmax and Vknee lt vd_start lt Vbreakdow
143. pe P region e Back to BSIM3v3 Characterization mosfet 165 MOSFET Models Test structures for Deep Submicron CMOS Processes A very important prerequisite for a proper model parameter extraction is the selection of appropriate test structures The following sections describe the necessary test structures for the determination of CV and DC model parameters A very detailed description of ideal test structures can be found in the JESSI AC 41 reports References mosfet 2 Transistors for DC measurements The minimum set of devices for a proper extraction of DC model parameters is marked with E in the following figure This means one transistor with large and wide channel and therefore showing no short narrow effects one transistor with a narrow channel one transistor with a short channel and one device with both short and narrow channel Please note that with this minimum set of devices some parameters cannot be determined correctly see Programming extractionandprog and they are set to default values during the extraction For an extraction of all model parameters and a better fit of the simulated devices over the whole range of designed gate length and gate width use more devices with different gate lengths and gate widths as shown in the following figure with signs You can use additional devices for example for evaluating the extraction results for certain channel lengths and widths used in you
144. purposes The parameters DWG and DWB are always off therefore they cannot be de selected Related Topics e DC Notes mosfet e DC Information mosfet e DC Initialize mosfet 107 DC Extract mosfet DC HTML mosfet DC Options mosfet DC Boundaries mosfet Back to Extraction of DC and CV Parameters mosfet MOSFET Models 108 MOSFET Models Extraction of Parameters for the RF Models Start extraction of RF parameters for the BSIM3 or BSIM4 PSP models by clicking the appropriate extract model to open the graphic user interface GUI you are already familiar with The tasks are separated on subfolders for easy handling Some of the folders are using the same look as in the DC Extraction part of the BSIM3 and BSIM4 PSP Modeling Tools can BSIM4_RF_Extract 12 loj x Fie Initialize Extract Plots HTML Options Boundaries Help EAEE IG t xA nE Notes Information Initialize Extract Display HTML Options Boundaries General data Technology Lot Wafer Chip Operator Date Notes on project Project Example_Scale Project directory j users deFault_2009 Status The top row menus are described in DC and CV Measurement mosfet As soon as you click File gt Open the PreSelection dialog box opens prompting you for some basic definitions for parameter extraction lolx Pre Selection of Special DC Bias and Frequency Settings Constant Frequency
145. r a a ey gt 5 m U0 f T i wee ww wwe wwe www eee de ww ewe eee eee ee ee eeee bene eee eee eee eee ee i calc UB T m B Foo o D g a gt w o i 366 4 356 4 400 8 Temperatures CE e c Saturation of Carrier Velocity The carrier velocity VSAT is reduced with increasing temperature as shown in the following equation and Output Characteristic VSAT f T T E nom Vo 47T VSAT AT 1j Output Characteristic Id f Vd T id f Yd Vb 0 Vg max m 5 LJ LJ a 4 TEE o ET TE beuleecucese ni AT 0 4 i Vsat const E v 2 vo CE 0J Temperature 250 4800K Output Characteristic VSAT f T 96 0 E 3 AT 0 Vsat const 55 9 a aa aa a mies calc VSAT T m B Foe 30 0 calc YSAT T s AT 33 000 Vsat f T 75 5 76 6 254 6 368 4 356 4 4668 4 Temperaturs CE E d Drain source resistance The temperature dependence of the drain source resistance is given by the following equation see Drain source resistance RDSW f T 158 MOSFET Models T T nom Rysp D RDSW PRT 1 Drain source resistance RDSW f T m wa H 322 4 ma WT 222 2 4 i mii gT i ai 322 8 3 r 1 i l Oo i 321 686 4 P ms i i U h E 321 6 i i i i i i a21 4 5 4 3 i A 321 2 m 250 0 366 4 356 4 66 4 ie Temp
146. range to cover the cutoff as well as the linear region including the mobility reduction range The bulk should be biased at OV as well as at values that cover the normal operating range of the device Parameters UO and VTO are first extracted from the Vb O curve To calculate these parameters a least squares fit is carried out to the maximum slope of the curve in the linear region The parameter UEXP is calculated to fit the reduction in the slope of the Same curve when higher gate voltages are applied The parameter is calculated based on the specified value of UCRIT The combination of UO UEXP and UCRIT has a redundant parameter IC CAP keeps the UCRIT fixed at its specified value and extracts UO and UEXP An unreasonable value for UCRIT might result in an unexpected value for the mobility UO The same curve fitting is carried out on the curve with the largest absolute value of bulk voltage The threshold voltage at this bias is then calculated from the intersection of this line The parameter NSUB is calculated from the difference in the two threshold voltages Narrow Width Parameter Extractions This extraction calculates the narrow device parameters WD and DELTA from the Id versus Vg measurement The setup and extraction are similar to the classical extraction The threshold voltage VTH and Beta effective mobility are calculated using least squares fitting The parameter WD is calculated from Beta and UO The parameter DELTA is calcu
147. second one uses the tuner T the third one uses the optimizer O Related Topics RF Extract Notes mosfet RF Extract Information mosfet RF Initialize mosfet RF Display mosfet RF Extract HTML mosfet RF Extract Options mosfet RF Extract Boundaries mosfet Back to Extraction of Parameters for the RF Models mosfet RF Extract Boundaries The Boundaries folder is the same as the one in DC Extraction For details see DC Boundaries mosfet Related Topics RF Extract Notes mosfet RF Extract Information mosfet RF Initialize mosfet RF Extract mosfet RF Display mosfet RF Extract HTML mosfet RF Extract Options mosfet Back to Extraction of Parameters for the RF Models mosfet RF Extract HTML This folder helps you to prepare a report file in HTML format to be displayed using an internet browser Since this folder is the same as in the DC Extraction section see DC HTML mosfet for details Related Topics RF Extract Notes mosfet RF Extract Information mosfet RF Initialize mosfet RF Extract mosfet RF Display mosfet RF Extract Options mosfet RF Extract Boundaries mosfet Back to Extraction of Parameters for the RF Models mosfet RF Extract Information The second folder Information has the same look and function as the one in DC Extraction See DC Information mosfet Related Topics RF Extract Notes mosfet 112 MOSFET Models RF Extract Notes
148. segment you defined 8 Press RETURN gt RETURN gt TRIGGER MENU gt CONTINUOUS to set a continuous stimulus Sweep 9 Press MENU gt POWER and set the desired power level then press the x1 terminator key In setting the source power and attenuation take care that the power level will not be excessive at the device input Also consider the gain of the device and set a power level that will not saturate the input port samplers of the analyzer If a receiver input is overloaded gt 14 dBm the analyzer automatically reduces the output power of the source to 85 dBm and displays the error message OVERLOAD ON INPUT R A B POWER REDUCED In addition the annotation P appears in the left margin of the display to indicate that the power trip function has been activated When this occurs reset the power to a lower level then toggle the SOURCE PWR on off softkey to switch on the power again 10 Press AVG gt AVERAGING FACTOR and enter an averaging factor high enough to reduce trace noise and increase dynamic range as appropriate for your device measurements A good default averaging factor is 256 To speed your measurements you may find it convenient to set an averaging factor as low as 16 Press AVERAGING ON 11 You can further reduce the noise floor by reducing the receiver input bandwidth Press IF BW in the average menu and enter one of the following allowed values in Hz 3000 1000 300 100 30 or 10 A tenfold reduction in IF bandw
149. set and should not be changed Measuring and Plotting This procedure triggers the DC source monitor measurement and monitors the results Note Before making the DC measurement manually put the network analyzer in hold sweep mode by pressing STIMULUS gt MENU gt MORE gt HOLD on an Agilent 8510 or MENU gt TRIGGER MENU gt HOLD on an Agilent 8753 Be sure to keep a UNIX window open so that you will see any compliance error that may be reported by the DC source monitor 1 From the Plots tab select Display All to the left of the setup window Two plots are displayed 2 Select the Measure Simulate tab then select Measure When the measurement is complete the Measuring light on the DC source monitor goes out the IC CAP wristwatch icon disappears and the measured data is displayed in the plot window 3 Check the id_vd plot The data displayed should resemble that shown in the following figure with the lowest curve close to the X axis to show the threshold characteristics If the data indicates the device is not operating in its normal range go back to the inputs and change the gate voltage values If more than one curve is low change vg Start to a higher value Or if all the curves are high change vg Start to a lower value Then select Measure again Example Measured pre_verify id_vd Data 328 MOSFET Models 4 If the measured data looks wrong for your device check the probe contacts the bias connections
150. showing the use of those temporary parameters tmp_rdb1 tmp_rdb2 tmp_rsb1 and tmp_rsb2 The following figure shows a RF multifinger MOS transistor with symmetric substrate contacts use RSUB_EQ 0 whereas 3 dimensional view of a symmetric substrate contact with Source connected to Substrate shows a 3 dimensional view of such a contact Symmetric substrate contacts top view Rup tmp_rdb1 5 5 5 5 5 5 5 5 5 A R PSLRA ERS HESS Rsubeg 0 Rep tnp_rsb1 3 dimensional view of a symmetric substrate contact with Source connected to Substrate The following equations are used to calculate substrate resistance temporary values inside the fully scalable model tmp rdbl feon ene odd YE PPRC EE tmp rsbl face see tmp rdb2 DHSDBCRSHB NF DGG L cho DHSDBC RSHB tmp rsb2 L NF DGG L 213 MOSFET Models The following figures show the horseshoe substrate contact as well as a 3 dimensional view of such a contact use RSUB_EQ 1 Horseshoe substrate contacts top view R sR tmp _rsb2 susssssssssss A e vases Rsubeg 1 Rpg mp_rdb2 The temporary values calculated above are combined to give BSIM4 model parameters as follows RSUB_EQ 0 RBDB RDB tmp rdb1 RBSB RSB tmp rsb1 3 dimensional view of a horseshoe substrate contact with Source connected to Substrate RSUB_EQ 1 _ _ tmp rdb1 tmp rdb2 a ae tmp rdb1 tmp rdb2 _ _ tmp rsb1
151. simultaneously solving the two equations for total capacitance of each of the measured structures An iterative method is used to obtain the built in potential and grading factors 382 MOSFET Models HSPICE LEVEL 6 MOSFET Model The general form of the Ids equation for the HSPICE LEVEL 6 MOSFET model is similar to the UCB MOS LEVEL 2 model However small geometry effects such as mobility reduction and channel length modulation are modeled differently Also the LEVEL 6 model can be used for modeling MOS transistors with ion implanted channels due to its multi level GAMMA capability The HSPICE MOS LEVEL 6 model is based on the ASPEC MSINC and ISPICE MOSFET model equations and has been enhanced by Meta Software Different versions of the model are invoked with the switch parameter UPDATE There are more than 5 other switch parameters that are used for selecting different model equations Refer to the HSPICE User s Manual References mosfet 2 for more information on this model The IC CAP LEVEL 6 model parameter extraction routines and configuration file are described in this section Three extraction functions for this model are included in the IC CAP function library The configuration file hnmos6 md supports a limited number and combination of parameters in the LEVEL 6 model However different parameter combinations can be supported by modifying the included optimization strategy This configuration file can also be used for the HSPI
152. temperature dependence of THESAT Coefficient for the width dependence of temperature dependence of THESAT Coefficient for the length times width dependence of temperature dependence of THESAT Coefficient for the geometry independent part of back bias dependence of velocity saturation Coefficient for the length dependence of back bias dependence of velocity saturation Coefficient for the width dependence of back bias dependence of velocity saturation Coefficient for the length times width dependence of back bias dependence of velocity saturation Coefficient for the geometry independent part of gate bias dependence of velocity saturation Coefficient for the length dependence of gate bias dependence of velocity saturation Coefficient for the width dependence of gate bias dependence of velocity saturation Coefficient for the length times width dependence of gate bias dependence of velocity saturation Coefficient for the geometry independent part of linear saturation transition factor Coefficient for the length dependence of linear saturation transition factor Coefficient for the width dependence of linear saturation transition factor Coefficient for the length times width dependence of linear saturation transition factor Coefficient for the geometry independent part of CLM pre factor Coefficient for the length dependence of CLM pre factor Coefficient for the width dependence of CLM pre factor Coefficient f
153. test structures are built on a silicon wafer on top of the silicon dioxide isolator This leads us to a propagation velocity of Cc C cC P JE XE J3 9 1 975 Using this result the physical length of the line would be _ Qc _ c 360 f 360 f 1 975 Example A measurement gives a phase difference between input and output of a through line as 10 at a frequency of 5 GHz The test structure uses silicon dioxide as the isolator material We would like to know the electrical length of our through test structure Using the above formula leads to p e 10 3x10 Therefore the physical length of the measured line is 0 84E 3 m or 840 um e Back to BSIM3v3 Characterization mosfet 175 MOSFET Models Extraction of Model Parameters This section describes the parameter extraction sequence and the extraction strategy Parameter Extraction Sequence The default setting of the extraction flow is programmed according to a procedure found to give best extraction results Using this macro everything is done automatically The extraction functions are equipped with error and plausibility checks If an error occurs or some parameters have strange or unrealistic values you will get an error warning at the end of the macro In some cases it can be useful not to extract all the parameters For instance if a 3 0 micron CMOS process has to be modeled with BSIM3 the typical short channel effects of the threshold volt
154. than the ratio between them An incorrect ratio of W L results in extraction of an unreasonable value for UO In general the mobility parameter UO should be set between 200 and 800 Start the extraction after setting the ratio of Land W to 1 then change the ratio of L to W to scale back the extracted value of UO Capacitance Measurement and Extraction Capacitance parameters can be extracted before or after the DC parameters The extraction requires that two different DUTs be measured model parameters are extracted from the second DUT The extraction in the cbd1 cjdarea setup requires a single geometry to be measured and produces the parameters CJ MJ and PB The extraction uses a transform set_CJ to find the initial zero bias value of CJ then uses optimization to obtain all three parameter values The extraction in the cbd2 cjdperimeter setup requires two geometries to be measured one in the cbd1 cjdarea setup and one in the cbd2 cjdperimeter setup that produces the parameters CJ MJ PB CJSW and MJSW and therefore a more complete capacitance model The extract transform uses the MOSCV_total_cap function to simultaneously solve for the bottom area and sidewall capacitance parameters To extract the capacitance contributions from the bottom area and the sidewall periphery the geometries must have different area to perimeter ratios The device measured with the cbd1 cjdarea setup should have a high bottom area to perimeter area ratio and t
155. the transform to generate the model if you are not performing a verification or at a later time as described at the end of this section Y data This file contains the Y parameters as a function of bias to examine through graphical interface NO changes can be made to the Y data file except for adding header and footer labels as explained under Plotting the Measured Data dc_test set or some other name designated by you If you decided to save it this is the measured DC data generated in the idvd_vg DC preverification procedure spar_test set or some other name designated by you If you decided to save it this is the measured S parameter data generated in the s_vgvdf S parameter AC preverification Verifying the Model DC Data This procedure verifies the model DC data against the DC data measured in the idvd_vg preverification setup using the MNS simulator link Note The simulator used must be MNS If the SIMULATOR in the model variable table is set to another value change it to mns The name of the model file must be State mds for the purposes of verification to maintain the MNS simulator link 1 Select the idvd_vg setup Make sure the output Type is set to B for both measured and simulated data 2 From the Plots tab select the id_vd plot and Display Plot Select Measure Simulate gt Simulate 341 MOSFET Models Example Measured and Simulated id_vd Data 4 Check that the simulated data dotted line a
156. the Parameter Extraction using the Global Model approach sat Copy Example Project Select Example Project Path c Agilent ICCAP _2009U 1 examples model_files mosfet psp examples dc_projects Example psp_binning psp_nmos_global _nmos Select target directory and name of project to which the Example is copied Path c users default Project _psp_nmos_global approach or for the Global only extraction Choose Extract gt Extraction Flow gt Default Flow to choose between two standard flows Local to Global or Global E Wheractive Extraction Execute Extraction ES Move Down Satta Lut action Rep XX Fion Delete Avadablie Functions Eran t 10 Function Pow aS gt T TORO NSUBO FBO TOO NSUBO VF Edt Goba Binning Par ameter Import Model Parameter Set Export Model Parameter Set Export Extracted Deck ad E traphal s r Fabre Log jet H ses f f amp temperature lt amp STI ress Effect lab Save Parameters Extraction will start vith Parameters o MPS Reset Parameters and Results global OO mps Pesuit is stored in File File lt gt global Ol mps Sets The default flow for the Local to Global extraction is shown below 259 MOSFET Models Notes Information Initialize Binning Extract Extraction Flow Data mo Reset Parameters andResults Global 2 Local Capacitance Cg
157. the Simulate command For more information refer to Transforms and Functions extractionandprog For more information on simulation refer to Simulation simulation Displaying Plots Plots can be displayed from the Plots folder for the setup To display plots issue the Plot Display command from a DUT to display the plots for all setups in that DUT The plots use the most recent set of measured and simulated data Viewing plots is an ideal way to compare measured and simulated data to determine if further optimization would be useful For more information on plots refer to Printing and Plotting printandplot Optimizing The optimization operation uses a numerical approach to minimize errors between measured and simulated data As with the other IC CAP commands optimization can be performed at either the DUT or setup level Optimization is typically interactive in nature with the best results obtained when you specify the characteristics of the optimization function For more information refer to Optimization optimization 380 MOSFET Models Extraction Algorithms This section describes the extraction algorithms for the classical narrow width short channel saturation region and sidewall capacitance extractions Classical Parameter Extractions This extraction calculates the classical model parameters UO VTO NSUB and UEXP from the ID versus Vg measurement at varying bulk voltages on a large device Select the gate voltage
158. the value of dotemp for any device is set to 1 then this device will be measured at temperature The devices setup contains the following transforms connect calls SWM_init and Connect to connect the matrix for a particular device or prompts you to connect the device It uses information contained in the outputs described for the setup devices dummy is an empty apart from comments PEL transform It was found that when a variable that affects the array size in any setup NUMDUT in this case is changed from a C transform then a call to a dummy transform is necessary to force IC CAP to re establish the proper array dimensions before attempting to write to these arrays extract single_ext contains the sequences for extracting the miniset parameters The variable table of this setup contains a list of MIN and MAX values for use in the optimization steps It is easier to modify the optimization limits from such a variable table rather than from the individual optimization transforms For the extraction of a miniset for any particular DUT this setup is first copied into the appropriate DUT The optimizations then operate on the miniset variables local to that DUT The single_ext setup contains the following transforms full_extract is the controlling PEL for miniset extraction For more information refer to the discussion on full_extract in the section Optimization Transforms and Macros mosfet par_init initializes parameter local variab
159. to Export or Import plot data Select a plot then choose Export from the Data Table area at the top of the plot window marked with a blue rectangle below Data Table Cycle Devices Cycle Plot Types All Diagrams Za 0000 V ug S6E0 mV w 1250 Viide110 1 nA n ae Bias Conditions SJH moaoonna oooooo0 Plot Type Temperature Master Setup 25 40 Idvd idvd v 125 m You will be prompted for a name of the table to be saved the file extension for this table will be txt This feature is useful to compare different settings of parameter for example If you ve saved a data table you can change a parameter value simulate the device Finetune This feature enables you to add customized optimization steps You can select one or more measured diagrams to create and save an extraction step in which to adjust certain parameters for a specific region of device behavior This step can be inserted into the extraction flow at any desired step in the extraction procedure To use the finetuning feature do the following Open a Data Display Select the desired Plot Types Devices and Bias Conditions to be displayed Activate a diagram Activate this diagram for optimization PO button to the right of the diagram Repeat the steps above for each plot you would like included in your finetuning step Open the Plot Optimizer right mouse button Optimizer gt Open Optimizer From the parameter list of the Plot Optimiz
160. to Y plots are displayed during measurement and optimizations Otherwise they are not unless they have previously been displayed and not closed The setup_details macro also calls the transform set_unit_dimensions which sets the dimensions in the analysis DUT to unity measure_cv This macro causes a measurement to be taken in the cv setups of the area locos and gate DUTs At the end of these measurements you are prompted to specify the following information CV_VMI_ The lower voltage limit for optimizations with respect to the C V data CV_VMAX The upper voltage limit for optimizations with respect to the C V data measure_forward_iv This macro causes a measurement to be taken in the fwd_iv setups of the area locos and gate DUTs At the end of these measurements you are prompted to specify the following information FIV_VMIN The lower voltage limit for optimizations with respect to the forward I V data FIV_VMAX The upper voltage limit for optimizations with respect to the forward I V data measure_reverse_iv This macro causes a measurement to be taken in the rev_ v setups of the area locos and gate DUTs At the end of these measurements you are prompted to specify the following information RIV_VMIN The lower voltage limit for optimizations with respect to the reverse I V data RIV_VMAX The upper voltage limit for optimizations with respect to the reverse I V data extract_cv_pars This macro controls the extraction of the C V param
161. used for later comparison with data predicted by the generated model It is not necessary to do the preverification measurement every time you perform a model generation especially if you are using a data sheet Device Configuration The input values you set in this procedure configure the device as shown in the following figure MOSFET Bias Configuration for DC Preverification Defining the DC Source Monitor Instrument State Follow the same process you used in the r_series measurement Use the same settings Then return to this section and continue Setting the idvd_vg Inputs 321 MOSFET Models This procedure defines the input signals to be applied to the device under test for the DC preverification measurement The actual settings you use will be dependent on the compliance limits for both the device and the SMUs bias networks and on the range of measurements you wish to take Since this measurement is intended only to preverify the device the values can be quite conservative and need not stress the device to the boundaries of its performance If you are measuring a series of devices of the same type and have already set the input parameters go directly to Measuring and Plotting Otherwise select the idvd_vg setup use the following settings as a guideline For the vd input Set To Mode V Compliance no greater than the maximum breakdown current value for the device Sweep Type _ LLIN to provide a linear voltage sweep from sta
162. user is able to change between model versions 1 21 1 22 or 2 01 Enhancements to the following features have been added Data Display e Refined selection of curve data e Organize plot location e Select devices improved usability e Switch all Plot Optimizers simultaneous on and off in a multi plot window Measurement Tool e Sort devices e New setups idvb idvs e Synchronized measurement input 370 MOSFET Models UCB MOS Level 2 and 3 Characterization This section provides information on the following topics e Introduction to UCB MOS Level 2 and 3 Characterization mosfet e UCB MOSFET Model Simulators and Model Parameters mosfet e MOSFET Test Instruments mosfet e MOSFET Measuring and Extracting mosfet e MOSFET Extraction Algorithms mosfet e HSPICE LEVEL 6 MOSFET Model mosfet References 1 A Vladmirescu and Sally Liu Simulation of MOS Integrated Circuits Using SPICE2 UCB ERL M80 7 University of California at Berkeley 2 HSPICE User s Manual H92 Release Meta Software Inc 1992 371 MOSFET Models Introduction to UCB MOS Level 2 and 3 Characterization This section describes the UC Berkeley MOSFET transistor model supported in SPICE Descriptions of model setup instrument connections and model parameters are included as well as test instrument information Information is included for making DC and Capacitance measurements and their corresponding extractions Note The HSPICE LEVEL 6 MOSFET
163. variations for DFM support not considered parameter variations for DFM support is considered Back to HiSIM2 and HiSIM_HV Characterization mosfet 239 MOSFET Models Modeled Device Characteristics of the HiSIM2 model In HISIM 2 4 0 the following device characteristics are included see HiSIM References 2 e Drain Current IDS o Short Channel Effect o Reverse Short Channel Effect impurity pile up and pocket implant o Mobility Models Universal High Field Quantum Mechanical Effect Gate Poly Depletion Effect Channel Length Modulation Narrow Channel Effect Temperature Dependency Thermal Voltage Band Gap ni Phonon Scattering Maximum Velocity o Pinch Off o Shallow Trench Isolation Threshold Voltage Mobility Leakage Current e Leakage Currents Modeled o IBS o IGate o IGIDL e Capacitances o Intrinsic o Overlap o Lateral Field Induced o Fringing e Junction Diodes o Current o Capacitances e Higher Order Phenomena o Harmonic Distortion o Noise Characteristics 1 f Thermal Induced Gate GIDL o Small Signal Analysis o Large Signal Analysis e Source Drain Resistances o e Back to HiSIM2 Characterization mosfet 236 MOSFET Models SPICE Model Parameters for the HiSIM MOS Model The following tables list the model parameters used in the HISIM MOS model with their default values and the possible parameter range A separate section shows additional and removed parameters u
164. way to do this is to model the OPEN and the SHORT device using the equivalent circuits given in Test_open and Test_short Physical Length Verification of the Through Test Structure 174 MOSFET Models Checking the physical length of the Through line involves a measurement of the phase angle between the input and output signal of the through Since it is assumed that the through line is designed to give a ZO of 50 Ohms as is used for RF measurements using a network analyzer the output and input signal amplitude are the same The S parameter measurement gives a phase difference between input and output signals Using the Smith diagram you can calculate the physical length of the through line between the pads using the phase difference of the signals This phase difference is calculated from 360 xL L length of the line distance between pads A wave length c speed of light 3 x 108m s C L 6 n Ao Since f the electrical length of the line is 360 f The formulas above are valid only for air as dielectricum since the velocity of the wave depends on the relative dielectric and permeable constants of the material Building standard test structures on silicon wafers using silicon dioxide as dielectric changes the propagation velocity of the waves from light speed c to c Y The constants for silicon and silicon dioxide are Material H E Silicon 1 11 8 Silicon 1 3 9 dioxide Typically the
165. which results are being used for the selected extraction step Now if you Add or Delete change the arrangement of the steps or reset to Defaults the following extractions will become invalid because they are based on the results of the extraction immediately before them Therefore you will be warned before changes are made J Invalid history and initial conditions Delete Extraction Capacitance Fringing and Overlap Changing this model extraction configuration will invalidate some previous results Therefore subsequent result files mps dps lib would be deleted or overwritten bsim4 _for_experts bsim4 _de_cv_extract bsim _for_experts bsim4_de_cv_extract global_03 bsim4 _Ffor_experts bsim4 _de_cv_extract global_04 bsim4 _for_experts bsim4_dc_cv_extract global_05 bsim4 _for_experts bsim4 _de_cv_extract global_06 bsim4 _for_experts bsim4_de_cv_extract global_O7 bsim4 _Ffor_experts bsim4 _de_cv_extract global_08 bsim4 _Ffor_experts bsim4_de_cv_extract global_09 bsim4 _Ffor_experts bsim4_de_cv_extract global_10 bsim4 _for_experts bsim4 _dc_cv_extract global_11 bsim _for_experts bsim4_de_cv_extract global_12 bsim4 _Ffor_experts bsim4_de_cv_extract global_13 bsim4_for_experts bsim4_dc_cv_extract global_14 bsim4 _Ffor_experts bsim4 _de_cv_extract global_15 bsim4 _for_experts bsim4_de_cv_extract global_16 bsim4 _Ffor_experts bsim4_de_cv_extract global_17 bsim4_for_experts bsim4_de_cv_extract global_18 h
166. with an analytical equation excluding the inversion charge Qover is calculated with an iterative procedure including the inversion charge Qover is calculated with an analytical equation including the inversion charge HV 1 1 1 original no overlap charges capacitances are added to intrinsic ones overlap charges capacitances are added to intrinsic ones constant overlap capacitance bias dependent overlap capacitance model at drain side constant overlap capacitance bias dependent overlap capacitance model at source side no self heating self heating considered no substrate current calculated substrate current is calculated no gate current gate current is calculated no GIDL current GIDL current is calculated no STI leakage current STI leakage current is calculated no quasi static mode quasi static mode is invoked gate contact resistance not included gate contact resistance is included no substrate resistance network included substrate resistance network is invoked no 1 f noise calculated 1 f noise is calculated no thermal noise considered thermal noise is calculated RD T 0T RDVD VMAX NINVD TO RD RDVD VMAX NINVD TO RD RDVD VMAX NINVD T 0T RD RDVD T 060T VMAX NINVD TO and COTHRML O no induced gate and cross correlation noise and COTHRML 1 ind gate and cross corr noise are calculated previous calculated lt is not used for next iteration previous calculated is used for iteration parameter
167. you use your own circuit files it is recommended to copy the entire examples directory into a directory where you have write access and set the path according to your situation You will find the path to the examples directory on the options folder If you are satisfied with the default settings or to use as a starting point just leave the path entries as provided There is a field to enter the printer command for printing the plots see the notes on printing in the section DC and CV Measurement mosfet If you want to change the plot window size choose Use X Y Plot Size Fixed_Plot_Size and enter the desired X and Y size into the respective fields You are able to change the background color of the plot window from black to white by activating the field White background of plots Circuit Files The circuit files are located in ICCAP_ROOT example model_files mosfet bsim3 or bsim4 or psp circuits You will find subdirectories below the circuits directory for each supported simulator hpeesofsim hspice spectre spice3 Each directory contains a circuit cir as well as a test circuit tci directory which contain the circuit files using the appropriate simulator syntax 113 MOSFET Models Related Topics RF Extract Notes mosfet RF Extract Information mosfet RF Initialize mosfet RF Extract mosfet RF Display mosfet RF Extract HTML mosfet RF Extract Boundaries mosfet Back to Extraction of Parameters for t
168. you want to retain this filename select OK or press Enter Otherwise change the name to a new filename that associates this model with the device retaining the suffix mds for compatibility with MDS Note If you plan to do a verification retain the filename State mds for now as the verification process requires this filename You will have another opportunity to change the filename after the verification process 3 The model generation takes a few seconds A Done message in the UNIX window indicates the model generation is complete Generating a Model from Previously Measured Data If you wish to generate a model from a previously stored measurement you will need to perform these additional steps to bring the data into this model in the correct form 1 From the IC CAP Main window select File gt Change Directory Type in the path name of the file where your data is stored and select OK 2 Select the create_mdl setup 3 Select compute_para gt Execute 4 Now perform the standard procedures described under Setting the Starting Point for Contour Integration and Executing the Model Generator Transform 340 MOSFET Models Note To plot the data note the extra steps described under To Plot an Earlier Data Acquisition Plotting the Generated Data In the create_mdl setup the Qg and Qd plots show the calculated state function data generated by the model_generator transform Note The modeled state function d
169. 0 Ohm RBDBYO Scaling prefactor for RBDBY 100 0 Ohm RBSDBXL Length scaling parameter for RBSBX and RBDBX 0 RBSDBXW_ Width scaling parameter for RBSBX and RBDBX 0 RBSDBXNF Number of fingers scaling parameter for RBSBX and RBDBX 0 RBSDBYL Length scaling parameter for RBSBY and RBDBY 0 RBSDBYW__ Width scaling parameter for RBSBY and RBDBY 0 RBSDBYNF Number of fingers scaling parameter for RBSBY and RBDBY 0 Layout Dependent Parasitics Model Parameters Layout Dependent Parasitics Model Parameters Parameter Description Default Unit Value DMCG Distance from S D contact center to the gate edge 0 0 m DMCI Distance from S D contact center to the isolation edge in the channel length DMCG direction DMDG Same as DMCG but for merged device only 0 0 m DMCGT DMCG of test structures 0 0 m NF Number of device fingers 1 0 DWJ Offset of the S D junction width in CV model DWC MIN Whether to minimize the number of drain or source diffusions for even number fingered 0 0 devices XGW Distance from the gate contact to the channel edge 0 0 m XGL Offset of the gate length due to variations in patterning 0 0 m XL Channel length offset due to mask etch effect 0 0 m XW Channel width offset due to mask etch effect 0 0 m NGCON Number of gate contacts 1 0 Model Selection Flags Model Selection Flags 226 Parameter LEVEL VERSION BINUNIT PARAMCHK MOBMOD RDSMOD IGCMOD IGBMOD CAPMOD RGATEMOD RBODYMOD TRNQSMOD ACNQSMOD FNOIMOD TEMPMOD TNOIMOD DIO
170. 0 flat bans shift for gate to bulk current m V 1 GLPART1 0 5 0 0 1 0 partitioning ratio of gate leakage current FN1 50 first coefficient of Fowler Nordheim current VA 1 54 m2 contribution 170E 6 second coefficient of Fowler Nordheim current a 0 5 m contribution coefficient of Fowler Nordheim current contribution F FVBS 1 12E 3 Vbs dependence of Fowler Nordheim current p GIDL Current Parameters 241 MOSFET Models Parameter Default Range a Description Unit Name min GIDL1 magnitude of GIDL A A V4 3 24 C4 14 m GIDL2 field dependence of GIDL VA 2A A mMA LAFA 7 3 2 GIDL3 oe Vds dependence of GIDL p GIDL4 threshold of Vds dependence t poe 0 2 correction of high field 2 Grane Conservation of the Symmetry at Vds 0 for Short Channel MOSFETs Parameters Parameter Name Default Range min Range max Description Unit aa 10m symmetry conservation V coefficient paa 5m symmetry conservation V coefficient Smoothing coefficient between linear and saturation region Parameters Parameter Name Default Range min Range max max Description Unit DDLTMAX 0 0 20 0 0 smoothing coefficient for Vds perce g 0 20 0 Lgate dependence of smoothing coefficient pa f Lgate dependence of smoothing pes coefficient Source Bulk and Drain Bulk Diodes Parameters Parameter Default Range Range Description Unit Name min max pee m n current density m 2 poe i pe saturation current densit
171. 0 p f STXCOR L Temperature dependence of 0 XCOR STXCORO G Temperature dependence of 0 XCOR FETA IL Effective field parameter E 1 0 FETAO lG Effective field parameter E 1 f Series Resistance Parameters i e al series resistance at 30 j i RSW1 Source rain series resistance for 2500 channel width WEN at TR RSW2 Higher order width scaling of i i i source drain series resistance Is STRS Lo Temperature dependence of RS p STRSO Temperature dependence of RS R p RSB L Back bias dependence of RS V 1 0 5 1 RSBO fe Back bias dependence of RS V 1 p RSG IL Gate bias dependence of RS V 1 p 0 5 RSGO lG Gate bias dependence of RS Vv 1 p p Velocity Saturation Parameters THESAT L Velocity saturation parameter at WV 1 1 0 TR THESATO G Geometry independent velocity V 1 0 saturation parameter at TR THESATL lG Length dependence of THESAT Vv 1 0 05 p THESATLXP G Exponent for length dependence 1 of THESAT THESATW lG Width dependence of THESAT 0 f p THESATLW G Area dependence THESAT p 0 p STTHESAT L Temperature dependence of 1 THESAT STTHESATO G Geometry independent 1 temperature dependence of THESAT STTHESATL lG Length dependence of STTHESAT 0 STTHESATW lG Width dependence of STTHESAT 0 p p STTHESATLW lG Area dependence of STTHESAT 0 p pee i cae dependence of velocity 1 0 k h satu
172. 00 0 m cox m 82 01p 250 W Coo VZDALI 4 F20 ie ZOD l ToD re 00 C_Oxidefcg_va Cox_vq C_Oxide cg_va Cox1 C_Oxidefcg_va Cox1 C Use Plot in Optimizer Show Region in Plot Calculation of Default Region Vgb E 0 Vgb E 0 0 You can add any of the Available Extractions to the Default Extraction Flows to the right of the tab ar Default Extraction Flows marked Factory Flow cannot be modified Instead copy a factory flow and add the groups and functions to the copied extraction flow Available Extractions and Default Extraction Flows Available Extractions Overview Customized Functions Easy Functions E NEFF copy New Main Group New Group O TOXO NSUBO FBO DLQ Global Capacitance Oxide Fu The new default flow can be modified The Available Extractions defined on the first tab are shown on the left side of the window For each optimizer a tuner will be inserted Copy the previously created Customized Function into the new flow by selecting the function on the left side of the tab and copy it to the right side using the arrow Adding a customized function to the Default Extraction Flow st Configuration Wizard for Extraction Functions 12 Configuration Edit Options Help BAHE Available Extractions Overview Customized Functions Default Extraction Flows Available Extractions Default Extraction Flows O Global wi Global Facto
173. 0m 42 74m 200 000m UA 1 00000u 160 3p 1 00000u uc 100 000m 62 42m 100 000m UB 1 00000p 5 608E 0 1 00000p DELTA 1 00000f 10 00m 1 00000M 1 00000f 1 00000M_ d2id_dvg m s E 6 flee _ 3 mM gt o Save actual Optimizer Min Max values _ an A and use them instead of the global Min Max values 20 1 0 0 5 0 0 0 5 1 0 1 5 20 vg E 0 Extraction Step Large Basic Vth Mobility Function O UO UA UB EU UC Save Starting Values gt Saving the Changes Go to the main window select File gt Save As and save the mdl file under a new name into a user directory The path may not include spaces Use this file for future parameter extractions Do not rename the model file as it is displayed in the main window A renamed file cannot be opened since the program requires a standard file name to be used in the IC CAP main window The model name has to be XXX_DC_CV_Extract where XXX defines a place holder for BSIM3 BSIM4 PSP HiSIM The model file name to be saved may be different 78 MOSFET Models Defining Extraction Functions Experienced users would like to implement their own extraction functions which they found to give good results for a specific semiconductor process Note This is recommended only for users who are familiar with the PEL language in IC CAP We will provide the basics of implementation using an example PEL program The program definitions an
174. 1 0 Wgate dependence of SVGS p Subthreshold Swing Parameters Parameter Name Default Range min Range max Description Unit PTHROU 0 0 50m correction for subthreshold swing Impact ionization induced Bulk Potential Change Parameters Parameter Name Default Range min Range max Description Unit m 0 i ka impact ionization induced bulk potential gi change IBPC2 0 0 1 0E12 impact ionization induced bulk potential V change 1 Gate Leakage Current Parameters Parameter Default Range Range Description Unit Name min max GLEAK1 50 gate to channel current coefficient A V 3 2 C 1 m ie gate to channel current coefficient a 1 2 m GLEAK3 6 60E 3 lg ate to channel current coefficient i GLEAK4 4 0 gate to channel current coefficient maA 14 ae gate to channel current coefficient short channel V m 1 correction P lt m gate to channel current coefficient Vds V dependence correction pisa a gate to channel current coefficient gate length m and width dependence correction EGIG 0 0 temperature dependence of gate leakage Vv IGTEMP2 0 temperature dependence of gate leakage VK IGTEMP3 0 temperature dependence of gate leakage V K2 GLKSD1 laf g ate to source drain current coefficient A m V4 24 pears Pee ae to source drain current coefficient A 1 m GLKSD3 5E6 g ate to source drain current coefficient ae GLKB1 5E 16 gate to bulk current coefficient AVA 24 GLKB2 1 0 gate to bulk current coefficient m VA 14 GLKB3 1
175. 1 IJTH 0 1 CJ 5e 4 MJ 0 5 PB 1 CUSW 5e 10 MJISW 0 33 PBSW 1 CUSWG 5e 10 MISWG 0 33 PBSWG 1 CGDO 0 CGSO 0 CGBO 0 CGSL 0 CGDL 0 CKAPPA 0 6 CF 0 NOFF 1 VOF FCV 0 ACDE 1 MOIN 15 DLC 0 DWC 0 LLC 0 LWC 0 LWLC 0 WLC 0 WWC 0 WWLC 0 CLC 0 1e 6 CLE 0 6 ELM 2 XPART 0 5 KT1 0 11 KT1L 0 KT2 0 022 UTE 1 5 UA1 4 31e 9 UB1 7 6e 18 UC1 5 6e 11 AT 3 3e4 PRT 0 XTI 3 0 TPB 0 TPBSW 0 TPBSWG 0 TCJ 0 TCJSW 0 TCUSWG 0 AF 1 5 EF 1 5 KF te 17 EM 4 1e7 NOTA 2e29 NOIB 5e4 NOIC 1 4e 12 LINTNOI 0 Additional model parameters necessary for scalability scalable external capacitors taking into account cross coupling between metal lines and inductors to account for delay effects due to the size of the devices scalable channel length reduction in multi finger devices a scalable substrate network and scalable Delta L reduction CGDEXT0 1te 9 external capacitance gate drain per gate width and gate finger F m CGSEXT0 1te 9 external capacitance gate source per gate width and gate finger DEAM CDSEXT0 1e 9 external capacitance drain source per gate width and gate finger Ps i RSHG 25 gate sheet resistance Ohm sq LDRAINO 1e 6 245 MOSFET Models drain inductance per gate width and gate finger H m LGATE0 1e 6 gate inductance per gate width and gate finger H m L SOURCE0 1e 6 source inductance per gate width and gate finger H m BULKO 1e 6 bulk inductance per gate width and g
176. 12 1 4E12 EM Saturation field 4 1E7 V m AF Frequency exponent 1 a E EF Flicker exponent 1 KF Flicker noise parameter 0 IL LINTNOI Length reduction parameter offset 0 m Non Quasi Static Model Parameters Parameter Description Default Value Unit ELM Elmore constant of the 5 i channel Model Selection Flags 164 MOSFET Models Parameter Value Type of Model LEVEL 8 BSIM3v3 model selector in UCB SPICE MOBMOD 1 Mobility model INQSMOD k Non quasi static model a ACNQSMOD 0 introduced from BSIM4 a NOIMOD 1 Noise model i new thermal noise SPICE2 flicker noise 6 new thermal noise BSIM3 flicker noise User Definable Parameters Parameter Description Default Value Unit XPART Charge partitioning coefficient 0 p DELTA Parameter for smoothness of effective Vas 0 01 calculation Additional Parameters needed for accurate RF modeling RF Parameters for the RF subcircuit Parameter Description eraut Value m RSHB bulk sheet resistance square distance between gate stripes 2 2E 6 im oes o o distance source to bulk contact l2 2E 6 im DDCB distance drain to bulk contact 2E 6 im RBDB resistance between bulk connection point and drain 100 a RBSB resistance between bulk connection point and source 100 a RBPD resistance between the region below the channel and the drain region 100 a p resistance between the region below the channel and the source
177. 16 1E19 oO 0 0 0 0 0 1 0 1 0E 6 1 0E 6 Small Size Effect Parameters MOSFET Models Description threshold voltage change due to capacitance change threshold voltage shift modification of pocket concentration for narrow width modification of pocket concentration for narrow width phonon related mobility reduction phonon related mobility reduction change of surface roughness related mobility change of surface roughness related mobility threshold voltage shift due to STI Vds dependence of STI subthreshold the same effect as SC1 but at STI edge the same effect as SC2 but at STI edge substrate impurity concentration at the STI edge width of the high field region at STI edge channel length dependence of WSTI channel length dependence of WSTI channel width dependence of WSTI channel width dependence of WSTI threshold voltage shift of STI leakage due to small size effect threshold voltage shift of STI leakage due to small size effect pocket concentration change due to diffusion region length between gate and STI pocket concentration change due to diffusion region length between gate and STI pocket concentration change due to diffusion region length between gate and STI mobility change due to diffusion region length between gate and STI mobility change due to diffusion region length between gate and STI mobility change due to diffusion region length between gate and STI reference length o
178. 2 NoOwnGroups 2 and delete the third user defined function Assign an unique ID for the new extraction group MyExtrGroup_ID ptrGr Customer_GO1 Assign a name which is displayed in the GUI MyExtrGroup_Name ptrGr My C_Oxide Extraction o Assign the main group Either AdMOS_3_M0O1i for the main group Global or AdMOS_3_ M06 for the main group PSP Scaling MyExtrGroup_Main ptrGr AdMOS_3_M0O1 Functions o In BSIM3 only the main group AdMOS_1_ M01 and in BSIM4 only the main group AdMOS_2_ M01 can be used e Define the function of the new extension groups This functions are shown in the window Available Functions of the GUI when assigning this extraction group MyExtrGroup_Func ptrGr ICCAP_ARRAY 2 MyExtrGroup_Func ptrGr 0 USER_001 Optimizer MyExtrGroup_Func ptrGr 1 USER_OO1T Tuner Each optimizer can be used as a tuner as well by adding a T to the ID Define the default function flow This functions are shown in the window Function Flow of the GUI when adding this extraction group MyExtrGroup_Def ptrGr ICCAP_ARRAY 2 MyExtrGroup_Def ptrGr 0 USER_001 MyExtrGroup_Def ptrGr 1 USER_OO1T e User defined extraction step in the GUI m PSP_DC_CV_Extract 30 MER File Jnitialize Binning Extract Plots HTML Qptions Boundaries Help He i ed I a Notes Information Initialize Binning n a Extract HTML Options Boundaries Extraction Flow Extrac
179. 3 gt a Gi p a 4 o v 118 of wo mo oO gt a o oO wo o o gt oo p Fas WwW wo o 2 i A si a v 2 S Draw a rectangle for each bin and press the button Set Bin 299 MOSFET Models 48 Devices 17 File Options Optimizer Windows Help M 0 dummy _input 0 000 Y X 5 000u Available_Real_Devices 5 000u 1E 5 ay a 1E 6 L m LOG Availlable_Real_Devices Ext Devices Bin Devices Selected Devices Remember Bins must include devices at each corner of the bin otherwise you ll get an error message Press Set Bin after each selecting rectangle The devices selected for binning will be listed inside the Binning Area of the folder 45 BSIMSOI4_DC_CV_Extract 16 File Initialize Binning Extract Plots HTML Options Boundaries Tools Help r a f a e s K G SESS SS cGHHUXE BIA aa G Notes Information Initialize Binning Extract HTML Options Boundaries E Tolerance of Binning Area um Extension um Parameters to switch off scalable effects Show Devices L min direction L min direction 0 14 DUG W min direction rarer L max direction W min direction 0 16 DWB W max direction 0 005 L max direction 10000 Delete all Bins W max direction 10000 Binning 4rea Binning Area Tolerance Name Change Tolerance Binning 4rea Extension Add Extension Delete Extension Project bsimsoi _binne
180. 5 0 35 0 5 07 1 10 LENGTH DUT Name W um L um Category Large m fio fio Large OK Perform Auto Set and select Large_m as the Large Transistor inside the Set Category window 184 MOSFET Models Now the size categories are defined automatically and the resulting DCTransistorDUTs folder is shown in the following figure DC Transistor DUTs folder after successful set size categories BSIMS_DC_ V_ Measure eed 3 i New Open S me i Delte i Tugg Pint Help indo Doma impot BSIMI03 Notes Measurement Conditions Tenpe wie Sep SwichMaik DE Transistor DUTs Capackaree DUTe DE Diode DUTa Options DUT 0 w L AD AS PO PS NF Comment Size Selig si K im fu fma fuma f um Category ea Lage m S M w 0 U 0 2 R 1 Luge Narrow m M 04 10 04 N4 28 28 1 Narrows DUTs Naron mi M 0 8 10 08 18 36 3 6 1 W Scale Add Naron m2 M 12 10 1 2 1 2 44 aa 1 W Scale Shoil_n M 10 03 10 0 2 2 Shot Delle i x n Shatt_nl M w os mw 10 2 1 L Sese MELT Shatt_n2 M w as 9 0 2 1 LSede f Skond M w ar mw 0 2 1 LScse Size anpoy Skait_nd M 10 1 10 10 22 22 1 LSede Smal_n M 04 O28 of d4 26 20 1 Sma E Smal_ni M 08 a o8 no 36 3 1 LW Scale Display i Smal_n2 M 12 QB 12 12 44 44 4 LW Scale Sat You can now Save the project and proceed as you would with measured project data Hints If you do not have such clearly defined test structures at hand you may have to select the size category manually The following example demons
181. A1 bin N_W30n0_L5u0_SA1 Special extractions for Long Wide devices When selecting the Long Wide device the Function Flow to the right of the Extract folder shows special optimizations for the Long Wide device 269 MOSFET Models Short Wide device Binning Entraction Intermediate Results IP Function Flow N Wa I IL Nal 0 4 10u0 Special extractions for Short Wide devices In this case the Short Wide device was selected and the Function Flow shows optimizations especially for Short Wide devices All other devices Extraction Intermediate Results P Binning ELFE m Function Flow biri W N W00 LESNO SA10u0 bin N bin N Common extractions for all devices The extraction Ca culate Binned Model creates a binned circuit which depends on the devices selected in bins As soon as this circuit is created it is loaded inside the extraction flow after that function and the HTML report is created using the circuit If you change the position inside the extraction flow to one created before binning was started for example in using the test mode at that position the regular circuit not the binned one will be loaded e Back to PSP Characterization mosfet 270 MOSFET Models Parameters for the PSP model This section lists the parameters used for the PSP model together with a description of their meaning as well as the default
182. Add icon and select the type of pad by clicking Open Short or Through on the appearing window see below A new line will be inserted inside the field Pad Structures You can change the name of the dummy pads as you like The following rows are showing the status not measured showing 0 measured showing M or not applicable showing as well as a user comment The Data gt Measure menu is used to perform the measurement of the defined pads Or you can press the Measure icon and select the pad you would like to measure in the appearing Measure form before clicking Measure DUT After the measurement has been performed plots can be displayed using the appropriate icon or menu function so that the measured results could be checked for plausibility of the measured data Click the Close Plots icon to close the displayed plots of measured pads You can view the measured pad data at any time after a measurement has been performed by clicking Display Plots under the Data menu or the appropriate icon then selecting the pad to be displayed The data will be displayed on Smith charts and can be closed using the Close Plots icon or the Data menu If you have chosen to perform a Verification of de embedding by activating the Perform Verification of de embedding Using check box on the top right part of the folder the field De embedding Sets is being activated and you are able to configure the sets for use within the DUTs folder Save the se
183. BS id The current output from the vd terminal The variables VDS VGSO VGS1 VGS2 and VBS are setup variables and are set automatically by the function MM9_LIN_EXT The in_quick_ext setup contains the following transforms mm9_ids calls the MM9 transform for current simulation 351 MOSFET Models copy_ids allows current to be copied from mm9_ids to id m set_dimensions sets the dimension information in the quick_ext DUT from the information in the extract devices arrays linear_extract calls the linear region extraction functions quick_measure used by MM9_LIN_EXT to initiate measurements If the variable DATASOURCE is set to M then real measurements are to be performed If not then it is assumed that measurements are being made using an ideal miniset This causes a little confusion because the quick extraction changes the miniset parameters as it proceeds Thus the ideal miniset parameters and the quick extraction miniset parameters have to be used appropriately Some transforms in the setup store are used to achieve this par_init_quick_ext sets initial values of ETAGAM and ETAM quick_ext svt_quick_ext used during the extraction of the subthreshold region parameters It contains input definitions for the bias voltages vd vg vs and vb as well as the definition for the current to be measured id The svt_quick_ext setup contains the following inputs and outputs vd A constant value set by the variable VD vg A constant va
184. BSIM3v3 model suggest to use a parameter LINT for the I V model which is different from DLC other literature sources References and Copyright Information mosfet 3 propose that LINT should have the same value as DLC This approach is also implemented in the BSIM3v3 Modeling Package to ensure that the extracted values of the channel length reduction are very close to the real device physics Therefore the channel length reduction LINT for the I V model will be set to DLC from the C V model extracted from capacitance measurements b Intrinsic Capacitance Model The intrinsic capacitance model that is implemented in the BSIM3 model is based on the principle of conservation of charge There are a few major considerations in modeling the 144 MOSFET Models intrinsic capacitance of a deep submicron MOS transistor e The difficulty in capacitance measurement especially in the deep submicron regime At very short channel lengths the MOSFET intrinsic capacitance is very small while the conductance is large e Charge can only be measured at high impedance nodes i e the gate and substrate nodes only 8 of the 16 capacitance components in an intrinsic MOSFET can be directly measured An alternative solution is to use a 2 D device simulator e The access to the internal charges in a simulator Therefore this section presents no details about the intrinsic charge formulations Please refer to the BSIM3v3 manual References and Copyright Inf
185. CE MOS LEVEL 7 model provided that the PHI parameter is set to PHI 2 following the extraction Note Set the SIMULATOR variable to your version of HSPICE after loading the hnmos6 md configuration file into IC CAP Refer to Simulation simulation for additional details on using HSPICE Model Parameters The parameters used in the hnmos6 md example file are listed in the following table Six switch parameters are selected in the supplied configuration The fixed parameter values are based on typical MOSFETs they may need to be altered for certain devices An important feature of the HSPICE LEVEL 6 model is its multi level Gamma capability IC CAP extraction routines support both single and multi level Gamma parameters extractions If VBO is set to 0 before the Large IdVg extraction only GAMMA is extracted Otherwise GAMMA LGAMMA and VBO are extracted Optimization is necessary with the LEVEL 6 model for optimum agreement between measured and simulated data The IC CAP Setup attributes for the LEVEL 6 model are listed in HSPICE LEVEL 6 Model Setup Attributes HSPICE LEVEL 6 Parameters used in hnmos6 mdl Switch Fixed Parameters Extracted Parameters Parameters UPDATE 1 BULK 99 KU ACM 0 FDS 0 9 MAL CAPOP 4 LATD 0 2 MBL MOB 1 ESAT 86 0E3 PHI CLM 3 KL 0 05 VT WIC 1 KA 0 97 GAMMA VSH 0 7 LGAMMA Optional KCL 1 0 VBO Optional MCL 1 0 F1 LAMBDA UB TOX Input F3 Parameter L Input Parameter
186. Capacitance Cog Capactance Oude PSP Scale Short Dependence Width Dependence C tance Overlap Global Optimizabons PSP Scale Long Width Dependence STI Stress Effect PSP Scale Length Width F PSP Scale Length Dependence Wide Global Local Calculate Birmed Model metung Capactance Junction F My C_Oxide Extraction y Scale Exttacton Group Saving and Restoring Changes after an Update Save Changes Change to the main window select the menu file and than Save As Save the mdl file under a new name in a user directory not in the IC CAP install directory The path may not include a space Use this file for future parameter extraction Do not rename the model name as displayed in the main window Restore Changes after Update After an update to a newer version of the modeling package you should use the new model files as basis To resume the user defined additions in the new model file go through the following steps e Open the user defined model file in the main window and rename it e Do not save this model when its name is changed It wouldn t work Open the new model file model_files mosfet PSP PSP_DC_CV_Extract mdl from your ICCAP example folder and edit both model files Copy the user defined setups to the new model file In the Example copy setup PSP_DC_CV_Extract_635102 Scaling User_execute to DUT PSP_DC_CV_Extract Scaling and PSP_DC_CV_Extract_635102 C_Oxide User_cg_vg to DUT P
187. Channel Length and Width Effective channel length and width are modelled the same way as in BSIM3v3 see Effective Channel Length and Width mosfet Single Equation for Drain Current The drain current is represented in BSIMSOI through a single equation in all three areas of operation sub threshold linear and saturation region Due to this single formula all first order derivatives of the drain current are continuous This is important for convergence in analog simulations Drain Saturation Voltage Vdsat The drain saturation voltage is divided into two cases the intrinsic case with Ry 0 and the extrinsic case with Ry gt 0 Those cases are explained inside the BSIM3v3 documentation Refer to Drain Current mosfet Effective Bulk Charge Factor When the drain voltage is high combined with a long channel length the depletion depth of the channel is not uniform along the channel length This will cause the threshold voltage to vary along the channel length this effect is known as the bulk charge effect Parasitic Resistance As MOS devices are scaled into the deep sub micron region both the conductance g and the current of the device increase Therefore the voltage drop across the source and drain series resistance becomes a non negligible fraction of the applied drain source voltage Early Voltage The drain current in the saturation region of sub micron MOSFET s is influenced by the effects of channel length modulation CLM
188. Cref value Power Compliance PC PCref 1E 6 wium PC M W Ldrift PCref The Safe Operation Area is the region of the Id vs Vd diagram which is safe for the transistor to be operated in This means the maximum allowable power consumption of the transistor will not be exceeded During measurement of a transistor the power delivered to the transistor will be calculated by multiplying Vd with Id This value will be compared to the PC value entered or computed ub 5 0 a E 2 1 0 vd E 0 Inside the diagram the safe operation area is marked using the red line As you can see measurements using values to the right of the SOA line will not be performed DC The Measurement Data tree uses setups to define different measurement configurations For compatibility reasons with former versions of IC CAP there are two basic setups provided One called idvg for measuring the drain current dependency from the gate voltage of the device e g transconductance of the device The other one called idvd for measuring the drain current dependency from the drain voltage the so called output characteristics of the device e idvg Transconductance I f V This part of the measurement conditions is designed for transfer diagram measurements Again there is a choice between a Linear sweep and a List of discrete voltage values where you can enter a number of points and their respective value For Linear sw
189. D 0 The Initial Values section of the folder contains fields for Model Parameters and Model Flags Into the field Model Parameters enter process related parameters like oxide thickness TOX or doping concentrations channel doping concentration NCH respective gate doping concentration NGATE and so on Entering values into the fields and selecting Save starts a routine to check the values entered This routine will flag an error message and change the color of the field whose parameter is given an unrealistic value The specific field will be marked with red color and remains red until the value is corrected The Model Flags section is used to set BSIM3 model flags There are fields for global model flags like BINUNIT or PARAMCHK as well as fields for DC Capacitance and Noise model 103 MOSFET Models flags The model flags are set to a default value as has been described in the BSIM3 manual from UC Berkeley 1 See Model Selection Flags mosfet for details or the above mentioned UCB manual 1 If you are using HSPICE a field is provided to set parameters for Gate current extraction A section called Initial Parameter Set is located below the Initial Values section You can use a parameter set from any other extraction with IC CAP a circuit simulator cir file or a text model file Using the cir or model file requires you to specify an appropriate simulator You enter the required information using the menu Initi
190. DVDSUB 1 0 Vds dependence of depletion width p RDVSUB 1 0 Vsub dependence of depletion width DDRIFT 1 0E 6 Depth of the drift region m NSUBSUB 1 0E15 Impurity concentration of the substrate p The following parameter settings are used to prevent the modeling of some effects 251 Effect to be excluded Short channel effect Reverse short channel effect MOSFET Models Parameters and Settings SC1 SC2 SC3 0 LP 0 Quantum mechanical effect QME1 QME3 0 Poly depletion effect PGD1 PGD2 PGD3 0 Channel length modulation CLM1 CLM2 CLM3 0 Narrow channel effect WFC MUEPHW WLi 0 Small size effect WL2 0 Model Flags Default values are in bold Flag Name COSYM CORSRD COQOVSM COADOV COOVLP COOVLPS COSELFHEAT COISUB COIIGS COIGIDL COISTI CONQS CORG CORBNET COFLICK COTHRML COTEMP COIGN COPPRV CODFM Values Description uneoro I m N a O Borg wWwnrnNrFO lrodordod irdoderordrdodro rdordo rd rvFrao rFO FO 0 1 asymmetrical LDMOS structure HV MOS structure no contact resistance RS and RD RS RD 0 internal resistance nodes RD 0 analytical description RD 0 both internal nodes and analytical description RS RD 0 external resistance nodes Qover is calculated with an analytical equation excluding the inversion charge Qover is calculated with an iterative procedure including the inversion charge
191. E Optimizer Tuner NEF E 1 00000E 02 8 43068E 023 1 00000E 02 BETN p 7 0008 37 99m 15 00 THEMU E 0 000 1 864 20 00 If you change one of the local parameters you will see its influence on electrical device behavior for the selected device The following figures show for example the global 265 MOSFET Models influence of the parameter NEFF changed using a local device The first value shows a good agreement between the global influence and the value of the local parameter left plot By changing the local value for NEFF the plot to the right shows a different behavior for this value marked by a red arrow NEFF Lscale NEFF Lscale KEFA ets Loun E oo oo REPT HET as LoP Fi oo oo 05 0 4 1E 16 7 16 6 16 5 1E 8 1E 7 1 6 16 5 Ldes LOG Ldes LOG Using this feature it is easy to see influences from local parameters to global behavior On the other hand it is possible to calculate local parameters from global behavior At the bottom of the Local Extractions folder is a button marked G gt L Using this button parameters for the selected local device are calculated by scaling the global model The difference is that this is not an extraction from measured local device data but a calculation of the local parameters from the global behavior which is what local parameters should be in order to have good agreement between local and
192. E AB junction area LS STI edge part of the junction perimeter LG gate edge part of the junction perimeter Note Since the transistor width W is not available at the local level an additional parameter for the junction width JW is necessary for SWJUNCAP 3 or 4 This parameter replaces WE in the table above Since PSP uses a hierarchical approach parameters are used inside the local the global or both models For this reason the following tables have a column for parameters of the local model and one column for parameters of the global model Under the column for the local model only parameters used inside the local model are listed The global model column lists global model parameters only If you are extracting parameters just fora local model e g for one geometry exactly only the parameters in the first column are needed for this task But if you are extracting a global model the parameters inside both of the columns are relevant This is because you can use a local model separately but a global model always needs local models The table is organized in a way that you can see the relations of the parameters For example you will find a parameter called VFB flat band voltage in the local level column under the process parameters section of the table The field at the global level beside this entry is empty Beneath the VFB entry the fields of the local level column are empty But 211 MOSFET Models there a
193. EPLD 0 NDEPW 0 NDEPWP 1 0 NINVD 0 Narrow Channel Effect NSUBCW 0 NSUBCWP 1 0 NSUBCW2 0 NSUBCWP2 1 0 NSUBCMAX 5E18 NSUBPW 0 NSUBPWP 1 0 MUEPWD 0 MUEPHW2 0 MUEPWP2 1 0 VGSMIN 5 n type 5 p type SC3VBS 2 5 removed INSUBPO 0 INSUBWP 1 Diode TCIBD 0 TCIBDSW 0 TCIBDSWG 0 TCIBS 0 TCIBSSW 0 TCIBSSWG 0 Noise FALPH 1 0 Capacitance QYRAT 0 5 Bypass Option BYPTOL 0 Bypass Option removed GLPART1 0 5 FN1 50 FN2 0 017 FN3 0 IF FVBS 0 0 012 Back to HiSIM2 and HiSIM_HV Characterization mosfet MOSFET Models 244 MOSFET Models RF Circuit used for HiSIM2 The following listing represents a scalable HiSIM2 NMOS transistor used for RF extraction complete with extensions to account for parasitic capacitances arising from metal crossovers and inductors to account for device size Scalable subcircuit model for hsim2 4 0 RF n type devices Simulator Agilent Advanced Design System Model hsim2 Modeling Package Date 11 04 2008 lt Origin ICCAP_ROOT hsim2 circuits hpeesofsim cir rf_nmos_scale cir Information for model implementation In ADS call the sub circuit model as follows with the actual values of L W etc hsim2_RF_Extract x_rf_transistor n1 n2 n3 n4 tmp_1 0 25u tmp_w 80u Please note The parameters tmp_w tmp_ad tmp_as tmp_pd tmp_ps tmo_nrs tme_nrd always define the TOTAL width drain area number of dra
194. ER 3E16 FE NOVERS 0 lem 3 VFBOVER 0 5 Vv CVDSOVER o 0 1 0 For modifying Cag spikes Qovsm 0 2 For smoothing of Qover LDRIFT1 lo Length of the lightly doped driftregion m o LDRIFT2 1E 6 Length of the heavily doped drift region mo o LDRIFTIS 0 Length of the lightly doped driftregion im LDRIFTIS 1E 6 Length of the heavily doped drift region m RDVG11 loom a e E RovGi2 000 RDVD e2 foo O OwA Rovs b Po ooo DoS o S Eo Ros bo To O Po Do S Eoo Rose Woo ooo Po ooo S Eoo Rovot b oZ Po Doo S Eoo Rovor Wo Poo DoS o S Eo o Rovos b oOo DS s S Eoo Rovose tt S S S oO Rozo b o Z Po Do S Eoo Rozi Wo Poo Po ooo S Eoo m RD22D 0 0 2 0 RD23 0 5 c RD23L 0 RD23LP 1 RD23S 0 rr o RD23SP 3 3 33 nia RD25 0 RDOV11 0 cover dependent reatence Lover dependent resistance RDOV12 1 0 L Lover dependent resistance RDOV13 0 1 0 1 0 Lover dependent resistance RDSLP1 0 Ldrift1 dependent resistance RDICT1 1 0 Ldrift1 dependent resistance RDSLP2 1 0 Ldrift2 dependent resistance g RDICT2 0 Ldrift2 dependent resistance RDTEMP1 0 Temp dependent resistance m K RDTEMP2 0 Temp dependent resistance m K2 RDVDTEMP1 0 Temp dependent resistance k RDVDTEMP2 0 Temp dependent resistance self heating effect VBISUB 0 7 Built in potential at the drift substrate junction p R
195. ET Models PSP Characterization This section provides a theoretical background for the PSP model It is based on the model revision PSP103 1 1 which released in December 2009 The PSP model is a compact MOSFET model that is intended for digital analog and RF design PSP is a surface potential based model It includes all relevant physical effects mobility reduction velocity saturation DIBL gate current lateral doping gradient effects STI stress and so on to model deep submicron bulk CMOS technologies A source drain junction model the JUNCAP2 model is an integrated part of PSP In December 2005 the Compact Model Council CMC selected PSP as the new industrial standard model for compact MOSFET modeling You can download the PSP source code user manual and testing examples from http pspmodel asu edu_ or http www nxp com Philips Models mos_models psp PSP Model Overview The PSP model uses a hierarchical structure therefore global and local parameter are set A separation exists between the scaling rules that are used for the global model and the parameters of the local model The model can be used at each level With the introduction of PSP103 0 in November 2008 the Global Local and Binning models are unified The model selector SwGEO decides the usage of a certain model By default when SWGEO 1 the model selector selects the Global model Setting SWGEO 0 selects the Local model The Binning model is invoked when
196. FACT execute_VYTHO_K1_K2_ aremt ni are Extract Optimize Plots F UsedPlot 2 Large idvg d2id dvg Now double click the modified model file BSIM4_DC_CV_Extract in the main window to open the GUI Within the GUI open a project and go to the Extract folder The new plot will appear in the multiplot window of the tuner and optimizer T O UO_UA_UB_EU_UC In this state the plot will be shown for information only and will not be taken in account for optimization Tuner T UO_UA_UB_EU_UC with additional plot d2id_dvg am InteractiveP lot 5 File Options Optimizer Plots Windows Help Id f V g Vb low va 20 y f ah or oO id m id s E 6 gm m s E 6 o0 oo on n 0 Es 1 0 0 5 0 0 05 1 0 15 vg E 0 0 J 1 0 0 5 0 0 05 1 0 1 5 20 vg E 0 Extraction Step Large Basic Vth Mobility Function O UO UA UB EU UC Save Functions Devices Optimizer Available Device s WSu0_LSu0_SA3u0 W0u18_LSu0_SA3u0 WSu0_LOu13_SA3u0 W0u18_LOu13_SA3u0 WSu0_LOu16_SA3u0 WSu0_LOu18_SA3u0 WSu0_LOu4_SA3u0 WSu0_L0u25_5A3u0 Y Selected Device s Name Wlum L um Category STI Cat WSu0_LS5u0_5 5 5 Large SA ref Results Adding a Plot and an Extraction Region for the Optimizer Add a new plot to the tuner optimizer T O UO_UA_UB_EU_UC as shown before Select the transform opt_U
197. FET echo MAIN 10 20 30 4 BSIMSOI_HF echo L dpar x_rf_transistor L 1u W dpar x_rf_transistor W 10e 6 echo AD dpar x_rf_transistor AD 10e 12 AS dpar x_rf_transistor AS 10e 12 echo PD dpar x_rf_transistor PD 22e 6 PS dpar x_rf_transistor PS 22e 6 echo NRD dpar x_rf_transistor NRD 0 NRS dpar x_rf_transistor NRS 0 Xx ends Modeling Strategy Modeling the AC behavior of a MOS device with the BSIMSOI model heavily depends on the accurate modeling of the DC curves and the capacitances at low frequencies e g 10 kHz to 1MHz However more and more applications especially in the telecommunication industry require the modeling of MOS transistors for use in a frequency range of 1 to 10GHz Therefore S parameter measurements have to be done see also Test Structures for SOI Transistors mosfet to cover this frequency range by a proper device model 307 MOSFET Models As is pointed out using the BSIMSOI model for high frequency applications requires some special attention to the modeling strategy We found the following procedure to give the most accurate results Measurement of DC and CV curves Extraction of the BSIMSOI model parameters from DC and CV measurements with special emphasis on a physically based extraction strategy Here model parameters should not be used for fitting purposes they should have their correct physical meaning Modeling of the output characteristic I f V 4 and the output resistance
198. FET Models te 5 05 Sarg 3 054 1 0 0 6 toil oo jo jo 25e41 oll DORFPFADCRFPODVAOARFR OD 0 5e 10 Oat Igbmod Trngs Diomod Toxe Xj Xt Phin K 3b Vom Dvtp0 Dvt2w UO Ud Vsat B1 Voff Cit Pcl Drout Delta Pditsd Rdwmin Prwbo Dwg w Lin Lie Wwe D m Cgbo Ckappad Die Vof fev Rbpd Ropsnf Ropdnf Rbpbxn f ALPHA1L EGIDL AIGBINV AIGC CIGSD NTOX CGBO CF VF BCV XRCRG1 RBDB RBPSW RBPDNF RBPBYO RBSBYO RBSDBXNF OIB KF DMCI XGL IJTHSFWD JSWGS CJSWGS IJTHDREV JSWD CJSWD PBSWGD KVSAT LLODVTH LKVTHO STETAO XN KT4L UD1 NJS TPBSW TSS JTSSWGD VTSD TSS TSSWGD VF BSDOF F KUOQWE OoOorRrOOCO CO OO 135 54 O7 tot dl psa N he oO Ul oO 100 100 0 12 3 0 0 0 0 0 5e 1 m OR ON OorPrcoo CcrR OO WORF OF ome NO N 0 0 0 X IGBMOD mod TRNQSMOD DIOMOD TOXE XJ XT PHIN K3B VBM DVTPO DVT 2W UO UD VSAT B1 VOFF CIT PCLM DROUT DELTA PDITSD RDWMIN PRWB DWG WW N G WWC EGIDL NIGBACC EIGBINV CIGC DLCIG NTOX CGBO CKAPPAD DLC VOFF CV RBPD RBPSNF RBPDN RBPBX 216 5 5e26 0 Orv RbpbyO RBPBYO Rbpby Rosbx0 RBSBX0 Rbsby Rosdbxl RBSDBXL Rbsdb Rbsdbyl RBSDBYL Rbsdb Noia NOIA Noi
199. For the ig input Set To Mode I To Node G gate From Node GROUND Compliance as high as 5 to 10V because the device is not yet connected Start Stop values that define a current range within the limits of the bias network 1 of Points a value sufficient to make several measurements across the current range The Step Size will be set automatically The Unit name must match the name of the SMU connected to the device gate probably VG This is also the SMU unit name set in the hardware window Refer to Renaming the SMUs With a current input compliance refers to voltage 326 MOSFET Models Caution The bias networks can be destroyed if IC CAP measurement current values are set too high Be sure you know the maximum current ratings of your bias networks and do not set current values beyond these limits The standard bias networks are rated at 0 5 amp For the id input Set To Mode I To Node D drain From Node GROUND Unit VD Compliance the same as for ig Sweep Type SYNC Ratio 1 000 so that the id sweep is synchronized to the ig sweep Offset 0 0 Master ig so that the id sweep is synchronized to the ig sweep Sweep e The Outputs are factory set and should not be changed Measuring and Extracting the Port Series Resistance Values mm Under Measure Simulate select Measure 2 When the measurement is complete the Measuring light on the DC source monitor goes out and the IC CAP wristwatch icon goe
200. H 25um Wringer 10Hum Nfinger 16 IMAG E S deemb 5 21 4 0 2 B 6 6 2 5 4 6 REAL CEt f 6 1 i 26 GHz S deemb M 21 Reverse Transmission Parameter S12 L 0 25um Wfinger 10um Nfinger 16 158 8 ia IMAG CE 3 50 0 CEE EE EE EE EE EE EE EE EE E i 6 150 0 150 5 100 0 50 B 0 0 50 B 166 6 156 4 S deemb M 1e S deemb S 12 i ill oe f 1 20 GHz Back to BSIM3v3 Characterization mosfet 155 MOSFET Models Temperature Dependence This chapter gives some information about the temperature model used in BSIM3v3 Built in Temperature Dependencies The BSIM3v3 model uses some physically based built in temperature dependencies as listed below Temperature voltage _ kBT tm q Intrinsic carrier concentration _6885 ye i 16_3 2 N 2 6310 T e Unfortunately the surface potential which is a very important model parameter from a physical point of view is not temperature dependent in BSIM3 Nh NIT i nom 2Vim Tnom Temperature Effects In addition to the built in temperature dependencies the following temperature related effects are modeled in BSIM3 They are related to threshold voltage mobility saturation of carrier velocity drain source resistance and the saturation current of the drain source bulk diodes a Threshold Voltage KT L a oe Fa T V T__ KT KT V 1 th th nom 1 Li ff 2 bseffi The behavio
201. Hall prefactor of bottom component Shockley Read Hall prefactor of STI edge component Shockley Read Hall prefactor of gate edge component Junction depth of STI edge F Tm V 1 m4 V 1 m4 V 1 m2 V 1 m2 V 1 V 1 C F m2 F m F m A m A m A m A m A m A m 1E 15 1 0 1 0 8E22 8E22 3E7 3E7 21 1000 1E 3 1E 9 1E 9 0 5 0 5 0 5 1E 12 1E 18 1E 18 1E2 1E 4 1E 4 1E 7 2T 0 273 1E 12 1E 12 1E 18 1E 18 Vbi low Vbi low Vbi low 0 05 0 05 0 05 1E 9 0 95 0 95 0 95 MOSFET Models component XJUNGAT L G Junction depth of gate edge m 1E 7 1E 9 l component CTATBOT L G Trap assisted tunneling prefactor m2 1E2 0 of bottom component CTATSTI L G Trap assisted tunneling prefactor A m2 1E 4 0 of STI edge component CTATGAT L G Trap assisted tunneling prefactor A m2 1E 4 0 of gate edge component MEFFTATBOT L G Effective mass in units of m0 0 25 0 01 for trap assisted tunneling of bottom component MEFFTATSTI L G Effective mass in units of mO 0 25 0 01 for trap assisted tunneling of STI edge component MEFFTATGAT L G Effective mass in units of m0 0 25 0 01 for trap assisted tunneling of gate edge component Band to band Tunneling Parameters CBBTBOT L G Band to band tunneling prefactor AV 3 1E 12 0 of bottom component CBBTSTI L G Band to band tunneling prefactor AV 3 1E 18 0
202. HiSIM_HV Modeling Package Initial Values Parameters Flags TOX 3 5E 008 DC Capacitance High Frequency Internal Iteration Method NSUBC 1 GE 016 corso 3 il cones lo cory i NSUBP 1 8E 016 z NOVER 2E 016 cooviP 1 CORG o COPPRY i EJ LDRIFT1 2E 006 COOVLPS 1 CORBNET 1 LDRIFT2 1E 009 LDLD 4E 008 COQOVSM 1 DFM i LOVERLD 2E 006 cossues 1 copFMY o ia comcs o Noise RD 0 016 RDICT2 1 COGIDL 1 COFLICK o DDLTMAX 10 costi o COTHRM o HISIM HY coapoy ji coIGN jo l COSELFHEAT 1 COTEMP o cosyM COLDRIFT 0 You can enter parameters and or change flags The parameters you ve entered or changed will be taken into account only after you ve pressed Reset Parameters and Results button located on the Extract Tab Related Topics DC Notes mosfet DC Information mosfet Binning appendixb DC Extract mosfet DC HTML mosfet DC Options mosfet DC Boundaries mosfet Back to Extraction of DC and CV Parameters mosfet DC Notes There is a folder provided to take some Notes on the project It has the same look as the one used in the Measurement modules see Notes mosfet Note This folder is intended for notes on extraction It will not overwrite your notes entered and saved during the measurement session These are kept in the information folder Related Topics e DC Information mosfet e DC Initialize mosfet
203. Js equals Is divided by the junction area For example Isd Js Ad where Ad is the drain area Drain Ohmic Resistance This parameter is geometry independent in SPICE and IC CAP In fact it is inversely proportional to channel width Critical Field for Mobility Degradation Used in level 2 model only Critical Field Exponent Used in level 2 model only Surface Mobility at Low Gate Levels Specifies mobility in level 2 and level 3 models In the level 2 model if Kp is UTRA Transverse Field Coefficient Used in level 2 model only Set UTRA to 0 to obtain same result as SPICE Maximum Drift Velocity of Carriers Determines whether Vdsat is a function of scattering velocity limited carriers or a function of drain depletion region pinch off VMAX is valid only for level 2 and level 3 models If VMAX is specified the scattering velocity limited carrier model is used to determine Vdsat Total Channel Charge A multiplicative factor of NSUB NEFF determines saturated output conductance Used only in the level 2 model and only when Vmax is specified Physical Process Lateral Diffusion Coefficient Used to determine the effective channel length Oxide Thickness Used when calculating conduction factor backgate bias effects and gate channel capacitances Type of Gate Indicates whether gate is of metal or poly silicon material OQ aluminum 1 opposite substrate 1 same as substrate Used in calculating threshold voltage when Vto is no
204. L Options Boundaries Tools Help a ei wy Es y l o 3 eA 5s ale ov iS H j E j EL PN A 8 44 a aq 13 3 Notes Information Initialize Binning Extract HTML Options Boundaries Extraction Flow Selected Extraction Step Data Available Functions x Global 3b Capacitance Oxide 4k Large Basic Vth Mobility ab Capacitance Fringing and Overlap ak Length Scaled th low Vd ab Capacitance Yth Shift in Overlap ak Short Rds Subthreshold Behavior ak Large Bulk Charge Effect ak Width Scaled Bulk Charge Effect ak Large Gate Current GIDL ak Large Gate Current Acc Inv ak Short Output Behavior ah Length Scaled Substrate Current 4K Length Scaled Yth high vd ak Short Output Behavior ak Length Scaled Output Resistance ak Length Scaled Weak Inversion 4K Width Scaled wth ak Narrow DY 4K Width Scaled wth ak Narrow DY ak Small D S Resistance 4k Width Scaled DW j Hl l F E l H l fee ee ee ee ee tt Hj E ak Length Scaled Mobility ak Width Scaled Bulk Charge Effect 4K Length Width Scaled wth low Yd ak All Transistors Finetuning Rds DY DL ab Capacitance Junction Bulk Drain d Diode Bulk Drain ak Temperature All Parameters 4k STI Stress Effect ak Well Proximity Effect E ak Finetuning iw Save Parameters j Et Hj E joe E C Messages Diagrams Tuners
205. L must be able to load measured data from a project it is recommended to load one prior to start working with the wizard eYou need to save possible changes in a currently loaded project before opening the Configuration Wizard Otherwise the changes will be overwritten eOpen the Configuration Wizard either from the menu Tools Configuration Wizard or from Extract gt Configuration Wizard Note This may take some time eYou will be prompted to save changes to the active project prior to opening the wizard Configuration Wizard GUI wenn Configuration Wizard for Extraction Functions 5 Configuration Edit Options Help GEGurk Available Extractions Overview Customized Functions Default Extraction Flows Available Extractions E Global 4 ia Local Capacitance Cgg H Local Long Wide Local Length Dependence Wide gt Local Long Width Dependence lt gt Local Length Width Dependence l amp PSP Scale Parameters lt gt Local Short Wide l Local Short Width Dependence 4 FA Binning The Configuration Wizard GUI uses 3 tabs Available Extractions Overview Customized Functions and Default Extraction Flows The Available Extractions tab shows the extractions defined for a specific model file Either a model file delivered with IC CAP Default Model File or Factory Settings or a customized model file can be loaded All extraction groups and functions included into th
206. MBER of POINTS and enter the number of frequency points to be measured across the range Keep in mind that the fewer the number of points the less time the measurements take Press DONE to return to the frequency list menu The segment you just defined is listed on the screen Press DONE to return to the main stimulus menu Press FREQUENCY LIST to activate the frequency list mode Press PRIOR MENU gt MORE gt CONTINUAL to set a continual stimulus sweep Press PRIOR MENU gt POWER MENU and set the desired power level In setting the source power and attenuation take care that the power level will not be excessive at the device input Also consider the gain of the device and set a power level that will not saturate the input port samplers of the analyzer If the power level at the sampler goes above 8 dBm an IF OVERLOAD error message is displayed and you will need to reduce the source output power The default network analyzer power level is 0 dBm For a device with power drop off at higher frequencies you may wish to set a power slope using the stimulus menus An appropriate power slope would be in the region of 2 3 dB GHz Press RESPONSE MENU gt AVERAGING ON restart and enter an averaging factor high enough to reduce trace noise and increase dynamic range as appropriate for your device measurements Although the default is 256 you may wish to use an averaging factor as low as 16 to reduce overall measurement time If the cal kit
207. MJSWS 0 33 MJSWGS 0 33 PBS 1 PBSWS 1 IJTHDFWD 0 1 XJBVD 1 BVD 10 JSWGD 0 CJD 5e 4 MJD 0 5 CJSWGD 5e 10 MJISWGD 0 33 PBD 1 SAREF 1E 6 SBREF 1E 6 WLOD 2E 6 KVTHO 2E 8 TKUO 0 0 LLODKUO 1 1 WLODVTH 1 0 LKUO 1E 6 WKUO 1E 6 WKVTHO 1 1E 6 PKVTHO 0 0 STK2 0 0 LODETAO 1 0 LAMBDA 0 VTL 2e5 TEMPMOD 0 TNOM 27 UTE e KT2 0 022 UA1 te 9 UB1 1e 18 AT 3 3e4 PRT 0 TVFBSDOFF 0 NJD 1 XTIS 3 XTID 3 TPBSWG 0 TOJ 0 TCJSW 0 JTSD 0 JTSSWS 0 JTSSWD 0 NJTS 20 0 NJTSSW 20 NJTSSWG 20 VTSSWS 10 VTSSWD 10 VTSSWGS 10 XTSD 0 02 XTSSWS 0 02 XTSSWD 0 02 TNJTS 0 TNITSSW 0 TNITSSWG 0 WEB 0 WEC 0 KVTHOWE O SCREF 1E 6 WPEMOD 0 model bsim4_mos BSIM4 NMOS NMOS PMOS PMOS Version VERSION Binunit BINUNIT Paramchk Mobmod MOBMOD Rdsmod RDSMOD Igcmod Capmod CAPMOD Rgatemod RGATEMOD Rbodymod Acngsmod ACNQSMOD Fnoimod FNOIMOD Tnoimod Permod PERMOD Geomod GEOMOD Epsrox TOxp TOXP Toxm TOXM Dtox Ndep NDEP Ngate NGATE Nsd Rsh RSH Rshg RSHG Vth K1 K1 K2 K2 K3 WO WO LpeQ LPEOQ Loeb Dvt0 DVTO Dvt1 DVT1 Dvt2 Dvtpt DVTP1 DvtOw DVTOW Dvtiw Eta0 ETAO Etab ETAB Dsub Ua UA Ub UB Uc Up UP Lp EP Eu AO AQ Ags AGS BO Keta KETA At Al A2 Vof Fl VOFFL Minv MINV factor Cdsc CDSC Cdscb CDSCB Cdscd Pdiblet PDIBLC1 Pdiblc2 PDIBLC2 Pdiblcb Pscbe1 PSCBE1 Psc
208. MOD PERMOD GEOMOD RGEOMOD WPEMOD Note Values 14 4 5 0 0 1 N N N W 0101010 0 0 0 0 i MOSFET Models Type of Model BSIM4 model selector in UCB SPICE3 Model version number Binning unit selector Switch for Parameter value check Parameters checked Mobility model same as in BSIM3v3 2 Bias dependent source drain resistance model selector internal Rds V Gate to channel tunneling current model selector Igc Igs Igd are off Gate to substrate tunneling current model selector Igb is off Capacitance model selector single equation and charge thickness model Gate resistance model selector no gate resistance Substrate resistance network model selector network off Charge deficit transient non quasi static model selector charge deficit model off Charge deficit AC small signal non quasi static model selector charge deficit model off Flicker noise model selector unified physical flicker noise model is used Temperature mode selector TEMPMOD 0 original temperature model TEMPMOD 1 BSIM4 3 0 temperature model TEMPMOD 2 BSIM4 5 0 enhanced temperature model Thermal noise model selector charge based thermal noise model Asymmetric source drain junction diode IV model selector Junction diodes are modeled breakdown free PS PD parameters include gate edge perimeter including the gate edge perimeter Geometry dependent parasitics model selector specify how the end S D diffusi
209. MSOI the SPICE simulator iterates the floating body voltage by use of diode current impact ionization GIDL and body contact current for DC simulations In AC simulations the displacement currents of the capacitance are also taken into account To model the dynamic depletion several new concepts have been developed The effective body bias Vbseff concept allows the use of one single equation for threshold voltage mobility and sub threshold for the cases with and without quasi neutral body regions Also the full depletion body voltage VbsOeff is being modeled Full depletion condition means Vbs is close to VbsOeff Furthermore the effective bulk charge effect accounts for the different bulk charge effects in PD and FD operation Finally vertical coupling dependency is incorporated into the diode current Using these advanced concepts it is possible to integrate SOI physics into the BSIM3v3 model with only a few alterations Body Potential The body potential at full depletion is the dominant factor for PD to FD transition This potential is V coa e for all regions of operation but not strong inversion in this region it will be V so With the help of V the classification of SOI devices is as follows e if Vicg is larger than OV the device operates in FD mode e if Vico is smaller than OV the devices operates as PD NFD device If the potential V9 is higher than 0 4V the device can be considered as strongly fully depleted
210. Models L 06 25um Wfinger 10um Nfinger 16 408 08 m i 5 w 300 B Li i A i i yp i 3J 266 6 r O I i amp 4 E 5 100 5 L m T vd LEFer f 1 206 GHz Influence of Incorrectly Modeled Output Characteristic on S21 25um WFinger 10um Nfinger 16 IMAG E E ll H S deer 5 21 REAL Ered f 60 1 206 GHZ S deemb M 12 S deer 5 12 S deer M21 e Extraction of the gate resistance from the input reflection S11 see the following figure e Verification of the gate drain overlap capacitance for higher frequencies e Extraction of the substrate resistance network parameters from S22 see the following figure e If a good fitting could not be found additional peripheral elements like inductances at drain gate or source should be added in a further sub circuit Input Reflection Parameter S11 L 0 25um WF inger 10um Nfinger 16 wren pacttroree ecko v Ope y 5 Tu ates S deemb S 11 vsa mr aor wer p ny B T T Ta Se eee ee t lec be ww www ewww wee e weno ne bem w www ewww ewww eee eee eee een S deemb M 11 TTT l l l l l l e e ee a a o e a a a a eee a a a a Output Reflection Parameter S22 154 MOSFET Models L 6 25um NF inger 1 Bum Nfinger 16 we teem e ewww eee ee eee S deemb 5 22 ee n S deemb M 22 wee wee eee eee eee ee Forward Transmission Parameter S21 L
211. Models i i 1 parameter P is continuous at the boundary between two bins That s the reason why the devices at the edges of a bin are used to determine the parameters Poi original model parameter for example VTHO extracted separately for each device P L i finally used interpolated model parameter inside a bin internal SPICE value Pi constant model parameter inside a bin in model parameter set Please note this is the same parameter as Poi but with a different meaning PLi length dependant model parameter inside a bin in model parameter set PWi width dependant model parameter inside a bin in model parameter set PPi length width dependant model parameter inside a bin in model parameter set Leff effective gate length Weff effective gate width For BSIM3 Eest ee oe ee a a ett des yt Ny LWN Np b des des des des W W 2 WINT VL _WW_ L _ ett des WLN WN WLN _WWN b des des des des For BSIM4 poan _des LEN EEN des des WF des NF _ Vdes Ee ee J ww WWI af pr Ss n we WWN a KWN i des Anami i des UNF J des NF Implementation into the BSIM3 4 Modeling Packages Output for the selected simulator The output of the BSIM3 BSIM4 Modeling Packages is ready for use with a simulator One of the major problems is that the basic SPICE3F5 simulator of UC Berkeley does not include the binning features of ADS HSPICE or Spectre Therefore binning will be limited to those co
212. NOTICE This document contains references to Agilent Technologies Agilent s former lest and Measurement business has become Keysight lechnologies For more information go to www keysight com KEYSIGHT TECHNOLOGIES MOSFET Models Bee Agilent Technologies IC CAP 2012 01 January 2012 MOSFET Models MOSFET Models Agilent Technologies Inc 2000 2011 3501 Stevens Creek Blvd Santa Clara CA 95052 USA No part of this documentation may be reproduced in any form or by any means including electronic storage and retrieval or translation into a foreign language without prior agreement and written consent from Agilent Technologies Inc as governed by United States and international copyright laws Acknowledgments UNIX is a registered trademark of the Open Group MS DOS Windows and MS Windows are U S registered trademarks of Microsoft Corporation Pentium is a U S registered trademark of Intel Corporation PostScript is a trademark of Adobe Systems Incorporated Java is a U S trademark of Sun Microsystems Inc Mentor Graphics is a trademark of Mentor Graphics Corporation in the U S and other countries Qt Version 4 6 Qt Notice The Qt code was modified Used by permission Qt Copyright Qt Version 4 6 Copyright c 2009 by Nokia Corporation All Rights Reserved Qt License Your use or distribution of Qt or any modified version of Qt implies that you agree to this License This library is fr
213. Number of curves measured in the linear region Automatically displays plots when measuring or optimizing Hint For a small number of devices such as two you may want to set this variable to Y When measuring or optimizing three or more set this variable to N Enables you to generate measured data from the model code if measured data is not available To do this set this variable to S and execute one of the measure macros When measuring real data this variable must be set to M Help variable used during the setup of the non nominal temperature models Help variable used to set temperature Array size for the data in extract par_vs_T Low GDS limit used for determining optimization targets Last value of Vbs for linear region Indicates if one of the parameters is at its allowed limit Used to indicate an error with the quick extraction routines for the linear subthreshold or saturation regions Temporary store for THE3 Indicates whether a quick extraction function should do a measurement or use existing data Linear Region Variables for Quick Extraction A reference value of Vsb to set the threshold voltage to at the end of the quick extraction routines The maximum expected change in threshold voltage between successive iterations If the change in threshold voltage exceeds this value an error occurs Choice of K factor model 1 a single K factor is used 2 the dual K factor model is used Control variable for body effec
214. O A ee ete gt i a00 B yf 9 4 Se oi u gis ee E ana aa HF Theoretical decrease of threshold al F voltage with shorter channel lengths I a e Sala due to the short channel effects gt 160 B aF 6 5 ie 1 1e Ldes CLOGI For short channel lengths together with small channel widths the following additional expression AVih 4 is needed to formulate the threshold voltage D F opt off f D W 6 off vIiw 2I O PT wT AV inva Prrow 2e V where Esi Tox dep T lw D pw bef sio Narrow Channel Effect All the effects on the threshold voltage are based on the non uniformity along the channel length Regarding the channel width the depletion region is always larger due to the existence of fringing fields at the side of the channel This effect becomes very substantial as the channel width decreases and the depletion region underneath the fringing field becomes comparable to the depletion layer formed from the vertical field This additional depletion region results in an increase of the threshold voltage with smaller channel widths which is expressed by AV ins W s AV ney E tE F ox th s 7 E3 43 bse 5 SH W a A Influence of Narrow Channel Effects on the Threshold Voltage CE 3 VTH_ Wem O E O cale VTH Wis Woes CE 63 Threshold Voltage Reduction Through DIBL The effect of the drain induced barrier lowering DIBL will be exp
215. O Length parameter for u0 stress effect 0 0 WLODKU Width parameter for u0 stress effect 0 0 k KVTHO Threshold shift parameter for stress effect 0 0 vm LKVTHO Length dependence of KVHTO 0 0 WKVTHO Width dependence of KVHTO 0 0 PKVTHO Cross term dependence of KVHTO 0 0 LLODVTH Length parameter for Vth stress effect 0 0 WLODVTH Width parameter for Vth stress effect 0 0 i STK2 K2 shift factor related to VthO change 0 0 m LODk2 K2 shift modification factor for stress effect 1 0 STETAO EtaO shift factor related to vthO change 0 0 m LODETAO EtaO shift modification factor for stress effect 1 0 RF Model Parameters Table RF Model Parameters Parameter Description Default Unit Value XRCRG1 Parameter for distributed channel resistance effect for intrinsic input resistance XRCRG2 Parameter to account for the excess channel diffusion resistance for intrinsic pe input resistance NGCON Number of gate contacts 1 XGW Distance from the gate contact to the channel edge 0 0 im XGL Offset of the gate length due to patterning variations 0 0 Im rbsb Resistance between sbNode and bNode 50 lQ rbdb Resistance between dbNode and bNode 50 lQ igbmin Conductance parallel with RBSB RBDB 1E 12 1 Q Back to BSIMSOI4 Characterization mosfet 320 MOSFET Models Agilent Root MOSFET Model Generator This section describes the Agilent 85194B Agilent Root MOSFET model generator It also provides an
216. OS echo LEVEL Smpar LEVEL 8 VERSION 3 2 4 BINUNIT Smpar BINUNIT 2 echo MOBMOD Smpar MOBMOD 1 CAPMOD Smpar CAPMOD 3 NOIMOD Smpar NOIMOD 1 echo PARAMCHK Smpar PARAMCHK 1 DELTA Smpar DELTA 0 01 TNOM Smpar TNOM 27 echo TOX Smpar TOX 7 5E 9 TOXM Smpar TOXM 7 5E 9 echo NCH Smpar NCH 1 7e17 XJ Smpar XJ 1 5E 7 NGATE Smpar NGATE 0 RSH Smpar RSH 0 echo echo VTHO Smpar VTHO 0 7 K1i Smpar K1 0 53 K2 Smpar K2 0 013 K3 Smpar K3 0 echo K3B Smpar K3B 0 WO Smpar W0 2 5E 6 NLX Smpar NLX 0 174u DVTO Smpar DVT0 2 2 echo DVT1 mpar DVT1 0 53 DVT2 Smpar DVT2 0 032 DVTOW mpar DVTOW 0 echo DVT1W Smpar DVT1W 5 3E6 DVT2W Smpar DVT2W 0 032 151 MOSFET Models echo ETA0 Smpar ETA0 0 ETAB mpar ETAB 0 DSUB Smpar DSUB 0 56 echo echo U0 Smpar U0 670 UA Smpar UA 2 25E 9 UB Smpar UB 5 87E 19 UC Smpar UC 4 65E 11 echo VSAT Smpar VSAT 8e4 A0 Smpar A0 1 AGS Smpar AGS 0 BO Smpar B0 0 echo B1 Smpar B1 0 KETA Smpar KETA 0 047 Al Smpar A1 0 A2 Smpar A2 1 echo RDSW Smpar RDSW 0 PRWB Smpar PRWB 0 PRWG Smpar PRWG 0 WR Smpar WR 1 echo echo WINT Smpar WINT 0 WL Smpar WL 0 WLN Smpar WLN 1 WW Smpar
217. O_UA_UB_EU_UC DUT Large Setup idvg and extend the variable F_RegionPEL_default with l Plot 2 d2ig_dvg Plot2_x1 min vg Plot2_ x2 max vg 75 MOSFET Models Plot2_y1 max derivative vg smooth3 id m 2 Plot2_y2 0 5 Plot2_y1 Default extraction region for Optimizer O UO UA UB EU UC Measure Simulate Instrument Options Setup Variables Extract Optimize Plots Select Transform Tune Fast extr VTH ough S Tune Slow oar 0 extr_VOFF_NFACTOR extr_VTHO extr_K1_K2_NDEP extr_UA_UB_EU extr_UC extr_AIGBINY_BIGBIN extr_AIGBACC_BIGBA extr_UA_UB_UD EU adi opt_All_Idvg Store Par opt _U0_ UA UB EU Lk opt_YOFF_NFACTOR Recall Par opt_ THO_K1_K2 3 opt_AIGBINV_BIGBINV Undo Optim opt_AIGBACC_BIGBAC opt_All_Igate opt_U0_UA_UB_EU_Uk execute_UO UA _UB_E execute_VOFF_NFACT execute_VTHO_K1_K2_ execute_AIGBINY_BIG execute_AIGBACC_BIc execute_All_Idvg_opt execute_All_Igate_opt vth vbs set_Vth v The value of the variable F_RegionPEL_default is included in apostrophes marked with red circles Comment lines are preceded by an exclamation mark The variable names of the x data boundaries are Plot2_x1 and Plot2_x2 as well as Plot2_y1 and Plot2_y2 of the y data The variable names must be exact as specified while the number of the plot Plot2 is corresponding to the plot number defined by
218. Optimization of model parameters improves the agreement between measured and simulated data An optimize transform whose Extract Flag is set to Yes is automatically called after any extraction that precedes it in the transform list Extracting Parameters 377 MOSFET Models This section describes the general procedure for extracting model parameter data from the UCB MOSFET transistor The general procedure applies to all types of parameters differences between extracting one type and another are primarily in the types of instruments setups and transforms used Also included in this section is information specific to DC and capacitance measurements and extractions Parameters are extracted from measured data taken directly from instruments connected to the inputs and outputs of the DUT Using the extracted parameters simulated data can be generated by the simulator Once measured and simulated data have been obtained each data set can be plotted and the resulting Plots visually compared in the Plot window IC CAP also extracts model parameters from simulated data This capability is useful for creating a set of model parameters from the parameters of another model parameter conversion or for testing the accuracy of the extraction The general extraction procedure is summarized next starting with the measurement process 1 Install the device to test in a test fixture and connect the test instruments 2 Ensure the test fixture signa
219. P Model mosfet References Compact MOS modeling for analog circuit simulation IEDM 93 The high frequency analogue performance of MOSFETs IEDM 94 Circuit Sensitivity Analysis in Terms of Process Parameters SISDEP 95 Unclassified report NL UR 003 94 R M D A Velghe D B M Klaassen F M Klaassen Philips Research Laboratories June 1995 5 Unclassified report NL UR 028 95 R M D A Velghe PE el ee 343 MOSFET Models Introduction to MOS Model 9 MOS Model 9 developed by Philips is a compact model for circuit simulation suitable for both digital and analog applications It provides the following features Non uniform doping effect on V Mobility reduction due to vertical field Vps influence on mobility reduction Velocity saturation Channel length modulation Subthreshold conduction DIBL Static feedback Substrate current Parameter scaling with respect to W L and temperature Based on single equation I V and Q V formulations Continuous gm Im Ig and Jgs behavior in the weak to strong inversion and linear to saturation transition regions This implementation is intended only for enhancement mode MOSFETs Although MOS Model 9 also has applications for depletion mode devices this implementation does not support this option It is intended to work in the absence of a circuit simulator with MOS Model 9 being available to IC CAP Thus the MOS Model 9 equations are implemented with C routines that are lin
220. PSP_DC_CY_Extract Mo Model Control Flags Process Parameters WARO LYARL LY AR Vy LAP WY ARO W ARL WAR YW WOT DLO DW VFBO VFBL VFB YFEL STYFBO STYFBL STVFBW STVFBLW TOXO EPSROXO NSUBO NSUBYY WSEG NPCK NPCKW WSEGP LPCK LPCK YW FOL1 FOL2 VNISIIRO Cancel eClick OK to add the desired parameter to the selected extraction step The list of parameters will be updated Parameter DLQ added to the list of parameters used with this Optimizer Tuner gt Custom Defined Function Function Parameters ee Add a Add H Del Type Optimization Tuner Name O TOXO NSUBO VFBO copy ePress the button lt marked red to auto generate a name of the function from the actual parameter list The name will change to O TOXO NSUBO VFBO DLQ eYou can enter a name into the Name field if you like to use your own names instead eUse the File menu to store the changed model file using a unique file name With this step the Available Extractions list to the left of the window will be updated with the newly generated extraction name O TOXO NSUBO VFBO DLQ Store the model file using a name you can easily remember since this model has to be used everytime you are working with projects that contain those newly defined Customized Functions Using a new function in a project eExit the Configuration Wizard eDouble c
221. ParName 0O PARAMETER 1 Parameter which is shown F_ParName 1 PARAMETER 2 Parameter which is shown 2 1 4 Special data handling and simulation 94 MOSFET Models Transforms to be executed after data is loaded F_Prepare ICCAP_ARRAY 0 No transform is executed F_Prepare ICCAP_ARRAY 2 More transforms are executed ordered from 0 up to x F_Prepare O 7RANSFORM Name of the transform in the setup where F_Setup points to F_Prepare 1 DUT SETUP TRANSFORM Begin with DUT if a transform is not in this setup Transforms to be executed instead of simulation F_Simulate ICCAP_ARRAY 0 The setup specified in variable F_Setup will be simulated F_Simulate ICCAP_ARRAY 2 F_Simulate O 7RANSFORM Name of the transform in the setup where F_Setup points to F_Simulate 1 DUT SETUP TRANSFORM Start with DUT if a transform is not used in this setup 2 1 5 Plots F_UsedPlot ICCAP_ARRAY 4 Number of displayed plots Counting starts at the upper left corner filling up a row first before going to the next row F_UsedPlot 0 log_id_vg Plot displayed top left Plot is specified inside the setup by F_Setup F_UsedPlot 1 Large idvg id_vg Plot displayed top right F_UsedPlot 2 log_id_vd Plot displayed bottom left Plot is in the setup specified by F_Setup F_UsedPlot 3 Large idvg id_vd Plot displayed bottom right 2 1 6 Region PEL code F_Regi
222. Rout f Vas is very important for S parameter fitting Perform S parameter measurements and proper de embed parasitics The starting points of the S parameter curves at the lowest frequency are to be modeled by fitting the curves with DC and capacitance parameters The following sequence of diagrams is intended to describe this process DC measurement of I f Va Output Characteristic of a SOI MOSFET ves ET Tr Trp rrrryprrrryprrrryprrry i i i i 3 8 Cee ee ATTELLI TETTETETT a m i LJ H ui i 2 0 a ee Se ea oi e 4 4 i o i y _ i i einai a en L etait aaea te oo Tae ewe EE SS mm ma mw ef fe P i a F m ee So ERR an i a B G 5 5 5 5 1 8 1 5 2 8 2 35 Use I f Vg to model R f Vg as shown below Rout aS a function of drain voltage i oe ke Pe Pate gee ee ee el ete i i i i i E 3 rout s rout m va CE I Measure S Parameters as function of V Fit low frequency S Parameters with DC diagrams as shown in the following figure by the colored circle to lead low frequency starting points for this parameter see the second figure Measured and de embedded parameter S22 308 MOSFET Models 4 i i I 4 Pn a ee ee en nn ee ne ee ne wn ne ee ee enn mene en nnn n eens ce S quasp GS S277 quesp s Starting points of S22 as functi
223. S E j F Hi o i aa t 3 Notes Information Initialize Binning Extract HTML Options Boundaries General data Technology Lot Wafer Chip Operator Date Notes on project Project bsim4_for_experts Project directory js users default_2009 Status The top row of the GUI window contains a menu to perform file operations like Open Examples Save Setup Entries Export and Import Extraction and Batch Processing The next menu items are used to Initialize extractions to set Binning items and Extract options to show Plots to create HTML reports to set Options and Boundaries and to call the He p menu The Help menu gives access to specific help for the different tasks during extraction of parameters You ll find help for each folder of the BSIM Modeling Packages as well as a list of topics The Info menu item provides some information about the BSIM Modeling Package like version date and its creators AdMOS You can find most of the menu settings in the form of icons just below the menu Some icons are only activated for specific tasks At the bottom of the extract window you can find the project name and project directory used for the extraction Using the File gt Examples menu a form opens to let you copy an example project to a path and a location where you have write access This step is necessary since the IC CAP example directories are usually write protected and you need
224. S Modeling mosfet DC and CV Measurement mosfet Using DC and CV Measurement Module with WaferPro mosfet RF Measurement mosfet Extraction of DC and CV Parameters mosfet Extraction of Parameters for the RF Models mosfet MOSFET Models Introduction to the MOS Modeling Packages AdMOS has developed the technology for measurement and extraction of parameters using the MOS Modeling Packages for HISIM2 HISIM_HV BSIM3v3 BSIM4 BSIMSOI4 and PSP model parameters These Modeling Packages use similar Graphic User Interfaces GUI and are handling the measurement and extraction tasks in a similar way and therefore only need to be described once The model specific parts are located in BSIM3v3 Characterization mosfet BSIM4 Characterization mosfet BSIMSOI4 Characterization mosfet PSP Characterization mosfet HiSIM2 Characterization mosfet HiSIM_HV Characterization mosfet The above sections describe theoretical aspect of each model Supported Measurements The modeling packages support measurements for the following e Single finger normal transistors e Parasitic diodes e Capacitance o Oxide o Overlap o Bulk drain and source drain junction o Intrinsic e RF multifinger transistors Supported Extractions The modeling packages supports extractions for the following e Basic transistor behavior e Parasitic diodes e Capacitances e RF behavior S parameters See Also Key Features of the MOS Modeling Pac
225. SCBE Parasitic resistance effects Quantum mechanic charge thickness model Well proximity effect Enhanced temperature mode TempMod 2 Enhanced mobility model using Leff dependency Enhanced drain current model e VTH model for pocket retrograde technologies e New predictive mobility model e Gate induced drain leakage GIDL e Internal external bias dependent drain source resistance RF and high speed model Intrinsic input resistance Rgate model Non Quasi Static NQS model Holistic and noise partition thermal noise model Substrate resistance network Calculation of layout dependent parasitic elements Asymmetrical source drain junction diode model I V and breakdown model Gate dielectric tunneling current model Back to BSIM4 Characterization mosfet 190 MOSFET Models Key Features of the BSIM4 Modeling Package e The graphical user interface in Agilent s IC CAP enables the quick setup of tests and measurements followed by automatic parameter extraction routines The data management concept allows a powerful and flexible handling of measurement data using an open and easy data base concept The powerful extraction procedures can be easily adapted to different CMOS processes They support all possible configurations of the BSIM4 model Quality assurance procedures are checking every step in the modeling flow from measurements to the final export of the SPICE model parameter set The fully automatic generation of HTML repor
226. SIM4 Description Default Value Variable Parameter UO UO Low field mobility NMOS 670 PMOS 250 cm2 Vs UA UA First order mobility degradation MOBMOD 0 1 1E 9 MOBMOD z2 coefficient due to vertical field le 15 m V UB UB Second order mobility degradation 1E 19 m V 2 coefficient UC UC Coefficient of the body bias effect of MOBMOD 1 0 0465 1 V mobility degradation MOBMOD 0 2 0 0465E 9 m V 2 UD UD Mobility coulomb scattering coefficient 1 14 1 m72 UP UP Mobility channel length coefficient 0 1 m2 EU EU Exponent for mobility degradation of NMOS 1 67 PMOS 1 0 MOBMOD 2 Drain Source Resistance Model The resistances of the drain source regions are modeled using two components The sheet resistance which is bias independent and a bias dependent LDD resistance In contrast to the BSIM3 models the drain and source LDD resistances are not necessarily the same they could be asymmetric This is a prerequisite for accurate RF simulations A further enhancement of the BSIM4 model over BSIM3 is the external or internal RDS option invoked by the model selector RDSMOD 0 internal RDS or RDSMOD 1 external RDS The external RDS option looks at a resistance connected between the internal and external source and drain nodes See the following figure G seu Sk AN RSDIFF RS V RDDIFF RD V RDSMOD 0 internal Rs V 1 Ras dia WR 126 W offcj RDSWMIN RDSW Paws Ps bse Ps Te PRIG V gsteff RD
227. SMOD 1 external Rd V and Rs V 202 l R rf V a WR 1e6 W oftep NF RDSWMIN RDSW l PRWB V bd PRIVG V 7V 5 1 PRWG Ved V psa j 1 R P S WR le6 W effec NF RDSWMIN RDSW d 1 gt PRWB V R a ee bs 1 PRWG V os V fsd l The flatband voltage Vfbsd is calculated as follows If NGATE gt 0 V kg l T ae NGA TE fbsd q NSD Else bsa 7 Drain Source Resistance Parameters MOSFET Models Equation BSIM4 Description Default Variable Parameter Value NGATE NGATE Poly Si gate doping concentration 0 0 cm 3 PRWB PRWB Body bias coefficient of LDD resistance 0 0 Vv 0 5 PRWG PRWG Gate bias dependence of LDD resistance 1 0 1 V RDSW RDSW Zero bias LDD resistance per unit width for RDSMOD 0 Q um RDSWMIN RDSWMIN LDD resistance per unit width at high Vgs and zero Vbs for 0 0 2 um RDSMOD 0 WR WR WR Channel width dependence parameter of LDD resistance 1 0 Saturation Region Output Conductance Model The following figure shows a typical MOSFET Ids vs Vds diagram The calculated output resistance is inserted into the diagram as well This output resistance curve can be divided into four distinct regions each region is affected by different physical effects The first region at low Vds is characterized by a very small output resistance It is called the linear region where carrier velocity is not yet saturated Increasing Vds leads to a region that is domi
228. SP_DC_CV_Extract C_Oxide Assign change of transform Customer_Configuration Extract defineExtractionGroups from user defined model PSP_DC_CV_Extract_635102 to the new model PSP_DC_CV_ Extract Execute steps to implement a user defined extraction routine into a model file as described above Save the new model file under a new name 89 MOSFET Models Programming details Initializing Common variable F_ID A unique ID do not use the string AdMOS For each ID of an optimizer a tuner ID will be generated because every optimizer can be used as a tuner too The tuner ID is the optimizer with an added T This has to be considered when naming the IDs Example Never use UserID1 and UserID1T as well F_Name Name of function start with E for extractions and O for optimizations The generating routine will automatically add a tuner T Note There is a blank before and behind the F_Setup Location of the transform starting with the name of the DUT Data Source NoData 1 Local variable for the number of data lists 1 to 4 sources can be used F_DataSourceHead ist Headline of the list field where used sources can be selected Only to be configured if more than one source is used NoData contains the number F_DataTargetSetup ist ICCAP_ARRAY 1 Must be an array Another setup can be loaded with the same data F_DataTargetSetup st 0 Large idvg Setup to which the data will
229. Setup Switch Matrix Device Definition Options Data E Transistor l 3k Capacitance PCT Pel Pe um A Measuremer E Device List Junction BD 27 jeder L Comment Category DE Diode CperimBD_AZ8n0_P7m6_NF100 M M M 10 BD Perim CperimgateBD_A28n0_P7 m6_NF100 M M 10 BD Perim Gate CareaBD_A426n0_P760u0_NF1 M M 10 BD Area Junction BS L AS Comment Category CperimBS_A28n0_P7m6_NF100 10 28000 BS Perim CareaBS_A28n0_P760u0_NF1 10 28000 BS Area CperimgateBS_426n0_P7m6_NF1i00 10 28000 BS Perim Gate C Oxide L 40 45 be Comment Category Cox_W200u0_L100u0_NF1 100 Oxide C Overlap G DS L NF M 4D AS if Comment Category CoverGDS_W2m0_LOu18_NF200 0 16 200 1 2000 Overlap GDS auar COSR AoA LAS MENN non naglann li ann aa Averlan COSR Ka Project bsim _for_experts Project directory g users default Status This folder provides fields to enter names of DUTs geometries and switch matrix connections and to select temperatures at which to measure the DUTs e To add new DUTs Choose the Add icon You will be prompted for a group of capacitances to add DUTs to Select the desired category junction bulk drain or bulk source oxide overlap or intrinsic and choose Add New lines are added according to the selection you made Note Selecting overlap capacitances actually adds two DUTs Overlap_GDS and Overlap_GDSB Not for Overlap_GD and Overlap_GS For proper parameter extraction you are
230. T L G B Flag for impact ionization current 0 0 1 SWGIDL L G B Flag for GIDL GISL current 0 0 0 1 off SWIJUNCAP L G B Flag for JUNCAP O off 0 0 3 SWJUNASYM L G B Asymmetric junction flag s 0 0 1 Off 0 SWNUD L G B NUD effect flag 0 0 1 Off 0 SWDELVTAC L G B separate charge calculation flag 0 0 1 QMC L G B Quantum mechanical correction 1 0 factor Labels for Binning Set LMIN B Dummy parameter to label m 0 binning set LMAX B Dummy parameter to label m 1 binning set WMIN B Dummy parameter to label m 0 binning set WMAX B Dummy parameter to label m 1 binning set Process Parameters LVARO G B Geometry independent difference m 0 between actual and programmed polysilicon gate length LVARL G B Length dependence of difference 0 between actual and programmed polysilicon gate length LVARW G B Width dependence of difference 0 between actual and programmed polysilicon gate length LAP G B Effective channel length reduction m 0 per side due to lateral diffusion of source drain dopant ions WVARO G B Geometry independent difference 0 between actual and programmed field oxide opening WVARL G B Length dependence of difference 0 between the actual and the programmed field oxide opening WVARW G B Width dependence of difference 0 between actual and programmed 242 A Models field oxide opening WOT G B Effective reduction of channel width per side due to lateral di
231. TH Lku0d LKUO PKUO LkvthO LKVTHO kvth0 WKVTHO STK2 Lodk2 LODK2 Steta0 STETAO da LAMBDA Vtl VTL Le LC UTE Kt1 KT1 Kt11 KT1L UAt Ub1 UBt Uct UC1 At AT Prt PRT Tvfbsdoff TVFBSDOFF NJS Njd NJD Xtis XTIS TPB Tobsw TPBS Tobswg TPBSWG w TCJSW Tcjswg TCJSWG Jtss JTSS ws JTSSWS Jtsswd JTSSWD Jtsswgs JTSSWGS NJTS Njtssw NJTSSW Njtsswg NJTSSWG VTSD Vtssws VTSSWS Vtsswd VTSSWD wgd VTSSWGD Xtss XTSS Xtsd XTSD wd XTSSWD Xtsswgs XTSSWGS Xtsswgd XTSSWGD ssw TNJTSSW Tnjtsswg TNJTSSWG Lintnoi LINTNOI WEB Wec WEC KvthOwe KVTHOWE e KUOWE Scref SCREF Woemod WPEMOD seam EXtension tO BSIMA hOsehab lets cease cele SaaS ere ass Hoes Ue See scalable external capacitors taking into account cross coupling between metal lines kd and inductors to account for delay effects due to the size of the devices i scalable channel length reduction in multi finger devices a scalable substrate network using different configurations symmetric horseshoe scalable Delta L reduction CGDEXTO te 9 external capacitance gate drain per gate width and gate finger F m CGSEXTO te 9 external capacitance gate source per gate width and gate finger F m CDSEXTO te 9 external capacitance drain source per gate width
232. The next folder Extract defines the Extraction Flow for the devices There is a standard extraction flow implemented but you can change this flow if you find another one better suiting your requirements If you would like to implement your own extractions there is a feature called the Configuration Wizard mosfet You are able to define custom extraction functions and insert them into the GUI Extract folder as well as extending an existing standard optimizer tuner or an extraction This feature is described in detail in Customized Functions mosfet The PSP model extraction flow is somewhat different since it extracts local and global parameters in alternating steps although the handling is the same It is described in detail under Extraction of Parameters for the PSP Model mosfet You can also add custom extraction steps using a feature called Finetuning See Finetune mosfet It is possible to rename the default names inside the Extraction Flow This is possible for all Main Groups and for Extraction Groups but not for Devices and special extractions like Save Paramter or Reset Parameter To rename a Group select the appropriate entry from the list using the right mouse button An entry field will be opened where you can enter the desired name Default names will be restored if the prompt is left empty The changes will be stored with the project Extract form 45 BSIM4_DC_CV_Extract 6 File Initialize Binning Extract Plots HTM
233. This is the maximum output current capability of the Agilent 4142 plug in source monitor unit SMU supplying the drain terminal In the example procedure this is VD or HPSMU3 For the Agilent 41420A high power SMU the compliance is 1A for the Agilent 41421B medium power SMU the compliance is 100 mA Ours Caution Also be aware of the current ratings of your bias networks and do not set current values beyond their specified maximum limits It is quite possible to destroy the bias networks and the probes by applying current values beyond the specified limits The standard bias networks are rated at 0 5 amp 15 You can save the values in the transform to use for another extraction Select File gt Save As then the File Type Transform type an appropriate filename and select OK The file is saved with the suffix xfm Performing the Data Acquisition Measurement This procedure performs the measurement you defined Once you initiate the transform the data acquisition takes approximately 1 to 2 hours to run before your interaction is needed again The data acquisition rate is approximately 700 points per hour The number of data points measured depends on the nonlinear behavior of the device and on the measurement conditions you set up 1 In the create_mdl setup select the Extract Optimize tab 2 Select data_acquisition gt Execute During the data acquisition process a running message in the UNIX window indicates the appr
234. WW 0 echo WWN Smpar WWN 1 WWL Smpar WWL 0 DWG Smpar DWG 0 DWB Smpar DWB 0 echo LINT mpar LINT 0 Smpar LL 0 LLN Smpar LLN 1 LW Smpar LW 0 echo LWN Smpar LWN 1 LWL mpar LWL 0 echo VOFF Smpar VOFF 0 08 NFACTOR Smpar NFACTOR 1 CIT Smpar CIT 0 echo CDSC mpar CDSC 2 4E 4 echo CDSCB Smpar CDSCB 0 CDSCD Smpar CDSCD 0 PCLM Smpar PCLM 1 3 echo PDIBLC1 Smpar PDIBLC1 0 39 echo PDIBLC2 mpar PDIBLC2 0 0086 PDIBLCB mpar PDIBLCB 0 0 DROUT Smpar DROUT 0 56 echo PSCBE1 Smpar PSCBE1 4 24E8 echo PSCBE2 Smpar PSCBE2 1 0E 5 PVAG Smpar PVAG 0 VBM Smpar VBM 3 echo ALPHAO Smpar ALPHA0 0 ALPHA1 Smpar ALPHA1 0 BETAO Smpar BETA0 30 echo echo JS 1e 20 JSW 1 0E 20 NJ 1 IJTH Smpar IJTH 0 1 echo echo CJ 0 MJ 0 5 PB 1 CJSW 0 echo MJSW 0 33 PBSW 1 CJSWG Smpar CUSWG 5E 10 MJSWG Smpar MISWG 0 33 echo PBSWG Smpar PBSWG 1 CGDO Smpar CGDO 0 CGSO Smpar CGSO 0 CGBO Smpar CGBO 0 echo CGSL mpar CGSL 0 CGDL mpar CGDL 0 CKAPPA Smpar CKAPPA 0 6 CF Smpar CF 0 echo NOFF Smpar NOFF 1 VOFFCV Smpar VOFFCV 0 ACDE mpar ACDE 1 MOIN mpar MOIN 15 echo DLC Smpar DLC 0 DWC mpar DWC 0 C Smpar LLC 0 LWC Smpar LWC 0 echo LWLC Smpar LWLC 0 WLC Smpar WLC 0 WWC Smpar WWC 0 WWLC Smpar WWLC 0 echo CLC Smpar CLC 0 1E 6 CLE mpar CLE 0 6 echo ELM Smpar ELM 2 XPART Smpar XPART 0 5 echo echo KT1 Smpar KT1
235. XM 3E 009 PARAMCHK 1 MTRLMOD o RBODYMOD o i DTOX 0 MTRLCOMPATMOD o TRNQSMOD o xJ 1 5E 007 a c ERT RDSMOD 0 z ACNQSMOD 0 NGATE 0 IGCMOD 1 B Noise TES IGBMOD 1 momo 1 yL 0 CAPMOD 2 momo o gt aT 1 55E 007 CYCHARGEMOD Jo RSH 0 DIOMOD 1 B Transistor Layout PERMOD 1 i TEMPMOD o g SEoMop Cs x WPEMOD 1 B GIDLMOD o Initial Parameter Set O nothing selected Drain Source Symmetry Drain Source Resistance Overlap Capacitance Junction Capacitance PSP Initialization of PSP model parameters 104 Junction Diode MOSFET Models Initial Yalues Parameters Flags NPO 6E 026 pc NOYO 5E 025 SWIGATE i 5 WARO 4 905E 011 LYARL 1 531E 017 SWIMPACT 1 LY AR YY 2 022E 020 SWGIDL 1 e LAP 2 574E 011 WVARO 1 018E 009 SWIUNCAP 1 lw WVARL 1 497E 018 SWIUNASYM 0 WVARW 1 01797E 019 omc is WOT 4 965E 010 The Initialize menu contains a field to Set Initial Values to Circuit Defaults Inside the Initial Values Model Parameters section enter process related parameters like the relative dielectric constant of the gate oxide EPSROX Advanced CMOS process generations are more and more making use of high k gate dielectrics Therefore you can specify the relative dielectric constant of your process by changing EPSROX from 3 9 default value for SiO gate dielectric There are other process parameters to be specified on this
236. You can speed up a measurement by using S short but this is not recommended because it degrades the dynamic range of the measurement Set Range to 0 to implement SMU autoranging Power Compliance is used to set the maximum current voltage combination for the DC source monitor However in the models SMU voltage and current compliances are set individually in the individual setups Therefore the value here can be set to 0 000 Set SMU Filters ON to Yes This switches in low pass filters on the SMU outputs to protect the device from voltage spikes caused by DAC output changes High frequency IC CAP is not generally configured for pulsed measurements therefore Pulse Unit can be left blank All other Pulse settings are then irrelevant and can be ignored Module Control is not used in these procedures leave the field blank Init Command sets the instrument to a mode not supported by other fields in this table It is not generally used in these models Leave the field blank unless instructed otherwise If you wish refer to the DC source monitor manual for more detail If the measurement setup you are configuring calls fora DC measurement only close the instrument options window Then return to the modeling procedure nteg Time to M medium Then return to this section and continue Setting the r_series Inputs Use the following guidelines to set the ig and id inputs most will not need to be changed from the default settings
237. a Drain source n MOS capacitor of high doping concentration Buried oxide Pt as dielectric buried oxide insulation Bulk p Via Large finger MOS capacitor of high doping concentration n buried oxide insulation layer and underlying substrate _Perim_ m AD NF a b PD NF 2 a b pn junction 311 MOSFET Models C_Perim_ Gate_m pn junction Drains ource Vid _ 1 J Bulk p PERMOD 0 PD NF 2 a W NF 2 b PERMOD 1 AD NF a b PD NF 2 a b W NF 2 b Finger diode with a large perimeter a small area and the low doping concentration n of the LDD region shown here for an ntype device m Gate 7 Gate poly S1 j Bulk p Ve Gate Hi poly Si S Vs tn D Lo i Bip PERMOD 0 PD no_inner drain 2a no_outer_drain 2 a b PS no_inner_source 2c no_outer_source 2 b c PERMOD 1 W NF 5 AD no_dran a b AS no_source a b PD no_drain 2 a b PS no_source 2 a b PERMOD 0 PD no_inner drain 2a no_outer_drain 2 a b PS no_inner_source 2c no_outer_source 2 b c PERMOD 1 312 Large area MOS capacitor with poly MOSFET Models W NF b AD no_dran a b AS no_source a b PD no_drain 2 a b PS no_source 2 a b Test Structures for Intrinsic Capacitance Measurements DUT Shape Applied bias n type Comment One or more
238. ables RIVSTART RIVSTOP and RIVSTEP control the voltage sweeps id The output current id_sim A call to JUNCAP to evaluate the simulated current set_temp This transform sets the setup level variable TEMP to the model level variable TREVERSE The reverse data may be measured at a different temperature TREVERSE than the forward I V or C V data However the JUNCAP function looks for a variable TEMP to determine the device temperature Therefore TEMP is defined as a setup level variable in the area rev_iv locos rev_iv gate rev_iv and analysis rev_iv setups Thus during simulations in these setups the setup variable TEMP will supersede the model level variable TEMP make_iv_data A transform to make synthetic reverse I V data The function 362 MOSFET Models MM9_COPY is used is this transform connect_riv You can modify this transform to enable automatic connection to the DUT for reverse I V measurements rev_ivplot The plot definition for the reverse I V data The analysis DUT In the analysis DUT the dimensions AB LS and LG are set to unity The setups are cv fwd_iv and rev_iv cv This setup controls the extraction of the C V parameters and contains the following va This input definition for the anode voltage is the same as that in the area cv locos cv and gate cv setups cjbvn A transform that extracts and holds the normalized area sub region contribution to capacitance from the measurements in the area cv locos cv and
239. above figure shows the tree structure used for extracting BSIM3 device parameters If you are using the SOI Modeling Package the Device Definition pane displays the entries which are not normally present on BISM3 4 HSIM or PSP measurement projects For example there are no floating transistors to be measured in BSIM3 or 4 modeling tasks Click the sign to expand the Transistor Diode and Capacitance entries and reveal the Measurement and Device List 16 MOSFET Models Data H A Measuremer EE Device List 5 4 Capacitance g Measuremer EE Device List 1 Diode A Measuremer EE Device List does wl The Measurement node shows the predefined measurement sets as well as setups already selected for the specific measurement To add a setup click the icon You will be prompted to select a setup and enter a name for it The new setup will be included in the tree below Measurement Data gt Polarity G aE Transistor A Measuremer nmos Pos E idvg idvd are Compliance A EE Device List vd vg vb vs ve v6 t 3 Capacitance y l E p Diode 0 1 o o01 o1 fo 0 1 o 1 Measurement Sets SetName Setups included Seti idva idvd Set2 idvg idvd idvd_vbmin There are fields named Compliance where you may define compliance settings for your SMU The settings are in Ampere A and are valid for all measurements defined That is you cannot define a compliance setting for the drain v
240. acitance Measurements it is physically not possible to eliminate all stray capacitances up to the DUT Therefore you need to calibrate the instrument up to the switch matrix with all matrix connections set to open Calibration will remove the capacitance of the cables between CV meter and switch matrix To calibrate the way all to the DUT for each matrix connection the capacitance needs to be measured with the probe card in the up position no DUTconnected The measured capacitances for every switch matrix connection will be removed from the measurements of the DUTs capacitances For automatic measurements macros are available These macros enable you to make automatic series measurements of complete dies or arrays They are created for automatic measurements with or without heated chucks For example open the IC CAP model for BSIM3_DC_CV_Measure from the IC CAP Main window right click the DC_CV_Measure model then select Edit The Macros folder contains a macro called Example_Wafer_Prober You will also find a macro in the ICCAP_ROOT examples model_files mosfet BSIM3 examples waferprober directory named prober_control md Please use this macro or model file and tailor it to your needs There are readme sections to explain the steps to be taken inside the macros The automatic measurement of model diagrams using the macro works without involving the GUI For your convenience the waferscan macro in the prober_control md example
241. ackage ee es Basic Effects Modeled in BSIM4 cc 24 2 Sha aca es we aces Sta Shee GR Ge Se daa ies ae heh a SE eae eee Key Features of the BSIM4 Modeling Package 0 ccc es BSIM4 DC Behavioral Modeling ws iis Bcc at Sates Af ated Shak RT AS a aig es ed ee ea Sian CV Modeling ot asp net caste Ge ee Ae vba a a Bs end vie a me gh Sp Ge cae Bolsa anode MEA ia Saye Goi as me a asa wh Ain ena erat The BSIM4 RE Simulation Model ssc se has a ee ace te Sea we ee as we Sa ee Se Ga SPICE Model Parameters for BSIM4 6 2 0064 260 45 8 ee ee Pe Ee ew ee eae HiSIM2 Characternization o saena tod ce wun catch Wi Bk Sly ce reheat Pod elo anes Bo Butt Soa ed Dire andi het te Introduction to HiSIM2 Characterization a na aa aoaaa a a HISIM MOGI A sa nE aie aae eaaa Se des aaiae D eect a a aah each to a Aie DE aah E aE Modeled Device Characteristics of the HiSIM2 model 000 cee a SPICE Model Parameters for the HiSIM MOS Model 000 cee es RE Circuit used FOr IST M2 Ferm ches Dah ts wim Ro Ea St he eet Bes Siew ald a tes Rim as Spee aeaa S bees Ore ASM SF WO GES Daan st ata arra de E EE a Cassa ee tan a a on Se cast thy Da ab sarge ct eal iG a a ae Gh Se een a PSP Characterizati Mie auras desns ahi odia D eee ce Aw He MS aS Clete ei al ila iny aa Be BLA wm Rw ee ra eae ath Gi a Extraction of Parameters using the Local Global approach cee ee es Parameter Extraction using Global Model only ce es Simultaneous
242. act ionization pre factor Coefficient for the length dependence of impact ionization pre factor Coefficient for the width dependence of impact ionization pre factor Coefficient for the length times width dependence of impact ionization pre factor Coefficient for the geometry independent part of impact ionization exponent at TR Coefficient for the geometry independent part of temperature dependence of A2 Coefficient for the geometry independent part of saturation voltage dependence of II Coefficient for the length dependence of saturation voltage dependence of II Coefficient for the width dependence of saturation voltage dependence of II Coefficient for the length times width dependence of saturation voltage dependence of II Coefficient for the geometry independent part of back bias dependence of II Coefficient for the length dependence of back bias dependence of II Coefficient for the width dependence of back bias dependence of II Coefficient for the length times width dependence of back bias dependence of II Coefficient for the geometry independent part of gate tunneling energy adjustment Coefficient for the geometry independent part of gate channel current pre factor Coefficient for the length dependence of gate channel current pre factor Coefficient for the width dependence of gate channel current pre factor Coefficient for the length times width dependence of gate channel current prefactor Coef
243. action as it was in the beginning of a project To delete a step Choose the Delete button Note You cannot delete the first Reset Parameters and the last Save Parameters step inside an extraction flow To export the extracted parameters The step Save Parameters inside the Extraction Flow informs you of the path and name for the saved mps or lib file On the right side of the Extract folder you will find a field named Extraction i Extraction Name Scale Overlap Capacitance Transform RF_Scalable_Transistor Cgd extract_all This field shows the name of the extraction as well as name and path of the transform used in this extraction step There is a field Function Flow which is used to set the flow of extraction steps Select the desired function out of the list found under Available Functions by selecting the function and clicking the arrow in between the Function Flow and the Available Functions fields Arranging the functions inside the function flow is done using the buttons provided below the Function Flow field 111 MOSFET Models Function Flow E CF CGDO CGS0 CGDL CGSL DLC T CF CGDO CGSO0 CGDL CGSL DLC 0 CF CGDO CGSO CGDL CGSL DLC Move Up Default Move Down Delete Insert above selected item Direct Execution Mode Under Available Functions you will find in the example above three functions for this function flow The first function is an extraction step E the
244. age are not given and the extraction of the parameters DVTO DVT1 and SO On can result in very unrealistic values In this case those parameters should be removed from the extraction flow In general if the macro produces errors you should add the visual tuning feature to those parameters that caused the error In a further run the correspondent curves are simulated and displayed and the user can try to find the source of the error The sequence of the model parameter extraction is shown in the following figure You can modify this extraction flow by editing the flow if you find another sequence that better fits your special process Extracton Flow Extiacton Name Transform Function Flow Avalable Functor E ALPHAD ALPHA BETAD T ALPHAD ALPHAT BETAO 0 ALPHAD ALPHAT BETAO Extraction Strategy This section describes two aspects of the extraction strategy a group extraction and a physically oriented model parameter extraction Group Extraction Strategy A major enhancement of the BSIM3v3 model compared to older simulation models is that one set of model parameters covers the whole range of channel lengths and channel widths of a certain process that can be used in circuit designs Many effects in the BSIM3 model depend very strongly on device dimensions such as the channel length and width This is considered in the determination of model parameters in the BSIM3v3 Modeling Package through the use of a group extraction st
245. ail 23 Close the instrument options window Then return to the modeling procedure U1 Different Settings for Agilent 8753 with External Test Set An Agilent 8753 with an external test set uses different settings for power level and attenuation Also these analyzers do not have the power autoranging or coupled port power functions These are the different settings 1 Port 1 Atten and Port 2 Atten must be set to the same level of attenuation you set in the network analyzer calibration The default is 20 dB 2 Source Power must be set to the same level as in the network analyzer calibration The default is 10 dBm Exceptions Because you used a frequency list cal rather than a swept frequency cal note the following e Be sure the instrument states you set for the network analyzer correspond to the values you set in your calibration e Set Use Fast CW to No e Be sure to set the averaging factor the same as in your calibration e Set Cal Type SHN to H for hardware e Set Cal Set No to the cal set or register where you stored your calibration 333 MOSFET Models e Set Use Linear List to Yes Then return to this section and continue Setting the s_vgvdf Inputs This procedure defines the input signals from both the DC source monitor and the network analyzer for this measurement Since this measurement only preverifies the device the values can be quite conservative and need not stress the device to the limits of its perf
246. ainst measured data e Store the data and model files for circuit simulation in Agilent MDS O Notes e Measurement parameters and measured data are specific to individual devices Information and data provided here are examples and guidelines and are not intended to represent the only correct results The procedure provides guidelines on setting values to measure your device However the values you use is based on your device and information in its data sheet and the guidelines presented here which may or may not correspond with the example values e The illustrations of plotted data are provided as visual examples of possible results They are not intended to represent a single device and may not correspond with the values given in the procedure The plots can be used to check the reasonableness of your own data which should appear similar in shape but not necessarily coincident in values DUT and Setups The Model window is the central access point for measurement and model generation process It includes the DUT Setup panel and the file tabs to access the Model Parameters table the model variable table and other needed IC CAP features The illustration shows the DUT Setup panel for the model generator file HPRootMos md The DUTs for example pre_verify indicated by the inverted triangles are groupings of similar measurement setups used to make related measurements or extract related model parameters The setups for example _idv
247. al device type definitions are also imported as shown in screenshot below WaferPro Device Types Definition Identification Name Polarity D G 5 B Node5 Node6 Name 4 C Node3 Node Name Polarity BES ee Be Name P1 51 52 P2 SUB BIP_RES_RB Name Polarity P1 51 52 P2 5UB E C AdMOS_DC_Transistor Name 4dMOS_Project Polarity SizeCategory STI WP D G 5 B E Node AdMos_cy Name 4dMoS_Project Polarity Category WPE COMM D G 5 B 4dMOS_Diode Name 4dMOS_ Project Polarity Category WPE COMM D G 5 B To view the new measurement routines select Test Plan gt Measurement Conditions in the WaferPro window In the Edit Measurement pane you can select the new routines from the Routines drop down list The following screenshot displays the added routines in the WaferPro window 39 MOSFET Models RRR EN RE EERE ERR Edit Measurement Conditions Routine my_MOS_DC_basic v Description Measure _Idvd Yes No only Calc_PCM_data Yes No only Importing Devices Types Similarly to measurement routines you can also import the defined devices from the MOS Modeling Toolkit to a WaferPro project The device list in the MOS Modeling toolkit can be exported in a csv format which can be further imported in a WaferPro project Follow the steps below to import the defined devices from the MOS Modeling Toolkit to a WaferPro project 1 In the MOS Modeling Toolkit window choose File gt Expo
248. al parameter name Extraction Flow of the PSP Toolkit 285 Extraction Group Global Capacitance and Junction parameters Local Long Wide Local Long Width dependence PSP Scale Parameters Long Width dependence Local Short Wide Local Length Dependence Wide Wim 240n 150n 90n 65n Device Configuration i Short Wide Length Dependence Wide Long Wide 45n 60 90n 150n 240n Long Width Dependence Length Width Dependence Short Width Dependence Wim 45n 60n 90n 150n 240n 45n 60n 90n 150n 240n MOSFET Models Local Level Parameters NEFF BETN CS MUE DPHIB VP XCOR THEMU THESAT GCO GC2 GC3 Al A2 etc VFB NP NEFF BETN DPHIB MUE IINV IGOV etc THESATG THESATB RS RSB XCOR ALP ALP1i ALP2 Snax ETC Global Level Parameters VFB TOX TOXOV NP NOV IDSAT VBR etc MUEO MUEW CSO CSW 286 Notes Extraction of Capacitance parameters from the Long Wide device Local parameters fixed for all devices among others VP THEMU GCO GC2 A2 A3 Local parameter extraction of all long devices Global extraction using all the long devices to extract width dependent parameters which do not have a length dependency Local extraction using the short wide device Local Length Dependence Wide PSP Scale Length Dependence Wide Lo
249. alize gt Initial Parameter Set gt Add The form that opens enables you to enter the necessary information browse to the file location and select the simulator To change between using the Initial Values and Initial Parameter Sets select the radio button to the left of each section Select which initialization procedure you want to use If you would like to use the binning capability check the Generate Binning Model button With this button checked the folder Binning is activated There is a field provided to enter PEL commands which are executed at initialization of the extraction process Note that the sequence of initialization uses values of the model parameters first before PEL commands are executed From the menu Initialize chose Set Initial Values to Circuit Defaults if you would like to reset the parameters You can Add or Remove a Parameter from the list shown in the middle of the folder by selecting the Initialize menu You will get a list with parameters to select from This might be helpful if you would like to extract some specific parameters at initialization BSIM4 Initialize Folder for the BSIM4 Modeling Package Model Parameters press Reset Parameters and Results Extract Tab to accept Initial Yalues Parameters Flags EPSROX 3 9 Model DC Capacitance High Frequency TOXE 3E 009 BINUNIT 1 MOBMOD 1 reatemop lo TOXP 3E 009 TO
250. and gt 0 Oxe Oxe 0 CGSO 0 0 CGDO 0 i CODO y CGSO C a T a If CGBO is not given it is calculated by COBO 2 DWC C xe For CAPMOD 1 or 2 the bias dependent overlap charge is modeled at the source side by Coverlap S W CGSO Vas active 2 5 1 2 2 8 COG ae _ aoe SA Kes 2 ra 100 4 es T0 a eaS 2 Poe v 2 2 CKAPPAS gs 100 45 amp 10 100 ee _ 2 A i CKAPPAS at the drain side by Q Sonan i Z capo Y od active oe scapi v a t r gt r Toa gd 2 gd 100 WX g2 10 100 Aee 2 F_ F_ CKAPPAD raa 100 4A gd 100 100 ee O aa eee 2 ey CKAPPAD and the gate overlap charge by Q 1 overlap g overlap d iJ Coverlap 5 CGBO L YF active gb Intrinsic Capacitance Model Parameters Equation BSIM4 Description Default Variable Parameter Value NOFF NOFF CV parameter in Vgsteff CV for weak to strong inversion 1 0 VOFFCV VOFFCV CV parameter in Vgsteff CV for weak to strong inversion 0 0 V ACDE ACDE Exponential coefficient for charge thickness in accumulation 1 0 m V and depletion regions in CAPMOD 2 CKAPPAS CKAPPAS Coefficient of bias dependent overlap capacitance on source 0 6 V E CKAPPAD CKAPPAD Coefficient of bias dependent overlap capacitance on drain CKAPPAS E CLC CLC Constant term for the short channel model 0 1E 7 m CLE CLE Exponential term for the short
251. and BSIM4 PSP Modeling Packages Cross section of a MOSFET showing device geometries 24 MOSFET Models S D DrainPerimeter PD You are not bound to an order of entry This means you are not required to begin with the large transistor the short transistor or the narrow one Just type in the geometries into each line as you like Top view of a multifinger MOSFET ou number of fingers number of gate stripes Source NF 4 Gate Drain In addition to the standard BSIM4 definitions columns for SA SB and SD are available see the following figure for a definition of the parameters used in shallow trench isolation modeling Shallow trench isolation related parameters Trench isolation Moreover each transistor is assigned to two different categories as is described in the following section Categories The Device List shows one or more category columns depending on what you are extracting The first one is the size category the second one is the STI category and the third one is the WPE category e Size category applicable for BSIM3 and BSIM4 PSP determines the properties of a transistor regarding channel length L and width W e STI category applicable only for BSIM4 PSP determines the properties of a transistor regarding the actual value of SA SB Mainly this category defines whether a device belongs to the reference values SAREF SBREF or has SA SB values which are different from the refe
252. and gate finger F m LDRAINO te 6 3 drain inductance per gate width and gate finger H m LGATEO te 6 3 gate inductance per gate width and gate finger H m LSOURCEO 1e 6 3 Source inductance per gate width and gate finger H m LBULKO te 6 bulk inductance per gate width and gate finger H m RSHB 29 bulk sheet resistance Ohms sq DSBC 2e 6 3 distance source implant to bulk contact m DDBC 2e 6 3 distance drain implant to bulk contact m DGG 2e 6 distance gate to gate m DHSDBC 2e 6 distance drain source edge to horseshoe substrate contact m DLO 0 basic channel length reduction correction m DL1 0 channel length reduction correction 1 and 2 outer fingers m DL2 0 channel length reduction correction outer fingers m RSUBEQ 0 selection flag for different substrate resistance configurations RSUBEQ 0 symmetric substrate resistance contacts RSUBEQ 1 horseshoe substrate resistance contacts temporary constants echo factor_even_odd 0 5 1 tmp_nf 2 int C0 5 tmp_nf echo tmo_dl1 C tmp_nf 4 5 C2 abs tmpo_nf 4 5 8 tmp_nf echo tmo_d12 tmp_nf 2 5 C2 abs tmo_nf 2 5 4 tmp_nf calculation of substrate resistance for different configurations echo tmp_rdo1 factor_even_odd tmp_nf DDBC RSHB tmp_w echo tmp_rsb1 factor_even_odd tmp_nf DSBC RSHB tmp_w echo tmp_rdo2 DHSDBC RSHB tmp_nf DGGttmp_1 echo tmp_rsb2 tmp_rdb2 ec
253. aphic user interface GUI For tips on how to measure and what to measure using the right devices see BSIM3v3 Characterization mosfet BSIM4 Characterization mosfet BSIMSOI4 Characterization mosfet HiSIM2 Characterization mosfet and PSP Characterization mosfet Note As the measurement modules of the MOS Modeling Packages are identical only one is described in detail Double click the Model icon BSIM3 BSIM4 or PSP icon in the IC CAP Main window to open the Model GUI The BSIM3 BSIM4 or PSP Icon which appears in the IC CAP Main window after you open one of the example files To open an example file choose File gt Examples gt model_files gt mosfet gt bsim3 or bsim4 or PSP then select a Measure or Extract model file The following figure shows four of the files in one IC CAP Main window using BSIM3 as an example Starting the BSIM3 GUI from IC CAP Main window mai IC CAP Main File Edit Tools Measure Windows Help DG be YD X 0 Pro a After you have double clicked the DC_CV_Measurement icon for example the GUI window of the MOS Modeling Packages figure below appears on your screen Measurement part of the Graphic User Interface for the MOS Modeling Packages ir BSIM4A_DC_CV_Measure 1 File Configuration Data Tools Hep peGBEPFee gt xk BE Notes Temperature Setup Switch Matrix px pa px The top row of the GUI shows the File Configuration Data Tools and Help menu
254. arameter Set global_31 mps Import Export Plot Layout Plot Optimizer Display Template Automatic Save Save 8 150 wWO0uls L5u0_SAGu0 We 1800n L 5000u NF 1 000 100 o a w 4 z g 4 ex o o Z g 50 2g 2 0 0 0 vd E 0 Adk AR WSu0_ L0u13_SAGu0 Wwe 5 pidu L 130 0n NF 1 000 Wu0_L5u0_SAGu0 w 5 D00 L 5 000u NF 1000 1 0 vd E 0 vd E 0 Configure the plot window using the Plot Layout pull down menu to select a specific type of display layout You can change between automatic and a predefined number of plot rows and columns or a user defined number of plots in the Plot window Note that the defined number of plots are opened only if an appropriate number of devices outputs or temperatures is selected This means if you manually set a plot display of 3x3 plots select the IdVg plot of one device at one temperature and one output you will only see one plot Choosing the Automatic plot layout displays the appropriate number of plots according to your selection To the right you are able to select Devices Bias Conditions and Outputs to be plotted Changes take place if you press Redisplay Under the Plot menu of the Plot window you can zoom in on a specific plot or get a full screen plot You will be prompted for the plot to zoom to This menu is also used to undo the display changes There is a pull down menu located below the top row of the
255. arameters Finally all the nominal devices are resimulated using the new maxiset parameters optimize_maxiset Calls the optimization sequence for the maxiset parameters at the nominal temperature The extraction sequence itself is controlled by the transform extract scaled_ext sca_opt After the optimization all the devices are resimulated using the new model parameters display_parameter_vs_geometry_plots Displays plots of the chosen miniset parameters vs geometry simulate_using_extended_equations Causes all the DUTs at the nominal temperature to be resimulated using the extended equations as would be used in a circuit simulator optimize_at_one_temperature Prompts you to specify the temperature of interest calls the extract single_temp_ext single_temp_opt transform to perform optimizations of the temperature sensitive parameters at the chosen temperature and then causes all the devices at this temperature to be resimulated using the new parameters You would typically execute this macro once for each non nominal temperature being used extract_temperature_coefficients Controls the extraction of the temperature coefficients that are valid over the full range of temperatures First the temperature sensitive parameters at all the temperatures are written to a file whose name is given by the variable TEMPFILE Then the function MM9_TEMPSCAL is called which reads the parameters from the file just created and extracts the temperature coefficient
256. are as follows 1 Measure several devices at nominal temperature 2 For each device extract values for parameters 1 through 21 in section 4 5 List of Parameters for an individual transistor of the Philips MOS Model 9 documentation see References mosfet 4 These parameters are referred to as the miniset parameters In practice this step consists of a series of optimizations on the data for the individual devices a Initialize parameter values Choose 1 or 2 body effect factors Set ETAM ETAGAM and ETADS b Linear Ijs Vas data Optimize BET THE1 and VTO for Vp OV Optimize KO K VSBX and THE2 for all Vz c Subthreshold Ijs Vas data for Vp OV Optimize GAMOO MO and ZET1 d Saturation ggs Vg data for V p OV Optimize VP for large device Optimize GAM1 and ALP for other devices e Saturation I Vy data for Vj OV Optimize THE3 f Substrate current I Vys data for Vz OV Optimize A1 A2 and A3 g Repeat steps b through f h Subthreshold Ijs Vys data for all Vsp Optimize VSBT 3 Apply the geometry scaling rules to the parameter sets generated in the previous step and generate the full set of device parameters at the nominal temperature In practice this step consists of a least squares fitting procedure followed by optimizations on all the devices at nominal temperature This set of parameters is referred to as the maxiset e An initial estimate is obtained by fitting the scaling rules dir
257. arge Gate Large Impa AE Length Scali copy 1 Data Selection 4 Width Scaling 4 Length Widt 4 Temperature E Global Optimizations J STI Stress Effect ak Well Proximity Effect 4 Finetuning Local Capacitance Cag Local Long Wide Plots Local Length Dependence Wide Local Long Width Dependence Local Length Width Dependence amp PSP Scale Parameters Local Short Wide Local Short Width Dependence ttt Binning PEL Defined Function not editable Optimization Tuner TOXO NSUBO YFBO Move Up Move Down apti m optional Default Size Category Large Narrow Short Small Only WPEret Only SAref SS SSSR SRE SES Selection Policy Allow Multiselection of Devices Sort Devices by 1 W WF Z O X idesc g voji O VQ ae ee ee ee ee Se es Default Optimizer Settings Algorithm Levenberg Marquarct Abs Error Relative sim meas meas eAdd a parameter by using button Add to the right of the window under Parameters A window opens where you can select one of the parameters valid for this model see Figure 3 In our example the parameter DLQ is added to the selected extraction step Select a parameter from a list of available parameters for this model 62 L Scale Parameters TOXO NSUBO VFBO Additional Configure MOSFET Models Select Parameters Parameters Insert Select From list i Parameters A
258. ary In the following example the files in the Import Wizard window are located in G tmp and are named W25_L50_idvg mdm respective W25_L50_idvd mdm 36 MOSFET Models 48 mdm Import Wizard 9 File Delete Data Help baea tx FF Name ImportTest Path G susers default Polarity NMOS PMOS Temperature Setup DC Transistor DUTs Capacitance DUTs DC Diode DUTs CY Diode DUTs Select device list cs G fusers default Export_BSIM4_Experts csy kz Basic data directory lt DIR gt G fusers default ped mdm Type in Project mdm description in im Yt dependency on imp lt MDM_PRI gt lt MDM_FILE gt idvg idvd MDM File Constructor lt DIR gt W25_L50_ lt MDM_FILE gt When all folders are filled with the required information start the automatic checking process by clicking _ The Import check window appears see below loxi 0 Check Settings 0 Check Files DC 0 Check Files CV 0 Check Files Diode 0 Check Files CV Diode 0 Import 0 Check Project Next Do All Finish Cancel You can check each setting step by step using the Next button or you can Do All checks automatically You will get error messages if something is wrong If no errors occur the Finish button on the Import window will be activated Press this button to complete the import process before saving the changes and exiting the wizard The DC_CV_Measure
259. as coefficient of short channel TOXE 0 0 150E 9 0 0 If NDEP is not given but GAMMA1 is given c oxe iy NDEP _ N given NDEP 1E17 6E16 1e20 1 55E 7 VBX Ds n g NDEP XT 2 e SI 0 0 0 1 1 0 NMOS 1 5 PMOS 1 5 NMOS 0 7 PMOS 0 7 0 5 0 0 80 0 0 0 2 5E 6 1 74e 7 0 0 3 0 0 53 0 032 4 Esi 2 If both are not 219 Unit y 1 2 y 1 2 cm 3 cm cm 3 2 sq Q sq 1 V DVTPO DVTP1 DVTOW DVT1W DVT2W ETAO ETAB DSUB UO UA UB UC UD UP LP EU VSAT AO Al A2 AGS BO B1 KETA VOFF VOFFL MINV NFACTOR CIT CDSC CDSCB CDSCD RDSW RDSWMIN RDW RDWMIN RSW RSWMIN WR PRWB PRWG NRS NRD effect on VTH First coefficient of drain induced Vth shift for long channel pocket devices Second coefficient of drain induced Vth shift for long channel pocket devices First coefficient of narrow width effect on VTH for small channel length Second coefficient of narrow width effect on VTH for small channel length Body bias coefficient of narrow width effect on VTH for small channel length DIBL coefficient in the subthreshold region Body bias for the subthreshold DIBL effect DIBL coefficient exponent in subthreshold region Mobility Low field mobility First order mobility degradation coefficient due to vertical field Second order mobility degradation coeffici
260. at model file are shown on the Available Extractions tab Once you have added customized groups and 61 MOSFET Models functions they will be inserted into that first tab The Overview Customized Functions tab lists all user defined customized functions as well as the groups they are used for This tab is originally empty if you load a default extraction model such as PSP_DC_CV_ Extract or any other extraction model file from the supported MOS models Supported models are eBSIM3 eBSIM4 e BSIMSOI4 eHiSIM and HiSIM_HV ePSP The third tab Default Extraction Flows lists the extraction flows for the loaded model file Customization of groups or functions must be performed on the Available Extractions tab Once the customized groups and functions are defined you are able to change them on any of the tabs the other tabs will be updated with the customizations Customization is model dependent and will be saved for a specific model only It is not possible for example to customize the BSIM3_DC_CV_Extract model and use the customization for the PSP model If you open a customized project using a default model file warnings will occur stating that customized functions or extraction flows have been inserted into the project but are not available with the default model file You need to open customized projects with the same model file that has been used to create the customization for that project Otherwise customizations will be d
261. at the drain end of the channel will be introduced The potential barrier can be reduced by the drain voltage even in long channel devices This effect is called Drain Induced Threshold Shift DITS and the early voltage due to DITS is r RN SEN l ADITS PDITS Ey 1 FPROUT Vis KR T V gt 2 gsteff q 1 1 PDITSL Lop exp PDITSD F s Saturation Region Output Conductance Parameters Equation BSIM4 Description Default Variable Parameter Value DROUT DROUT Channel length dependence coefficient of the DIBL effect on 0 56 output resistance PSCBE1 PSCBE1 First substrate current induced body effect parameter 4 24E8 V m PSCBE2 PSCBE2 Second substrate current induced body effect coefficient 1 0E 5 m V PVAG PVAG Gate bias dependence of Early voltage 0 0 FPROUT FPROUT Effect of pocket implant on Rout degradation 0 0 V m 9 5 PDITS PDITS Impact of drain induced Vth shift on Rout 0 0ov t PDITSL PDITSL Channel length dependence of drain induced Vth shift on 0 0 Rout PDITSD PDITSD Vds dependence of drain induced Vth shift on Rout 0 0v t PCLM PCLM Channel length modulation parameter 1 3 PDIBLC1 PDIBLC1 First output resistance DIBL effect parameter 0 39 PDIBLC2 PDIBLC2 Second output resistance DIBL effect parameter 8 6m PDIBLCB PDIBLCB Body bias coefficient of output resistance DIBL effect 0 0 1 V Body Current Model The substrate current of a MOSFET consists of diode junction currents gate to body tunneling current impact ionization Iii and gate
262. at which the forward I V and the C V curves will be measured TREVERSE The temperature at which the reverse I V curves will be measured If possible this should be higher than TEMP to accentuate the current component from generation effects AB1 The area of the area DUT LS1 The locos perimeter length of the area DUT AB2 The area of the locos DUT LS2 The locos perimeter length of the locos DUT AB3 The area of the gate DUT LS3 The locos perimeter length of the gate DUT LG3 The gate perimeter length of the gate DUT CONNECT_CV This variable is set depending on whether the user wishes to use manual or automatic connections for C V measurement CONNECT_FIV This variable is set depending on whether the user wishes to use manual or automatic connections for forward I V measurement CONNECT_RIV This variable is set depending on whether the user wishes to use manual or automatic connections for reverse I V measurement CVSTART The start voltage for C V sweeps CVSTOP The stop voltage for C V sweeps CVSTEP The voltage step for C V sweeps FIVSTART The start voltage for forward I V sweeps FIVSTOP The stop voltage for forward I V sweeps FIVSTEP The voltage step for forward I V sweeps RIVSTART The start voltage for reverse I V sweeps RIVSTOP The stop voltage for reverse I V sweeps RIVSTEP The voltage step for reverse I V sweeps DATASOURCE If set to M measurements will be taken Otherwise data will be generated from simulations DISPLAYPLOTS If set
263. ata will not be plotted unless the init_parameters macro has been executed see the instructions near the beginning of this section The icplotnotes file generated by the init_parameters macro provides the x axis information needed to plot the modeled data IC CAP will display an error message if you have not executed the init_parameters macro 1 From the Plots tab select the plot of your choice and Display Plot e Qg is the distribution of charge current under the gate The illustration shows this data for an example device e Qd is the distribution of charge current under the drain Other Outputs of the Model Generation Process The model generation process results in a number of different output files to be used for different purposes These include the model file for MDS interface data on various modeled parameters measured device data and files for internal use by the program Some files have default filenames assigned by the program Others may be files you created during the procedure to save device specific information Caution In general the files should NOT be modified because changing them can cause problems that may invalidate the model It is also important that you do not change the names of files created by the model generator with the exception of State mds Following is a list of some files that will be or may be created during the modeling process icplotnotes This is the only file you can safely edit
264. ate S source and B bulk substrate for the MOSFET device nodes These nodes are defined in the Circuit folder Measurement units abbreviated as follows are defined in Hardware Setup SMU for DC measurement units VS for voltage source units VM for voltage monitor units CM for capacitance measurement units NWA for network analyzer ports units Instrument to Device Connections DUT Drain Gate Source Bulk Comments large SMU1 SMU2 SMU3 SMU4 narrow SMU1 SMU2 SMU3 SMU4 short SMU1 SMU2 SMU3 SMU4 cbdi CM L open open CM H calibrate for parasitic capacitance cbd2 CM L open jopen CM H calibrate for parasitic capacitance Notes DUT is the name of the DUT as specified in DUT Setup Example DUT arge has the DC measurement unit SMU1 connected to its drain SMU2 connected to its gate SMU3 connected to its source and SMU4 connected to its bulk 376 MOSFET Models Measuring and Extracting This section provides guidelines as well as procedures for performing measurements and extractions of MOSFET devices Measurement and Extraction Guidelines The following guidelines are provided to help you achieve more successful model measurements and extractions Setting Instrument Options Before starting a measurement you can quickly verify instrument options settings Save the current instrument option settings by saving the model file to lt file_name gt mdl from the model window Some of the Instrument Options
265. ate finger H m RSHB 25 bulk sheet resistance Ohm sq DSBC 2e 6 distance source implant to bulk contact m DDBC 2e 6 distance drain implant to bulk contact m DGG 2e 6 distance gate to gate m DLO 0 basic channel length reduction correction m DL1 0 channel length reduction correction 1 and 2 fingers m DL2 0 channel length reduction correction outer fingers m internal temporary variables factor_even_odd 0 5 1 tmp_nf 2 int 0 5 tmo_nf tmo_dl1 tmp_nf 4 5 2 abs tmp_nf 4 5 8 tmp_nf tmp d1l2 tmoe_nf 2 5 2 abs tmp_nf 2 5 4 tmp nf Leff tmp_l 2 DLO tmpop_dl1 DL1 tmp_d1l2 DL2 p SSS secS Ss Gate network C CGDEXT n20 n10 C CGDEXT0 tmpe_w C CGSEXT n20 n30 C CGSEXT0 tmp_w R RGATE n20 n24 R 0 333 RSHG tmp_w tmo_1 tmp_nf tmp_nf ngcon 2 Noise 1 L LGATE i2 n20 L LGATEO tmp_w es cae Cet Taal Drain network s SshsssssS Resse EnA RRA C CDSEXT n10 n30 C CDSEXTO0 tmp_w DRAIN i1 n10 L LDRAINO tmp_w p SSsSoss5 Source network SOURCE i3 n30 L LSOURCE0 tmp_w fe eda Substrate fe lWork macta nS aS Ss Sera S a Diodes are for n type MOS transistors hsim_diode_area Djdb_area n12 n10 Area tmp_ad hsim_diode_perim Djdb_perim n12 n10 Area tmp_pd hsim_diode_area Djsb_area n32 n30 Area tmp_as hsim_diode_perim Djsb_perim n32 n30 Area tmp_ps R
266. ated Parameters relative gate dielectric constant Electrical gate equivalent oxide thickness equivalent SiO2 thickness Default Value 3 9 SiO2 3E 9 1 5E 9 Physical gate equivalent oxide thickness TOXE Gate oxide thickness at which parameters are extracted defined as TOXE TOXP Source Drain junction depth Body effect coefficient near the surface Body effect coefficient in the substrate Poly Si gate doping concentration Channel doping concentration at depletion edge for zero body bias Substrate doping concentration Source Drain doping concentration Doping depth Vbs at which depletion region equals XT Sheet resistance Gate electrode sheet resistance Threshold Voltage Flatband voltage Gate voltage at which EOT is measured effective Gate length at which EOT is measured effective gate width at which EOT is measured Temperature at which EOT is measured Long channel threshold voltage at Vbs 0 Zero bias threshold voltage variation Non uniform vertical doping effect on surface potential First order body effect coefficient Second order body effect coefficient Narrow width coefficient Body effect coefficient of K3 Narrow width parameter Lateral non uniform doping parameter at Vbs 0 Lateral non uniform doping effect on K1 Maximum applied body bias in VTHO calculation First coefficient of short channel effect on VTH Second coefficient of short channel effect on VTH Body bi
267. ates separately for each measurement setup ina modeling procedure However use the same settings for all the swept S parameter measurement setups in one model except that Integ Time can differ among setups Unless you use the example settings documented here write down the settings you use to duplicate among setups within one model The settings used here are examples Your settings may differ Explanations here apply to all swept frequency S parameter measurements in the different device measurement procedures 332 MOSFET Models Note Source parameters such as frequency range are not set in this procedure but in the individual S parameter setup procedures in each model chapter Do not use these settings for a CW S parameter measurement The settings for a CW measurement are Slightly different and are documented following this procedure 1 Zi 3 4 Select the swept S parameter setup of your choice Select the Instrument Options tab Set the Agilent 4142 instrument state the same as for the DC measurements Set the Agilent 8753 instrument state according to the actual hardware configuration the calibration used and the device to be measured following these guidelines Set Use User Sweep to No because this is a standard internal sweep 6 Hold Time is the time in seconds before the instrument starts a sweep to allow for DC settling Generally no hold time is required 7 Delay Time is the delay in seconds the
268. aturation portion of the curve Sidewall and Junction Capacitance Parameter Extractions To accomplish total cv extraction due to both bottom area and sidewall area measure two DUTs using the same setup specifications In these extractions CJ and CJSW are calculated then PB MJ and MJSW are extracted CJ and CJSW Extractions The values of CJ and CJSW are extracted from the measured capacitance data from the two different structures The capacitors should have different ratios of their bottom area to sidewall area for best resolution of the equations The areas and perimeters used for the calculations are stored in the Model level variable table The example MOS Model files provided with IC CAP use variable names AreaCap1 PerimCap1 AreaCap2 and PerimCap2 The capacitor in the cjdarea Setup has a capacitance dominated by the bottom area of the device The capacitor in the cjdperimeter Setup has a capacitance whose perimeter area contribution is significant The names in the variable table and in the DUT must match for the extraction to perform properly 381 MOSFET Models PB MJ and MJSW Extractions The parameter PB is extracted using the junction capacitance measurement not dominated by the sidewall effect This is the DUT named cbd1 in the example MOS Model files The total capacitance is modeled by two equations that represent the bottom junction area and the sidewall junction area The values of MJ and MJSW are obtained by
269. atus There are icons to Calibrate the network analyzer to start a Measurement using the Start Stop and Step definitions on the measurement setup folder to Add or Delete DUTs to Configure the De embedding and to De embed All DUTs To Clear measured data or to Synthesize data use the Data menu Once a DUT has been measured completely the Status column will change from 0 to M to show the state of measurement Synthesize data performs a simulation of S parameters using the frequency definitions on the DUTs folder and a set of parameters loaded into the program from any other extraction task to see correlations or to extract parameters into BSIM4 from another model release A De embedding task starts with configuration before de embedding the measurement setup De embed All Click Configuration Configure De embedding Set or use the icon Ta to assign a de embedding set defined on the De embedding Pad Structures folder to a specific DUT You will get a list of DUTs and de embedding sets defined for assignment 46 MOSFET Models ay Configuration of De embedding O x Assign De embedding Set to selected DUT tr2_nl6_w4 Click the DUT then click the SET to be assigned to the selected DUT Click the De embed All icon to start de embedding measured data for each DUT with a de embedding set assigned The Display Plots icon is intended to check the measurement results in the form of diagrams using th
270. b Af AF Ef Tnoia TNOIA Tnoib Dmcg DMCG Dmci Dwj DWJ XSZw X1 XL Xw Ijthsrev IJTHSREV Ijth Jss JSS Jsws Mjs MJS Mjsw Mjswgs MJSWGS Pbs Ijthdrev IJTHDREV Ijth Jsd JSD Jswd Mjd MJD Mjsw Mjswgd MJSWGD Pod Saref SAREF Sobre Kvsat KVSAT Kvth Wlodku0O WLODKUO Llod Wk uO WKUO PkuQ PkvthO PKVTHO Stk2 Lodeta0 LODETAO Lamb Xn XN Tempmod TEMPMOD Tnom TNOM Ute Kt2 KT2 Vat Ud1 UD1 Tvof f TVOFF Njs Xtid XTID Tob TEJ TCJ Tcjs Jtsd JTSD Jtss Jtsswgd JTSSWGD Njts Vtss VTSS Vtsd Vtsswgs VTSSWGS Vtss Xtssws XTSSWS Xtss Tnjts TNJTS Tnjt Vfosdoff VFBDSDOFF Web we K2WE Ku0w K2 kA MOSFET Models l RBPBYL Rbpbyw RBPBYW Rbpbynf RBPBYNF 0 RBSBYO Rbdbx0 RBDBX0 Rbdby0 RBDBYO xw RBSDBXW Rbsdbxnf RBSDBXNF yw RBSDBYW Rbsdbynf RBSDBYNF NOIB Noic NOIC Em EM EF Kf KF Ntnoi NTNOI TNOIB DMCI Dmdg DMDG Dmcgt DMCGT XGW Xgl XGL Ngcon NGCON x sfwd IJTHSFWD Xjbvs XJBVS Bvs BVS JSWS Jswgs JSWGS Cis CJS s MISWS Cjsws CJSWS Cjswgs CJSWGS PBS Posws PBSWS Poswgs PBSWGS dfwd IJTHDFWD Xjbvd XJBVD Bvd BVD JSWD Jswgd JSWGD Cjd CJD d MJSWD Cjswd CJSWD Cjswed CJSWGD PBD Poswd PBSWD Poswgd PBSWGD f SBREF Wlod WLOD Ku0 KUO 0 KVTHO Tku0 TKUO Llodku0 LLODKUO vth LLODVTH Wlodvth WLODV
271. be loaded F_DataSourceType ist Listed type of DUTs see attached list Only one dc_idvg kind can be used F_DataSourceDefault_Func ist Large Default selection of DUTs More types can be used see attached list F_DataSourceDefault_STI ist SA ref Default selection of DUTs More types can be used see attached list F_DataSourceAllowMulti ist O Allow multiple selection of DUTs 0 1 Scaling for example uses 1 F_DataSourceSortDUT ist If multiple selection is allowed sort data by values of the content of the array in model variables To sort by length use F_DataSourceSortDUT 0 DUT_L because the length is stored in the model variable array DUT_L Parameters The parameters must always be specified for Extractions Optimizer Tuners For an extraction F_ParRef ParameterSet Shows the model parameters F_ParName ICCAP_ARRAY 2 Array of the parameter names F_ParName 0 PARAMETER 1 Parameter which is shown F_ParName 1 PARAMETER 2 Parameter which is shown For an optimization F_ParRef execute_VTHO_K12_DVTx_LPEx_opt Points to an optimizer Without specifying the path to the optimizer the setup which is configured in the variable F_Setup is used The configured variables in the optimizer are overwritten from these configurations F_ParName ICCAP_ARRAY 2 Array of the parameter names F_ParName 0O PARAMETER 1 Parameter which is shown
272. be2 PSCBE2 Pvag Forout FPRROUT Pdits PDITS Pditsl Rdsw RDSW Rdswmin RDSWMIN Rdw RSw RSW Rswmin RSWMIN Prwg Wr WR int LINT int Dwb DWB W1 WL ln Wwn WWN Ww WWL L1 Lw LW Lwn LW Lwl Lwc LWC Lwle LWLC wlc wlc WWLC AlphaO ALPHAO Alphat ALPHA1 Beta0 B Agidl AGIDL Bgidl BGIDL Cgidl C Aigbacc AIGBACC Bigbacc BIGBACC Cigbacc Aigbinv AIGBINV Bigbinv BIGBINV Cigbinv Nigbinv NIGBINV Aigc AIGC Bigc Aigsd AIGSD Bigsd BIGSD Cigsd Nigc NIGC Poxedge POXEDGE Pigcd Toxref TOXREF Xpart XPART Cgso CGSO Cgdo C Cgsl CGSL Cgdl CGDL Ckappas C Cf CF Cle CLC Cle C Dwc DWC Vfocv VFBCV Nof f N Acde ACDE Moin MOIN Xrergi XRCRG1 Xrerg2 XRCRG2 Rbpb RB Rbps RBPS Rbdb RBDB Rosb RBSB Gomin GB Rbps0O RBPSO Rbpsl RBPSL Rbpsw RB Rbpdd RBPDO Ropdl RBPDL Ropdw RB Rbpbx0 RBPBXO Rbpbxl RBPBXL Rbpbxw RB ALPHAO CGIDL IGBACC IGBINV IGSD PIGCD CGDO CKAPPAD DWC MOIN RBPS RBPSL RBPDW RBPBXNF RBSBX0 RBSDBXW OIA EF DMCG XGW IJTHSREV JSWS CJSWS PBSWGS JSD MJSWD PBSWD KUO LODKUO PKUO LODK2 LC KT1 UC1 TVOFF TPB TCJS JTSS VTSS VTSS TSS LINT K 2WE GS GD GS OI PARAMCHK IGCMOD RBODYMO TNOIMOD EPSROX TOX A2 FACTOR CDSCD PDIBLCB PVAG PDITSL RDW PRWG WINT WLN GDO KAPPAS LE OFF PB MIN PSW PDW PBXW MOS
273. ble The following example of the parameter UC which is a part of the mobility reduction demonstrates the problem In BSIM3v2 the effective mobility eff was calculated according to the following formula Ho Hoff 7 p 1 Ul Vost Fip Lp U Vos Vy hich U P In BSIM3v3 2 2 the formula changed to Ho B T i eff P F r a Oa r j fiyr r Fi 2 1 U t U Vhsefp Vosteff 2 th a pa U Vestept Vh Tox It can easily be recognized that UC has quite different values in both equations That means if BSIM3v2 is implemented in the simulator and the parameter is extracted for BSIM3v3 2 2 the simulation will give catastrophic results in the case of UC 119 MOSFET Models Therefore you must be sure that you use the same version of BSIM3 in both your simulator and your extraction tool The latest release BSIM3v3 3 0 is a minor change to BSIM3v3 2 4 with only a few bug fixes and some enhancements in noise modeling The model equations used are mainly the same in those versions Additionally a few effects are modeled by introducing the ACNQSMOD as well as the LINTNOI model parameters from BSIM4 See Also Whats New in BSIM3 Modeling Package mosfet The Unified I V Model of BSIM3v3 mosfet Capacitance Model mosfet High Frequency Behavior mosfet Temperature Dependence mosfet Noise Model mosfet SPICE Model Parameters for BSIM3v3 mosfet Test structures for Deep Submicron CMOS Processes mo
274. ca_lin_opt2 is an optimization call for linear region fitting at all Vbs for the parameters THE2R SLTHE2R SWTHE2 KOR SLKO SWKO KR SLK SWK VSBXR SLVSBX and SWVSBX This sequence is used for the 2 k factor model option sca_lin_opt3 is an optimization call for linear region fitting at all Vbs for the parameters THE2R SLTHE2R SWTHE2 KOR SLKO and SWKO This sequence is used for the 1 k factor model option sca_subvt_opt1 is an optimization call for subthreshold optimization at Vbs O for the parameters GAMOOR SLGAMOO MOR SLMO ZET1R and SLZET1 sca_gds_opt1 is an optimization call for gds fitting for Vbs O for the parameters GAM1R SLGAM1 SWGAM1 ALPR SLALP SWALP and VPR sca_ids_opt1 is an optimization call for ids fitting for Vbs O for the parameters THE3R SLTHE3R and SWTHES3 sca_isub_opt1 is an optimization call for substrate avalanche current fitting at Vbs O for the parameters A1R SLA1 SWA1 A2R SLA2 SWA2 A3R SLA3 and SWA3 349 MOSFET Models sca_opt_subvt2 is an optimization call for subthreshold current fitting for all Vbs for the parameters VSBTR and SLVSBT sca_limit_check is called at the end of a maxiset extraction or optimization to check the parameters with respect to the maxiset limits It is used by the macros extract_maxiset and optimize_maxiset extract single_temp_extract contains the optimization sequences necessary for the extraction of the temperature sensitive parameters at a
275. cal and Global Short Width Dependence Local Length Width Dependence PSP Scale Length Width Global Optimizations 240n 150n 90n 65n Wim 45n 60n 90n 150n 240n Wim 45n 60n 90n 150n 240n 45n 60n 90n 150n 240n MOSFET Models NEFF DPHIB XCOR ALP ALP1 ALP2 CF AX etc NEFF BETN DPHIB RS etc AXO AXL RSW1 RSW2 NSUB NSUBOW DPHIBO DPHIBL DPHIBW XCORO XCORL XCORW XCORLW etc 287 Local extraction using all devices with max W to extract length dependent parameters without width dependency Global extraction using the wide devices with different length Local and global extractions of the short devices steps 7 and 8 global extraction using all devices MOSFET Models Global optimize Optimizations Wim corner devices as well as Su HO 0O 0 0 Siar wary i length 1 I 1 i width and 1 ot i l length width E a l l scaling ae 4 240n O i O ong OO a a a O S00 OQ Qo G 65n 0 O a ina a a een I 45n 60n 90n 150n 240n 5u L m Related Topics Simultaneous Adjustment of Local and Global Parameters mosfet Binning of PSP Models mosfet Parameters for the PSP model mosfet Back to PSP Characterization mosfet 288 MOSFET Models BSIMSOI4 Characterization The BSIMSOI Modeling Package provides the user with a complete extraction strategy for all model parameters of the BSIMSOI model
276. can be edited too In the PEL code the following variables can be used PlotO_x1 First x value of PlotO plot specified in variable F_UsedPlot 0 PlotO_x2 Second x value of Plot0O PlotO_y1 First y value of PlotO PlotO_y2 Second y value of Plot0O Ploti_xi Ploti_x2 Ploti_y1 Plot1_y2 Ploti is specified in variable F_UsedPlot 1 Plot _x1 Plot _x2 Plot _y1 Plot _y2 Plot is specified in variable F_UsedPlot Example F_RegionPEL_default PlotO_x1 0 PlotO_x2 0 9 VTHO PlotO_y1 1e 12 PlotO_y2 max abs id m 91 MOSFET Models From the content of the variable F_RegionPEL_default a transform will be created This transform is copied into the setup which is specified in the variable F_Setup So if no path is used the PEL code is using the local variables inputs outputs parameters etc of the setup F_Setup Attachments initializing Available content of F_DataSourceType list Transistor dc_idvg C Junction c_bd_area c_bd_perim C_bd_perim_gate c_bs_area c_bs_perim cC_bs_perim_gate C Oxide C_oxide C Overlap C_g_ds C_g_dsb C Intrinsic c_d_g Diode di_bs_area di_bs_perim di_bs_perim_gate di_bd_area di_bd_perim di_bd_perim_gate Available content of F_DataSourceDefault_Func list Empty disables this section for default selection All DUTs will be selected by default Transistor Large Short Narrow Small L Scale
277. ce High Frequency Internal Iteration Method xL 0 corsrp 3 congs jo cory i XW 0 TPOLY E 007 cOOVLP 1 coc p COPPRY 1 NSUBC 1E 017 COOVLPS 1 CORBNET 1 NSUBP 1E 017 LDRIFT1 o COQOVSM 1 v DFM LDRIFT2 2 7E 006 COISUB 1 CODFM Y 0o mous cones jo Noise LOVERLD 9E 007 MUEPH1 4000 COGIDL jo B COFLICK o B RS 0 001 cos1 lo B COTHRML 0 HISIM HY RDICT2 1 A A A DDLTMAX 10 COADOV E COIGN o B COSELFHEAT 1 E RDVG11 0 1 COTEMP o COSYM o amp COLDRIFT o BSIMSOI4 Initialize Folder for the BSIMSOI4 Modeling Package Initial Yalues Parameters Flags TOX 1E 008 Model Noise TOXM 1E 008 a a SOIMOD 0 FNOIMOD 1 TBOX 3E 007 s l TSI 1E 007 BINUNIT jo TNOIMOD a 8J 1E 007 PARAMCHK 0 NCH 1 7E 017 NGATE 0 DC Capacitance RSH 0 MOBMOD 1 XGW 0 capmop 2 4 XGL 0 SHMOD 0 IGBEMOD 0 IGMop io IGCMOD 1 You can enter parameters and or change flags The parameters you ve entered or changed will be taken into account only after you ve pressed Reset Parameters and Results button located on the Extract Tab Related Topics e DC Notes mosfet e DC Information mosfet e DC Binning mosfet e DC Extract mosfet e DC HTML mosfet e DC Options mosfet e DC Boundaries mosfet e Back to Extraction of DC and CV Parameters mosfet Binning You will find some theory on binning inside Binning of Model Parameters mosfet The following figure sho
278. ce for width offset Im Ww WWN Power of width dependence for width offset ww Coeff of length and width cross term for width offset Im IL LINT length offset fitting parameter from IV without bias Im LL Coeff of length dependence for length offset Im IL LLN Power of length dependence for length offset Lw Coeff of width dependence for length offset Im LWN Power of width dependence for length offset Lw Coefficient of length and width cross term for length offset Im Dw Coefficient of the gate dependence of Weff m V Dw Coefficient of the body bias dependence of Weff m vo 5 ae Width offset for body contact isolation edge Im ee Output resistance PCLM Channel length modulation coefficient 1 3 PDIBLC1 First output resistance DIBL effect correction parameter 0 39 PDIBLC2 Second output resistance DIBL effect correction parameter 0 086 PDIBLCB Body effect coefficient of output resistance DIBL effect correction 0 1 V parameter DROUT L dependence coefficient of the DIBL correction parameter in output pee resistance DELTA Effective Vas Parameter 0 01 VDSATIIO Nominal drain saturation voltage at threshold for impact ionization current 0 9 Vv PVAG Gate dependence of Early voltage 0 ALPHAO f first parameter of impact ionization current _ Im N F FBITII Fraction of bipolar current affecting impact ionization penne a Vps dependent parameter of impact ionization current a i BETAL Second Second Vps dependent parameter o
279. centration NGATE and so on Entering values into the fields and selecting Save starts a routine to check the values entered This routine will flag an error message and change the color of the field whose parameter is given an unrealistic value The specific field will be marked with red color and remains red until the value is corrected 100 MOSFET Models The Model Flags section is used to set BSIM3 model flags There are fields for global model flags like BINUNIT or PARAMCHK as well as fields for DC Capacitance and Noise model flags The model flags are set to a default value as has been described in the BSIM3 manual from UC Berkeley 1 See Model Selection Flags mosfet for details or the above mentioned UCB manual 1 If you are using HSPICE a field is provided to set parameters for Gate current extraction A section called Initial Parameter Set is located below the Initial Values section You can use a parameter set from any other extraction with IC CAP a circuit simulator cir file or a text model file Using the cir or model file requires you to specify an appropriate simulator You enter the required information using the menu Initialize gt Initial Parameter Set gt Add The form that opens enables you to enter the necessary information browse to the file location and select the simulator To change between using the Initial Values and Initial Parameter Sets select the radio button to the left of each section Sele
280. cg_vg Go to the Plots folder and copy the Cox_vg plot as shown below The copied plot has been renamed to Cox1 Plot Cox_vg has been copied to Coxi 66 Configuration Wizard for Extraction Functions 1 2 u Et Available Extractions Overview Customized Functions Available Extractions E O Global New Main Group a Local Capaci tottus BB MOSFET Models Change to the Configuration Wizard window select the customized function O TOXO NSUBO VFBO DQL generated before Press the Configure button marked red in the following Figure Configuration of Plots inside a customized function Available Extractions O Global New Main Group New Group fe E NEFF m O COX fe E Parameter Initial Values E GP Local Long Wide Add the previously copied plot Cox1 by selection inside the Add Plot window Selection of an additional plot to be used in this extraction step PSP_DC_CY_ Extract PSP_DC_CY_Extract C_Odide cg_ve is Active 16 File Edit Measure Extract Simulate Optimize Data Tools Macros Windows Help DUTs Setups Circuit Model Parameters Model variables Macros Select DUT Setup __DC_Transistor a H Global a oe Local Scaling __DC_Transistor_WPE__ t WPE_Scaling __DC_Transistor_STI___ J STI Large_SA Narrow_SA Short_SA Small _5A __ Capacitance t C_Junction_BD C_Junction_BS J C_Oxide
281. channel model 0 6 Back to BSIM4 Characterization mosfet 210 MOSFET Models The BSIM4 RF Simulation Model Structure of the BSIM4 RF Simulation Model The BSIM4 model consists of some major features that make it ideal for use in real high frequency simulations It contains e scalable gate resistance e dedicated thermal noise model formulation e different device layouts multifinger devices are taken into account e substrate resistance network with correct connection to the main transistor through parasitic diodes e New in BSIM4 3 0 Horseshoe substrate contacts While the first three effects are fully scalable which means the influence of the device dimensions like gate length or width is already included in the model formulation the substrate resistance effect included into BSIM4 has not included any of this information up to version 4 3 0 To specify the substrate resistance effect only fixed values for up to 5 different resistors could have been set However in reality the substrate resistance effect depends on sheet resistance of the body number of gate fingers and width of the devices Due to this shortcoming it is not possible to generate one fully scalable model card for a family of typical RF multifinger transistors This is the reason why the BSIM4 Modeling Package includes two different approaches for generating BSIM4 RF models e Single transistor models describe the very classic approach where one simulation
282. cient for the width dependence of effective doping of overlap region Coefficient for the length times width dependence of effective doping of overlap region Coefficient for the geometry independent part of DIBL parameter Coefficient for the length dependence of DIBL parameter Coefficient for the width dependence of DIBL parameter Coefficient for the length times width dependence of DIBL parameter Coefficient for the geometry independent part of back bias dependence of CF Coefficient for the geometry independent part of product of channel aspect ratio and zero field mobility at TR Coefficient for the length dependence of product of channel aspect ratio and zero field mobility at TR Coefficient for the width dependence of product of channel aspect ratio and zero field mobility at TR Coefficient for the length times width dependence of product of channel aspect ratio and zero field mobility at TR Coefficient for the geometry independent part of temperature dependence of BETN Coefficient for the length dependence of temperature dependence of BETN Coefficient for the width dependence of temperature dependence of BETN Coefficient for the length times width dependence of temperature dependence of BETN Coefficient for the geometry independent part of mobility reduction coefficient at TR Coefficient for the length dependence of mobility reduction coefficient at TR Coefficient for the width dependence of mobility red
283. cified in any desired order This gives the highest available flexibility for adopting any parameter extraction to a certain process e Automatic generation of binned model files is now supported A new folder Binning in the BSIM3_DC_CV_Extract module allows the specification of the binning areas as well as extended binning Final circuits are generated for Hspice Spectre and ADS e Generation of HTML files enhanced to include a navigation tree through all results In addition all measured data at each temperature for each device is compared with the simulated results e The new IC CAP feature Plot Optimizer is supported by a user friendly configuration of the devices and setups for a final fine tuning approach e A new function is implemented to extract multiple projects in batch mode This can be very useful for statistical modeling where a large number of model parameter sets must be generated for the same type of devices but from different measured test chips Please see the macro Example_Wafer_Extraction in the BSIM3_DC_CV_Extract md file e Parameter extractions have been steadily enhanced due to user s feedback e BSIM3_RF_Extract A complete new extraction flow is implemented Please see 3 BSIM3_DC_CV_Extract for more details The automatic generation of HTML files has been enhanced to include a navigation tree through all results e Documentation The documentation was totally reworked to account for the common user interface w
284. citance ec c ec um um f Diode 5 C Measurement Junction BD 2f j 29 127 Ww L DareaBD_A28n0_P760u0_NF1 M 10 10 DperimgateBD_A26n0_P7m6_NF100 M 5000 10 DperimBD_A28n0_P m6_NF100 M 1000 10 Junction BS W L DperimgateBS_A28n0_P7m6_NF100 5000 10 DperimBS_A26n0_P m6_NF1i00 1000 10 DareaBS_A28n0_P760u0_NF1 10 10 s Project bsim4 _for_experts Project directory g users default e To add new DUTs Click the Add icon You will be prompted with a list to select DUTs to add Select the desired DUTs and click Add New lines are added according to the selection you ve made Note If you have entered all necessary categories clicking Add will not open a window to select new diode DUTs since all are present Measuring more diode DUTs will not create new information since the measured values will be the same as the one s that have been measured already For each line enter a name for the DUT and necessary geometrical data For your convenience only relevant data is to be entered for specific diodes Relevant data fields have a white background irrelevant data fields show a dashed line For example DUTs to measure bulk drain diodes do not require source area AS and perimeter length of source PS geometrical data You only have to enter drain area AD and drain perimeter PD as well as the number of device fingers NF of the diode to be measured Remember all geometri
285. citance for intrinsic channel Coefficient for the geometry independent part of V V A V3 A V3 A V3 A V3 V K 0 375 6 3E 2 3 1 1E 14 1E 15 282 PLCGOV PWCGOV PLWCGOV POCGBOV PLCGBOV PWCGBOV PLWCGBOV POCFR PLCFR PWCFR PLWCFR Noise Model Parameters POFNT PONFA PLNFA PWNFA PLWNFA PONFB PLNFB PWNFB PLWNFB PONFC PLNFC PWNFC PLWNFC Other Parameters DTA Stress Model The stress model is adopted from BSIM4 4 and has undergone only minor changes Parameters for stress model MOSFET Models oxide capacitance for gate drain source overlap Coefficient for the length dependence of oxide Capacitance for gate drain source overlap Coefficient for the width dependence of oxide Capacitance for gate drain source overlap Coefficient for the length times width dependence of oxide capacitance for gate drain source overlap Coefficient for the geometry independent part of oxide capacitance for gate bulk overlap Coefficient for the length dependence of oxide capacitance for gate bulk overlap Coefficient for the width dependence of oxide Capacitance for gate bulk overlap Coefficient for the length times width dependence of oxide capacitance for gate bulk overlap Coefficient for the geometry independent part of outer fringe capacitance Coefficient for the length dependence of outer fringe Capacitance Coefficient for the width dependence of out
286. ck background to white You can select if you want to include Delta W and Delta L into the VTH extraction process You can also set a value for the normalized reference current as well as Channel width and length reduction values for VTH extraction Those values should be entered as a dimension in meters Other DC CV Measurement Module Folders Notes mosfet Temperature Setup mosfet Switch Matrix mosfet e Device Definition mosfet Import Wizard This feature enables you to import data measured using data formats or software not compatible with the IC CAP format The base for this task are project description files in spreadsheet format csv files As a template for these csv files the File gt Export menu contains selections to create devices lists for DC Capacitance and Diode data Load a project into the IC CAP Measurement module then select either DC device list Capacitance device list or Diode device list A csv style file will be created This file can be opened with EXCEL for example It contains all device data that was entered into the DC Capacitance or Diode DUTs folder You can edit the project document or you can create a new one using the same format The first row of the sheet contains keywords The values below these keywords will be read into IC CAP and are assigned to the appropriate values in the MOS Modeling Toolkits By default the list contains a certain set of keywords However you can add more ke
287. coefficient Isolation edge sidewall junction Capacitance grading coefficient Isolation edge sidewall junction Capacitance per unit area Gate edge sidewall junction capacitance per unit length Gate edge sidewall junction capacitance grading coefficient Source bottom junction built in potential Drain bottom junction built in potential Isolation edge sidewall junction built in potential of source junction Isolation edge sidewall junction built in potential of drain junction Gate edge sidewall junction built in potential of source junction Gate edge sidewall junction built in potential of drain junction Asymmetric Source Drain Junction Diode Model Bottom trap assisted saturation current density Source side Drain side STI sidewall trap assisted saturation current density Source side Drain side Gate sidewall trap assisted saturation current density Source side Drain side Non ideality factor for JTSS JTSD Non ideality factor for JTSSWS JTSSWD Non ideality factor for JTSSWGS JTSSWGD Power dependence of JTSS JTSD on temperature Source side Drain side Power dependence of JTSSWS JTSSWD on temperature Source side Drain side Power dependence of JTSSWGS JTSSWGD on temperature Source side Drain side Bottom trap assisted voltage dependent parameter Source side Drain side STI sidewall trap assisted voltage dependent parameter Source side Drain side STI sidewall t
288. concentration near interface 1 7E17 li cm3 INSUB Doping concentration away from interface 6E16 l1 cm3 INGATE Poly gate doping concentration 0 tyem3 VFB Flat band voltage 1 0 Vv ammal Body effect near interface 5 1 2 g y s 2a Es NCh V or panre Body effect far from interface 24e5 Nsup a 2 Ya Cor XT Doping depth 1 55E 7 V RSH Source Drain Sheet resistance 0 Q square Temperature Modeling Parameters Parameter Description Default Value Unit UTE Mobility temperature coefficient 1 5 KT1 Threshold voltage temperature coefficient 0 11 Vv KTIL Channel length dependence of KT1 0 0 vm KT2 Threshold voltage temperature coefficient 0 022 lUA1 Temperature coefficient for UA 4 31E 19 m V UB1 Temperature coefficient for UB 7 61E 18 m vy2 UCI Temperature coefficient for UC 0 056 m v PRT Temperature coefficient for RDSW 0 0 Qu m AT Saturation velocity temperature coefficient 3 3E4 m s XTI Junction current temperature exponent 3 0 coefficient TPB Temperature coefficient for PB 0 v K TPBSW Temperature coefficient for PBSW 0 V K TPBSWG Temperature coefficient for PBSWG 0 V K TCI Temperature coefficient for CJ 0 1 K TCISW Temperature coefficient for CJSW 0 1 K TCISWG Temperature coefficient for CISWG 0 1 K Flicker Noise Model Parameters Parameter Description Default Value NMOS PMOS Unit NOIA Noise parameter A 1 1E20 9 9E18 5 NOIB Noise parameter B 5 E4 2 4E3 NOIC Noise parameter C 1 4E
289. constants for your calibration kit are not loaded into the network analyzer load them from disc now by pressing DISC gt LOAD and specifying the data type and file name If you wish to modify one of the internal cal kit definitions do so now Press CAL gt CAL1 or CAL2 depending on your cal kit and perform a two port calibration measuring each of the standard devices in turn and pressing the softkeys as each measurement is complete At the end of the calibration sequence the cal set numbers are listed in the softkey menu Press CAL SET 1 to store the calibration in cal set 1 Or use another available cal set CW Calibration Subset for an Agilent 8510 Based System 1 To create a CW frequency subset of the broadband frequency list calibration press CAL gt CORRECTION ON gt CAL SET 1 this turns on the broadband cal you just completed then MORE gt MODIFY CAL SET gt FREQUENCY SUBSET Use the SUBSET START and SUBSET STOP softkeys in the SUBSET menu NOT the front panel keys to set both start and stop to the same frequency Press CREATE amp SAVE and store this calibration in cal set 2 or another available cal set Note the numbers of the cal sets where you save the calibrations you will need to list one of these numbers as part of the instrument state for each of the network analyzer measurements Note For more detailed information refer to the Agilent 8510 Operating and Programming Manual Frequency Li
290. correct values for W L and MULT For the measurement of any device dutx is first copied to a new DUT Then the dimension information in this DUT has to be set to correct values tid_lin converts the measured data to make a target array for the linear region extractions It is common practice in Philips to filter any data points with current less than 10 of maximum when doing the linear region optimizations This transform mimics this procedure by setting any points less than 10 of maximum to a value of 0 5 IMIN Because IMIN will be used to set an optimization floor the resulting data points are ignored calc_all causes all the currents in the DUT to be re evaluated with calls to MM9 print_par calls the MM9_SAVE_SPARS transform that writes the miniset parameters to a file copy_sim_to_meas copies the current generated by the MM9 transform into the measured array It is used for making sample measured data It uses the MM9_COPY C transform which is necessary to enable data to be copied into a measured array set_par_from_quick_ext transfers miniset parameter values from the DUT quick_ext to a DUT containing the conventional optimization type measured data found in idvg setup of dutx dutx idvdi performs the saturation region measurements for the first Vbs value OV that are needed for the optimization of the output conductance and saturation parameters The idvdi setup contains the following transforms gds is a call to the
291. ct OK to close the configuration window 4 To save this hardware configuration in a file for future use select File gt Save A file filter is displayed showing the pathname of the current directory Type in an appropriate name for the hdw file you are creating and select OK 5 Close the hardware window Defining the DC Source Monitor Instrument State Note For details on IC CAP instrument options instrument states for specific instruments refer to Supported Instruments measurement IC CAP provides remote control of the DC source monitor and the network analyzer to measure the device under test This procedure configures IC CAP with the instrument state settings instrument options for the DC source monitor Use this procedure if you have been referred here from one of the device modeling procedures You will need to set the DC source monitor instrument state separately for each DC or DC biased measurement setup in a modeling procedure However use the same settings for all the measurement setups in one model except that Integ Time can differ among setups Unless you use the default settings documented here it is helpful to write down the settings to duplicate in the other setups Note DC signal levels and other input parameters that differ among measurement setups are not set in this procedure but in the individual setup procedures in each model chapter The settings used in this procedure are defaults and the e
292. ct which initialization procedure you want to use If you would like to use the binning capability check the Generate Binning Model button With this button checked the folder Binning is activated There is a field provided to enter PEL commands which are executed at initialization of the extraction process Note that the sequence of initialization uses values of the model parameters first before PEL commands are executed From the menu Initialize chose Set Initial Values to Circuit Defaults if you would like to reset the parameters You can Add or Remove a Parameter from the list shown in the middle of the folder by selecting the Initialize menu You will get a list with parameters to select from This might be helpful if you would like to extract some specific parameters at initialization BSIM4 PSP Initialize Folder for the BSIM4 Modeling Package Initial Yalues Parameters Flags EPSROX 3 9 Model DC Capacitance High Frequency ioe are BINUNIT 1 MOBMOD l RGaTEMoD o TOXP 3E 009 a en Too 3 009 PARAMCHK 1 MTRLMOD lo RBODYMoD o DTOX 0 RDSMOD l o TrNgsmop o xJ 1 5E 007 ees arte IGCMOD l1 acngsmop o 3 NGATE o IGBMOD 1 Noise NSD 1E 020 CAPMOD 2 FNOIMOD XW 0 XL o CYCHARGEMOD 0 TNOIMOD 0 xT 1 55E 007 DIOMOD 1 F RSH 0 r Transistor Layout PERMOD 11 i GEOMOD 0 TEMPMOD o WPEMOD i g Initialization of PSP model parameters
293. cts and holds the normalized gate sub region contribution to forward current from the measurements in the area fwd_iv locos fwd_iv and gate fwd_iv setups ign_sim A transform that calls JUNCAP to evaluate the gate sub region component of current fit_ign An optimization definition that causes the parameters JSDGR NG and JSGGR to be optimized with respect to the normalized gate sub region forward current The parameter limits are controlled by the following model variables which you can change in the model variables table JSDGR_MIN JSDGR_MAX NG_MIN NG_MAX JSGGR_MIN JSGGR_MAX The data limits are controlled by the following variables which are also in the model variables table FIV_VMIN FIV_VMAX init_iv_pars A transform to initialize some of the I V parameters before optimization begins The parameters initialized are JSDBR 10n JSDSR JSDGR 10f INB NS NG 1 JSGBR 1u JSGSR JSGGR 100p opt_all_fwd_iv An optimization definition that causes all the I V parameters to be optimized with respect to the measured data in the area fwd_iv locos fwd_iv and gate fwd_iv setups The parameters optimized are JSDBR JSDSR JSDGR NB NS NG JSGBR JSGSR JSGGR The parameter limits are controlled by the following model variables JSDBR_MIN JSDBR_MAX JSDSR_MIN JSDSR_MAX JSDGR_MIN JSDGR_MAX NB_MIN NB_MAX NS_MIN NS_MAX NG_MIN NG _MAX JSGBR_MIN JSGBR_MAX JSGSR_MIN JSGSR_MAX JSGGR_MIN JSGGR_MAX The data limits are controlled by t
294. d Project directory g fusers ICCAP2011 Status Add Fixed Binning to Extraxction Flow Change to the Extract folder 300 MOSFET Models Select from the menu Extract Extraction Flow Add 48 BSIMSOI4_DC_CV_Extract 16 File Initialize Binning MS Plots HTML Options Boundaries Tools Help XE S F S ae elg HTML Options Boundaries Oo ae A Execute Extraction Notes Information F Move Up Extraction Flow Eh Move Dow Selected Extractio Data X Flow Delete Available Function mt Reset Paramets Function Flow gt EN A Float Large Edit Global Binning Parameter Figure Dependencies of Initial Conditic 4 Float Large Default Extraction Flow 3 4k Float Short Import Model Parameter Set H 4K Float Lengt Export Model Parameter Set 45 Float Short Export Extracted Deck 4 Float Lengt al Save eed fore Follow Extraction Flow Configuration Wizard Click Binning Fixed Devices at the AddExtraction window The previously defined bins will be inserted into the Extraction Flow Extraction Flow Data fo Reset Parameters and Results E C Global E y Float i Binning Fixed Devices Fixed_WSu00_LOu25 Fixed_WSu00_L5u00 Fixed_W0u18_L5u00 Fixed_W0u18_LOu25 Fixed_WSu00_LOu15 Fixed_WSu00_LOu18 Fixed_W0u18_LOu18 Fixed_W0u18_LOu15 ave Parameters D eem Tee eae ae ee ee ae age T E Now you are able to use the f
295. d RDICT1 Or LDRIFT2 and RDICT2 are zero the whole expression is zero The following table gives an overview of the different parameters used with each possible CORSRD flag CORSRD Model parameters used for this selection 0 No resistances i RS NRS RSH RDVG11 RDVG12 RDVB RDS RDSP NRD RD RDVD RDVDL RDVDLP RDVDS RDVDSP RDSLP1 RDICT1 RDSLP2 RDICT2 RDOV11 RDOV12 Same as CORSRD 1 but nodes solved internally E RD21 RD22 RD23 RD23L RD23LP RD23S RD23SP RD24 RD25 RD20 This model flag considers both CORSRD 1 and CORSRD 2 RDVG11 RDVB RDVD RDTEMP1 RDTEMP2 RDVDTEMP1 RDVDTEMP2 The flag CORSRD 3 is the most comprehensive using the most model parameters In most cases you should use the CORSRD flag with the value 3 which is the default setting in HiSIM_HV w N e 249 MOSFET Models Additional SPICE Model Parameters for HiSIM_HV The following tables list the model parameters used in the HiSIM_HV MOS model together with the default values and the range possible for that parameter Parameters Introduced for HiSIM_HV 250 MOSFET Models ead pan Ee atv Poserietee uae NSUBCW 1 0 cmNNSUBCWP INSUBCWP 0 SCSTI3 0 p SUBLD1 0 SUBLD2 0 MPHDFM 0 3 E 3 RTHO Ker CTHO 1 1E 7 Ws Kcm RTHOW 0 Ee e RTHOWP o o a RTHONF o ooo POwRAT dho bo oOo hao O DO E E E U E XLDLD ie 6 im LOVERLD l1e 6 im NOV
296. d STA1 The variable table of this setup contains the MIN and MAX limits that are to be used for these parameters during optimization There is one input defined in this setup index that is used to set up the array size for the output temp This output holds the list of non nominal temperatures at which you want measurements to be performed This array will be updated whenever you execute the SETUP macro The all_temp_extract setup contains the following transforms dummy is an empty except for comments PEL that is used to re establish the array size in this setup when the variable NUMTEMP changes read_all_temp_opt_files forces the optimization tables to be rebuilt and read 350 MOSFET Models from the file system whenever SETUP macro is run all_temp_lin_opti fits the linear region data at Vbs 0 by optimizing the parameters and ETABET STVTO STTHE1R STLTHE1 all_temp_lin_optz2 fits the linear region data at all Vbs by optimizing the parameters STTHE2R and STLTHE2 all_temp_subvt_opt1 fits the subthreshold region data at Vbs 0 by optimizing the parameter STMO all_temp_ids_opt1 fits the ids saturation data at Vbs 0 by optimizing the parameters STTHE3R and STLTHE3 all_temp_isub_opti fits the avalanche current data at Vbs O by optimizing the parameter STAL all_temp_Iimit_check is used to check the overall temperature parameters with respect to their limits It is used by the macros extract_temperature_coeffic
297. d in a word processing program e BSIM3_RF_Measure This module measures all data which is necessary for the generation of RF models The data is compatible with the BSIM4_RF_Measure module and can also be used for the generation of BSIM4 RF models 117 MOSFET Models e BSIM3_RF_Extract A new fully scalable subcircuit model for the BSIM3 RF behavior was added The user can now select whether he wants to create a single device model one model for each test device or a fully scalable model that covers all available test devices e BSIM3_Tutorial These are the well known files for learning more about the BSIM3 model itself e Documentation The Help buttons are still linked to the BSIM4 Online Help This is OK because the usage of the BSIM3 Modeling Package and the BSIM4 Modeling Package is identical For more information about the BSIM3 model itself please refer to this section A reworked version of the documentation is included in the IC CAP 2004 release See Also e Introduction to BSIM3 Model mosfet e The Unified I V Model of BSIM3v3 mosfet e Capacitance Model mosfet e High Frequency Behavior mosfet e Temperature Dependence mosfet e Noise Model mosfet e SPICE Model Parameters for BSIM3v3 mosfet e Test structures for Deep Submicron CMOS Processes mosfet e Extraction of Model Parameters mosfet e Binning of Model Parameters mosfet e Importing older version BSIM3v3 Files mosfet e BSIM3v3 Characteriza
298. d to test the quick extraction algorithms using synthetic data generated from a previously extracted optimized set of miniset parameters make_extra_par_vs_geometry_plots This macro is used to create parameters versus length plots for a user specified width and parameter versus width plots for a user specified length This is useful if the device set includes more than one L array and more than one W array display_extra_par_vs_geometry_plots Displays plots of the chosen miniset parameters versus L2 and W2 read_data_from_directory Reads data previously stored in a subdirectory under the current working directory write_data_to_directory Writes data to a subdirectory under the current working directory 357 MOSFET Models Parameter Extraction The purpose of parameter extraction is to determine the maxiset parameters needed to characterize a particular process The implementation of MM9 in IC CAP allows the extraction of all the model parameters that control DC behavior over a wide temperature range The aim of this implementation is to extract values for parameters 1 through 70 in section 4 4 List of scaling and reference parameters of the Philips MOS Model 9 documentation see References mosfet 4 The main extraction sequence is defined as a set of optimization transforms with a special function MM9GEOMSCAL used to determine a first guess for the maxiset parameters by regression The main steps for parameter extraction
299. d variables are presented together with some graphic representations of the program and how it looks like inside the PSP Modeling Package If users modify an existing tuner or extraction function or add a new function they need to consider that the changes are overwritten with the default IC CAP installation Therefore changes should be saved before updating IC CAP and added again afterwards 9 Only global extraction steps can be added to an existing Modeling Package This means in case of the PSP Modeling Package extraction steps can only be added to the Main Group Global or PSP Scale Parameters but not to the Main Group Local xxx In the BSIM3 and BSIM4 Modeling Packages all extraction steps are global The following paragraphs explain how to add new extraction steps with user defined functions to the existing Extraction Flow using PSP_DC_CV_Extract as an example First it is shown how to add an extraction step to the main group Global which contains a tuner with modified parameters an additional plot and modified boundaries of the optimization region Secondly it is shown how to add an extraction step to the main group PSP Scale Parameters which contains a user defined extraction function with modified code as well as already existing functions It is also shown how to define the default Function Flow Modified Extraction Flow with user defined extraction steps m PSP DC _CV_Extract 22 fe felix
300. d_vg contain the information used to define the inputs and outputs for each measurement and extraction as well as the measurement hardware configurations and the transforms and plots associated with each setup Agilent Root MOSFET DUT Setup Panel Select DUT Setup Y pre_verify on s_vgvdf extr_para teres parasitics Y main Initializing Device Parameters You begin the procedure by giving the device an identifying name and entering the number of fingers and gate width For this you use the init_parameters macro When this macro is executed it also initializes internal program functions that are essential in the model generation process and it provides annotations for the data plots IC CAP macros are used to combine or simplify operations 1 Click the Macros tab to display the macro names 2 From the Select Macro list select initt_parameters and Execute 3 In the dialog box that appears enter a name to identify the device under test then click OK or press Return 4 In the next dialog box enter the number of gate fingers 322 MOSFET Models 5 Next enter the gate width in meters 6 The next dialog box prompts you for a directory name Click OK to store the model files in the directory shown enter the name of another existing directory Click OK or press Return 7 The macro is executed and the values you selected are entered in the model variable table You can open the table by clicking on the Mod
301. dd a new measurement set to the list of available sets If the Device List subfolder is selected then you can define which set to use for which device The Device List under the Transistor branch in the tree view is used to enter DUT names geometries and connections to the appropriate DUTs Since there are differences between the BSIM3 and BSIM4 PSP models some parameters are to be used only inside the appropriate model and only activated there The BSIM4 PSP models enables stress effect modeling which is not possible in BSIM3 Therefore all stress effect parameters are only used inside the BSIM4 PSP Modeling Packages and are activated only there If you would like to enter additional parameters to the default model parameters select the Device List from the tree choose Configuration gt Add Device Parameter and enter the desired additional parameter Those parameters will be shown on the device list see figure below the added parameter is named NEW and will be inserted into all mdm files The mdm files will be written to disk this will take a while c C C Measure um um um um um 27 23 127 Set ID wW L NF M AD AS PD PS NEW SA SB 0 0 0 Set2 5 5 1 1 5 11 10 3 o Seti 5 5 1 1 5 11 10 3 0 Seti 5 5 1 1 5 11 10 3 0 Seti 5 5 1 1 5 11 10 3 There is a document to be found inside the Knowledge Center describing the procedure of adding new parameters The Configuration menu enables you to set BSIM4
302. dent parameter for gate current in 17 V ERER VOXH Limit of VOX in gate current calculation 5 0 DELTAVOX Smoothing parameter in VOX smoothing function 0 005 VEVB electron tunneling parameter for valence band auxiliary voltage 0 075 calculation VECB electron tunneling parameter for conduction band auxiliary 1 0 voltage calculation region VOFFFD ls Smoothing parameter in FD module Vv NORD Smoothing parameter in FD module K1 First backgate body effect parameter p Ion ls Second backgate body effect parameter for short channel effect dk2b Third backgate body effect parameter for short channel effect 0 dvbd0 First short channel effect parameter in FD module 0 dvbd1 Second short channel effect parameter in FD module 0 moinfd Er bias dependence coefficient of surface potential in FD 1E3 module vbsOpd Upper bound of built in potential lowering for BSIMPD operation 0 0 Vv vbsOfd Lowering bound of built in potential lowering for ideal FD 0 5 Vv 315 a aaa operation me praesen oo resistance per unit width Wr WR Width offset from Weff for RDS calculation offset from Weff for RDS calculation AR Body effect coefficient of RDSW ooo PRWG Gate bias effect coefficient of RDSW 1 v0 5 E ee Ss E Channel geometry WINT width offset fitting parameter from IV without bias 0 Im WL Coeff of length dependence for width offset Im WLN Power of length dependence for width offset ww Coeff of width dependen
303. derivative function to evaluate the derivative of the measured current mm9_gds is a call to the derivative function to evaluate the derivative of the simulated current mm9_ids calls the MM9 transform to evaluate the model current copy_sim_to_meas copies the current generated by the MM9 transform into the measured array It is used for making sample measured data It uses the MM9_COPY C transform which is necessary to enable data to be copied into a measured array set_vth stores the threshold voltage in the setup variable VTH dutx idvd2 idvd3 perform the saturation region measurements at the two non zero Vbs values The data in these setups is not used during the parameter optimization sequences 354 MOSFET Models but is used as an extra check on model accuracy The idvd2 idvd3 setups contain the following transforms gds is a call to the derivative function to evaluate the derivative of the measured current mm9_gds is a call to the derivative function to evaluate the derivative of the simulated current mm9_ids calls the MM9 transform to evaluate the model current copy_sim_to_meas copies the current generated by the MM9 transform into the measured array It is used for making sample measured data It uses the MM9_COPY C transform which is necessary to enable data to be copied into a measured array dutx subvti performs the subthreshold measurements for the first value of Vbs OV These measurements are used for the sub
304. drain induced barrier lowering DIBL and substrate current induced body effect SCBE These effects can 296 MOSFET Models be seen clearly looking at the output resistance Rout of the device Channel length modulation CLM With drain bias approaching the drain saturation voltage a region of high electric field forms near the drain and the electron velocity in this region saturates In saturation the length deltaL of the high field region increases by an expansion in the direction of the source with increasing drain source voltage Vds and the MOSFET behaves as if the effective channel length has been reduced by deltaL This phenomenon is termed channel length modulation CLM CLM is not a special short channel phenomenon since the effect is present no matter how long the MOSFET s channel is However its relative importance increases and the effect on the saturated output conductance becomes distinctly more pronounced at shorter gate lengths The effect of CLM is visible in the foloowing figure rout s CE 3 rout m vo CE 0J e Drain Induced Barrier Lowering DIBL This effect is related to a drain voltage induced lowering of the injection barrier between the source and the channel and is termed the drain induced barrier lowering DIBL CE 3 rout s rout m vo CE O Body Current The total body current consists of six currents in BSIMSOI liit fagidl sgidl bs ba bp 7 This is one of the
305. drain side junction capacitance per unit 5 0E 10 length CJISWG Source drain gate side junction capacitance per CJSW unit length M3 Bottom junction capacitance grading coefficient 0 MISW Source drain side junction capacitance grading 0 33 coefficient poni Source drain gate side junction cap grading MJSW es PB Bottom junction built in potential 1 0 vo P PBSW ls Source drain side junction built in potential 1 0 y PBSWG Source drain gate side junction built in PBSW potential CGSO Gate source overlap capacitance per unit W XJ COX 2 CGDO Gate drain overlap capacitance per unit W x XJ COX 2 fim GGBO Gate bulk overlap capacitance per unit W 0 0 ae can cae doped source gate region overlap 0 0 F m capacitance ee at doped drain gate region overlap 0 0 F m capacitance CKAPPA Coefficient for lightly doped region overlap 0 6 F m CF Fringing field capacitance F m IcLc Constant term for the short channel model 0 1E 6 m CLE Exponential term for the short channel model 0 6 DLC Length offset fitting parameter from C V LINT Im DWC Width offset fitting parameter from C V WINT Im NOFF Subthreshold swing factor for CV model 1 VOFFCV Offset voltage for CV model 0 Vv Process Related Parameters 163 MOSFET Models Parameter Description Default Value Unit TOXM Gate oxide thickness at which parameters are extracted 15e 9 im TOX Gate oxide thickness 15E 9 im x Junction depth 150E 9 im NCH Doping
306. dt x Error Relative sim meas meas m a LESACA 1E 7 1E 6 Ldes LOG DPHIB LWscale DPHIB m OPHIB s E3 NEFF m NEFF s E 24 Ldes LOG NEFF LWscale ESI Parameters pea e OPHIB m OPHIB s 63 Ldes LOG Vth f Ldes Vb low Vd Ldes LOG Vth f Ldes Vb max Vd a 600 Nane Min Value Max 4 NSUBO 1 0000000 8 40038E 1 0000 E 3 BT SEN hL EAT 1 ANNAN 27 7Om 1 Annan gt 1E7 TES 1E5 x Clear Save X Close Help Ldes LOG th L m Yth_L s Under Configuration in the top right area of the window you can select which parameters to adjust and which electrical properties diagrams to show You can select more than one plot or parameter If you change any of the settings red arrows appear to the left of the Update button see figure below reminding you to press Update now to refresh the display and perform the necessary simulations Configuration Show Elecincal Properties Vth_ lin L Yih sat L Adjust Parameters Reset CG Update Two tabs are located below the Configuration area one for Global Scaling and one for Local Extractions The Global Scaling folder enables you to select one of the parameters of the Configuration for optimization or tuning If you select Automatic update of Electrical Property Plots each time you change a parameter the plots will be updated immediately Otherwise you have to use the Update bu
307. dure measures S parameters at a calibrated CW frequency across a range of drain and gate bias voltages It takes adaptive measurements densely spaced in the most nonlinear regions such as at the knees of the I V curves and at the onset of breakdown and less densely spaced in the linear saturation region The number of data points measured depends on the nonlinear behavior of the device and on the measurement conditions you set up Some knowledge of the device characteristics is needed in order to enter valid parameters The data you measured in the DC and S parameter preverifications may be useful in determining appropriate values for your device Do not exceed maximum allowable values Perform the steps in the following paragraphs The data acquisition rate is approximately 700 points per hour Once you have initiated the transform the data acquisition takes approximately 1 to 2 hours before your interaction is needed again Defining the Instrument States The instrument states for the main data acquisition are set in the dc_bias and ac_bias setups Caution Do not change the Inputs in the dc_bias or ac_bias setups Their function is not the same as in the other setups They contain factory set information essential to the program and they must not be changed 1 Select the dc_bias setup 2 Select the Instrument Options tab to display the DC source monitor instrument states 3 Set the Agilent 4142 instrument state the same as
308. e 9071 I I i lt I S astout Wrasltoutl CLOG noise current Freq BSIM3v3 Noise Model The BSIM3v3 noise model uses the following equation to describe the flicker noise 7 Vimi laste l 14 iN pi O14 log 2 2 x10 7 NOIB No NI NI 2x10 2 EF x 8 10 Cox off noise eff y where No is the charge density at the source given by 160 MOSFET Models C V_ V No 2X 8S th q NI is the charge density at the drain given by Cox Vos n a Vas q NI The channel thermal noise is given by ART off Vy oise eff 2 inv eff with A bulk QO W ed 1 Ty inv eff eff ox gsteff 20 stopp Vtm dseff Back to BSIM3v3 Characterization mosfet 161 MOSFET Models SPICE Model Parameters of the BSIM3v3 Model The model parameters of the BSIM3v3 model can be divided into several groups The main model parameters are used to model the key physical effects in the DC and CV behavior of submicron MOS devices at room temperature Here they are grouped into subsections related to the physical effects of the MOS transistor The second group are the process related parameters They should only be changed if a detailed knowledge of a certain MOS production process is given The third group of parameters are the temperature modeling parameters The following two groups are used to model the AC and noise behavior of the MOS transistor Finally the las
309. e Unit NOIA Noise parameter A 1E20 9 9E18 E NOIB Noise parameter B 5E4 2 4E3 E NOIC Noise parameter C 1 4E 12 1 4E12 NOIF Floating body excess noise ideality factor 1 0 EM Saturation field 4 1E7 V m AF Frequency exponent 1 EF Flicker exponent 1 KF Flicker noise parameter 0 p TNOIA coefficient of channel length dependence of total channel noise 1 5 TNOIB Channel length dependence parameter for channel thermal noise 3 5 partitioning NTNOI Noise factor for short channel devices TNOIMOD 0 or 2 1 0 RNOIA Thermal noise parameter 0 577 RNOIB Thermal noise parameter 0 37 p WOflk Flicker noise width dependence parameter 1 p bf Flicker noise length dependence exponent 2 0 BSIMSOI Stress Model Parameters Table BSIMSOI Stress Model Parameters Value SA Distance between OD edge to poly from one side 0 0 m SB Distance between OD edge to poly from another side 0 0 m SD Distance between neighbouring fingers 0 0 m SAREF Reference distance between OD and edge to poly of one side l1e 6 m SBREF Reference distance between OD and edge to poly of another side l1e 6 m WLOD Width parameter for stress effect 0 0 m KUO Mobility degradation enhancement 0 0 m KVSAT Saturation velocity degradation enhancement parameter for stress effect 0 0 m TKUO Temperature coefficient of KUO 0 0 LKUO Length dependence of KUO 0 0 WKUO width dependence of KUO 0 0 ia PKUO Cross term dependence of KUO 0 0 LLODKU
310. e dose of implantation as well as the same geometry and therefore the parameters are equal for drain and source areas Note Since most MOS processes use symmetric source and drain processing parameters there is no need to extract the parameters for the bulk source or bulk drain diodes separately Instead check that the symmetry fields and the respective parameters are set equally Only for unsymmetrical processes which could be modeled in BSIM4 PSP the fields remain unchecked and a separate parameter set will be extracted for bulk source and bulk drain diodes HiSIM2 Initialize Folder for the HiSIM2 Modeling Package Initial Values Parameters Flags TOX 3E 009 DC Capacitance High Frequency Internal Iteration Method TEGAY cE U corsRo 1 gl conos lo corr 1 E NSUBC SE 017 NSUBP 4E 018 COOVLP 1 3 core 1 A COPPRY 1 E NPEXT 8E 017 COISUB 1 CORBNET o LOVER 3 5E 008 ae NOVER fl COIIGS 1 Noise DFM XLD 1E 009 COGIDL 1 COFLICK o G CODFMY 0 thal ame coisti i B COTHRML E GLKSD1 1E 017 l GIDL2 SE 007 coapoy 1 COIGN jo B a J i HiSIM_HV Initialize Folder for the HiSIM_HV Modeling Package 105 MOSFET Models Initial values Parameters Flags TOX 1 4E 008 DC Capacitan
311. e eecs berkeley edu bsim3 bsim4_get html Defining Devices For your convenience there are predefined DUTs on the Device List folder when creating a new project You can either use those predefined DUTs only adjusting names device geometries connections and so on or you can delete existing DUTs and add your own e Choose Add from the row of icons or Configuration gt Add from the menu You will be prompted for the DUTs to copy Select the desired names and choose Add from the Add DUT window It is also possible to set the number of copies of the selected DUTs Added DUTs will automatically get the extension _new to the name of the original DUTs For each line enter a name for the DUT gate length and width L W drain and source areas AD AS perimeter length of drain and source PD PS and the number of device fingers NF of the transistor to be measured If modeling stress effects in BSIM4 or PSP enter SA SB and SD as well See Cross section of a MOSFET showing device geometries as well as Top view of a multifinger MOSFET for details on device geometry respective Shallow Trench Isolation related parameters for details on STI modeling parameters Well Proximity modeling requires the entry of parameters SCA SCB SCC and or SC Note Remember all geometries are to be given in microns um Geometries Shown in the following two figures are views of MOSFET s where you can find the geometries required by the BSIM3
312. e list In that case the extraction process uses the parameters already extracted during an earlier step in the extraction process and you overcome the reset parameter step e All warnings and errors during the extraction process are written to the failure log which is opened using the Extract gt Failure Log menu item Note The contents of the Failure Log window doesn t contain all the warnings written to the IC CAP status window Only the warnings and errors regarding parameter extraction are re directed to the Failure Log 54 MOSFET Models You can add several steps of the same extraction after each other The extraction method selected in one step could be another one in a further extraction step In other words you are able to set the tuner option in one extraction step and the optimizer option in another step probably when other parameters of influence have been extracted in between the steps e Change the function flow inside the Function Flow field using the Move Up or Move Down buttons below that section to move a selected extraction routine one step up or down e The Default button restores the order of parameter extractions inside the Function Flow list as it was in the beginning of a project e To delete an extraction from the Function Flow choose Delete Note You cannot delete the first Reset Parameters or the last Save Parameters extraction step inside an extraction flow e Below the Extraction Flow fi
313. e measured data is stored together with device information like gate length pin numbers of a switch matrix used and so forth in IC CAP mdm data base format These mdm files are organized as projects that can be identified by project name Now the extraction module extracts the necessary data from stored mdm files to perform model parameter extraction and visualization of measured and simulated results In addition this method enables the generation of new data representations where the scalability of a model can be easily verified Files Resulting from Measurement and Extraction using the Modeling Packages This section describes the files resulting from measurement and extraction of MOS devices using the MOS Modeling Packages The following table shows how file names are being used The bold printed words inside the left most column names the task the files are being used for and the normal printed names are the appropriate file names used to store the files for a specific project The columns marked DC and RF list the task performed by each file For example measure extract in the column DC means that this file is used in measurement and extraction of DC parameters Note The following characters are excluded from use in file or project names 1 7 1 2 AAGOUU AS well as empty space Data Structure of MOS Modeling Packages File Usage DC RF Comment Project search dc_idvg mdm measure extract rf_s_dut mdm measure
314. e modeling of MOS transistors for the use in a frequency range of 1 to 10 GHz Therefore S parameter measurements have to be done see also Test Structures for S parameter Measurements mosfet to cover this frequency range by a proper device model As is pointed out using the BSIM3v3 model for high frequency applications requires some special attention to the modeling strategy We found the following procedure to give the most accurate results e Measurement of DC and CV curves e Extraction of the BSIM3v3 model parameters from DC and CV measurements with a special emphasis on a physically based extraction strategy Here model parameters should not be used for fitting purposes they should have a correct physical meaning e The modeling of the output characteristic 14 f V 4 and the output resistance Rout f Vy is very important for further S parameter measurements see Input Reflection Parameter S11 and Influence of Incorrectly Modeled Output Characteristic on S21 e Performing S parameter measurements and proper de embedding of parasitics e The starting points of the S parameter curves at the lowest frequency can be modeled by fitting the curves with DC and capacitance parameters The following diagrams describe this influence on the high frequency behavior Incorrectly Modeled Drain Current L Hi 25um WF inger 1 Bum Nfinger16 va Lar f Tf 2 amp 8 GHz Incorrectly Modeled Output Characteristic 153 MOSFET
315. e of surface roughness mobility reduction MUESLP 1 0 length dependence of surface i roughness mobility reduction NDEP 1 0 0 1 0 depletion charge contribution on effective electric field NDEPL 1 0 modification of QB contribution for short channel case NDEPW 1 0 width modification of QB contribution for short channel case NDEPWD 1 0 second width modification of QB contribution for short channel case NDEPLP 1 0 modification of QB contribution for short channel case NINV 0 5 0 1 0 inversion charge contribution on effective electric field BB 2 0 high field mobility degradation p Channel Length Modulation Parameters Parameter Name Default Range min Range max Description Unit CLM1 0 05 0 01 1 0 hardness coefficient of channel contact i junction CLM2 2 0 1 0 2 0 coefficient for QB contribution CLM3 1 0 1 0 5 0 coefficient for QI contribution CLM4 1 0 1 0 5 0 used in former versions CLM5 1 0 0 5 0 effect of pocket implantation le CLM6 0 0 5 0 effect of pocket implantation is Narrow Channel Effect Parameters 239 Parameter Name WFC WVTHO NSUBPO NSUBWP MUEPHW MUEPWP MUESRW MUESWP VTHSTI VDSTI SColli SCSTI2 NSTI WSTI WSTIL WSTILP WSTIW WSTIWP WL1 WLI1P NSUBPSTI1 NSUBPSTI2 NSUBPSTI3 MUESTI1 MUESTI2 MUESTI3 SAREF SBREF Default Range Range min max 0 5 0E 15 1E 6 1 0 1 0 1 0 0 0 0 0 5E17 1E
316. e plot menu select File gt Print Setup Enter the name of a printer and make any other changes to the printer plotter setup you wish then select OK 6 If you have your printer setup completed select File gt Print To Plot an Earlier Data Acquisition If you wish to view data from a previously stored Agilent RootMOS data acquisition you will need to perform these extra steps to bring the data into this model and display the plots 1 From the IC CAP main menu select File gt Change Directory Type in the path name of the file where your data is stored and select OK 2 Select the create_mdl setup 3 From the Plots tab select the plot of your choice and Display Plot The displayed plot window will be blank and an error message will be displayed Ignore the error message and click OK Now select Display Plot again and the plotted data will be properly displayed The first time you selected Display Plot an internal function re initialized the data from the changed directory The Measured Data Plots The plots listed next illustrate the data measured by the data_acquisition transform for an example device Id_vd plots the DC measurement of drain current Id as a function of Vds for different values of Vgs Check this plot to see if you are satisfied with the bias range of the measurement If not go back to Setting the Variables and make appropriate changes in the values of Min Vd Max Vd Min Vg and Max Vg Y11i plots the i
317. e preverification every time you generate a model especially if you are using data sheet values Device Configuration The input values you set in this procedure configure the device as shown in the following figure MOSFET Bias Configuration for S Parameter Preverification e NA PORT 331 MOSFET Models Defining the Instrument States Select the Instrument Options tab and follow the steps described in the appropriate section shown next with the exceptions noted below For an Agilent 8510 based system You will need to set the instrument states separately for each measurement setup in a modeling procedure However use the same settings for all the swept S parameter measurement setups in one model except that Integ Time can differ among setups as explained under Defining the DC Source Monitor Instrument State Unless you use the example settings documented here write down the settings you use to duplicate among setups within one model This procedure uses the sparm_bias setup in the BJT measurement as an example though the explanations here apply to all swept frequency S parameter measurements in the different device measurement procedures Note Source parameters such as frequency range are not set in this procedure but in the individual S parameter setup procedures in each model chapter Note Do not use these settings for a CW S parameter measurement The settings for a CW measurement are different and are
318. e same Sweep Time as in the network analyzer calibration You can check this on the network analyzer in LOCAL mode by pressing MENU gt SWEEP TIME If you set a reduced IF bandwidth for calibration the sweep time may have been slowed down automatically 14 Set IF Bandwidth to the same value as in the calibration The noise floor can be reduced by reducing the receiver input bandwidth 15 Set Use Fast CW to No because fast CW is not compatible with the instrument calibration 16 Set Avg Factor to the same averaging factor you set in the calibration 17 Set Cal Type to H hardware so that IC CAP will recognize calibration device measurements at the network analyzer front panel 18 Cal Set No must be set to the analyzer register number where you store your swept broadband calibration Do not use register 6 which stores the active instrument state 19 Soft Cal Sequence refers to the sequence of measurements of the cal standard devices load open short thru You can set a different sequence if you prefer 20 Delay for Timeouts increases the timeout and wait times It can generally be set to the default value of 0 000 21 If you define a specific number of points for the measurement calibration set Use Linear List to No the normal setting for a swept measurement The setting would be Yes for a log or list sweep 22 If necessary refer to the Application and Operation Concepts chapter of the Agilent 8753C Operating Manual for more det
319. e settings made on the Options folder You can Display and Close Plots using the appropriate icon for this task Select the plots you would like to see or view all plots in one window Related Topics RF Notes mosfet RF Measurement Conditions mosfet De embedding mosfet RF Options mosfet Back to RF Measurement mosfet RF Measurement Conditions The first task during RF modeling is to set up measurement conditions Use the Measurement Conditions folder shown in the following figure to enter the measurement conditions at which you would like to measure and extract RF parameters Measurement Conditions folder way BSIM4_RF_Measure b Fie Configuration Data Tools Help J6 s pulsos Hotes Measurement Conditions De embedding Pad Structures DUTs Ontions amp x i ee General S Paremeters Polarity Frequency NMOS Sweep Start Stop sE 1 Frequency J 100 0MEG 20 005 Temperature mom o K Freq Points si Lin Freq Points Decade fro T Leg Bias Conditions Transconductance amp derived from output data Project Example_Scale Project drectory j users deFaut_20091 Satus A Select the Polarity of the transistor to be measured NMOS or PMOS using the appropriate check box Enter the measurement temperature TNOM if the measurement is being conducted at any other temperature than the default of 300K 47 MOSFET Models Note Be sure t
320. e short channel effect AV is isolated in the next step from Vp as a function of gate length and bulk voltage Vps The following figure shows AV as a function of those two variables Only a subset of this data array is used for the determination of DVTO and DVT1 and the boundaries for defining this subset are set by the extraction routine As shown in the flowchart in Extraction of Short Channel Effect Parameters DVTO DVT1 different results from this action are possible In the first case no data point is available for the extraction and the user is informed with a warning message This may occur for instance after measurement errors or with old CMOS processes that do not show a short channel effect As a further possible result only one usable data point is returned From this data point one model parameter can be determined while the second one has to be set to its default value Short Channel Effects in Vth as a Function of Gate Length and Vbs 177 Short channel effects in VTH V MOSFET Models Simulated NLX DVT Part in VTH 0 3 i s 15 06 A m 2 1 5 Baa His gt 9 Vbs M Channel length L um In the normal case a group of usable data points can be identified and transformed in such a way that DVTO and DVT1 can be extracted through linear regression methods Extraction of Short Channel Effect Parameters DVTO DVT1 Extraction of threshold voltage Vin f L Yhs from test transistors ith different chann
321. e to change the measurement information during the extraction session This folder is for information on measurements only Information Folder during Extraction 4 BSIM4_DC_CV_Extract 1 File Initialize Binning Extract Plots HTML Options Boundaries Tools Help SHUG tTHH XLS AE aa e Information Binning Project bsim4_for_experts Project directory g users default Status rr Related Topics DC Notes mosfet DC Initialize mosfet DC Binning mosfet DC Extract mosfet DC HTML mosfet DC Options mosfet DC Boundaries mosfet Back to Extraction of DC and CV Parameters mosfet DC Initialize The folder Initialize is intended to set initial conditions for parameter extraction Since the initial conditions for BSIM3 and BSIM4 PSP models differ the following section shows both Initialize folders one after the other BSIM3 Initialize folder to set initial conditions for the extraction of BSIM3 parameters Initial values Parameters Flags TOX 7 5E 009 Model Noise a aa BINUNIT nomon 1 NCH 1 7E 017 PARAMCHK Gate Current HSPICE only NGATE 0 DC Capacitance IGBMOD fo ai RSH l DLC SE 008 capmop 3 tememoo fo The Initial Values section of the folder contains fields for Model Parameters and Model Flags Into the field Model Parameters enter process related parameters like oxide thickness TOX or doping concentrations channel doping concentration NCH respective gate doping con
322. e view for WaferPro displaying the default routines defined Select DUT Setup ModelfileMaintenanceutilities RoutineMagr CentralLtilities et ee et my_MOS_DC_basic my_DIODE_DC_C _basic my _NPN_basic my_MOS_4Dev_DC_basic my _Ringo_basic H CONTACT CONTACT_PIN H MOS_PT SPAR_S WEEP Mos_DC MOS_C H MOSIUNC_DC MOSIUNC_CY BIP_DC BIP_CY DIO_DC DIO_C RES DC CAP CY lt al Follow the steps below to export measurements defined in the MOS Modeling Packages to a WaferPro project 1 From IC CAP Main window open IC CAP Wafer Professional WaferPro measurement application 2 Open the MOS Modeling toolkit and an example model file for example BSIM3_DC_CV_Measure madl 3 Double click the MOS Modeling file to open the Model window 4 In the Model window select Tools gt Configure WaferPro from the menu bar You will get a warning that the default model file for WaferPro will be overwritten ah Configure WaferPro The modelfile Routine does not exist in the IC CAP main window First open WaferPro that the model Routine can be configured 5 Select Yes If you select Yes the existing WaferPro model file will be overwritten 6 In WaferPro window choose Tools gt Synchronize IC CAP routines to update WaferPro with the new measurement routines A warning to synchronize the Routine and Measurement Condition may appear 38 MOSFET
323. ectly to the miniset parameters This step also sets the parameters ETAALP ETAGAMR ETAMR ETAZET and ETADSR to their correct constant values e The resulting parameters are optimized to the measured characteristics of all the devices in the set 4 For each temperature above or below the nominal extract values of the temperature sensitive parameters appropriate to this temperature In practice this step consists of a series of optimizations on the devices measured at a particular non nominal temperature 5 Apply the temperature scaling rules to the sets of parameters extracted in the previous step to generate the temperature coefficients of the model In practice this step consists of a least squares fitting followed by optimizations on all the devices measured at the non nominal temperature Data Organization For extraction of MOS Model 9 parameters I V data is measured in accordance with the recommendations of the Philips report NL UR 003 94 MOS Model 9 This is basically e Linear region data te Vas for low Vgs range of Vib e Vgs gt Vin e Subthreshold region data o Iq Vas for range of Vas and Vip Vgs low to just above Vi e Saturation characteristics o Igs Vg for range of Vgs and Vp o includes one curve at Vgs Vin 100 mV e Output conductance data 358 MOSFET Models Gus Vas derivative of Ijs Vgs data e Substrate current data Slap Vas for range of Vas and V OV Scalin
324. ed description of ideal test structures can be found in the JESSI AC 41 reports Reference 8 Floating versus fixed body biased devices Due to the nature of a SOI transistor the internal body is normally floating However for modeling purposes to determine the effect of parasitic diodes and parasitic bipolar transistors it is very useful to have an additional contact to this internal body Therefore the BSIMSOI Modeling Tool includes a flexible approach to make the following I V curve measurements Fixed body transistors example Large_m e Large_m __biased_body_ve0 MOS transistor at fixed body bias Vbs idvg idvgh idvd idvd2 Large_m floating_body_ve0O MOS transistor at floating body bias Vbs this is the normal operation of a SOI MOS transistor idvg_float idvgh_float idvd_float Large_m parasitics fearly fgummel idiode parasitic source drain to bulk diodes Floating body transistors example Large_float_m Large_float_m floating_body_veO MOS transistor at floating body bias Vbs normal operation idvg_float idvgh_float idvd_float biased body devices enables the determination of parasitic bipolar and diode effects The floating body devices should only be used for verification purposes e IMPORTANT NOTE It is not possible to use floating body devices for the modeling Only the use of Test Structures for CV Measurements DUT Shape Applied bias n type Comment i Large are
325. ed VBSMIN Resistance Modeling in HiSIM_HV The most critical aspect of modeling a high voltage MOS transistor is the drift region resistance modeling A flag is used to switch between different resistance settings CORSRD This flag can have the following values that affect resistance modeling of RS and RD as is shown in the following table 231 MOSFET Models CORSRD value Drift region resistance modeling valid only if Rg Rp 0 0 Rs and Rp are not considered 1 Rs Rp considered as internal HiSIM resistances 1 Rs Rp considered as external HiSIM resistances 2o Ro Rp considered using an analytical solution a Ro RpD considered using both internal and analytical solution This is the default case The CorSRD flag provides a few more options as shown below Options Selected by CORSRD Yes CORSRD 0 No CORSRD 1 CORSRD 1 or 3 HiSIM iteration Circuit simulator generates nodes for RS and RD Vosen Vos 1x Re Vasor Vd x Rs Rarirt Vbser Vb en Ix R Surfacr Potential Calculation Device Characteristic Calculation No CORSRD 2 or3 Yes has fiso 1 liso Ral Vas Be careful when using the CORSRD flag since more parameters are taken into account depending on the CoRSRD flag value There is the possibility that some parameters may not be considered if others are set to zero For instance the equation to calculate the parameter RDVD uses a
326. ed are CJBR CJSR CJGR VDBR VDSR VDGR PB PS PG The parameter limits are controlled by the following model variables CJBR_MIN CJBR_MAX CJSR_MIN CJSR_MAX CJGR_MIN CJGR_MAX VDBR_MIN VDBR_MAX VDSR_MIN VDSR_MAX VDGR_MIN VDGR_MAX PB_MIN PB_MAX _ PS_MIN PS MAX PG_MIN PG_MAX The data limits are controlled by the following variables CV_VMIN CV_VMAX set_unit_dimensions A transform that sets the dimensions AB LS and LG in the analysis DUT to unity update_cv_curves A transform that resimulates all the C V curves in the area cv locos cv gate cv and analysis cv setups cjb A plot definition for the normalized area sub region contribution to Capacitance cjs A plot definition for the normalized locos sub region contribution to Capacitance cjs A plot definition for the normalized gate sub region contribution to capacitance fwd_iv This setup controls the extraction of the I V parameters with respect to the forward I V data In the forward region at moderate and high applied voltages the diffusion current components dominate However for low applied voltages the generation components are also important Therefore all the optimizations to the forward I V curves target both the diffusion and generation parameters va vk These input definitions for the anode and cathode voltages are the same as those in the area fwd_iv locos fwd_iv and gate fwd_iv setups ibn A transform that extracts and holds the normalized area sub reg
327. ed by a device simulator The symmetrical profiles correspond to V 0 and the asymmetrical profiles to V gt 0 In the figure the simulated potential barrier near the source is observed to decrease with increasing drain bias which indicates the origin of the DIBL effect Band Diagram at Si SiO2 Interface of a 0 1 pm MOSFET Gate Source n n Drain Vas 0Y Distance between F ermi Level Conduction band and _ Fermi level Vas 1V 0 0 1 0 2 03 Position ym The DIBL effect is modeled in BSIM3v3 with the following equations i _ _ Tgstefft Vim i Abul dsat ADIBLC rout PDIBLC Vosefp Abulk dsat V gstefft Vtm with iD f APE D L __rout eff gt en __rout eff Sout P prexci ae lida ae Porprc The following figure shows the influence of the DIBL effect on the output resistance of a short channel transistor Influence of Drain Induced Barrier Lowering DIBL effect on output resistance LE H s 2 without DIBL rout s rout m vd CE e d Substrate Current Induced Body Effect SCBE Substrate current is induced through hot electrons at high drain voltages as described in Substrate Current It is suggested that the substrate current increases exponentially with the applied drain voltage The total drain current will change because it is the sum of the channel current from the source as well as the substrate current It can be expressed as las Isource lbutk The
328. ee software you can redistribute it and or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation either version 2 1 of the License or at your option any later version This library is distributed in the hope that it will be useful but WITHOUT ANY WARRANTY without even the implied warranty of MERCHANTABILITY or FITNESS FORA PARTICULAR PURPOSE See the GNU Lesser General Public License for more details You should have received a copy of the GNU Lesser General Public License along with this library if not write to the Free Software Foundation Inc 51 Franklin St Fifth Floor Boston MA 02110 1301 USA Permission is hereby granted to use or copy this program under the terms of the GNU LGPL provided that the Copyright this License and the Availability of the original version is retained on all copies User documentation of any code that uses this code or any modified version of this code must cite the Copyright this License the Availability note and Used by permission Permission to modify the code and to distribute modified code is granted provided the Copyright this License and the Availability note are retained and a notice that the code was modified is included Qt Availability http www gtsoftware com downloads Patches Applied to Qt can be found in the installation at HPEESOF_DIR prod licenses thirdparty qt patches You may also contact Brian Buchanan at Agilent Inc at b
329. eep mode you specify Start Step and Stop voltages for gate bulk and drain nodes Stop value of drain voltage is set to a fixed value in order to measure the relevant range of voltages for proper extraction of the parameters used to model this device behavior The following figure shows the typical form of a transconductance diagram Transconductance diagram 19 MOSFET Models Id FC Yg Ybl Aiff Wa E 6 id s id m 21 0 2 0 L O 2 9 vg CE e 4 If you change the settings of the diagram in the figure above one of the effects appearing in submicron semiconductor devices becomes visible The following figure shows a typical transconductance diagram using a logarithmic y axis to show the influence of the GIDL gate induced drain leakage effect on transistor behavior Transconductance diagram showing GIDL effect Id f cvqg Vbs diff Va id s CLOG id m vg CE AJ e idvd Output characteristics I f Vp Here you specify the stimulus voltages used for measuring the output characteristic of your devices You can choose either a Linear sweep or a List of discrete voltage values where you enter a number of points and their respective value For Linear sweep mode you define Start Step and Stop voltages for drain gate and bulk nodes respectively The following figure shows the typical measured output characteristic of a MOSFET Output diagram of a MOSFET Id fc Yad Ygl7 diff Wk
330. el Variables tab Note Do not edit the init_parameters macro The macro includes executable code modifying it can cause problems in the program Setting the Extraction Frequency You use the model variable table to set the frequency at which the model will be generated To edit the variable table move the mouse pointer to the appropriate variable value click left and move the pointer over the old information to highlight it Then type in the new value over the old Model Variable Table Name Value Freq 2 0G Num_fingers 5 Width 3 Sum ris 400 0m r2s 400 0m SIMULATOR mns ANNOTATE PLOTS YES ANNOTATE FILE icplotnotes ANNOTATE AUTO YES 1 Enter the CW frequency you intend to use for the data acquisition and model generation This must be the same as the frequency of the network analyzer CW calibration you will perform before doing any S parameter measurements Refer to the explanation under Calibrating the Network Analyzer which explains how to perform a CW calibration and how to decide the CW frequency 2 Make sure the Value listed for SIMULATOR in the model variable table is mns to ensure that the mns link is in place to allow verification of the model in IC CAP 3 Do not change the other values in the table at this time Values in the Parameters Table The illustration shows the Model Parameters table with the initial values for the extrinsic parasitic capacitances and inductances The table is presented here
331. el length Warning and DYT 1 through linear regression e Back to BSIM3v3 Characterization mosfet 178 MOSFET Models Binning of Model Parameters Usage of binned models in a simulator The binning idea The idea of binning is to provide different model parameter sets for a scalable model e g a MOS device according to the device dimensions In the case of MOSFETs the validity of such a parameter set is determined by LMIN LMAX WMIN WMAX for each bin Major commercial simulators like HSPICE Spectre and ADS support the binning feature for semiconductor models However it is not included in standard UC Berkeley SPICE3f5 Binned model according to the measured devices Wim Measured devices 0 18 0 5 10 L ym Lets take the example shown in the diagram above we have 4 different bins with 4 different parameter sets If we look only at the bins with the smallest width see the arrow above we still have 2 different parameter sets set 1 and set 2 The simulator would take the bins according to the following table Bin Conditions L lt LMIN bin1 Error not specified LMIN bin1 lt L lt BIN1 interpolated LMAX bin1 LMIN bin2 lt L lt BIN2 interpolated LMAX bin2 L gt LMAX bin2 Error not specified Please note LMAX bin1 LMIN bin2 The simulator now calculates an effective model parameter P L from the different binned parameter sets and the actual gate length of t
332. el with a graphical representation for better understanding the model Some model parameters and effects are taken from the BSIM3v3 bulk MOSFET model they are listed inside the BSIM3v3 manual of the University of California at Berkeley Links 290 MOSFET Models are provided to the appropriate paragraphs of the BSIM documentation where you can find a description of some effects together with basic equations used A typical cross section of a SOI MOSFET device is shown in Cross section of SOI MOSFET Device figure In contrast to a bulk MOSFET device there is a buried oxide with thickness Tbox Just below the channel of the SOI MOSFET Using the floating body configuration there are four external bias voltages applied to the device These are the gate voltage Vyr the drain voltage Vg the source voltage V and the substrate voltage V The internal body node voltage V is usually iterated in circuit simulation However in case of an existing body contact one more external bias has to be applied the external body contact voltage Vp Cross section of SOI MOSFET Device Source Contact Gate Contact G Gate Oxide SE SE PU Body Substrate tox Drain Contact Buried Oxide box Transistor 1 Gap between Transistor 2 Devices G1 G1 1 D1 1 D1 t g T 5 7 i p k Substrate SOI MOSFET s Model Categories SOI MOSFET s are classified into three categories
333. eld check boxes enable you to Deactivate Tuners or to use the Test Mode without saving the extracted parameters This mode is intended for you to test influences of some parameters on others without overwriting already extracted parameters from the selected step You are able to use every mps file with every extraction step without saving and resetting parameters You will notice the changing of colors on the Extraction Folder This is a visual warning that intermediate results are not stored in this mode Note This feature makes it possible to test influences of any other mps file to compare extraction results Test mode starts with the last step taken in the flow No results are overwritten or saved e TO export the extracted parameters during the defined extraction flow for the purpose of saving intermediate results use Export Extraction under the Extract menu You must specify the path and the name for the parameter file to be exported Exported files will be packed into a tar file using the project name as a file name and appending Export and a number to the extracted tar file project_name Export_1 for example e An item is provided under the Extract menu to Import Model Parameter Set from an earlier project for example You will receive a warning message stating that importing parameters will overwrite the actual model parameters in IC CAP Select either a Project or if existing an exported tar file for a specific p
334. eleted and the project will use default extraction flows and functions A customized model file can either be saved as the default model file overwriting the installation default model or in a user directory If it is saved as the default configuration the customization will be present whenever you open the model files delivered with IC CAP These files will be overwritten when installing updates and new releases of IC CAP Plus you are bound to use the customized model whenever you use IC CAP Sometimes it won t be necessary to use customized models for extractions If your customized model file is stored in another location it won t be overwritten by updates You load the customized model file only for the purpose of using the customization Available Extractions Add a simple Customized Function To add a customized function open the Global gt Capacitance Oxide extraction step Use the right mouse button to click on O TOXO NSUBO VFBO Choose Generate Customized Function from the sub menu see Figure 2 Generate a Customized Function se Configuration Wizard for Extraction Functions 5 Configuration Edit Options Help OP tt Available Extractions Overview Customized Functions Default Extraction Flows Available Extractions Global 3 Capacitance Oxide B E TOXO i Function Generate Customized Function 3 Capacitance d Type 3 Capacitance tt Diode Insert Space Name 0 J Large Vth L
335. eling Abulk is defined different from DC e te 0 A es bulk CV r y W B Lof 2 pts Xlep eff f LPEB L w K1OX EEEL norr sA D 2 fs P bse Fid eff 1 1 XETA osef Numerical simulation has shown that the charged layer under the gate of a MOSFET has a significant thickness in all regions of operation Therefore a Charge Thickness Model has been introduced in BSIM4 This model uses a capacity in series with the oxide capacitance Cox and an effective oxide capacitance is used E _ Si i oxe Xpo oxeff g C SI oxe yY DC DC charge layer thickness in accumulation and depletion is calculated by 208 MOSFET Models 1 4 1 NDEP Tno 3 Adebye a acos EE Yose hse V PBeff TOXE whereas in inversion ee 19 19 DC ne yt 4 THO 1 2 TOXP 1 2 VF Bef fezb 3 Cea Fb 2 2 3 Caz Y gb Too 7 f f V fbzb Yh 0 Po l Ps 4 th 0 th 7 By introducing the VFB term in the equation above the calculation is valid for N or P poly silicon gates and future gate materials too Using TEMPMOD z2 the calculation of Vfbzb becomes temperature dependent and is calculated the following way T Vzal T mzb TNOM KTI 1 Intrinsic Capacitance Model Equations There are three intrinsic capacitance models to choose from using the model flag CAPMOD Additionally there are three charge partitioning schemes 40 60 50 50 and 0 100 Those schemes describe distr
336. ements C Matix Debug Mode Basic Settings Agilent E5250A Matrix Modal SMU Connections Card Setup Bus Cadsbt M SWM Address Card stat 2 HP IB Interface cedsbt3 O Delay after switching s Coupled Card sot C smu 10 O smJ2 6 C smu 3 5 O smj4 O sws O sw D High Project bsim4 for experts Project drectory cusers default The Basic Settings provide a choice of several different Matrix Models which are supported by IC CAP Type the appropriate Bus and GPIB address of the Switch Matrix SWM Address 22 in our example as well as the GPIB Interface name See Prober measurement and Matrix Drivers measurement for a complete description of the GPIB settings for the selected switch matrix Our example shows the use of an Agilent E5250A matrix model For this type of instrument you have to define which port is connected to which SMU or C meter input pin and which slot is equipped with a card It is now possible to use Instrument Cards for your measurements Activation is done using a port pin combination A1 or A26 for example This means Port A and Pin 1 or Port A and Pin 26 are activated The Switch Matrix folder shows an additonal field to enter a pin number BSIM4_DC_CV_Measure 1 Fit Configuration Data Tools Help 5 fr gt a Ne e ESI Temperature Setup Switch Matrix Device Definition Optons Use Switch Matrix for DC Transistor Measurements C Capacitance Meas
337. ent Coefficient of the body bias effect of mobility degradation Mobility coulomb scattering coefficient Mobility channel length coefficient Mobility channel length exponential coefficient Exponent for mobility degradation of MOBMOD 2 Drain current Saturation velocity Bulk charge effect coefficient First non saturation effect factor Second non saturation effect factor Coefficient of Vgs dependence of bulk charge effect Bulk charge effect coeff for channel width Bulk charge effect width offset Body bias coefficient of the bulk charge effect Subthreshold region Offset voltage in subthreshold region for large W and L Channel length dependence of VOFF Vgsteff fitting parameter for moderate inversion condition Subthreshold swing factor Interface trap capacitance Drain Source to channel coupling Capacitance Body bias coefficient of CDSC Drain bias coefficient of CDSC Drain Source resistance Zero bias LDD resistance per unit width for RDSMOD 0 LDD resistance per unit width at high Vgs and zero Vbs for RDSMOD 0 Zero bias LDD drain resistance per unit width for RDSMOD 1 Zero bias LDD drain resistance per unit width at high Vgs and zero Vbs for RDSMOD 1 Zero bias LDD source resistance per unit width for RDSMOD 1 Zero bias LDD resistance per unit width at high Vgs and zero Vbs for RDSMOD 1 Channel width dependence parameter of LDD resistance Body bias coefficient of LDD r
338. ent temperature double click and enter the actual environment temperature inside your measurement lab into the TNOM field Add new measurement temperatures using the Add icon or the Configuration menu If you no longer need a measurement temperature click the Delete button You will be prompted for the temperature to be deleted If there is a file containing measured data for this temperature the data file will be deleted if you choose OK on the prompt dialog The delete window does not contain an entry for the temperature set as TNOM since TNOM cannot be excluded from measurement and extraction Note Don t forget to enter the actual temperature in degree Celsius C into the TNOM field during measurement of the devices It is not possible to delete the nominal temperature TNOM When you add a new measurement temperature a new column is added to the Device List folder s Device List table for DC Transistor Capacitance and DC Diode Any changes on the Temperature Setup folder must be saved prior to selecting another folder Other DC CV Measurement Module Folders e Notes mosfet e Switch Matrix mosfet e Device Definition mosfet e Options mosfet Switch Matrix Use this folder to define which measurements use a switch matrix see figure below There are three options Use a switch matrix for DC Transistor Measurements for Capacitance Measurements and for Diode Measurements You can select any one or more tha
339. ents mosfet for details on device geometries and requirements for proper extraction of capacitances of your devices like test lead connections and so on To delete DUTs Choose the Delete icon or Delete from the Configure menu You will be prompted with a list of DUTs Select the DUTs to be deleted and choose Delete on the Delete DUT folder A prompt dialog box appears Select OK if you are satisfied with your choice of DUTs to be deleted To select devices to be measured at different temperatures Choose the Temperature Measurement icon or Temperature Measurement from the Configuration menu You will be prompted with a list of DUTs Select the devices to be measured at those temperatures entered in the Temperature Setup folder and click OK Note You cannot prevent a DUT from being measured at TNOM All DUTs are measured automatically at that temperature If you have entered one or more temperatures on the Temperature Setup folder the DUTs selected for temperature measurement are all measured at those temperatures In other words you cannot select a DUT for measurement at temperature T1 but not at another temperature m2 To start measurement of the devices Choose the Measure icon and select the DUTs to be measured on the dialog box that opens You can select measurement temperature if there is a temperature other than TNOM defined in the Temperature Setup folder as well as a specific DUT or all DUTs Start the measurement with Measu
340. ependence for CV LL channel length offset LWC Coefficient of width dependence for CV LW channel length offset LWLC Coefficient of length and width cross LWL term dependence for CV channel length offset WLC Coefficient of length dependence for CV WL channel width offset Coefficient of width dependence for CV WW channel width offset WWLC Coefficient of length and width cross WW term dependence for CV channel width offset LMIN Minimum channel length 0 0 LMAX Maximum channel length li 0 WMIN Minimum channel width 0 0 max Maximum channel width 1 0 Coefficient of gate bias dependence of 0 0 Weff Coefficient of substrate bias m v 0 5 tite of Weff _ Outputresistance resistance PCLM Channel length modulation parameter z PDIBL1 First output resistance DIBL effect 0 39 7 parameter PDIBL2 Second output resistance DIBL effect 8 6m parameter PDIBLB Body bias coefficient of output 0 0 1 V resistance DIBL effect DROUT Channel length dependence coefficient 0 56 of the DIBL effect on output resistance PSCBE1 ie substrate current induced body fe V m effect parameter PSCBE2 Second substrate current induced body 1 0E 5 m V effect coefficient PVAG Gate bias dependence of Early voltage 0 0 FPROUT Effect of pocket implant on Rout m V m 99 degradation PDITS Impact of drain induced Vth shift on pe Vet Rout PDITSL Channel length dependence of drain 0 0 m1 induced Vth shift on Rout
341. er select the parameters you would like to finetune using the selected diagrams Save your configuration e Once the configuration has been stored it will be present inside the BSIM4 PSP GUI extract folder under Available Functions in the Finetuning step and can be inserted into the Function Flow The following is an example using this feature to extract the threshold voltage from two different types of plots Open the Data Display Menu Plots gt Open Display and go to folder All Diagrams Select a 2x1 plot layout from the Plot Layout menu Select one of the plots then use the right mouse button to access Flexible Plot Configuration Under the Plot Type pull down menu in the All Diagrams folder change plot type to IdVg The measured devices together with the measurement voltages and temperatures appear Select the desired voltages temperatures and devices then press Redisplay The plot will be displayed Activate the second plot using the right mouse button to select Other Diagrams Vth Cap gt Transistor Capacitance gt C Overlap G DS to display the overlap Capacitance measured at the same voltages already selected for the first plot Plot Optimizer Now activate Area Tools located under the Options menu To the right of each of the plots the area tools are displayed These are tools to change the display of the plot to a zoomed condition to change axis settings to display relative or absolute errors and to activate t
342. er fringe Capacitance Coefficient for the length times width dependence of outer fringe capacitance Coefficient for the geometry independent part of thermal noise coefficient Coefficient for the geometry independent part of first coefficient of flicker noise Coefficient for the length dependence of first coefficient of flicker noise Coefficient for the width dependence of first coefficient of flicker noise Coefficient for the length times width dependence of first coefficient of flicker noise Coefficient for the geometry independent part of second coefficient of flicker noise Coefficient for the length dependence of second coefficient of flicker noise Coefficient for the width dependence of second coefficient of flicker noise Coefficient for the length times width dependence of second coefficient of flicker noise Coefficient for the geometry independent part of third coefficient of flicker noise Coefficient for the length dependence of third coefficient of flicker noise Coefficient for the width dependence of third coefficient of flicker noise Coefficient for the length times width dependence of third coefficient of flicker noise temperature offset with respect to ambient circuit temperature F 0 F 0 F 0 F 0 F 0 F 0 F 0 F 0 F 0 F 0 F 0 1 1 Vm4 8E22 1 Vm4 0 1 Vm4 0 1 Vm4 0 1 Vm2 3E7 1 Vm2 0 1 Vm2 0 1 Vm2 0 1 V 0 1 V 0 1 Vm4 0 1 Vm4 0 K 0 283 MOSFET Models Parameter Description Uni
343. erature CE e e Saturation Current of Drain Source Bulk Diodes The temperature dependence of the drain source bulk diodes is given by the following equation for the saturation current density Js ib f CVda CLOG ENE EE E A eee A S ib ib m SS eee eee i 4 i i 2 i i lt i 8 600 8 405 0 205 0 6 6 va CE 3J Temperature 250 400K The influence of XTI on diode current and saturation current density J is shown below Saturation Current as Function of Temperature ee Eerd Vimo Vim nom ad JT JS e Back to BSIM3v3 Characterization mosfet 159 MOSFET Models Noise Model There are two noise models implemented in BSIM3 a conventional noise model named Spice2 model and a newly formulated noise model which is referred to as BSIM3v3 noise model The following equations and diagrams should give insight into these two noise formulations Conventional Noise Model for MOS Devices Flicker noise 9 AF T s Pa 5 Los KF1 5 k eff ee noise Channel thermal noise Em Sas is Emb _ 8kT noise eff 3 e Influence of AF on Effective Noise Voltage Tt a i T I g Tt C907 bot GF S Sastout Wrasltoul CLOG moise current Freq Influence of EF on Effective Noise Voltag
344. ered using the following formulation V VTHO K1 V B h 4222 th N s bs NN s L N eff f f K2 V K1 hal fo N eff J N Additionally drain induced threshold shift DITS has to be considered in long channel devices using pocket implant For Vys in a range of interest a simplified threshold voltage shift caused by DITS was implemented AV DITS nv In eff AF ee i an _ DVIPI V L gt DVTPO 1 6 Using TEMPMOD 2 this formula changes to L ra AV DITS aV In il 3 nom DVTP1 Fe i Lop PVTPO 1 e Short Channel and Drain Induced Barrier Lowering DIBL Effects For shorter channels the threshold voltage is more sensitive to drain bias DIBL effect and less sensitive to body bias because of reduced control of the depletion region The short channel effect coefficient is given by es Se 2 cosh at 1 0 LZ eff t 195 MOSFET Models In BSIM3v3 this equation is approximated which results in a phantom second roll up when Leff becomes very small To avoid this effect the exact formulation is used in BSIM4 Model flexibility is increased for different technologies with additional parameters introduced and the short channel and drain induced barrier lowering effects are modeled separately This leads to a short channel effect coefficient of the form SCE th LO gt cosh DYTI lt 1 i t and a variation of V
345. erimeter is labeled LG and has dimensions of m Parameters are specified for each of these three sub regions separately To enable these parameters to be uniquely determined at least three different source drain regions must be measured with various dimensions for the three sub regions The present implementation assumes that three different test structures labeled area locos and gate will be measured as shown in the following table Test Structures for JUNCAP Model DUT AB LS LG area AB1 large LS1 small LG1 zero locos AB2 small LS2 large LG2 zero gate AB3 intermediate LS2 LG3 non zero intermediate The parameters AB1 AB2 and AB3 are the areas associated with the three DUTs LS1 LS2 and LS3 are the LOCOS perimeters and LG1 LG2 and LG3 are the gate perimeters In the area DUT the contribution of the area sub region is assumed to be large while the contributions of the locos and gate sub regions are small or zero The locos DUT is assumed to have a larger contribution from the locos sub region and the gate DUT has a non zero contribution from the gate sub region The capacitance associated with any DUT is considered to be the sum of the contributions of the three sub regions For example for the DUT gate the capacitance at any voltage V is given by C V C_AREA V AB3 C_LOCOS V LS3 C_GATE V LG3 where C_AREA V C_LOCOS V and C_GATE V are the normalized contributions of the area locos and gate sub regions at voltage V
346. ers to be extracted during this extraction step You can select a device of your choice within the Devices folder or use the Default button to be found on Devices to accept the default transistor suggested by AdMOS To the left of the Interactive Plot window the extraction step and the extraction function for the selected step are shown Start extraction by clicking Execute The parameters are extracted and the plot window shows the simulated diagrams together with the measured ones Now you are able to Store the results or continue the extraction process without storing intermediate results Use the gt button to go on to the next step inside the extraction flow or extract all parameters of this step using the gt gt button o During extraction of some parameters inside the Extract folder the Region Boundaries section is activated Then you are able to select a specific extraction region by using Show button The upper left of the plots is now showing a rectangle This is the region where extraction takes place You are able to change the predefined extraction area by opening a rectangle in Plot O the upper left plot using the left mouse button A rectangle is shown If you are satisfied with the selected area use the right mouse button and select Add 55 MOSFET Models Region The added rectangle now changes color and is used as the extraction region for this step Remove the rectangle the defined region is still valid by using Hide
347. ertain MOS production process is given The next group of parameters are the temperature modeling parameters The following table lists parameters that are used to model the AC behavior of SOI MOS transistor Finally there is a table listing the parameters used to model the RF behavior for the BSIM SOI model Model Selection Flags Table Model Selection Flags Parameter Default Values Type of Model Description of values LEVEL 10 BSIMSOI model selector in UCB SPICE SOIMOD 0 SOI model selector BSIMPD Unified model for PD amp FD ideal FD auto selection by BSIMSOI MOBMOD 1 Mobility model selector Mobility model based on the effective electrical field concept WIN eO m Mobility model for depletion mode devices Like MOBMOD 1 body bias dependence included CAPMOD 2 Intrinsic Capacitance model selector 1 In BSIMSOI CAPMOD 0 and 1 are not supported model based on BSIM3v3 2 short channel capacitance model WIN WIN oO charge thickness model FNOIMOD 1 Flicker noise model selector 0 simple flicker noise model 1 unified physical flicker noise model TNOIMOD 0 Thermal noise model selector 0 charge based thermal noise model 1 heuristic thermal noise model SHMOD 0 Self heating model selector 0 no self heating 1 self heating RGATEMOD 0 Gate resistance model selector 0 No gate resistance 1 Constant gate resistance 2 Rii model with variable resistance 3 Rii model using two nodes RBODYMOD 0 Body res
348. es are to be given in microns um 33 MOSFET Models Note W AD AS PD and PS are total values including all fingers of the device Depending on your choice of temperatures on the Temperature Setup folder one or more columns marked with the temperatures you have entered appear The fields of those columns show either 0 for no measured data available M for DUT already measured or for DUT not to be measured at that temperature You can enter a comment for each DUT If you are using a switch matrix you can enter a module name as well as the pin numbers of the switch matrix pin connections to the transistor Only relevant connections should be entered In the case of the bulk drain diode no source connection should be entered the appropriate field shows a dashed line See Device geometries for details on device geometries and Test Structures for Intrinsic Capacitance Measurements mosfet for requirements on a proper extraction of diode data To delete DUTs Choose Delete from the icons or menu You will be prompted with a list of DUTs Select the DUTs to be deleted and click Delete on the Delete DUT folder A prompt dialog box appears Choose OK if you are satisfied with your choice of DUTs to be deleted To select devices to be measured at different temperatures Choose Temperature Measurement from the Configuration menu You will be prompted with a list of DUTs Select the devices to be measured at the temperatures entered
349. es in the drain diffusion Multiplied by Rsh to obtain parasitic drain resistance Rd 374 0 8 volt 0 5 1x10716 Amp 1x10 4 A m2 0 Ohm 1000 V cm t 600 cm2 V x S Om si O Meter 100 x 107 9 Meter 1 O Meter O Meter o vi 2 O Volt 0 2 0 A V2 O Volt 1 x 1074 Meter 1 x 1074 Meter 0 m2 Om 1 0 MOSFET Models Equivalent Squares in Source Diffusion Number of equivalent squares in the source 1 0 diffusion Multiplied by Rsh to obtain parasitic source resistance Rs Ran Junction Perimeter Used with CJSW and MJSW to model the junction sidewall 0 Meter capacitance of the drain Source Junction Perimeter Used with CJSW and MJSW to model the junction sidewall 0 Meter capacitance of the source General LEVEL Extraction Level Specifies one of four extraction levels 1 MOSFET Setup Attributes DUT Setup Setup Inputs Outputs Tra nsform Fu nction Extractions LEVEL 2 LEVEL 2 Model large idvg vg vb vd vs extract MOSDC_lev2_lin_large NSUB UO UEXP VTO optimize NSUB UO UEXP VTO narrow idvg extract MOSDC_lev2_lin_narrow DELTA WD optimize DELTA WD short idvg V extract MOSDC_lev2_lin_short LD XJ optimize LD RD RS XJ short idvd vd vg vb vs lid s MOSDC_lev2_sat short lev2_sat_short NEEMA VMAX optimize NEFF VMAX as cjdarea g vd 5 E CJ n zero bias CJ extract Optimize Ic MJ PB L ER vb vd
350. es resistance at TR Coefficient for the length times width dependence of source drain series resistance at TR m 3 m 3 m 3 V 1 V 1 V 1 m2s V m2s V m2s V m2s V m V m V m V m V V 1 0 7E 2 jo oO oO 30 280 POSTRS PORSB PORSG Velocity Saturation Parameters POTHESAT PLTHESAT PWTHESAT PLWTHESAT POSTTHESAT PLSTTHESAT PWSTTHESAT PLWSTTHESAT POTHESATB PLTHESATB PWTHESATB PLWTHESATB POTHESATG PLTHESATG PWTHESATG PLWTHESATG Saturation Voltage Parameters POAX PLAX PWAX PLWAX Channel Length Modulation CLM Parameters POALP PLALP PWALP PLWALP POALP1 PLALP1 PWALP1 PLWALP1 POALP2 PLALP2 PWALP2 PLWALP2 POVP Impact Ionization Parameters POA1 MOSFET Models Coefficient for the geometry independent part of temperature dependence of RS Coefficient for the geometry independent part of back bias dependence of RS Coefficient for the geometry independent part of gate bias dependence of RS Coefficient for the geometry independent part of velocity saturation parameter at TR Coefficient for the length dependence of velocity saturation parameter at TR Coefficient for the width dependence of velocity saturation parameter at TR Coefficient for the length times width dependence of velocity saturation parameter at TR Coefficient for the geometry independent part of temperature dependence of THESAT Coefficient for the length dependence of
351. es the total width of all fingers in one block in our case this is W Wf NF Wf 4 width of one finger times the number of fingers Our model device consists of four blocks Blocks 4 In BSIM4 the model selector GEOMOD is used to select a geometry dependent parasitics model that specifies whether the end source drain diffusions are connected or not The default value is 0 not connected The parameter RGEOMOD is the source drain diffusion resistance model selector It specifies the type of end source drain diffusion contact type point wide or merged contact The default value is 0 no source drain diffusion resistance See the BSIM4 manual from UC Berkeley 1 on page 11 5 and 11 6 for a definition of GEOMOD and RGEOMOD model selector values The parameters NRS NRD and MIN are the layout dependent parameters Number of Source Drain diffusion squares and Minimization of diffusion squares for even numbered devices They are set to their default values 0 too The last column enables you to enter a comment for this DUT DUTs folder all options are activated mem BSIM4_RF_Measure 6 Fie Configuration Data Tools Help Status De embed um um um um fum um jemo iw kiN Po mp jses isa 0o25 j6 32 MD Set 025 1 f ji i t J M D __ Set 1 32 0 25 8 TMD Set 2 64 0 25 16 36 Project Example_Scale Project drectory j users defauk_2009 St
352. esistance Gate bias dependence of LDD resistance Number of source diffusion squares Number of drain diffusion squares MOSFET Models 5 3E6 0 032 0 08 0 07 DROUT NMOS 670 PMOS 250 MOBMOD 0 and 1 1E 9 MOBMOD 2 1E 15 1E 19 MOBMOD 1 0 0465 MOBMOD 0 and 2 0 0465E 9 1E14 0 1E 8 NMOS 1 67 PMOS 1 0 8 0E4 1 0 0 0 1 0 0 0 0 0 0 0 0 047 0 08 0 0 0 0 1 0 0 0 2 4E 4 0 0 0 0 200 0 0 100 0 0 100 1 0 0 0 1 0 1 0 1 0 220 1 m 1 V 1 V cm 2 Vs m V m V 2 1 V m V 2 1 m 2 1 m 2 m m s 1 V 1 V 1 V mV F m 2 F m 2 F Vm 2 F Vm Q um WR Q um WR Q um WR Q um WR Q um WR Q um WR V 0 5 1 V MOSFET aati Channel geometry ant Channel width offset parameter T Coeff of length dependence for width 0 0 m W K En WLN Power of length dependence for width offset WW Coeff of width dependence for width fe m WWN offset WWN Power of width dependence for width 1 0 offset i Coeff of length and width cross term for width offset nen Channel length offset parameter CES Coeff of length dependence for length 0 0 offset nt Power of length dependence for length ees E e LW Coeff of width dependence for length fe m LWN offset LWN Power of width dependence for length 1 0 offset LWL Coeff of length and width cross term 0 0 m for length offset LWN LLN LLC Coefficient of length d
353. est Structures for CV Measurements mosfet describes the effects of de embedding It is intended to give you an insight into de embedding methods and describes the results of S Parameter measurements with and without de embedding Related Topics RF Notes mosfet RF Measurement Conditions mosfet DUTs mosfet RF Options mosfet Back to RF Measurement mosfet DUTs The DUTs folder is used to define transistor geometries for the DUT to be measured Following the column for entering the name of the DUT there is a column showing the status of the DUT This column shows 0 if no measurement and de embedding has been performed It changes to M if a measurement has been performed and to M D if measurement and de embedding has been done The geometries to be entered into the following columns are Width and Length of the transistor Number of transistor Fingers NF Drain and Source Area and Perimeter Length AD AS PD PS If the appropriate check boxes are checked or if the menu item Configuration gt Geometric Entries has been set to GEOMOD 0 RGEOMOD 0 or NRS 0 NRD 0 and so on the model selectors GEOMOD and RGEOMOD appear as a column applicable to BSIM4 PSP only and are set to their default values 0 The columns NRS NRD and MIN are originally BSIM4 parameters but are used also inside the extended BSIM3 model from AdMOS Note W AD AS PD and PS are total values including all fingers of the device There are two n
354. et chuck temperature manually IC CAP does not support heated chuck drivers If you select measurement of a module all DUTs in this module are measured automatically if the use of a switch matrix is activated The DUTs Setup folder in the BSIM3 4_DC_CV_Measure model contains an AutoMeasure setup for the Configuration DUT Using this AutoMeasure setup you can program automatic measurements for all DUTs in one module Note Automatic measurement uses a macro for the wafer prober This macro is programmed to start measurement as soon as the wafer prober has reached its programmed destination You ll find the macro Example_Wafer_Prober and it s transforms together with a description of the transforms in the Macro folder of the BSIM3 4_DC_CV_Measure model e If you would like to clear some or all measured data select Clear Data from the Data menu You can select whether you would like to clear measured data of some or all DUTs at specified temperatures and choose Clear Data to delete measured data files Using the Data menu s Synthesize Measured Data you can simulate data from existing model parameters By selecting this feature already measured data files are overwritten with synthesized data You will be prompted before existing data files are overwritten There is the choice of either synthesizing data or loading an MPS File This synthesized data uses the voltages set on the Measurement Conditions folder to generate measuremen
355. eter Description Default Value Unit TNOM Nominal Temperature 27 C UTE Mobility temperature exponent 1 5 KT1 Threshold voltage temperature coefficient 0 11 Vv KT11 Channel length dependence of KT1 0 0 vm KT2 Body bias coefficient of KT1 0 022 UAL Temperature coefficient for UA 4 31E 9 m V UB1 Temperature coefficient for UB 7 61E 18 m v luci Temperature coefficient for UC 0 056 41 V PRT Temperature coefficient for RDSW 0 0 Ww yum AT Saturation velocity temperature coefficient 5 364 m s TPBSWG Temperature coefficient for PBSWG v K TPBSWGD Temperature coefficient for PBSWGD Default source a value TI Temperature dependent parameter for impact ionization current ERT Temperature coefficient for CISWG a 1 K TCJSWGD Temperature coefficient for CISWGD Default source oa value CTHO Normalized thermal capacity 1E 5 RTHO Normalized thermal resistance WTHO Minimum width for thermal resistance calculation 0 im XBIT Power dependence of Jbjts on temperature 1 XDIF Power dependence of jy son temperature XBJT l XREC Power dependence of j on temperature 1 i XTUN Power dependence of j on temperature 0 k XDIFD Power dependence of jgifg on temperature XBJT l XRECD Power dependence of j ecg on temperature 1 i XTUND Power dependence of jtung on temperature 0 Noise Model Parameters Table Noise Modeling Parameters 319 MOSFET Models Parameter Description Default Valu
356. eters by splitting the C V data into the area locos and gate contributions and optimizing the parameters to these At the end of the extractions the simulated C V arrays in the area locos gate and analysis DUTS are updated with the new parameters extract_fwd_iv_pars This macro controls the extraction of the forward I V parameters by splitting the forward I V data into the area locos and gate contributions and optimizing the parameters to these At the end of the extractions the simulated I V arrays forward and reverse in the area locos gate and analysis DUTS are updated with the new parameters extract_rev_iv_pars This macro controls the extraction of the reverse I V parameters by splitting the reverse I V data into the area locos and gate contributions and optimizing the parameters to these At the end of the extractions the simulated I V arrays forward and reverse in the area locos gate and analysis DUTS are updated with the new parameters opt_all_cv This macro controls the optimization of the full set of C V parameters with respect to the measured data in the area locos and gate DUTs At the end of the extractions the simulated C V arrays in the area locos gate and analysis DUTS are updated with the new parameters opt_all_fwd_iv This macro controls the optimization of the full set of I V parameters with respect to the measured forward I V data in the area locos and gate DUTs At the end of the extractions the simulated I
357. eters so they can be taken into consideration in the first extraction step A more accurate value for each is produced by the second and third extractions When a very large device is not available and you cannot enter LD and WD try the following 1 Use the largest available device for the large setup and execute all four steps of the DC extraction 2 Repeat the extraction sequence starting with the first step you do not need to re enter the parameters The previously extracted parameters particularly LD and WD are used as the initial values To extract DC parameters when only one size of device is available extract model parameters using the following sequence This sequence does not extract geometry dependent parameters but does extract a subset of parameters to fully model that size device 1 Perform the large idvg extraction to obtain the classical parameters 2 Perform the short idvd extraction to obtain the saturation parameters Enter the same L and W device parameters for both DUTs The model can be reconfigured so that it has only one DUT with two setups one similar to idvg and one similar to idvd Copy the setup from large idvg and the setup from short idvd copy complete setups so the appropriate extraction and optimization functions are included If you cannot determine the L and W for a single geometry device as might be the case with a packaged transistor set estimated values The actual values are less important
358. ew The MOS Modeling Packages allow the user to define his own extraction functions and insert them into the GUI Extract folder as well as to extend an existing standard optimizer tuner or an extraction The following paragraphs describe how the user can modify existing functions or implement his own extraction functions 72 MOSFET Models Modifying Existing Functions Modifications of existing tuners or extraction functions are overwritten with the default installation routine of IC CAP Therefore changes should be saved before updating IC CAP and added again afterwards As an example the following sections are discussing how to extend the existing tuner optimizer T O UO UA UB EU UC by adding additional plots and parameters We will use the large transistor as an example e Tuner T UO UA UB EU UC extended by a plot second derivative of the drain current an extraction region and the parameter DELTA 48 BSIM4_DC_CV_Extract 2 File Initialize Binning Extract Plots HTML Options Boundaries Tools Help oo TE je E a SE BPP FF tee XE BFE aa Notes Information Initialize Binning Extract HTML Options Boundaries Extraction Flow Selected Extraction Step Data Available Functions m Reset Parameters and Results amp E U Global E UA UB EU t 3b Capacitance Oxide E UA UB UD EU ak Large Basic Yth Mobility E VTH rough E u0 Gy E VOFF NFACTOR E
359. ewly introduced instance parameters Blocks Number of Blocks and NGCON Number of Gate contacts The Blocks parameter is actually a multiplier for the transistor The other parameters L W AD AS refer to Blocks 1 The second new parameter NGCON defines the number of Gate contacts a transistor actually has thus reducing resistance for example Those parameters can be activated or deactivated using the menu Configuration gt Geometric Entries By default both parameters are on and set to 1 If they are set to off the columns inside the DUTs folder will not be present Note The DUTs folder looks the same for BSIM3 and BSIM4 PSP However this folder contains some parameters and model flags that are only applicable for BSIM4 PSP The default values for parameters not used in BSIM3 are set in such a way that BSIM3 ignores them This is done to make the form compatible for both models The following graphic describes how the parameters are used to describe an example device consisting of four blocks each having 4 fingers as shown in the inset to the left top of the following figure Number of blocks M Multiplier Number of fingers in one block Je Confiquesesn One ols Help EAE LAL x Mow Mesosrenen Condsons De ebedding Pad Souctres os Q out Width of all fingers in one block W WPNF Proyect drectory d focal romas rca 07 ham 45 MOSFET Models The parameter W declar
360. example procedure with step by step instructions to achieve data acquisition and model generation This complete procedure includes the steps required to generate a new device model by modifying variable values in macros and factory default tables After setting the variables subsequent measurement and model generation are much faster Model Description The Agilent Root MOSFET model applies to MOS devices with the same database modeling principles as used in the Root FET model This three terminal model can be applied to vertical LD and power MOS devices where substrate effects are not required to be a part of the model It can be used for both NMOS and PMOS devices Similarly to Root FET model the Root MOS model is generated from small signal S parameters measured at numerous bias points over the entire operating current voltage IV plane Based on current and power dissipation device compliance provided in software the data acquisition system calculates the safe operating range for the device Within this region the model takes data adaptively at multiple bias points depending on the specific nonlinearities of the device Measurements are densely spaced in the most nonlinear regions such as at the knees of the IV curves and the onset of breakdown However it is less densely spaced in linear regions The data set of internodal nonlinear current and charge components at each bias point is then mathematically generated and stored Therefore
361. extended equations that would be implemented in a circuit simulator Selects equation and parameter set for miniset maxiset single temperature or all temperature extraction 0 Use the miniset parameters to evaluate the currents These miniset parameters are read from the variable table of the DUT from which MM9 is invoked 1 Use the maxiset parameters and the full scaling rules but assuming operation at nominal temperature The maxiset parameters are read from the model parameter list 2 Use the full geometry and temperature scaling rules i e the normal model equation The model parameters are read from the model parameter list 3 Use the full geometry scaling rules with the geometry coefficients as read from the model parameter list However the values of the temperature sensitive parameters are read from the variable table of the model from which the function is invoked usually a model holding data at a non nominal temperature Device type 1 for NMOS 1 for PMOS Measurement temperature Indicates if there are multiple transistors connected in parallel Indicates how the devices are to be connected M manually A automatically with a scanner Number of temperatures at which the devices will be measured for temperature parameter extraction Name of system file in which the miniset parameters will be temporarily stored Name of system file in which the temperature specific parameters will be temporarily stored
362. extension m indicates the parameter values extracted ata single temperature while the extension s indicates the predicted value of the parameter using the temperature coefficients of the current model set assuming the plots have been updated with a call to the C transform MM9_TEMPPAR and the suffix _ sq indicates the fits that were obtained by the temperature coefficients obtained from the least squares extraction transform MM9_TEMPSCAL extract par_vs_L2 and par_vs_W2 enable parameter versus length plots for a user specified width and parameter versus width plots for a user specified length to be generated This is useful if the device set includes more than one L array and more than one W array The quick_ext DUT The quick_ext device contains the measurement templates and the transforms used for quick extraction of the miniset parameters of MOS Model 9 The DUT variables are used to store the current values of the miniset parameters as they are being extracted quick_ext lin_quick_ext is used during the extraction of the linear region parameters It contains input definitions for the bias voltages vd vg vs and vb as well as the definition for the current to be measured id The in_quick_ext setup contains the following inputs and outputs vd A constant value set by the variable VDS vg A list with three voltages set by the variables VGSO VGS1 and VGS2 vs A constant value of OV vb A constant value set by the variable V
363. f diffusion between gate and STI reference length of diffusion between gate and STI Description Unit F cm 2 m 1 cm 3 5 cm 3 3 3 3 3 3 Unit Parameter Default Range Range Name min max WL2 0 WL2P 1 0 MUEPHS 0 MUEPSP 1 0 VOVERS 0 VOVERSP 0 Substrate Current Parameters threshold voltage shift due to small size effect threshold voltage shift due to small size effect mobility modification due to small size mobility modification due to small size modification of maximum velocity due to small size modification of maximum velocity due to small size 240 MOSFET Models Parameter Name Default Range Range max Description Unit min ee pee aaa current coefficient of magnitude is 1 SUB1L 2 5E 3 Lgate dependence SUB1 im SUB1LP 1 0 Lgate dependence SUB1 p pu B pee current coefficient of exponential V term Is SUB2L 2 2E 6 0 1 0 Lgate dependence of SUB2 Im ls SVDS 0 8 substrate current dependence on Vds p ls SLG 3 3E 8 substrate current dependence on Lgate im ls SLGL 0 substrate current dependence on Lgate im SLGLP 1 0 substrate current dependence on Lgate p SvBS 0 5 substrate current dependence on Vbs E SVBSL 0 Lgate dependence of SVBS Im SVBSLP 1 0 Lgate dependence of SVBS p SVGS 0 8 substrate current dependence on Vgs SVGSL 0 Lgate dependence of SVGS im SVGSLP 1 0 Lgate dependence of SVGS p SVGSW 0 Wgate dependence of SVGS Im SVGSWP
364. f drain side are copied to those of source side LDMOS asymmetrical Structural parameters have to be determined for both source and drain HiSIM_HV solves the Poisson equation iteratively including the highly resistive drift region effects depending on the structure of the MOS transistor to be modeled The following figure cross section through a LDMOS and a HVMOS structure shows the drift region resistance parameters and their usage 230 MOSFET Models Asymmetrical LDMOS Channel Symmetrical HV MOS Ldrift2 Ldrift Loverld Channel Asymmetrical HV MOS Ldrift2s Ldriftis Lovers Novers Channel With Version 1 1 1 of the HiSIM_HV model you have the choice of using an asymmetrically structured HVMOS transistor The lower part of the figure above shows the geometrical meaning of parameters of the asymmetrical model Version HiSIM_HV 1 2 0 includes LDMOS devices with additional substrate node Therefore additional parameters have been introduced to cover this situation VBISUB RDVDSUB RDVSUB DDRIFT and NSUBSUB Larita Drift Region N Channel Region N subsub V sub s Cross Sections and Drift Resistance Parameters There is a limit for the bulk voltage considered to model the bias dependency of the drift region resistance This limit is set per default to Vbs min 10 5V However there is a parameter that can be used to override this default setting call
365. f impact ionization current Second Vpg dependent parameter of impact ionization current parameter of impact ionization current n Third Vps dependent parameter of impact ionization current v LII Channel length parameter at threshold for 0 impact ionization current ESATII Saturation channel electric field for impact ionization current 1E7 V m suo First Vgs dependent parameter of impact ionization current 0 5 su Second Vgs dependent parameter of impact ionization current suz2 0 Third Third Vpg dependent parameter of impact ionization current Third Vpg dependent parameter of impact ionization current of impact ionization current a Vps dependent parameter of drain saturation voltage for impact ionization current AGIDL p re exponential GIDL constant 0 BGIDL GIDL exponential coefficient 2 3E V m 2 poe aa for body bias effect on GIDL a i 3 EGIDL Fitting parameter for band bending for GIDL 1 2 V called NGIDL in BSIMSOI3 316 MOSFET Models 2 9 Diode and BJT characteristic NTUN Reverse tunneling non ideality factor source side 10 0 NTUND Reverse tunneling non ideality factor drain side 10 0 NDIODE Diode non ideality factor source side 1 0 NDIODED Diode non ideality factor drain side 1 0 NRECFO Recombination non ideality factor at forward bias for 2 0 Source NRECFOD Recombination non ideality factor at forward bias for default to source Drain value NRECRO Recombination non ideal
366. fficient extraction You can also specify minimum current and conductance levels for extraction You can use setup to modify existing information as well as specify new information The setup information is held in the model variable table of MM9 and in the devices and all_temp_ext setups of the extract DUT Any information that can be represented by a single value is held in the variable table while information represented as an array is held in the setups When SETUP is run the information is first read from the existing IC CAP arrays or variables At the end of SETUP the information is written back into the IC CAP tables or arrays SETUP also builds optimization tables for use in the maxiset and temperature extractions and puts them in the setups sca ed_ext single_temp_ext and all_temp_ext measure Controls the measurement sequence for all specified devices The macro prompts you to specify whether you want to measure the devices at the nominal temperature or at another temperature The template for the measurements is located in dutx When you measure devices at the nominal temperature dutx is copied as dut1 dut2 etc for each device specified and then the measurement transforms are invoked in each of these new DUTs When you measure devices at non nominal temperatures a new model is created for each specified temperature by copying mm9_tempx to a new model mm9_tx where x is a number representing the temperature extract_one_minise
367. ffset of V 0 PLWDPHIB Coefficient for the length times width dependence of V 0 offset of PONP Coefficient for the geometry independent part of m 3 1E26 gate poly silicon doping PLNP Coefficient for the length dependence of gate poly m 3 0 silicon doping PWNP Coefficient for the width dependence of gate poly m 3 0 silicon doping PLWNP Coefficient for the length times width dependence of m 3 0 gate poly silicon doping POCT Coefficient for the geometry independent part of 0 interface states factor PLCT Coefficient for the length dependence of interface 0 states factor PWCT Coefficient for the width dependence of interface 0 states factor PLWCT Coefficient for the length times width dependence of 0 interface states factor POTOXOV Coefficient for the geometry independent part of m 2E 9 overlap oxide thickness PONOV Coefficient for the geometry independent part of m 3 5E25 effective doping of overlap region 279 Wi re PLNOV PWNOV PLWNOV DIBL Parameters POCF PLCF PWCF PLWCF POCFB Mobility Parameters POBETN PLBETN PWBETN PLWBETN POSTBET PLSTBET PWSTBET PLWSTBET POMUE PLMUE PWMUE PLWMUE POSTMUE POTHEMU POSTTHEMU POCS PLCS PWCS PLWCS POSTCS POXCOR PLXCOR PWXCOR PLWXCOR POSTXCOR POFETA Series Resistance Parameters PORS PLRS PWRS PLWRS MOSFET Models Coefficient for the length dependence of effective doping of overlap region Coeffi
368. ffusion of channel stop dopant ions Effective channel length offset for m CV Effective channel width offset for m 7 7 K VFB F Flat band voltage at TR Vv VFBO Geometry independent flat band V voltage at TR VFBL oe dependence of flat band voltage VFBW G Eg dependence of flat band 0 voltage VFBLW G Ee dependence of flat band 0 voltage STVFB sts L Temperature dependence of VFB V K 5E 4 Bile eae independent Me 5E 4 temperature dependence of VFB ls STVFBL Lo iLength dependence of STVFB ooo STVFBW i Width dependence of STVFB STvFBLM IL Area dependence of STVFB TO IL Gate oxide thickness at local level I m 2E 9 l1 1E 10 p 10o i lt oxide thickness at global i 2E 9 10 level NEFF IL Substrate doping m 3 5E23 1E20 1E26 NSUBO G Geometry independent substrate ca 3E23 1E20 fF doping NSUBW G Width dependence of substrate 0 doping due to segregation WSEG G Characteristic length of fee 1E 10 FS segregation of substrate doping NPCK fe Pocket doping level m 3 1E24 0 NPCKW G Coefficient describing width 0 dependence of pocket doping due to segregation joes e Gea length of i 1E 8 m i segregation of pocket doping LPCK G Characteristic length of lateral m 1E 8 1E 10 doping profile LPCKW G Coefficient describing width 0 dependence of characteristic length of lateral doping profile FOL1 G First order length dependence of 0 short channel body effect FOL2 G Second order length dependence 0 of shor
369. ficient for the geometry independent part of gate overlap current pre factor Coefficient for the length dependence of gate overlap current pre factor Coefficient for the width dependence of gate overlap current pre factor Coefficient for the length times width dependence of gate overlap current pre factor Coefficient for the geometry independent part of temperature dependence of gate current Coefficient for the geometry independent part of gate current slope factor Coefficient for the geometry independent part of gate current curvature factor Coefficient for the geometry independent part of tunneling barrier height Coefficient for the geometry independent part of GIDL pre factor Coefficient for the length dependence of GIDL pre factor Coefficient for the width dependence of GIDL pre factor Coefficient for the length times width dependence of GIDL pre factor Coefficient for the geometry independent part of GIDL probability factor at TR Coefficient for the geometry independent part of temperature dependence of BGIDL Coefficient for the geometry independent part of back bias dependence of GIDL Coefficient for the geometry independent part of oxide capacitance for intrinsic channel Coefficient for the length dependence of oxide capacitance for intrinsic channel Coefficient for the width dependence of oxide Capacitance for intrinsic channel Coefficient for the length times width dependent part of oxide capa
370. folder including electrical process or measured gate oxide thickness TOXE TOXP TOXM junction depth doping concentrations and sheet resistances You will find a description of the model parameters and model flags for the BSIM4 model in Main Model Parameters mosfet and for the PSP model in Parameters for the PSP model mosfet See also the manual from UC Berkeley Appendix A Complete Parameter List for more details on model parameters as well as the PSP manual Entering values into the fields and selecting the Save button starts a routine to check the values entered This routine will flag an error message and change the color of the field whose parameter is given an unrealistic value For example if you enter 3 into the EPSROX field this field will be marked with red color and remains red until the value is corrected You are able to add BSIM4 PSP parameters to the Initial Values by clicking Add Parameter inside the Initialize menu You will be prompted with a list of BSIM4 PSP parameters Select the parameters you would like to add and click OK The parameters are added and you are able to enter initial values as desired The Model Flags section is used to set BSIM4 PSP model flags The fields only enable settings as defined in the BSIM4 PSP model and are predefined to standard settings There is a field defining the symmetry of the drain and source areas Check the appropriate box es if drain and source are processed using the sam
371. for Igb in accumulation 0 43 BIGBACC BIGBACC Parameter for Igb in accumulation 0 054 CIGBACC CIGBACC Parameter for Igb in accumulation 0 075 NIGBACC NIGBACC Parameter for Igb in accumulation 1 0 AIGBINV AIGBINV Parameter for Igb in inversion 0 35 BIGBINV BIGBINV Parameter for Igb in inversion 0 03 CIGBINV CIGBINV Parameter for Igb in inversion 0 006 NIGBINV NIGBINV Parameter for Igb in inversion Led Gate to Channel Current Igc The gate to channel current is determined by electrons tunneling from the conduction band in NMOS transistors respective holes tunneling from the valence band in PMOS transistors TOY NTOX loe W afr Loff E LOAREI l lt 7 7 g g TOXE Pas VIBO NIGC v J 7 gse eo NIGC v log i 1 exp exp F TOXE AIGC BIGC V oxdepinv 1 CIGC V oxdepinv The physical constants E and F are listed in the table Values of constants for gate channel and gate S D tunneling below Gate to Source and Gate to Drain tunneling currents These currents tunnel from the gate contact to the source or drain diffusion regions They are caused by electron tunneling from the conduction band in NMOS transistors and by hole tunneling from the valence band in PMOS transistors Fas Waff DLCIG E l eRatiokdge l Pis V _ exp F TOXE POXEDGE gs AIGSD BIGSD V 1 CIGSD V r j gt e Vos NA Vos V thsa le 4 For the computin
372. g PSP Scale Parameters Global a Local Long Wide Local Long Width Dependence PSP Scale Parameters a Local Short Wide Local Length Dependence Wide PSP Scale Parameters Short Width Dependence 2 Global OH PSP Scale Parameters Local Length Width Dependence PSP Scale Parameters Ge Ge ee eh S S A A A S S e L S la Save Parameters With this default flow there are sequences of extraction for the Global model mixed with extractions for the Local model If you choose the Global extraction flow the extraction sequence will be as shown in the next figure Extraction Flow Data m Reset Parameters and Results i a Global 3b Capacitance Oxide 3b Capacitance Overlap 3 Capacitance Junction th Diode S Global 4k Large Vth Mobility Saturation Velocity f Large Gate Current 4 Large Impact Ionization and GIDL 4k Length Scaling Vth Mobility Saturation Velocity 4k Width Scaling amp Corner f Length Width Scaling Global 4 ak Temperature h STI Stress Effect la Save Parameters EHE eh eh E m This default extraction flow doesn t contain extractions for the Local model only Global extractions are present See Also Extraction of Parameters using the Local Global approach mosfet Simultaneous Adjustment of Local and Global Parameters mosfet Binning of PSP Models mosfet Parameters for the PSP model
373. g This model file shows the typical extraction flow to generate a binned simulation model If you create a binned model make sure the Generate Binning Model flag in the Initialize folder is marked and the bins are set correctly to include the available devices into the defined bins See details in Binning appendixb When you open the example you can see that the Generate Binning Model marker on the Initialize folder is activated and the bins are set according to the devices available Binning Extraction Flow The general extraction flow for a binned project is shown in the following screenshot The extraction flow follows the general rules as previously described see Extraction of 267 MOSFET Models Parameters for the PSP Model mosfet After extracting global model parameters local parameters for the devices selected inside the different bins during initialization are extracted Then the calculation of the binned model is done before global parameters like the ones used for Stress Effect modeling are handled File Initialize Binning Extract Plots HTML Options Boundaries Help aS Bilel S ele x Notes Information Initialize Binning Extract HTML Options Boundaries Intermediate Results Start with global parameters Generate all local models Calculate binned model Extract further global effects Furthermore the extraction of the local models should be done in a special order to preserve the correct na
374. g Rules This section describes the scaling rules applied to individual parameters ALP ALP ALPR 1_ L f y ee ee A a ETAALP ETAALP W eft er i ei Wer where ETAALP O or 1 BET W dW BET BETSQ e lt L dL e where dW 2WOT WVAR and dL 2LAP LVAR e Here BETSQ dW and dL can be extracted by a nonlinear fit to the miniset parameter BET versus W and L GAMOO MO ZET1 and VSBT a 1l 1 P W L Pp Wen LY ett IS where n can have the value of 2 0 5 ETAZET 0 5 or 1 or 1 Here the reference parameter Pp and the scaling coefficients S and Sy can be extracted by linear regression The quantities W and L are the effective width and length of a reference device you choose KO K VSBX THE1 THE2 THE3 GAM1 A1 A2 and A3 j 1 P W L Pp PEM ww et er ef er VP L a pp _ eit VP VPR L f er VTO VTO VTOR sz imao st2vTO swvro Leff Tew Lir Lar ett Fer Device Geometries The recommended criteria for selecting devices for extraction is illustrated in the following figure where L array represents a set of devices with the same width but different lengths and W array represents a set of devices with the same length but different widths Device Size Selection L arma A Y Width e o0 ooo o Intermediate Sizes W aray B 2 Minimum Device B Length A quantity Rag is defined to aid visualization
375. g of I_ the values of Vgs in equation above has to be replaced by Vga gd The flat band voltage between and the source or drain diffusion areas is dependent from NGATE If NGATE gt 0 0 fbsd q a NS D j Else V bsd 0 To take drain bias effects into account the tunneling current from the gate contact splits Im tI gc ges f map gcd into two components and itis The components are calculated as 199 MOSFET Models PIGCD V exp PIGCD V 1 le 4 Iges lge 2 2 PIGCD V 2e 4 1 PIGCD F 1l exp PIGCD V 35 le 4 I ee ag a lt a ged ge PIGCD V 2e 4 If the model parameter PIGCD is not specified it is calculated by _ B TOXE Vasett PGC Voste fo Estep The constants used in the equations above have different values for NMOS and PMOS transistors Values of constants for gate channel and gate S D tunneling NMOS PMOS E 4 97232 A V 3 42537 A V F 7 45669E11 fi z 1 16645E12 Partl Part2 Part3andPart4 7 45669E11 Ng F s Gate Tunneling Parameters continued from Gate Tunneling Parameters Equation BSIM4 Description Default Value Variable Parameter DLCIG DLCIG Source Drain overlap length for Igs and Igd LINT POXEDGE POXEDGE Factor for gate oxide thickness in 1 0 source drain overlap regions AIGSD AIGSD Parameter for Igs and Igd NMOS 0 43 PMOS 0 31 n Fs g m BIGSD BIGSD Parameter for Igs and Igd NMOS 0 054 PMOS 0 024 f 9
376. ge at least as wide as the operating range of the device Set the CW frequency segment to the frequency you intend to use for the data acquisition the same frequency you set in the model variable table at the beginning of this procedure This frequency should be above 200 MHz to eliminate the effects of test set coupler roll off at low frequencies and low enough to eliminate bond inductances and other parasitic inductance considerations Based on the broadband cal use a calibrated measurement point equal to the start frequency plus an integer multiple of the step size An example frequency might be 600 MHz 200 MHz start freq 1 400 MHz step size 600 MHz Frequency List Calibration for an Agilent 8510 Based System If you are using an Agilent 8510 based system follow the steps below 1 2 3 10 11 12 13 14 On the network analyzer press PRESET To define a linear frequency list on the network analyzer press STIMULUS gt MENU gt MORE gt EDIT LIST gt ADD A default frequency list segment is presented To change the segment to your chosen frequency range press SEGMENT START and use the numerical keypad to set the start frequency ending with one of the terminator keys such as M y at the right of the keypad Similarly press STOP and set the stop frequency Note Use the SEGMENT START and STOP softkeys not the START and STOP hardkeys in the STIMULUS area of the front panel Press SEGMENT NU
377. global extractions This feature is especially useful in a situation where one of the local devices might not fit into the global extractions Additional buttons are located at the bottom to Clear parameters to Save an actual copy of the parameters and to Close the window Back to PSP Characterization mosfet 266 MOSFET Models Binning of PSP Models Binning Rules in PSP The PSP Model Version 102 has 3 different binning rules with a fixed assignment to certain parameters e Type I Wen Loy Wey par L W POpar PLpar n 5 PWpar EN PLWpar EN EN e Type II Lp We Lp We par L W POpar PLpar PWpar PLWpar _ Ley W EN Len Wen e Type III Lew W Ley W par L W POpar PLpar PWpar PLWpar _ Lp Wen Le Wen Binning Parameters Parameter Explanation Name LE effective channel length WE effective channel width LEN normalized channel length 1E 6 WEN normalized channel width 1E 6 par LE WE effective parameter calculated by the simulator for a certain effective length and width par can be any binnable parameter VFB for example This parameter will be renamed in the binned PSP model Prefixes are added to name the dependency of the parameter PO PL PW or PLW The parameter VFB will become POVFB PLVFB PWVFB and PLWVFB Channel length reduction LE WE are calculated as a Wey 2 vee EN f Pd AL ps LVARO 1 LVARL 1 rvarw
378. global scaling and local extraction Using the Global Scaling folder you can select a parameter for global scaling select or deselect certain devices or disable parameters temporarily to have their influence isolated You can also save intermediate results or retrieve saved ones see the next figure You can start optimization or tuning for the selected configuration of devices parameters and plots 262 MOSFET Models Select parameter to adjust global scaling Perform Optimization or Tuning Devices can be de selected if necessary Parameters can be temporarily disabled Save and retrieve global results maintain history list Using the Local Extraction folder the same possibilities exist on the local level as can be seen in the following figure Inter me tiap tot 7 Device to modify local parameter set Select available Optimizers Tuners for this device Perform Optimization or Tuning _peannnnet i t gt lt 7 4 i t 2 t Save and retrieve local results maintain history list Generate a local model for the selected device from the global Adjust local parameter value scaling in the global scaling plot Setting up the Extraction Flow to Use this Feature Switch to the Extract folder Scroll down the Extraction Flow list to the PSP Scale Parameters extraction At this point add an extraction step Extractions gt Extraction Flow gt Add for example se
379. global extractions respective to the list of devices for binning extractions Extraction List Extraction Flow Data m Reset Parameters and Results E Gy Global Jb Capacitance Oxide ey E TOXE ACDE i T TOXE ACDE ak Large Basic Yth Mobility qb Capacitance Fringing and Overlap ak Length Scaled wth low Yd qb Capacitance Yth Shift in Overlap ak Short Rds Subthreshold Behavior 4 Large Bulk Charge Effect oot AR GE Le a Selecting an extraction step will show the available functions for this step in the right part of the window Selected Extraction Step Available Functions E TOXE ACDE gt T TOXE ACDE O TOXE ACDE There is also a message section in the lower right part of the extract folder You will get messages regarding the selected extraction step Extraction will start with Parameters of MPS Reset Parameters and Results lt gt gGlobal OO mps Result is not yet available You are able to select more than one extraction step for execution by using the Shift or Ctrl button of your keyboard Length Scaled Mobility Width Scaled Bulk Charge Effect Length Width Scaled wth low Yd All Transistors Finetuning Rds DW DL Capacit Junction Bulk Drain Diode Bulk Drain a Temperature All Parameters A STI Stress Effect Hie Well Proximity Effect ES aC a a If you
380. gt Measure Check the S parameter plots If the results are unexpected recheck the values you set in Inputs and Instrument Options In particular be sure the instrument states and input stimulus signals match the values you set in the network analyzer broadband calibration 1 If you change the inputs or instrument states repeat the measurement If the data still looks abnormal the device may be defective and may need to be replaced with an acceptable one 2 To save the measured data select File gt Save As type in an appropriate filename for example spar_test set and select OK 3 Close the plots If you are satisfied with the measured data for your device continue with the procedures Measuring and Extracting Parasitic Resistance Values This procedure measures the device S parameters across the frequency range of operation with the device in an unbiased condition that is with both the gate and drain bias set to zero Under these conditions the transconductance and drain conductance are negligible so the equivalent circuit consists only of the parasitic elements and 334 MOSFET Models capacitances The program calculates the intrinsic parasitic resistance from the measured data Device Configuration The input values you set in this procedure configure the device as shown in the following figure MOSFET Bias Configuration for parasitics Measurement ee NA PORT G Note Make sure you have calibrated the ne
381. hannel V 0 Current at VOFF The subthreshold swing parameter n is determined by channel length and interface state density and is calculated using C n 1 NFACTOR oxe 1 7 7 5 CDSC CDSCD V as CDSCB bseff Cir isc L FA oxe cosh DYTI oT 1 i The parameter NFACTOR is used to compensate for errors in calculating the depletion width capacitance Subthreshold swing parameters Equation BSIM4 Description Default Value Variable Parameter W W channel width 0 25E 6 L L channel length 5E 6 LL carrier mobility electrons 670 cm holes le Vsec VOFF VOFF Offset voltage in subthreshold region for large 0 08 mV W and L VOFFL VOFFL Channel length dependence of VOFF OV NFACTOR NFACTOR Subthreshold swing factor 1 0 CIT CIT Interface trap capacitance 0 F m 2 CDSC CDSC Drain Source to channel coupling capacitance 2 4E 4 F m 2 CDSCB CDSCB Body bias coefficient of CDSC 0 F Vm 2 CDSCD CDSCD Drain bias coefficient of CDSC 0 F Vm 2 Cdep depletion capacitance Gate Direct Tunneling Current Model Gate oxide thickness is decreasing therefore tunneling currents from the gate contact are playing an important role in the modeling of sub micrometer MOSFET s In BSIM4 the gate current consists of one part tunneling from gate to bulk Igb and one part tunneling from gate to channel Igc The latter one again is partitioned to flow to the source contact Igcs and to the drain contact Igcd
382. havior of the transistor This macro model approach results in a sub circuit for scalable RF SOI MOS transistors parts of which is listed below Part of the SOI RF macro model used echo MOIN mpar MOIN 15 0 306 MOSFET Models echo DELVT mpar DELVT 0 0 KB1 mpar KB1 1 0 DLBG mpar DLBG 0 0 echo TOXQM mpar TOXQM 10 0E 9 echo WTHO mpar WTHO 0 0 RHALO mpar RHALO 1E15 NTOX mpar NTOX 1 echo TOXREF mpar TOXREF 2 5E 9 echo EBG mpar EBG 1 2 VEVB mpar VEVB 3 LPHAGB1 mpar ALPHAGB1 0 35 echo BETAGB1 mpar BETAGB1 0 03 echo VGB1 mpar VGB1 300 VECB mpar VECB 1 echo BETAGB2 mpar BETAGB2 0 05 echo VGB2 mpar VGB2 17 VOXH mpar VOXH 5 0 echo NOFF mpar NOFF 1 0 echo NOIA mpar NOIA 1E20 NOIB mpar NOIB 5E4 NOIC mpar NOIC 1 4E 12 echo EM mpar EM 4 1E7 echo EF mpar EF 1 0 AF mpar AF 1 0 KF mpar KF 0 0 echo TNOIA mpar TNOIA 1 5 TNOIB mpar TNOIB 3 5 echo RNOIB mpar RNOIB 0 37 NTNOI mpar NTNOI 1 0 echo KT1 mpar KT1 0 11 KT1L mpar KT1L 0 0 KT2 mpar KT2 0 022 echo UA1 mpar UA1 4 31E 9 echo UB1 mpar UB1 7 61E 18 UCi1 mpar UC1 0 056E 9 UTE mpar UTE 1 5 echo AT mpar AT 3 3E4 echo TCJSWG mpar TCISWG 0 0 TPBSWG mpar TPBSWG 0 0 echo NGCON mpar NGCON 1 RSHG mpar RSHG 0 XRCRG1 mpar XRCRG1 0 echo XRCRG2 mpar XRCRG2 0 x Additional model parameters necessary for scalability scalab
383. he Initialize folders contain sections to enter PEL commands to be executed at initialization of the extraction process Model Parameter Sets From the Initialize menu you can Import DC CV Start Set to be used for RF extraction You get a list of existing mps files for selection A selected mps file will be copied into the RF project directory This action will set parameter values extracted from DC CV measurements as starting points for RF extraction Since the devices measured for RF extraction are very compact multifinger transistors due to design requirements and also to enhance accuracy through reducing measurement noise during network analyzer 114 MOSFET Models measurements their parameters differ from the ones extracted from DC measurements To get results consistent for the process not only for the actual measured device the extraction of RF relevant parameters must start with initial parameter start points to fit the S parameters at low frequencies Therefore using parameters extracted during the DC extraction process are used to give start points of good accuracy for the RF extraction process The path and filename of the selected start set will be shown on blue background Note You cannot change directly the path and filename of the start set in the field DC Parameter Set to use Instead use the Import DC CV Start Set button from the menu to enter the correct path or to browse for the location of your start set
384. he MOSFET behaves as if the effective channel length has been reduced by AL This phenomena is termed channel length modulation CLM CLM is not a special short channel phenomenon since the effect is present if a MOSFET is short or long However its relative importance increases and the effect on the saturated output conductance becomes distinctly more pronounced at shorter gate lengths The part of the Early voltage due to CLM is given by y a ae A bulk sat i V osteff V y ACLM PCLM Apu Esat ds dseff Channel Length Modulation CLM id s CE 3 d m rout s E 3 rout m c Drain Induced Barrier Lowering DIBL The depletion charges near source and drain are under the shared control of these contacts and the gate In a short channel device this shared charge will constitute a 134 MOSFET Models relatively large fraction of the total gate depletion charge and can be shown to give rise to an increasingly large shift in the threshold voltage V with decreasing channel length L Also the shared depletion charge near drain expands with increasing drain source bias resulting in an additional V dependent shift in V This effect is related to a drain voltage induced lowering of the injection barrier between the source and the channel and is termed the drain induced barrier lowering DIBL The following figure shows the band diagram at the semiconductor insulator interface of an 0 1 um n channel MOSFET simulat
385. he Plot Optimizer See the following figure 59 MOSFET Models Zoom this plot Activate Plot Set to Autoscale Display Error Area Tools Set X axis to Lin or Set Y axis to Lin or When you activate the Plot Optimizer the color of the PO button changes to blue At the same time a blue rectangle appears around the plot window Draw a rectangle around the area of the plot you d like to use for optimization by pressing and holding the left mouse button The rectangle appears in black color Use the right mouse button to access the menu choose Optimizer gt Global Region gt Add or simply press r on your keyboard The rectangle s color changes to blue and the optimizer area is ready Select the appropriate area inside the second plot the same way If the optimizer area in both plots appear with a blue rectangle the plot optimizer is ready for use Open the Plot Optimizer window by choosing Optimize gt Open Optimizer from the menu or simply press o on your keyboard The optimizer window opens Inside the Plot Optimizer select the parameters for use with this optimizing step In our example this would be VTHO Save the configuration by clicking Save in the Plot Optimizer region at the top of the Data Display window not the Optimizer window and enter a name for this configuration Now you can close the Data Display window and go to the Extract folder inside the BSIM4 PSP GUI Press Extract gt Extraction Flow gt Add choose
386. he RF Models mosfet RF Initialize The folder Initialize is used to set initial values during extraction for process and geometric parameters as well as model flags There are differences in initializing BSIM3 and BSIM4 PSP models The following figures show the initialization folders of each of the models BSIM3 Initialize Initialize folder for the BSIM3 model DC Parameter Set to use Type of Extracted Model C Single Transistor Model Scalable Transistor Model Initial Values Model Parameters Model Flags PART 05 High Frequency Model Flags ELM 2 NQSMOD o PEL commands executed at initialization BSIM4 PSP Initialize Initialize folder for the BSIM4 model nan BSIM4_RF_Extract 12 Fie Initialize Extract Plots HTML Options Boundaries Help joS BFF S Sele xe amp Sl Notes Information Inkiakze Extract Display HTML Options Boundaries Model Parameter Set Import DC C Start Set DC Parameter Set to use Type of Extracted Model C Single Transistor Model Hebe R eh Scalable Transistor Model Set to Greuit Defauts Model Fleas Model Parameter List High Frequency Model Flags Add Parameter RGATEMOD 2 Remove Parameter RBODYMOD t TRNQsMop fo gt acngsmop o Subsbrate Resistance Equation RSLBEQ fo y PEL commands executed at initialization Project Example_Scale Project drectory ji users defauk_2009 Status T
387. he device measured with the cbd2 cjdperimeter should have a low bottom area to perimeter area ratio Place the device to be measured into the test fixture Ensure that the CMs Capacitance Meters Units connected to the device correspond to the same CMs in Instrument to Device Connections mosfet for each of the next two measurements Calibrate the 379 MOSFET Models Capacitance meter before taking each measurement The extractions of the sidewall capacitance parameter sets use the measured data from both setups measure both setups before performing the extraction 1 In Macros select init_cap_parameters and Execute 2 Enter the drain area and perimeter information 3 Connect the low terminal of the capacitance meter CM low to drain and connect the high terminal CM high to bulk 4 Select cbd1 cjdarea and Measure to measure the first drain bulk junction capacitance 5 Repeat steps 3 and 4 for cbd2 cjdperimeter if both geometry sizes are being measured Perform the model parameter extractions 1 If a single geometry was measured select cbd1 cjdarea If two different geometries were measured select cbhd2 cjdperimeter 2 Choose Extract Optimization is usually not required for capacitance data Notes on Capacitance Parameter Extraction The drain to substrate and source to substrate junction capacitances are modeled as a combination of the sidewall and bottom area capacitances To extract the parameters for these ca
388. he device to simulate In addition inside a certain bin the parameter itself is interpolated so that we end up with the following diagram Calculation of binned model parameters device a not defined device b device c not J definea 10 L um 0 1 Bin Bin2 Advanced binning approaches 179 MOSFET Models As the diagram in the previous figure clearly shows the model is defined only inside the gate length of the characterized devices This is a critical condition because the following two scenarios are very common for MOS devices e It is very usual to use a transistor with for example L 10 um as the largest measured device and to extrapolate the parameter set to devices with larger gate lengths This is not a problem because the 10 um transistor already behaves like an ideal MOS transistor without short and narrow channel effects e For statistical simulations the gate length and widths are overlaid by a statistical variation to reflect variations in lithography If gate length or gate width are already at the boundary of the available model bins this would not work Both described effects would cause no problem using the normal BSIM3 or BSIM4 model without binning However having the restrictions of the binning implementation in the simulators the following two alternatives would help to overcome this bottleneck Extension of binning to include virtual devices The first idea is to add addi
389. he inversion region is caused by electron tunneling from the valence band It is calculated by TOXREF NIOX l I W L ne C 1 V gbinv eff eff TONE 2 g TOXE F_ gt exp D TOXE AIGBINV BIGBINV V__ _ aux oxdepiny 1 CIGB ACCINV V oxdepinv Inside this equation the auxiliary voltage is V xdepiny EIGBINY NIGBINV Y 1 gl Ji ex _OAQGEPINY j J t og exp EIGBINV v y aux The constants in the above equation are e C 3 75956E 7 A V2 e D 9 82222E11 g F s2 The voltage across the gate oxide Vox consists of the oxide voltage in accumulation and the one in inversion as used in Auxiliary Voltage Equation and Tunneling Current Equation Gate Oxide Equation V V V ox oxace oxdepinv The parts of Vox are calculated by 7 1 f 2 y 7 V7 oxacc Vyzb V ob 100 ji z E fe 5 y i y fbzb gb 10 100 fbzb K lp 7 P a lox Ns gsteff The flatband voltage calculated from zero bias Vth is 198 th V andV 0 bs ds K1 S S N MOSFET Models Gate Oxide Equation is continuously valid from accumulation through depletion to inversion Gate Tunneling Parameters Equation BSIM4 Description Default Variable Parameter Value TOXREF TOXREF Nominal gate oxide thickness for gate direct tunneling 3E 9 m model NTOX NTOX Exponent for the gate oxide ratio 1 0 AIGBACC AIGBACC Parameter
390. he name of the plot inside the Plots Single Transistor field on the folder Open plots for scalable transistor models by clicking the name of the desired plots inside the Plots Scalable Transistor field on this folder Note You can only choose a plot for the extracted model that was selected in the field Type of Extracted Model on the Initialize folder Plots inside the other fields are not selectable Each plot is opened in a new window Close all windows by using the Close All button on the right side of the Display folder or close single windows using the Close icon inside the appropriate window Related Topics RF Extract Notes mosfet RF Extract Information mosfet RF Initialize mosfet RF Extract mosfet RF Extract HTML mosfet RF Extract Options mosfet RF Extract Boundaries mosfet Back to Extraction of Parameters for the RF Models mosfet RF Extract Within this folder you define the extraction process for the parameters of the devices There is a standard extraction flow implemented but you can change this flow if you find another one suits your needs better than the default flow Extract Folder 110 my BSIM4_RF_Extract 12 Fie Intiaize Extract Plots HTML Options Boundaries Help JeClBSSiSSOexturnisle Notes Information Incite Extract Diplay Hm Options soundaries Project Example_Scale Project directory flusers default_20094 Ratus A e To extrac
391. he real part of the measured device impedance z m Example parasitics r_f Data _Sso ert Karae fparec tise f fim S11 Ohl RA Oe re 5 If you wish you can recompute the resistance values over the linear portion of the data only using the X low X high function as follows e Select Setup Variables A variable table will appear listing X_LOW and X_HIGH with their default values of O or current values e Choose a relatively linear portion of the plotted traces Click at the lower and upper boundary points of the linear portion to make a box on the trace as shown next Choosing a Relatively Linear Portion of the Traces 335 MOSFET Models 171 N IFAI UA ic t a s t P g P amp A r e From the plot menu select Options gt Copy to Variables This changes the X_LOW and X_HIGH values in the table to the boundary points you selected 6 Select Extract Optimize gt compute_r gt Execute The transform recalculates the parasitic resistance values as the average of the linear data you defined and modifies the Para data file accordingly The values for rs rd and rg are listed in the IC CAP Status window 7 The parasitic values can be modified after the main data acquisition just before the model generation 8 Close the plot Setting Up the Main Data Acquisition This sets up the values for the main measurement procedure which takes the data from which the model will be generated The proce
392. he second derivative Also make sure to change the Y Data 0 description to provide a unique name after the e Plot with the second derivative of the drain current versus gate voltage Measure Simulate Instrument Options Setup Variables Extract Optimize E d2id dw Display All XY GRAPP vg derivative vg smooth3 ic d2id_dvg Plot Finder Close All a LINEAR LINEAR LINEAR Change to the tab Extract Optimize and select the transform opt_UO_UA_UB_EU_UC Add your new plot to the existing plots by appending F_UsedPlot 2 Large idvg plotname where plotname is the name of the new plot defined in the previous step 74 MOSFET Models Increase the number of elements in the ICCAP ARRAY F_UsedPlot F_UsedPlot ICCAP_ARRAY 3 The modifications are marked red in the next figure for clarity Plots defined in transform opt_UO_UA_UB_EU_UC Measure Simulate Instrument Options Setup Variables Execute Select Transform Tune Fast extr_ TH_rough T extr_UO Tune Slow extr_YOFF_NFACTOR extr_V THO extr_K1_K2_NDEP extr_UA UB EU extr_UC extr_AIGBINY_BIGBIN extr_AIGBACC BIGBAC Functions VIEW extr_Ua_UB_UD_EU Rename opt _All_Idvg opt U0 UA UB_EU_U Store Par opt_YOFF_NFACTOR opt_VYTHO_K1_K2 Recall Par opt_AIGBINY_BIGBINY opt_AIGBACC_BIGBAC Undo Optim opt_All_Igate opt_UO_UA_UB_EU_L amp execute_UO UA UB_E execute_VOFF_N
393. he substrate to source drain bottom capacitance Cesb Cedb The contribution of these different components to the overall extrinsic capacitance is demonstrated below Different Components of the Extrinsic Capacitance Overlap Capacitance between Gate and Drain Source Sub strate 303 MOSFET Models 250 0 G p ie 2 LE i Yel s D sh m m a 7 B p i 150 8 E CES O A E F AS O 3 0 2 0 1 0 8 9 1 0 2 0 3 0 vg CE oJ Fringing Capacitance The fringing capacitance of a MOS transistor consists of a bias independent outer fringing capacitance and a bias dependent inner fringing capacitance In the present release of the BSIMSOI model only the bias independent outer fringing capacitance is implemented Experimentally it is virtually impossible to separate this capacitance with the overlap capacitance Nonetheless if the model parameter C is not given the outer fringing capacitance can be calculated Overlap Capacitance In BSIMSOI the overlap capacitance model from BSIM3v3 has been implemented See Overlap Capacitance mosfet for details Sidewall Source Drain Capacitance The parasitic source drain to substrate capacitance has the buried oxide layer for dielectric and is bias dependent For V 0 this MOS structure might be in accumulation and for V y V it is driven into depletion This results in a much smaller capacitance of the MOS structure because the Si substrate in
394. he variables FIV_VMIN FIV_VMAX update_iv_curves A transform that resimulates all the I V curves in the following setups area fwd_iv rev_iv locos fwd_iv rev_iv gate fwd_iv rev_iv analysis fwd_iv rev_iv ib A plot definition for the normalized area sub region contribution to current is A plot definition for the normalized locos sub region contribution to current ig A plot definition for the normalized gate sub region contribution to current rev_iv This setup controls the extraction of the I V parameters with respect to the reverse I V data Current in the reverse region is dominated by the generation effects and so only the generation parameters are considered during these extractions va vk These input definitions for the anode and cathode voltages are the same as those in the area rev_iv locos rev_iv and gate rev_iv setups ibn A transform that extracts and holds the normalized area sub region contribution to reverse current from the measurements in the area rev_iv locos rev_iv and gate rev_iv setups ibn_sim A transform that calls JUNCAP to evaluate the area sub region component of current fit_ibn An optimization definition that causes the parameter JSGBR to be optimized with respect to the normalized area sub region reverse current The 365 MOSFET Models parameter limits are controlled by the following model variables which you can change in the model variables table JSGBR_MIN JSGBR_MAX The data limits a
395. hen selecting LIN f Vth restrictions apply to the sweep options that are underlined in the table above To configure a LIN f Vth sweep select the idvd setup and choose LIN f Vth from the Vg pull down list of sweep types See the following figure Part of the Device List folder with sweep type Lin f Vth selected 21 MOSFET Models DC idvd VD VG VB Measure Id Measure Ig Measure Ib Linear v Lin f vth v Constant Start o Start Value 0 Veh Idref Wi L Offset Step 0 05 Setup idvg wv Stop 1 8 a Idref 100 0n No Pts 3 Offset 200 0m Res 1 000m Stop 1 800 No Pts 5 Compliance 100 0m Compliance 1 000m Compliance 100 0m Choose an appropriate vg type setup dvg in our example and set Idref offset resolution res stop value and the number of points No Pts The vg start voltage value will be calculated using this settings List f Vth A new type of sweep has been introduced List Vth The usage of this type of sweep is simular to the Lin f Vth sweep The start value of the gate voltage for the List f Vth sweep will be calculated like the Lin f Vth sweep The difference is you define a list with Start Value Number of Points and Step value to be used for this sweep If you would like to add measurement setups choose Configuration gt Add from the menu or use the appropriate icon from the top row of icons A window opens for you to select o
396. ho tmo_rdbo_rsubeqd tmp_rdb1 RSUBEQ 0 symmetric substrate contacts echo tmp_rsb_rsubeqOd tmp_rsbt echo tmp_rdb_rsubegqt tmp_rdb1 tmp_rdb2 tmp_rdb1i tmp_rdb2 RSUBEQ 1 horseshoe echo tmp_rsb_rsubeqt tmp_rsbi tmp_rsb2 tmp_rsbit tmp_rsb2 substrate contacts echo tmo_flag_rsubegO 1 1 abs RSUBEQ 1e9 flag to select substrate equations echo tmo_flag_rsubegqi 1 1 abs RSUBEQ 1 1e9 echo tmo_rbdb tmp_flag_rsubeq0 tmp_rdb_rsubeqd tmp_flag rsubeqi tmp_rdb_rsubeqt echo tmpo_rbsb tmp_flag_ rsubeq0 tmp_rsb_rsubeqd tmp_flag_ rsubeqi tmp_rsb_rsubeat 2 SSS Sais Gate network C Cgdext n20 n10 C CGDEXTO tmp_w C Cgsext n20 n30 C CGSEXTO tmp_w L Lgate i2 n20 L LGATEO tmp_w paanan Drain network lt lt s s s5ssss ssSesSsesce C Cdsext n10 n30 C CDSEXTO tmp_w L Ldrain i1 n10 L LDRAINO tmp_w a a Source N 6twork soseeseos es essences es senses L Lsource i3 n30 L LSOURCE0 tmp_w 217 MOSFET Models BS a ae ete Substrate network L Lbulk i4 n40 L LBULKO tmp_w bd nsn Cah fully sCatapte MOSFET Sas SSes A JAS Soar a a E S a a Soro aa echo bsim4_mos M1 n10 n20 n30 n40 echo Length tmpo_l 2 DLO tmp_d11 DL1 tmp_d12 DL2 echo Width tmp_w Nf tmo_nf Ad tmp_ad As tmp_as Pd tmpo_pd Ps tmp_ps echo Sa tmp_sa Sb tmp_sb Sd tmp_sd echo Rbpb 1e9 echo Rops 0 5 RSHB tmp_1 DGG tmp_w echo Ropd 0 5 RSHB
397. hoosing this folder They are designed to Add Delete Verify or Configure De embedding sets and are displayed in the following figure from left to right De embedding Pad Parasitics HEHA l0 x Fie Configuration Data Tools Help JOSE Bie PSSoxX SRBBE ee Notes Measurement CondRions De embedding Pad Structures outs Options De embadding Method _ erification of De embedding C No De embedding V Perform verification of De embedding using the Through device Cc Open Open Sheet User defined Pad Structures De eebeckting Sets Usad for De embedding on fokler DUTS Comment Open 1D Neme Pad Aea Set t tri Br tt r3 y St2 v2 ni eeanlewt Set 3 EEr T3 r68 Set 4 tdm ve v4 ni2 ve Project Example _Scale Project drectory j users defauk_2005 Status The section De embedding Method provides check boxes to select the method for de embedding to be used Check one of No De embedding Open Open Short or User 43 MOSFET Models defined Your selection of the de embedding method will affect the definition of de embedding sets described later in this paragraph There is a section Verification of De embedding where you can check a box to perform verification of de embedding using the through device if applicable The field Pad Structures is intended to declare dummy pads for de embedding purposes Click the
398. ibution of the intrinsic capacitance charges between drain and source side The exact formulations for the different operation regimes and charge partitioning schemes are in the UC Berkeley manual References 1 on pages 7 13 to 7 19 Fringing Capacitance Models The fringing capacitance consists of a bias independent outer fringing capacitance and an inner fringing capacitance bias dependent The outer fringing capacitance is modeled in BSIM4 if not given through 2 EPSROX CF h 2 T TOXE The inner capacitance is not modeled Overlap Capacitance Model For accurate simulation results especially the drain side overlap capacitance has to be modeled exactly because the influence of this capacitance is amplified by the gain of the transistor Miller effect Formerly used capacitance models assume a bias independent overlap capacitance However experimental data show a gate bias dependent overlap Capacitance which is invoked using CAPMOD 1 or 2 Using CAPMOD Q a simple bias independent model is invoked For CAPMOD O the overlap charges are expressed by Gate to source overlap charge W CGSO io Savard ap s T W active Gate to drain overlap charge Coverlap d W active CGDO Ved Gate to bulk overlap charge 209 MOSFET Models Lactive COBO Vo 2 overlap b active The parameters CGSO and CGDO are calculated if not given by CGSO and CGDO Parameters cGSO CGDO
399. ically be slightly negative to allow data to be taken slightly beyond the bounds of the model so that it is possible to properly extrapolate beyond the data e Max Vd should typically be slightly higher than any anticipated breakdown voltage e Min Vg should typically be one to several volts lower than Vthreshold for an NMOS device e Max Vg should typically be around the maximum gate operating voltage 8 For Min Step enter a value to define the step size between densely spaced measurements 9 For Max Step enter a value to define the measurement step size where you expect the data to be relatively linear and you do not need densely spaced measurements 10 For Vth enter the gate threshold voltage Vthreshold 11 Delta defines a voltage range below Vth where a high density of Vgs measurements is needed due to the nonlinear decrease in drain current at threshold 12 Eps Epsilon is used to predict the next point to be measured and thus control automatic data acquisition step size Increasing the value of epsilon decreases the sensitivity of the automatic data acquisition 13 For Noise thresh enter a current threshold value for both drain current and gate current below which you do not need closely spaced measurements The automatic step size algorithm is not used below the Noise thresh value where measured currents are sampled at the maximum step size 14 For SMU Compl enter the drain SMU maximum current compliance value in amps
400. icense and may be used or copied only in accordance with the terms of such license Restricted Rights Legend U S Government Restricted Rights Software and technical data rights granted to the federal government include only those rights customarily provided to end user customers Agilent provides this customary commercial license in Software and technical data pursuant to FAR 12 211 Technical Data and 12 212 Computer Software and for the Department of Defense DFARS 252 227 7015 Technical Data Commercial Items and DFARS 227 7202 3 Rights in Commercial Computer Software or Computer Software Documentation MOSFET Models Supported Model Versions scarce Sie dleote aos ecw a Os dia Gale Sie dd eaten ew Oe dit ee oes Using the MOS Modeling PackageS 0 cee Introduction to the MOS Modeling Packages 00 cece ee es Data Structure in MOS Modeling Packages cc ce es Getting Started with MOS Modeling 2 0 cc es DG and CV Meas rement p siia ti a ata a Guta Bite eras nee Adare de aa a te aai a ats Oe ce ae lee amp aides as Using DC and CV Measurement Module with WaferPro 00 cee es RF Measurement rmi a ee fa wh hg ae agit a ke u aye cas Re Gee nae kg Wig ae nea Oe se Ae ae tag a a A a a a E Sep Extraction of DC CV Parameters aaau dace ee ed Gh eee amp Se a Oey Wd ee OG Bae ee Modifying Existing Functions sasaaa ast o er a waa al Gerlach a Defining Extraction FUNCTIONS x Ain eaii eana a ake de
401. ick extraction KO_INIT Initial value for KO 0 8 K_INIT Initial value for K 0 2 VSBX_INIT Initial value for VSBX 1 5 GAMOO_INIT Initial value for GAMOO 0 01 MO_INIT Initial value for MO 0 5 ZET1_INIT Initial value for ZET1 1 VP_INIT Initial value for VP 1 5 ALP_INIT Initial value for ALP 0 01 THE3_INIT Initial value for THE3 0 GAM1_INIT Initial value for GAM1 0 01 The extract DUT The extract device contains all of the sequences used for the parameter optimizations and much of the setup information extract devices holds setup information that has the form of an array The input index is used to establish the size of the various arrays Its size in turn is controlled by the variable NUMDUT from the model variable table Note that the DUTs are labeled from 1 to the number of devices but the arrays holding the DUT information begin with index 0 The outputs for this setup are shown next width Holds the widths of the devices to be measured length Holds the lengths of the devices to be measured mult Holds the values for MULT for each device that is the number of similar structures connected in parallel drain Holds the matrix pin numbers connected to the drains if a switching matrix is being used gate The matrix pin numbers connected to the gates source The matrix pin numbers connected to the sources bulk The matrix pin numbers connected to the bulks dotemp An array that indicates if the devices are to be measured at temperature If
402. icon or Data gt Display Plots You will see a dialog box to select which measured data set you would like to display Choosing the plots you would like to see opens the selected plots This is a convenient way to detect measurement errors before starting the extraction routines If you are satisfied with the data you just measured use the Close Plots icon to close the windows that show diagrams of measured data Drain Source Bulk Diodes for DC Measurements For test structures to measure DC Drain Source to Bulk diodes see Drain Source Bulk Diodes for DC Measurements mosfet Other DC CV Measurement Module Folders Notes mosfet Temperature Setup mosfet Switch Matrix mosfet Options mosfet Options This folder lets you define options for the appearance of the plot windows Options folder 34 MOSFET Models loxi Fie Configuration Data Tools Help Ced Fra E e a pr J Ge o F P Z Pi JE i smu Notes Temperature Setup Switch Matrix Device Definition Options Description Variable Value Use X plot size FIX_PLOT_SIZE E Normalized reference current for YTH extraction ID_REF_ TH 100e 9 Project bsim3_for_expertroject direct j users default_ZB0Stus To change the plot window size deselect the FIX_PLOT_SIZE To change the background color of a plot window in the plot window select Options gt Exchange Black White This changes a white background to black or a bla
403. icon to perform the verification of a selected set Note Ideal de embedding means The S Parameters should behave like an ideal matched transmission line with Zo 50Q and a time delay Tp representing the electrical length of the TROUGH device measured S11 and S22 should be concentrated at the center of the Smith chart while S21 and S12 both start at 1 _ JO and turn clockwise on the unity circle If this is not true the following items should be checked e Is the calibration OK e If the OPEN method is used De embedding quality can be enhanced by switching to the OPEN SHORT method e For very high frequencies approximately above 30 GHz the assumptions for using the OPEN SHORT method might not be given You should probably change to an alternate calibration method The verification will be done and the plots will be displayed after clicking OK on the upcoming message window The following plots show what is to be expected for correct de embedding 44 MOSFET Models Plot BSIM4_RF_Measure Through s_pad Sx On Plot BSIM4_RF_Measure Through s_pad Sxy On S_deemb m 22 S deemb mi2 IMAG E 0 S_deemb m 11 1 0 0 5 6 8 B 5 1 6 S deembh m 21 REAL CE Q An error message will show up if one of the sets is not configured correctly After the de embedding is done you can assign the appropriate pad sets on the DUTs folder to their respective devices De embedding of Parasitic Structures The section T
404. id_svt generates target current values for subthreshold optimization The main purpose is to eliminate data that could lie on the noise floor It evaluates the transconductance on a log scale and eliminates points that have a transconductance of less than 70 of maximum on the low current side of the maximum point by setting their value to 0 5 IMIN copy_sim_to_meas copies the current generated by the MM9 transform into the measured array It is used for making sample measured data It uses the MM9_COPY C transform which is necessary to enable data to be copied into a measured array set_vth stores the threshold voltage in the setup variable VTH dutx ibvg allows the measurement of substrate avalanche current needed for the extraction of the substrate avalanche current parameters The ibvg setup contains the following transforms mm9_isub calls the MM9 transform to evaluate the avalanche current copy_sim_to_meas copies the current generated by the MM9 transform into the measured array It is used for making sample measured data It uses the MM9_COPY C transform which is necessary to enable data to be copied into a measured array Macros Macros control the overall extraction sequence SETUP Lets you provide setup information to describe the device type dimensions and matrix connections if appropriate the bias voltages used the nominal measurement 355 MOSFET Models temperature and the measurement temperatures for temperature coe
405. ide thickness Im 2E 9 1E 10 p TOXOVO lG Overlap oxide thickness Im 2E 9 1E 10 a i pe length for gate drain and In b i gate source overlap capacitance mov l E Effective doping of overlap region m 3 5E25 l1 1E20 l1 1E27 NOVO Geometry independent part of a 3 5E25 i i overlap region NOVD Effective doping of overlap region m 3 5E25 1E20 E27 drain side h NOVDO G Geometry independent part of ae 5E25 i i overlap region drain side DIBL Parameters OoOo COO EO eo l DIBL parameter vi o b E Length dependence of DIBL V 1 Fees i i CFLEXP Exponent for length dependence of CF erw G Width dependence of CF p p coe IL Back bias dependence of CF v 1 0 a cep fe Back bias dependence of CF vel 0 1 Moby Parameters wo e Zero field mobility at TR mz 5E 2 E FBET1 Relative mobility decrease due to first lateral profile FBET1W lG Width dependence of FBET1 g p p LP1 G Mobility related characteristic m 1E 8 1E 10 l length of first lateral profile LP1Ww lG Width dependence of LP1 E 0 f FBET2 G Relative mobility decrease due to 0 second lateral profile LP2 G Mobility related characteristic m 1E 8 1E 10 l length of second lateral profile BETN G Product of channel aspect ratio m2s V 7E 2 0 and zero field mobility at TR BETW1 G First higher order width scaling 0 coefficient of BETN BETW2 G Second higher order width 0 scaling coefficient of BETN WBET G Characteristic w
406. ids to id m saturation_extract calls the saturation region extraction functions quick_measure used by MM9_SAT_EXT to initiate saturation region measurements Its functionality is the same as that of quick_measure in lin_quick_ext quick_ext weav_quick_ext used during the extraction of the weak avalanche parameters It contains input definitions for the bias voltages vd vg vs and vb as well as the definitions for the current to be measured id and ib The weav_quick_ext setup contains the following inputs and outputs 352 MOSFET Models vd A constant value set by the variable VD vg A constant value set by the variable VG vs A constant value set by the variable VS vb A constant value set by the variable VB id The current output from the vd terminal ib The current output from the vb terminal The variables VD VG VS and VB are setup variables and are set automatically by the function MM9_WEAVAL_EXT The weav_quick_ext setup contains the following transforms mm9_ids calls the MM9 transform for current simulation copy_ids allows current to be copied from mm9_ids to id m mm9_ib calls the MM9 transform for ib simulation copy_ib allows current to be copied from mm9_ids to ib m weaval_extract calls the weak avalanche extraction functions quick_measure used by MM9_WEAVAL_EXT to initiate weak avalanche region measurements Its functionality is the same as that of quick_measure in lin_quick_ext quick_ext store contains miscellane
407. idth for width m 1E 9 1E 10 scaling of BETN STBET L Temperature dependence of 1 BETN STBETO G Geometry independent 1 temperature dependence of BETN STBETL lG Length dependence of STBET E 0 E p STBETW fe Width dependence of STBET E 0 E STBETLW lG Area dependence of STBET g 0 p MUE L Mobility reduction coefficient at m V 0 5 0 TR MUEO G Geometry independent mobility m V 0 5 reduction coefficient at TR MUEW lG Width dependence of MUE p ie STMUE IL Temperature dependence of MUE p o ls STMUEO lG Temperature dependence of MUE p THEMU IL Mobility reduction exponent at TR f 0 THEMUO lG Mobility reduction exponent at TR 1 5 0 f STTHEMU L Temperature dependence of 1 5 THEMU STTHEMUO G Temperature dependence of 1 5 THEMU CS L Coulomb scattering parameter at 0 0 TR Geometry independent Coulomb i i scattering parameter at TR ie Length dependence of CS k CSLEXP Exponent for length dependence of CS i es e Width dependence of CS j E ES E E E E 274 MOSFET Models ICSLW Area dependence of CS z ls STCS Temperature dependence of CS p p STCSO e Temperature dependence of CS g p f XCOR Lo Now universality parameter V 1 0 XCORO Geometry independent non v 1 i i universality parameter XCORL fe IL Length dependence of XCOR f XCORW lG Width dependence of XCOR 0 p XCORLW lG Area dependence of XCOR g
408. idth lowers the measurement noise floor by about 10 dB however the sweep time may be slower For more information on averaging and the different trace noise reduction techniques refer to the Agilent 8753 operating manual 12 Press CAL gt CAL KIT and select the appropriate default or user defined cal kit for your calibration devices 13 If you wish to modify an internal calibration kit definition do so now 14 Press CAL gt CALIBRATE MENU and perform the calibration of your choice at the analyzer front panel measuring each of the standard devices in turn and pressing the softkeys as each measurement is complete A full two port cal provides the greatest accuracy A TRL or LRM cal is an appropriate alternative for in fixture measurements Omit isolation cal Press DONE and save the cal in the register number specified in the instrument options table 15 Detailed procedures for measurements of calibration standards are provided in the Agilent 8753 operating manual Preverifying the Device S Parameter AC Data This procedure uses the s_vgvdf setup to measure the device S parameters across a calibrated frequency range with the drain bias voltage swept from OV to the upper limit of its normal operating range and several values of gate bias The procedure can be used as a quick check that the device performance is good at higher frequencies before you do a complete data acquisition and model generation It is not necessary to do th
409. ients and optimize_temperature_coefficients extract par_vs_L par_vs_W par_vs_R and par_vs_T are used to illustrate the geometry L W R and temperature T scaling The par_vs_L par_vs_W and par_vs_R setups store graphs of the miniset parameters A1 A2 A3 ALP GAM1 GAMOO K KO MO THE1 THE2 THE3 VP VSBT VSBX VTO ZET1 and BET vs 1 Leff 1 Weff or 1 Reff where Reff is a dimension number associated with transistors that do not lie on the standard length and width arrays The parameters in these 3 setups are initially created by the C transform MM9_GEOMSCAL which extracts the geometry scaling coefficients the maxiset model In any of these plots the variables with extension m e g V7O m represent the values of the miniset parameters as extracted for an individual device The variables with extension s e g V7O s represent the miniset value predicted by using the scaled model Because the scaled model can be optimized these values can be recalculated for the new scaling coefficients by a call to the C transform MM9_GEOMPAR The variables with suffix _ sg are used to hold the initial fits to the miniset parameters just after the least squares fitting in MM9_GEOMSCAL The par_vs_T setup shows the variation of the temperature sensitive parameters VTOR BETSQ THE1R SLTHE1R THE2R SLTHE2R THE3R SLTHE3R MOR and A R with temperature and their fitting with the temperature scaling rules In these plots the
410. impact ionization pre factor A1 ait G Length dependence of A1 aw lG Width dependence of Al A2 IL 1 Impact ionization exponent at TR Vv 0 A20 fe Ir Impact ionization exponent at TR Vv E STA2 L Temperature dependence of A2 Vv l a STA20 e Temperature dependence of A2 Vv p te dependence of fF h i eo G Geometry independent 1 saturation voltage dependence of II A3 lG IL Length dependence of A3 rer 3W lG Width dependence of A3 g p ba L Back bias dependence of II 0 Geometry independent back bias i i dependence of II ase G L Length dependence of A4 f p rem fe Width dependence of A4 Current Parameters ee tunnelling energy i 0 k adjustment GCOO G Ee tunneling energy i 0 i i adjustment IGINV IL Gate channel current pre factor A 0 0 IGINVLW G Gate channel current pre factor A 0 for a channel area of WEN x LEN IGOV IL Gate overlap current pre factor A 0 0 IGOVW G Gate overlap current pre factor A 0 for a channel width of WEN STIG L Temperature dependence of gate 2 current STIGO G Temperature dependence of gate 2 ia GC2 IL Gate current slope factor E 0 375 0 ho GC20 lG Gate current slope factor E 0 375 fa GC3 IL Gate current curvature factor E 0 063 2 a IGC30 lG Gate current curvature factor E 0 063 p o CHIB Tunnelling barrier height Vv 1 CHIBO G Tunnelling barrier height Vv l1 E Ga
411. in Gate Induced Drain Leakage model model AGIDL Pre exponential coefficient for GIDL T im BGIDL Exponential coefficient for GIDL l2 2 3e9 CGIDL Parameter for body bias effect on GIDL 0 5 EGIDL Fitting parameter for band bending for 0 8 V GIDL AGISL Pre exponential coefficient for GISL AGIDL mho e BGISL E Exponential coefficient for GISL BGIDL vim _ CGISL Parameter for body bias effect on GISL CGIDL EGISL Fitting parameter for band bending for EGIDL _ gprs Prona e pen penra T e oo Gate Dielectric Gate Dielectric Tunneling Current _ Current AIGBACC Parameter for Igb in accumulation e BIGBACC Parameter for Igb in accumulation 0 054 geac Parameter for 1gb In accumulation for Igb in accumulation oors 0 075 NIGBACC Parameter for Parameter for Igb in accumulation __ in accumulation parameter for Igb in inversion Bo 35 hese Jesvs BIGBINV Parameter for Igb in inversion p a 2 a Fs fg m V CIGBINV Parameter for Igb in inversion 0 006 EGBIN Parameter for Igb in inversion Hoo 1 NIGBINV Parameter for Igb in inversion NIFs g NIFs g CIGC p Parameter for Igcs and Igcd NMOS 0 075 PMOS 0 03 piss parame for Igs pes 0 43 PMOS 0 31 hese el piss promes for Igs jes 0 054 PMOS 0 024 lesve vs CIGS P Parameter for Igs NMOS 0 075 PMOS 0 03 fso parame for Igd pes 0 43 PMOS 0 31 sive g pice promes for Igd jes 0 054 PMOS 0 024 isis Li CIGD p Parameter for Igd NMOS 0
412. in squares of the multi finger device The width drain area of a single finger of the multifinger MOSFET will internally be calculated by Width tmp_w tmp_nf This hsim2 RF model finally uses the multiplier _M to account for _M tmp_nf number of gate fingers see the call of the MOSFET below define hsim2_RF_Extract i1 i2 i3 i4 3 parameters for sub circuit parameters tmp_l 1u tmp_w 10e 6 tmp_nf 1 tmp_ad 10e 12 tmp_as 10e 12 tmp_pd 22e 6 tmp_ps 22e 6 tmp_nrd 0 tmp_nrs 0 ngcon 1 hsim2 model card 3 5 5555 r rrr rrr rrr Parameters for the MOS device MOS 1 PMOS 0 IDSMOD 8 VERSION 3 3 BINUNIT 2 ACM 12 MOBMOD 1 CAPMOD 3 OIMOD 1 PARAMCHK 1 DELTA 0 01 TNOM 27 TOX 7 5e 9 TOXM 7 5e 9 NCH 1 7e17 XJ 1 5e 7 GATE 0 RSH 0 VTHO 0 7 K1 0 53 K2 0 013 K 3 0 K 3B 0 WO0 2 5e 6 LX 0 174e 6 DVT0 2 2 DVT1 0 53 DVT2 0 032 DVTOW 0 DVT1W 5 3e6 DVT 2W 0 032 ETAO 0 ETAB 0 DSUB 0 56 U0 670 UA 2 25e 9 UB 5 87e 19 UC 4 65e 11 VSAT 8e4 A0 1 AGS 0 B0 0 B1 0 KETA 0 047 A1 0 A2 1 RDSW 0 PRWB 0 PRWG 0 R 1 WINT 0 L 0 WLN 1 W 0 WWN 1 WL 0 DWG 0 DWB 0 LINT 0 0 LLN 1 LW 0 LWN 1 WL 0 VOFF 0 08 FACTOR 1 CIT 0 CDSC 2 4e 4 CDSCB 0 CDSCD 0 PCLM 1 3 PDIBLC1 0 39 PDIBLC2 0 0086 PDIBLCB 0 0 DROUT 0 56 PSCBE1 4 24e8 PSCBE2 1 0e 5 PVAG 0 VBM 3 ALPHAO 0 ALPHA1 0 BETAO 30 JS 1 0e 4 JSW 1e 12 NJ
413. ine measurements for Junctions Diodes of the devices to be measured First define the measurement conditions to reflect the desired voltages Number of Points and Compliances used for the measurement 32 MOSFET Models 45 BSIM4_DC_CV_Measure 8 File Configuration Data Tools Help a e a Er i nO er nHNeBas oee txtk isc Notes Temperature Setup Switch Matrix Device Definition Options Data af Transistor 3H Capacitance nmos PMos t Diode Compliance 4 E Device List Polarity vd vg vb vs o1 o 001 o1 jo Diode BD Diode BS VD Measure current at VS Measure current at Linear Bulk B Linear Bulk B O Drain D Source 5 Start 0 7 Start Step 005 Step Stop 2 Stop No Pts 55 No Pts 55 S Project bsim4_for_experts Project directory g users default Next select the Device List to enter names of DUTs geometries and switch matrix connections and to select temperatures at which to measure the DUTs Don t forget to Save your setup after you ve entered the DUT data Test Structures for Drain Source Bulk Diodes mosfet briefly describes usable test structures to characterize diode behavior Diode device list 45 BSIM4_DC_CY_Measure 8 Fie Configuration Data Tools Help 9 zu fs m ee HheBEPFS e tx BE Notes Temperature Setup Switch Matrix Device Definition Options Data ak Transistor l 3 Capa
414. ing mosfet e DC Extract mosfet e DC Options mosfet e DC Boundaries mosfet e Back to Extraction of DC and CV Parameters mosfet DC Information MOSFET Models Measurement Conditions for RF Test Devices Device Type NMOS Temperature 300K 2VG svn am an om jiwo ov 057 ovios 2 DC Transistor Output Sweep Stat Step Stop 0 25 V m ov Ng Transconductance is derived from output data The voltage settings are for n type MOS devices The polarity will be automatically changed with the TYPE Flag trl_n8_ w4 S Parameters S_deerD N 31 S amp S Ceerd 5 31 S_deerh N J2 3S deer S 32 PPG IE 7N Pin HI PF Mea P _ Geog te Tr naera mie Gdl wdey Si five vg S_deeeh N 22 S_ceerh 5 22 Pin BEI Cyr eon apin Tr aa ie Re Vasey Sire ive ae S_deerh N 21 S_deer S 2 IPRG ICom Pin BI PF vi rece mapie Tr anara i Gee ides Pi BI OF Cer reo Pf Greg la Te aaa are Ret Vasey Br Five vg The next folder to the right gives you Information about the devices measured see the following figure You ll find the type of MOSFET measurement temperatures DUT names together with their geometries and categories as well as the notes entered during the measurement If no measurement was performed on any of the DUTs there will be a notice stating the incomplete measurement status at the end of the line for that DUT 99 MOSFET Models It is not possibl
415. ing areas One of the major disadvantages of the binning approach is that the scalability feature of a model is not fully taken into account With the binning approach all binned parameters are interpolated using the same functions 1 L and 1 W Typically a scalable model behavior for example the threshold voltage is replaced by the binning approach The following example will make this more clear 181 MOSFET Models Vp VTHO Kn JO Vig K1 K3 K3B V E o W W0 DVTOW Leg Wey l cosh DVTIW The threshold voltage of BSIM4 is given above It is a complex equation that describes length and width related effects In a binned model parameters describing those effects DVTO DVT1 LPEO e t c are normally not used Instead the basic threshold voltage parameters VTHO K1 and K2 together with the binning extensions PVTHO LVTHO WVTHO WK2 are describing these effects If we have a Vth function like in the following figure it is clear that a proper selection of binning areas is necessary to cover this behavior Typical Vth behavior of a 0 18um CMOS process n type Vth Ff t Ldes Vke gt lew Va LEs Vth 0 9 ides CLOG J Vth scaling vs channel length Two different binning scenarios QO Binning scenario Binning scenario 2 Bin Bin2 The previous diagram clearly shows the difficulty in defining proper boundaries for the different binning areas While the binning scenar
416. ing the short wide device Local Length Dependence Wide PSP Scale Length Dependence Wide Local and Global Short Width Dependence Local Length Width Dependence PSP Scale Length Width Global Optimizations 240n 150n 90n 65n Wim 45n 60n 90n 150n 240n Wim 45n 60n 90n 150n 240n 45n 60n 90n 150n 240n MOSFET Models NEFF DPHIB XCOR ALP ALP1 ALP2 CF AX etc NEFF BETN DPHIB RS etc AXO AXL RSW1 RSW2 NSUB NSUBOW DPHIBO DPHIBL DPHIBW XCORO XCORL XCORW XCORLW etc 257 Local extraction using all devices with max W to extract length dependent parameters without width dependency Global extraction using the wide devices with different length Local and global extractions of the short devices steps 7 and 8 global extraction using all devices MOSFET Models Global optimize Optimizations Wim corner devices as well as length width and length width scaling 45n 60n 90n 150n 240n 5u L m e Back to PSP Characterization mosfet 258 MOSFET Models Parameter Extraction using Global Model only Using Parameter Extraction using Global Model only process the extraction of parameters for the PSP model follows the extraction flow of other MOS models without using the Local Global approach Example File You will find an example project where you are able to experiment with
417. interactively as described for the LEVEL 2 and LEVEL 3 MOSFET models There is no extraction routine in the short IdVd setup for saturation region parameters Instead the parameters KU MAL MBL and LAMBDA must be optimized For certain devices it may be necessary to alter the optimization setup and default parameter values for accurate results 384
418. io 1 covers the typical behavior of Vth the second scenario would miss the point of maximum Vth 182 MOSFET Models To verify the correct behavior additional devices between the binning boundaries are necessary especially in the critical areas with minimum gate lengths and widths as outlined below Devices for verification Wlum 10 Measured devices at binning boundaries 0 8 E Additional devices for 0 3 la b verification 0 18 0 5 10 Li um Back to BSIM3v3 Characterization mosfet 183 MOSFET Models Importing older version BSIM3v3 Files This section is intended for users wishing to import model files created with former versions of the BSIM3 Modeling Package the non graphic version into the new BSIM3 Modeling Package using the GUI If you have a model file created with a former non graphic version of the BSIM3 Modeling Package please proceed as described in the following example Open examples model_files mosfet BSIM3 BSIM3_DC_CV_Measure as well as the BSIM3v3 Model File mdl you wish to import For example if the BSIM3v3 mdl file is located in examples model_files mosfet bsim3v3 examples dc_modeling MASTER_MEAS_nmos mdl open that one The next step is to choose ImportBSIM3v3 in the header of the new GUI BSIM3_DC_CV_Measure mdl You will get a prompt as shown in the following figure m Select Model TNOM Data Import from Models bsim3_meas_nmos Create New Project
419. ion oe v na linear region p of operation Drain Saturation Voltage Vdsat The equation for the drain saturation voltage is divided into two cases the intrinsic case with Rgs 0 and the extrinsic case with Ry gt 0 l Esat Loff Vosteff 2V im y Abul sar efft Vosteff 2V rm e dsat E BERR b yb 4ac lt where 129 MOSFET Models 2 14 ee Spat a a aA bulk gt a b ostat Vt 5 1 r 7 oD id 4 bulk sat eff 345 u i as ox sat V esteff i tm 3 En E eat eff Vosteff 27 tm Rds ox Vat Vosteff 20 im The influence of the maximum carrier velocity VSAT on the drain current I and the conductance ggs is demonstrated in the following figure Influence of VSAT on Drain Current Tas id s CE 3 td lm 0 0 8 5 t 0 1 5 2 0 2 5 va cere Influence of VSAT on Conductance ggs gds s CE 3 gds m Bulk Charge Effect When the drain voltage is high combined with a long channel length the depletion depth of the channel is not uniform along the channel length This will cause the threshold voltage to vary along the channel length and is called bulk charge effect The following figure shows the depletion depth as a function of channel length For long channels this effect causes a reduction of the drain current Depletion Width along the Channel Length Sourc Drain Depletion layer boundary The bulk charge effect Apuk
420. ion contribution to forward current from the measurements in the area fwd_iv locos fwd_iv and gate fwd_iv setups ibn_sim A transform that calls JUNCAP to evaluate the area sub region component of current fit_ibn An optimization definition that causes the parameters JSDBR NB and JSGBR to be optimized with respect to the normalized area sub region forward current The parameter limits are controlled by the model variables which you can change in the model variables table JSDBR_MIN JSDBR_MAX NB_MIN NB_MAX JSGBR_MIN JSGBR_MAX The data limits are controlled by the following variables which are also in the model variables table FIV_VMIN FIV_VMAX isn A transform that extracts and holds the normalized locos sub region contribution to forward current from the measurements in the area fwd_iv locos fwd_iv and gate fwd_iv setups isn_sim A transform that calls JUNCAP to evaluate the locos sub region component of current fit_isn An optimization definition that causes the parameters JSDSR NS and JSGSR to be optimized with respect to the normalized locos sub region forward current The parameter limits are controlled by the following model variables 364 MOSFET Models which you can change in the model variables table JSDSR_MIN JSDSR_MAX NS_MIN NS_MAX JSGSR_MIN JSGSR_MAX The data limits are controlled by the following variables which are also in the model variables table FIV_VMIN FIV_VMAX ign A transform that extra
421. ion the extrinsic capacitance of a MOS transistor consists of the following three components e the outer fringing capacitance Cp between polysilicon gate and the source drain e the overlap capacitance Copo between the gate and the heavily doped source drain regions e the overlap capacitance CgpoL between the gate and the lightly doped source drain regions The contribution of these different components to the overall extrinsic capacitance is demonstrated in the following two figures 142 MOSFET Models Different Components of the Extrinsic Capacitance Overlap Capacitance Between Gate and Drain Source Bulk 250 0 re aN Lil Ld 2009 9 n o 5i a 150 98 D TE E 100 8 D z m D 59 8 3 0 a Fringing Capacitance The fringing capacitance of a MOS transistor consists of a bias independent outer fringing capacitance and a bias dependent inner fringing capacitance In the present release of the BSIM3v3 model only the bias independent outer fringing capacitance is implemented Experimentally it is virtually impossible to separate this capacitance with the overlap capacitance Nonetheless if the model parameter CF is not given the outer fringing capacitance can be calculated with the following equation 2E i j T CF S102 T Tox b Overlap Capacitance In BSIM3v3 an accurate model for the overlap capacitance is implemented In old Capacitance models this capacitance is assumed to be bias indepe
422. ion TOX im TSI Silicon film thickness 1E 7 Im TBOX Thickness of the buried oxide 3E 7 Im TOXREF Target oxide thickness 2 5E 9 Im xJ Source Drain junction depth TSi im NCH Channel doping concentration near interface 1 7E17 1 cm3 INSUB Substrate doping concentration 6E16 1 cm3 INGATE Poly gate doping concentration 0 1 cem3 RBODY Intinsic body contact sheet resistance 0 Q square RBSH Extrinsic body contact sheet resistance 0 Q square RSH Source drain sheet resistance 0 Q square RHALO Body halo sheet resistance 1E15 Q m RSW Zero bias lightly doped source resistance per unit width for RDSMOD 1 50 Q um i RSWMIN Lightly doped source resistance per unit width at high Vgs and zero Vbs 0 Q um for RDSMOD 1 WR RDW Zero bias lightly doped drain resistance per unit width for RDSMOD 1 50 Q um F RDWMIN Lightly doped source resistance per unit width at high Vgs and zero Vbs 0 Q um for RDSMOD 1 WR DVTPO First parameter for Vth shift due to p ocket 0 0 im DVTP1 Second parameter for Vth shift due to p ocket 0 0 VA 14 PDITS Coefficient for drain induced Vth shifts 1e 20 VA 14 PDITSL Length dependence of drain induced Vt h shifts 0 mA 14 PDITSD Vds dependence of drain induced Vth shifts 0 VA 14 PROUT Effect of pocket implant on rout degradation 0 0 v m0 5 MINV Vgsteff fitting parameter for moderate inversion 0 0 Temperature Modeling Parameters Table Temperature Modeling Parameters Param
423. is recommendation is the base for the default extraction flow programmed into the PSP Modeling Toolkit The following describes the sequence of parameter extraction used in the toolkit For every device the extraction of local parameters must be performed However not every local parameter for all devices must be extracted Some parameters are extracted for only one device Other parameters are extracted for a few devices and are fixed for other devices A number of parameters can be kept fixed at default values and only optimized in fine tuning steps during extraction Note that for all extractions the reference temperature TR must be set to the actual room temperature the devices are measured under Before extraction switch parameters SWIGATE SWIMPACT SWGIDL SWJUNCAP and TYPE are set to appropriate values and QMC is set to 1 to include quantum mechanical corrections Some parameters influencing the DC behavior of a MOSFET are extracted accurately only from CV measurements NP for example In order to get good DC parameter values you should start from the default parameter set and use a value of TOX as is known from technology With this settings extractions of VFB NEFF DPHIB NP and COX can be done using the measurement of CGG vs VGS of the long wide device The extraction process starts with local parameters for the Long Wide device followed by extraction of local parameters for the rest of the devices with max length The
424. is modeled in BSIM3 with the parameters AO AGS BO B1 and KETA as shown below 130 MOSFET Models 2 eo og K a a ae Se a oe eff l eff N J dep f f r 3 2 F bse s Laff z 1 AGS T gsti gt ES eff N J dep dj 1 1 Iir T lk 1 K ata The influence on the drain current is shown in the following figure Influence of AO and KETA on Ids at High Drain Voltages m LJ A LI vi l 6 oy ods E I E D ee Drain Current in the Subthreshold Region The drain current in the subthreshold region is modeled in BSIM3v3 by the effective voltage Vastett The model parameters VOFF and NFACTOR describe the subthreshold current for a large transistor while the parameters CDSC CDSCD and CDSCB are responsible for modeling the subthreshold behavior as a function of channel length All these parameters contribute to the factor n in the formula for Vosteft see Effective Voltage Vgs Vth Equation _ Cq Case Casca as Cased bse Cit n 1 Nactore Ont Cc ox Ox ox i r i a D eff D _ eff Fri 21 FI l 8 7 e 2e The influence of VOFF and NFACTOR on the drain current in the subthreshold region is shown in the following figure Influence of VOFF and NFACTOR on Drain Current in the Subthreshold Region 1d s CLOG le iaae aaa deleted I J r I I I r id vm 2 ok wearer trae vo CE e 3 Parasi
425. isplayed in the Circuit folder MOSFET Setup Attributes lists setup attributes Summary of UCB MOSFET Controlling Model Parameters Type LEVEL 1 LEVEL 2t LEVEL 3 Classical VTO GAMMA PHI KP IS NSUB UO UCRIT UEXP UTRA NSUB UO THETA JS TOX NFS NSS TPG NFS NSS TPG Short channel LD XJ LD XJ Narrow width DELTA wD t Saturation LAMBDA NEFF VMAX ETA KAPPA External resistance NRD T NRS RD RS Junction capacitance AD AS T CBD CBS CJ FC MJ PB Sidewall capacitance Pp t pst CSJW MISW Overlap capacitance CGBO CGDO CGSO General LEVEL L t wit IC CAP Temperature TNOM system variable Specification TLEVEL 2 and LEVEL 3 also include LEVEL 1 parameters tTIndicates device parameters model and device parameters are listed together TtTWD does not exist in the SPICE UCB version it has been added to some SPICE versions and is included in IC CAP If WD is not in your simulator ignore the result set to zero or subtract 2 WD from the channel width In the MOS model files provided with IC CAP the width specification W in each of the DUTs has been modified to subtract the value of 2 WD from the drawn width WD is specified in Model Variables UCB MOSFET Parameters Name _ Description Default Capacitance CGBO Gate to Bulk Overlap Capacitance Capacitance due to design rules that require the gate 0 F m be extended beyond the channel by some amount Not voltage dependent Total Cgb Capacitance equals Cgbo ti
426. istance model selector 0 No body resistance 1 Two resistor body model RDSMOD 0 Bias dependent source drain resistance model selector IGMOD 0 Gate current model selector 0 1 IGBMOD 0 Gate Body tunneling current model selector 0 1 IGCMOD 0 Gate Channel tunneling current model selector 0 1 BINUNIT 0 Bin unit selector 0 Units for Log and Wor in the binnig equation are in meters 1 Units for Log and Wo in the binnig equation are in microns Main Model Parameters Table Main Model Parameters Parameter Description Default Unit Value 314 ners Models 2 1 Threshold Voltage VTHO Threshold voltage Vbs 0 for long and wide device Vv VOFF Offset voltage in subthreshold region for large L and W 0 08 Vv K1 First order body effect coefficient 0 6 0 5 K1W1 F First body effect width dependent parameter Im K1W2 ls Second order body effect width dependent parameter m K2 Second order body effect coefficient K3 Narrow width coefficient K3 Body effect coefficient of K3 1 V KB1 Backgate body charge coefficient Iwo Narrow width parameter Im L LPEO IL Lateral non uniform doping parameter called NLX in BSIMSOI3 1 74E 7 Im DVTO F First coefficient of short channel effect on VTH D DVT1 Second coefficient of short channel effect on VTH DVT Body bias coefficient of short channel effect on VTH 0 032 l1 v vron First coefficient of narrow channel effect on VTH DVT1W Second coefficient of narrow channel effect on VTH 5 3E6
427. ith the BSIM4 Modeling Package and similar upcoming modeling products In addition a detailed description of all files of the Modeling Packages is included This is an update to the already existing BSIM3v3 Modeling Package in IC CAP The complete user interface and data structure was modified and reworked to have the same style as the existing BSIM4 Modeling Package One of the main advantages of this concept is the usage of measured data by the BSIM3 Modeling Package as well as the BSIM4 Modeling Package for parameter extraction Please note for compatibility reasons the old BSIM3v3 files can still be accessed in the ICCAP_ROOT examples model_files mosfet bsim3v3 directory The new style files are located in the directory SICCAP_ROOT examples model_files mosfet bsim3 Don t get confused by the missing version information of the bsim3 term The new style files don t use the version information any more e BSIM3_DC_CV_Measure A feature Import BSIM3v3 was added to reuse data in the file format of the former BSIM3v3 Modeling Package The measured data of the new BSIM3 Modeling Package is now in a format that can be used for the generation of BSIM3 and BSIM4 models e BSIM3_DC_CV_Extract The existing extraction functions have been ported to the new style user interface A new more user friendly HTML report can be generated which allows a comparison of measured and simulated data for each device In addition the report can be easily include
428. itial Values T NEFF BETN MUE RS 0 NEFF BETN MUE RS T NEFF BETN MUE RS THEMU l 0 NEFF BETN MUE RS THEMU I T NEFF BETN MUE RS RSG RSE O NEFF BETN MUE RS RSG ASI T NEFF DPHIB CT 0 NEFF OPHIB CT T XCOR CS BETN MUE RS E Configuration of Initial Conditions a R i aan ae re a Device Ful Paramotor Set Single Parameters C N WSO LSO SARS Defaut pa NW5u0_LESA0_ SAOS fN wou L5u0 SAMS v C MWSOLIOOSAOS N WSLS SAS Y C MWO LESNO SANS fn weud LESO SANS v C NWON LINO SANS fN W200n0 LES SAOS v C N AOMNO LSA SADS fN W200n0 L900 SAOS v Configuration of Initial Conditions for devices to be binned Inside the Configuration of Initial Conditions window you can select the Full Parameter Set appropriate for this device by using the pull down menu to the right of each device There is a tailored function flow adopted to the requirements of _Binning as shown in the following three screenshots The first one shows the Function Flow for the Long Wide device the second one for the Short Wide device Special functions for these devices are marked with a comment in brackets behind the parameter name showing for which device this function is used Long Wide device Extraction Intermediate Results IP Binning Function Flow JN Ww5u0_L6u0 _SA10u0 bin N_W5u0_L5u0_SA1C binN_W5u0_L65n0_SA1 bin N_W90n0_L65n0_SA bin N_WSOn0_L90n0_S4 binN_W5u0_L90n0_S
429. ity accurately is critical to precise modeling of MOS transistors BSIM4 provides three different mobility models selectable through the MOBMOD flag The MOBMOD 0 and 1 models are the same as being used in BSIM3v3 There is a new and accurate universal mobility model selectable through MOBMOD 2 which is also suitable for predictive modeling BSIM4 References mosfet 1 With BSIM4 5 0 an L dependency was added to the formulas for the effective mobility using the newly introduced parameters Up and Up see parameter list for details MOBMOD 0 L pa oo eff vo 1 UP exp i B P LP ef a 4 2V 4 27 2 i V TOXE y gt f f th gt gsteff th airy th 1 U4 UC V stef _th yp _esteff __ thy typ bseff U TOXE TOXE a y Fay gsteff th MOBMOD 1 L en U0 1 UP expl efi Ll SIP Hoff E i 27 V 27 2 V TOXE l ga 84E _ th yg _gsteff thy ayey a UD K toxe UB TOXE 1 UC Vise UD Fay gsteff th MOBMOD 2 201 MOSFET Models rE ay U0 1 UP exp j Hoff E PEET V staf Co VTHO VFB P EU V ih TOXE Y 1 UA UC Ve seff TOXE UD 7 ioy gsteff th The constant CO has different values for different MOS processes For NMOS processes CO 2 for PMOS processes CO 2 5 is used Using UD 0 0 and UP 0 0 the model is backwards compatible Mobility Model Parameters quation B
430. ity factor at reversed bias for 10 0 Source NRECROD Recombination non ideality factor at reversed bias for default to source Drain value NTRECF Temperature coefficient for NRECF 0 NTRECR Temperature coefficient for NRECR 0 ISBIT BJT injection saturation current source side 1E 6 A m IDBJT BJT injection saturation current drain side 1E 6 A m ISDIF Body to source injection saturation current 0 A m2 IDDIF Body to drain injection saturation current 0 A m2 ISREC Recombination in depletion saturation current source 1E 5 A m2 side IDREC Recombination in depletion saturation current drain 1E 5 A m2 side ISTUN Reverse tunneling saturation current source side 0 A m2 IDTUN Reverse tunneling saturation current drain side 0 A m2 LN Electron hole diffusion length 2E 6 m VRECO Voltage dependent parameter for recombination 0 V current source side VRECOD Voltage dependent parameter for recombination defaults to source V current drain side value VTUNO Voltage dependent parameter for tunneling current 0 V source side VTUNOD Voltage dependent parameter for tunneling current defaults to source V drain side value NBJT Power coefficient of channel length dependency for 1 bipolar current LBJTO Reference channel length for bipolar current 0 2E 6 m VABJT Early voltage for bipolar current 10 0 V AELY Channel length dependency of Early voltage for 0 V m bipolar current AHLI High level injection parameter for bipolar current 0 source side AHLID High level
431. ixed devices binning feature Back to BSIMSOI4 Characterization mosfet 301 MOSFET Models CV Characterization BSIMSOI model includes the following features A separate effective channel length and width equation for the CV model other than for the IV model A single equation is used for each nodal charge to cover all regions of operation The inversion and body capacitance are continuous at threshold voltage Threshold voltage formulation is consistent with the IV mode Body effect and DIBL are incorporated into the capacitance model There are two options for the intrinsic capacitance model taken from BSIM3v3 capmod O or 1 options are not supported in BSIMSOI4 o Capmod 2 based on BSIM3v3 1 short channel capacitance model The drain voltage induced channel depletion charge Q is modified due to dynamic depletion For silicon films much thicker than the depletion width the original BSIM3v3 1 formulation is retained o Capmod s3 A new option for better prediction of capacitive coupling The same charge formula is used as in capmod 2 but Q is derived from channel potential This approach results in better precision at high positive biased Vps Gate overlap capacitance one part is bias independent and counts for the effective overlap capacitance Codo between gate and source drain the other part is the gate bias dependent capacitance Cgdol between gate and LDD region Fringing capacitance Cp between gate and source a
432. jects for extraction or for 50 MOSFET Models generation of HTML reports The tasks to be performed are ordered using different folders from the left to the right side of the BSIM3 4_extract window They should be performed in this manner Some of the folders have default values for your convenience If you are satisfied with the defaults those folders could be left as they are However you are not required to follow this order DC CV Extraction Module Folders DC Notes mosfet DC Information mosfet DC Initialize mosfet DC Binning mosfet DC Extract mosfet DC HTML mosfet DC Options mosfet DC Boundaries mosfet See Also Data Structure used for the MOS Modeling Packages Getting Started with MOS Modeling mosfet DC and CV Measurement mosfet RF Measurement mosfet Extraction of Parameters for the RF Models mosfet Using the MOS Modeling Packages mosfet DC Boundaries The folder Boundaries is intended to set optimizer boundaries for some parameters Since the parameters differ between BSIM3 and BSIM4 PSP there are little differences in the look of the boundaries folders Boundaries Boundary settings for the BSIM Modeling Packages san BSIM4_DC_C _Extract 7 Fie Initialize Binning Extract Plots HTML Options Boundaries Help jepu oP a J E ES amp l ig td G a 4 A Notes Information Initialize Binning Extract HTML Options Boundaries
433. k Diodes The following figure shows a pn junction diode between the bulk and the drain of an n type MOS Transistor pn junction diode The drain bulk and the source bulk pn junctions can be used as diodes in CMOS designs BSIM3v3 offers a simple DC model for the current I or Ibd flowing through these diodes hs INV pi gee Sa sbs MIN bs ths IJTH 1 ITH yV V G NV bs ism Sun bs tm where NJ is the emission coefficient of the source junction and the saturation current I is calculated as Isbs AsJs Ps where Js is the saturation current density of the source bulk diode As is the area of the source junction Jocyw is the sidewall saturation current density of the source bulk diode and Pz is the perimeter of the source junction J and Jocgy are functions of the temperature and can be described as E E tm0 tm nom NJ Jg Joge Fimo Vim Inom NJ Jssw Ysosw where 4 2 E 1 16 202X10 Tnom go i Tnom 1108 49 P L ee g g T 1108 Jcg is the saturation current density default is 1074 A m Jsosw is the sidewall saturation current density default is 0 NV m NJ K T q Vism NVem In ijth I i 1 sbs The current Ips through the diode is shown in the following figure Current Ibs Through Diode 137 MOSFET Models Current Ibs Through Diode ib s CLOG th im Consistency Check of DC measurement data
434. k analyzer two separate calibrations must be performed Frequency list calibration procedures for an Agilent 8510 based system and an Agilent 8753 based system are provided in the next few pages A CW calibration subset procedure for an Agilent 8510 based system is also provided Calibration for an Agilent 8753 Based System Although the Agilent 8753 has frequency list capability IC CAP does not support the subset calibration technique used in an Agilent 8510 system Therefore it is necessary to perform two separate calibrations for an Agilent 8753 or 8720 based system one frequency list calibration and one CW calibration A separate set of standards measurements must be made for each calibration Frequency List Mode Frequency list lets you define an arbitrary list of frequencies in one or more segments During the measurement sweep the synthesizer is phase locked at each frequency point as in the stepped sweep mode The advantage of frequency list mode for use in a table based model such as this is that it lets you define a smaller number of measurement points than for a step or ramp frequency cal This reduces the total measurement time A of Points of 11 provides adequate measurement resolution as well as a quite fast total measurement time For the purpose of this model you will define two frequency segments in the list a swept 329 MOSFET Models broadband segment and a CW segment Set the broadband frequency list segment ran
435. kages Data Structure used for the MOS Modeling Packages Getting Started with MOS Modeling mosfet DC and CV Measurement mosfet RF Measurement mosfet Extraction of DC and CV Parameters mosfet Extraction of Parameters for the RF Models mosfet MOSFET Models Data Structure in MOS Modeling Packages The MOS Modeling Packages use a different and more advanced data storing concept as compared to former modeling products in IC CAP The drawback of recent modeling products is that measured data is always stored in model files with transforms macros plot definitions and so on DC CV Measurement Module e Different DUT Setup templates e Measurement control code e Test and measurement setup GUI mdm Files Project Large idvg 300K mdm e Measured curves e Device information e Organized in projects Project L10_W20 idvg 400K mdm Project cjurc_c_area 300K mdm DC CV Extraction Module e Extraction routines e Data import export e Documentation features etc This method had two major disadvantages e The additional information is stored n times and is therefore highly redundant e The combination of data and code makes it very difficult to introduce updates to the code Now the new architecture of the MOS Modeling Packages overcome these disadvantages The measurement module contains all measurement related items like DUTs Setups to perform measurements and setup of test and measurement conditions Th
436. ked directly to the IC CAP executable The suitability and accuracy for DC AC and statistical applications have been demonstrated by Philips in several publications see References mosfet 1 2 and 3 MOS Model 9 Model MOS Model 9 uses two IC CAP models mm9 and mm9_tempx Both of these models are stored in the file mm9 md When saving in the Main window ensure both model definitions are kept e mm9 is the main model definition file and contains the templates for measurements and extraction e mm9_tempx is the template file for data that will be measured at non nominal temperature The most important aspect of this file is that the MM9 parameter values are set to the values in the model MM9 The primary method of model evaluation relies on the function MM9 which appears in the Function Group MM9 This function requires the inputs VD VG VS and VB which are arrays that give the drain gate source and bulk voltages respectively It also requires the parameter Output which controls the current returned by the function and is defined by one of the following options e D to return drain current e S to return source current e B to return bulk avalanche current The calculations performed by this function are also influenced by two variables MODLEVEL and EQNTYPE These quantities and their influence are shown in MM9 Variables mosfet The following figure illustrates the overall structure of the model Overall Structu
437. keley June 1998 BSIMSOI4 0 University of California at Berkeley November 2005 J Gautier J Y C Sun On the transient operation of partially depleted SOI NMOSFET s IEEE Electron device letters vol 16 no 11 pp 497 499 Nov 1995 D Sinitsky R Tu C Liang M Chan J Bokor and C Hu AC output conductance of SOI MOSFET s and impact on analog applications IEEE Electron device letters vol 18 no 2 pp 36 38 Feb 1997 7 BSIMSOI v2 1 p 5 5 University of California at Berkeley 1999 8 Characterisation System for Submicron CMOS Technologies JESSI Reports AC41 94 1 through 94 6 oS gt 289 MOSFET Models Introduction to BSIMSOI Model The BSIMSOI model BSIMSOI Berkeley Short channel Insulated gate field effect transistor Model for Silicon On Insulator devices was published in the first version by the University of California at Berkeley in 1997 The current version of the model is BSIMSOI4 4 0 released by the University of California at Berkeley in December 2010 This Modeling Package is based on version BSIMSOI4 4 BSIMSOI is a public model and intends to simulate analog and digital circuits that consist of deep sub micron MOS devices manufactured in Silicon on Insulator technology It is based on the well known BSIM3 model for bulk MOSFET devices It is a physical model intended for the simulation of both Partially Depleted PD and Fully Depleted FD devices with built in dependencies of important device di
438. l and power dissipation The threshold voltage then depends on geometrical parameters like the effective channel length and the shape of the source bulk and drain bulk junctions These device dimensions have a strong influence on the surface potential along the channel A shallow junction with a weak lateral spread is desirable for the control of short channel effects while the source and drain resistance must be kept as low as possible However a trade off between the search for very shallow junctions and the degradation of the maximum achievable current through the parasitic resistance of low doped drain regions must be found Those effects can be shown in device simulators where drift diffusion and additionally the hot electron behavior can be simulated The following equations are responsible for the modeling of the short channel effect part AV 3 in the BSIM3 model L L eff eff na Pvt AV in 3 Pyro ad a a ie g _ St OX dep s i ioa Ql Dyr Vb soff Pe o V P x Si S se e N p N IN oh where Voi built in voltage of the PN junction between the source drain and the substrate a a Nohal gt h Ot q pa E E i Ng source drain doping concentration or in the LDD regions if they exist DVTO DVT1 DVT2 are parameters used to make the model fit different technologies Influence of Short Channel Effects on the Threshold Voltage 124 MOSFET Models Soe m U 720 0 uT 620 28 J mM ee
439. l noise coefficient First coefficient of flicker noise First coefficient of flicker noise for a channel area of WEN x LEN Second coefficient of flicker noise Second coefficient of flicker noise for a channel area of WEN x LEN Third coefficient of flicker noise Third coefficient of flicker noise for a channel area of WEN x LEN Temperature offset with respect to ambient circuit temperature Reference temperature Maximum current up to which forward current behaves exponentially Zero bias capacitance per area unit of bottom component Zero bias capacitance per length unit of STI edge component Zero bias capacitance per length unit of gate edge component Built in voltage at the reference temperature of bottom component Built in voltage at the reference temperature of STI edge component Built in voltage at the reference temperature of gate edge component Grading coefficient of bottom component Grading coefficient of STI edge component Grading coefficient of gate edge component Zero temperature bandgap voltage of bottom component Zero temperature bandgap voltage of STI edge component Zero temperature bandgap voltage of gate edge component Saturation current density at the reference temperature of bottom component Saturation current density at the reference temperature of STI edge component Saturation current density at the reference temperature of gate edge component Shockley Read
440. l source and measuring instruments and workstation are physically and logically configured for the IC CAP system Load the model Select the DUT In the DUT Parameters folder enter the W and L device parameters for the selected DUT In the Macros folder select the appropriate macro to enter the process parameters Select the setup Issue the Measure command Issue the Extract command Issue the Simulate command Display the results Fine tune the extracted parameters if needed by optimizing Pe HOLPNDYN 1 1 DC Measurement and Extraction In DC parameter extraction the extracted parameters are directly related to the geometries of the devices being tested For a DUT to accurately extract DC model parameters it must have the correct L drawn or mask channel length and W drawn or mask channel width device parameters Before executing an extraction or simulation edit each DUT to ensure the L and W parameters are correct Before starting the extraction enter several process parameters The most important of these is TOX Determine TOX by reading the process information for the device or by measuring the oxide capacitance TOX is measured in meters Enter its value directly in Model Parameters or run the nit_parameters macro Also use the nit_parameters macro to enter initial values for XJ LD and RS These initial values can contribute to the accuracy of the extracted parameters They are overwritten by new values when the
441. lained later BSIM3 uses the following equation to model the DIBL effect in the threshold voltage L E eff a eff Sub nj sub i AV n 6 20 E ta0 Etab bef Vas _ ae g I _si_ox_dep t0 N sio2 125 MOSFET Models Carrier Mobility Reduction BSIM3v3 provides 3 different equations for the modeling of the mobility reduction They can be selected by the flag MOBMOD MOBMOD 1 lo Haff 7 7 I y 7 y Va LUV Vy l U U Vosa U gst Tih Ton aT psta Th ae MOBMOD 2 u Hoff 1 nf u V sof l V estaff i 2 S U Festat ae MOBMOD s3 Ho Hag 7 1l ua Vosteff 2 th Wi Uzi Vestf Vh Tod A U Vy seg The influence of the mobility reduction parameters is demonstrated in the following figure where the simulated drain current with and without mobility reduction is shown Influence of Mobility Reduction Ideal curve I d f V g without mobility reduction P W UA UB UC 0 k Influenceof UA UB and UC on 7 the curve I d f Vg The following figure shows the effective mobility as a function of gate voltage and bulk source voltage Effective Mobility peff as a Function of Gate and Bulk Source Voltage veff fivg diff bulk voltages CE Ss wefF ueff Effective Channel Length and Width Effective Channel Length Influence of Channel Length Reduction on the Drain Current 126 MOSFET Models The effective channel length is defined in BSIM3 as fol
442. lated from the shift in threshold voltage the difference of VTH and VTO Short Channel Parameter Extractions This extraction calculates the short channel parameters LD and XJ from the Id versus Vg measurement The setup and extraction are similar to the classical and narrow width The effective Gamma or effective NSUB and Beta effective mobility are calculated using least squares fitting The parameter LD is calculated from Beta and UO The parameter XJ is calculated from the change in Gamma or NSUB The parameter XJ is the only parameter that controls the effect of channel length on the shift of threshold voltage due to bulk bias This parameter is extracted by IC CAP to fit the threshold shift and therefore its extracted value may not correspond to the metallurgical junction depth In other words XJ is an empirical not a physical parameter in this model Saturation Parameter Extractions This extraction calculates the saturation parameters VMAX and NEFF from the Id versus Vd measurement The measurement can be taken at a single gate voltage or at various gate voltages Only the highest gate voltage curve is used in the extraction Ensure the drain voltage sweep is sufficient to cover both the linear and saturation regions In this extraction first the knee point or the saturation point is found from the shape of the curve for the maximum gate voltage VMAX is calculated from the saturation point NEFF is then calculated to fit the s
443. lder one or more columns marked with the temperatures you have entered appear The fields of those columns show either 0 for no measured data available M for DUT already measured or for DUT not to be measured at that temperature e To select devices to be measured at different temperatures Choose Temperature Measurement from the icons or from the Configuration menu You will be prompted with a list of DUTs Select the devices to be measured at those temperatures entered in the Temperature Setup folder and click OK You can select more than one DUT at a time for temperature measurement by repeated clicks on each one you want to choose Note You cannot prevent a DUT from being measured at TNOM All DUTs are measured at that temperature If you have entered one or more temperatures T1 and T2 for example on the Temperature Setup folder the DUTs selected for temperature measurement are all measured at those temperatures In other words you cannot select a DUT for measurement at temperature T1 but not at temperature T2 Note To extract temperature effects on parameters a large a short and a small device is necessary You can enter a comment for each DUT If you are using a switch matrix you can enter a module name and the pin numbers of the switch matrix pin connections to the transistor in the fields below the node names those fields are present only if the use of a switch matrix is selected on the Switch Matrix folder See
444. le external capacitors and inductors to account for cross coupling in the metal stripes and additional delay due to large sizes a scalable substrate network a scalable channel length reduction x echo CGDEXT0 mpar CGDEXT0O 1e 9 external capacitance gate drain per gate width and gate finger F m echo CGSEXT0 mpar CGSEXT0 1e 9 external capacitance gate source per gate width and gate finger F m echo CDSEXT0 mpar CDSEXT0O 1e 9 external capacitance drain source per gate width and gate finger F m echo LDRAINO mpar LDRAINO 1e 6 drain inductance per gate width and gate finger H m echo LGATEO mpar LGATEO 1e 6 gate inductance per gate width and gate finger H m echo LSOURCEO mpar LSOURCEO 1e 6 source inductance per gate width and gate finger H m echo DGG mpar DGG 2e 6 distance gate to gate m echo DLO mpar DLO 0 basic channel length reduction correction m echo DL1 mpar DL1 0 channel length reduction correction 1 and 2 outer fingers m echo DL2 mpar DL2 0 channel length reduction correction outer fingers m x Gate network echo LGATE 2 20 dpar CALC LGATE 0 1p echo CGDEXT 20 10 dpar CALC CGDEXT 0 1f echo CGSEXT 20 30 dpar CALC CGSEXT 0 1f x Drain network echo LDRAIN 1 10 dpar CALC LDRAIN 0 1p echo CDSEXT 10 30 dpar CALC CDSEXT 0 1f Xx Source network echo LSOURCE 3 30 dpar CALC LSOURCE 0 1p call single MOS
445. le stress effect model for process induced stress effect device performance becoming thus a function of the active area geometry and the location of the device in the active area Asymmetric current capacitance model S D diode and asymmetric S D resistance Improved GIDL model with BSIM4 GIDL compatibility Noise model Improvements e Improved width length dependence on flicker noise e SPICE2 thermal noise model is introduced as TNOIMOD 2 with parameter NTNOI that adjusts the magnitude of the noise density e Thermal noise induced by the body resistance network as well as the Body contact resistance e Shot noises induced by Ibs and Ibd separated 5 A two resistor body resistance network introduced for RF simulation 6 Threshold voltage model enhancement e Long channel DIBL effect model added e Channel length dependence of body effect improved 7 Drain induced threshold shift DITS model introduced in output conductance 8 Improved model accuracy in moderate inversion region with BSIM4 compatible Vgsteff 9 Multi finger device with instance parameter NF 10 Gate current improvement for body contact 11 Threshold voltage variations are included oN For a detailed description of these features refer to the BSIMSOI manual of The University of California at Berkeley http www device eecs berkeley edu bsimsoi archive bsimsoi4p0 BSIMSOI Model Basics The following sections describe some SOI effects with some basic description of the BSIMSOI4 mod
446. lect PSP Scale Parameters from the Main Groups and select Global Local from the Extraction Groups Devices field The following figures explain this step by step m Extraction Flow PSP Scale Parameters 263 MOSFET Models MB Add Extraction Main Groups C Global r Cc gt 9 PSP Scale Parameters Extraction Groups Devices PSP Scale Short Dependence Width Dependence PSP Scale Long Width Dependece PSP Scale Length Width PSP Scale Length Dependence Wide Global Local Select the Global Local step just added and start extraction using Interactive Extraction or Step by Step Extraction the Multiplot window opens with a basic setting This may take a while since the specified simulator will be opened in the background performing simulations of device behavior using the parameters so far extracted The basic settings are shown in the following figure Multiplot Window to Adjust Local Versus Global Parameters E GloballocalPlot 3 File Options Optimizer Plots Windows Help NEFF Wscale y NEFF m NEFF s E 21 DPHIB m DPHIB s 63 1E 6 1E 5 X Wdes LOG NEFF Lscale 16 7 16 6 Wdes LOG OPHIB Lscale Update Global Scaling Local Extraction Parameter to adjust global scaling Update Electrical Property Plots NEFF a I automatic Update CEEIAIES Ca SEE Devices Optimizer Tuner Optimizer Features Algorithm Levenberg Marquar
447. les in fact values at the beginning of miniset extraction lin_opti1 is an optimization call for linear region fitting at Vbs O for the parameters BET THE1 and VTO lin_opt2 is an optimization call for linear region fitting for all Vbs for the parameters KO THE2 VSBX and K This transform is used for the case of the 2 k factor model 348 MOSFET Models lin_opt3 is an optimization call for linear region fitting for all Vbs for the parameters KO and THE2 This transform is used for the case of the 1 k factor model subvt_opt1 is an optimization call for subthreshold region fitting at Vbs O for the parameters GAMOO MO and ZET1 normal_gds_opt1 is an optimization call for gds fitting at Vbs O for the normal devices and for the parameters GAM1 and ALP large_gds_ opti calls an optimization sequence for gds for the special case of the device with the largest length This sequence in turn calls vp_opt and alp_opt vp_opt is an optimization call for gds fitting at Vbs O for the parameter VP alp_opt is an optimization call for gds fitting at Vbs O for the parameter ALP set_VP sets the VP of any device by scaling of the VP of the large device set_VP_large sets a model level variable VP_ arge to hold the VP of the large device ids_opt1 is an optimization call for ids fitting at Vbs O for the parameter THES isub_opti1 is an optimization call for avalanche current fitting for Vbs O for the parameters A1 A2 and A3
448. lick the actual modified model in the Main Window Note that the displayed model name in the IC CAP Main Window has not changed eLoad a project e g example psp_nmos eGo to Extraction Flow Global Capacitance Oxide eAdd the newly generated function They will be shown in Available Functions to the right Adding a new function prompts you to allow the deletion of results already present within the loaded project since this extraction results may be different when using an additional parameter for optimization or tuning eExecute the function in Interactive Mode and the added parameter DLQ will be used in the Optimizer by default Interactive extraction of Cox using an additional parameter DLQ 63 MOSFET Models a InteractiveP lot 6 File Options Optimizer Plots Windows Help Cox f V gb Functions Devices Optimizer M 6 INDEX 31 00 Ygk 1 200 Y cox r amp 165 0p Region Boundaries Wood 0a Sor Calculate and show regions L 100 Du PEL Edit Calculation of regions Optimizer Features Algorithm Levenberg Marquardt Error Relative sim meas imeas Parameters Name Min Value Max TOXO 100 000p 2 366n 10 0000n NSUBO 1 Q00000E 3 459E 0 1 OQ0000E VFBO 1 50000 1 092 1 00000 DLO 100 000n 30 08n 100 000n 1 00000f 1 00000M N 1 w n 2 a oOo 5 oO O Save actual Optimizer Min Max values and use them instead of the global Min Max values
449. like to modify the standard circuit test circuit files be sure to copy the directory ICCAP_ROOT examples model_files bsim3 or bsim4 or psp circuits lt SIMULATOR gt and change the files inside the copied directory not the original ones There are predefined values for the variables You can change those variables or accept the values Using those variables you can define a minimum usable current for extraction The purpose of these variables is to cut out noisy current measurements by defining the lower limit of currents used for extraction of different parameters Related Topics DC Notes mosfet DC Information mosfet DC Initialize mosfet DC Binning mosfet DC Extract mosfet DC HTML mosfet DC Boundaries mosfet Back to Extraction of DC and CV Parameters mosfet DC Initialize The folder Initialize is intended to set initial conditions for parameter extraction Since the initial conditions for BSIM3 BSIM4 PSP HiSIM2 HiSIM_HV and BSIMSOI4 models differ the following section shows each Initialize folder one after the other BSIM3 Initialize folder to set initial conditions for the extraction of BSIM3 parameters Initial Yalues Parameters Flags TOX 7 5E 009 Model Noise TOXM 7 5E 009 z BINUNIT 1 NOIMOD 1 xJ 1 5E 007 cae aa ae PARAMCHK 1 Gate Current HSPICE only NGATE 1 DC Capacitance IGBMOD 0 ioe MOBMOD 1 E IGCMOD 10 LINT SE 008 AA DLC 5E 008 CAPMOD 3 3 TEMPMO
450. lows Loff L Designed 2dL The channel length reduction on one side of the channel consists of several empirical terms as shown below L re Eo rae L Pea J wl L n pe n L n n wn The use of the model parameters LL LLN LWN LW and LWL is very critical because they are only used for fitting purposes On the other hand they may be needed to achieve a good fit over a large area of channel lengths especially for processes with a minimum designed gate length of less than 0 25um The previous figure shows the influence of the geometrical channel length reduction LINT on the drain current of a short channel transistor while The following figure represents the channel length reduction according to the previous equation Channel Length Reduction dL as a Function of Channel Length L DL CE 9 la 6 8 2 0 4 8 E 6 6 14 8 Ldes E 6 Effective Channel Width The effective channel width is defined in BSIM3 as follows W _2dw W otf W Designed 2d The channel width reduction on one side of the channel consists of several empirical terms as shown below d Wy Wl dW _ lt _ _ _ _ int L Win p L Win ywn The use of the model parameters WL WLN WWN WW and WWL is very critical because they are only used for fitting purposes On the other hand they may be needed to achieve a good fit over a large area of channel widths especially for processes with a minimum designed gate width of les
451. lue set by the variable VG vs A constant value set by the variable VS vb A constant value set by the variable VB id The current output from the vd terminal The variables VD VG VS and VB are setup variables and are set automatically by the function MM9_STH_EXT The svt_quick_ext setup contains the following transforms mm9_ids calls the MM9 transform for current simulation copy_ids allows current to be copied from mm49_ids to id m subvt_extract calls the subthreshold region extraction functions quick_measure used by MM9_STH_EXT to initiate subthreshold region measurements Its functionality is the same as that of quick_measure in lin_quick_ext quick_ext sat_quick_ext used during the extraction of the saturation including output conductance parameters It contains input definitions for the bias voltages vd vg vs and vb as well as the definition for the current to be measured id The sat_quick_ext setup contains the following inputs and outputs vd A constant value set by the variable VD vg A constant value set by the variable VG vs A constant value set by the variable VS vb A constant value set by the variable VB id The current output from the vd terminal The variables VD VG VS and VB are setup variables and are set automatically by the function MM9_SAT_EXT The sat_quick_ext setup contains the following transforms mm9_ids calls the MM9 transform for current simulation copy_ids allows current to be copied from mmd9_
452. lumn on the Device List subfolder will be updated to reflect the actual assignment of Measurement Sets to Devices Configuration of Measurement Sets 2 MOSFET Models I Assignment of Devices to Measurement Sets DUT WS5u0_ L5u0_ Sa3ud W5u0 L5u0 SA3u0_WPEZ W5u0 L5u0 SA3u0_ WPE3 W5u0_L5u0 Sa3u0_WPE4 W5u0 L5u0 SA3u0 WPE1 WOu1s_LSu0 Sa3u0_WPE4 WOu1s L5u0 SA3u0_ WPE3 WOuis L5u0 sa3ud WOu1s L5u0 Sa3u0_WPE2 WOuis L5u0 Sa3u0 WPE1 W5u0_LOui3 Sa3u0 WPE1 W5u0_LOu13_ SA3u0_WPE3 W5u0 LOui3 Sa3u0_ WPE4 W5u0_LOu1i3_ sa3ud W5u0 LOu1i3 SA3uO_WPEZ WOu1s_LOu13_sa3ud W5u0_ LOui Sa3zud W5u0_LOu4 sa3ud WS5u0 LOuz5 Sa3ud WSud Lous Sa3ud m t m C c c C c c Cor cr tf Che a c eI SO SOC Sc oe S m m minm m m aeee m m m n Assign Measure Set to selected DUT Set Seti idvg idvd Set2 idvg idvd idvd_vbmin Cancel Importing measured data You are able to import data in other than IC CAP format by using the Too s menu and choosing Import Measured Data from other File Formats You can import data from UTMOST using the dat extension for example The Import Data window opens and lets you browse or enter the input file name as well as the output file location and a project name J Im port Data Import Import from Directory Import Files Output Directory For Project Name of Project ImportPrj Content of Output Directory Existing Projects _ Existing
453. maginary part of the Y11 admittance data Y12i plots the imaginary part of the Y12 admittance data Y2ir plots the real part of the Y21 admittance data Y22r plots the real part of the Y22 admittance data Vd_Vg plots the distribution of test data in the Vgs Vds plane It shows how the data is taken adaptively depending on the device nonlinearities More test data is taken 338 MOSFET Models where the device characteristics change rapidly such as at the knees of the I V curves and the onset of breakdown and less in the linear saturation region If you are satisfied with the measured data for your device proceed to the model generation Be sure the limits of the measurement domain are adequate the domain should extend beyond the normal operating range of the device If the measured data does not show the limits of device behavior you may wish to redefine the voltage ranges you set in the data_acquisition transform using values that are less conservative and perform the data_acquisition again Generating the Model This procedure calculates the model parameters from the measured data and generates a corresponding model for the device The model nonlinear functions are calculated by contour integration therefore you must provide the program with a starting point for the contour integration If you are generating a model from a previously stored data set perform the steps listed later in this procedure under Generating a Model from P
454. mance Extractions are typically completed instantly and the newly extracted model parameter values are placed in Model Parameters Simulating Device Response Simulation uses model parameter values currently in Model Parameters A SPICE deck is created and the simulation performed The output of the SPICE simulation is then read into IC CAP as simulated data Select a simulator from Tools gt Hardware Setup or define a STIMULATOR variable DC simulations generally run much faster than cv simulations CV simulations can be done in a much shorter time by executing the calc_mos_cbd_model transform instead of running the simulator If simulated results are not as expected use the Simulation Debugger Tools menu to examine the input and output simulation files The output of manual simulations is not available for further processing by IC CAP functions such as transforms and plots For more information refer to Using the Simulation Debugger simulation Displaying Plots The Display Plot function displays all graphical plots defined in a setup The currently active graphs are listed in the Plots folder in each setup Measured data is displayed as a solid line simulated data is displayed as a dashed or dotted line After an extraction and subsequent simulation view the plots for agreement between measured and simulated data Plots are automatically updated each time a measurement or simulation is performed Optimizing Model Parameters
455. mbedding structures The Graphic User Interface from BSIM4 has been adopted One of the main advantages of this concept is that the measured data can be used by BSIM3 and BSIM4 Modeling Packages for parameter extraction The BSIM3 Modeling Package now generates model cards and scalable RF models for the following simulators Spice3 delivered with IC CAP Advanced Design System Hspice Spectre The documentation was totally reworked to account for the common user interface with the BSIM4 Modeling Package and similar upcoming modeling products In addition a detailed description of all the files of the Modeling Package is given All temperatures in the setup and documentation are now given in K instead of degree C The supported model is BSIM3v3 2 4 released on Dec 21st 2001 BSIM3_DC_CV_Measure The Keithley switching matrix models K707 and K708a are now supported The maximum compliance values can now be defined together with the other measurement settings Three new functions are implemented to drive the BSIM3_DC_CV_Measure module from a wafer prober control macro An example for such a control macro can be found in examples model_files mosfet BSIM3 examples waferprober prober_control mdl e BSIM3_DC_CV_Extract A complete new extraction flow is implemented A certain extraction group e g Basic VTH Mobility can be invoked several times with different configurations Moreover the flow inside an extraction group can be spe
456. me_pd tmp_ps tmp_nrs tmp_nrd always define the TOTAL width drain area number of drain squares of the multi finger device The width drain area of a single finger of the multifinger MOSFET will be calculated inside the BSIM4 model using the instance parameter NF and the selected GEOMOD parameter define bsim4_rf_extract i1 i2 i3 i4 epar ame tero Or SUH C Ir CUIT SAPA AE a a E a ease parameters tmp_l 1u tmo_w 10e 6 tmp_nf 1 tmp_ad 10e 12 tmp_as 10e 12 tmp_pd 22e 6 tmp_ps 22e 6 tmp_sa 0 tmp_sb 0 tmp_sd 0 tmp_nrd 0 tmp_nrs 0 2 A BS IMA model card S SosSSs 5 reepa HS S A SSS SSS SSS Se Se SS SS Se eee SS SSeS NMOS 1 PMOS 0 VERSION 4 50 BINUNIT 2 PARAMCHK 1 MOBMOD 1 RDSMOD 0 IGCMOD 0 IGBMOD 0 CAPMOD 2 RGATEMOD 0 RBODYMOD 0 TRNQSMOD 0 ACNQSMOD 0 FNOIMOD 1 NOIMOD 0 DIOMOD 1 PERMOD 1 GEOMOD 0 EPSROX 3 9 TOXE 3e 9 TOXP 3e 9 TOXM 3e 9 DTOX 0 XJ 1 5e 7 NDEP 1 7e17 NGATE 0 NSD 1e20 XT 1 55e 7 RSH 0 RSHG 0 1 VTHO 0 7 PHI 0 K1 0 33 K2 0 018 K3 2 K3B 0 WO 2 5e 6 LPEO 1 74e 7 LPEB 0 VBM 3 DVTO 2 2 DVT1 0 53 DVT2 0 032 DVTPO 0 DVTP1 0 001 DVTOW 0 DVTIW 5 3e6 DVT2W 0 032 ETAO 0 08 ETAB 0 07 DSUB 0 56 UO 0 067 UA 1e 9 UB 1e 19 UC 0 0465 UD 1e 14 UP 0 LP 1e 8 EU 1 67 VSAT 8e4 AO 1 AGS 0 BO 0 Bt 0 KETA 0 047 At 0 A2 1
457. mensions and process parameters like channel length and width gate oxide thickness substrate doping concentration and LDD structures Due to its physical nature and built in geometry dependence prediction of device behavior of advanced devices based on parameters of the existing process is possible As a further improvement one set of model parameters covers the whole range of channel lengths and widths of a certain process which can be used in circuit designs Due to the physical meaning of many model parameters the BSIMSOI model is an ideal basis for the statistical analysis of process fluctuations BSIMSOI models the following physical effects of modern sub micron MOS transistors manufactured in Silicon on Insulator technology e Threshold Voltage o Vertical and lateral non uniform doping o Short channel effects o Narrow channel effects e Mobility o Mobility reduction due to vertical fields o Carrier Velocity Saturation e Drain Current o Bulk charge effect o Sub threshold conduction o Source drain parasitic resistance e Bulk Current e Output Resistance o Drain induced barrier lowering DIBL o Channel length modulation CLM o Substrate current induced body effect SCBE e Short channel capacitance model e Temperature dependence of the device behavior BSIMSOI4 Enhancements The following enhancements are done in BSIMSOI4 to account for constantly shrinking design features and effects caused by the shrinking dimensions 1 Scalab
458. ments Multifinger devices are common only in high frequency characterization of MOS devices since the input resistance of a network analyzer is typically 50 Ohm Remember all geometries are to be given in microns um Device geometries Source Area Source Perimeter AS PS Depending on your choice of temperatures on the Temperature Setup folder one or more columns are marked with the temperatures you have entered appear The fields of 31 MOSFET Models those columns show either 0 for no measured data available M for DUT already measured or for DUT not to be measured at that temperature You can enter a comment for each DUT When using a switch matrix for capacitance measurements you can enter a module name to measure one complete module with all its DUTs at once This is intended for use with a prober card and taking measurements using the step and repeat function of a wafer prober If you are using a switch matrix you must enter the pin numbers of the switch matrix pin connections to the capacity you re about to measure The fields for high and low connection of the CV measuring instrument are marked H or L respectively the ground connection is to be entered in the column marked 0 Since a ground connection is not required for every measurement only those fields where a ground connection is not required are marked with a all others are predefined to node No 0 See Test Structures for CV Measurem
459. mes channel length CGDO Gate to Drain Overlap Capacitance Capacitance due to the lateral diffusion of the drain in 0 F m an Si gate MOSFET Not voltage dependent Total Gcd capacitance equals Cgdo times the channel width CGSO Gate to Source Overlap Capacitance Capacitance due to the lateral diffusion of the source 0 F m in an Si gate MOSFET Not voltage dependent because it is not a junction capacitance Total Cgs capacitance equals Cgso times channel width CJSW Zero Bias Junction Sidewall Capacitance Models the nonlinear junction capacitance 0 F m between the drain and the source junction sidewall Pd Ps CJSW total junction sidewall capacitance MJSW Grading Coefficient of Junction Sidewall Models the grading coefficient for the junction 0 33 373 PB FC IS JS RD UCRIT UEXP UO UTRA VMAX NEFF LD TOX TPG WD XJ NFS NSS NSUB DELTA ETA GAMMA VTO KAPPA KP MOSFET Models sidewall capacitance Bulk Junction Potential Models the built in potential of the bulk drain or bulk source junctions The default is usually adequate Forward Bias Non Ideal Junction Capacitance Coefficient Models the point FC PB at which junction capacitance makes the transition between forward and reverse bias Electrical Process Substrate Junction Saturation Current Helps model current flow through the bulk source or bulk drain junction Substrate Junction Saturation Current m2
460. meters for a specific device simultaneously The model developers outline a practical extraction sequence This recommendation is the base for the default extraction flow programmed into the PSP Modeling Toolkit The following describes the sequence of parameter extraction used in the toolkit For every device the extraction of local parameters must be performed However not every local parameter for all devices must be extracted Some parameters are extracted for only one device Other parameters are extracted for a few devices and are fixed for other devices A number of parameters can be kept fixed at default values and only optimized in fine tuning steps during extraction Note that for all extractions the reference temperature TR must be set to the actual room temperature the devices are measured under Before extraction switch parameters SWIGATE SWIMPACT SWGIDL SWJUNCAP and TYPE are set to appropriate values and QMC is set to 1 to include quantum mechanical corrections Some parameters influencing the DC behavior of a MOSFET are extracted accurately only from CV measurements NP for example In order to get good DC parameter values you should start from the default parameter set and use a value of TOX as is known from technology With this settings extractions of VFB NEFF DPHIB NP and COX can be done using the measurement of CGG vs VGS of the long wide device The extraction process starts with local parameters for the L
461. mevdi_bd_area TempK mdm measure extract project_name DUT_namevwdi_bd_perim TempK mdm measure extract project_name DUT_name di_bd_perim_gate TempK mdm measure extract project_name DUT_namevwdi_bs_area TempK mdm measure extract project_name DUT_namevw di_bs_perim TempK mdm measure extract project_name DUT_name di_bs_perim_gate TempK mdm measure extract project_name DUT_nameerf_s_dut TempK mdm measure a project_name DUT_namerwrf_id_bias project_name DUT_name rf_id_bias_points TempK mdm gt mdm measure project_name DUT_nameerf_idvd TempK mdm measure extract project_name DUT_name rf_s_open TempK mdm measure project_name DUT_name rf_s_short TempK mdm measure project_name DUT_name rf_s_through TempK mdm measure o ATMO PathHTML htm o tract extract Ss PathHTML imgmenu extract extract Pictures for file structure Path HTML setups htm extract extract Measurement Setups PathHTML results htm extract extract Pages with results PathHTML results txt extract extract Parameter set for HTML p PathHTML results images gif extract extract Images p PathHTML results imgzoom gif extract extract Zoomed Images See Also Getting Started with MOS Modeling mosfet MOSFET Models DC and CV Measurement mosfet RF Measurement mosfet Extraction of DC and CV Parameters mosfet Extraction of Parameters for the RF Models mosfet Using the MOS Modeling Packages mosfet
462. mmercial simulators The following listing shows a typical binned library for ADS example ADS BinModel Min Cinclusive Max exclusive inclusive if Max Min model my_nmos BinModel Model 1 my_nmosi Model 2 my_nmos2 Model 3 my_nmos3 Model 4 my_nmos4 Model 5 my_nmos5 Model 6 my_nmos6 Model 7 my_nmos7 Model 8 my_nmos8 Model 9 my_nmos9 Param 1 Length Param 2 Width Min 1 1 L1 Max 1 1 L2 Min 1 2 W1 Max 1 2 w2 Min 2 1 L2 Max 2 1 L3 Min 2 2 W1 Max 2 2 Ww2 Min 3 1 L3 Max 3 1 L4 Min 3 2 W1 Max 3 2 w2 Min 4 1 J L1 Max 4 1 L2 Min 4 2 W2 Max 4 2 w3 Min 5 1 J L2 Max 5 1 L3 Min 5 2 W2 Max 4 2 w3 Min 6 1 J L3 Max 6 1 L4 Min 6 2 W2 Max 4 2 w3 Min 7 1 L1 Max 7 1 J L2 Min 7 2 W3 Max 4 2 w4 Min 8 1 J L2 Max 8 1 L3 Min 8 2 W3 Max 4 2 w4 Min 9 1 J L3 Max 9 1 L4 Min 9 2 W3 Max 4 2 w4 model my_nmos1 MOSFE MOS 1 PMOS 0 etc model my_nmos2 MOSFE MOS 1 PMOS 0 etc model my_nmos3 MOSFE MOS 1 PMOS 0 etc model my_nmos4 MOSFE MOS 1 PMOS 0 etc model my_nmos5 MOSFE MOS 1 PMOS 0 etc model my_nmos6 MOSFE MOS 1 PMOS 0 etc model my_nmos7 MOSFE MOS 1 PMOS 0 etc model my_nmos8 MOSFE MOS 1 PMOS 0 etc model my_nmos9 MOSFE MOS 1 PMOS 0 etc Definition of binn
463. model file can be loaded into IC CAP and can be run in a demo mode without taking actual measurements Other DC CV Measurement Module Folders Notes mosfet Temperature Setup mosfet Device Definition mosfet Options mosfet Device Definition The next step in the modeling process is to set up the measurement conditions for different measurement tasks like DC Capacitance or Diode measurements and to enter the devices to be used The Device Definition pane allows an easy setup of conditions for DC Transistor and Capacitance as well as DC Diode measurements The following figure shows the Device Definition pane used for setting up measurement conditions as well as the devices to be measured You can use the icons or the menu to save this settings before proceeding to the next task Device Definition Folder 48 BSIM4_DC_CV_Measure 1 File Configuration Data Tools Help oe 4 Prd E TFT MACAK t xk BEL Notes Temperature Setup Switch Matrix Options Data AE Transistor Measureme Polarity NMOS PMOS E idvg vier Compliance 4 E Device List vd vg vb vs ve v6 3k Capacitance qr Ir 4 1r ered loa ooor flor for flor fo Measurement Sets Set Name Setups included Seti idvg idvd Set2 idvg idvd idvd_vbmin 5 The Data tree on the left side of the Device Definition pane displays the Data for this measurement project This tree definition can be different for different models The
464. mosfet 260 MOSFET Models Simultaneous Adjustment of Local and Global Parameters The extraction flow starts with the extraction of some global parameters followed by local extractions and the scaling process as described before For this purpose you can use manual or automatic extractions After that iterations are necessary to adjust local and global model behavior Since these extractions optimizations are very sensitive no automatic extractions are programmed so you have complete control over the process Extraction Flow used for the PSP Modeling Package W psP_DC _CV_Extract 1 File Initialize Binning Extract Plots HTML Optior SN mile S15 Notes Information Initiaize Binning n a Extrac Extraction Iteration is necessary at this point For this adjustment purpose a special arrangement of plots has been defined see the following figure The plot area is divided into three regions e a global parameter region with scaling plots of up to three parameters e an electrical scaling region with additional plots to show the scaling behavior of the global simulation model It is useful to have for example diagrams of Vtlin L or Idsat W to view the influences of parameter changes onto the electrical behavior of all devices e a local extraction region to invoke a specific local device with its parameter set In addition to what the modeling engineer is used to the PSP model parameter extraction shows plo
465. mosfet RF Initialize mosfet RF Extract mosfet RF Display mosfet RF Extract HTML mosfet RF Extract Options mosfet RF Extract Boundaries mosfet Back to Extraction of Parameters for the RF Models mosfet RF Extract Notes The Notes folder has the same functionality as the one being used in the DC modules and has been described already See DC Notes mosfet Related Topics RF Extract Information mosfet RF Initialize mosfet RF Extract mosfet RF Display mosfet RF Extract HTML mosfet RF Extract Options mosfet RF Extract Boundaries mosfet Back to Extraction of Parameters for the RF Models mosfet RF Extract Options This folder is used to set variables for the extraction process and options for plots to be displayed Options Folder TEBSIM4_RF_Entract 12 Ss o laxi Pile Intishze Extract Pls HTWL Options Boundaries Help IsSia F229 So0le xe ul Notes Information Initialize Extract Display HTML Options Boundaries r OE EE BE a a tae pr HICCAP _2009 examples model_files masfer bsim4lc Project Example scab Project directory i usersidefadt_ 2007 Satus The Simulator variable field and the paths to circuit and test circuit files have a blue background You cannot change those field entries directly Instead you have to choose the Simulator and Circuits Change button to set another target simulator as well as paths to circuit and test circuit files If
466. most important equations within the BSIMSOI formulations since it determines the body potential through the balance of the various body current parts Only after determining the body potential the IV characteristics of a SOI MOSFET can be predicted precisely The parts of this current are shown in the following figure which is taken from the original UC Berkeley documentation 297 MOSFET Models The parts of this current are Impact Ionization Current The electrons in the channel of an n channel MOSFET are exposed to a very large electrical field near the drain In this high field some electrons coming from the source will gather enough energy to cause impact ionization and additional electrons and holes are generated by avalanche multiplication Gate Induced Drain Leackage At low Vgs and high Vds in long channel devices the DC body potential can be affected by the gate induced drain leakage effect e Diode and BJT Modeling There are five current components included into the modeling of diodes and parasitic bipolar action within BSIMSOI These are injection currents from body to source drain and from source drain to body recombination in the body to source drain junction depletion region and in the neutral body as well as tunneling current If there is a neutral region present a conventional pn junction diode model could be used But in full depletion with only a few majority carriers available for diffusion or recombination
467. mple Open the project using this modelfile Since the required customized functions are stored with this modelfile no warning occurs The displayed file name in the IC CAP Main Window uses the default extraction modelfile name Additional Modifications Custom Main Groups and Extraction Groups Since it is not possible to modify the default extraction steps the factory settings you must define your own Main Groups and Extraction Groups in order to modify an existing extraction flow To add a New Main Group select one of the available Main Groups using the right mouse New Main Group Adding a new main group 64 MOSFET Models T Add New Main Group New Name New Main Groupi You will be prompted to enter a name for the main group to be created The new main group will be inserted below the group it is based on Newly created Main Group set Configuration Wizard for Extraction Functions 12 Configuration Edit Options Help o eA tt Available Extractions Overview Customized Functions Default Extraction Flows Available Extractions in Cy Lc New Main Group 4 tc AddGroup E Le Move Up ide H Le ce n Le Move Down ance E PS ia Le H Le nce amp FA Binning In rare cases a newly added main group will not be empty as it should be Instead there are items in the new group Even though there are items shown you cannot select any of those functions
468. must be connected to the emitter as GND Getting Started with Agilent Root MOSFET Model Generator To open Agilent Root MOS model example file 1 Launch IC CAP and choose the required model file The default Agilent Root MOS model file used as a starting point in this tutorial is examples model_files mosfet HPRootMos mdl 2 Choose File gt Examples gt model_files gt mosfet from the IC CAP Main window and open the HPRootMos mdl1 Agilent Root MOS model example file The Model icon is displayed in the IC CAP Main window 3 Double click the HPRootMos model icon to start the measurement module The HPRootMos Model window is displayed Important Do not install the device yet This tutorial provides instructions to install it after extracting the measurement port resistances Before you continue with the IC CAP procedure create a directory in an appropriate location in the UNIX structure using the mkdir command to store the generated data and model files Rename the new directory to associate it with the device you are going to model Use the cd command to change to the new directory in UNIX Using the Agilent Root MOS Model This section provides an example step by step procedure for measurement and model generation of an NMOS device The values you use in generating your own device model depend on the particular characteristics of your device Therefore it is recommended to use the device data sheet if available as a refere
469. n or e vg_start Vthreshold 2 and vd_start Vbreakdown 2 vgmax is the approximate gate voltage corresponding to the maximum device drain current for a typical drain voltage in saturation vgmax is generally lower in magnitude than Max Vg The figure above shows an appropriate value for the contour integration point of an example device marked with a on the plot Setting the model_generator Variables 1 Select create_mdl gt Extract Optimize gt model_generator The table illustrated below is displayed Variables in the model_generator Transform Select Transform Function HPRoot_MOSFET data_acqusition vd_start 3 000 EEEN vg_start t_dispersion Enter an appropriate value for vd_start Note that for a PMOS device this will be lt OV Enter an appropriate value for vg_start Note that for a PMOS device this will be lt OV Enter an appropriate value for t_dispersion This is the dispersion time constant and its default value is 1e 17 or 10 attoseconds 10 00a In most cases t_dispersion is not a significant factor although it is used in the model generation calculations However in a case where you wish to add time dispersion effects you can increase the value ae a Executing the Model Generator Transform 1 Select Execute to start the model_generator transform 2 A dialog box asks you for an MDS file name The standard file generated by the model for interface with MDS is named State mds If
470. n tactor even odd NF Dpc p Resp W factor even odd 0 5 for even number of fingers NF factor even odd 1 for odd number of fingers NF The values of the elements of the SPICE equivalent circuit are calculated from device dimensions of the actual device W L NF and additional model parameters like the gate sheet resistance RSHG Following is a SPICE netlist for the fully scalable BSIM3 model LINK CIRC Circuit data circuitdeck T aa a pe a a a eb a a a Se S a a tts en ec ph ne ah ye el ay ye ee Fully scalable subcircuit model for BSIM3v3 RF n type devices Simulator UCB Spice3e2 Model BSIM3 Modeling Package Date 08 11 2003 Origin ICCAP_ROOT bsim3 circuits spice3 cir rf_nmos_scale cir NS Airs pce Fl ea eee te ee cera eal ae i hr rt A ee a hr pee a A a ie ae a aa pe a ar alae ie Re pee OO ete subckt bsim3_rf_extract 1 2 3 4 Information for model implementation 7 755 r rrr rrr rrr rrr rrr rrr rrr tre Due to the limitation of UCB spice3e2 the equations for the scaled RF model behavior are included in the DUT parameters of the DUT RF_Transistor_Scale in the IC CAP model BSIM3_RF_Extract To implement this scalable model in your target simulator please include those equations using the appropriate syntax in the final model deck BSIM3 model card cession rrr rrr rrr rrr rrr rrr rrr ssc sne echo MODEL BSIM3_HF NM
471. n OPEN and SHORT or to achieve a higher quality in de embedding Please see the transform deembed_all to locate the entry point for your specific de embedding procedure The ultimate tool for de embedding with IC CAP is the De embedding Tool kit where a large number of ready to go solutions together with the theoretical background can be found Please contact Dr Franz Sischka from Agilent EEsof franz_sischka agilent com for more details Verification procedures The BSIM3v3 Modeling Package provides a method to verify the de embedding It uses a THROUGH dummy test device After a correct de embedding of the parasitic components the S parameters of the THROUGH should show the behavior of an ideal matched transmission line with ZO 50 Ohm and a TD that represents the electrical length of the through line in the THROUGH dummy device The S and S curve should be concentrated in the center of the Smith chart while S and S should both begin at 1 j 0 and turn clockwise on the unity circle If these pre assumptions are not given the following items should be checked e Is the calibration OK e If the OPEN method is used consider to enhance the de embedding quality by using the OPEN_SHORT method which removes the inductive parasitics in the measured data e If the OPEN_SHORT method is used and the frequency is very high gt 30 GHz it should be checked whether the assumptions for using OPEN_SHORT are still given The easiest
472. n is defined by the error handling section Begin and end of the error handling section is defined by if val action error then end if Add code for the error message of the failcode defined in the executing section e g if val failcode NPO_NPL_3 then msgi1 Failure msg2 Laux is constant 84 MOSFET Models end if e Error handling PSP_DC_CV_Extract PSP_DC_CV_Extract Scaling User_execute is Active 34 Eile dit Measure Extract Simulate Optimize Data Tool Macros Windows Heb 2 XO PS 4 oa HOM MSO Hl clais DUTs Setups Circu Model Parameters Model Variables Macros Model GUI Items Select DUT Setup OC Transistor Global Measure Simulate Instrument Options Setup Variables Extract Optimize Plots Setup GUI Items _ Execute Select Trarstorm Tune Fast Function Lecale Wocale LWscale tune LocaPa execute User_execute Vth_Ideat_ve_Devices _DC Trarsistor STI STi Extended specifications for the configuration routine Open the the setup Extract and the DUT Customer_Configuration Add a new extracton Group Edit the transform defineExtractionGroups There are three user defined extraction groups provided which can be used as a pattern Modify the code of this transform e Definitions of the user defined extraction groups 85 MOSFET Models e Change the number of user defined extension groups to
473. n of the channel stop dopant ions Temperature at which the parameters have been determined Threshold voltage at zero back bias Coefficient of the temperature dependence of VTO Coefficient of the length dependence of VTO Second coefficient of the length dependence of VTO Coefficient of the width dependence of VTO Low back bias body factor Coefficient of the length dependence of KO Coefficient of the width dependence of KO High back bias body factor Coefficient of the length dependence of K Coefficient of the width dependence of K Transition voltage for the dual k factor model Coefficient of the length dependence of VSBX Coefficient of the width dependence of VSBX Gain factor Exponent of the temperature dependence of the gain factor Coefficient of the mobility due to the gate induced field Coefficient of the temperature dependence of THE1 Coefficient of the length dependence of THE1 Coefficient of the temperature dependence of the length dependence of THE1 Coefficient of the width dependence of THE1 Coefficient of the mobility due to the back bias Coefficient of the temperature dependence of THE2 Coefficient of the length dependence of THE2 Coefficient of the temperature dependence of the length dependence of THE2 Coefficient of the width dependence of THE2 Coefficient of the mobility due to the lateral field Coefficient of the temperature dependence of THE3 Coefficient of the length depende
474. n one by checking the appropriate boxes Note If you are not using a switch matrix leave all three check boxes unchecked In this case you do not have terminal assignment columns in the Transistor s Device List table in the Device List folder Instead you determine the connections by wiring the appropriate SMU to the desired transistor terminal Note Assignments must use SMU1 SMU4 This assignment is done inside the hardware setup of IC CAP Usually the default of the appropriate DC CV Analyzer is SMU1 4 In rare cases such as the Agilent E5250 for example the default SMU number corresponds to the slot number of the module inserted into the instrument If your E5250 uses 4 SMU s at slot No 1 3 5 6 the default names of the SMU s are SMU1 SMU3 SMU5 and SMU6 You must change this default names to reflect SMU1 SMU2 SMU3 and SMU4 to properly communicate with the BSIM3 4 and PSP modules Note To change or enter the names of the Source Measurement Units SMU s open the model for editing then go to the folder DUTs Setup subfolder Measure Simulate Configure the different inputs outputs there Defining the use of a switch matrix for measurements 14 MOSFET Models az BSIM4_DC_CV_Measure 1 File Configuration Data Tools Help pe GSeSee gt xk Bk Notes Temperature Setup Switch Matrix Device Definition Options Use Switch Matrix for 0 OC Transistor Meanrements C Capacitance Measurements C Diode Measur
475. n step from a list of parameters You can select the intermediate results to use from a drop down list at the bottom of the Add Starting Parameters window that shows already extracted devices up to this stage of extractions You are also able to delete single parameters from the list Note Global binning in this context means there is the possibility to extract some parameters in a more global way The device parameters are already extracted now you are interested in geometrical influences on some parameters Binning in the usual way recognizes dependencies on device length and width represented through bins Those bins represent ranges of lengths and widths of the devices However global binning uses no bins but tries to extract the influences over length parameter L width parameter W and the product of L W parameter P Using this feature it is possible for example to represent a normally not on length and width depending parameter like VTHO in a geometry dependent way through extraction over several different devices in this global binning approach Using the menu Extract gt Extraction Flow there are buttons to Add or Delete Extractions from the flow There are icons provided for these actions too You will be prompted with a list of available extractions Select one of the extraction steps and press Add on that form If you have already extracted parameters the Extraction Status field shows intermediate steps This will show
476. n there is a global parameter extraction optimization step involving all devices of max length The next step uses the Short Wide device same width but shortest length to extract local parameters and so on The following figure is a graphical representation of the extraction sequence The numbers show the extraction order the circles and squares with blue background or shaded in a black and white representation and blue numbers are local parameter extraction steps the ones with a red frame and red numbers are global parameter extraction steps Flow of Extraction as programmed inside the PSP Toolkit Wim 4 5 10 5u 240n 150n 90n 65n 45n 60n 90n 150n 240n 5u L m This procedure was enhanced since the one recommended by the model developers needs a totally regular arrangement of devices a requirement usually not given in practice Therefore the PSP Modeling Package uses a somewhat different approach local parameters that do not have for example a width dependency will be computed from global parameters and will not be extracted for the local model again The following table should clarify the extraction sequence as programmed for the standard extraction flow This table shows due to limited space a reduced number of parameters only Note Inside the extraction flow window some parameters shown have an x appended This is a place holder used during multiple extractions optimizations for this parameter not a re
477. nated by carrier velocity saturation this is the so called saturation region In this region three different physical mechanisms are controlling device behavior Those mechanisms are Channel Length Modulation CLM Drain Induced Barrier Lowering DIBL and Substrate Current Induced Body Effect SCBE Each of those mechanisms dominate the output resistance in a specific region Output Resistance vs Drain Source Voltage CLM ly MA ee o l i lX 5Xli MlMli MlMi I iMl i i iMl iIi iMliI 5 iiI 5ii W a ad D 17 D a a a D swyoy Y The continuous channel current equation for the linear and saturation region as 203 MOSFET Models implemented in BSIM4 is N P V y laso NE 1 Vasat ACLM lis z e 1 s__ds0 cim Asat 7 J Viseff J1 V y 4 ADITS ASCBE ADIBL Vas Vaai The Early voltage VAsat at Vgs Vdsat sat is used to get continuous expressions for drain current and output resistance between linear and saturation region B _ Abulk Vdsat V a eg Asat Kp T 2 2 V 2 gsteff q E L R y 9 gt Y W PV sat eff V isat sie aa Coxe Waff j steff P K TANC rg Voff Abuik 4 In this equation the channel current dependencies are modeled using specific Early voltages VA as will be described in the following sections Channel Leng
478. nce 321 MOSFET Models This example is a starting point and utilizes only a subset of total capabilities provided by IC CAP It describes all the steps necessary to configure IC CAP with the parameters for preverification measurements parasitic extractions and the main data acquisition Once a model is developed for a particular device type the built in scaling feature allows you to apply it to any device with the same process and a different total gate width and or number of fingers Notes e In this example you can modify the variable values in factory default files but do not change the names of any variables or setups These variables or setups are used by IC CAP in data acquisition and model generation process e This example measures the MOSFET under test in a common source configuration The Agilent Root MOS Model example provides detailed instructions on how to Initialize device parameters e Measure and extract the system measurement port series resistances e Perform a DC measurement to preverify device DC performance e Calibrate the network analyzer for both swept and CW measurements e Perform an S parameter measurement to preverify device performance at high frequencies e Measure and extract the device parasitic resistances e Set up and initiate the main data acquisition and plot the measured data e Set up and initiate the model generation and plot the calculated state functions e Verify the model ag
479. nce of THE3 Coefficient of the temperature dependence of the length dependence of THE3 Coefficient of the width dependence of THE3 Coefficient for the drain induced threshold shift for large gate drive Coefficient of the length dependence of GAM1 Coefficient of the width dependence of GAM1 Exponent of the VDS dependence of GAM1 Factor of the channel length modulation Exponent of length dependence of ALP Coefficient of the length dependence of ALP Coefficient of the width dependence of ALP Characteristic voltage of channel length modulation Coefficient of the drain induced threshold shift at zero gate drive Coefficient of the length dependence of GAMO Exponent of the back bias dependence of GAMO Factor of the subthreshold slope Coefficient of the temperature dependence of MO Coefficient of the length dependence of MO Exponent of the back bias dependence of M Weak inversion correction factor Exponent of length dependence of ZET1 Coefficient of the length dependence of ZET1 345 Default 501 3n 9 787u 198 7n 0 000 212 7n 0 000 27 00 810 2m 1 508m 18 95n 15 09f 55 35n 610 0m 76 45n 55 79n 170 5m 293 1n 185 5n 1 926 443 2n 349 8n 155 9u 1 655 306 3m 613 8u 66 10n 95 78p 44 23n 43 49m 97 75u 56 97n 13 64p 19 14n 264 4m 8 227u 135 8n 509 4p 20 09n 65 48m 28 22n 9 967n 600 0m 6 248m 0 000 0 000 4 761n 443 5m 20 40m 5 295f 2 000 536 6m 470 4u 164 2u
480. nd Qd are outputs of the model generator and will be viewed later For hardcopy output black and white can be reversed for faster printing and easier reading on paper as explained in the procedure If you wish to plot data from a previously stored data set you will need to perform the steps explained under To Plot an Earlier Data Acquisition on the next page Otherwise follow these steps 1 From the Plots tab select the plot of your choice and Display Plot 2 You can augment the annotation of a plot by specifying header and footer labels you wish to print with the data However it is essentia not to change the Y data input fields 3 To change a plot s annotation go to the Header or Footer lines in the plot definition You can type a label of your choice in the header or footer input field right side of the definition table Then select Options gt Update Annotation and your label is added to the plot Note Changing the Y Data input fields can cause anomalies in the measurement and modeling results 4 If you wish to exchange the black and white in a plot for better hardcopy quality select Options from the plot menu and Exchange Black White from the pull down menu You can also change from colored traces to all black by selecting Options gt Color This is particularly useful if one of the traces is a light color such as yellow which may not show well against a white background 5 To get a hardcopy of a plot from th
481. nd measured data agree The illustration shows example measured and simulated id_vd data Verifying the Model S Parameter Data This procedure verifies the model S parameter data against the S parameter data measured in the s_vgvdf setup using the MNS simulator link Note The simulator used must be MNS If the SIMULATOR in the model variable table is set to another value change it to mns The name of the model file must be State mds for the purposes of verification to maintain the MNS simulator link 1 Select the s_vgvdf setup Make sure the s output Type is set to B 2 Select Plots gt Display All Two S parameter plots are displayed 1 s11_s22 shows example measured and simulated S11 and S22 data 2 S12_s21 shows example measured and simulated S12 and S21 data 3 Select Measure Simulate gt Simulate Check the agreement between the simulated data dotted lines and measured data 4 Close the plots Storing Your Model and Interfacing with MDS Once you have developed your device model you can store it in a file for future use You can use it for circuit simulation in the Agilent RF and Microwave Design System inserting it into circuits under design to emulate the characteristics of your device It can be used to represent any device with the same geometry from the same process or scaled to represent a different sized device It will predict the gain power gain compression and harmonics performance of the device as a comp
482. ndent However experimental data show that the overlap capacitance changes with gate to source and gate to drain biases In a single drain structure or the heavily doped S D to gate overlap region in a LDD structure the bias dependence is the result of depleting the surface of the source and drain regions Since the modulation is expected to be very small this region can be modeled with a constant capacitance However in LDD MOSFETs a substantial portion of the LDD region can be depleted both in the vertical and lateral directions This can lead to a large reduction of overlap capacitance This LDD region can be in accumulation or depletion In BSIM3v3 a single equation is implemented for both regions by using such smoothing parameters as VQS overlap ANd Vgdoverlap for the source and drain side respectively Unlike the case with the intrinsic capacitance the overlap capacitances are reciprocal In other words Cgs and Cgd overlap CSG overlap overlap Cdg overlap The model equations for the overlap capacitance are shown for the drain overlap capacitance and are identical for the source overlap capacitance Overlap charge per gate width Overlap Capacitance Equation 143 MOSFET Models Coveriap cGDov tca pLly y _CKAPPA 1 ji Hod ove Le Wore gd gd overlap 2 CKAPPA where 2e gN gt i t LDO CKAPPA c ox with the smoothing parameter p Hay fa 2 Ved overlap 7 ol ga tD 4V gat n 8
483. nductance i M Devices DUTs Output Behavior 3 Results for Different Test Devices S Parameters btr ng w4 Transition Frequency h21 i li Transconductance citance tr3_n6_w8 J tr2_nt 6_w4 Output Behavior _Jtr3_n6_w8 S Parameters oJ tr4_n 2_we8 Transition Frequency h21 CI Model Parameter Set Capacitance jo ify tr2_n1 6_w4 te _nl2_w8 Transconductance Output Behavior S Parameters Transition Frequency h21 Capacitance Model Parameter Set trl_n3_w4 tr2_nl6_ w4 tr3 n w3 tr ni2 w3 98 Zoom Detach Print New HTML report i Content eB E Setup ply Measurement iw lity Devices DUTS a r Results for Different Test Devices wn nB_w4 i lif Transconductance lif Output Behavior lif S Parameters lif Transition Frequency h21 i iow lity Capacitance tr2_n1 6_w4 fj tr3_n6_we8 _jtr4_n12_w8 sC Mode Parameter Set e tri _n8_we4 ifm tr2_111 B_w4 liga tr3_n16_w8 iow ling tr4_ 111 2_ we Zoom Detach Print New HTML report J Setup fy Measurement jj Devices DUTs Results for Different Test Devices 4 Jtr1_n8_w4 jy Transconductance Cie ren Behavior S Parameters fq Transition Frequency h21 T Capacitance A tr2_ ni w4 tra _n6_w8 tr _n12_w8 I Model Parameter Set Titri _ng_ w4 ify tr2_n1 6_we4 ify tr3_n6_w8 fy tr4_n1 2_w8 Related Topics e DC Notes mosfet e DC Information mosfet e DC Initialize mosfet e DC Binn
484. ne of the standard setups and to enter a name for the copy of this setup By clicking Add the new setup will appear inside the list of setups It will use the same settings as defined in the standard setup from which it was created Adjust all the settings for this new setup according to your needs A newly created setup must be configured into a measurement set which in turn can be used to measure the devices Click Configuration gt Configure Measurement Setup or use the configure icon to open a window for creating a new measurement set or to add a newly created setup to the standard measurement sets Just click the desired setups to be added or use the Add button to create a new set Thus you are able to define measurement sets measuring data from different setups Transistor Device List Select Device List from the tree to enter the devices to be measured When creating a new project the device list contains predefined device names that you can simply overwrite with device names of your choice The device list table contains additional columns for each temperature you ve entered on the Temperature Setup folder Device List tree with entries for the devices to be measured 22 MOSFET Models 48 BSIM4_DC_CV _Measure 8 File Configuration Data Tools Help HaSb Fee txk BE Notes Temperature Setup Switch Matrix Device Definition Options Data af Transistor i a 7 ial A Measuremer c c C Aeasure um urn um
485. ng RGATEMOD O no gate resistance 1 constant gate resistance 2 variable gate Gate resistance model Page 8 8 resistance 3 two gate resistances overlap capacitance current will selector not pass through intrinsic input resistance RBODYMOD O no substrate resistance network 1 five substrate resistors are Substrate resistance Page 8 9 present network model selector TRNQSMOD O charge deficit NQS model is off 1 charge deficit NQS model is Transient Non Quasi Page 8 3 on Static NQS model selector ACNQSMOD 0 small signal AC charge deficit NQS model is off 1 small signal AC AC small signal Non Page 8 5 charge deficit NQS model is on Quasi Static model selector Note Page 8 X refers to the page numbers of the BSIM4 3 0 Manual from UC Berkeley 1 Related Topics RF Extract Notes mosfet RF Extract Information mosfet RF Extract mosfet RF Display mosfet RF Extract HTML mosfet RF Extract Options mosfet RF Extract Boundaries mosfet Back to Extraction of Parameters for the RF Models mosfet 115 MOSFET Models BSIM3v3 Characterization This section provides information on the following topics Whats New in BSIM3 Modeling Package mosfet Introduction to BSIM3 Model mosfet The Unified I V Model of BSIM3v3 mosfet Capacitance Model mosfet High Frequency Behavior mosfet Temperature Dependence mosfet Noise Model mosfet SPICE Model Parameters for BSIM3v3 mosfet Test structures fo
486. ntration of pocket tail cm 34 NPEXTW 1 0 width dependence of pocket tail heat ee o parameter width dependence of pocket tail LPEXT 1 00E 50 1E 50 10E 6 lextension length of pocket tail m VFBC 1 Er 0 8 flat band voltage V VBI 1 4 1 0 1 2 built in potential V KAPPA 3 9 dielectric constant for gate detectne dielectric constant for gate dielectric E EGO 1 1 1785 1 0 1 3 bandgap ati Ci O O O O O penne fe 25u bon 200 files dependence of bandgap Y K 1 po H n an dependence of bandgap eV K 2 TNOM 27 temperature selected as a nominal degC temperature value Saturation Velocity Parameters Parameter Default Range Range Description Unit Name min max K K a i velocity ae 1 VOVER 0 3 0 1 0 velocity overshoot effect cm VOVERP 0 3 0 l2 Leff dependence of velocity overshoot VTMP 0 2 0 1 0 temperature dependence of the saturation cm s velocity 1 Quantum Mechanical Effect Parameters Parameter Default Range Range max Description Unit Name min QME1 0 0 300n Vgs dependence of quantum mechanical m V effect 2A QME2 1 0 0 3 0 Vgs dependence of quantum mechanical V lee QME3 0 0 800p minimum Tox modification Im Poly Silicon Gate Depletion Effect Parameters Parameter Name Default Range min Range max Description Unit PGD1 0 0 50m strength of poly depletion effect vo PGD2 1 0 0 1 5 threshold voltage of poly depletion effect vo PGD3 0 8 0 1 0 Vds dependence
487. nts to lead to correct results Choose at least 5 to 7 data points otherwise the results will not be correct Folder All Diagrams Using this folder you can display different plots to be compared or used for optimization In contrast to the other folders of this window you should define a Plot Layout first If you select a 2x3 configuration for example you will get 6 empty plots inside the display area of the window Click on one of those empty plots open a menu by using the right mouse button and select Flexible Plot Configuration from this menu Now you can select a 58 MOSFET Models predefined plot type from the All Diagrams folder and choose the desired voltages axis settings temperature or devices to be displayed inside the selected plot Using another plot choose Transistor Capacitance gt C oxide from the menu below the right mouse button for example This gives you the ability to mix plot types and devices in any configuration you d like For details see the example provided in the following section There is the possibility to define plot headers to your needs Select a plot use the right mouse button context menu and choose Define Caption Enter the header you wish to be displayed above this plot You can copy plot definitions from one plot to another Choose the plot to be copied select Copy Plot Configuration from the context menu then choose the plot to be configured and select Paste Plot Configuration You are able
488. o Coo of width dependence for length ofset of width dependence for length offset m LWN Power of width Power of width dependence for length offset _ for length offset Coeff of length and width cross term for length eo E p Coefficient of Weff s gate dependence oe Coefficient of Weff s substrate dependence o A i resistance PCLM Channel length modulation coefficient 1 3 g porie PDIBLC1 First output resistance DIBL effet First output resistance DIBL effect o 0 39 PDIBLC2 O Second Second output resistance DIBL effect resistance DIBL effect 0 0086 PDIBLCB Body effect coefficient of output resistance DIBL effect DROUT L dependent coefficient of the DIBL effect in output resistance p PSCBE1 F First substrate current body effect coefficient 4 4 24E8 vin PSCBE2 Second substrate current body effect 1 0E 5 ae Gee denendone GFE vokge PVAG gt Gate Gate dependence of Early voltage i ast t s of Early voltage ALPHAO The first parameter of impact ionization oo ALPHA1 L Length dependent substrate current parameter O 0 1 ay BETAO The second parameter of impact ionization 30 Diode characteristic JS Source drain junction saturation density 1E 4 A m2 J SSW ls Side wall saturation current density 0 A m NJ le Emission coefficient of junction 1 ITH Diode ming curent limiting current oe Capacitance fe Serafin to io psn ar bottom junction capacitance per ce OE 4 m unit area CJSW Source
489. o enter the temperature value in Kelvin The DC Transistor fields in this folder enable you to set sweep values for gate and drain voltages respectively Enter Step values for the Output fields The purpose of this field is to define measurement of DC characteristics of multifinger transistors used for RF NWA measurements This step is necessary since the DC behavior of a multifinger transistor differs from that of a single finger transistor During DC measurement and extraction a single finger transistor is being used whereas a multifinger transistor is used in RF measurements to deliver sufficient drain currents for network analyzers to improve the measurement accuracy Actual transistor DC measurements are used to set start points for S parameters at low frequencies and control extraction at those points Note It is necessary to use the same values of start stop and step voltages for RF measurements as have been used for DC measurements This is because it might be difficult for the optimizer to find parameter optimums during extraction if the operating points differ in DC and RF measurements since DC values are used as starting points for RF extractions S parameter part of the Measurement Conditions folder 5 Parameters m Frequency Sweep Start Stop 1 Frequency 100 0MEG 20 00G Freg Points 51 Iv Lin Freq Points Decade fio Log Bias Conditions YD VG Linear Linear Start fo Start fo Step bs Step joas
490. od_T2 W5u0_L0u25 bsim4_for_ex N L Scale SA ref WPE ref 7 8 31 32 5 0 25 1 1 5 11 5 11 0 D 1 Mod_T2 W 5u0_LOu8_ bsim4_for_ex N L Scale SA ref WPE ref 9 10 31 32 50 8 1 1 6 11 5 11 0 D0 1 Mod_T2 W Ou25 L5u0 bsim4_for_ex N W Scale oA ref VYVPE ref 11 12 31 32 0 25 5 1 10 25 01 Mai 0 25 01 Mai 0 O 1 Mod_T2 WYOu4 L5u0_ bsim4_for_ex N W Scale SA ref VWPE ref 13 14 31 32 0 4 51 104 01 Aug 0 4 01 Aug 0 D0 1 You can edit the template to suit your specific needs e g dimensions device names and so on Import Data into the BSIM4 MOS Modeling Package After adapting the template to your project select File gt Import gt Import Wizard mdm The mdm Import Wizard window opens and the Model _DC_CV_Measure window Select File gt New from the wizard browse to the location where you want to store the project and enter a name for your project Select Create On the Temperature Setup folder enter TNOM in Kelvin and if used a temperature alias If you have data measured at other temperatures add those temperatures as well Next open the DC Transistor DUTs folder select the desired device list as well as the Basic data directory then enter the MDM_FILE_CONSTRUCTOR into the line at the bottom of the window see the following figure Don t forget to enter the correct mdm description in import files assignment Check the entries by clicking the Assignment icon P to check the input output assignment Correct if necess
491. odel shown above no changes are done in the BSIM3v3 3 0 model code itself This is the ultimate precondition for its use in a commercial circuit simulator that includes the BSIM3v3 3 0 model and makes it available to circuit design engineers The BSIM3v3 3 0 model already consists of a non quasi static model and an accurate capacitance model which makes it the ideal base for RF simulations However the description of the resistance behavior of a transistor is very poor In the BSIM3v3 3 0 model itself no gate resistance is included Due to the nature of the MOS transistor such a resistance cannot be seen in the DC operation region However looking at the real existing poly silicon gates of modern MOS devices there is a resistance which cannot be neglected in AC simulations This resistance Rgate has a major influence on the reflection coefficient S11 of an input signal to the MOS transistor as demonstrated in the following figure It should be noted that the parameter R in this high frequency model is used to fit the gate input reflection of the MOS transistor Therefore it is very likely that R has a different gate value as the measured sheet resistance of the poly Si gate during process characterization on PCMs using for instance a van der Pauw test structure The second enhancement in the RF BSIM3v3 3 0 macro model is a resistance network for the substrate resistance which is described by four resistors Rapp RBPS RBDB and
492. odeling A flag is used to switch between different resistance settings CORSRD This flag can have the following values that affect resistance modeling of RS and RD as is shown in the following table 248 MOSFET Models CORSRD value Drift region resistance modeling valid only if Rg Rp 0 0 Rs and Rp are not considered 1 Rs Rp considered as internal HiSIM resistances 1 Rs Rp considered as external HiSIM resistances 2o Ro Rp considered using an analytical solution a Ro RpD considered using both internal and analytical solution This is the default case The CorSRD flag provides a few more options as shown below Options Selected by CORSRD Yes CORSRD 0 No CORSRD 1 CORSRD 1 or 3 HiSIM iteration Circuit simulator generates nodes for RS and RD Vosen Vos 1x Re Vasor Vd x Rs Rarirt Vbser Vb en Ix R Surfacr Potential Calculation Device Characteristic Calculation No CORSRD 2 or3 Yes has fiso 1 liso Ral Vas Be careful when using the CORSRD flag since more parameters are taken into account depending on the CoRSRD flag value There is the possibility that some parameters may not be considered if others are set to zero For instance the equation to calculate the parameter RDVD uses a multiplication of parameters among others as shown here RDVD x LDRIFT1 RDICT1 x LDRIFT2 RDICT2 x saa If either LDRIFT1 an
493. of poly depletion effect PGD4 0 0 3 0 Lgate dependence of poly depletion effect Short Channel Effect Parameters 238 MOSFET Models Parameter Default Range Range Description Unit Name min max PARL2 l10n 0 50n depletion width of channel contact junction im SCc1 1 0 0 200 magnitude of short channel effect E ls SC2 1 0 0 50 Vds dependence of short channel effect v 1 n f i m i dependence of short channel effect e V 1 sca fe D SS ls SCP1 1 0 0 50 magnitude of short channel effect due to pocket ls SCP2 0 1 0 50 Vds dependence of short channel due to pocket VA 14 SCP3 0 0 1m Vbs dependence of short channel effect due to o pocket 1A SCP21 0 0 5 0 short channel effect modification for small Vds Vv SCP22 0 0 50m short channel effect modification for small Vds v4 Bsz b9 lbs ho body coefficient modification by impurity profile voo o Mobility Parameters Parameter Default el hla Description ual Name mi MUECBO 100E3 coulomb scattering A ha IA MUECB1 10E3 coulomb scattering aA a i MUEPHO 0 3 0 25 0 3 p honon scattering p MUEPH1 25E3 NMOS 30E3 phonon scattering 9E3 PMOS a ae 1 MUETMP 1 5 a dependence of phonon z scattering MUEPHL 0 length dependence of phonon mobility reduction MUEPLP 1 0 length dependence of phonon mobility reduction MUESRO 2 0 1 8 l2 2 surface roughness scattering p MUESR1 1E15 1E14 1E16 surface roughness scattering wa d 1 MUESRL length dependenc
494. of the scaling rules For devices on the L and W arrays respectively 1 l 1 1 eae cape rR W eff et or eff eft R For the other devices 1 ft l a I 7 Rett eee Wor 359 MOSFET Models Optimizing MOS Model 9 The steps below represent the basic maxiset optimization sequence 1 Linear lig Vys data Vp 0V Optimize VTOR SLVTO SL2VTO SWVTO BETSQ THEIR SLTHE1R and SWTHE1 Varying Vp Optimize KOR SLKO SWKO KR SLK SWK VSBXR SLVSBX SWVSBX THE2R SLTHE2R and SWTHE2 Subthreshold Ijs Vas data Vop OV Optimize GAMOOR SLGAMOO MOR SLMO ZET1R and SLZET1 Saturation ggs Vy data Vop OV Optimize GAM1R SLGAM1 SWGAM1 ALPR SLALP SWALP and VPR Saturation I Vgs data Vo OV Optimize THE3R SLTHE3R and SWTHES3 Substrate current I ub Vas data Vop OV Optimize A1R SLA1 SWA1 A2R SLA2 SWA2 A3R SLA3 and SWA3 Subthreshold Lie Vas data Varying V Optimize VSBTR and SLVSBT Optimization Transforms and Macros The transforms described in this section are available with the DUT extract full_extract The full_extract transform controls the optimization sequence for miniset extraction It can be found under the setup single_ext 1 Initialize parameters par_init 2 Linear region fitting at Vbs 0 in_opt1 3 Linear region fitting at all Vbs in_opt2 for 2 k factor model or in_opt3 for 1 k factor model 4
495. oise coefficient 0 577 RNOIB Thermal noise coefficient 0 37 Stress Effect Modeling Stress Effect Model Parameters Parameter Description Default Unit Value SA Instance parameter Distance between OD edge to poly Si from one side see 0 0 m MOSFET device geometry using a shallow trench isolation scheme mosfet If not given or lt 0 stress effect will be turned off SB Instance parameter Distance between OD edge to poly Si from the other side 0 0 m see MOSFET device geometry using a shallow trench isolation scheme mosfet If not given or 0 stress effect will be turned off SD Instance parameter Distance between neighboring fingers see MOSFET device 0 0 m geometry using a shallow trench isolation scheme mosfet For NF gt 1 if not given or lt 0 stress effect will be turned off SAREF Reference distance between OD edge to poly Si from one side 1E 6 m SBREF Reference distance between OD edge to poly Si from the other side 1E 6 m WLOD Width parameter for stress effect 0 0 m KUO stress effect mobility degradation enhancement coefficient 0 0 1 m KVSAT Stress effect saturation velocity degradation enhancement parameter 0 0 1 lt KVSAT lt 1 TKUO KUO temperature coefficient 0 0 LKUO KUO length dependence 0 0 WKUO KUO width dependence 0 0 PKUO KUO cross term dependence 0 0 LLODKUO iLength parameter for UO stress effect gt 0 0 0 WLODKUO width parameter for UO stress effect gt 0 0 0 KVTHO stress effect threshold shift pa
496. ollowing sub chapters explain each type of capacitance and its implementation in the BSIMSOI model Different Parts of the Capacitance of a SOI MOS Transistor 302 MOSFET Models Gate fringing capacitance Ce Poly Gate idewall Source to Substrate capacitance Source and Drain Capacitance The source drain body junction capacitance consists of only one component in a SOI MOSFET structure since source or drain are contacted to the silicon film only at the gate side The bottom of the source drain region is on top of the buried oxide as can be seen in Different Parts of the Capacitance of a SOI MOS Transistor Therefore a bottom area Capacitance is present in SOI MOS transistors which actually is a MOS capacitor since it s dielectric is the buried oxide The calculation of this capacitance will be done in the next sub chapter The junction capacitance is voltage dependent and is calculated as is described inside the BSIMSOI4 manual Extrinsic Capacitance As mentioned in the introduction to this chapter the extrinsic capacitance of a MOS transistor consists of the following five components The outer fringing capacitance CF between polysilicon gate and the source drain The overlap capacitance CGSO between the gate and the heavily doped source drain regions The overlap capacitance CGSOL between the gate and the lightly doped source drain regions The substrate to source drain sidewall capacitance Cessw Cesdw T
497. oltage source in one measurement and another one for the next measurement The values are shown for reference only inside the different measurements To the right of the compliance definition area there is a field to be activated if you would like to use the Safe Operation Area SOA limiting the power delivered by the SMU to the drain of the DUT There are choices If you select one of the measurement setups inside the tree the folder changes to reflect the measurement conditions valid for the selected setup 9 Setups not assigned to a Measurement Set will be deleted on opening a project The same is valid for Measurement Sets not used To assign a setup to a Measurement Set select Measurements from the tree Now you can configure the measurement sets by clicking the icon P or selecting Configuration gt Configure Measurement Set The Configure Measurement Set window appears meye gt sen Configure Measurement Sets idvd_vbmin O O O D uiecravgansians Co cae Add your setups to predefined measurement sets or define your own sets As you will notice the default settings are greyed out they cannot be changed However there is an unlock field where you can remove the locking You will be noted that devices cannot be used for extraction if idvd and idvg measurements are not performed 17 MOSFET Models You are able to change the order of execution of the measurements by clicking Define Order and move
498. oltages is necessary to establish the gate biases for the saturation and subthreshold measurements The measure_vt setup contains the following transforms id_ fit estimates Vt It looks for the point of maximum transconductance fits a straight line in the neighborhood of this point and estimates the threshold voltage from the intercept of this line with the Vgs axis The output of this transform is the calculated current based on the resulting transconductance and threshold voltage for display on the vt_fit plot calc_vt invokes d_fit for each of three Ids Vgs curves measured in the setup This transform also rounds the Vt values to the nearest 10mvV mm9_ids calls the MM9 transform to evaluate the model current copy_sim_to_meas Copies the current generated by the MM9 transform into the measured array It is used for making sample measured data It uses the MM9_COPY C transform which is necessary to enable data to be copied into a measured array The variables table of measure_vt contains two quantities VT_FIT and CURVE where CURVE points to the curve that ca c_vt is working on at a given time and V7_FIT is the threshold voltage associated with this curve dutx idvg performs the measurements required for extraction of the linear region parameters The idvg setup contains the following transforms The idvg setup contains the following transforms mm9_ids calls the MM9 transform to evaluate the model current set_dimensions Sets the
499. on current of the drain source body diodes Thermal resistance Thermal capacity of a SOIMOS transistor Threshold Voltage Carrier Mobility Saturation velocity and series resistance Temperature dependency of threshold voltage carrier mobility saturation velocity and series resistance are modeled the same way as in BSIM3v3 Current Components of Drain Source Body Diodes The temperature dependency of the drain source body diode current components is different from BSIM3v3 Details are given on page 5 1 of the BSIMSOI4 manual see Reference 4 Self Heating Self heating in SOI is more important than in bulk since the thermal conductivity of silicon dioxide is about two orders of magnitude lower than that of silicon It may degrade the carrier mobility increase the junction leakage enhance the impact ionization rate and therefore affect the output characteristics of floating body SOI devices The self heating of a SOIMOS transistor is modeled using auxiliary components Rth and Cth as thermal resistance and thermal capacity if the self heating model selector SHMOD is set to ON See page 5 3 of the BSIMSOI4 manual for details Reference 4 Noise Model The flicker and thermal noise model implemented in BSIMSOI is compatible to the BSIM4 noise model To account for SOI specific noise sources shot noise from gate tunneling and thermal noise due to gate resistance has been implemented as is described in Chapter 8 of the BSIMSOI4 manual
500. on of the device in the isolated region Influence of stress on mobility and saturation velocity has been known since the 0 13 um technology BSIM4 References mosfet 1 For the named reasons BSIM4 considers the influence of stress on e mobility e velocity saturation e threshold voltage e body effect e DIBL effect Mobility related dependence of device performance is induced through band structure modification Doping profile variation results in Vth dependence of the stress effect Both effects follow the same 1 LOD trend but have different L and W scaling influence By modifying some parameters in the BSIM model a phenomenological model has been implemented The model assumes mobility relative change to be proportional to stress distribution MOSFET device geometry using a shallow trench isolation scheme Trench isolation Ww The figure above shows a typical MOSFET layout surrounded by shallow trench isolation SA SB are the distances between trench isolation edge to Gate PolySi from one and from the other side respectively SD is the distance between neighboring fingers of the device The Length of Oxide Definition LOD is expressed through the following equation LOD SA SB N L N 1 SD 2D simulation shows that stress distribution can be expressed by a simple function of SA and SB To cover doping profile changes in devices with different LOD VthO K2 and ETAO are modified The total LOD effect for multiple finge
501. on of voltage lt parameter ourve S the of Starting points 4 wobes oai SI tins ila mm el es eeccbooss csocess ce Se mime mw E i E i I i i i i i i odie i eee eet i a i idia 22 S qQuaap g eu TT Shes eos Be eran CE 0AJ veda eee Se ee eee eens 22 W queap S Gew e Extraction of the gate resistance from the input reflection coefficient S11 Input reflection coefficient S11 NF inger 16 WF inger 1Gum L 62 25um at aaaea aea aaaeaii n aaaea tele an Soe ee Cen eee we See ee SSeS Sees OSES ESSE S SSS ESS S SESE SESE SEES 1 wow ww ww eb ww ww ww ew ewww eee eee ntd Ii S qwaap S I W gwaeap S Freq 20 GHz Output reflection coefficient S22 309 MOSFET Models L 25um Wr inger 10um Nfinger 16 S deemb M 22 S deemb S 22 e Verification of the gate drain overlap capacitance for higher frequencies e If no good fit could be found additional peripheral elements like inductors at drain gate or source should be added in a further sub circuit Back to BSIMSOI4 Characterization mosfet 310 MOSFET Models Test Structures for SOI MOSFET A very important prerequisite for a proper model parameter extraction is the selection of appropriate test structures The following subsections describe the necessary test structures for proper determination of CV and DC model parameters A very detail
502. on to the HiSIM2 model developed by the University of Hiroshima together with the STARC consortium Here STARC stands for Semiconductor Technology Academic Research Center co funded by major Japanese semiconductor companies in 1995 The main differences between a conventional MOSFET and a high voltage MOSFET arises from the drift region introduced to enhance the sustainability to high voltages which is shown in the following cross section of a HV MOSFET Larift i Drain lt gt LoverLD Drift Region n Nover Accurate modeling of the drift region is a major task in HV MOSFET modeling This region not only affects the resistance through additional charges inside the drift region but the capacitances are affected as well The basic equations of the HiSIM2 model are used for HiSIM_HV also and complete with additional equations to model the drift region influence The HV model can be used for simulation of symmetrical as well as asymmetrical device structure A flag is introduced to switch from the symmetric to the asymmetric device structure COSYM 0 refers to the asymmetric LDMOS structure and cosym 1 to the symmetric HVMOS structure The following figure shows the parameter extraction approach using the COSYM parameter HVMOS symmetrical All structural parameters values of drain side are copied to those of source side LDMOS asymmetrical Structural parameters have to be determined for both source and drain
503. onPEL_default If empty no region PEL code is used no user defined code can be edited too In the PEL code the following variables can be used PlotO_x1 First x value of PlotO plot specified in variable F_UsedPlot 0 PlotO_x2 Second x value of Plot0O PlotO_y1 First y value of PlotO PlotO_y2 Second y value of Plot0O Ploti_xi Ploti_x2 Ploti_y1 Plot1_y2 Ploti is specified in variable F_UsedPlot 1 Plot _x1 Plot _x2 Plot _y1 Plot _ y2 Plot is specified in variable F_UsedPlot Example F_RegionPEL_default PlotO_x1 0 PlotO_x2 0 9 VTHO PlotO_y1 1le 12 PlotO_y2 max abs id m From the content of the variable F_RegionPEL_default a transform will be created 95 MOSFET Models This transform is copied into the setup which is specified in the variable F_Setup So if no path is used the PEL code is using the local variables inputs outputs parameters etc of the setup F_Setup 2 1 7 Attachments initializing Available content of F_DataSourceType list Transistor dc_idvg C Junction c_bd_area c_bd_perim C_bd_perim_gate c_bs_area c_bs_perim cC_bs_perim_gate C Oxide C_oxide C Overlap C_g_ds C_g_dsb C Intrinsic c_d_g Diode di_bs_area di_bs_perim di_bs_perim_gate di_bd_area di_bd_perim di_bd_perim_gate Available content of F_DataSourceDefault_Func list Empty disables this selection for default selection All DUTs will
504. ondition is fixed and the start point is depending on the threshold voltage of the reference sweep If this sweep is selected the setup must not have any other sweeps e g vb vs because the IC CAP rectangular data format does not support it The referenced sweep must include the vb vs ve value of the actual sweep which is defined to be a constant value In the case of vd 1st sweep the threshold voltages in the reference sweep at all vd values are taken and a mean value is generated Furthermore it is necessary to specify a resolution value in order to send reasonable voltage values to a measuring instrument Taking this into account the effective start and step values are calculated according to the following formulas _ l stop th I offset V step raw No Pts 1 y iy 5 f I step raw a resolution J flaon step resolution resolution V a No Pts 1 V start st J step The following table shows the minimum source configuration It is now possible to select an output from each source for example ig ib id is The source s output current is in bold letters to indicate that it was used as the minimum required output Minimum measurement setups Name Sweep order Mode voltage to be swept Fixed settings Default settings Options idvg 1 vg LIN 2 vb LIN LIST CON 3 vd LIN LIST CON 4 vs CON LIN LIST idvd 1 vd LIN 2 vg LIN LIST CON LIN f Vth 3 vb LIN LIST CON 4 vs CON LIN LIST W
505. onent in circuits you design using MDS It will predict large signal device operation over a range of bias points and loading conditions The file generated by the modeling process for interface with MDS is called State mds You need to change the name to one that will identify the device under test since every Agilent RootMOS model file is initially named State mds If you chose not to perform a verification you may already have changed the filename using the dialog box presented before the model_generator transform If not you can change the filename now in UNIX and store the file as follows Storing the Model 1 Use the UNIX directory you created at the beginning of the procedure when you first opened the model file 2 From the IC CAP Main window select File gt Save As 3 A dialog box is displayed Select the desired File Type for example md for a complete model 4 Select a new filename that associates this model with the device 5 Use the UNIX cp command to copy the file State mds to the new filename including the path name of the designated directory Select OK This completes the example Agilent Root MOSFET measurement and model generation procedure 342 MOSFET Models MOS Model 9 Characterization This section provides information on the following topics e Introduction to MOS Model 9 mosfet e The MM9 Model File mosfet e Parameter Extraction mosfet e Optimizing MOS Model 9 mosfet e The JUNCA
506. ong Wide device followed by extraction of local parameters for the rest of the devices with max length Then there is a global parameter extraction optimization step involving all devices of max length The next step uses the Short Wide device same width but shortest length to extract local parameters and so on The following figure is a graphical representation of the extraction sequence The numbers show the extraction order the circles and squares with blue background or shaded in a black and white representation and blue numbers are local parameter extraction steps the ones with a red frame and red numbers are global parameter extraction steps Flow of Extraction as programmed inside the PSP Toolkit Wim 4 5 10 5u 240n 150n 90n 65n 45n 60n 90n 150n 240n 5u L m This procedure was enhanced since the one recommended by the model developers needs a totally regular arrangement of devices a requirement usually not given in practice Therefore the PSP Modeling Package uses a somewhat different approach local parameters that do not have for example a width dependency will be computed from global parameters and will not be extracted for the local model again The following table should clarify the extraction sequence as programmed for the standard extraction flow This table shows due to limited space a reduced number of parameters only Note Inside the extraction flow window some parameters shown have an x
507. ons are used e For SOIMOD 3 BSIMSOI selects the operation mode for the user based on the estimated value of VbsO at phi 2FB bias independent VbsOt o If VosOt gt VbsOfd BSIMSOI is in the ideal FD mode SoiMod 2 o If VosOt lt VbsO0pd BSIMSOI is in the BSIMPD mode SoiMod 0 o Otherwise BSIMSOI operates under SoiMod 1 Both Vos0fd and Vbs0pd are model parameters Note With SOIMOD set to 1 or 2 the default model equations BSIMPD model are used with the enhancements of the FD module In CV and IV formulations the back gate effect is taken into account SOI specific effects such as body contact parasitic bipolar and self heating are implemented For this reason a lot of the physical effects are common in bulk and SOI MOSFET s and the BSIM3v3 model for bulk MOSFET devices could be used The common physical effects of bulk and SOI devices are e Short channel effect e Poly depletion e Velocity saturation e DIBL in sub threshold and output resistance e Mobility degradation e Narrow width effect e Source drain series resistance BSIMSOI always uses a floating body Few proposed FD SOI models use a body potential derived from diode leakage and impact ionization currents The body therefore is not floating in those models Models of this type can be made simpler than BSIMSOI but cannot model the possible transition between PD and FD as well as the frequency or time dependent kink effect Reference 4 In BSI
508. ons are connected isolated S D diffusion resistance and contact model selector specifying the end S D contact type point wide or merged and how S D parasitic resistance is computed no S D diffusion resistance Well Proximity Effect Model no well proximity Underlined values in bold italics are defaults underlined comments in italics in brackets are valid for default model selector values Back to BSIM4 Characterization mosfet 221 MOSFET Models HiISIM2 Characterization This section provides information on the following topics e Introduction to HiSIM2 Characterization mosfet e Modeled Device Characteristics of the HiSIM2 model mosfet e SPICE Model Parameters for the HiSIM2 model mosfet e RF Circuit used for HiSIM2 mosfet References 1 HiSIM Web Site http home hiroshima u ac jp usdl HiSIM html 2 H J Mattausch et al Accuracy and Speed Performance of HiSIM Versions 231 and 240 Compact Modeling for CMOS Nano Technologies MOS AK ESSDERC ESSCIRC Workshop Munich Germany September 14th 2007 3 M Miura Mattausch et al HiSIM Self Consistent Surface Potential MOS Model Valid Down to Sub 100nm Technologies Technical Proceedings of the 2002 International Conference on Modeling and Simulation of Microsystems Vol 1 Nanotech 2002 P 678 681 NSTI Nano Science and Technology Institute 2002 Cambridge Massachusetts USA also to be found at http www nsti org procs MSM2002 13 T41 03
509. ope are dB GHz the default value is 0 000 A network analyzer message will caution you that the correction may be invalid but this can be ignored 11 Set Fast Sweep RAMP to No because the network analyzer is in stepped sweep mode set earlier in the calibration procedure 12 Sweep Time applies only to ramp sweep mode therefore the value set is irrelevant for a stepped sweep measurement 13 Set Use Fast CW to Yes to minimize repeated switching between the test set ports 14 Trim Sweep is set to 0 This feature is used only in ramp sweep mode 15 Set Avg Factor to the same averaging factor you set in the calibration The default value is 256 but as little as 16 may be adequate 16 Set Cal Type SHN to H for hardware 17 Set Cal Set No to the cal set number in the analyzer where you stored your swept calibration so that IC CAP can find the calibration 18 Soft Cal Sequence refers to the sequence of measurements of the cal standard devices load open short thru 19 Delay for Timeouts can generally be set to the default value of 0 000 20 Set Use Linear List to No because this is a standard stepped frequency measurement 21 Init Command sets the instrument to a mode not supported by other fields in this table It is not used in this model Leave the field blank 22 Close the instrument options window Then return to the modeling procedure For an Agilent 8753 or 8720 based system You will need to set the instrument st
510. oped source gate region overlap capacitance Light doped drain gate region overlap capacitance Coefficient for lightly doped region overlap capacitance fringing field Fringing field capacitance Constant term for the short channel model Exponential term for the short channel model MOSFET Models 0 1E 10 defaults to source side value 0 5 defaults to source side value 0 7 defaults to source side value 1E 12 1 1 calculated see Appendix B of the BSIMSOI4 manual calculated see Appendix B of the BSIMSOI4 manual 0 0 3 0 calculated see Appendix B of the BSIMSOI4 manual calculated the same way as CGSO 0 0 0 0 0 0 6 calculated see Appendix B of the BSIMSOI4 manual 0 1E 7 0 0 Length offset fitting parameter for gate charge from CV LINT Length offset fitting parameter for body charge from CV Length offset fitting parameter for backgate charge from CV Width offset fitting parameter from CV Threshold voltage adjust for CV Scaling factor for body charge Exponential coefficient for charge thickness in capmod 3 for accumulation and depletion regions Coefficient for the gate bias dependent surface potential Process Related Parameters Table Process Related Parameters 0 0 WINT 1 0 1 0 15 0 318 F m2 F m2 F m F m F m F m F m F m F m F m m V yi 2 MOSFET Models Value TOX Gate oxide thickness 1E 8 im TOXM Gate oxide thickness used in extract
511. or add to The program appends it as a label to any graphical outputs to identify the device It includes a device ID string and any additional information you choose to add to graphs when they are plotted icplotnumbers This is an internal file used by the program to generate a graphical interface It is related to the Max_num and Max_row messages that appear in the variable table of the main DUT and in the UNIX window at the end of the data acquisition While these parameters are irrelevant to user interaction with the program they are essential to its function and they must appear on screen Do not change this file Measured data This is the raw measured S parameter data as a function of bias and frequency produced by the create_mdl data acquisition process Para data This is the S parameter vs frequency data with the device in an unbiased condition used by the program to calculate parasitic resistance and inductance values State data This file is used by the program in plotting nonlinear functions such as Qg and Qd Do not change this file State mds This is the model file used by the Agilent RF and Microwave Design System MDS in a circuit simulation It is also used in verifying the model and needs to retain the name State mds in the verification process in order to maintain the MNS simulator link However since every Agilent RootMOS model initially has this name you change the name to identify the device either when you execute
512. or the length times width dependence of CLM pre factor Coefficient for the geometry independent part of CLM enhancement factor above threshold Coefficient for the length dependence of CLM enhancement factor above threshold Coefficient for the width dependence of CLM enhancement factor above threshold Coefficient for the length times width dependence of CLM enhancement factor above threshold Coefficient for the geometry independent part of CLM enhancement factor below threshold Coefficient for the length dependence of CLM enhancement factor below threshold Coefficient for the width dependence of CLM enhancement factor below threshold Coefficient for the length times width dependence of CLM enhancement factor below threshold Coefficient for the geometry independent part of CLM logarithmic dependence parameter Coefficient for the geometry independent part of V 1 V 1 V 1 V 1 V 1 V 1 V 1 V 1 V 1 V 1 V 1 V 1 1 281 PLA1 PWA1 PLWA1 POA2 POSTA2 POA3 PLA3 PWA3 PLWA3 POA4 PLA4 PWA4 PLWA4 Gate Current Parameters POGCO POIGINV PLIGINV PWIGINV PLWIGINV POIGOV PLIGOV PWIGOV PLWIGOV POSTIG POGC2 POGC3 POCHIB Gate Induced Drain Leakage GIDL Parameters POAGIDL PLAGIDL PWAGIDL PLWAGIDL POBGIDL POSTBGIDL POCGIDL Charge Model Parameters POCOX PLCOX PWCOX PLWCOX POCGOV MOSFET Models imp
513. ormance Select the s_vgvdf setup For the vd input Set To Mode V Compliance no greater than the maximum breakdown current value for the device Sweep Type LIN Sweep Order 2 Start 0 0 Stop at or below the upper limit of the device s normal operating range 1 of Points 2 or 3 is sufficient to display the data while giving fast results For the vg input Set To Mode V Compliance no greater than the maximum allowable gate current value Sweep Type LIN Sweep Order 3 Start Stop of to measure at two or three different bias points in a range from approximately Points Vgs Vthreshold to Vgs 3 or 4V Note The vd and vg ranges apply to an NMOS device Recognize that for a PMOS device both vd Start and vg Start are negative and Stop is 0 000 For the freq input Set To Mode F To Node From Node Unit Compliance Sweep Type LIN Sweep Order 1 Start Stop of correspond with the broadband frequency list calibration you performed Points Note If you set a MHz value write MEG in full Measuring and Plotting Note Before performing the S parameter measurements manually take the network analyzer out of hold sweep mode Press STIMULUS gt MENU gt MORE gt CONTINUAL on an Agilent 8510 or MENU gt TRIGGER MENU gt CONTINUOUS on an Agilent 8753 to initiate continuous sweep 1 2 3 From the Plots tab select Display All Two S parameter plots are displayed Select Measure Simulate
514. ormation mosfet 1 for more information Only the basic principles are described here To ensure charge conservation terminal charges instead of the terminal voltages are used as state variables The terminal charges Qg Qpr Qs and Q are the charges associated with the gate bulk source and drain The gate charge is comprised of mirror charges from 3 components e The channel minority inversion charge Qiny e The channel majority accumulation charge Qcc e The substrate fixed charge Q ub The accumulation charge and the substrate charge are associated with the substrate node while the channel charge comes from the source and drain nodes i 0 0 0 2 sub inv acc 0 O b sub Sacc O in Qst Qd The inversion charges are supplied from the source and drain electrodes The ratio of Q and Q is the charge partitioning ratio Existing charge partitioning schemes are 0 100 50 50 and 40 60 given by the model parameter XPART O 0 5 and 1 which are the ratios of Qy to Q in the saturation region From these four terminal charges 9 transcapacitances C terminal voltage are calculated inside the BSIM3 model as partial derivatives with respect to the voltages Vb Vap and V sb The abbreviation can be interpreted as C a i ggb oV Partial derivatives of Q Qu Q T gt C bgb Qu gt 8 Q Qu gt C bdb ap a Q qo amp rT FS C
515. osfet for details 48 Related Topics RF Notes mosfet RF Measurement Conditions mosfet De embedding mosfet DUTs mosfet Back to RF Measurement mosfet MOSFET Models 49 MOSFET Models Extraction of DC CV Parameters Extraction of the complete BSIM3 BSIM4 or PSP model parameters is done using two different modules There is a module inside each Modeling Package for extraction of DC CV parameters and a module for RF parameter extraction Note The RF extraction module needs start values for some parameters of a given process Usually those start values are taken from the DC CV extraction process Therefore you should extract DC CV parameters first The following figure shows the GUI used for extraction purposes You can see the folders for the tasks during the extraction process Again ordered from left to right are folders for Notes for measurement Information and to Initialize the extraction process The next folders are used for Binning to Extract parameters from measurement data to create a report in HTML format for publishing the parameters extracted together with some graphics of simulations using the parameters extracted and to set some Options and Boundaries for the parameters to be extracted GUI for the Parameter Extraction Process sanBSIM4_DC_C _Extract 7 l x File Initialize Binning Extract Plots HTML Options Boundaries Help anh ey gt ge n i E af 5 FA F eB
516. ou are ready to begin measurement and extraction operations Note P channel and N channel MOS extractions are handled the same pmos2 mdl or pmos3 mdl files are used for P channel extractions nmos2 md and nmos3 mdl files are used for N channel extractions 2 Select the DUT large Enter the values for L and W To include the effect of WD 378 MOSFET Models enter the following expression for W lt value gt 2 WD where value is the drawn width and WD is defined as a model variable 3 In Macros select init_parameters Enter the values for TOX XJ LD and RS Default values can be used by simply choosing OK in each dialog box 4 Select the idvg setup and issue the Measure command 5 Repeat these steps for narrow idvg short idvg and short idvd To perform DC parameter extractions 1 Select large idvg Select the transform extract and execute the selection to extract the LEVEL 2 classical parameters 2 Repeat this procedure for narrow idvg short idvg and short idvd All DC model parameters have now been extracted and their values are listed in Model Parameters Notes on DC Parameter Extraction These procedures assume that the large device is large enough to make small geometry effects irrelevant This condition exists when the device geometries are much larger than LD and WD For a typical process 50 50 microns should be sufficient To improve accuracy enter the approximate values of LD and WD in Model Param
517. ous data and transforms used during quick extraction The store setup contains the following inputs and outputs index An input definition used to set up array sizes vdsids An array containing the drain voltage offsets to be used by MM9_SAT_EXT for Ids measurements vgsids An array containing the gate voltages to be used by MM9_SAT_EXT for Ids measurements vdsgds An array containing the drain voltage offsets to be used by MM9_SAT_EXT for gds measurements vgsgds An array containing the gate voltages to be used by MM9_SAT_EXT for gds measurements The store setup contains the following transforms ideal_parameters used to copy the present miniset parameters into the transform array restore_ideal_parameters used to set the miniset parameters to the values stored in the array deal_parameters working_parameters used to copy the present miniset parameters into the transform array restore_working_parameters used to set the miniset parameters to the values stored in the array print_par a call to MM9_SAVE_SPARS that appends the list of miniset variables to the file whose name is held in the model variable GEOMFILE quick_extraction_setup used to specify the quick extraction setup details including options and bias voltages It can be used as an alternative to entering these details from the keyboard You can make multiple copies of this transform with different names to store the setup information for frequently used processes The setups in
518. oximate percentage of completion amp Caution Do not perform data acquisition more than once This will write over the existing data and will use more time and memory 3 If you do attempt to perform data acquisition after the measurement has already 337 MOSFET Models been done a dialog box will alert you that a measurement file exists You then have several choices If you do not need the data in the current file you can select OK or Return to overwrite it Or you can abort your new measurement by selecting Cancel Or if you wish to save the measured data and perform another data acquisition go to a UNIX window change directories if necessary find the file Measured data and rename it with another appropriate name then continue with the data acquisition Ignore this message if it occurs CAUTION CALSET X STATE MAY BE INVALID When the process is complete a message similar to the following is shown in the UNIX window up INITIAL Extraction Results Max_num 66 00 Max_row 49 00 Done The numbers are part of the internal function of the program and irrelevant in user interaction with the program They are associated with the maximum number of points for a given Vgs and the number of Vgs steps Plotting the Measured Data The plots in the create_mdl setup provide graphical outputs of the data acquisition and model generation Most of the plots are of data measured in the main data acquisition However Qg a
519. pacitances first measure capacitance against voltage on two different size Capacitors Then execute the extraction command using two setups cjdarea and cjdperimeter Execute cjdarea on a square shaped capacitance with a small sidewall to bottom ratio and cjdperimeter on a long narrow junction with a large sidewall to bottom ratio Each p n junction should be reverse biased when measured Extraction is performed by the MOSCV_total_cap function The parameters CJ MJ CJISW MJSW and PB are calculated from a combination of the two measurements Before running the extraction specify the area and perimeter of the capacitance Enter these numbers by executing the init_cap_parameters macro This sets the variables defined at the model level for the area and perimeter of the two DUTs The parameters AD or AS area and PD or PS perimeter in the cbd1 and cbd2 DUTs are set by these variables Simulating To simulate any individual setup choose Simulate with an active setup Simulations can be performed in any order once all of the model parameters have been extracted IC CAP provides a special function MOSCVmodCBD to speed up capacitance simulation in the cbd1 and cbd2 DUTs This function models the simple pn junction capacitance and provides a fast simulation of the CBD capacitance Use this function to execute a simulation by specifying the transform calc_mos_cbd_model in the setups for the two DUTs and Execute the Transform rather than issuing
520. perature Global Optimizations STI Stress Effect Well Proximity Effect Finetuning New Main Group ZAE New Group Local Capacitance Cgg 4 4 E E3 E3 4 E E E3 E 4 4 ce CH ta Local Long Wide ta ta ta E ta ta FA Cee SS ee Local Length Dependence Wide Local Long Width Dependence Local Length Width Dependence PSP Scale Parameters Local Short Wide Local Short Width Dependence Binning he A A a T Pi Global Factory Flow me Reset Parameters and Results H Capacitance Diode Transistor Temperature la Save Parameters New Default Flow K Reset Parameters and Results Capacitance Diode Transistor Temperature la Save Parameters Local to Global Factory Flow m ARNE E a If you try to add this function to the Capacitance Overlap extraction step you will get an error message Error message when trying to insert a function into a group it does not belong to e PSP_DC_CV_Extract 10 Ki B G oe S HTML d Options Boundaries Edit Global Binning Parameter Import Model Parameter Set 3 Capacitanc Jk Capactanc Export Model Parameter Set d Diode Export Extracted Deck Temperature Failure Log H ell Sava Parimate manent neteninrrcacnniarmin _ Follow Extraction Flow Configuration Wizard Selected Extraction Step
521. ple is copied Path c Agilent ICCAP_201 1_04 bin Projects in Path Project Explanation Copy and Open 4 In the Copy Example Project dialog box select an example project to be loaded from the Examples list 5 Specify a Path where the selected example project needs to be copied The selected example is loaded in the Model window Each Modeling Package contains example files for DC and RF Projects As the example model parameter files are copied to a directory the original files are not overwritten Therefore you can test with every IC CAP function that is implemented without modifying the original files 10 MOSFET Models Notes e Ensure that you have write permissions for the directory where you want to copy the example project e Files with same name in the target directory are overwritten If files with the same name exist you will be prompted before they are overwritten See Also Using the MOS Modeling Packages mosfet Data Structure in MOS Modeling Packages mosfet DC and CV Measurement mosfet RF Measurement mosfet Extraction of DC and CV Parameters mosfet Extraction of Parameters for the RF Models mosfet 1 MOSFET Models DC and CV Measurement This section provides information on the DC and CV measurement of MOS Model and other necessary measurements of your devices It provides information on features of the MOS Modeling Packages and how to use the Model gr
522. r CALC LSOURCE 0 1p aeccraicieec a aie SUBSi rete Nenwork sas seo Sse S ease SaaS Se See Sear SS ees Pa ene Diodes are for n type MOS transistors echo Djdb_area 12 10 bsim_diode_area AREA Sdpar x_rf_transistor AD 10e 12 echo Djdb_perim 12 10 bsim_diode_perim AREA Sdpar x_rf_transistor PD 22e 6 echo Djsb_area 32 30 bsim_diode_area AREA Sdpar x_rf_transistor AS 10e 12 echo Djsb_perim 32 30 bsim_diode_perim AREA Sdpar x_rf_transistor PS 22e 6 echo RBDB 12 40 Sdpar CALC RBDB 100 152 MOSFET Models echo RBSB 32 40 Sdpar CALC RBSB 100 echo RBPD 12 41 Sdpar CALC RBPD 100 echo RBPS 32 41 Sdpar CALC RBPS 100 techo LBULK 4 40 dpar CALC LBULK 0 1p os Call single MOSFET A Sete cies AE ie pe re I ee er i echo MAIN 10 21 30 41 BSIM3_HF echo L Sdpar x_rf_transistor L 1u W Sdpar x_rf_transistor W 10e 6 echo AD Sdpar x_rf_transistor AD 10e 12 AS Sdpar x_rf_transistor AS 10e 12 echo PD Sdpar x_rf_transistor PD 22e 6 PS Sdpar x_rf_transistor PS 22e 6 echo NRS Sdpar x_rf_transistor NRS 0 NRD Sdpar x_rf_transistor NRD 0 echo NQSMOD Smpar NQSMOD 0 ends Modeling Strategy Modeling the AC behavior of a MOS device with the BSIM3v3 model heavily depends on the accurate modeling of the DC curves and the capacitances at low frequencies for example 10kHz to 1MHz However more and more applications especially in the telecommunication industry require th
523. r Deep Submicron CMOS Processes mosfet Extraction of Model Parameters mosfet Binning of Model Parameters mosfet Importing older version BSIM3v3 Files mosfet References and Copyright Information mosfet 116 MOSFET Models What s New in the BSIM3v3 Modeling Package This section lists the enhancements and changes made to the Modeling Package for each revision since IC CAP 2002 They are listed in reverse order so that the new version is on top followed by changes made in former versions Version IC CAP 2011 04 April 2011 IC CAP 2006 spring 2007 IC CAP 2004 spring 2005 IC CAP 2004 January 2004 IC CAP 2002 March 2003 Features Enhancements The BSIM3 Modeling Package is enhanced to the model version BSIM3v3 3 2 The BSIM3 model version enhanced to the model version BSIM3v3 3 0 The GUI is updated to look similar to BSIM4 and PSP Modeling Packages e BSIM3_DC_CV_Measure The time to load a new project has been dramatically reduced also in BSIM3_DC_CV_Extract BSIM3_RF_Measure BSIM3_RF_Extract List sweeps are now supported e BSIM3_DC_CV_Extract The extraction flow has been enhanced to store and retrieve complete extraction scenarios including intermediate results and boundary settings The usability of the plot optimizer inside the BSIM3 Package has been enhanced and user configured plot optimizers can be easily integrated into the extraction flow e BSIM3_RF_Measure New scheme to define de e
524. r devices is the average of the LOD effect on every finger Since MOSFETs often use an irregular shape of their active area additional instance parameters have to be introduced to fully describe the shape of the active area This will result in many new parameters in the netlists and an increase in simulation time To avoid this drawbacks BSIM4 3 0 uses effective SA and SB values A third dimension is added to standard geometry parameters of MOSFET devices by introducing new parameters SA and SB to model stress effect influence on device performance 206 MOSFET Models The left part of the figure above shows the geometry parameters used in MOSFET models so far To the right the SAREF plane represents the standard L W plane which is varied by SA and SB Until BSIM4 2 1 gate length L and gate width W have been the major device geometry parameters required For more details regarding the modeled stress effect influences on device performance see Chapter 13 of the BSIM4 3 0 manual see BSIM4 References mosfet 1 Back to BSIM4 Characterization mosfet 207 MOSFET Models CV Modeling Capacitance Model To accurately model MOSFET behavior a good capacitance model considering intrinsic and extrinsic overlap fringing capacitances is important BSIM4 provides three options to select different capacitance models These are the models from BSIM3v3 2 which are taken without changes There is only one exception Differen
525. r of the threshold voltage for a large and a short device is shown in the following figure Threshold Voltage Vth f T of a Large Device 700 0 60a 0 400 0 B 254 6 366 6 356 6 4050 8 calc VTHA_ T s calc VTH _T cale_VTH YES T m calc VTH Y amp S T E Temperature EE tB Threshold Voltage Vth f T of a Short Device 156 MOSFET Models Hl A 380 0 376 8 Se ee calc _VIHL_T m SS ee TETT calc YTH L T s 250 0 240 0 I I 5 I I 4 i I I 336 8 254 6 300 8 350 8 400 8 Temperature CE 0J b Carrier Mobility All four model parameters of the carrier mobility are implemented in BSIM3 with a temperature dependence r UTE HoT V0 F nom E U 1 UA UAL 3 1 nom U T UB UBI 1 BY LF j nom 7 ho o 7 E UAT UC UCI 1 nom The following two diagrams show the effect of temperature dependent mobility on the transconductance of a large transistor Temperature Dependence of Carrier Mobility UO Influence on Drain Current id f Yg Vbs0 Vd min 106 aa mI T LJ m 6a ie au a 44 E ga 24 I I I I I I I I I I I vo CE e 4 Temperature 2560 400K Temperature Dependence of Carrier Mobility U0 Dependence from UTE 157 MOSFET Models m 1 Om Lil
526. r process They are marked Recommended Test Transistor Geometries for proper parameter extraction Wium SHORT A Design geometries covered by extraction 54 B O O O O g ARSE N t 1 Design geometries extrapolated from extraction Cd Forbidden geometries due to process limitations 0150203 05 1 0 5 Lum Requirements for Devices Large For a proper extraction of the basic model parameters the short and narrow channel effects should not affect the large device extraction Also the drain source resistance parameters should not have an influence on the simulated behavior of the large device For a typical 0 5 micron CMOS process with a gate oxide thickness of 11 nm a large device with channel length of 10 microns and channel width of 10 microns was found to meet these requirements You can check this prerequisite if you only extract the parameters in the idvg Large setup and then perform a simulation of the setup idvg Large_m After that simulation perform the other geometry extractions and re simulate the idvg Large setup again Now the curve ID F Vg5 should not change more than roughly 5 compared to the first simulation If the difference is bigger a larger device should be used to enable a good extraction of the basic model parameters Narrow For the DUT Narrow_m you should use a device with the smallest designed gate width of your process Using more narrow devices will increase the number
527. r the width dependence of the flat band V 0 voltage at TR PLWVFB Coefficient for the length times width dependence of V 0 the flat band voltage at TR POSTVFB Coefficient for the geometry independent part of V K 5E 4 temperature dependence of VFB PLSTVFB Coefficient for the length dependent part of V K 0 temperature dependence of VFB PWSTVFB Coefficient for the width dependent part of V K 0 temperature dependence of VFB PLWSTVFB Coefficient for the length times width dependent part V K 0 of temperature dependence of VFB POTOX Coefficient for the geometry independent part of m 2E 9 Gate oxide thickness PONEFF Coefficient for the geometry independent part of m 3 5E23 substrate doping PLNEFF Coefficient for the length dependence of substrate m 3 0 doping PWNEFF Coefficient for the width dependence of substrate m 3 0 doping PLWNEFF Coefficient for the length times width dependence of m 3 0 substrate doping POVNSUB Coefficient for the geometry independent part of V 0 effective doping bias dependence parameter PONSLP Coefficient for the geometry independent part of V 5E 2 effective doping bias dependence parameter PODNSUB Coefficient for the geometry independent part of V 1 0 effective doping bias dependence parameter PODPHIB Coefficient for the geometry independent part of the V 0 offset of PLDPHIB Coefficient for the length dependence of offset of V 0 PWDPHIB Coefficient for the width dependence of o
528. rameter 0 0 LKVTHO KVTHO length dependence 0 0 WKVTHO KVTHO width dependence 0 0 PKVTHO KVTHO cross term dependence 0 0 LLODVTH VTH stress effect length parameter gt 0 0 0 WLODVTH VTH stress effect width parameter gt 0 0 0 STK2 Shift factor for K2 with changing VTHO 0 0 LODK2 K2 shift modification factor for stress effect gt 0 1 0 STETAO Shift factor for ETAO related to change of VTHO 0 0 LODETAO ETAO shift modification factor for stress effect gt 0 1 0 Well Proximity Modeling Well Proximity Effect Model Parameters Parameter Description Default Value Unit SCA Integral of the first distribution function for scattered well dopant 0 SCB Integral of the second distribution function for scattered well dopant 0 SCC Integral of the third distribution function for scattered well dopant 0 SC Distance to a single well edge 0 m WEB Coefficient for SCB 0 WEC Coefficient for SCC 0 KVTHOWE Threshold shift factor for well proximity effect 0 K2WE K2 shift factor for well proximity effect 0 KUOWE Mobility degradation factor for well proximity effect 0 SCREF Reference distance to calculate SCA SCB and SCC 1E 6 m 225 MOSFET Models High Speed RF Model Parameters High Speed RF Model Parameters Parameter Description Default Unit Value XRCRG1 Parameter for distributed channel resistance effect for both intrinsic input 12 0 resistance and charge deficit NQS models XRCRG2 Parameter to account for the excess channel diffu
529. rap assisted voltage dependent parameter Source side Drain side Temperature coefficient for NJTS Temperature coefficient for NJTSSW Temperature coefficient for NJTSSWG Capacitance Charge partitioning parameter Non LDD region gate source overlap Capacitance per unit W MOSFET Models 1 0 1 0 3E 9 IJTHSREV 0 1 IJTHDREV IJTHSREV IJTHSFWD 0 1 IJTHDFWD IJTHSFWD XJBVS 1 0 XJBVD XJBVS BVS 10 0 BVD BVS JSS 1 0e 4 JSD JSS JSWS 0 0 JSWD JSWS JSWGS 0 0 JSWGD JSWGS CJS 5 0e 4 CJD CJS MJS 0 5 MJD MJS MJSWS 0 33 MJSWD MJSWS CJSWS 5 0e 10 CISWD CJSWS CJSWGS CJSWS CJSWGD CIJSWS MISWGS MJSWS MJSWGD MJSWS PBS 1 0 PBD PBS PBSWS 1 0 PBSWD PBSWS PBSWGS PBSWS PBSWGD PBSWS 0 0 JTSS 0 0 JTSSWS 0 0 JTSSWGS NTIS 20 NTJSD NTIS NTISSW 20 NTJISSWD NTJSSW NTISSWG 20 NTJISSWGD NTJSSWG 0 02 0 02 0 02 10 VTSS 10 VTSSWS 10 VTSSWGS 0 0 calculated see Overlap Capacitance Model 223 A m2 A m A m F m2 A m A m A m F m MOSFET Models Non LDD region gate drain overlap calculated see Overlap Capacitance F m capacitance per unit W Model aa bulk overlap capacitance per unit e 0 CGSL Light doped gate source region overlap 0 0 capacitance CGDL Light doped gate drain region overlap 0 0 F m capacitance CKAPPAS Coefficient of bias dependent overlap 0 6 V capacitance on source side CKAPPAD Coefficient of bias dependent overlap CKAPPAS capacitance on drain side
530. rategy The following figure shows the principle procedure of model parameter extraction as it was used in older models like the MOS Level 3 model The model parameter P is determined from the measured electrical behavior of one single test transistor The measured data is transformed in such a way that P can be determined with regression methods Model Parameter Extraction from Single Devices i _ curve I f U transformed curve Extracted model I g U parameter Px In contrast the group extraction strategy which is shown in the following figure uses the measured electrical behavior of several test transistors with different gate lengths and gate widths Group Extraction Strategy 176 MOSFET Models curves I f U of test new data array transformed extracted transistors with e g VTH g L as array model different device function of gate VTH h L parameter Px dimensions length In a first step intermediate values like the threshold voltage V are determined and stored in a new data array as a function of gate length In the next step this new data array is transformed in such a way that the model parameters P can be determined with regression methods Parameters extracted with this method describes the behavior very well of the devices in a wide range of channel lengths and channel widths Physically Oriented Model Parameter Extraction For the determination of device model parameters from measured I V or C V
531. ration THESATBO lG Back bias dependence of THESAT V 1 0 k E THESATG L Gate bias dependence of velocity V 1 0 a i saturation THESATGO lG Gate bias dependence of THESAT Vv 1 Saturation Voltage Parameters px Linear saturation transition factor E Geometry independent 18 linear saturation transition factor AX fe IL Length dependence of AX 0 p Channel Length Modulation CLM e Lo CM pre factor 0 01 Mp Length dependence of CLM pre 5E 4 factor ALP ALPLEXP Exponent for length dependence of ALP ALPW fe Width dependence of ALP 0 ALP1 L CLM enhancement factor above V 0 0 threshold ALP1L1 G Length dependence of CLM V 0 enhancement factor above threshold ALP1LEXP G PORN describing the length i 0 5 i i dependence of ALP1 ALP1L2 G Second order length dependence 0 0 of ALP1 TT 275 MOSFET aa ALP1W Width dependence of ALP1 z ALP2 CLM enhancement factor below V 1 threshold ALP2L1 Length dependence of CLM enhancement factor below threshold ALP2LEXP G Exponent describing the length 0 5 dependence ALP2 ALP2L2 G Second order length dependence 0 0 of ALP2 ALP2W lG Width dependence of ALP2 0 p VP L CLM logarithmic dependence V 0 05 1E 10 TETN VPO G CLM logarithmic dependence V 0 05 1E 10 l ee Impact Ionization c Parameters AL Ir Impact ionization pre factor 0 Geometry independent part of i i i
532. rature_coefficients The optimize_temperature_coefficients macro controls the optimization sequence for the temperature coefficients by calling the transforms listed below found under the all_temp_extract setup in the order shown all_temp_lin_opt1 all_temp_lin_opt2 all_temp_subvt_opt1 all_temp_ids_opt1 all_temp_isub_opt1 VL ONS 361 MOSFET Models The JUNCAP Model The JUNCAP model represents the C V and I V behavior of the parasitic source and drain regions of MOSFET devices References mosfet 5 The JUNCAP model file contains four DUTs area locos gate and analysis The area locos and gate DUTs hold the data for the area locos and gate test structures respectively The analysis DUT and its associated setups contains the transforms that control the parameter extraction strategies The area locos and gate DUTs The area locos and gate DUTs all have the same structure as shown in the following table Parameters for area locos and gate Test Structures area locos gate AB is set to AB1 LS is set to LS1 AB is set to AB2 LS is set to LS2 AB is set to AB3 LS is set to LS3 and and LG is set to 0 and LG is set to 0 LG is set to LG3 Each of these DUTs contain three setups cv fwd_iv and rev_iv cv This setup contains measured and simulated C V data It consists of the following va This input defines the voltage sweep for C V measurement It uses the variables CVSTART CVSTOP and CVSTEP as defined in the setup_de
533. rce per gate width and finger F m echo RSHG Smpar RSHG 25 gate sheet resistance Ohm sq echo LDRAINO Smpar LDRAINO 1e 6 drain inductance per gate width and gate finger H m echo LGATEO Smpar LGATE0 1e 6 gate inductance per gate width and gate finger H m echo LSOURCE0 Smpar LSOURCE0 1e 6 source inductance per gate width and finger H m echo LBULKO Smpar LBULK0 1e 6 bulk inductance per gate width and finger H m echo RSHB Smpar RSHB 25 bulk sheet resistance Ohm sq echo DSBC Smpar DSBC 2e 6 distance source implant to bulk contact m echo DDBC Smpar DDBC 2e 6 distance drain implant to bulk contact m echo DGG Smpar DGG 2e 6 distance gate to gate m echo DLO Smpar DLO 0 basic channel length reduction correction m echo DL1 Smpar DL1 0 channel length reduction correction 1 and 2 outer fingers m echo DL2 Smpar DL2 0 channel length reduction correction outer fingers m pasa See Cave NetWOnK Asso n eases Sass on areas See R or Se Roel Seer Cea echo LGATE 2 20 Sdpar CALC LGATE 0 1p echo RGATE 20 21 Sdpar CALC RGATE 10 echo CGDEXT 20 10 S dpar CALC CGDEXT 0 1f echo CGSEXT 20 30 Sdpar CALC CGSEXT 0 1f FOSS SS a Drain network n 2sS3 oS See Se SSS SSS See See SSS Sees Serio Se Se eS Se ae SS echo LDRAIN 1 10 Sdpar CALC LDRAIN 0 1p echo CDSEXT 10 30 Sdpar CALC CDSEXT 0 1f a aera Source network see t Se rrr rrr rr rrr E a a A se echo LSOURCE 3 30 Sdpa
534. re as the part AVin 1 of the overall threshold voltage r AV K BT pK my th 1 1 bseff_ 2 bse ma Toxm seff Toxm seff K 2 2K As Vim G GO Tia Js K f i a ae l 7 A b N D bx Nl D Vp gt gt 2g amp Neh ox hae N A 24s sub a a Ox where Vbx substrate bias voltage when the depletion width x equals a Went xX er r a Vim Maximum substrate bias voltage Toxm gate oxide thickness at which parameters are extracted Tox default value of Thy V a RS bseff _ s a Parag ES Se Fer Vye 0 5 Tps Ve 81 t Tyg Pye 48 Vye P 0 001V V bc Ki 09 a 4K In BSIM3 either the model parameters K1 and K2 or NCH NSUB VBM or XT can be used to model this effect The following figure shows the threshold voltage V as a function of the applied bulk voltage for a transistor with a large channel length and a wide channel width LARGE Threshold Voltage Vth as a Function of Vbs 122 MOSFET Models LE 3 YTH m calo VTIHVs Non Uniform Lateral Channel Doping The doping concentration N near the drain and the source is higher than the concentration N in the middle of the channel This is referred to as lateral non uniform doping concentration and is shown in the following figure Lateral Doping Profile in the Channel Smia E Drain Doping profile F ping p Pa Approximation Xchanna As the channel length
535. re controlled by the following variables which are also in the model variables table RIV_VMIN RIV_VMAX isn A transform that extracts and holds the normalized locos sub region contribution to reverse current from the measurements in the area rev_iv locos rev_iv and gate rev_iv setups isn_sim A transform that calls JUNCAP to evaluate the locos sub region component of current fit_isn An optimization definition that causes the parameter JSGSR to be optimized with respect to the normalized locos sub region reverse current The parameter limits are controlled by the following model variables which you can change in the model variables table JSGSR_MIN JSGSR_MAX The data limits are controlled by the following variables which are also in the model variables table RIV_VMIN RIV_VMAX ign A transform that extracts and holds the normalized gate sub region contribution to reverse current from the measurements in the area rev_iv locos rev_iv and gate rev_iv setups ign_sim A transform that calls JUNCAP to evaluate the gate sub region component of current fit_ign An optimization definition that causes the parameter JSGGR to be optimized with respect to the normalized gate sub region reverse current The parameter limits are controlled by the following model variables which you can change in the model variables table JSGGR_MIN JSGGR_MAX The data limits are controlled by the following variables which are also in the model va
536. re entries at the global level VFBO VFBL VFBW and VFBLW Those parameters describe influences of the device geometry onto the behavior used in the global model VFBO means the geometry independent part of VFB VFBL describes the length influence and VFBW the width influence whereas VFBLW describes the area influence of device geometry onto the flatband voltage of the device Using this arrangement you can easily see parameter correspondences between the local and the global model of the PSP hierarchy The following table lists the model parameters used This table shows whether a local parameter has length and or width dependant elements which generally use the same parameter name followed by L for a length dependency W for a width dependency or LW for a length and width dependency Parameters in the global parameter set that begin with the letters ST refer to the temperature scaling of a parameter Parameters used for local global and binning model Parameter Parameter used Description Unit Default Min Max for Global Local B inning LEVEL L G B Model selection parameter 103 TYPE L G B Channel type parameter 1 1 1 1 NMOS 1 PMOS TR L G B Reference temperature oC 21 273 l DTA L G B Temperature offset w r t K 0 ambient circuit temperature Switch parameters SWGEO L G B Geometrical Model flag 1 0 2 Local 0 Global 1 Binning 2 SWIGATE L G B Flag for gate current O off 0 0 1 SWIMPAC
537. re of MOS Model 9 Parameter Set for a Given Process 74 Parameters Maxiset Temperature DC Capacitance Noise Coefficients 60 2 2 10 Scaling Rules Parameter Set for a Single Device at a Specific Temperature 26 Parameters Miniset Drain Current Substrate Current Capacitance Noise 6D 3 2 2 344 MOSFET Models The MM9 Model File This section describes the MOS Model 9 model parameters model variables DUT setup details and macros Model Parameters The following table describes the MOS Model 9 parameters MOS Model 9 Parameters Parameter Description LER WER LVAR LAP WVAR WOT TR VTOR STVTO SLVTO SL2VTO SWVTO KOR SLKO SWKO KR SLK SWK VSBXR SLVSBX SWVSBX BETSQ ETABET THEIR STTHE1R SLTHE1R STLTHE1 SWTHE1 THE2R STTHE2R SLTHE2R STLTHE2 SWTHE2 THE3R STTHE3R SLTHE3R STLTHE3 SWTHE3 GAMiIR SLGAM1 SWGAM1 ETADSR ALPR ETAALP SLALP SWALP VPR GAMOOR SLGAMOO ETAGAMR MOR STMO SLMO ETAMR ZETIR ETAZET SLZET1 Effective channel length of the reference transistor Effective channel width of the reference transistor Difference between the actual and the programmed poly silicon gate length Effective channel length reduction per side due to the lateral diffusion of the source drain dopant ions Difference between the actual and the programmed field oxide opening Effective channel width reduction per side due to the lateral diffusio
538. re on that dialog box If measuring at elevated temperatures be sure to wait until your devices are heated up or cooled down to the desired temperature If you would like to clear some or all measured data choose Clear Data from the Data menu You can select whether you would like to clear measured data of some or all DUTs at specified temperatures and click Clear Data to delete measured data files Using Synthesize Measured Data from the Data menu you can simulate capacitance data from existing parameters These synthesized data use the voltages set on the Measurement Conditions folder to generate measurement data from a known set of SPICE parameters It might be especially useful to convert parameters of other models into BSIM3 or BSIM4 parameters by loading the created measurement data into the extraction routines and extract parameters for the desired model To see the diagrams of what has just been measured click the Display Plots icon or Data gt Display Plots You will see a dialog box to select which measured data set you would like to display After choosing the plots you would like to see click Display Plots on that dialog box to open the selected plots This is a convenient way to detect measurement errors before starting the extraction routines If you are satisfied with the data you have just measured choose Close Plots to close the windows that show diagrams of measured data Diode This part of the Data tree is used to def
539. red into the form using a bin number and the geometries of the four corners for this bin Delete all Bins Using this menu item all bins are deleted from the graphic as well as the form Change Tolerance The purpose of this menu item is to change a predefined tolerance for the binning areas This tolerance is needed because of the definition of Binning Boundaries There are boundaries for each binning area LMIN LMAX WMIN WMAX Those boundaries will be analyzed using Leff and Weff If Unable to render embedded object File icmdl 02 1 67 gif not found a subcircuit will be used This means if a device with L 10um is used and this is LMAX then it is not possible to simulate this device using the binned model This is due to the above mentioned region for the parameters Unable to render embedded object File icmdl 02 1 68 gif not found So if L LMAX the device does not fit into the binning boundaries which require a value smaller than LMAX and cannot be used for simulations Therefore tolerances are implemented to correct for this error You are able to change the predefined tolerance 0 01um to a value which suits your needs The results within the measured and extracted areas will not be altered But it is now possible to simulate devices having a gate length or width a little delta L or delta W outside the defined binning areas Add Extension By choosing this button you will get a form to enter Extension Delta Values like
540. rence values e WPE category determines the properties regarding the well proximity effect Note Devices at SA SAREF and SB SBREF are used to determine all other model parameters except the STI related parameters The Configuration menu enables you to Sort the entries into an order or to Set the size category of your devices manually See Transistors for DC measurements mosfet You can use Configuration gt Sort or the appropriate icon to set the size category of your devices automatically Otherwise you are required to enter the size category manually using the form shown in the following figure Set geometry and STI categories 25 MOSFET Models 45 Select Devices Winger um 0 25 2 co Devices EE EN E E right click to change Size Category The device category is used for extraction purposes See Transistors for DC measurements mosfet for an explanation of categories and requirements for proper extraction of device parameters as well as the paragraph about Stress Effect Modeling mosfet If you would like to delete devices e Choose Delete from the row of icons or from the Configuration gt Delete menu You will be prompted with a list of DUTs Select the DUTs to be deleted and choose Delete on the Delete DUT form A prompt dialog box appears Select OK if you are satisfied with your choice of DUTs to be deleted According to your choice of temperatures on the Temperature Setup fo
541. required to measure both DUTs and extract the parameters from both measurements Therefore it only makes sense to add those DUTs together Since oxide capacitance requires only one test structure you are able to have only one oxide capacitance DUT It is now possible to use different capacitances for drain and source area GD and GS are extracted by default only for the HISIM HV model However it is possible to add a sufficient extraction step for other models using Finetuning This makes sense only for the HISIM and BSIM4 models since only for these models asymmetric drain source capacitances are possible For each line you can change the predefined name for the DUT and enter necessary geometrical data For your convenience only relevant data should be entered for a specific group of capacities Relevant data fields are shown with white background and can be edited Gray shaded data fields are not editable For example DUTs to measure bulk drain junction capacitances do not require gate length and width L W source area AS and perimeter length of source PS geometrical data You only have to provide drain area AD and drain perimeter PD as well as the number of device fingers NF of the transistor to be measured See Device geometries for some details on capacitances and geometries Note W AD AS PD and PS are total values including all fingers of the device Note Usually you use single finger transistors for DC measure
542. reviously Measured Data Computing the Parasitics for the Model Generation An earlier part of the procedure calculated the intrinsic parasitic resistances of the device and entered them in the file Para data Now this procedure updates the data and gives you the opportunity to override the calculated values and input values of your own if you believe they are more appropriate Select the main DUT and the DUT Variables tab A variable table is displayed showing current values for the intrinsic parasitic resistances and inductances as well as other variable values The following figure illustrates the DUT variables table Note the intrinsic inductances Ls_tot Ld_tot and Lg_tot all have default values of 1 000f Variable Table of the main DUT Showing Parasitic Values Do not change any of the other variable values in the table besides the R and L values The other variables listed are internal functions necessary to the program and can be ignored If you have reason to change any of the parasitic values you can change them in this variable table For example if you have calculated the parasitic values by another method such as from material measurements or by using a different algorithm you may prefer to use those values Or based on the model generation results plotted later in the procedure you may wish to return to this step and modify values then perform the transforms again Note If you make any changes to the
543. riables table RIV_VMIN RIV_VMAX set_temp This transform sets the setup level variable TEMP to the model level variable TREVERSE opt_all_rev_iv An optimization definition that causes all the generation parameters to be optimized with respect to the measured data in the area rev_iv locos rev_iv and gate rev_iv setups The parameters optimized are JSGBR JSGSR JSGGR The parameter limits are controlled by the following model variables JSGBR_MIN JSGBR_MAX JSGSR_MIN JSGSR_MAX JSGGR_MIN JSGGR_MAX The data limits are controlled by the following variables FIV_VMIN FIV_VMAX ib A plot definition for the normalized area sub region contribution to current is A plot definition for the normalized locos sub region contribution to current ig A plot definition for the normalized gate sub region contribution to current Macros This section describes the macros provided with the JUNCAP model setup_details This macro prompts you for various setup details These details are stored in the model variables table The current values of the variables are used as prompts so you can easily change one setting by executing the macro a second time and choosing OK to all questions except the change required The information requested by this macro is as follows 366 MOSFET Models TR Model parameter representing reference temperature VR Model parameter representing the reference voltage for parameter scaling usually 0 TEMP Ambient temperature
544. rian_buchanan agilent com for more information For details see http bmaster soco agilent com mw Qt_License_Information Errata The IC CAP product may contain references to HP or HPEESOF such as in file names and directory names The business entity formerly known as HP EEsof is now part of Agilent Technologies and is known as Agilent EEsof To avoid broken functionality and to maintain backward compatibility for our customers we did not change all the names and labels that contain HP or HPEESOF references Warranty The material contained in this documentation is provided as is and is subject to being changed without notice in future editions Further to the maximum extent permitted by applicable law Agilent disclaims all warranties either express or implied with regard to this manual and any information contained herein including but not limited to the implied warranties of merchantability and fitness for a particular purpose Agilent shall not be liable for errors or for incidental or consequential damages in connection with the furnishing use or performance of this document or of any information contained herein Should Agilent and the user have a separate written agreement with warranty terms covering the material in this document that conflict with these terms the warranty terms in the separate agreement shall control Technology Licenses The hardware and or software described in this document are furnished under a l
545. roach which is supported by the BSIM4 model The description of the model in a simulator is very easy because only the call of a model card is necessary The following netlist in spice3e2 syntax shows an example for this model description OPTIONS GMIN 1 0E 14 Model card for BSIM4 3 0 n type devices Simulator SPICE3e2 Model BSIM4 Modeling Package Date 16 07 2004 Origin ICCAP_ROOT bsim4 circuits spice3 cir nmos cir M1 1 D 2 G 3 S 4 B MOSMOD L 0 25u W 5u NF 1 AD 5p AS 5p PD 12u PS 12u SA 0 SB 0 SD 0 NRD 0 NRS 0 MODEL MOSMOD NMOS LEVEL 14 VERSION 4 3 0 BINUNIT 2 PARAMCHK 1 MOBMOD 1 RDSMOD 0 IGCMOD 0 IGBMOD 0 CAPMOD 2 RGATEMOD 0 RBODYMOD 0 TRNQSMOD 0 ACNQSMOD 0 FNOIMOD 1 TNOIMOD 0 DIOMOD 1 PERMOD 1 GEOMOD 0 Fully Scalable Device The fully scalable model has the same structure in principal as the single transistor model but uses additional scalable external inductors and capacitors It uses equations to determine the values for the substrate resistance parameters These equations are derived from simple assumptions according to MOS Transistor Modeling for RF IC Design BSIM4 References mosfet 3 Please see the following schematic and cross section as well as the model equations for more details Scalable BSIM4 RF model BSIM4 RF Subcircuit BSIM4 Internal D Tronsistor Network n L D_db Rbpd ig Rd G r Rbpb BSIM4 Intr he D_sb
546. roject In this case you must select the project as well as the exported extractions Then you will be able to select whether you would like to use all or specific parts of the saved extraction project components by de activating the components not to be used results settings boundaries and finetuning If there are stored files they will be shown under the Files section of this window Note This feature makes it possible to import any other mps file to compare results But be careful importing other parameter files will overwrite the actual parameters Don t use this option during an extraction session with partly extracted parameters unless you ve saved the work in progress Interactive Extraction Mode A new powerful feature of IC CAP and the BSIM Modeling Packages is the ability to display several plots in one window It is called a Multiplot window This feature is used when you enter the Interactive Extraction Mode Either use the Extract menu or the EH interactive mode icon SRR to invoke this mode The Interactive Extraction Mode opens a Multiplot window with a default number of plots shown To the right of the interactive plot window you can see three folders e Devices This folder is used to select devices for extraction You will find a list of devices as has been defined inside the measurement module DC Transistor DUTs Select one of the devices for extraction Extract This folder shows one or more paramet
547. rt and select the required Device List you wish to export DC Device List Capacitance Device List or Diode Device List The Export Device List window is displayed 2 In the Export Device List window choose the path where you can store the device list data in csv format 3 Type the Device list file name for example Device_List and click Save Export Device List Capacitance DUIs Save in Device_List a 5 Recent 9 My Computer k My Network File name Device_List csv v save Places Save as type esv v Cancel 4 Now In WaferPro window choose Wafer Map gt Device Info under the Navigation view and click Device Type View tab Subsite view Device Type View a j T e ee g ES E i Device Type MOS 4 k lt 5 Click the Load_Device_icon in to load the csv file with the MOS Modeling Toolkit device information The IC CAP WaferPro Load Subsite Device Infor from cvs File window appears 6 Click Select and select the csv file 7 Select the required subsites in the Se ect Subsites pane If you are using the Add User Parameters feature in one of your model file the imported devices will not reflect the settings To get the correct settings close IC CAP and launch it again as the configuration is written only when you launch IC CAP The following figures display the imported modules from the BSIM4_for_experts example file Subsite View in WaferPro Subsite
548. rt to stop voltage values Start 0 0 Stop at or below the upper limit of the device s normal operating range 1 of Points sufficient to clearly display the measurement results The Step Size will be set automatically For the vg input Set To Mode V Compliance no greater than the maximum allowable gate current value Sweep Type LIN to provide a linear voltage sweep from start to stop voltage values Start Stop such that three to five values points will be measured in a range from approximately of Points Vgs Vthreshold to Vgs 3 or 4V Set Start to a value close to Vthreshold but not so close that the curve will be difficult to discern The Step Size will be set automatically O Note The vd and vg ranges apply to an NMOS device Recognize that for a PMOS device both vd Start and vg Start will be negative and Stop will be 0 000 e The Unit names must conform to the names you set in the hardware window when you configured IC CAP to recognize the system hardware probably VD and VG They must also correspond with the actual SMU source monitor unit connections from the Agilent 4142 Since the device source terminal is grounded only the drain and gate inputs need to be set e You provide compliance values to limit SMU output voltage or current and thus prevent damage to the device under test as well as to the SMUs bias networks and probes if used With a voltage input compliance refers to current e The Outputs are factory
549. rts this helps to facilitate measurement of a BJT with only two SMUs since the port 2 SMU is used for measurements at both the collector and emitter terminals Some models use more than two SMUs their SMU names are defined in their respective chapters The following figure illustrates the SMU unit names for a FET measurement and the corresponding device terminal connections SMU Unit Names for a FET Measurement The following figure illustrates the SMU unit names for a Gummel Poon BJT measurement and the corresponding device terminal connections SMU Unit Names for a BJT Measurement 324 MOSFET Models 1 In the Instrument List click on HP4142 to highlight it Select Configure and the Configuration of HP4142 window is displayed 2 The Unit Table lists the SMUs Also listed for each is a unit ID identification name that can be edited e In a FET measurement the medium power MPSMU1 is renamed VG because it is connected to the gate terminal and the high power HPSMU3 is renamed VD because it is connected to the drain terminal e In a Gummel Poon BJT measurement the medium power MPSMU1 is renamed SMU1 because it is the port 1 SMU and the high power HPSMU3 is renamed SMU2 because it is the port 2 SMU 3 To make this change click left with the mouse and move the mouse pointer over the name assigned to MPSMU1 to highlight it Then type in the new name and press Return Similarly change MPSMU3 s assigned unit name Then sele
550. ructure referred to as HV structure The HiSIM_HV model is valid for both the structures It is an extension to the HiSIM2 model developed by the University of Hiroshima together with the STARC consortium Here STARC stands for Semiconductor Technology Academic Research Center co funded by major Japanese semiconductor companies in 1995 The main differences between a conventional MOSFET and a high voltage MOSFET arises from the drift region introduced to enhance the sustainability to high voltages which is shown in the following cross section of a HV MOSFET Love L lt gt Gate lt _ gt Source Ei i lt gt nt LoverLD p Drift Region n Nover Accurate modeling of the drift region is a major task in HV MOSFET modeling This region not only affects the resistance through additional charges inside the drift region but the capacitances are affected as well The basic equations of the HiSIM2 model are used for HiSIM_HV also and complete with additional equations to model the drift region influence The HV model can be used for simulation of symmetrical as well as asymmetrical device structure A flag is introduced to switch from the symmetric to the asymmetric device structure COSYM 0 refers to the asymmetric LDMOS structure and coSym 1 to the symmetric HVMOS structure The following figure shows the parameter extraction approach using the COSYM parameter HVMOS symmetrical All structural parameters values o
551. ry Flow 2 Be n a f Local to Global Factory Flow Hs New Group ia Local Capacitance Cgg H Local Long Wide H g Local Length Dependence Wide H Local Long Width Dependence H g Local Length Width Dependence E amp PSP Scale Parameters H g Local Short Wide H Local Short Width Dependence HH Binning 70 Generate Calculation MOSFET Models O it is only posssible to copy a Group or a Function into a Main Group or a Group it belongs to For example the function E TOX cannot be used in Extraction Group Capacitance Overlap this function can only be used in the group Capacitance Oxide as defined in Available Extractions on the first tab Adding a function to a different extraction step m Configuration Wizard for Extraction Functions 12 Configuration Edit Options Help B Eft Available Extractions Overview Customized Functions Default Extraction Flows Available Extractions Default Extraction Flows Global 6S 3H Capacitance Oxide E TOxo O TOXO NSUBO VFBO E T TOXO NSUBO YFBO O TOXO NSUBO YFBO DLO A T TOXO NSUBO YFBO DLO ae Capacitance Overlap Capacitance Junction Diode Large Vth Mobility Saturation Velocity Large Gate Current Large Impact Ionization and GIDL Length Scaling Yth Mobility Saturation Velocity Width Scaling amp Corner Length Width Scaling Tem
552. s Some menu topics are only activated when using specific tasks depending on which folder is activated For example if you are setting up the conditions for a Temperature measurement the Configuration menu only allows you to add or delete temperatures The rest of the menu is not active since it is not necessary to set or sort categories during temperature setup for example The File menu has entries to Import and Export list and measurement data from measurement software other than IC CAP Those functions are described in Import Wizard 12 MOSFET Models mosfet To import data from other software or saved in another data format use the Import Wizard This feature is accessible through the following file menu File gt Import gt Import Wizard mosfet The standard IC CAP icons from left to right are located below the menu Use these icons to create a New to Open an existing to Copy and Open an Example to Save Setups or Entries to Measure to Display and Close plots to Add or Delete to define Temperature Measurements to Set categories or to Check SMU connections You will be prompted before the selected action takes place Again some of the icons are only activated when specific folders are active The lower part of the window displays the project name and project directory To Print a setup choose File gt Print Setup This opens a dialog box In this dialog box enter the command line for your specific printing de
553. s 10 00u Ldes 2 000u Vth 375 0m LIEI Vth E 3 Vth_T E 3 og lt xl Ldes LOG of DUT E 0 Left part Vth f L W Right part Vth f temp device See Also Capacitance Model mosfet High Frequency Behavior mosfet Temperature Dependence mosfet Noise Model mosfet SPICE Model Parameters for BSIM3v3 mosfet Test structures for Deep Submicron CMOS Processes mosfet Extraction of Model Parameters mosfet Binning of Model Parameters mosfet Importing older version BSIM3v3 Files mosfet BSIM3v3 Characterization mosfet 139 MOSFET Models Capacitance Model Please use the examples provided with the Modeling BSIM3v3 Modeling Package to visualize the capacitance model parameters Load the file into IC CAP and run the different macros to see how certain parameters affect the device behavior of a deep submicron MOS transistor The capacitance in a MOS transistor can be divided into three different parts e Junction capacitance C between source drain and the bulk region Junc e Capacitance of the extrinsic MOS transistor which consists of o The outer fringing capacitance C between polysilicon gate and the source drain o The overlap capacitance Copo between the gate and the heavily doped source drain regions o The overlap capacitance Copo between the gate and the lightly doped source drain regions e Capacitance of the intrinsic MOS transistor in the region between the metallurgical source
554. s away 3 Select the Extract Optimize tab 4 Select compute_rseries gt Execute The transform calculates the port series resistances from the measured data and enters the values into the model variable table as ris and ras Installing the Device A Caution Ground yourself with an antistatic wrist strap to reduce the chance of electrostatic discharge Install the device carefully on the probe chuck or in the fixture Be sure to handle the device as little as possible to avoid damaging it Once the device is in place avoid bumping the test station Caution Remove any high intensity light sources such as microscope light before taking a measurement One simple method of blocking light is to place an opaque box on the fixture directly above the device Preverifying the Device DC Data This procedure uses the idvd_vg setup to measure drain current and gate current with respect to drain voltage at several values of gate voltage The drain voltage is swept from OV to the upper limit of its normal operating range This is an opportunity to take a first look at the device performance and explore its characteristics This also lets you select the most appropriate measurement range for the main data acquisition and other measurements In addition this is a quick way to verify that the device DC characteristics are good before starting a complete data acquisition and modeling generation The data from this measurement can also be
555. s identified by the higher slot number of the two An Agilent 85123 system can include different combinations of SMUs the standard system includes two SMUs one Agilent 41421B medium power SMU and one Agilent 41420A high power SMU The medium power SMU is factory installed in slot 1 and is initially identified in the IC CAP software as MPSMU1 The high power SMU is installed in slots 2 and 3 initially identified as HPSMU3 The ground unit is identified as GNDU It is generally more convenient to assign unit names to the SMUs that identify their purpose in a device measurement depending on the bias connections at the device terminals and the type of device you are modeling Instrument Library Instrument List k An Hi ltron 366 Netwo HP357 Network HP8S18 Network n Hn A An A An A An A HP8702 Network HP8719 Network HP8720 Network HP8722 Network An HP8753 Network r a a a na lyze i a a Rebut ld 6 gt 3JU Networ nal HP4141 DC Source Moni ti HP4142 Medular OC Sour HP4145 Semiconductor P HP4155 Semiconductor P DeleteAll Delete C onf igure In configuring IC CAP to recognize the system hardware you need to set the SMU names used in software to identify the SMU connections at the measurement terminals In a FET measurement the SMUs are identified as VG gate supply and VD drain supply Ina BJT measurement the SMUs are identified as SMU1 and SMU2 corresponding to the network analyzer test po
556. s than 0 25um The following figure shows the influence of the geometrical channel width reduction WINT on the drain current of a narrow channel transistor while Channel Width Reduction dW as a Function of Channel Width W represents the channel width reduction according to the previous equation Influence of Channel Width Reduction on the Drain Current 127 MOSFET Models J d s CE 6 id vm 9 va CE 8 Channel Width Reduction dW as a Function of Channel Width W OW CE 9 calle r I I i r Wdes LE 6J Drain Current Single Equation for Drain Current In contrast to former implementations of the BSIM3 model the drain current is represented through a single equation in all three areas of operation subthreshold region linear region and saturation region Due to this single formula all first order derivatives of the drain current are continuous which is an important prerequisite for analog simulations In the case that no parasitic drain source resistance is given the equation for the drain current is given below Drain Current Equation 7 y fy ___ are _y 1 gsteff U 2V an dseff eff I u fE 7 ds0 eff oxL 7 i dseff E sath This equation is valid for all three regions of operation of the MOS transistor because the voltages at drain gate and bulk are replaced by effective drain voltage Vy o the effective gate voltage Vostetf and the effecti
557. s using least squares fitting The DUTs at the non nominal temperatures are then resimulated with the new parameters optimize_temperature_coefficients Calls the optimization sequences in extract all_temp_ext to optimize the temperature coefficients for all the devices measured at the non nominal temperatures Each such device is resimulated with the new parameters when the optimizations are complete display_parameter_vs_temperature_plots Displays plots of specified parameters versus temperature quick_extraction_one_dut This asks the user to specify a DUT number one of the 356 MOSFET Models devices already specified in setup and then performs the quick extraction procedures on these The measurements are performed in the gquick_ext DUT and the miniset parameters extracted are placed in this DUT also Therefore performing a quick extraction on a device will overwrite any data or miniset parameters in quick_ext associated with a previous device Therefore performing a quick extraction does not create any new data structures in IC CAP This choice to consider the quick extraction data as temporary and not to create new data structures for every device measured was made to keep the quick extraction time to a minimum and to avoid the possibility of generating an unmanageable model size when IC CAP is being used to gather volume data i e hundreds or more model sets for statistical analysis test_quick_ext_with_ideal_pars This macro is use
558. s well as gate and drain There is also a sidewall source drain to substrate under the buried oxide fringing Capacitance Coidesw included A parasitic MOS capacitor between source drain and substrate Cog e with the buried oxide as dielectric For FD and PD devices a front to backgate coupling charge has been included which is only effective at the fully depleted drain side region in a PD device A coupling charge between body and backgate Q sicv For SOI MOSFET s correct modeling of charges is even more important as for bulk MOSFET s The transient behavior in the floating body mode depends heavily on capacitive currents as well as external bias voltages If the thickness of the silicon film on top of the buried oxide is comparable to the depletion width source drain to body capacitance becomes a strong function of backgate bias Reference2 The capacitance in a SOI MOS transistor can be divided into the following parts Junction capacitance Ciswg between source drain and the body region Sidewall source drain to substrate capacitance Area capacitance between source drain bottom and substrate with the silicon oxide as dielectric Capacitance of the extrinsic MOS transistor which consists of Capacitance of the intrinsic MOS transistor in the region between the metallurgical source and drain junction when the gate is at flat band voltage These different parts of the capacitance of a SOI MOS transistor are shown below The f
559. sed in HISIM 2 5 1 e Additional and removed Parameters from HISIM2 4 1 to HISIM2 5 1 e Instance Parameters e Basic Device Parameters e Saturation Velocity Parameters e Quantum Mechanical Effect Parameters e Poly Silicon Gate Depletion Effect Parameters e Short Channel Effect Parameters e Mobility Parameters e Channel Length Modulation Parameters e Narrow Channel Effect Parameters e Small Size Effect Parameters e Substrate Current Parameters e Subthreshold Swing Parameters e Impact ionization Induced Bulk Potential Change Parameters e Gate Leakage Current Parameters e GIDL Current Parameters e Conservation of the Symmetry at Vds 0 for Short Channel MOSFETs Parameters e Smoothing Coefficient between Linear and Saturation Region Parameters e Source Bulk and Drain Bulk Diodes Parameters e 1 f Noise Parameters e DFM Support Parameters e Non Quasi Static Model Parameters e Capacitance Parameters e Parasitic Resistances Parameters e Binning Model Parameters Instance Parameters Parameter Name Description L W AD AS PD PS NRS NRD XGW XGL NF NGCON RBPB RBPD RBPS RBDB RBSB SA SB SD TEMP DTEMP NSUBCDFM SUBLD1 SUBLD2 gate length Lgate gate width Wgate drain junction area source junction area drain junction perimeter source junction perimeter number of source squares number of drain squares distance from the gate contact to the channel edge offset of the gate length number
560. sfet Extraction of Model Parameters mosfet Binning of Model Parameters mosfet Importing older version BSIM3v3 Files mosfet 120 MOSFET Models The Unified I V Model of BSIM3v3 For a complete summary of all equations of the BSIM3v3 2 4 model please refer to the original documentation from University of California at Berkeley see BSIM3v3 References mosfet to order this paper The main equations of the BSIM3v3 3 0 model are shown together with a graphical representation for a better understanding of the model Threshold Voltage The threshold voltage is one of the most important parameters of deep submicron MOS transistors and is affected by many different effects when the devices are scaled down into the region of 0 1 microns The complete equation of the threshold voltage in BSIM3v3 3 0 is given below Vth VTideal tha t AM tay Ah AT tha t Aths Atho The different parts of this complex equation are expressed by the following sub equations in more detail Ven Ytho 1 J9 far S ee S j gt _ F K I 1 s bseff 2 ae bseff K Tox f Nk t E h 1 co 1 jb Toxm N Log is L L amp ff j eff DyT1 2 Dyr 1 J Wn eff Wafi eff DyTiw 1 DyTiw AE DP ytow 2e Vi T HE FE F TE gt ies bseff yt Wy S i i L ln fff p ff l P subFio D ubt j he e E tao Etab bsefP ds Ideal Threshold Voltage The basic equation of the threshold voltage is V E
561. sg6 If the variable MESSAGE is activated on the Options page those messages are displayed in a box In any case the messages are written to the file log_fail txt Example if val action error then if val failcode VOFF_NFACTOR_DataRange then msg1 Failure in Large idvg extr_VOFF_NFACTOR msg2 PlotO_x1 or PlotO_x2 or PlotO_y1 or PlotO_y2 is not defined in region selection msg3 Make sure the region selection sets those boundaries 97 MOSFET Models end if DC HTML The folder HTML is used to generate a report file in HTML format You can define a headline and comments for the report specify the path to save the report as well as the command to start the browser You can also define the size of plots and the diagram background as it appears in the HTML report Note Generate HTML uses the project mps file project_name bsim _dc_cv_extract mps not the loaded or imported one If you use a path where an HTML project report already exists you will get a warning If the path doesn t exist you will be a prompted to accept creation of the specified directory The following figures show part of a generated HTML report This report could be published over the intranet for use inside your company or over the web for customer use Zoom Detach Print Output Behavior 5 Parameters Transition Frequenc 1 New HTML report Capacitance lif Content tr2_n16_w4 ag Setup ow y Measurement Transco
562. si5 Gielel l9 visits A AeDele Notes Information Initialize Binning n a Extract HTML Options Boundaries Extraction Flow Extraction Intermediate Res A My Scale Extraction Group Available Functions My Scale Extraction Group Project psp_nmos Project directory d ICCAP_Examples User_defined_Functions PSP Status Extend an existing extraction Group Edit the transform defineAddFunctionsToAdmosGroups There is one user defined extended extraction group provided which can be used as a pattern Modify the code of this transform e Change the number of user defined functions to add 2 NoToAdd 2 Define the functions and the group to add to AddFunctToGroup_ID_Group ptrAdd AdMOS_3_ G02 Capacitance Oxide AddFunctToGroup_ID_Func ptrAdd USER_001 O TOXO VFBO User defined ptrAdd ptrAdd 1 AddFuncToGroup_ID_Group ptrAdd AdMOS_3_G46 _ PSP Scale Capacitance Cgg AddFunctToGroup_ID_Func ptrAdd USER_002 E NPO NPL User defined ptrAdd ptrAdd 1 Ly e Definitions of the user defined extension of an extraction groups 87 MOSFET Models IRE fwan egam execuneCuctomearDatiritocie clearCustomerDelinions W PSP_DC_CV_Extract 26 Bille SD Wie S ee aaea 2 A ee Notes Information Initialize Binning n a Extract HTML Options Boundaries y Extraction Capactance Oxide Project drectory G VICCAP_Examples PSP Example e User
563. sind For eynerteehsind dr ru evtracteoinhal 19 Delete and continue Always show this dialogue tenable on Option page Arranging the flow is possible by using the Move Up or Move Down buttons below the Function Flow or by using the icons provided To extract parameters from one flow only Select the desired flow under the Extraction Flow section in the left half of this folder and choose Extract gt Single Extraction Again you will be warned before the selected extraction will be performed To go through the extraction process one step at a time highlight the step and choose Extract gt Step by Step Extraction A dialog box may appear prompting you for input e To automatically extract all parameters using the extraction flows listed under the Extraction Flow section choose Extract gt Automatic Extraction The programmed Extraction Flow will be extracting all parameters defined in the active extraction flow list The programmed extraction flow has to begin with the Reset Parameters step otherwise you will get an error message e In case you would start an extraction of some parameters after you already have extracted some other parameters you are not able to start from the beginning without resetting all parameters including the ones already extracted To re extract or to optimize one parameter after some other parameters are already extracted simply add the desired step in the extraction flow list on a place further down th
564. single temperature It will be copied into each model that exists for a non nominal temperature and the extraction sequences in this setup will therefore modify the variables of the model in which this setup occurs At a model level the variables that represent the temperature sensitive parameters are xVTOR xBETSQ XTHE1R xSLTHE1R xTHE2R xSLTHE2R xTHE3R xSLTHE3R XMOR and xAIR The variable table of single_temp_extract contains the upper and lower bounds that will be used during the optimization sequences The single_temp_extract setup contains the following transforms temp_par_init initializes the temperature sensitive parameters at any temperature to their value at the nominal temperature select_single_temp_model sets MODLEVEL and EQNTYPE so that the single temperature option of the MM9 transform will be used That is to say where most parameters are read from the Parameters table and full geometry scaling is used but where the values for the temperature dependent parameters are read from the variable table of the model that has measurements at a non nominal temperature swapdata is used to transfer setup information mainly bias voltages and temperatures from the MM9 model to any model containing temperature data single_temp_opt controls the optimization sequence for temperature optimizations at one temperature For more information refer to the discussion on single_temp_opt in the section Optimization Transforms and Macros
565. sion coefficient for Drain Emission coefficient for Drain junction xm Junction current temperature exponent coefficient oo 0 of source body junction e Junction current temperature exponent coefficient aba i of drain body junction TPB Temperature coefficient for PB 0 0 v K TPBSW Temperature coefficient for PBSW 0 0 V K TPBSWG Temperature coefficient for PBSWG 0 0 V K TCI Temperature coefficient for CJ 0 0 1 K TCISW Temperature coefficient for CJSW 0 0 1 K TCISWG Temperature coefficient for CJISWG 0 0 1 1 K TVOFF Temperature coefficient of VOFF b 1 1 K TVFBSDOFF Temperature coefficient of VFBSDOFF 1 K Flicker Noise Model Parameters Flicker Noise Model Parameters 224 MOSFET Models Parameter Description Default Value Unit NOIA Flicker noise parameter A NMOS 6 25e41 PMOS ev 1 s 1 EF 6 188e40 m 3 NOIB Flicker noise parameter B NMOS 3 125e26 PMOS ev t s 1 EF 1 5e25 m NOIC Flicker noise parameter C 8 75 eV s 1 EF m EM Saturation field 4 1e7 V m AF Flicker noise exponent 1 0 EF Flicker noise frequency exponent 1 0 KF Flicker noise coefficient 0 0 A Z EF s 1 EF LINTNOI Length Reduction Parameter Offset 0 m NTNOI Noise factor for short channel devices for TWOIMOD 0 1 0 z only TNOIA Coefficient of channel length dependence of total 1 5 channel thermal noise TNOIB Channel length dependence parameter for channel 3 5 thermal noise partitioning Holistic Thermal Noise RNOIA Thermal n
566. sion resistance for both 1 0 intrinsic input resistance and charge deficit NQS models RBPB Resistance connected between bNodePrime and bNode 50 0 Ohm RBPD Resistance connected between bNodePrime and dbNode 50 0 Ohm RBPS Resistance connected between bNodePrime and sbNode 50 0 Ohm RBDB Resistance connected between dbNode and bNode 50 0 Ohm RBSB Resistance connected between sbNode and bNode 50 0 Ohm GBMIN Conductance in parallel with each of the five substrate resistances to avoid 1 0e 12 mho potential numerical instability due to unreasonably too large a substrate resistance RBPSO Scaling prefactor for RBPS 50 0 Ohm RBPSL Length scaling parameter for RBPS 0 0 Ohm RBPSW Width scaling parameter for RBPS 0 0 Ohm RBPSNF Number of fingers scaling parameter for RBPS 0 0 Ohm RBPDO Scaling prefactor for RBPD 50 0 Ohm RBPDL Length scaling parameter for RBPD 0 0 RBPDW Width scaling parameter for RBPD 0 0 RBPDNF Number of fingers scaling parameter for RBPD 0 0 RBPBXO Scaling prefactor for RBPBX 100 0 Ohm RBPBXL Length scaling parameter for RBPBX 0 RBPBXW Width scaling parameter for RBPBX 0 RBPBXNF Number of fingers scaling parameter for RBPBX 0 RBPBYO Scaling prefactor for RBPBY 100 0 Ohm RBPBYL Length scaling parameter for RBPBY 0 RBPBYW Width scaling parameter for RBPBY 0 RBPBYNF Number of fingers scaling parameter for RBPBY 0 RBSBX0O Scaling prefactor for RBSBX 100 0 Ohm RBSBYO Scaling prefactor for RBSBY 100 0 Ohm RBDBXO Scaling prefactor for RBDBX 100
567. so that you can enter values for these extrinsic parasitics based on your knowledge of the device or on estimates or on measurements of the open fixture In addition you can set limits by entering minimum and maximum values for each parameter Parameter values that are outside their limits are clamped to their minimum or maximum values Model Parameters Table it Model Parameters Model Variables Macros Param Nave Value tin tan opds c 0 000 epgrl c 0 000 apys a 0 000 ls_eot 1 0 000 last 0 000 la et 1 0 000 To access the Parameters table click on the Model Parameters tab To change a value in the Parameters table move the mouse pointer over the current entry and click left to highlight it then type in a new value The default for all the c values is 0 000 A reasonable capacitance value to enter for a pad on a wafer might be 50 fF The _ext values are the bond inductances for the three terminals The default value for all three is 0 000 If you Know or can estimate the bond inductances for your device based on wire length or grid size enter appropriate values Extracting the Measurement Port Series Resistances This procedure need be performed only following initial installation of the system or if changes are made in the system hardware The procedure measures a short circuit at the normal device measurement interface plane IC CAP controls the DC source monitor to force a gate current and monitor the gate 323
568. specify instrument calibration For the most accurate results calibrate the instruments before taking IC CAP measurements Typical DC and cv instrument options are e DC measurements are generally taken with Integration Time Medium e CV measurements in the femtofarad region usually require High Resolution Yes and Measurement Freq kHz 1000 Measuring Instruments Ensure that the measuring instruments specified by unit names in the inputs and outputs are correctly connected to the DUT Refer to Instrument to Device Connections mosfet for a list of nodes and corresponding measurement units The quality of the measuring equipment instruments cables test fixture transistor sockets and probes can influence the noise level in the measurements and extracted parameter values For some measurements the instruments or test hardware must be calibrated to remove non device parasitics from the DUT For MOS devices stray capacitance due to probe systems bond pads and so on should be calibrated out prior to each measurement Extracting Model Parameters For a given setup you can find the extraction transforms in the Extract Optimize folder IC CAP s extraction algorithms exist as functions choose Browse to list the functions available for a setup When the Extract command is selected from the setup all extractions in the setup are performed in the order listed in the setup This order is usually critical to proper extraction perfor
569. splayed in a box In any case the messages are written to the file log_fail txt Example if val action error then if val failcode VOFF_NFACTOR_DataRange then msg1 Failure in Large idvg extr_VOFF_NFACTOR msg2 PlotO_x1 or PlotO_x2 or PlotO_y1i or PlotO_y2 is not defined in region selection msg3 Make sure the region selection sets those boundaries end if 2 1 Initializing 2 1 1 Common variable 93 MOSFET Models F_ID A unique ID do not use the string AdMOS For each ID of an optimizer a tuner ID will be generated because every optimizer can be used as a tuner too The tuner ID is the optimizer with an added T This has to be considered when naming the IDs Example Never use UserID1 and UserID1T as well F_Name Name of function start with E for extractions and O for optimizations The generating routine will automatically add a tuner T Note There is a blank before and behind the F_Setup Location of the transform starting with the name of the DUT 2 1 2 Data Source NoData 1 Local variable for the number of data lists 1 to 4 sources can be used F_DataSourceHead ist Headline of the list field where used sources can be selected Only to be configured if more than one source is used NoData contains the number F_DataTargetSetup st ICCAP_ARRAY 1 Must be an array Another setup can be loaded with the same data F_DataTargetSetup st
570. ssage and change the color of the field whose parameter is given an unrealistic value For example if you enter 3 into the EPSROX field this field will be marked with red color and remains red until the value is corrected You are able to add BSIM4 PSP parameters to the Initial Values by clicking Add Parameter inside the Initialize menu You will be prompted with a list of BSIM4 PSP parameters Select the parameters you would like to add and click OK The parameters are added and you are able to enter initial values as desired The Model Flags section is used to set BSIM4 PSP model flags The fields only enable settings as defined in the BSIM4 PSP model and are predefined to standard settings There is a field defining the symmetry of the drain and source areas Check the appropriate box es if drain and source are processed using the same dose of implantation as well as the same geometry and therefore the parameters are equal for drain and source areas Note Since most MOS processes use symmetric source and drain processing parameters there is no need to extract the parameters for the bulk source or bulk drain diodes separately Instead check that the symmetry fields and the respective parameters are set equally Only for unsymmetrical processes which could be modeled in BSIM4 PSP the fields remain unchecked and a separate parameter set will be extracted for bulk source and bulk drain diodes HiSIM_HV Initialize Folder for the
571. st Calibration for an Agilent 8753 Based System If you are using an Agilent 8753 based system follow the steps below 330 MOSFET Models 1 On the network analyzer press LOCAL to gain front panel control Press PRESET to return to a known standard state 2 If you are using a system with the 6 GHz receiver option and you wish to measure in the 3 GHz to 6 GHz range press SYSTEM gt FREQ RANGE 3GHZ6GHz 3 To define a linear frequency list on the network analyzer press MENU gt SWEEP TYPE MENU gt EDIT LIST gt CLEAR LIST gt YES gt ADD A default frequency list segment is presented 4 To change the segment to your chosen frequency range press SEGMENT START and use the numerical keypad to set the start frequency ending with one of the terminator keys such as M y at the right side of the keypad Similarly press STOP and set the stop frequency Note Use the SEGMENT START and STOP softkeys not the START and STOP hardkeys on the front panel 5 Press SEGMENT NUMBER of POINTS and enter the number of frequency points to be measured across the range then press the x1 terminator key Keep in mind that the fewer the number of points the less time the measurements take 6 Press DONE to return to the edit list menu The segment you just defined is listed on the screen 7 Press DONE to return to the sweep type menu Press LIST FREQ gt SINGLE SEG SWEEP to activate the frequency list mode and set the analyzer to sweep the
572. standard IC CAP values and the changed values are used for this extraction session o The Parameters field of this folder enables you to add parameters to this step using the blank parameter field below the predefined parameters used in this step If you enter a valid BSIM parameter and press enter the value of this parameter as has been extracted so far will be shown in the middle column o If you check the Save actual Optimizer Min Max values check box a new invocation of IC CAP will use the changed boundaries otherwise the standard values will be used again o You can enter an exclamation mark in front of a parameter to temporarily deactivate a parameter without removing it from the list Using the Tuner feature this folder will change the name from Extract or Optimize to Parameter The Parameters field of this folder has the same function as has been described for the optimizer above The third folder now changes from n a to Tuner It shows the parameter tuner sliders for interactive tuning The results of changing the slider positions will be shown immediately inside the plots Again you are able to store results under predefined names You can use the results of this step or go on without the results of the tuning step Plots Click Open Display from the Plots menu The Multiplot window opens displaying the plot data Data Display 56 MOSFET Models ay Diagrams 1 1 File Options Optimizer Plots Windows Help P
573. step size for substrate current curves Vds value for subthreshold curves Vds value for subthreshold curves Vds value for subthreshold curves Vds for linear region curves Array size for the data in extract par_vs_L Array size for the data in extract par_vs_W Array size for the data in extract par_vs_R Low current limit used for determining optimization targets and the minimum current predicted by MM9 15 97 10 12u 61 47 50 07m 907 0n 7 211u 31 48 877 5n 923 4n 755 6m 114 4n 12 17n 15 00n 100 0p 0 000 0 000 Default Value 4 210 10 00u 1 16 22 22 5 000 14 00 2 20 00 26 00 18 00 22 00 HP4085B 1 000 500 0f 1 2 000 1 5E 13 100 0m 0 000 2 000 5 000 100 0m 2 000 3 500 5 000 100 0m 600 0m 300 0m 50 00m 4 000 4 500 5 000 100 0m 1 000 3 000 5 000 100 0m 7 000 5 000 3 000 500 0f Allows equation simplification for linear parameter extraction 0 0 Use normal parameter extraction equations 1 Usea simplification to help linear region extraction 2 Use the 346 MODLEVEL TYPE TEMP MULTDUT PROBETYPE NUMTEMP GEOMFILE TEMPFILE LIN_NUMVBS DISPLAYPLOTS DATASOURCE SWAPDIRECTION TA_SWAP NUMTPLOT GDSMIN VBSTOP LIMIT_FLAG ERROR THE3_STORE RECALC VSBREF VT_RANGE K_MODEL DOBODY VGATE1 VGATE2 VGATE3 VSB11 VSB12 VSB21 VSB22 VTHMAX VDSPRG VDSSTH1 VDSSTH2 VGATST1 VGATST2 VSBSTH1 VSBSTH2 NUMIDS NUMGDS MOSFET Models
574. surement Module Folders Notes mosfet Temperature Setup mosfet Switch Matrix mosfet Device Definition mosfet Options mosfet How to Import measured Data not compatible with the IC CAP format e Import Wizard mosfet See Also Using the MOS Modeling Packages mosfet Introduction to MOS Modeling Packages mosfet Data Structure used for the MOS Modeling Packages Getting Started with MOS Modeling mosfet RF Measurement mosfet Extraction of DC and CV Parameters mosfet Extraction of Parameters for the RF Models mosfet Project Notes The notes folder is provided to store notes you take on a specific project You can enter general data like technology used to produce this wafer as well as lot wafer and chip number There is a field to enter the operator s name and the date the measurement was taken Space has been provided to enter notes on that project Notes entered into the measurement module will be transferred to the Information folder inside the DC_CV_Extraction modules Other DC CV Measurement Module Folders e Temperature Setup mosfet e Switch Matrix mosfet e Device Definition mosfet e Options mosfet 13 MOSFET Models Temperature Setup Use this folder to define measurements at specified temperatures Basically the measurement of all DUTs is performed at SPICE default temperature TNOM which is set to 27 Celsius Note To change the default value of 27 C to represent your measurem
575. surement of parasitic elements to de embed them from the measurements on the test device A principle layout of such a test structure is shown in the following figure References mosfet 9 Layout of a Test Structure for a MOS Transistor eliminate parasitic Reference plane of NWA port 1 through de embedding Source Substrat Ground n m Gare m Sm Signal Ground rce Subs rce Subs Reference plane of circuit library dement The MOS transistor is designed as a finger structure with four common gates three source areas and two drain areas In summary this compact layout results in a very wide gate width which can drive a high current Ijs The probes are connected in a Ground Signal Ground scheme according to the recommendations in References mosfet 4 As it is shown above the calibration plane of the network analyzer is at the end of the probe head This means the transmission lines that connect the DUT with the probe head must be modeled and their effect must be de embedded from the measured data of the DUT This can be done by measuring an OPEN and a SHORT test device without a DUT and using these measurements to de embed the parasitic influence of the pads The following two figures show the design of these OPEN and SHORT test structures Both of these test structures will be used for a simple and effective de embedding procedure OPEN_SHORT as will be shown later Additional test devices
576. t a Detach Organize Active Setup PSP_DC_CV_Extract C_Oxide User_cg_vg Repeat the procedure for the DUT Scaling Mind the naming conventions described above Add a new setup named User_execute in the DUT Scaling Copy the transform extr_NPO_NPL from the setup execute to the new setup e Change the code of the new transform extr_NPO_NPL e Use a different ID from the ID of function opt_TOXO_VFBO e Function definitions of the user defined function extr_NPO_NPL 80 MOSFET Models PSP_DC_CV_Extract PSP_DC_CV_Extract Scaling User_execute is Active 25 File Edit Measure Extract Simulate Optimize Data Tools Macros Windows Help e lt gt KIC PS S E OSSD L S la S DUTs Setups Cucu Model Parameters Model Variables Macros Model GUI Items Measure Simulate Instrument Options Setup Variables Extract Optimize Plots Setup GUI Items Ewou Select Tandem Function Figganl LL Boe OC_Tiansisto STI STi Large SA Nasrow_SA v G gt Pens owe Active Setup PSP_DC_CV_Extract Scaling User_execute Before you can execute the steps described above the paths to plots data etc must be corrected as shown in the two figures below e F_ParRef execute_TOXO_VFBO_opt Use the name of the transform of the new optimizer You can use an existing optimizer In this case you need to correct the path e
577. t data from a known set of SPICE parameters This feature might be especially useful to convert parameters of other models into BSIM4 parameters by loading the created measurement data into the extraction routines and extract BSIM4 parameters e To see the diagrams of what has just been measured use the Display Plots icon or Data gt Display Plots You will see a Multiplot window with different folders Using those folders you can change the plot types as well as the devices whose plots are to be shown This is a convenient way to detect measurement errors before starting the extraction routines If you are satisfied with the data plots you ve just measured choose the Close Plots icon to close the displayed plots of measured data The Data menu has an entry Check Data consistency to see if measurement errors have occurred If you select this menu item a Multiplot window opens for a quick consistency check If errors are detected an error window opens and gives you a hint on what might be inconsistent within your measurements Select one of the available plots and use the Plots gt ZoomPlot gt SelectedPlot menu item to see a zoomed display of the saturation current of all measured devices for example The plot to be displayed should look similar to the one shown below For an explanation of this consistency check feature see Consistency Check of DC measurement data for multiple measured devices mosfet ldsat M 33 Wdes 10 00u Ldes 2
578. t parameters for source and drain sides are introduced which are used to precisely model different doping concentrations and so on The model flag CAPMOD allows three values CAPMOD O uses piece wise and simple equations whereas with CAPMOD 1 and 2 uses smooth and single equation models For CAPMOD 0 VTH is taken from a long channel device for CAPMOD 1 and 2 VTH is consistent with the BSIM4 DC model The overlap capacitance model uses a bias independent part to model the effective overlap capacitance between gate and heavily doped source drain regions and a gate bias dependent part between the gate and the lightly doped source drain regions Fringing capacitances between gate and source as well as gate and drain are modeled bias independent Intrinsic Capacitance Modeling All capacitances in Intrinsic Capacitance Model formulations are derived from terminal charges instead of terminal voltages to ensure charge conservation Long channel device models assume the mobility to be constant and no channel length modulation occurs However with shrinking device dimensions velocity saturation and channel length modulation are to be considered to accurately model device behavior For capacitance modeling in BSIM4 a drain bias is defined at which the channel charge becomes constant to T NOFF n TS g CL Anyi CV l active Vasat CY 7 NOFF n cg Og VOFFOY i aferan For capacitance mod
579. t Default SAREF Reference distance between OD edge to poly from m 1E 6 1E a one side i SBREF Reference distance between OD edge to poly from m 1E 6 1E other side 9 WLOD Width parameter im 0 ie ie KUO Mobility degradation enhancement parameter Im 0 i ihe KVSAT Saturation velocity degradation enhancement m 0 1 k parameter TKUO Temperature coefficient of KUO p 0 i LKUO Length dependence of KUO imLLODKUO 0 WKUO Width dependence of KUO imWLODKUO 0 PKUO Cross term dependence of KUO m LLODKUO WLODKOU 0 ies LLODKUO Length parameter for mobility stress effect 0 lo Wo WLODKUO Width parameter for mobility stress effect p 0 lo KVTHO Threshold shift parameter vm 0 j LKVTHO Length dependence of KVTHO mLLODVTH 0 fe Ale WKVTHO Width dependence of KVTHO mWLODVTH 0 e PKVTHO Cross term dependence of KVTHO im LLODVTH WLODVTH 0 LLODVTH Length parameter for threshold voltage stress effect 0 lo WLODVTH Width parameter for threshold voltage stress effect p 0 lo STETAO ETAO shift factor related to threshold voltage im 0 LODETAO ETAO shift modification factor p l1 lo l e Back to PSP Characterization mosfet 284 MOSFET Models Extraction of Parameters using the Local Global approach Because of correlations you should not derive all local parameters for a specific device simultaneously The model developers outline a practical extraction sequence Th
580. t Invokes the miniset extraction sequence for one device It is a special case of the extract_all_minisets macro extract_all_minisets Controls the miniset extraction for all the devices measured at the nominal temperature Miniset extraction consists of a series of optimizations that act on the miniset parameters These miniset parameters are stored as DUT variables in the individual DUTs The template for the extraction sequence is held in the setup extract single_ext As the miniset parameters for each DUT are being extracted the setup extract single_ext is first copied into the DUT The optimizations are then performed and the single_ext setup is then deleted from the DUT This procedure was implemented to prevent multiple copies of what should be the same extraction sequence extract_maxiset Invokes the extraction of the maxiset parameters i e the normal MOS Model 9 parameters at nominal temperature First each of the miniset parameter sets is written to a file whose name is given by the variable GEOMFILE and then the transform MM9_GEOMSCAL is called This reads the miniset parameters from the file just created and performs a least squares fitting to obtain the maxiset parameters This function writes the new parameter values into the parameter list and creates plots in the par_vs_L par_vs_W and par_vs_R setups of extract showing the variation of the miniset parameters with geometry and the fitting of this variation achieved by the maxiset p
581. t channel body effect VNSUB L Effective doping bias dependence V 0 parameter VNSUBO G Effective doping bias dependence V 0 parameter NLSP L Effective doping bias dependence V 0 05 1E 3 parameter NLSPO G Effective doping bias dependence V 0 05 parameter DNSUB L Effective doping bias dependence V 1 0 0 parameter DNSUBO G Effective doping bias dependence V 1 0 0 parameter pee dt tert et DPHIBO lG Geometry independent offset of Vv E DPHIBL Length dependence of DPHIB p f DPHIBLEXP Exponent for length dependence of DPHIB DPHIBW G Width dependence of DPHIB E 0 f o DPHIBLW lG Area dependence of DPHIB p f DELVTACO lG Geometry independent part Vv ee DELVTACL lc IL Length dependence Vv g a DELVTACLEXP lG Exponent for length dependence E DELVTACW lG Width dependence Vv 0 p Loo DELVTACLW lG Area dependence Vv Nol Gate poly silicon doping m 3 1E26 0 alee independent gate Re 3 1E26 i polysilicon doping Length dependence of gate poly e ae doping ier IL Interface states factor 0 lo p aoa E E EE EE EE E 273 MOSFET CTO Geometry independent part of 0 interface states factor CT Length dependence of interface ee i CTLEXP Exponent describing length dependence of interface states factor CT CTW G Width dependence of interface 0 ce CTLW lc Area dependence of CT E 0 k TOXOV L Overlap ox
582. t group contains flags to select certain modes of operations and user definable model parameters For more details about these operation modes refer to the BSIM3v3 manual References mosfet 1 Main Model Parameters Parameter Description Default Value Unit NMOS PMOS Threshold Voltage VTHO Ideal threshold voltage 0 7 0 7 V Ki First order body effect coefficient 0 5 y0 5 K2 Second order body effect coefficient 0 5 K3 Narrow width coefficient 80 0 K3B Body effect coefficient of K3 0 0 1 V WO Narrow width parameter 2 5E 6 m NLX Lateral non uniform doping coefficient 1 74E 7 m VBM Maximum applied body bias in VTH calculation 5 0 V DVTO First coefficient of short channel effect on VTH 2 2 DVT1 Second coefficient of short channel effect on 0 53 VTH DVT2 Body bias coefficient of short channel effect on 0 032 1 V VTH DVTOW First coefficient of narrow channel effect on 2 2 VTH DVT1W Second coefficient of narrow channel effect on 5 3E6 VTH DVT2W Body bias coefficient of narrow channel effect 0 032 1 V on VTH ETAO DIBL coefficient in the subthreshold region 0 08 ETAB Body bias for the subthreshold DIBL effect 0 07 1 V DSUB DIBL coefficient in subthreshold region DROUT Mobility UO Mobility 670 250 cm2 Vs UA First order mobility degradation coefficient 2 25E 9 m V UB Second order mobility degradation coefficient 5 87E 19 m V 2 UC Body effect of mobility degradation 4 65E 11 m V 2 Drain current
583. t name as frie entered in the WaferPro configuration The wafer name FRIE_WAF1 is defined in the Configuration gt Bench view The AdMOS directory is added to store the data files for the Prj_N11 die Die_X 3 Y3 project 41 MOSFET Models t Open Project E 4 In BSIM4_DC_CV_Measure model choose File gt Open and open the project Prj _ N11 While opening the created measurements with the DC_CV_Measure model additional checks are performed and required settings are added Now you can view the measured diagrams imported through WaferPro in the DC_CV_Measurement modules You can save the project and continue with the Extraction of Parameters See Also Using the MOS Modeling Packages mosfet DC and CV Measurement mosfet RF Measurement mosfet Extraction of DC and CV Parameters mosfet Extraction of Parameters for the RF Models mosfet 42 MOSFET Models RF Measurement This section provides information on the RF measurements using the BSIM3 BSIM4 and PSP Modeling Packages The RF module GUI is divided into a number of folders for each task The top row icons are similar to DC and CV measurement module For information on the function on each folder for the specified task refer to DC and CV Measurement mosfet RF Measurement Modules The following topics are included in RF Measurement Module e RF Notes mosfet e RF Measurement Conditions mosfet e De embedding mosfet e DUTs mosfet e RF Options mosfet
584. t parameters 0 no body effect parameters are extracted 1 body effect parameters are extracted First gate overdrive voltage Second gate overdrive voltage Third gate overdrive voltage 1st Vsb 2nd Vsb 3rd Vsb 4th Vsb The maximum absolute value of threshold voltage anticipated for the device under test The drain voltage to be used during linear region extractions Subthreshold Region Variables for Quick Extraction 1st Vds 2nd Vds Offset from threshold voltage of 1st Vgs bias Offset from threshold voltage of 2nd Vgs bias 1st Vbs 2nd Vbs Saturation Region Variables for Quick Extraction Number of points chosen to optimize with respect to ids Number of points chosen to optimize with respect to gds 1 1 000 21 00 N M 2 000 mm9_geompars mm9_temppars 6 000 N 100 3 000 1 000p 5 0 0 6 1 5 3 5 0 3 0 15 0 1 0 15 0 2 347 MOSFET Models VSBSAT Vbs for saturation measurements 0 DVDGDS The increment in drain voltage to be used when measuring output 0 05 conductance Weak Avalanche Variables for Quick Extraction VSBWA Vbs for weak avalanche measurements 0 VGSWAI1 Offset from threshold voltage of 1st Vgs 0 75 VGSWA2 Offset from threshold voltage of 2nd Vgs 0 5 VGSWA3 Offset from threshold voltage of 3rd Vgs 1 5 VDSWA1 1st Vds 5 VDSWA2 2nd Vds 6 5 QTRANS_NAME Holds the name of the transform in quick_ext store which can be quick_extraction_setup used to set the variables associated with qu
585. t parameters from one flow Select the desired flow under the Extraction Flow section of this folder and choose the Single button Only the selected extraction will be performed The status of extraction is visible in the status field This field shows a if extraction of this parameters is not completed yet or done if the parameters from this step are extracted e To go through the extraction process one step at a time highlight the step then choose Step by Step A dialog box may appear prompting you for input e To automatically extract all parameters using the extraction flows listed under the Extraction Flow section Choose Automatic The programmed extraction flow will be extracting all parameters defined in the active extraction flow e All warnings and errors during the extraction process are written to the failure log which is opened using the Failure Log button If you would like to clear the status of extraction use Clear Status Note Already extracted parameters are reset to defaults You can add steps to the extraction flow by clicking the Add button on the left side of the folder under the section Extraction Flow You will be prompted for an extraction to add Select the desired extraction and choose Add on the Add Extraction folder Change the flow of extraction by using the Move Up or Move Down buttons to move a selected extraction routine one step up or down The Default button restores the order of parameter extr
586. t specified Channel Width Reduction Used to determine the effective channel width This parameter is assumed to be O in SPICE Metallurgical Junction Depth Defines the distance into the diffused region around the drain or source at which the dopant concentration becomes negligible Used to model some short channel effects Threshold Related Effective Fast Surface State Density Used to determine subthreshold current flow Not valid for extracting simple linear region classical parameters Effective Surface Charge Density Used to calculate threshold voltage when Vto is not specified Substrate Doping Concentration Used in most calculations for electrical parameters It is more accurate to specify Vto rather than deriving it from NSUB However NSUB should be specified when modeling the back gate bias dependency of Vto Width Effect on Threshold Voltage Used in LEVEL 2 and LEVEL 3 models to shift threshold voltage for different channel widths Static Feedback Used in LEVEL 3 model to decrease threshold for higher drain voltage Bulk Threshold The proportionality factor that defines the threshold voltage to backgate bias relationship Used in the derivation of Vto Ids and Vdsat If not specified in LEVEL 2 and LEVEL 3 models it is computed from NSUB Extrapolated Zero Bias Threshold Voltage Models the onset of strong inversion in the LEVEL 1 model Marks the point at which the device starts conducting if weak inversion current
587. t will show the new extraction region the data points inside the extraction region will be used for optimization Optimizer E UOQ_UA_UB_EU_UC with an additional extraction region 76 MOSFET Models zm InteractiveP lot 1 3 File Options Optimizer Plots Windows Help Id f Vg Vb low Vd al EI Functions Devices Optimizer PO Region Boundaries g show Calculate and show regions Edit Calculation of regions Optimizer Features Algorithm Levenberg Marquardt M Error Relative sim meas meas v b id m id s E 6 gm m s E 6 oo oo wn oO Parameters 0 i 0 ai 10 05 00 05 10 15 20 40 05 00 05 10 15 20 a ls S48 N_ 9 000 vb O0 000 V wg 1800 V d2id 0 000 prcecacnane Name Min Value Max i vo 1 00000m 42 74m 200 000m UA 1 00000u 180 3p 1 00000u uc 100 000m 62 42m 100 000m UB 1 00000p 5 608E 0 1 00000p 1 00000f 1 00000H_ L d2id_dvg m s E 6 a Save actual Optimizer Min Max values and use them instead of the global Min Max values 05 00 05 10 15 20 vg E 0 Extraction Step Large Basic Vth Mobilty Function O Uo UA UB EU UC Save gt Adding a Parameter Select the transform opt_UO_UA_UB_EU_UC DUT Large Setup idvg Add an additional parameter to the existing parameters by appending F_ParName 4 DELTA Increase the number of elements in the ICCAP ARRAY F_ParName
588. t with the left mouse button You can also select one curve of the chosen plot to be enhanced for reading voltages or currents from specific data points Those currents and voltages are displayed above the diagram for the selected and marked data point You can either select the devices to be viewed by clicking on the device name inside the Select Device area or you can click the select button to select the devices from the Select Devices window as shown below There are the short the small the narrow and the large devices selected 45 Select Devices Winger urn Additional LW Scale LW Scale LW Scale Li Scale LW Scale LW Scale 0 25 Lw Scale LW Scale C Only 54 ref C Only WPE ref Choose the devices you would like to look at and click OK The plot window will be updated with the diagrams of the devices selected You can change the default axis settings by a number of math operations To choose a math operation click on the arrow inside the math field of a specific axis Select Output Axis Scaling _ Math vd Linear v Axis Scaling Math Id vi Linear MLW v 2 Axis Scaling v Linear v Select Device dvidx N_ W10u0_L10u0 fd dx N_WOu25_L10u0 dvd N_W10u0_Lou18 dv idx N_WOu25_LOu16 dxfd 2 N_W10u0_Liu0 dxjdv N_W10u0_LOu40 d idx N_W10u0_LOu25 N_Widu0_LOu60 Note Be aware that derivatives of functions need a number of data poi
589. table CJSR_MIN CJSR_MAX PS_MIN PS MAX VDSR_MIN VDSR_MAX The data limits are controlled by the variables which are also in the model variables table CV_VMIN CV_VMAX cjgvn A transform that extracts and holds the normalized gate sub region contribution to capacitance from the measurements in the area cv locos cv and gate cv setups set_cjgr A transform that makes an initial approximation to the parameter CJGR by setting it to the value of cjgvn at the point where the anode voltage is closest to zero cjgvn_sim A transform that calls JUNCAP to evaluate the gate sub region component of capacitance fit_cjgvn An optimization definition that causes the parameters CJGR PG and VDGR to be optimized with respect to the normalized gate sub region Capacitance The parameter limits are controlled by the following model variables which you can change in the model variables table CJGR_MIN CJGR_MAX PG_MIN PG_MAX VDGR_MIN VDGR_MAX 363 MOSFET Models The data limits are controlled by the following variables which are also in the model variables table CV_VMIN CV_VMAX init_cv_pars A transform to initialize some of the C V parameters before optimization begins The parameters initialized are VDBR VDSR VDGR 0 75 PB PS PG 0 4 opt_all_cv An optimization definition that causes all the C V parameters to be optimized with respect to the measured data in the area cv locos cv and gate cv setups The parameters optimiz
590. tai s macro cap This output holds the measured capacitance cap_sim This transform calls JUNCAP to evaluate the simulated capacitance make_cv_data This transform is used for making synthetic data for demonstration purposes It performs a model evaluation using the existing parameter set by calling cap_sim and then copies the resulting simulated data into the m part of the cap output This macro assumes that the MOS Model 9 function MM9_COPY is available connect_cv Modify this transform to enable automatic connection to the area DUT for C V measurements cv_plot This is a plot definition showing measured and simulated C V data fwd_iv This setup contains the measured and simulated forward I V data It consists of the following va vk These inputs define the anode and cathode voltages for forward I V measurements The variables FIVSTART FIVSTOP and FIVSTEP control the voltage sweeps id The output current id_sim A call to JUNCAP to evaluate the simulated current make_iv_data A transform to make synthetic forward I V data The function MM9_COPY is used in this transform connect_fiv Modify this transform to enable automatic connection to the DUT for forward I V measurements fwd_ivplot The plot definition for the forward I V data rev_iv This setup contains the measured and simulated reverse I V data It consists of the following va vk These inputs define the anode and cathode voltages for reverse I V measurements The vari
591. tance k RDVDTEMP2 0 Temp dependent resistance self heating effect VBISUB 0 7 Built in potential at the drift substrate junction p RDVDSUB 1 0 Vds dependence of depletion width p RDVSUB 1 0 Vsub dependence of depletion width DDRIFT 1 0E 6 Depth of the drift region m NSUBSUB 1 0E15 Impurity concentration of the substrate p The following parameter settings are used to prevent the modeling of some effects 234 Effect to be excluded Short channel effect Reverse short channel effect MOSFET Models Parameters and Settings SC1 SC2 SC3 0 LP 0 Quantum mechanical effect QME1 QME3 0 Poly depletion effect PGD1 PGD2 PGD3 0 Channel length modulation CLM1 CLM2 CLM3 0 Narrow channel effect WFC MUEPHW WLi 0 Small size effect WL2 0 Model Flags Default values are in bold Flag Name COSYM CORSRD COQOVSM COADOV COOVLP COOVLPS COSELFHEAT COISUB COIIGS COIGIDL COISTI CONQS CORG CORBNET COFLICK COTHRML COTEMP COIGN COPPRV CODFM Values Description uneoro I m N a O Boro WNFO rFOrO rFrOrOoO rFrOoOrorodo rodordod rdo rao FO FO 0 1 asymmetrical LDMOS structure HV MOS structure no contact resistance RS and RD RS RD 0 internal resistance nodes RD 0 analytical description RD 0 both internal nodes and analytical description RS RD 0 external resistance nodes Qover is calculated
592. te Induced Drain Leakage GIDL Parameters AGIDL L GIDL pre factor A V3 0 AGIDLW G Width dependence of GIDL pre A V3 0 ae BGIDL IL GIDL probability factor at TR Vv 41 0 BGIDLO lG GIDL probability factor at TR Vv 41 p STBGIDL L Temperature dependence of V K 0 BGIDL STBGIDLO G Temperature dependence of V K 0 BGIDL CGIDL IL Back bias dependence of GIDL 0 CGIDLO lG Back bias dependence of GIDL 0 p p Charge Model o ee ee Parameters COX L Oxide capacitance for intrinsic F 1E 14 0 channel TT 276 CGOV CGBOV CGBOVL CFR CFRW Noise Model Parameters FNT FNTO NFA NFALW NFB NFBLW NFC NFCLW Other Parameters DTA Parameters for the Source Drain Bulk Junction Model TRJ IMAX Capacitance Parameters CJORBOT CJORSTI CJORGAT VBIRBOT VBIRSTI VBIRGAT PBOT PSTI PGAT Ideal current Parameters PHIGBOT PHIGSTI PHIGGAT IDSATRBOT IDSATRSTI IDSATRGAT CSRHBOT CSRHSTI CSRHGAT XJUNSTI L G L G L G L G L G L G L G L G L G L G L G L G L G L G L G L G L G L G L G MOSFET Models Oxide capacitance for gate drain source overlap Oxide capacitance for gate bulk overlap Oxide capacitance for gate bulk overlap for an area of WEN x LEN Outer fringe capacitance Outer fringe capacitance for a channel width of WEN Thermal noise coefficient Therma
593. ter Default Range Range Description Unit Name min max NFALP 1E 19 contribution of the mobility fluctuation cm s Nene a m of trap density to attenuation coefficient V 1 cm 2 CIT 0 capacitance caused by the interface trapped F cm 2 carriers DFM Support Parameters 242 MOSFET Models Parameter Default Range Range Description Unit Name min max MPHDFM 0 3 3 3 mobility dependence on NSUBC due to phonon mobility Non Quasi Static Model Parameters Parameter Name Default Range min Range max Description Unit DLY1 100E 12 2 coefficient for delay due to diffusion of carriers DLY2 0 7 coefficient for delay due to conduction of carriers DLY3 0 8E 6 coefficient for RC delay of bulk carriers Ohm Capacitance Parameters Parameter Default Range Range Description Unit Name min max pov p i g distance drain junction to maximum electric field f point XQY1 0 0 50n Vbs dependence of Qy Im XQY2 0 0 50n Lgate dependence of Qy im LOVER 30n overlap length Im NOVER 1E19 impurity concentration in overlap region changed cm from 2 5 1 Beta1 a VFBOVER 0 flat band voltage in overlap region changed from V 2 5 1 Beta1 OVSLP 2 1E 7 coefficient for overlap capacitance p OVMAG 0 6 coefficient for overlap capacitance Vv eee p b ra gate to source overlap capacitance ae 1 Fea b p pom gate to drain overlap capacitance a 1 fore i p ma gate to bulk overlap capacitance vai
594. term safe DC operation 1 Select the create_mdl setup 2 Select the Extract Optimize tab and the create_mdl transforms are listed 336 MOSFET Models 3 Select data_acquisition to display the variables used in the data acquisition Variables in the data_acquisition Transform Select Transform function HPRoot_mos_acqd modet_generator Power level 1 000 conpte_pwra I Breakdown 1 000m Min Vd 0 000 Max vd 7 000 Min Vg 0 000 Max Vg 5 000 Min step 200 0m Max step 800 0m Vth 0 000 Delta 1 000 Eps 200 0m Noise thresh 1 000n SHU Compl 1 000 Follow the steps below to enter variable values appropriate for your device Do not change the Function name at the top of the table For Power level enter the total maximum power dissipation value This should typically be 2 watts per mm of gate width for devices up to 1 mm 7 For I Breakdown enter the reverse gate current breakdown value The next four voltage values define hard limits to the measurement domain The voltage values are set well beyond the normal device operating range to explore the device s boundary response If the values are set too conservatively data will not be measured in the nonlinear areas of breakdown and maximum forward conduction If this occurs in the measurement return to this transform and change the voltage values Reduce the minimum values and increase the maximum values e Min Vd should typ
595. th Modulation CLM Through integration based on a quasi two dimensional analysis we obtain y y Vas Viasat J l eff ACLM PCLM 1 FPROUT V 2 gsteff q mi g T V 1 pvaG Se eff Sat l1 Ris Laso f 7 Y asar Esi 104E 0 dseff ef Eat N EPSROX Drain Induced Barrier Lowering DIBL The gate voltage modulates the DIBL effect To correctly model DIBL the parameter PDIBLC2 is introduced This parameter becomes significant only for long channel devices y 2v y eee a ADIBL ii 1 PDIBLCB Vy steff _V A bulk V isat 1 E Kp _ VY 7 9 A bulk Vasat V asteff q f y f 1 PVAG __gsteff sat eff The parameter 9 out is channel length dependent in the same manner as the DIBL effect in VTH but different parameters are used here PDIBLC1 rout f DROUT Teff 2 cosh 2 itd d 6 PDIBLC2 Substrate Current Induced Body Effect SCBE Due to increasing Vds some electrons flowing from the source of an NMOS device will gain high energies and are able to cause impact ionization Electron hole pairs will be 204 MOSFET Models generated and the substrate current created by impact ionization will increase exponentially with the drain voltage The early voltage due to SCBE is calculated by L VASCBE aa PSCBE2 exp 222E ds dsaf If the device is produced using pocket implantation a potential barrier
596. th due to the short channel effect of AV SCE gt ____liv L pvr 2 1 f j 2 cosh Drain induced barrier lowering is modeled the same way the threshold voltage shift due to DIBL is calculated as ETAQ ETAB V5 AV DIBL __ J th F as 2 cosh DSUB Z 1 0 j J DVT1 is basically equal to 1 h 1 2 ETAB and DVT2 represent the influence of substrate bias effects on SCE and DIBL Narrow Width Effect The existence of fringing fields leads to a depletion region in the channel that is always larger as is calculated using one dimensional analysis This effect gains more influence with decreasing channel widths since the depletion region underneath the fringing field becomes comparable to the depletion field formed in vertical direction The result is an increase of Vth The formulation for the narrow width effect is j TOXE i th bs W WO bi eff DVTOW A r 2 gt bi S gt LW DVTIW a SF _ tw cosh r W gt _ drawn eff NF Subthreshold Swing In the subthreshold region the drain current flow is modeled by 1 W ig Eci NDEP f Va d E f i gt a l L N 2 Po f ri eae P h me VOF F on VOF F L eff a n v j t i where 196 MOSFET Models is the thermal voltage VOFFL The expression elt represents the offset voltage and gives the c
597. the basic equation for non uniform doping concentration and for short or narrow channel effects Non Uniform Substrate Doping If the substrate doping concentration is not uniform in vertical direction the body bias coefficient is a function of the substrate bias and the depth from the interface The threshold voltage in case of non uniform vertical doping is V VTHO K1 IOg I t Ni ti bs _ fy K9 Vy JODE Vrs 4 kpT TAT 9 ae ig a PHIN S 10 4g on where 7 The doping profile is assumed to be a steep retrograde and is approximated in BSIM4 For details on how it is modeled see the manual from UC Berkeley BSIM4 References mosfet 1 starting on page 2 2 The model parameters K1 and K2 can be calculated from NSUB XT VBX VBM and so on This is done the same way as in BSIM3v3 Details can be found on page 2 4 of the BSIM4 manual Non uniform substrate doping model parameters Equation BSIM4 Description Default Variable Parameter Value ni intrinsic carrier concentration in the channel region PHIN PHIN Non uniform vertical doping effect on surface 0 0 potential Non Uniform Lateral Doping Pocket or Halo Implant The doping concentration in this case varies from the middle of the channel towards the source drain junctions Shorter channel lengths will result in a roll up of V from the rise of the effective channel doping concentration and the changes of the body bias effect Those effects are consid
598. the body potential is bound to VbsOeff The diode current reduces to zero if Vbs is equal to VbsOeff Modeling the source side diode and BJT currents uses four body to source current components Backward injection current into body to source diode Recombination in space charge region Recombination in the neutral body Reverse bias tunneling leakage current Body Contact Current For a thin silicon film the body resistance is a function of body and back gate bias It approaches infinite if the device becomes fully depleted Therefore the device at full depletion turns into a floating body device Back to BSIMSOI4 Characterization mosfet 298 MOSFET Models Binning of Model Parameters in BSIMSOI4 Binning of model parameters has been described in detail at Binning of Model Parameters mosfet For the BSIMSOI models it is useful to have binning not only for floating but also for fixed devices This feature will be described here To switch ON Binning of Fixed Devices Go to the Binning folder Select from the Menu Binning Use Fixed Devices instead of Float Devices The previously defined Binning configuration will be removed Define Binning Areas Press button Show Devices A window showing the devices defined for the actual project will be opened 48 Devices 17 File Options Optimizer Windows Help M 0 dummy _input 0 000 Y X 5 000u Available_Real_Devices 5 000u 1E 5 y LOG TES L rm LOG wo a C
599. the one shown below Extension values form Unable to render embedded object File icmdl 02 1 33 gif not found If the extension is not activated certain simulators would not be able to simulate devices with L Lmax or W Wmax of certain bins The extension delta values define the extensions from the measured devices This means you must set extension delta values Lmin and Wmin within the range of the minimal measured device otherwise you will get an error message In other words if your minimal measured device uses a gate length of 0 15um the extension in Lmin direction must be set between 0 and 0 149um There is no limit for the extension in the Lmax and Wmax direction If you select one of the defined bins the fields under Devices in Bin lt No gt will become green shaded and will show the name of the corner devices of this bin and the corner geometries At the same time the diagram will show the selected bin boundaries in light blue color Delete Extension You can delete the entered extensions by choosing the menu item Binning gt Delete Extension button The field Parameters to switch off scalable effects is used to set which parameters use the scalable possibilities as defined inside the BSIM4 PSP model and which parameters are prevented from scalable modeling in BSIM4 PSP All deselected parameters are using the extracted values whereas all selected parameters marked with blue background are using default values for binning
600. the present transform apply to a typical 5V process The new quick extraction functions control all aspects of quick extraction that is determining the bias levels to be applied to the device initiating measurements and performing calculations to extract the appropriate parameters MM9_LIN_EXT Performs the linear region parameter extractions MM9_STH_EXT Performs the subthreshold parameter extractions MM9_SAT_EXT Performs the saturation parameter extractions including output conductance MM9_WEAVAL_EXT Performs the weak avalanche substrate current parameter extractions The following arrays in quick_ext store control the applied drain and gate biases vgsids gate voltages for ids measurement vdsids drain voltages for ids measurement vgsgds gate voltages for gds measurement vdsgds drain voltages for gds measurement Note that Vds is never allowed to have a value of less than 0 1V during saturation region quick extraction measurements The dutx DUT The variable table of dutx contains the miniset parameters and the quantities VT1 VT2 and VT3 which are used to store the measured threshold voltages at the three back biases used for the saturation and subthreshold measurements 353 MOSFET Models dutx measure_vt performs a linear region measurement that is Ids vs Vgs for a low value of Vds to determine the threshold voltage of the devices at the three values of Vbs used for subsequent measurements An estimate of these threshold v
601. the setups up or down in their order by using the right mouse button Define Order SEE Setups idvg idvgi idvd_vbmin idve Move Down Measurement Conditions for the idvg setup Polarity NMOS PMOS Current Compliance C Power Compliance PC vd vg vb VS ve v6 Cref o1 fa ooo ca or ray for tay foa ray foa Jta PCref 0 w um gt c Constant v Constant v Constant Constant Constant vi Constant l vi PC idvg YG YB D vS Measure Ig Measure Ib Measure Id C Measure Is Linear v Linear v Linear a v Constant w Start 0 6 Start 0 Start 0 05 value 0 Step o5 Step 0 3 Ji Step 0o35 7 Stop 16 Stop 1 2 Stop 18 a No Pts 149 No Pts 5 l No Pts 6 On that form you can enter the polarity of the devices to be measured and define the conditions for DC measurements as well as to specify current limits for the SMUs compliance settings Add new setups by selecting Measurement from the tree and clicking Configuration gt Add or the Add icon You will be prompted to choose one of the predefined setups idvg or idvd and enter a name for the new setup Now you are able to define the measurement steps for that setup the current as well as the power compliance values Polarity There are polarity buttons to specify whether you are measuring NMOS or PMOS devices Select NMOS or PMOS Our
602. their influence on the device behavior in order to restrict the optimization process to a certain range of data In contrast to the optimization strategy the extraction strategy is strictly based upon the device equations If these device equations are physically oriented as in the case of the BSIM3v3 model for MOS transistors the extraction of the model parameters must give an accurate and realistic representation of the device physics The basic idea of this extraction strategy is to transform measured data into such a form that model parameters of a certain part of the device equations can be derived by mathematical regression methods The extraction routines must therefore incorporate much more knowledge about the model and its behavior Generally model parameters extracted in this way are more realistic and physically oriented However the fitting between the measured and simulated curves can be less accurate than in the case of an optimization because the extraction method gives a realistic physical representation of the device while the optimization only targets a minimum error between measurement and simulations Extraction of Short Channel Effect Parameters DVTO DVT1 shows the principle data flow of such an extraction routine for the short channel model parameters DVTO and DVT1 In this example the threshold voltage V of several test transistors with different gate lengths is determined and stored in an intermediate data array Th
603. threshold optimizations at Vbs OV The subvt1 setup contains the following transforms mm9_ids calls the MM9 transform to evaluate the model current abs_vg is a call to the equation transform to calculate the absolute value of Vgs This is necessary for the plot Jogidvg_vbs which shows the subthreshold current at non zero Vbs values tid_svt generates target current values for subthreshold optimization The main purpose is to eliminate data that could lie on the noise floor It evaluates the transconductance on a log scale and eliminates points that have a transconductance of less than 70 of maximum on the low current side of the maximum point by setting their value to 0 5 IMIN copy_sim_to_meas copies the current generated by the MM9 transform into the measured array It is used for making sample measured data It uses the MM9_COPY C transform which is necessary to enable data to be copied into a measured array set_vth stores the threshold voltage in the setup variable VTH dutx subvt2 subvt3 enable measurement of subthreshold data for non zero Vbs values that are required for the non zero Vbs subthreshold optimizations The subvt2 subvt3 setups contain the following transforms mm9_ids calls the MM9 transform to evaluate the model current abs_vg is a call to the equation transform to calculate the absolute value of Vgs This is necessary for the plot Jogidvg_vbs which shows the subthreshold current at non zero Vbs values t
604. tic Resistance As MOS devices are scaled into the deep submicron region both the conductance g and the current of the device increase Therefore the voltage drop across the source and drain series resistance becomes a non negligible fraction of the applied drain source voltage 131 MOSFET Models The resistance components associated with a MOSFET structure are shown in the following figure These include the contact resistance R opta between metallization and source drain area the diffusion sheet resistance R heet Of the drain source area the spreading resistance Ropread that arises from the current spreading from the channel and the accumulation layer resistance R ccum Resistance Components of a MOS Device Contact Gae Junction Paes Reoraact Rhee These components are put together to form the following equation in the BSIM3v3 x xr la _ Raswl Prog gstepf Prwb Ps Yosef Ps ds T 6 r 10 W fH R The diagram in the following figure visualizes the equation of Rys It should be noted that BSIM3 assumes that the drain resistance is equal to the source resistance This symmetrical approach may cause difficulties if a device with a nonsymmetrical drain source resistance for example a DMOS power transistor should be modeled In this case a scalable SPICE macro model should add the required behavior to BSIM3 Drain Source Resistance Rds as a Function of Vg and Vb 6 8 0 3 l G 1 5 2 0 2 5
605. timate pre condition for its use in a commercial circuit simulator which includes the BSIM3v3 2 model and makes it available to circuit design engineers The BSIM3v3 2 model already consists of a non quasi static model and an accurate Capacitance model which makes it the ideal basis for RF simulations However the description of the resistance behavior of a transistor is very poor In the BSIM3v3 2 model itself no gate resistance is included Due to the nature of the MOS transistor such a resistance cannot be seen in the DC operation region However looking at the real existing poly silicon gates of modern MOS devices there is a resistance which cannot be neglected in AC simulations 3D view of a multifinger SOI MOSFET This resistance R has a major influence on the reflections of an input signal to the gate MOS transistor S11 as is demonstrated below L 6 25um Wringer 1Gum Nfinger 16 S11 with gate Qi Ei 0 O kt N i o a a kf u S11 without gate resistance freq f 1 20 GHz It should be noted that the parameter R in this high frequency model is used to fit the gate input reflection of the MOS transistor Therefore it is very likely that R has a different gate value as the measured sheet resistance of the poly Si gate during process characterization on PCM s using van der Pauw test structures for instance With this approach the model is valid for both the DC and the RF be
606. tion Measurement is being carried out at gate and drain voltages from zero volts upward but parameter extraction will lead to erroneous values RF Extraction Module Folders RF Extract Notes mosfet RF Extract Information mosfet RF Initialize mosfet RF Extract mosfet RF Display mosfet RF Extract HTML mosfet RF Extract Options mosfet RF Extract Boundaries mosfet 109 MOSFET Models See Also Using the MOS Modeling Packages mosfet Data Structure used for the MOS Modeling Packages Getting Started with MOS Modeling mosfet DC and CV Measurement mosfet RF Measurement mosfet Extraction of DC and CV Parameters mosfet RF Extract Display Within this folder you will find fields to select plots for display Display folder mm BSIM4_RF_Extract 12 Fie Iritiakze Extract Plots HTML Options Boundaries Help eo paR xo n ue Notes Information Intistze Extret Display HIML Options Boundaries f Plots p Select Device Plots Singe Transistor 2 Use Actuel Model Parameter St Close Al tr2 ni5 ve Project Example Scale Project drectory jiyusers def udt _ 2009 Status A There are three fields to select models for display on this folder Select Device Use Actual Model Parameter Set or choose one of the buttons to the left of the transistors name for plots to be displayed Open plots for the selected transistor by clicking t
607. tion My C_Oxide Extraction 0 TOXO VFBO User defined T TOXO VFBO User defined Project directory d ICCAP_Examples User_defined_Functions PSP Status 86 MOSFET Models 9 Note The new extraction steps are not available until thecustomer extractions are generated Repeat the procedure for the new scaling extraction group e Assign a different ID MyExtrGroup_ID ptrGr Customer_G02 MyExtrGroup_Name ptrGr My Scale Extraction Group MyExtrGroup_Main ptrGr AdMOS_3_ M06 The user defined extraction can consist of every existing function not only user defined functions MyExtrGroup_Func ptrGr ICCAP_ARRAY 9 MyExtrGroup_Func ptrGr 0 USER_002 MyExtrGroup_Func ptrGr 1 AdMOS_3_193T MyExtrGroup_Func ptrGr 2 AdMOS_3_ 193 MyExtrGroup_Func ptrGr 3 MyExtrGroup_Func ptrGr 4 AdMOS_3_194T MyExtrGroup_Func ptrGr 5 AdMOS_3_194 MyExtrGroup_Func ptrGr 6 AdMOS_3_128 MyExtrGroup_Func ptrGr 7 AdMOS_3_042T MyExtrGroup_Func ptrGr 8 AdMOS_3_ 042 The definition MyExtrGroup_Func ptrGr 3 inserts a blank line MyExtrGroup_Def ptrGr ICCAP_ARRAY 4 MyExtrGroup_Def ptrGr 0 USER_001 MyExtrGroup_Def ptrGr 1 AdMOS_3_ 193 MyExtrGroup_Def ptrGr 2 AdMOS_3_ 194 MyExtrGroup_Def ptrGr 3 AdMOS_3_ 042 e User defined extraction step in the GUI PSP_DC_CV_Extract 30 DER Eile fnitialize Binning Extract Plots HTML Options Boundaries Help
608. tion mosfet 118 MOSFET Models Introduction to BSIM3 Model The BSIM3 Model The BSIM3 model BSIM Berkeley Short channel Insulated gate field effect transistor Model was published by the University of California at Berkeley in July 1993 BSIM3 is a public model and is intended to simulate analog and digital circuits that consist of deep submicron MOS devices down to channel lengths of 0 18 micron Since this channel length is no longer state of the art for modern MOS devices the model has been adopted several times to model effects not present in devices with greater channel lengths BSIM3 is a physical model with built in dependencies of important device dimensions and process parameters like the channel length and width the gate oxide thickness substrate doping concentration and LDD structures Due to its physical nature and its built in geometry dependence the prediction of device behavior of advanced devices based on the parameters of the existing process is possible As a further improvement one set of model parameters covers the whole range of channel lengths and channel widths of a certain process that can be used in circuit designs Due to the physical meaning of many model parameters the BSIM3 model is the ideal basis for the statistical analysis of process fluctuations BSIM3 can model the following physical effects of modern submicron MOS transistors e Threshold Voltage o Vertical and lateral non uniform doping o Short
609. tional model sets for areas in the L W space which are not fully covered by measured devices The following diagram shows such a scenario Extension of binning Wiurn Measured devices Extrapolated 0 18 0 5 10 Llum The binned model parameter sets for region 1 through 4 have been determined from measured devices Now for the generation of the parameter set of region 9 it is assumed that the parameters for device d are equal to the parameters of device c and parameters from h are equal the parameters from g The gate length of d and h are selected so large that they cover all useful applications The diagram in the following figure shows the principal calculation of the parameter P over an available range of gate lengths L Calculation of binned model parameters with extensions device a not defined device b device d 100 Lim Bin Bin2 Extraction of binned model parameters General algorithm e For each device D at the boundary of the bins the original parameter Po P is determined using a circuit model parameter set without the binning feature e For each bin the parameter is interpolated for the actual length and width according to the following equation P L W P PL jeff a pwhyweff ppl weff_eff e The binning parameters P PL PW PP for one bin must be determined from the Original parameters Po and Po This is also very important to make sure that the 180 MOSFET
610. tmp_1 DGG tmp_w echo Rbsb tmp_rbsb echo Rodb tmp_rbdb end BSIM4 RF_Extract O O o o echo Nrd tmp_nrd Nrs tmp_nrs fo 0 fo O 0 Back to BSIM4 Characterization mosfet 218 SPICE Model Parameters for BSIM4 6 2 MOSFET Models The model parameters of the BSIM4 model can be divided into several groups The main model parameters are used to model the key physical effects in the DC and CV behavior of submicron MOS devices at room temperature Here they are grouped into subsections related to the physical effects of the MOS transistor The second group of parameters are the process related parameters They should only be changed if a detailed knowledge of a certain MOS production process is given The third group of parameters are the temperature modeling parameters The following two groups are used to model the AC and noise behavior of the MOS transistor Finally the last group contains flags to select certain modes of operations and user definable model parameters For more details about these operation modes refer to the BSIM4 manual BSIM4 References mosfet Main Model Parameters Main Model Parameters Parameter EPSROX TOXE EOT TOXP TOXM DTOX XJ GAMMA1 GAMMA2 NGATE NDEP NSUB NSD XT VBX RSH RSHG VFB VDDEOT LEFFEOT WEFFEOT TEMPEOT VTHO DELVTO PHIN Ki K2 K3 K3B WO LPEO LPEB VBM DVTO DVT1 DVT2 Description Process rel
611. to add the Finetuning Extraction step This step will be inserted into the extraction flow If you click on this finetuning extraction the optimizing routine you just defined is available under the Available Functions list to the right of the Extract window and is ready to use The Options menu enables you to add the calculated errors to the plot window to set trace colors or exchange the background color Related Topics DC Notes mosfet DC Information mosfet DC Initialize mosfet DC Binning mosfet DC HTML mosfet DC Options mosfet DC Boundaries mosfet Back to Extraction of DC and CV Parameters mosfet Configuration Wizard 60 MOSFET Models ax i g 223 So HWE Options Boundaries Generai data t _ Technology X F i Notes on projec Felure Log wv Follow Extracten Flow Project drectory c users default Use this Wizard for Customized Available Extractions Customized Functions Customized Default Extraction Flows Start Configuration eOpen a DC_CV_ Extract modelfile From the File menu choose Examples gt model_files gt mosfet gt PSP or BSIM3 BSIM4 or any other MOSFET DC extract model file gt PSP_DC_CV_ Extract eOpen a project File gt Examples gt psp_nmos gt Copy and Open You re able to do some easy configurations without opening an example Since actions like displaying a plot or execute an Extraction PE
612. to as lateral non uniform doping concentration E Coan Source a Nd _ Doping profile Nas patie Fa Approximation No Xchannel The figure shows the lateral doping profile inside the channel of a SOI MOSFET The next figure shows the influence of the non uniform lateral channel doping onto the 295 MOSFET Models threshold voltage of a MOSFET Sn o Theoretical Increase of threshold voltage with shorter channel lengths due to lateral non uniform doping CE 3 m o 8 5 70 B VTH L m a a 8 D calc VTH Lis Sp B Lodes CLOG Short Channel Effect The decreasing of device dimensions causes the short channel effect o threshold voltage roll off and degradation of the sub threshold slope that in turn increases the off current level and power dissipation LE sl 8 D y VT 6ea e rs E e A a N a a 7i L saaa p honaga aana E S00 B _f f Le F ieee i Y s00 P 4 y 4 ane m i ETRA i c eee Theoretical decrease of threshold J voltage with shorter channel lengths 200 B I due to the short channel effects gt 146 82 7 ae S 1 1 ia Lodes CLOG Narrow Channel Effect Threshold Voltage Reduction through DIBL Carrier Mobility Reduction As in BSIM3v3 BSIMSOI4 provides 3 different equations for the modeling of the mobility reduction see Carrier Mobility Reduction mosfet They can be selected the MOBMOD flag Effective
613. trates this In the following figure the Large transistor does not fit the max L of the Length scaled and the max W of the Width scaled devices because it s size is 5 um x 5 um Therefore the automatic assignment of the size categories does not lead to satisfying results Select Categories lol x W 5 0 9 Additional um 0 25 03 0 6 0 8 5 8 LENGTH DUT Name W um L um T Transistor _A 5 5 gt Auto Set OK To set the size manually click at a certain device and change the category by selecting the appropriate category from a pull down menu in the middle of the bottom row of buttons in the Select Categories window Back to BSIM3v3 Characterization mosfet 185 MOSFET Models References and Copyright Information References 1 BSIM3v3 3 Manual University of California at Berkeley July 2005 2 Characterization System for Submicron CMOS Technologies JESSI Reports AC41 94 1 through 94 6 3 Peter Klein A consistent parameter extraction method for deep submicron MOSFETs Proc 27t European Solid State Device Research Conference Stuttgart Germany 1997 Layout Rules for GHz Probing Application Note Cascade Microtech F Sischka Deembedding Toolkit Agilent GmbH Boblingen Germany File deemb_short_open mdl in IC CAP examples Agilent EEsof W Liu et al R F MOSFET Modeling Accounting for Distributed Substrate and Channel Resistances with Emphasis on the BSIM3v3 SPICE Model Proc
614. ts is included to enable web publishing of a modeling project The modeling package supports SPICE3e2 and major commercial simulator formats such as HSPICE Spectre or Agilent s ADS The Modeling Package Supports Measurements on e Single finger normal transistors e Parasitic diodes e Capacitances o Oxide and Overlap o Bulk Drain and Source Drain junction o Intrinsic e RF multifinger transistors The Modeling Package Supports Extractions for e Basic transistor behavior e Parasitic diodes e Capacitances e RF behavior S parameters Back to BSIM4 Characterization mosfet 191 MOSFET Models BSIM4 DC Behavioral Modeling DC Behavioral Modeling This section provides a theoretical background of the BSIM4 DC model You will find some basic device equations together with some explanations on model selectors used inside the BSIM4 model and the BSIM4 Modeling Package Since this theoretical section can only be of introductional character we strongly recommend that you consult the manual from the University of California Berkeley for a detailed description of device equations and relevant parameters BSIM4 References BSIM4 Characterization References 1 as well as further literature located in BSIM4 References mosfet Threshold Voltage Model The complete threshold voltage model equation implemented in the BSIM4 model for SPICE is the influence of the well proximity effect is described at the end of this paragraph V
615. ts of parameters vs geometric values and gate length for example For an overview of device behavior see electrical values vs geometry which is called Electrical Scaling This arrangement shows global parameters to the left electrical scaling in the middle and local model parameters to the right of the window Special Arrangement of Plots to Adjust Local to Global Parameters 261 MOSFET Models i E e p p tere This arrangement enables you to show more than one group of global parameters simultaneously e g DPHIB and NEFF display scaling behavior of the global model for several devices show the typical behavior of a selected local device select a device and invoke the local parameter tuner optimizer for this device show the change of parameters in the local device behavior invoke tuning optimization for global parameters show the effects of changing global parameters on the electrical device behavior take global parameters and calculate local parameters for a selected device To use this feature proceed as follows see figure below In the Configuration region top right select parameters for global scaling to be displayed in the global region of the window Add plots to be shown in the electrical scaling region Using the tabs provided you can switch between global scaling and local extraction configurations EE inie a tib tot 2 Add scaling diagrams Parameters for Scaling Switch between
616. ttings before configuring de embedding sets A de embedding set actually is a combination of pad structures to be use for de embedding of measured devices They can be used for one or more devices and can consist of any available pad structure Click the Add De embedding Set icon once for each set to be used A line for each set will be added You are able to overwrite the predefined name of the sets Click the Configure Allocate icon to assign a pad structure to a selected de embedding set on the Configuration of de embedding Sets form Depending on the type of de embedding you have chosen No de embedding Open Short or User Defined in the De embedding Method part of this folder you are able to assign the respective pads to the sets In other words if you select Open as the de embedding method you can passing only pads of type Open to selected de embedding sets If you select Open Short or User defined you are able to assign pads of type Open Short and Through to a set san Configuration of De embedding Sets Ioj x Assign Pad Structures to selected De embedding Set Open Short Verify tr4_ni2_w8 tr4_ni2_w8 tri_n _w4 tr2_ni6_w4 tr4_ni2_w8 tr3_n6_w6 tr2_ni6_w4 tr2_n16_w4 _ You can select the check box Perform Verification of De embedding using the Through device if you have a Through device available on your test chip Only after activating the verification you can click the Verify Set
617. tton You will see any changes made to a parameter in the plots Inside the global scaling plots are squares for each device of the setup By selecting one of the squares using the left mouse button you can open a sub menu with the right mouse button This sub menu allows you to read device information and select this device for local parameter extraction The following figure shows a selected device as well as the sub menu 264 MOSFET Models 4 ba 7 E 5 amt i W 700 o 100 alng i ba ea IE 166 ies m EO GeO ier 168 1Es m fo 1E 5 Global Scaling Local Extraction z Wades LOG Wades LOG H w Parameter to adust global scaling DPH DPHIB Lscale M4 vba 000 V Ldesr 0004 DPHI n82 2AM 120 NEFF Lscale ERA jE 24 Devices Optimizer Tuner i 0 8 vo fae ria 06 DPHIBO E 07 g sot r z S 1o00 a7 Sam E ay 60 Optimizer _ aaa OPHIBL tolts ier 166 Be Ee 168 ten es wo z pa z Graphic gt amp Ldes LOG Error K 1000 5218m gt Session Settings OPHIBW Fk __ 1E 5 2s LOG 1E 5 Ldes LOG B NEFF LWscale DPHIB LWscale _Wscale aL Add Extraction Rogon gt o i w 168 Om re DPHIBLW 3l ines Device Info A x We 200F i m 0 gi 4 Ne EE ee J S E 21 The next screenshot explains how the tuning of a local parameter influences the electrical behavior of that local de
618. ture of a binned PSP model The order is as follows e Long Wide device e Short Wide device e all other devices The sequence shown in the following figure must be followed since some of the necessary parameters are to be extracted from the Long Wide or the Short Wide device only and are used for all other devices Extraction order to create a binned model 45n 60n 90n 150n 240n 5u Lim Extraction step Calculate Binning Model wim 2 4 B 45n 60n 90n 150n 240n 5u L m To correctly extract the binning model parameters you must select which intermediate result which preceding extraction step to use for the actual step For the Long Wide device the preceding step is a step from the global extraction this is the default For all other devices the results must be out of the Binning main group otherwise the parameters extracted are not correct To set the steps use the Initial Conditions window either from the pull down menu Extract gt Extraction Flow gt Initial Conditions or using the appropriate icon The following 268 MOSFET Models figure explains this in more detail E PsP _DC_CV_Extract 2 eh Fie Intialze Binning Extract Plots HTML Options Boundaries Help ley lanl one SN Bee 15 HG x Gi Sse lay a Notes Infomation Iniaze Binning Extract HTML Options Boundaies Extraction Flow Extraction Binning Function Flow Available Functions E Parameter In
619. twork analyzer before you begin this procedure Refer to the instructions earlier in this section Defining the Instrument States Perform the same procedure you did for the s_vgvdf measurement Pay particular attention to the notes listed in that procedure The instrument states need to be set independently for each setup Then return to this section and continue Setting the parasitics Inputs Most of the input values for this measurement are factory preset and should not be changed 1 Select the parasitics setup 2 Set the current Compliance for vg and vd to any reasonable values in this unbiased condition current values to the device will be negligible 3 The Sweep Type is set to CO stant for both vg and vd 4 The vg Value is set to 0 to ground the gate 5 The vd Value is set to 0 to ground the drain 6 The freq inputs set the network analyzer for a linear sweep of the calibrated frequency range Set the freq Start Stop and of Points to correspond with your broadband calibration Measuring Plotting and Extracting 1 Select Plots gt r_f gt Display Plot 2 Select Measure Simulate gt Measure 3 When the measurement is complete select Extract Optimize gt z gt Execute The transform calculates the parasitic R values vs frequency from the measured data and enters them in a file named Para data 4 The r_f plot illustrated shows parasitic resistance with frequency The resistance data displayed is t
620. ubcircuit model for BSIM3v3 3 0 RF n type devices Simulator UCB Spice3e2 Model BSIM3 Modeling Package Date 25 04 2003 Origin ICCAP_ROOT bsim3 code circuits spice3 cir rf_nmos_single cir BM me a a Fa oe aE pc a a a cg hy yc a gS te a yc a rch me ak te a eg pee yee a et E subckt bsim3_rf_extract 1 2 3 4 x BSIM3 model card 775 r rrr rrr rrr rrr rrr str echo MODEL BSIM3_HF NMOS echo LEVEL Smpar LEVEL 8 VERSION 3 2 4 BINUNIT Smpar BINUNIT 2 echo MOBMOD Smpar MOBMOD 1 CAPMOD Smpar CAPMOD 3 NOIMOD mpar NOIMOD 1 echo PARAMCHK Smpar PARAMCHK 1 echo DELTA Smpar DELTA 0 01 TNOM Smpar TNOM 27 TOX Smpar TOX 7 5E 9 echo TOXM Smpar TOXM 7 5E 9 echo NCH Smpar NCH 1 7e17 XJ Smpar XJ 1 5E 7 NGATE Smpar NGATE 0 RSH Smpar RSH 0 echo VTHO Smpar VTHO 0 7 K1i Smpar K1 0 53 K2 Smpar K2 0 013 K3 Smpar K3 0 echo K3B Smpar K3B 0 WO Smpar WO 2 5E 6 NLX Smpar NLX 0 174u DVTO Smpar DVTO0 2 2 echo DVT1 Smpar DVT1 0 53 DVT2 Smpar DVT2 0 032 DVTOW mpar DVTOW 0 echo DVT1W Smpar DVT1W 5 3E6 echo DVT2W Smpar DVT2W 0 032 ETA0 Smpar ETA0 0 ETAB Smpar ETAB 0 149 MOSFET Models echo DSUB mpar DSUB 0 56 echo U0 Smpar U0 670 UA Smpar UA 2 25E 9 UB Smpar UB 5 87E 19 UC Smpar UC 4 65E 11 echo VSAT Smpar VSAT 8e4 A0O Smpar A0 1 AGS Smpar
621. uction coefficient at TR Coefficient for the length times width dependence of mobility reduction coefficient at TR Coefficient for the geometry independent part of temperature dependence of MUE Coefficient for the geometry independent part of mobility reduction exponent at TR Coefficient for the geometry independent part of temperature dependence of THEMU Coefficient for the geometry independent part of Coulomb scattering parameter at TR Coefficient for the length dependence of Coulomb scattering parameter at TR Coefficient for the width dependence of Coulomb scattering parameter at TR Coefficient for the length times width dependence of Coulomb scattering parameter at TR Coefficient for the geometry independent part of temperature dependence of CS Coefficient for the geometry independent part of non universality parameter Coefficient for the length dependence of non universality parameter Coefficient for the width dependence of non universality parameter Coefficient for the length times width dependence of non universality parameter Coefficient for the geometry independent part of temperature dependence of XCOR Coefficient for the geometry independent part of effective field parameter Coefficient for the geometry independent part of source drain series resistance at TR Coefficient for the length dependence of source drain series resistance at TR Coefficient for the width dependence of source drain seri
622. ue of the LEVEL parameter After specifying the model enter the correct set of parameters for that model Some of these parameters are shared between different models while others affect only a specific model Extraction for the LEVEL 1 model Shichman Hodges is not supplied with this release of IC CAP The LEVEL 2 model References mosfet 1 is an advanced version of LEVEL 1 and can use either electrical or process type parameters The LEVEL 3 References mosfet 1 model is semi empirical because it uses parameters that are defined by curve fitting rather than by device physics Simulators The MOSFET model is supported by the SPICE simulators included with IC CAP SPICE2 SPICE3 and HPSPICE The model files provided can also be used with the HSPICE simulator and with some modification the Saber simulator Note Simulators are provided as a courtesy to IC CAP users they are not supported by Agilent Technologies The default nominal temperature for HPSPICE is 25 C for SPICE2 and SPICE3 it is 27 C To force a nominal temperature set the TVOM variable to the desired value MOSFET Model Parameters The following table lists parameters for the three model levels according to DC and cv extraction in IC CAP Some of these parameters are redundant and therefore only a subset of them is extracted in IC CAP UCB MOSFET Parameters describes model parameters by related categories and provide default values The parameter values are d
623. urements C Diode Measurements C Matix Debug Mode Basic Settings Keithley 703A Matrix Model SMU Connections Bus SWM Address HP IB Interface Delay after switching s Project rectory cfusers default Therefore when using Instrument Cards you need to define a port as well as a pin Note On some instruments ports are to be named using letters others using numbers for their ports Choosing the instrument from the drop down list of Matrix Models shows you how to name your instrument ports Using the Agilent E5250A Switch Matrix you need to define consecutive numbers ranging from 1 to 48 regardless of the card used inside the matrix Again you have to save your changes prior to leaving this folder The actual pin connections are entered into the DUT Variables folder for the measurement selected to use a switch matrix one or more of the DC Transistor Capacitance or Diode Measurements For example if you ve selected DC Transistor Measurements to use with 15 MOSFET Models a switch matrix you must open the model file for editing and in the DUT Setups folder select the DC Transistor then in the DUT Variables folder enter the switch matrix pin numbers in the fields below the node names This is especially useful if you would like to make series measurements on wafers using a probe card e g for quality control Note When using a Switch Matrix for Cap
624. ures for specific capacitances to be measured together with recommended instrument connections Measurement of oxide and overlap capacitance G oly Si The following figure shows a typical gate to drain source overlap capacitance diagram that you would expect to measure with this type of connection and the default values for Start Step and Stop voltage Vo Note To correctly extract overlap capacitance effects two devices are essential Standard CV measurement masks the channel capacity in short channel devices This is the so called Short Channel Effect To overcome this masking you need a short channel device for proper extraction of overlap capacitance parameters To extract the parameter NGATE you need to measure a long channel device in inversion since there is no short channel effect present in such a device Example diagram of measured overlap capacity 250 0 re AJ LJ a 200 9 n n 5 me 150 98 m oO E o 180 8 D Z m o 3 0 2 0 1 0 6 8 1 6 2 0 3 6 vg CE 84 Test Structures for CV Measurements See Test Structures for CV Measurements mosfet for a table of recommended test structures for CV measurements Capacitance Device List Click Device List to define the devices to be measured and their respective geometries See the following cut out for an example 30 MOSFET Models 46 BSIM4_DC_CV_Measure 8 File Configuration Data Tools Help neBa PeO t Xk BE Notes Temperature
625. ve bulk voltage Vag which are all defined by the continuous equations below The following equation shows the effective Vgs Vinh voltage where the factor n is defined in the Drain Current in the Subthreshold Region equation Effective Voltage Vgs Vth Equation V vV 2nv in 1 exp a A i V a T gsteff E F 27 1 2nC_ er eee off OX la e N i 2nv NTEs ch mabe 128 MOSFET Models Effective Voltage Vgs Vth Vgosteff f Ygs Teeter Pee eee ee Pee eee eee Pe eee eee eee Cree ra as Linear Er region en o gee nl i See y A N E S ow 9 o gt vg CE J The figure above shows Vgsteff in logarithmic scale Vostetf fits a linear function for values of Vgs greater than V while the subthreshold area is covered by the fit of an exponential function Through this equation the first derivative is continuous between both operational regions subthreshold and linear of the MOS transistor The equation below shows the effective drain source voltage Vgcere 7 yY l 7 7 7 7 7 Vaseff 7 Vasat 3 dsat Vas Vasat Vas 7 4 isat The following figure shows Vaseff in both the linear and the saturation region of operation of the MOS transistor Vjca models the transition between linear and saturation region without discontinuity in the first derivative of the drain current Effective Voltage Vdseff Vde eff fC Vded saturation region of 7 transistor operat
626. vice as well as the adjustment to the scaled diagram Simultaneous update of local parameter and the influence on scaling Local parameter moves with tuner for good adjustment to the scaled curve Original value of local parameter z 100 O S S i 80 3 S eo E I of s 2 e 40 s 2 1E 8 1E 7 1E 6 1E 5 4 0 0 5 0 0 0 5 1 0 1 6 2 0 Ldes LOG vg E 0 NEFF Jj Simultaneous update of 1 00000E 02 9 43068E 023 1 00000E 02 l V curves of a local I lt ti ER RS device and the local ras secan wg parameter in the scaling diagrams while tuning a 0 000 BBB 2a 2 000 local parameter The right side of the window displays two tabs Global Scaling and Local Extraction Those tabs are used to select parameters devices optimizer algorithms or tuners for either local or global devices Global Scaling Local Extraction Parameter to adjust global scaling Update Electrical Property Plots NEFF X automatic Update Devices Optimizer Tunes Optimizer Features Algorithm Levenberg M arquardt v Error Relative sim meas meas hd Parameters Autoset Reset Adopt anor v Optimize Simulate Using the Local Extraction folder you can select between the available devices and the available tuners optimizers Global Scaling Local Extraction Available Local Devices Available Tuners Optimizers N_W5u0_L5u0_5A10u0 NEFF BETN THEMU MU
627. vice and choose OK The folder will be printed Note On Windows operating system the command line is print d lt printer name gt For example if the printer is connected to a server named MYFS1 and the printer is named MY0017 type print d MYFS1 MY0017 Note If you don t enter a printer command the output will be redirected to the IC CAP Status window From the Help menu you can choose between browsing the Topics or getting help for each of the different task folders described below There are in depth hints for the task for example which device geometries to use or how to connect the instrument to the device under test to get the best extraction results from your measurements You will find links that bring you to PSP Characterization mosfet BSIM4 Characterization mosfet or BSIM3v3 Characterization mosfet Use your Browsers Back button to return to the location you were at before following the link Below the top row of icons are five folders Basically each folder is assigned to a specific task in the measurement process They are intended to be parsed from left to right but you are not bound to that order Some entries into one or the other folder will change settings on another folder For the new user You should process the folders in the order from left to right Each of the following sections describe one folder of the GUI BSIM3 BSIM4 and PSP model folders are usually equal to each other DC CV Mea
628. well This phenomenon is commonly known as the well proximity effect WPE Well Proximity Effect a caused by ion scattering during well implantation b Orientation of devices inside the well well ion implant a ontetiterd D m wri device device 5 closest lo WPE D closest lo WPE The Well Proximity model considers the influence of the effect on threshold voltage mobility as well as body effects The Configuration menu contains a selection to activate the well proximity effect or WPE Activating the well proximity effect inserts additional rows for WPE parameters SCA SCB SCC and SC into the device list It is possible to enter SC only after selecting the respective menu item from the Configuration menu If this option is chosen parameters SCA SCB and SCC are calculated from SC they cannot be modified once this option is set They will be updated as soon as you enter an SC value and select save SC is defined as The distance to a single well edge used in calculations of SCA SCB and SCC when layout information is not available If SCA SCB and SCC are not given due to lack of detailed layout information their estimation can be made by simulators based on the assumption that for most layouts the devices are close to only one well edge For details see the BSIM4 manual from the University of Berkeley Their website contains a link where you can download the complete manual The address is http www devic
629. with different de embedding methods to be selected depending on the availability of test structures and the frequency range of measurements They are e no_deembedding e resetDeembedding and e deembed_open e deembed_open_short e deembed_user_defined 1 OPEN This the simplest way of de embedding and is often used for frequency ranges up to 10 GHz It is assumed that the parasitics can be modeled using the following equivalent 171 No of 3L MOSFET Models circuit Equivalent circuit for the parasitic elements including MOS Transistor The OPEN device is measured and the S parameters of the DUT are calculated as shown next Stotal gt Ytotal Sopen gt Yopen Ydut gt Sdut where Stotal gt measured S parameters of the DUT including parasitics Sopen gt measured S parameters of the OPEN test structure Sdut gt S parameters of the DUT without influence of the parasitics Yxxx gt transformed Y parameters with Ytotal TwoPort Stotal S Y The typical behavior of this test structure is shown in the following 2 figures 11 22 of the OPEN structure S m 22 S m 11 12 21 of the OPEN structure 172 MOSFET Models IMAG E S m i2 S m 2l REAL Ceres d 2 0PEN_SHORT This is a very fast and effective way of de embedding from measurements of an OPEN and a SHORT device It is useful for frequencies above roughly 3 5 GHz if the accuracy of the OPEN method is not satisfying
630. write access to modify the example files If you would like to Open an existing project select the project path and name in the Open Project dialog box Using Export Extraction opens the Export Extractions form which enables you to choose path and name of the saved extraction settings file It is not possible to create a non existing path on Windows Instead you must create the desired folders if non existent using the Windows Explorer Note Opening a project takes some time You are able to reduce this time by saving the complete mdI file Reloading the mdl file is faster than opening a project However since the mdl file contains a large amount of data which is already stored somewhere in the system you need to have extra storage capacity on your hard disc You are able to Import Extractions by selecting the path and name of the saved extraction settings file inside the Import Extractions dialog box This might be useful for example if you found a special extraction sequence that best fulfills the need of your parameter extraction process You save those sequence by exporting the settings to a file and using this file as template for following extraction processes Note Importing extraction settings will overwrite the actual settings within the active extraction process The Batch Processing menu option enables you to run extractions overnight for example It is possible to specify the path and name of several pro
631. ws the Binning folder used in binning model parameters This folder is active only if the flag Generate Binning Model is checked otherwise you will find an n a sign next to the folder name This flag is located on the Initialize folder under Generate Binning Model Part of the Binning Folder Unable to render embedded object File icmdl 02 1 31 gif not found Show Devices By selecting Binning gt Show Devices you will see a diagram using logarithmic axes of gate width over length ranging from 0 1 to 100 microns showing the defined bin boundaries Inside this diagram you will find markers for existing measured devices for this project Diagram of measured devices red extension devices blue and binned devices magenta Unable to render embedded object File icmdl 02 1 32 gif not found Set Bin 106 MOSFET Models Select bin boundaries by using the displayed diagram marking two adjacent corners of a rectangle representing the bin and choose Set Bin from the Binning menu Be sure to include devices at every corner of your bin otherwise you will get an error message stating that the selected bin is not rectangular See the figures below for clarification Unable to render embedded object File icmdl 02 1 66 gif not found Binning areas Left Not correct because not every corner of the marked rectangle has a measured device Right Correctly defined binning area The selected binning areas are automatically ente
632. xis Scaling Math toate a Select Device W5u0_L5u0_543u0 WSu0_L5u0_SA3u0_WPEZ WSu0_L5u0_SA3u0_WPE3 WSu0_L5u0_SA3u0_WPE4 WSu0_L5u0_SA3u0_WPE1 WOu18_LS5u0_SA3u0_WPE4 WOu18_LSu0_SA3u0_WPE3 WOu18_L5u0_SA43u0 WOu18_L5u0_SA3u0_WPE2 Wii Oo too CAPM MWNE Select V Automatic Redisplay Redisplay MOSFET Models A selection of more than one value of Vd or Temperature displays the chosen diagram output with a number of curves corresponding to your choice of Bias or Temperature Folder Cycle Plot Types This folder enables you to choose different data representations or to compare the diagrams of different devices For example you can add a second y axis to any plot adding let s say the gate current to a diagram of the drain current vs gate voltage If you selected a number of devices to be displayed using the same diagram for comparison and want to examine a curve that seems to be different from the others you can zoom in on a plot To zoom in on a plot either select a plot and then Plots gt Zoom Plot gt Selected Plot from the menu of the multiplot window or Zoom Plot or Full Page Plot and select one of the plots by number The plots are numbered from top left to bottom right The window changes in the Zoom Plot mode to one magnified plot and all other plots are displayed very small In the Zoom Plot mode you can jump to zoom another plot just by clicking the desired plo
633. xplanations are general 1 Select the DC measurement setup of your choice 2 Select the Instrument Options tab and a window will be displayed showing the instrument states for the DC source monitor The following figure illustrates example DC source monitor instrument states 3 Set each of the DC source monitor measurement parameters according to the actual Agilent 4142 configuration and the device to be measured using the guidelines in the following steps Example Agilent 4142 DC Source Monitor Instrument State 325 10 Ii 12 13 14 15 Set I MOSFET Models HP4142 7 19 Use User Sweep No Hold Time BBB Delay Time BBB Integ Time ES Range 0 Power Compliance 8 880 SMU Filters ON Ves Pulse Unit Pulse Base E A Bae Pulse Width 1 AAAm Pulse Period F 18 AAm Module Control Init Command Set Use User Sweep to No as it is unnecessary for these procedures and the source monitor internal sweep is faster Hold Time is the delay in seconds before starting a sweep to allow for DC settling Generally no hold time is required Delay Time is the time in seconds the instrument waits before taking a measurement at each step of a sweep Generally no delay time is needed For Integ Time M medium is a good default choice In measurements where a long integration time is needed for noise reduction you would use L long and you will be instructed to do so in certain procedures
634. y if val action then end if Define Parameters Parameters are defined by the variable F_ParName In the example a parameter is deleted from the optimizer Delete the parameter 82 MOSFET Models F_ParName 1 NSUBO Decrease the number of elements in the ICCAP ARRAY F_ParName and the number of the variable of the parameter VFBO F_ParName ICCAP_ARRAY 2 F_ParName 1 VFBO Define Plots and Default Region You can add new plots to the user defined setup and use them in the new extraction or optimizer Add a new plot to the setup C_Oxide User_cg_vg e Define a new plot m PSP_DC_CV_Extract PSP_DC_CV_Extract C_Oxide User_cg_vg is Active 34 lolz Eile Edit Measure Extract Simulate Optimize Data Tools Macros Windows Help El XI S A E HIG MOO Ella DUTs Setups Circuit Model Parameters Model Variables Macros Model GUI Items Measure Simulate Instrument Options Setup Variables Extract Optimize Plots Setup GUI Items Display Prot Plot Finder peung mos l0g_Cox_vg OC _Transistor_STI_ Report Type XY GRAPH i a eral Data cg_vg vg vg gt Natrow_SA Data 0 abs cg_vg cox m cox m OS res i Data 1 abs cg_vg cox s cox s Yata 2 Capacitance 3 C_Junction_80 C_Junction_BS 5 a E a a a a E Oo Active Setup PSP_DC_CV_Extract C_Oxide User_cg_vg Status Cut Complete Ai Add the new plot to the plot definition
635. y poe 1 NJ 1 0 emission coefficient p NISW 1 0 sidewall emission coefficient p XTI 2 0 temperature coefficient for forward current densities E XTI2 0 temperature coefficient for reverse current densities p DIVX 0 reverse current coefficient VA 14 CTEMP 0 temperature coefficient of reverse currents p CISB 0 reverse biased saturation current p CISBK 0 reverse biased saturation current at low A temperature CV 0 lb bias dependence coefficient of CISB i e bias dependence coefficient of CISB at low temperature E bottom junction capacitance per unit area at zero F m bias 2 o 5E 10 source drain sidewall junction cap grading F m coefficient per unit length at zero bias 1 CJSWG 5E 10 source drain sidewall junction capacitance per unit F m length at zero bias 1A MJ 0 5 lb bottom junction capacitance grading coefficient MJSW 0 33 source drain sidewall junction capacitance grading coefficient Peon Pe source drain gate sidewall junction capacitance grading coefficient PB 1 0 bottom junction build in potential Vv PBSW 1 0 source drain sidewall junction build in potential Vv PBSWG 1 0 source drain gate sidewall junction build in potential Vv VDIFFJ 0 6E diode threshold voltage between source drain and V a substrate meso 0 roppsw oF TCIBDSWG 0 p ros Tasssw fof TCJBSSWG 0 1 f Noise Parameters Parame
636. ywords to help define the import paths All keywords can be used later to describe the name and the location of the stored mdm file The Role of the MDM_FILE_CONSTRUCTOR The major problem in accessing raw mdm data is that there are many possible data organization schemes The mdm files can be sorted according to the temperature in different directories and in one directory per device and so on To cover these different solutions the MDM_FILE_CONSTRUCTOR is introduced Its purpose is to enable you to define the mdm file structure This is done using the different keywords from the device list files and the import GUI Functionality The import routine performs the following steps 1 Scanning the files According to the definition in the MDM_FILE_CONSTRUCTOR the import routine looks for all available files first which are described by this expression Let s assume that the MDM_FILE_CONSTRUCTOR looks like lt DIR gt lt DEVICE_NAME gt lt TEMP_ALIAS gt mos_ lt MDM_FILE gt mdm and the different keywords have the following entries lt DIR gt lt DEVICE_NAME gt lt TEMP_ALIAS gt lt MDM FILE gt C tmp Transistor_1 minus40 idvg Transistor_2 25 idvd Transistor_3 125 my_idvg One possible file would be c tme Transistor1i minus40 mos_idvg mdm In this case all possible combinations using the 4 keywords are generated and each 35 MOSFET Models combination is then checked as to whether or not the file exists 2 Import to IC

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