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AT E Series User Manual

1. ACH O ome Ground G co lg o s o e Programmable igna Gain Source s Instrumentation e PA Amplifier PGIA ACH b lo Measured Common Voltage Mode re O so p Noise and Vv 7 oo 4 Ground cm Potential a hg ip oe Input Multiplexers oo AISENSE AIGND Selected Channel in DIFF Configuration 1 0 Connector Figure 4 6 Differential Input Connections for Ground Referenced Signals With this type of connection the PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the AT E Series device ground shown as Vom in Figure 4 6 National Instruments Corporation 4 21 AT E Series User Manual Chapter 4 Connecting Signals Differential Connections for Nonreferenced or Floating Signal Sources Figure 4 7 shows how to connect a floating signal source to an AT E Series device channel configured in DIFF input mode ACH bd o rome Bias Resistors co Floating see text o o Progianmable Signal Vs s Instrumentation Source Amplifier e so ACH oo Measured Voltage O so 9 Bias 0 So Current l l Return K Paths 3 o so dE Multiplexers TAREE 1 O Connector gt Llano L Selected Channel in DIFF Configurat
2. Level Min Max Input low current 320 uA Input high current 10 yA Output low voltage Io 24 mA 0 4 V Output high voltage lop 13 mA 4 35 V Power On Statens scisisceiesiehasieniaicecien Input high impedance Data transfers issiro Programmed I O Max transfer rate 1 word 8 bits 50 kwords s system dependent Constant sustainable rate 0 0 1 to 10 kwords s typical Number of channels 2 up down counter timers 1 frequency scaler Resolution Counter timers c00ccccsscsscceseeeeees 24 bits Frequency scaler eeeseeseeeseeeees 4 bits Compatibility serur eegen TTL CMOS Base clocks available Counter timers cccccccssssscssseeeeees 20 MHz 100 kHz Frequency scaler eee 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency 20 MHz Min source pulse duration 10 ns edge detect mode Min gate pulse duration ee 10 ns edge detect mode Data transfers ccceccccccecesesesesesereeees DMA interrupts programmed I O DMA mode Siessen darid Single transfer demand transfer A 26 ni com Appendix A Specifications for AT MIO 16XE 10 and AT AI 16XE 10 Triggers Analog Trigger SOUC Edner eased etree dees dda ids WLOVel coNtc tative tas a Roki tee Resolution inenen HYSt resis wi iesii ste nr a N Bandwidth 3 dB External input PFIO TRIG1 Impedance senn no R COUPE vives eden E Protection sesesesseesesseeeeee
3. 20 ppm C Output Characteristics Number of channels eeeeeceeeseeeseeeee 2 voltage RESOLUTION iaa e 12 bits 1 in 4 096 1 Source impedance lt 1 kQ AT E Series User Manual A 14 ni com Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 Max update rate eee eects 100 kS s system dependent LYPe OL DAG atier o tives Double buffered multiplying FIFO buffer size sssessscenscseneseneees None Data transfers sieren DMA interrupts programmed I O DMA Mmode ccccccceceeeesesesessreeeeeeeees Single transfer demand transfer Transfer Characteristics Relative accuracy INL After calibration eee 0 3 LSB typ 0 5 LSB max Before calibration 0 0 0 cee eeeeeeees 4 LSB max DNL After calibration eee 0 3 LSB typ 1 0 LSB max Before calibration 2 0 0 0 cesses 3 LSB max MOMotonicity cei 12 bits guaranteed after calibration Offset error After calibration ccccccceeeeeeeeees 1 0 mV max Before calibration cccc0ceeeeeee 200 mV max Gain error relative to internal reference After calibration eee 0 01 of output max Before calibration 0 00 0 0 5 of output max Gain error relative to external reference 0 to 0 67 of output max not adjustable Voltage Output Ran 6S eis tenehieeiveiiiindsn atone 10 V 0 to 10 V EXTREF 0 to EXTREF software selectable Output coupling eee eeeeees DC N
4. Type of ADC niina Successive approximation Resolutionices is eecdatsietis ens 12 bits 1 in 4 096 Max sampling rate oo eee eee 100 kS s guaranteed Input signal ranges Range Input Range Software Selectable Bipolar Unipolar 20 V 10 V 10 V 5 V Oto10V 5V 2 5 V 0to5 V 2V 1 V 0to2 V 1V 500 mV Otol V 500 mV 250 mV 0 to 500 mV 200 mV 100 mV 0 to 200 mV 100 mV 50 mV 0 to 100 mV Input coupling wo ee eee eee ete eeeeeeee DC Max working voltage signal common mode eeeeeeee Each input should remain within 11 V of ground Overvoltage protection eee 35 V powered on 25 V powered off AT E Series User Manual A 12 ni com Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 Inputs protected ACH lt 0 15 gt AISENSE FIFO buffer size eee neepa 512 samples Data transfers cccccccecceseeeeeeeeereeeeees DMA interrupts programmed I O Transfer rate 1 word 8 bits 50 kwords s DMA Mmod S cccccceceeeeseseeesensrseeeeees Single transfer demand transfer Configuration memory Size 512 words Transfer Characteristics Relative accuracy s es 0 2 LSB typ dithered 1 5 LSB max undithered PND a a RS ees 0 2 LSB typ 1 0 LSB max NO missing codes eeeeeeeeseeeeteeeteeeeeees 12 bits guaranteed Offset error Pregain error after calibration 2 uV max Pregain error before calibration 24 mV max Postgain error after ca
5. Analog Input Signal Connections AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16DE 10 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 The AI signals are ACH lt 0 15 gt AISENSE and AIGND The ACH lt 0 15 gt signals are tied to the 16 analog input channels of the AT E Series device In single ended mode signals connected to ACH lt 0 15 gt are routed to the positive input of the device PGIA In differential mode signals connected to ACH lt 0 7 gt are routed to the positive input of the PGIA and signals connected to ACH lt 8 15 gt are routed to the negative input of the PGIA e AT MIO 64E 3 The AI signals are ACH lt 0 63 gt AISENSE AISENSE2 and AIGND The ACH lt 0 63 gt signals are tied to the 64 AI channels of the AT MIO 64E 3 In single ended mode signals connected to ACH lt 0 63 gt are routed to the positive input of the AT MIO 64E 3 PGIA In differential mode signals connected to ACH lt 0 7 16 23 32 39 48 55 gt are routed to the positive input of the PGIA and signals connected to ACH lt 8 15 24 31 40 47 56 63 gt are routed to the negative input of the PGIA Caution Exceeding the differential and common mode input ranges distorts the input signals Exceeding the maximum input voltage rating can damage the AT E Series device and the PC NI is not liable for any damage resulting from such signal connections The maximum input voltage ratings are listed in Tables 4 3 through 4 6 in the P
6. INTR Output Interrupt Request This signal becomes high to request service during a data transfer The appropriate interrupt enable bits must be set to generate this signal and to allow it to interrupt the computer RD Internal Read Signal This signal is the read signal generated by the host computer WR Internal Write Signal This signal is the write signal generated by the host computer DATA Input Data Lines at the Selected Port PA or PB This signal indicates when the data on the or Output data lines at a selected port is or should be available National Instruments Corporation 4 51 AT E Series User Manual Chapter 4 Connecting Signals Mode 1 Input Timing Figure 4 38 details the timing specifications for an input transfer in Mode 1 172 74 ial gt STB _ i 1 i 1 17 i BE a cae po i gt INTR 2 T3 p T5 x DATA lt Name Description Minimum Maximum Tl STB Pulse Width 100 T2 STB 0 to IBF 1 150 T3 Data before STB 1 20 T4 STB 1 to INTR 1 150 T5 Data after STB 1 50 T6 RD 0 to INTR 0 200 T7 RD 1 to IBF 0 150 All timing values are in nanoseconds Figure 4 38 Mode 1 Input Timing AT E Series User Manual 4 52 ni com Chapter 4 Connecting Signals Mode 1 Output Timing Figure 4 39 details the timing specifications f
7. 120 dB Dynamic Characteristics Bandwidth Range Small Signal 3dB 5 to 20 V 63 kHz 1to2V 57 kHz 100 to 200 mV 33 kHz Settling time for full scale step Accuracy 0 0015 0 0061 Range 1 LSB 4 LSB 1 to 20 V 50 us max 50 us max 200 mV bipolar 75 us max 50 us max 100 mV unipolar 75 us max 50 us max Accuracy values valid for source impedances lt 1 KQ Refer to the Multiple Channel Scanning Considerations section of Chapter 3 Hardware Overview for more information Analog Output Appendix A Specifications for AT MIO 16XE 50 System noise LSB including quantization noise Range Bipolar Unipolar 1to20V 1 0 100 to 200 mV 1 6 Crosstalk DC to 20 kHz Adjacent channels eeee All other channels 00 0 0 eee Stability Offset temperature coefficient Pre Gain eine e AN Postga n E Gain temperature coefficient Output Characteristics Number of channels 00000eeee 85 dB max 100 dB max 1 pV C 12 uV C 5 ppm C 2 voltage Resolution 200 cc cccececeeeesesesesesessseteeees Max update rate eeeeeseeceneeeneeeeeees Type OL DAG mner ised FIFO buffer size eee ee eeeeeee eters Data transfers cccccceceeeeseeeeesetereeees DMA mod ccccceeeceeeeseseeeserseeeeeeees None 12 bits 1 in 4 096 20 kS s system dependen
8. e Pollution degree 1 means no pollution or only dry nonconductive pollution occurs The pollution has no influence e Pollution degree 2 means that only nonconductive pollution occurs in most cases Occasionally however a temporary conductivity caused by condensation must be expected e Pollution degree 3 means that conductive pollution occurs or dry nonconductive pollution occurs which becomes conductive due to condensation Clean the product with a soft nonmetallic brush The product must be completely dry and free from contaminants before returning it to service You must insulate signal connections for the maximum voltage for which the product is rated Do not exceed the maximum ratings for the product Remove power from signal lines before connection to or disconnection from the product Operate this product only at or below the installation category stated in Appendix A Specifications The following is a description of installation categories e Installation Category I is for measurements performed on circuits not directly connected to MAINS This category is a signal level such as voltages on a printed wire board PWB on the secondary of an isolation transformer Examples of Installation Category I are measurements on circuits not derived from MAINS and specially protected internal MAINS derived circuits e Installation Category II is for measurements performed on circuits directly connected to the low volta
9. 35 36 SCANCLK EXTSTROBE 37 38 PFIO TRIG1 PFI1 TRIG2 39 40 PFI2 CONVERT PFI3 GPCTR1_SOURCE 41 42 PFI4 GPCTR1_GATE GPCTR1_OUT 43 44 PFI5 UPDATE PFI6 WFTRIG 45 46 PFI7 STARTSCAN PFI8 GPCTRO_SOURCE 47 48 PFI9 GPCTRO_GATE GPCTRO_OUT 49 50 FREQ_OUT Figure B 4 50 Pin MIO Connector Pin Assignments National Instruments Corporation B 5 AT E Series User Manual Appendix B Optional Cable Connector Descriptions AT E Series User Manual Figure B 5 shows the pin assignments for the 50 pin DIO connector This is the other 50 pin connector available when you use the R1005050 cable assembly with the AT MIO 16DE 10 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO PA7 PA6 PA5 PA4 PA3 PA2 PA1 PAO 5V GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Figure B 5 50 Pin DIO Connector Pin Assignments B 6 ni com Appendix B Optional Cable Connector Descriptions Figure B 6 shows the pin assignments for the 50 pin extended AI connector This is the other 50 pin connector available when you use the R1005050 cable assembly with the AT MIO 64E 3 ACH16 1 2 ACH24 ACH17 3 4 ACH25 ACH18 5 6 ACH26 ACH19 7 8 ACH27 ACH20 9 10 ACH28 ACH21 11 12
10. 59 24 58 23 57 22 56 21 55 20 54 19 53 18 52 17 51 16 50 15 49 14 48 13 47 12 46 11145 10 44 9 43 42 41 40 39 38 37 36 35 NI BR oO DM N oo eee ACH 16 ACH 25 ACH 26 ACH 19 ACH 28 ACH 29 ACH 22 ACH 31 ACH 40 ACH 33 ACH 42 ACH 43 AISENSE2 ACH 36 ACH 45 ACH 46 ACH 39 ACH 56 ACH 57 ACH 50 ACH 59 ACH 60 ACH 53 ACH 62 ACH 63 N C N C N C N C N C N C N C N C N C Figure B 3 68 Pin Extended Al Connector Pin Assignments B 4 ni com Appendix B Optional Cable Connector Descriptions Figure B 4 shows the pin assignments for the 50 pin MIO connector This connector is available when you use the SH6850 or R6850 cable assemblies with the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 It is also one of the two 50 pin connectors available when you use the R1005050 cable assembly with the AT MIO 16DE 10 or AT MIO 64E 3 AIGND 1 2 AIGND ACHO 3 4 ACH8 ACH1 5 6 ACH9 ACH2 7 8 ACH10 ACH3 9 10 ACH11 ACH4 11 12 ACH12 ACH5 13 14 ACH13 ACH6 15 16 ACH14 ACH7 17 18 ACH15 AISENSE 19 20 DACOOUT DAC1OUT 21 22 EXTREF AOGND 23 24 DGND DIOO 25 26 DIO4 DIO1 27 28 DIO5 DIO2 29 30 DIO6 DIO3 31 32 DIO7 DGND 33 34 5V 5V_
11. AT E Series User Manual 4 54 ni com Chapter 4 Connecting Signals Field Wiring Considerations Environmental noise can seriously affect the accuracy of measurements made with the AT E Series device if you do not take proper care when running signal wires between signal sources and the device The following recommendations apply mainly to AI signal routing to the device although they also apply to signal routing in general You can minimize noise pickup and maximize measurement accuracy by taking the following precautions e Use differential analog input connections to reject common mode noise e Use individually shielded twisted pair wires to connect AI signals to the device With this type of wire the signals attached to the CH and CH inputs are twisted together and then covered with a shield You then connect this shield only at one point to the signal source ground This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference e Route signals to the device carefully Keep cabling away from noise sources The most common noise source in a PC DAQ system is the video monitor Separate the monitor from the analog signals as much as possible The following recommendations apply for all signal connections to the AT E Series device e Separate AT E Series device signal lines from high current or high voltage lines These lines are capable of inducing curr
12. DIO4 DGND DIO1 DIO6 DGND 5V DGND DGND PFIO TRIG1 PFI1 TRIG2 DGND 5V DGND PFI5 UPDATE PFI6 WFTRIG DGND PFI9 GPCTRO_GATE GPCTRO_OUT FREQ_OUT ie 34 68 33 67 32 66 31 65 30 64 29 63 28 62 27 61 N O 60 M oa 59 N EN 58 N wo 57 we N 56 M 55 pe 54 o 53 52 n N 51 O 50 oa 49 ER A 48 a wo 47 N 46 a k 45 en 44 o 43 42 41 40 39 38 37 36 P v A oO DM N o 35 CUO ACHO AIGND ACH9 ACH2 AIGND ACH11 AISENSE ACH12 ACH5 AIGND ACH14 ACH7 AIGND AOGND AOGND DGND DIOO DIO5 DGND DIO2 DIO7 DIO3 SCANCLK EXTSTROBE DGND PFI2 CONVERT PFI3 GPCTR1_SOURCE PFI4 GPCTR1_GATE GPCTR1_OUT DGND PFI7 STARTSCAN PF1I8 GPCTRO_SOURCE DGND DGND Not available on AT Al 16XE 10 Not available on AT MIO 16XE 1 0 AT AI 16XE 10 or AT MIO 16XE 50 Figure B 1 68 Pin MIO Connector Pin Assignments B 2 ni com Appendix B Optional Cable Connector Descriptions Figure B 2 shows the pin assignments for the 68 pin DIO connector This is the other 68 pin connector available when you use the SH1006868 cable assembly with the AT MIO 16DE 10 GND PC6 PC5 GN
13. GPCTRO_OUT Pulse on TC GPCTRO_OUT Toggle Output on TC TC i LT L AT E Series User Manual Figure 4 33 GPCTRO_OUT Signal Timing GPCTRO_UP_DOWN Signal This signal can be externally input on the DIO6 pin and is not available as an output on the I O connector The general purpose counter 0 counts down when this pin is at a logic low and counts up when it is at a logic high You can disable this input so that software can control the up down functionality and leave the DIO6 pin free for general use 4 46 ni com Chapter 4 Connecting Signals GPCTR1_SOURCE Signal Any PFI pin can externally input the GPCTR1_SOURCE signal which is available as an output on the PFI3 GPCTR1_SOURCE pin As an input the GPCTR1_SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR1_SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCTR1_SOURCE monitors the actual clock connected to general purpose counter 1 even if the source clock is being externally generated by another PFI This output is set to high impedance at startup Figure 4 34 shows the timing requirements for the GPCTR1_SOURCE signal tp 50 ns minimum ty 23 ns minimum Figure 4 34 GPCTR1_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 10 ns high or lo
14. Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 GPCTR1_OUT DO 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFIS UPDATE DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 KQ pu Vec 0 4 PFI6 WFTRIG DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI7 STARTSCAN DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI8 GPCTRO_SOURCE DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI9 GPCTRO_GATE DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 GPCTRO_OUT DO 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 FREQ _OUT DO 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 1 DIO lt 6 7 gt are also pulled down with a 50 KQ resistor AI Analog Input DIO Digital Input Output pu pull up ADIO Analog Digital Input Output The tolerance on the 50 KQ pull up and pull down resistors is very large Actual value may range between 17 KQ and 100 KQ National Instruments Corporation 4 9 AT E Series User Manual Chapter 4 Connecting Signals Table 4 4 1 0 Signal Summary for the AT MIO 16E 10 and AT MIO 16DE 10 Impedance Protection Rise Input Volts Source Sink Time Signal Name Drive Output On Off mA at V mA at V ns Bias ACH lt 0 15 gt AI 100 GQ in 35 25 200 pA parallel with 50 pF AISENSE AI 100 GQ in 35 25 200 pA parallel with 50 pF AIGND AO DACOOUT AO
15. 20 MHz Min source pulse duration Min gate pulse duration Data transfers 00 DMA modes 0608 Digital Trigger Compatibility 0 RESPONSE airis Pulse width RTSI Trigger lines eee 10 ns in edge detect mode 10 ns in edge detect mode DMA interrupts programmed I O Single transfer demand transfer TTL Rising or falling edge 10 ns min ni com Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 Calibration Recommended warm up time 15 min Calibration interval eee eee 1 year External calibration reference gt 6 and lt 10V Onboard calibration reference Devel ene 5 000 V 3 5 mV over full operating temperature actual value stored in EEPROM Temperature coefficient 0 5 ppm C max Long term stability 0 eee 15 ppm 41 000 h Bus Interface YPC Riek ih E Slave Power Requirement 5 V DG 45 sieesied tenet oe 0 7A Power available at I O connector 4 65 VDC to 5 25 VDC at lA Physical Dimensions not including connectors 0 0 0 eee 17 45 by 10 56 cm 6 87 by 4 16 in T O connector AT MIO 16E 10 0 eee 68 pin male SCSI II type AT MIO 16DE 10 00 ee 100 pin female 0 050 D type Maximum Working Voltage Maximum working voltage refers to the signal voltage plus the common mode voltage Channel to earth ee eee eeeeeeeeees 42 V Installation Ca
16. 36C to 36F Reserved 370 to 366 PC AT Parallel Printer Port 1 LPT1 2 4 ni com Chapter 2 Installing and Configuring the Device Table 2 1 PC AT I O Address Map Continued T O Address Range Hex Device 380 to 38C SDLC Communications 380 to 389 Bisynchronous BSC Communications alternate 390 to 393 Cluster Adapter 0 394 to 39F 3A0 to 3A9 BSC Communications primary 3AA to 3AF 3B0 to 3BF Monochrome Display Parallel Printer Adapter 0 3C0 to 3CF Enhanced Graphics Adapter VGA 3D0 to 3DF Color Graphics Monitor Adapter VGA 3E0 to 3EF nm 3F0 to 3F7 Diskette Controller 3F8 to 3FF Serial Port 1 COM1 A79 Reserved for Plug and Play operation Table 2 2 PC AT Interrupt Assignment Map IRQ Device 15 Available 14 Fixed Disk Controller 13 Coprocessor 12 AT DIO 32F default 11 AT DIO 32F default 10 AT MIO 16 default 9 PC Network default PC Network Alternate default 8 Real Time Clock National Instruments Corporation 2 5 AT E Series User Manual Chapter 2 Installing and Configuring the Device Table 2 2 PC AT Interrupt Assignment Map Continued IRQ Device 7 Parallel Port 1 LPT1 6 Diskette Drive Controller Fixed Disk and Diskette Drive Controller 5 Parallel Port 2 LPT2 PC DIO 24 default Lab PC PC default 4 Serial Port 1 COM1 BSC BSC Alternate 3 Serial Port
17. all timing I O lines except EXTSTROBE are high impedance How does NI DAQ treat bogus missed data transfer errors that can arise during DMA driven GPCTR buffered input operations When doing buffered transfers using GPCTR function calls with DMA you can call GPCTR_Watch to indicate dataTransfer errors NI DAQ takes a snapshot of transfers and counts how many points have been transferred If all the points have been transferred and the first instance of this error occurs NI DAQ returns a gpcetrDataTransfer Warning indicating that the error could be bogus If all the points have not been transferred NI DAQ returns the genuine error The error continues to be returned until the C 8 ni com Appendix C Common Questions acquisition completes The above error occurs because NI DAQ disarms the counter from generating any more requests in the interrupt service routine Due to interrupt latencies it is possible that the counter may have generated some spurious requests which the DMA controller may not satisfy because it has already transferred the required number of points What are the PFIs and how do I configure these lines PFIs are Programmable Function Inputs These lines serve as connections to virtually all internal timing signals If you are using NI DAQ or LabWindows CVI use the Select_Signal function to route internal signals to the I O connector route external signals to internal timing sources or tie internal timing signals tog
18. demand transfer Configuration Memory Size 512 words Transfer Characteristics Relative accuracy s es 0 5 LSB typ 1 LSB max DND vacciativtiah iii cies i 0 5 LSB typ 1 LSB max NO MISSING codes 0 eeeeeeseeeeseeeneeeeeees Offset error Pregain error after calibration Pregain error before calibration Postgain error after calibration Postgain error before calibration 16 bits guaranteed 3 uV max 1 mV max 76 uV max 4 mV max Gain error relative to calibration reference After calibration gain 1 Before calibration cccc0eeseeeees With gain error adjusted to 0 at gain 1 Gain 2 10 ia G in 100i atni Amplifier Characteristics Input impedance Normal powered on ceeeeeeeees Powered off Over load ccceeeeeesesessesssteeseseseeess Input bias current 0 0 lee eee eeteeeteeeeeees Input offset Current eee eeteeeeeeteees National Instruments Corporation 30 5 ppm of reading max 2 250 ppm of reading max 100 ppm of reading 250 ppm of reading 7 GQ in parallel with 100 pF 820 Q min 820 Q min 10 nA 20 nA AT E Series User Manual Appendix A AT E Series User Manual Specifications for AT MIO 16XE 50 CMRR DC to 60 Hz Range CMRR Bipolar CMRR Unipolar 20 V 80 dB 10 V 86 dB 80 dB 5V 86 dB 2V 100 dB 1V 100 dB 200 mV 120 dB 100 mV
19. instrumentation amplifier PGIA and the other connects to the negative input of the PGIA RSE A channel configured in RSE mode uses one analog channel input line which connects to the positive input of the PGIA The negative input of the PGIA is internally tied to AI ground AIGND NRSE A channel configured in NRSE mode uses one analog channel input line which connects to the positive input of the PGIA The negative input of the PGIA connects to the AI sense AISENSE input For more information about the three types of input configuration refer to the Analog Input Signal Connections section of Chapter 4 Connecting Signals which contains diagrams showing the signal paths for the three configurations Input Polarity and Input Range AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 These devices have two input polarities unipolar and bipolar Unipolar input means that the input voltage range is between 0 and V where Vef is a positive reference voltage Bipolar input means that the input voltage range is between V 2 and V e 2 The AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 have a unipolar input range of 10 V 0 to 10 V anda bipolar input range of 10 V 5 V You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely The software programmable gain on these devices increases
20. posttrigger applications PFI2 CONVERT DGND Input Output PFI2 Convert As an input this is one of the PFIs As an output this is the CONVERT signal A high to low edge on CONVERT indicates that an A D conversion is occurring AT E Series User Manual 4 6 ni com Chapter 4 Connecting Signals Table 4 2 1 0 Signal Summary for the AT E Series Continued Signal Name Reference Direction Description PFI3 GPCTR1_SOURCE DGND Input PFI3 Counter 1 Source As an input this is one of the PFIs Output As an output this is the GPCTR1_SOURCE signal This signal reflects the actual source connected to the general purpose counter 1 PFI4 GPCTR1_GATE DGND Input PFI4 Counter 1 Gate As an input this is one of the PFIs Output As an output this is the GPCTR1_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 1 GPCTR1_OUT DGND Output Counter 1 Output This output is from the general purpose counter output PFIS UPDATE DGND Input PFI5 Update As an input this is one of the PFIs Output As an output this is the UPDATE signal A high to low edge on UPDATE indicates that the analog output primary group is being updated PFI6 WFTRIG DGND Input PFI6 Waveform Trigger As an input this is one of the PFIs Output As an output this is the WFTRIG signal In timed analog output sequences a low to high transition indi
21. 17 single ended connections description 4 24 floating signal sources RSE 4 25 grounded signal sources NRSE 4 25 when to use 4 24 SISOURCE signal 4 39 software programming choices register level programming 1 4 software drivers D 1 specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 analog input A 1 amplifier characteristics A 3 dynamic characteristics A 4 input characteristics A 1 stability A 5 transfer characteristics A 3 analog output A 5 dynamic characteristics A 7 output characteristics A 5 stability A 7 transfer characteristics A 6 voltage output A 7 bus interface A 10 digital I O A 8 physical A 10 power requirements A 10 timing I O A 8 triggers analog trigger A 9 digital trigger A 9 RTSI A 10 AT E Series User Manual Index AT MIO 16E 10 and AT MIO 16DE 10 analog input amplifier characteristics A 13 dynamic characteristics A 14 input characteristics A 12 transfer characteristics A 13 analog output A 14 dynamic characteristics A 16 output characteristics A 14 stability A 16 transfer characteristics A 15 voltage output A 15 bus interface A 19 digital I O A 16 physical A 19 power requirements A 19 timing I O A 18 triggers digital trigger A 18 RTSI A 18 AT MIO 16XE 10 and AT AI 16XE 10 analog input amplifier characteristics A 22 dynamic characteristics A 23 input characteristics A 21 transfer characteristics A 22 analog output AT MIO 16X
22. 2 COM2 BSC BSC Alternate Cluster primary PC Network PC Network Alternate WD EtherCard default 3Com EtherLink default 2 IRQ 8 15 Chain from interrupt controller 2 1 Keyboard Controller Output Buffer Full 0 Timer Channel 0 Output Table 2 3 PC AT 16 bit DMA Channel Assignment Map Channel Device 7 AT MIO 16 series default 6 AT MIO 16 series default AT DIO 32F default 5 AT DIO 32F default 4 Cascade for DMA Controller 1 channels 0 through 3 B Note EISA computers also have channels 0 3 available as 16 bit DMA channels AT E Series User Manual 2 6 ni com Hardware Overview This chapter presents an overview of the hardware functions on the AT E Series device Figure 3 1 shows the block diagram for the AT MIO 16E 1 and AT MIO 16E 2 Voltage Calibration REF DACs Selection Switches 12 Bit Sampling Data AD Transceivers Converter Calibration Dither A Mux Circuitry EEPROM Memory ontrol T S Trigger Level 2 Analog z A oD DAC o 2 Trigger 1 75 c Trigger gt Circuitry omg 4 Analog Input i DMN a i Tri Tee 1 Interrupt c PFI Trigger rigger Timing Control Request Analog EEPROM DMA O c A ar a a a ee ee ee Control i ontrol intertacs Counter Bus ea 8 Timing Timing vo DAQ STC interface one Q PEENE AR
23. 2 Safety The DAQ device meets the requirements of the following standards for safety and electrical equipment for measurement control and laboratory use e EN 61010 1 1993 A2 1995 IEC 61010 1 1990 A2 1995 e UL 3101 1 1993 UL 3111 1 1994 UL 3121 1998 e CAN CSA 22 2 no 1010 1 1992 A2 1997 National Instruments Corporation A 37 AT E Series User Manual Appendix A Specifications for Maximum Signal Ratings for AT Series Devices Electromagnetic Compatibility CE C Tick and FCC Part 15 Class A Compliant Electrical emissions cceeeeeeeeeeeeeees EN 55011 Class A at 10 m FCC Part 15A above 1 GHz Electrical immunity eee eee eeeeeeee Evaluated to EN 61326 1998 Table 1 3 Note For full EMC compliance you must operate this device with shielded cabling In addition all covers and filler panels must be installed Refer to the Declaration of Conformity DoC for this product for any additional regulatory compliance information To obtain the DoC for this product click Declaration of Conformity at ni com hardref nsf This Web site lists the DoCs by product family Select the appropriate product family followed by the product and a link to the DoC appears in Adobe Acrobat format Click the Acrobat icon to download or read the DoC Maximum Signal Ratings for AT Series Devices ny Note NI is not liable for any damage resulting from signal connections that exceed these ratings Refer to the warranty for specific inf
24. 3 6 DIFF table 3 7 NRSE table 3 7 RSE table 3 7 common mode signal rejection 4 26 differential connections DIFF input configuration 4 20 floating signal sources 4 22 ground referenced signal sources 4 21 nonreferenced signal sources 4 22 single ended connections 4 24 floating signal sources RSE configuration 4 25 grounded signal sources NRSE configuration 4 25 input polarity and range National Instruments Corporation l 7 Index AT MIO 16E 1 AT MIO 16E 2 AT MIO 643 3 AT MIO 16E 10 and AT MIO 16DE 10 3 7 actual range and measurement precision table 3 8 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 3 8 AT MIO 16XE 10 AT MIO 16XE 50 actual range and measurement precision table 3 9 mixing bipolar and unipolar channels note 3 9 selection considerations 3 10 installation See also configuration common questions about C 2 hardware installation 2 1 unpacking AT E series boards 1 6 instrument drivers D 1 interrupt channel selection overview 2 3 to 2 4 PC AT 16 bit DMA channel assignment map table 2 6 PC AT I O address map table 2 4 to 2 5 PC AT interrupt assignment map table 2 5 to 2 6 INTR signal table 4 51 K KnowledgeBase D 1 mode 1 input Port C signal assignments table 4 50 timing specifications 4 52 mode 1 output Port C signal assignments table 4 50 timing specifications 4 53 AT E Series User Manual Index mode 2 bidi
25. 4 1 exceeding maximum ratings caution 4 1 4 15 4 17 4 28 T O signal summary table AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 4 8 AT MIO 16E 10 and AT MIO 16DE 10 4 10 AT MIO 16XE 10 and AT AI 16XE 10 4 12 AT MIO 16XE 50 4 13 signal descriptions table 4 5 input configurations common mode signal rejection 4 26 ni com differential connections DIFF input configuration 4 20 floating signal sources 4 22 ground referenced signal sources 4 21 nonreferenced signal sources 4 22 single ended connections 4 24 floating signal sources RSE configuration 4 25 grounded signal sources NRSE configuration 4 25 power connections 4 29 timing connections 4 30 data acquisition timing connections AIGATE signal 4 39 CONVERT signal 4 38 EXTSTROBE signal 4 41 SCANCLK signal 4 40 SISOURCE signal 4 39 STARTSCAN signal 4 36 TRIGI signal 4 33 TRIG signal 4 34 general purpose timing signal connections FREQ OUT signal 4 50 GPCTRO_GATE signal 4 45 GPCTRO_OUT signal 4 46 GPCTRO_SOURCE signal 4 44 GPCTRO_UP_DOWN signal 4 46 GPCTR1_GATE signal 4 47 GPCTR1_OUT signal 4 48 GPCTR1_SOURCE signal 4 47 GPCTR1_UP_DOWN signal 4 48 programmable function input connections 4 31 waveform generation timing connections 4 41 UISOURCE signal 4 44 National Instruments Corporation l 11 Index UPDATE signal 4 42 WFTRIG signal 4 41 types of signal sources 4 17 floating 4 17 ground referenced 4
26. 4 42 WFTRIG signal 4 41 Web professional services D 1 technical support D 1 WFTRIG signal timing connections 4 41 wiring considerations 4 55 worldwide technical support D 1 WR signal table 4 51 ni com
27. 4 51 DGND signal diag AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 13 description table 4 5 digital I O connections 4 28 digital timing connections 4 30 nostic resources D 1 DIFF differential input mode definition table 3 7 AT E Series User Manual description 4 20 ground referenced signal sources 4 21 nonreferenced or floating signal sources 4 22 single ended connections 4 24 floating signal sources RSE 4 25 grounded signal sources NRSE 4 25 when to use 4 20 digital I O common questions about C 7 operation 3 18 signal connections 4 28 specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 8 AT MIO 16E 10 and AT MIO 16DE 10 A 16 AT MIO 16XE 10 and AT AI 16XE 10 A 25 AT MIO 16XE 50 A 34 digital ports A B and C timing specifications mode input timing 4 52 mode output timing 4 53 mode 2 bidirectional timing 4 54 Port C signal assignments table 4 50 timing signals table 4 51 digital trigger specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 9 AT MIO 16E 10 and AT MIO 16DE 10 A 18 AT MIO 16XE 10 and AT AI 16XE 10 A 27 AT MIO 16XE 50 A 36 DIO lt 0 7 gt signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 ni com AT MI
28. AISENSE AISENSE2 ANSI AOGND ASIC BIOS C C CalDAC channel rate CMOS CMRR CONVERT D D A DAC AT E Series User Manual alternating current analog input channel signal A D converter analog input gate signal analog input ground signal analog input sense signal analog input sense 2 signal American National Standards Institute analog output ground signal application specific integrated circuit basic input output system or built in operating system Celsius calibration DAC reciprocal of the interchannel delay complementary metal oxide semiconductor common mode rejection ratio convert signal digital to analog D A converter G 2 ni com DACOOUT DACIOUT DAQ DC DGND DIFF DIO DMA DNL E EEPROM EISA EXTREF EXTSTROBE F FIFO FREQ OUT ft G GPCTRO_GATE GPCTR1_GATE GPCTRO_OUT National Instruments Corporation G 3 Glossary analog channel 0 output signal analog channel output signal data acquisition direct current digital ground signal differential mode digital input output direct memory access differential nonlinearity electrically erasable programmable read only memory Extended Industry Standard Architecture external reference signal external strobe signal first in first out frequency output signal feet general purpose counter 0 gate signal general purpose counter gate signal general purpose counter 0 output signal AT E Seri
29. DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 GPCTRO_OUT DO 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 FREQ _OUT DO 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 AI Analog Input DIO Digital Input Output pu pull up Table 4 6 1 0 Signal Summary for the AT MIO 16XE 50 Impedance Protection Rise Input Volts Source Sink Time Signal Name Drive Output On Off mA at V mA at V ns Bias ACH lt 0 15 gt Al 20 GQ in 25 15 3 nA parallel with 100 pF AISENSE AI 20 GQ in 25 15 3 nA parallel with 100 pF AIGND AO DACOOUT AO 0 1 Q Short circuit 5 at 10 5 at 10 2 to ground V us DAC1OUT AO 0 1 Q Short circuit 5 at 10 5 at 10 2 to ground V us AOGND AO DGND DO National Instruments Corporation 4 13 AT E Series User Manual Chapter 4 Connecting Signals Table 4 6 1 0 Signal Summary for the AT MIO 16XE 50 Continued Impedance Protection Rise Input Volts Source Sink Time Signal Name Drive Output On Off mA at V mA at V ns Bias VCC DO 0 1 Q Short circuit 1A to ground DIO lt 0 7 gt DIO Vec 0 5 13 at 24 at 0 4 1 1 50 kQ Vec 0 4 pu SCANCLK DO 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 EXTSTROBE DO 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFIO TRIG1 DIO
30. IS ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING THE SUITABILITY OF NATIONAL INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE INCORPORATED IN A SYSTEM OR APPLICATION INCLUDING WITHOUT LIMITATION THE APPROPRIATE DESIGN PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION Compliance FCC Canada Radio Frequency Interference Compliance Determining FCC Class The Federal Communications Commission FCC has rules to protect wireless communications from interference The FCC places digital electronics into two classes These classes are known as Class A for use in industrial commercial locations only or Class B for use in residential or commercial locations Depending on where it is operated this product could be subject to restrictions in the FCC rules In Canada the Department of Communications DOC of Industry Canada regulates wireless interference in much the same way Digital electronics emit weak signals during normal operation that can affect radio television or other wireless products By examining the product you purchased you can determine the FCC Class and therefore which of the two FCC DOC Warnings apply in the following sections Some products may not be labeled at all for FCC if so the reader should then assume these are Class A devices FCC Class A products only display a simple warning statement of one paragraph in length regarding interference and undesired operation Most of our products
31. Polarity ty 10 ns minimum Figure 4 26 WFTRIG Input Signal Timing ty 50 to 100 ns Figure 4 27 WFTRIG Output Signal Timing UPDATE Signal Any PFI pin can externally input the UPDATE signal which is available as an output on the PFIS UPDATE pin As an input the UPDATE signal is configured in the edge detection mode You can select any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected edge of the UPDATE signal updates the outputs of the DACs In order to use UPDATE you must set the DACs to posted update mode As an output the UPDATE signal reflects the actual update pulse that is connected to the DACs even if the updates are being externally generated by another PFI The output is an active low pulse with a pulse width of 300 to 350 ns This output is set to high impedance at startup 4 42 ni com Chapter 4 Connecting Signals When using an external UPDATE signal you must apply at least one more external update pulse than the number of points that you want to generate This is necessary for proper hardware operation otherwise the device does not indicate that the waveform generation is complete Figures 4 28 and 4 29 show the input and output timing requirements for the UPDATE signal Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 28 UPDATE Input Sign
32. STARTSCAN CONVERT fo Scan Counter Figure 4 13 Typical Posttriggered Acquisition 4 32 ni com Chapter 4 Connecting Signals TRIG1 TRIG2 STARTSCAN CONVERT Scan Counter Don t Care a ae Figure 4 14 Typical Pretriggered Acquisition TRIG1 Signal Any PFI pin can externally input the TRIG1 signal which is available as an output on the PFIO TRIG1 pin Refer to Figures 4 13 and 4 14 for the relationship of TRIG1 to the DAQ sequence As an input the TRIGI signal is configured in the edge detection mode You can select any PFI pin as the source for TRIG1 and configure the polarity selection for either rising or falling edge The selected edge of the TRIG1 signal starts the DAQ sequence for both posttriggered and pretriggered acquisitions The AT MIO 16E 1 AT MIO 16E 2 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 64E 3 support analog triggering on the PFIO TRIGI pin Refer to Chapter 3 Hardware Overview for more information on analog triggering As an output the TRIG1 signal reflects the action that initiates a DAQ sequence even if the acquisition is being externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to high impedance at startup National Instruments Corporation 4 33 AT E Series User Manual Chapter 4 Connecti
33. V Installation Electric Meter Circuit Plug in Breaker Equipment Building Fixed Local Level Secondary Installation Distribution Such Windings of Distribution as Wall Sockets Isolation Panel Transformers Category III Category II Category I AT E Series User Manual ni com Installing and Configuring the Device This chapter explains how to install and configure the AT E Series device Installing the Software Complete the following steps to install the software before installing the DAQ device 1 Install the application development environment ADE such as LabVIEW or Measurement Studio according to the instructions on the CD and the release notes 2 Install NI DAQ according to the instructions on the CD and the DAQ Quick Start Guide included with the device iy Note Itis important to install NI DAQ before installing the DAQ device to ensure that the device is properly detected Installing the Hardware You can install an AT E Series device in any available expansion slot in the PC However to achieve best noise performance you should leave as much room as possible between the AT E Series device and other devices and hardware The following are general installation instructions but consult the PC user manual or technical reference manual for specific instructions and warnings 1 Write down the AT E Series device serial number You need this serial number when you install and con
34. as long as 100 us for the circuitry to settle this much For a 16 bit device to settle within 0 0015 15 ppm or 1 LSB of the 100 mV full scale range on channel 1 the input circuitry has to settle within 0 00004 0 4 ppm or 1 400 LSB of the 4 V step It may take as long as 200 us for the circuitry to settle this much In general this extra settling time is not needed when the PGIA is switching to a lower gain Settling times can also increase when scanning high impedance signals due to a phenomenon called charge injection where the AI multiplexer injects a small amount of charge into each signal source when that source is selected If the impedance of the source is not low enough the effect of the charge a voltage error does not have decayed by the time the ADC samples the signal For this reason you should keep source impedances under 1 KQ to perform high speed scanning Due to the previously described limitations of settling times resulting from these conditions multiple channel scanning is not recommended unless sampling rates are low enough or it is necessary to sample several signals as nearly simultaneously as possible The data is much more accurate and channel to channel independent if you acquire data from each channel independently for example 100 points from channel 0 then 100 points from channel 1 then 100 points from channel 2 and so on AT E Series User Manual 3 12 ni com Chapter 3 Hardware Overview Analog Out
35. being externally generated by another PFI The output is an active low pulse with a pulse width of 50 to 100 ns This output is set to high impedance at startup Figures 4 21 and 4 22 show the input and output timing requirements for the CONVERT signal tw a gt Rising Edge Polarity j Falling Edge Polarity tw 10 ns minimum Figure 4 21 CONVERT Input Signal Timing ty 50 to 150 ns Figure 4 22 CONVERT Output Signal Timing 4 38 ni com Chapter 4 Connecting Signals The ADC switches to hold mode within 60 ns of the selected edge This hold mode delay time is a function of temperature and does not vary from one conversion to the next Separate the CONVERT pulses by at least one conversion period The sample interval counter on the AT E Series device normally generates the CONVERT signal unless you select some external source The counter is started by the STARTSCAN signal and continues to count down and reload itself until the scan is finished It then reloads itself in readiness for the next STARTSCAN pulse A D conversions generated by either an internal or external CONVERT signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence may be gated by either the hardware AIGATE signal or software command register gate AIGATE Signal Any PFI pin can externally input the AIGATE signal which is not available as
36. couples onto both connections yielding better rejection of electrostatically coupled noise Also this configuration does not load down the source other than the very high input impedance of the PGIA You can fully balance the signal path by connecting another resistor of the same value between the positive input and AIGND as shown in Figure 4 7 This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination sum of the two resistors If for example the source impedance is 2 kQ and each of the two resistors is 100 kQ the resistors load down the source with 200 KQ and produce a 1 gain error Both inputs of the PGIA require a DC path to ground in order for the PGIA to work If the source is AC coupled capacitively coupled the PGIA needs a resistor between the positive input and AIGND If the source has low impedance choose a resistor that is large enough not to significantly load the source but small enough not to produce significant input offset voltage as a result of input bias current typically 100 kQ to 1 MQ In this case you can tie the negative input directly to AIGND If the source has high output impedance you should balance the signal path as previously described using the same value resistor on both the positive and negative inputs you should be aware that there is some gain error from loading down the source National Instrument
37. coupling wo ee eee eee eeteeeeee DC Max working voltage signal common mode eeeeeeeees Overvoltage protection eee Inputs protected 100 pin devices 68 pin devices FIFO buffer size AT MIO 16E 1 cece eeeeeee AT MIO 16E 2 AT MIO 64E 3 ooo eee ee eeeeeeee Data transfers ccccccccceceeeseseseseeeees DMA modes ccecececeeeeseseseseeeeeeeeeens Configuration memory Size A 2 Each input should remain within 11 V of ground 25 V powered on 15 V powered off ACH lt 0 63 gt AISENSE AISENSE2 ACH lt 0 15 gt AISENSE 8 192 samples 2 048 samples DMA interrupts programmed I O Single transfer demand transfer 512 words ni com Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Transfer Characteristics Relative accuracy 0 0 cece eeeeseeeeeseeeees 0 5 LSB typ dithered 1 5 LSB max undithered DING cio mapras 0 5 LSB typ 1 0 LSB max NO MISSING codes eeeeeeeeeeeeeseeeneeeeeees 12 bits guaranteed Offset error Pregain error after calibration 12 uV max Pregain error before calibration 2 5 mV max Postgain error after calibration 0 5 mV max Postgain error before calibration 100 mV max Gain error relative to calibration reference After calibration gain 1 0 02 of reading max Before calibration eee 2 5 of reading max Gain
38. devices The settling time for most of the AT E Series devices is independent of the selected gain even at the maximum sampling rate The settling time for the high channel count and very high speed devices is gain dependent which can affect the useful sampling rate for a given gain No extra settling time is necessary between channels as long as the gain is constant and source impedances are low Refer to Appendix A Specifications for a complete listing of settling times for each of the AT E Series devices National Instruments Corporation 3 11 AT E Series User Manual Chapter 3 Hardware Overview When scanning among channels at various gains the settling times may increase When the PGIA switches to a higher gain the signal on the previous channel may be well outside the new smaller range For instance suppose a 4 V signal is connected to channel 0 and a mV signal is connected to channel 1 and suppose the PGIA is programmed to apply a gain of one to channel 0 and a gain of 100 to channel 1 When the multiplexer switches to channel 1 and the PGIA switches to a gain of 100 the new full scale range is 100 mV if the ADC is in unipolar mode The approximately 4 V step from 4 V to 1 mV is 4 000 of the new full scale range For a 12 bit device to settle within 0 012 120 ppm or 1 2 LSB of the 100 mV full scale range on channel 1 the input circuitry has to settle to within 0 0003 3 ppm or 1 80 LSB of the 4 V step It may take
39. ee Interface a Analog Output RTSI Bus Analog 8255 Bus l Q Digital VO 8 Digital V O Timing Control Interface Gotta contro face AO Control Data 16 A 8 8 Calibration DACs Figure 3 1 AT MIO 16E 1 and AT MIO 16E 2 Block Diagram National Instruments Corporation 3 1 AT E Series User Manual Chapter 3 Hardware Overview Figure 3 2 shows the block diagram for the AT MIO 64E 3 Voltage Calibration REF DACs 12 Bit Selection Sampling Data Je Switches ean ois Transceivers ee araso Dither Mux Circuitry Configuration Memory Al Control E T a T Level J 2 S Analog eb O Trigger Cc Trigger Circuitry r cc a H Analog Input i DMN g 7 i 1 1 c PFI Trigger Trigger Timing Control 1 Hel Analog EEPROM DMA quest Input O a ee 1 a epail Control Control Interface Counter Bus a DAQ STC 8 Timing Timing I O DAQ STC Interface Bus DAQ PnP Q IEA SO A A lt H Interface 2 1 Analog Output RTSI Bus Analog 8255 Bus O Digital VO 6 Digital O Timing Control_ Interface Output DIO Interface AO Control eee fonk 1 DACO Data 16 1 i L DAC1 1 Calibration DACs Figure 3 2 AT MIO 64E 3 Block Diagram AT E Series User Manual 3 2 ni com Chapter 3 Hardware Overvi
40. error of the AO channel either in software or with external hardware Refer to Appendix A Specifications for AO gain error information National Instruments Corporation 5 3 AT E Series User Manual Specifications This appendix lists the specifications of each device in the AT E Series These specifications are typical at 25 C unless otherwise noted AT MIO 16E 1 AT MIO 16E 2 and AT MI0 64E 3 Analog Input Input Characteristics Number of channels AT MIO 16E 1 AT MIO 16E 2 0 ee AT MIO 64E 3 ooo ee Type of ADC iui cinta iain REeSOLUtION isinira Max sampling rate AT MIO 16E 1 ooo AT MIO 16E 2 AT MIO 64E 3 ooo eee Throughput to system memory EISA machines sso ISA machines National Instruments Corporation A 1 16 single ended or 8 differential software selectable 64 single ended or 32 differential software selectable Successive approximation 12 bits 1 in 4 096 1 25 MS s guaranteed 500 kS s guaranteed 1 0 1 25 MS s 600 900 kS s AT E Series User Manual Appendix A AT E Series User Manual Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Input signal ranges Range Input Range Software Selectable Bipolar Unipolar 20 V 10 V 10 V 5 V Oto 10V 5V 2 5 V Oto5V 2V 1 V 0to2V 1V 500 mV Otol V 500 mV 250 mV 0 to 500 mV 200 mV 100 mV 0 to 200 mV 100 mV 50 mV 0 to 100 mV Input
41. in ea N a a E e a 2 2 Switchless Data Acquisition ssesssessseseesesessesresrsrrsrsersresrsresreerseeee 2 3 Base I O Address Selection sssseeeseeeeeeseessrrererrsrsrsresrrsrsrrsrsersree 2 3 DMA Channel Selection trederen hdi 2 3 Interrupt Channel Selection 0 0 cies eeeeseeseeseceeeeseeneeeseeneeeseesees 2 3 Chapter 3 Hardware Overview Analog MPUt i fernen ta tories e ova Sus A EEEE E E EE ieee EE 3 6 MPA ModE e ee ea Le es r 3 6 Input Polarity and Input Range seeseseessseeessesssrsresresesresrsresreesresesreserersresree 3 7 Considerations for Selecting Input Ranges eeeeeseeeseereereerereere 3 10 National Instruments Corporation vii AT E Series User Manual Contents Dith t erionenn aa Aa Meus agen cd bode ehh dase tea deletes eed E Multiple Channel Scanning Considerations 2 0 0 0 eee eseeeeeeneeeseeeeeeeeeaes Analog Output 1 ce fac haara a n E E E IEEE Ea Analog Output Reference Selection sseesssesrsseersressresersrsrrsrrersresesrsrrsrseese Analog Output Polarity Selection eee eeeeseceeesseesseeseceeeeseeneetaeeneeeaes Analog Output Reglitch Selection ee eeeeseeseeeseeseeeseeeensesaeseeeeaeenees A MALO S Tristranski an Seay ohne dies sa eed cutee Sa odedans E A AE E A TA NA Digital 1 O sesscsctas exces scapvestcas na R a ER A eases cela deans avrg eeeanas Timing Signal Routing iiceoe er scevenesdesabua used e E Ea Programmable Function Inputs 200 0 es eeeecess
42. signal which is available as an output on the PFI9 GPCTRO_GATE pin As an input the GPCTRO_GATE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform actions such as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTRO_GATE signal reflects the actual gate signal connected to general purpose counter 0 even if the gate is being externally generated by another PFI This output is set to high impedance at startup National Instruments Corporation 4 45 AT E Series User Manual Chapter 4 Connecting Signals Figure 4 32 shows the timing requirements for the GPCTRO_GATE signal Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 32 GPCTRO_GATE Signal Timing in Edge Detection Mode GPCTRO_OUT Signal This signal is available only as an output on the GPCTRO_OUT pin The GPCTRO_OUT signal reflects the terminal count TC of general purpose counter 0 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to high impedance at startup Figure 4 33 shows the timing of the GPCTRO_OUT signal GPCTRO_SOURCE
43. that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments
44. the Lab VIEW and LabWindows CVI documentation sets and the NI DAQ documentation After you set up the hardware system use either the application software LabVIEW or LabWindows CVI xii ni com About This Manual or the NI DAQ documentation to help you write your application If you have a large and complicated system it is worthwhile to look through the software documentation before you configure the hardware Accessory installation guides or manuals If you are using accessory products read the terminal block and cable assembly installation guides They explain how to physically connect the relevant pieces of the system Consult these guides when you are making the connections Related Documentation The following documents contain information that you might find helpful as you read this manual National Instruments Corporation AT E Series Register Level Programmer Manual DAQ STC Technical Reference Manual NI Developer Zone tutorial Field Wiring and Noise Considerations for Analog Signals at ni com zone xiii AT E Series User Manual Introduction This chapter describes the AT E Series devices lists what you need to get started describes the optional software and optional equipment and explains how to unpack the AT E Series device About the AT E Series Thank you for buying an NI AT E Series device The AT E Series devices are the first completely Plug and Play compatible multifunction analog digital
45. the major code transitions This uniform glitch energy appears as a multiple of the update rate in the frequency spectrum Notice that this reglitch circuit does not eliminate the glitches it only makes them more uniform in size Reglitching is normally disabled at startup and can be independently enabled for each channel through software AT E Series User Manual AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16XE 10 and AT AI 16XE 10 only In addition to supporting internal software triggering and external digital triggering to initiate a data acquisition sequence the AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16XE 10 and AT AI 16XE 10 also support analog triggering You can configure the analog trigger circuitry to accept either a direct analog input from the PFIO TRIG1 pin on the I O connector or a postgain signal from the output of the PGIA as shown in Figure 3 8 The trigger level range for the direct analog channel is 10 V in 78 mV steps for the AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 and 10 V in 4 9 mV steps for the AT MIO 16XE 10 and AT AI 16XE 10 The range for the post PGIA trigger selection is simply 3 14 ni com Chapter 3 Hardware Overview the full scale range of the selected channel and the resolution is that range divided by 256 for the AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 and divided by 4 096 for the AT MIO 16XE 10 and AT AI 16XE 10 3 Note The PFIO TRIG1 pin is a high impedance input
46. their overall flexibility by matching the input signal ranges to those that the ADC can accommodate The AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 National Instruments Corporation 3 7 AT E Series User Manual Chapter 3 Hardware Overview AT MIO 16E 10 and AT MIO 16DE 10 have gains of 0 5 1 2 5 10 20 50 and 100 and are suited for a wide variety of signal levels With the proper gain setting you can use the full resolution of the ADC to measure the input signal Table 3 2 shows the overall input range and precision according to the input range configuration and gain used Table 3 2 Actual Range and Measurement Precision Range Configuration Gain Actual Input Range Precision 0 to 10 V 1 0 Oto 10 V 2 44 mV 2 0 0to 5 V 1 22 mV 5 0 0 to 2 V 488 28 uV 10 0 Oto 1 V 244 14 uV 20 0 0 to 500 mV 122 07 uV 50 0 0 to 200 mV 48 83 uV 100 0 0 to 100 mV 24 41 uV 5 to 5 V 0 5 10 to 10 V 4 88 mV 1 0 5 to 5 V 2 44 mV 2 0 2 5 to 2 5 V 1 22 mV 5 0 1 to 1 V 488 28 uV 10 0 500 to 500 mV 244 14 uV 20 0 250 to 250 mV 122 07 uV 50 0 100 to 100 mV 48 83 uV 100 0 50 to 50 mV 24 41 uV 1 The value of 1 LSB of the 12 bit ADC that is the voltage increment corresponding to a change of one count in the ADC 12 bit count Note Refer to Appendix A Specifications for absolute maximum ratings e AT MIO 16XE 10 AT AI 16XE 10 AT MIO 16XE 50 These devices have two input polarities unipola
47. use an AT E Series device in a non Plug and Play system as a switchless DAQ device A non Plug and Play system is a system in which the Configuration Manager has not been installed and which does not contain any non NI Plug and Play products You use a configuration utility to enter the base address DMA and interrupt selections and the application software assigns them to the device 3 Note Avoid resource conflicts with non NI devices For example do not configure two devices for the same base address Base 1 0 Address Selection The AT E Series devices can be configured to use base addresses in the range of 20 to FFEO hex Each AT E Series device occupies 32 bytes of address space and must be located on a 32 byte boundary Therefore valid addresses include 100 120 140 3C0 3E0 hex This selection is software configured and does not require you to manually change any settings on the device DMA Channel Selection The AT E Series devices can achieve high transfer rates by using up to three 16 bit DMA channels You can use these DMA channels for data transfers with the AI AO and general purpose counter sections of the device The AT E Series devices can use only 16 bit DMA channels which correspond to channels 5 6 and 7 in an ISA computer and channels 0 1 2 3 5 6 and 7 in an EISA computer These selections are all software configured and do not require you to manually change any settings on the device Interrupt Channel
48. with respect to the AT E Series device In these cases the PGIA can reject any voltage caused by ground potential differences between the signal source and the device In addition with differential input connections the PGIA can reject common mode noise pickup in the leads connecting the signal sources to the device The PGIA can reject common mode signals as long as V and V are both within 11 V of AIGND The AT MIO 16XE 50 has the additional restriction 4 26 ni com Chapter 4 Connecting Signals that V V added to the gain times V Vin must be within 26 V of AIGND At gains of 10 and 100 this is roughly equivalent to restricting the two input voltages to within 8 V of AIGND Analog Output Signal Connections The AO signals are DACOOUT DACIOUT EXTREF and AOGND 3 Note DACOOUT and DAC1OUT are not available on the AT AI 16XE 10 EXTREF is not available on the AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 DACOOUT is the voltage output signal for AO channel 0 DACIOUT is the voltage output signal for AO channel 1 EXTREF is the external reference input for both AO channels You must configure each AO channel individually for external reference selection in order for the signal applied at the external reference input to be used by that channel If you do not specify an external reference the channel uses the internal reference 3 Note You cannot use an external AO reference with the AT MIO 1
49. you want to develop your own cable however the following guidelines may be useful For the AI signals shielded twisted pair wires for each AI pair yield the best results assuming that you use differential inputs Tie the shield for each signal pair to the ground reference at the source You should route the analog lines separately from the digital lines When using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so results in noise coupling into the analog signals from transient digital signals Mating connectors and a backshell kit for making custom 68 pin cables are available from NI National Instruments Corporation 1 5 AT E Series User Manual Chapter 1 Introduction Unpacking The AT E Series device is shipped in an antistatic package to prevent electrostatic damage to the device Electrostatic discharge can damage several components on the device UN Caution Never touch the exposed pins of connectors To avoid such damage in handling the device take the following precautions e Ground yourself using a grounding strap or by holding a grounded object e Touch the antistatic package to a metal part of the computer chassis before removing the device from the package Remove the device from the package and inspect the device for loose components or any sign of damage Notify NI if the device appears damaged in any way Do not install a damaged device into the co
50. 0 table 4 14 description table 4 6 PFI2 CONVERT signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 6 PFI3 GPCTR1I_SOURCE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 7 ni com PFI4 GPCTR1_GATE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 7 PFIS5 UPDATE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 7 PFI6 WFTRIG signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 14 description table 4 7 PFI7 STARTSCAN signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 14 description table 4 7 PFI8 GPCTRO_SOU
51. 0 1 Q Short circuit 5 at 10 5 at 10 15 to ground V us DACIOUT AO 0 1 Q Short circuit 5 at 10 5 at 10 15 to ground V us EXTREF AI 10 kQ 35 25 AOGND AO DGND DO VCC DO 0 1 Q Short circuit 1A to ground DIO lt 0 7 gt DIO Vec 0 5 13 at 24 at 0 4 1 1 50 KQ pu Vec 0 4 PA lt 0 7 gt DIO Vec 0 5 2 5 at 3 9 2 5 at 0 4 5 100 kQ pu PB lt 0 7 gt DIO Vec 0 5 2 5 at 3 9 2 5 at 0 4 5 100 kQ pu PC lt 0 7 gt DIO Vec 0 5 2 5 at 3 9 2 5 at 0 4 5 100 kQ pu SCANCLK DO 3 5 at 5 at 0 4 1 5 50 KQ pu Vec 0 4 EXTSTROBE DO 3 5 at 5 at 0 4 1 5 50 KQ pu Vec 0 4 PFIO TRIG1 DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 KQ pu Vec 0 4 PFI1 TRIG2 DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI2 CONVERT DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 KQ pu Vec 0 4 PFI3 GPCTR1_SOURCE DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 KQ pu Vec 0 4 AT E Series User Manual 4 10 ni com Table 4 4 1 0 Signal Summary for the AT MIO 16E 10 and AT MIO 16DE 10 Continued Chapter 4 Connecting Signals Impedance Protection Rise Input Volts Source Sink Time Signal Name Drive Output On Off mA at V mA at V ns Bias PFI4 GPCTR1_GATE DIO Vec 0 5 3 5at 5 at 0 4 1 5 50 kQ pu Vec 0 4 GPCTR1_OUT DO 3 5at 5 at 0 4 1 5 50 KQ pu Vec 0 4 PFIS5 UPDATE DIO Vec 0 5 3 5at 5 at 0 4 1 5 50 KQ pu Vec 0 4
52. 0 and AT MIO 16DE 10 A 15 AT MIO 16XE 10 A 24 AT MIO 16XE 50 A 33 TRIGI signal timing connections 4 33 TRIG2 signal timing connections 4 34 I 13 AT E Series User Manual Index triggers analog 3 14 block diagram 3 15 RTSI triggers 3 20 specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 analog trigger A 9 digital trigger A 9 RTSI A 10 AT MIO 16E 10 and AT MIO 16DE 10 digital trigger A 18 RTSI A 18 AT MIO 16XE 10 and AT AI 16XE 10 analog trigger A 27 digital trigger A 27 RTSI A 27 AT MIO 16XE 50 digital trigger A 36 RTSI A 36 troubleshooting resources D 1 troubleshooting See questions about AT E series boards U UISOURCE signal 4 44 unipolar input AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 3 7 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 3 8 mixing bipolar and unipolar channels note 3 9 unipolar output 3 13 unpacking AT E series boards 1 6 UPDATE signal timing connections 4 42 AT E Series User Manual 1 14 V VCC signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 voltage output AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 7 AT MIO 16E 10 and AT MIO 16DE 10 A 15 AT MIO 16XE 10 A 25 AT MIO 16XE 50 A 34 W waveform generation timing connections UISOURCE signal 4 44 UPDATE signal
53. 00 kHz internal timebase normally generates the UISOURCE signal unless you select some external source General Purpose Timing Signal Connections AT E Series User Manual The general purpose timing signals are GPCTRO_SOURCE GPCTRO_GATE GPCTRO_OUT GPCTRO_UP_DOWN GPCTR1_SOURCE GPCTR1_GATE GPCTR1_OUT GPCTR1_UP_DOWN and FREQ_OUT GPCTRO_SOURCE Signal Any PFI pin can externally input the GPCTRO_SOURCE signal which is available as an output on the PFI8 GPCTRO_SOURCE pin As an input the GPCTRO_SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO_SOURCE and configure the polarity selection for either rising or falling edge 4 44 ni com Chapter 4 Connecting Signals As an output the GPCTRO_SOURCE signal reflects the actual clock connected to general purpose counter 0 even if another PFI is externally inputting the source clock This output is set to high impedance at startup Figure 4 31 shows the timing requirements for the GPCTRO_SOURCE signal tp 50 ns minimum ty 23 ns minimum Figure 4 31 GPCTRO_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTRO_SOURCE signal unless you select some external source GPCTRO_GATE Signal Any PFI pin can externally input the GPCTRO_GATE
54. 1 be Interchannel Delay Scan Interval Figure C 2 Comparing Interchannel Delay and Scan Interval Timing and Digital 1 0 What types of triggering can be implemented in hardware on my AT E Series device Digital triggering is supported by hardware on every AT E Series MIO device In addition the AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16XE 10 and AT AI 16XE 10 support analog triggering in hardware What added functionality does the DAQ STC make possible in contrast to the Am9513 The DAQ STC incorporates much more than just 10 Am9513 style counters within one chip In fact the DAQ STC has the complexity of more than 24 chips The DAQ STC makes possible PFI lines analog triggering selectable logic level and frequency shift keying The DAQ STC also makes buffered operations possible such as direct up down control single or pulse train generation equivalent time sampling buffered period and buffered semiperiod measurement What is the difference in timebases between the Am9513 counter timer and the DAQ STC The DAQ STC based MIO devices have a 20 MHz timebase The Am9513 based MIO devices have a 1 MHz or 5 MHz timebase National Instruments Corporation C 7 AT E Series User Manual Appendix C Common Questions AT E Series User Manual The counter timer examples supplied with NI DAQ are not compatible with an AT E Series device Where can I find examples to illustrate the use of the DAQ STC
55. 11 ACH4 ACH12 ACH5 ACH13 ACH6 ACH14 ACH7 ACH15 AISENSE DACOOUT DAC10UT EXTREF AOGND DGND DIOO DIO4 DIO1 DIO5 DIO2 DIOG DIO3 DIO7 DGND 5V 5V SCANCLK EXTSTROBE PFIO TRIG1 PFI1 TRIG2 PFI2 CONVERT PFI3 GPCTR1_SOURCE PFI4 GPCTR1_GATE GPCTR1_OUT PFI5 UPDATE PFI6 WFTRIG PFI7 STARTSCAN PFI8 GPCTRO_SOURCE PFI9 GPCTRO_GATE GPCTRO_OUT FREQ_OUT 1 51 2 52 3 53 4 54 5 55 6 56 7 57 8 58 9 59 10 60 11 61 12 62 13 63 14 64 15 65 16 66 17 67 18 68 19 69 20 70 21 71 22 72 23 73 24 74 25 75 26 76 27 77 28 78 29 79 30 80 31 81 32 82 33 83 34 84 35 85 36 86 37 87 38 88 39 89 40 90 at 91 42 92 43 93 44 94 45 95 46 96 47 97 48 98 49 99 50 100 Ue PC7 GND PC6 GND PC5 GND PC4 GND PC3 GND PC2 GND PC1 GND PCO GND PB7 GND PB6 GND PB5 GND PB4 GND PB3 GND PB2 GND PB1 GND PBO GND PA7 GND PA6 GND PA5 GND PA4 GND PA3 GND PA2 GND PA1 GND PAO GND 5V GND Figure 4 3 1 0 Connector Pin Assignment for the AT MIO 16DE 10 4 4 ni com Chapter 4 Connecting Signals 1 0 Connector Signal Descriptions Table 4 2 1 0 Signal Summary for the AT E Series Signal Nam
56. 16 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 13 description table 4 5 National Instruments Corporation differential connections for floating signal sources 4 22 AISENSE signal analog input connections 4 15 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 13 description table 4 5 AISENSE2 signal analog input connections 4 15 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 description table 4 5 amplifier characteristics AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 3 AT MIO 16E 10 and AT MIO 16DE 10 A 13 AT MIO 16XE 10 and AT AI 16XE 10 A 22 AT MIO 16XE 50 A 31 analog input common questions about C 3 considerations for selecting input ranges 3 10 dither 3 10 input modes 3 6 input polarity and range 3 7 multiple channel scanning considerations 3 11 signal connections 4 15 l 1 AT E Series User Manual Index analog input specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 1 amplifier characteristics A 3 dynamic characteristics A 4 input characteristics A 1 stability A 5 transfer characteristics A 3 AT MIO 16E 10 and AT MIO 16DE 10 amplifier characteristics A 13 dynamic characteristics A 14 inp
57. 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 13 description table 4 5 AT E series boards See also hardware overview common questions about C 1 custom cabling 1 5 ni com features 1 1 getting started 1 2 optional equipment 1 5 software programming choices register level programming 1 4 unpacking 1 6 base I O address selection 2 3 bipolar input AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 3 7 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 3 8 bipolar output 3 13 3 14 block diagrams AT AI 16XE 10 3 5 AT MIO 16E 1 and AT MIO 16E 2 3 1 AT MIO 16E 10 and AT MIO 16DE 10 3 3 AT MIO 16XE 10 3 4 AT MIO 16XE 50 3 6 AT MIO 64E 3 3 2 board configuration See configuration bus interface specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 10 AT MIO 16E 10 and AT MIO 16DE 10 A 19 AT MIO 16XE 10 and AT AI 16XE 10 A 28 AT MIO 16XE 50 A 36 C cables See also I O connectors field wiring considerations 4 55 optional equipment 1 5 National Instruments Corporation l 3 Index calibration adjusting for gain error 5 3 external calibration 5 2 loading calibration constants 5 1 self calibration 5 2 charge injection 3 12 clocks board and RTSI 3 20 commonly asked questions See questions about AT E series boards common mode si
58. 32 66 ACH9 ACH10 31 65 ACH2 ACHS 30 64 AIGND AIGND 29 63 ACH11 ACH4 28 62 AISENSE AIGND 27 61 ACH12 ACH13 26 60 ACHS ACH6 25 59 AIGND AIGND 24 58 ACH14 ACH15 23 57 ACH7 DACOOUT 22 56 AIGND DAC10UT 21 55 AOGND EXTREF 20 54 AOGND DIO4 19 53 DGND DGND 18 52 DIOO DIO1 171511 pios DIO6 16 50 DGND DGND 15 49 DIO2 5V 1448 DIO7 DGND 13 47 DIO3 DGND 12 46 SCANCLK PFIO TRIG1 11 45 EXTSTROBE PFI1 TRIG2 10 44 DGND DGND 9 43 PFI2 CONVERT 5V 8 42 PFI3 GPCTR1_SOURCE DGND 7 41 PFI4 GPCTR1_GATE PFI5 UPDATE 6 40 GPCTR1_OUT PFI6 WFTRIG 5 39 DGND DGND 4 38 PFI7 STARTSCAN PFI9 GPCTRO_GATE 3 37 PFI8 GPCTRO_SOURCE GPCTRO_OUT 2 36 DGND FREQ_OUT Hisl DGND Not available on AT Al 16XE 10 Not available on AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 Figure 4 1 1 0 Connector Pin Assignment for the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT Al 16XE 10 and AT MIO 16XE 50 AT E Series User Manual 4 2 ni com Chapter 4 Connecting Signals AIGND AIGND ACHO ACH8 ACH1 ACH9 ACH2 ACH10 ACH3 ACH11 ACH4 ACH12 ACH5 ACH13 ACH6 ACH14 ACH7 ACH15 AISENSE DACOOUT DAC10UT EXTREF AOGND DGND DIOO DIO4 DIO1 DIO5 DI
59. 4 Connecting Signals AN Caution Under no circumstances should you connect these 5 V power pins directly to analog or digital ground or to any other voltage source on the AT E Series device or any other device Doing so can damage the AT E Series device and the PC NI is not liable for damage resulting from such a connection Timing Connections Caution Exceeding the maximum input voltage ratings which are listed in Tables 4 3 through 4 6 can damage the AT E Series device and the PC NI is not liable for any damage resulting from such signal connections All external control over the timing of the AT E Series device is routed through the 10 programmable function inputs labeled PFIO through PFI9 These signals are explained in detail in the next section Programmable Function Input Connections These PFIs are bidirectional as outputs they are not programmable and reflect the state of many data acquisition waveform generation and general purpose timing signals There are five other dedicated outputs for the remainder of the timing signals As inputs the PFI signals are programmable and can control any data acquisition waveform generation and general purpose timing signals The data acquisition signals are explained in the DAQ Timing Connections section later in this chapter The waveform generation signals are explained in the Waveform Generation Timing Connections section later in this chapter The general purpose timing signals are exp
60. 6XE 10 AT AI 16XE 10 or AT MIO 16XE 50 AO configuration options are explained in the Analog Output section of Chapter 3 Hardware Overview AOGND is the ground reference signal for both AO channels and the external reference signal Figure 4 10 shows how to make AO connections and the external reference input connection to the AT E Series device National Instruments Corporation 4 27 AT E Series User Manual Chapter 4 Connecting Signals EXTREF Ot DACOOUT g Channel 0 External ra bcd Reference y Signal ret Optional VOUT 0 Load VOUT 1 ead DAC10UT a Lo lt Channel 1 AOGND ss Analog Output Channels 1 O Connector al Figure 4 10 AO Connections The external reference signal can be either a DC or an AC signal The device multiplies this reference signal by the DAC code divided by the full scale DAC code to generate the output voltage Digital 1 0 Signal Connections A The digital I O signals are DIO lt 0 7 gt and DGND DIO lt 0 7 gt are the signals making up the DIO port and DGND is the ground reference signal for the DIO port You can program all lines individually to be inputs or outputs The AT MIO 16DE 10 has 24 additional DIO lines configured as three 8 bit ports PA lt 0 7 gt PB lt 0 7 gt and PC lt 0 7 gt You can configure each port for both input and output in various combinations with some handshaking cap
61. ACH29 ACH22 13 14 ACH30 ACH23 15 16 ACH31 ACH32 17 18 ACH40 ACH33 19 20 ACH41 ACH34 21 22 ACH42 ACH35 23 24 ACH43 AISENSE2 25 26 AIGND ACH36 27 28 ACH44 ACH87 29 30 ACH45 ACH38 31 32 ACH46 ACH39_ 33 34 ACH47 ACH48 35 36 ACH56 ACH49 37 38 ACH57 ACH50 39 40 ACH58 ACH51 41 42 ACH59 ACH52 43 44 ACH60 ACH53 45 46 ACH61 ACH54 47 48 ACH62 ACH55 49 50 ACH63 Figure B 6 50 Pin Extended Al Connector Pin Assignments National Instruments Corporation B 7 AT E Series User Manual Common Questions This appendix contains a list of commonly asked questions and their answers relating to usage and special features of the AT E Series device General Information What are the AT E Series devices The AT E Series devices are switchless and jumperless enhanced MIO devices that use the DAQ STC for timing What is the DAQ STC The DAQ STC is the new system timing control ASIC application specific integrated circuit designed by NI and is the backbone of the AT E Series devices The DAQ STC contains seven 24 bit counters and three 16 bit counters The counters are divided into three groups e Analog input two 24 bit two 16 bit counters e Analog output three 24 bit one 16 bit counters e General purpose counter timer functions two 24 bit counters The groups can be configured inde
62. BFBg INTRg Mode 1 Output OBF ACK T O VO INTR ACK3 OBF INTRg AT E Series User Manual 4 50 ni com Chapter 4 Connecting Signals Table 4 7 Port C Signal Assignments Continued Group A Group B Programming Mode PC7 PC6 PCS PC4 PC3 PC2 PC1 PCO Mode 2 OBF ACK IBF STB INTR VO T O T O Indicates that the signal is active low This section lists the timing specifications for handshaking with the AT MIO 16DE 10 port C circuitry The handshaking lines STB and IBF synchronize input transfers The handshaking lines OBF and ACK synchronize output transfers Table 4 8 summarizes the port C signals used in the timing diagrams that follow Table 4 8 Port C Signal Descriptions Name Type Description STB Input Strobe Input A low signal on this handshaking line loads data into the input latch IBF Output Input Buffer Full A high signal on this handshaking line indicates that data has been loaded into the input latch This is an input acknowledge signal ACK Input Acknowledge Input A low signal on this handshaking line indicates that the data written from the selected port has been accepted This signal is a response from the external device that it has received the data from the AT MIO 16DE 10 OBF Output Output Buffer Full A low signal on this handshaking line indicates that data has been written from the selected port
63. Butfer Calibration 16 Bit Sampling AID Converter Programmable Gain Amplifier Data Transceivers EEPROM M SAP Al Control Configuration Memory Trigger Circuitry Trigger Level 5 DACs Trigger T T gt Analog input OMA PFI Trigger Trigger Timing Control ee Analog EEPROM DMA Request Input 1 Gontrol Interface Control Counter Bus Timing VO DAQ STC Interface oe 1 Analog Output 1 RTSI Bus Digital VO Timing Control Interface DAQ STO Plu Bus DAQ PnP an Interface Play Analog 8255 Output DIO a Control 1 Control Digital 1 0 8 I O Connector AT I O Channel AO Control i paco 1 E 1 1 i I DAC1 i 1 if Data 16 Figure 3 4 AT MIO 16XE 10 Block Diagram AT E Series User Manual 3 4 ni com Chapter 3 Hardware Overview Figure 3 5 shows a block diagram for the AT AI 16XE 10 ner Buffer Calibration DACs Voltage REF Mux Mode tot Selection programmana Sampling ADC Data Switches Mn AD FIFO Transceivers _ Amplifier Converter EEPROM V Configuration Q Mamory Al Control c O z 2 o
64. D PC3 PC2 GND PCO PB7 GND PB5 PB4 GND GND PB1 PBO GND PA6 PA5 GND PA3 PA2 GND PAO 5V N C N C N C N C N C N C N C N C N C aa 34 68 33 67 32 66 31 65 30 64 29 63 28 62 27 61 26 60 25 59 24 58 23 57 22 56 21 55 20 54 19 53 18 52 17 51 16 50 15 49 14 48 13 47 12 46 11145 1044 43 42 41 40 39 38 37 36 35 o P A oO N oo PC7 GND GND PC4 GND GND PC1 GND GND PB6 GND GND PB3 PB2 GND GND PA7 GND GND PA4 GND GND PA1 GND GND N C N C N C N C N C N C N C N C N C National Instruments Corporation Figure B 2 68 Pin DIO Connector Pin Assignments B 3 AT E Series User Manual Appendix B Optional Cable Connector Descriptions AT E Series User Manual Figure B 3 shows the pin assignments for the 68 pin extended AI connector This is the other 68 pin connector available when you use the SH1006868 cable assembly with the AT MIO 64E 3 ACH 24 ACH 17 ACH 18 ACH 27 ACH 20 ACH 21 ACH 30 ACH 23 ACH 32 ACH 41 ACH 34 ACH 35 AIGND ACH 44 ACH 37 ACH 38 ACH 47 ACH 48 ACH 49 ACH 58 ACH 51 ACH 52 ACH 61 ACH 54 ACH 55 N C N C N C N C N C N C N C N C N C Z 34 68 33 67 32 66 31 65 30 64 29 63 28 62 27 61 26 60 25
65. D DO VCC DO 01 Q Short circuit 1A to ground DIO lt 0 7 gt DIO Vec 0 5 13 at 24 at 0 4 1 1 50 kQ pu Vec 0 4 SCANCLK DO 3 5 al 5 at 0 4 1 5 50 kQ pu Vec 0 4 EXTSTROBE DO 3 5 al 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFIO TRIG1 DIO Vec 0 5 3 5 al 5 at 0 4 1 5 4 75 KQ pu Vec 0 4 PFI 1 TRIG2 DIO Vec 0 5 3 5 al 5 at 0 4 1 5 50 KQ pu Vec 0 4 PFI2 CONVERT DIO Vec 0 5 3 5 al 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI3 GPCTR1_SOURCE DIO Vec 0 5 3 5a 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI4 GPCTR1_GATE DIO Vec 0 5 3 5a 5 at 0 4 1 5 50 kQ pu Vec 0 4 GPCTR1_OUT DO 3 5 al 5 at 0 4 1 5 50 KQ pu Vec 0 4 PFI5 UPDATE DIO Vec 0 5 3 5 al 5 at 0 4 1 5 50 kQ pu Vec 0 4 AT E Series User Manual 4 12 ni com Table 4 5 1 0 Signal Summary for the AT MIO 16XE 10 and AT Al 16XE 10 Continued Chapter 4 Connecting Signals AO Analog Output DO Digital Output The tolerance on the 50 kQ pull up and pull down resistors is very large Actual value may range between 17 kQ and 100 kQ Impedance Protection Rise Input Volts Source Sink Time Signal Name Drive Output On Off mA at V mA at V ns Bias PFI6 WFTRIG DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 KQ pu Vec 0 4 PFI7 STARTSCAN DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI8 GPCTRO_SOURCE DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI9 GPCTRO_GATE
66. DAQ AT E Series User Manual Multifunction 1 0 Devices for the PC AT Wy NATIONAL May 2002 Edition p INSTRUMENTS Part Number 370507A 01 Worldwide Technical Support and Product Information ni com National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 683 0100 Worldwide Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Brazil 011 3262 3599 Canada Calgary 403 274 9391 Canada Montreal 514 288 5722 Canada Ottawa 613 233 5949 Canada Qu bec 514 694 8521 Canada Toronto 905 785 0085 China Shanghai 021 6555 7838 China ShenZhen 0755 3904939 Czech Republic 02 2423 5774 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Greece 30 1 42 96 427 Hong Kong 2645 3186 India 91 80 4190000 Israel 03 6393737 Italy 02 413091 Japan 03 5472 2970 Korea 02 3451 3400 Malaysia 603 9596711 Mexico 001 800 010 0793 Netherlands 0348 433466 New Zealand 09 914 0488 Norway 32 27 73 00 Poland 0 22 3390 150 Portugal 351 210 311 210 Russia 095 238 7139 Singapore 6 2265886 Slovenia 386 3 425 4200 South Africa 11 805 8197 Spain 91 640 0085 Sweden 08 587 895 00 Switzerland 056 200 51 51 Taiwan 02 2528 7227 United Kingdom 01635 523545 For further support information see the Technical Support and Professional Services appendix To comment on the documentation send email to techpubs ni com 1994 2002 N
67. E 10 only dynamic characteristics A 25 output characteristics A 24 stability A 25 transfer characteristics A 24 voltage output A 25 bus interface A 28 digital I O A 25 physical A 28 power requirements A 28 timing I O A 26 AT E Series User Manual I 12 triggers analog trigger A 27 digital trigger A 27 RTSI A 27 AT MIO 16XE 50 analog input amplifier characteristics A 31 dynamic characteristics A 32 input characteristics A 30 transfer characteristics A 31 analog output dynamic characteristics A 34 output characteristics A 33 stability A 34 transfer characteristics A 33 voltage output A 34 bus interface A 36 digital I O A 34 physical A 37 timing I O A 35 triggers digital trigger A 36 RTSI A 36 stability analog input specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 5 AT MIO 16E 10 and AT MIO 16DE 10 A 14 AT MIO 16E 50 A 33 AT MIO 16XE 10 and AT AI 16XE 10 A 24 analog output specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 7 AT MIO 16E 10 and AT MIO 16DE 10 A 16 AT MIO 16XE 10 A 25 AT MIO 16XE 50 A 34 ni com STARTSCAN signal timing connections 4 36 STB signal table 4 51 support technical D 1 switchless data acquisition 2 3 system integration services D 1 T technical support D 1 telephone technical support D 1 theory of operation See hardware overview timebases board and RTSI clocks 3 20 timing connections 4 30 common qu
68. I DAQ Help NI DAQ version 6 7 or later or the NI DAQ Function Reference Manual NI DAQ version 6 6 or earlier Installing and Configuring the Device AT E Series User Manual How do you set the base address for an AT E Series device Windows NT will automatically detect an AT E Series device However you must use the Measurement amp Automation Explorer MAX to assign the base address For Windows 95 the base address can be changed in the Device Manager For Windows 2000 XP Me 9x the operating system detects the device and preassigns a base address 0x 180 200 220 240 280 and 300 are typical base addresses For operating system specific installation and troubleshooting instructions refer to ni com support daq What jumpers should I be aware of when configuring my AT E Series device The AT E Series devices do not contain any jumpers they are also switchless Which NI document should I read first to get started using DAQ software The DAQ Quick Start Guide and NI DAQ or application software release notes documentation are good places to start C 2 ni com Appendix C Common Questions What version of NI DAQ must I have to program my AT E Series device You must have version 4 9 0 or later for the AT MIO 16XE 10 and AT AI 16XE 10 version 4 8 0 or later for the AT MIO 16E 1 and version 4 6 1 or later for all other AT E Series devices For AT MIO 16E 10 and AT MIO 16DE 10 users you must have version 5 04 for W
69. NSE hie cchsssenczentvsrvedvactusssvateebaveetis Rising or falling edge Pulse widths ssei28 iesiri iins 10 ns min RTSI Trigger Lines sisisi neiii tes 7 Calibration Recommended warm up time 15 min Calibration interval s s s 1 year External calibration reference gt 6 and lt 9 999V Onboard calibration reference Eevee eee ence 5 000 V 3 mV over full operating temperature actual value stored in EEPROM Temperature coefficient 0 2 ppm C max Long term stability oe eee 15 ppm 41 000 h Bus Interface Typer ENA Slave Power Requirement 5 VDC 45 aiima 0 75 A Power available at I O connector 4 65 VDC to 5 25 VDC at lA AT E Series User Manual A 36 ni com Appendix A Specifications for AT MIO 16XE 50 Physical Dimensions not including connectors eee 33 8 by 9 9 cm 13 3 by 3 9 in T O CONNECHOL ccc eee ececeeeeseseeesensseeeeeees 68 pin male SCSI II type Maximum Working Voltage Maximum working voltage refers to the signal voltage plus the common mode voltage Channel to earth eee eeeeeeeeeeee 42 V Installation Category II Channel to channel eee eee 42 V Installation Category II Environmental Operating temperature ee 0 to 55 C Storage temperature 00 eee 20 to 70 C Humidity scinni nannaa 10 to 90 RH noncondensing Maximum altitude cccccceeeeseees 2 000 meters Pollution degree indoor use only
70. NVERT signal is shown in Figure 3 14 AT E Series User Manual 3 18 ni com Chapter 3 Hardware Overview a RTSI Trigger lt 0 6 gt _ gt gt gt CONVERT PFI lt 0 9 gt lt Sample Interval Counter TC gt GPCTRO_OUT ae Figure 3 14 CONVERT Signal Routing This figure shows that CONVERT can be generated from a number of sources including the external signals RTSI lt 0 6 gt and PFI lt 0 9 gt and the internal signals Sample Interval Counter TC and GPCTRO_OUT Many of these timing signals are also available as outputs on the RTSI pins as indicated in the RTS Triggers section later in this chapter and on the PFI pins as indicated in Chapter 4 Connecting Signals National Instruments Corporation 3 19 AT E Series User Manual Chapter 3 Hardware Overview Programmable Function Inputs The 10 PFIs are connected to the signal routing multiplexer for each timing signal and software can select one of the PFIs as the external source for a given timing signal It is important to note that any of the PFIs can be used as an input by any of the timing signals and that multiple timing signals can use the same PFI simultaneously This flexible routing scheme reduces the need to change physical connections to the I O connector for different applications You can also individually enable each of the PFI pins to output a specific internal timing signal For example if you n
71. NY APPLICATION INCLUDING THE ABOVE RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS CAN BE IMPAIRED BY ADVERSE FACTORS INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY COMPUTER HARDWARE MALFUNCTIONS COMPUTER OPERATING SYSTEM SOFTWARE FITNESS FITNESS OF COMPILERS AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION INSTALLATION ERRORS SOFTWARE AND HARDWARE COMPATIBILITY PROBLEMS MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL DEVICES TRANSIENT FAILURES OF ELECTRONIC SYSTEMS HARDWARE AND OR SOFTWARE UNANTICIPATED USES OR MISUSES OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER ADVERSE FACTORS SUCH AS THESE ARE HEREAFTER COLLECTIVELY TERMED SYSTEM FAILURES ANY APPLICATION WHERE A SYSTEM FAILURE WOULD CREATE A RISK OF HARM TO PROPERTY OR PERSONS INCLUDING THE RISK OF BODILY INJURY AND DEATH SHOULD NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM FAILURE TO AVOID DAMAGE INJURY OR DEATH THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO PROTECT AGAINST SYSTEM FAILURES INCLUDING BUT NOT LIMITED TO BACK UP OR SHUT DOWN MECHANISMS BECAUSE EACH END USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM NATIONAL INSTRUMENTS TESTING PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER MAY USE NATIONAL INSTRUMENTS PRODUCTS IN COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY NATIONAL INSTRUMENTS THE USER OR APPLICATION DESIGNER
72. O P Trigger Level Analog F IRQ gt gt f DACs Trigger DMA 8 r Circuitry Q m Toge a Analog Input DMN 1 P a O PFI Trigger Trigger Timing Control Se Analog IEEPROM DMA o g N gamer pag ste y on reo ae 2 lt Counter Bus BST ETI Timing vo DAQ STC interface Bus DAGPnP anc E aoU gta uo Analog Output RTS Bus i ee lt a 1 Analog Output 1 RTSI Bus Analog 8255 Bus Digital I O 8 Digital VO 1 Timing Control Interface Control i contro 1 Mtertace by Data 16 lt m Y Figure 3 5 AT Al 16XE 10 Block Diagram National Instruments Corporation 3 5 AT E Series User Manual Chapter 3 Hardware Overview Figure 3 6 shows a block diagram for the AT MIO 16XE 50 Voltage REF Calibration DACs 2 3 Mux Mode 16 Bit Wa Selection Sampling ADC Data Switches AD FIFO Transceivers Converter Calibration A Mux EEPROM Configuration Memory Al Control x j a IRQ gt od ro DMA Oa E i c a PFI Trigger Analog Input rs g E Trigger Timing Control interrupt Analog IEEPROM DMA Request Input G O Cholla pe a Control Control Interface 3 fo Counter 7 Bus Daa STE Pug oO Timing I O DAQ STC Interface Bus DAQ PnP and O eee ieee fe dS H Interface Play o iR 1 Analog Output RTSI Bus Analog 8255 Bus l Digital 1 0 8 D
73. O 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 5 digital I O connections 4 28 dither enabling 3 10 DMA channels configuring 2 3 PC AT 16 bit DMA channel assignment map table 2 6 documentation online library D 1 drivers instrument D 1 software D 1 dynamic characteristics analog input AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 4 AT MIO 16E 10 and AT MIO 16DE 10 A 14 AT MIO 16XE 10 and AT AI 16XE 10 A 23 A 24 AT MIO 16XE 50 A 32 analog output AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 7 AT MIO 16E 10 and AT MIO 16DE 10 A 16 AT MIO 16XE 10 A 25 AT MIO 16XE 50 A 34 E EEPROM storage of calibration constants 5 1 environmental noise avoiding 4 55 equipment optional 1 5 example code D 1 EXTREF signal analog output reference connections 4 27 National Instruments Corporation l 5 Index analog output reference selection 3 13 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 description table 4 5 EXTSTROBE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 6 timing connections 4 30 F field wiring considerations 4 55 floating signal sources description 4 17 differential connections 4 22 single ended conne
74. O2 DIO6 DIO3 DIO7 DGND 5V 5V SCANCLK EXTSTROBE FIO TRIG1 PFI1 TRIG2 PFI2 CONVERT PFI3 GPCTR1_SOURCE PFI4 GPCTR1_GATE GPCTR1_OUT PFI5 UPDATE PFI6 WFTRIG PFI7 STARTSCAN PFI8 GPCTRO_SOURCE PFI9 GPCTRO_GATE GPCTRO_OUT FREQ_OUT aa 1 51 2 52 3 53 4 54 5 55 6 56 7 57 8 58 9 59 10 60 11 61 12 62 13 63 14 64 15 65 16 66 17 67 18 68 19 69 20 70 21 71 22 72 23 73 24 74 25 75 26 76 27 77 28 78 29 79 30 80 31 81 32 82 33 83 34 84 35 85 36 86 37 87 38 88 39 89 40 90 41 91 42 92 43 93 44 94 45 95 46 96 47 97 48 98 49 99 50 100 eer ACH16 ACH24 ACH17 ACH25 ACH18 ACH26 ACH19 ACH27 ACH20 ACH28 ACH21 ACH29 ACH22 ACH30 ACH23 ACH31 ACH32 ACH40 ACH33 ACH41 ACH34 ACH42 ACH35 ACH43 AISENSE2 AIGND ACH36 ACH44 ACH37 ACH45 ACH38 ACH46 ACH39 ACH47 ACH48 ACH56 ACH49 ACH57 ACHS50 ACHS58 ACHS1 ACH59 ACH52 ACH60 ACH53 ACH61 ACH54 ACH62 ACHS55 ACH63 National Instruments Corporation Figure 4 2 1 0 Connector Pin Assignment for the AT MIO 64E 3 4 3 AT E Series User Manual Chapter 4 Connecting Signals AT E Series User Manual AIGND AIGND ACHO ACH8 ACH1 ACH9 ACH2 ACH10 ACH3 ACH
75. ONVERT appears when the onboard sample interval counter reaches zero If you select an external CONVERT the first external pulse after STARTSCAN generates a conversion The STARTSCAN pulses should be separated by at least one scan period A counter on the AT E Series device internally generates the STARTSCAN signal unless you select some external source This counter is started by the TRIG1 signal and is stopped either by software or by the sample counter Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence may be gated by either the hardware AIGATE signal or software command register gate National Instruments Corporation 4 37 AT E Series User Manual Chapter 4 Connecting Signals AT E Series User Manual CONVERT Signal Any PFI pin can externally input the CONVERT signal which is available as an output on the PFI2 CONVERT pin Refer to Figures 4 13 and 4 14 for the relationship of CONVERT to the DAQ sequence As an input the CONVERT signal is configured in the edge detection mode You can select any PFI pin as the source for CONVERT and configure the polarity selection for either rising or falling edge The selected edge of the CONVERT signal initiates an A D conversion As an output the CONVERT signal reflects the actual convert pulse that is connected to the ADC even if the conversions are
76. PFI6 WFTRIG DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vcc 0 4 PFI7 STARTSCAN DIO Vec 0 5 3 5at 5 at 0 4 1 5 50 KQ pu Vec 0 4 PFI8 GPCTRO_SOURCE DIO Vec 0 5 3 5at 5 at 0 4 1 5 50 KQ pu Vec 0 4 PFI9 GPCTRO_GATE DIO Vec 0 5 3 5at 5 at 0 4 1 5 50 KQ pu V c 0 4 GPCTRO_OUT DO 3 5at 5 at 0 4 1 5 50 KQ pu Vcc 0 4 FREQ_OUT DO 3 5 at 5 at 0 4 1 5 50 KQ pu Vec 0 4 AI Analog Input AO Analog Output 1 DIO lt 6 7 gt are also pulled down with a 50 KQ resistor DIO Digital Input Outpu DO Digital Output pu pull up The tolerance on the 50 kQ pull up and pull down resistors is very large Actual value may range between 17 KQ and 100 KQ National Instruments Corporation 4 11 AT E Series User Manual Chapter 4 Connecting Signals Table 4 5 1 0 Signal Summary for the AT MIO 16XE 10 and AT Al 16XE 10 Impedance Protection Rise Input Volts Source Sink Time Signal Name Drive Output On Off mA at V mA at V ns Bias ACH lt 0 15 gt AI 100 GQ in 25 15 l nA parallel with 100 pF AISENSE AI 100 GQ in 25 15 l nA parallel with 100 pF AIGND AO DACOOUT AO 0 1 Q Short circuit 5 at 10 5 at 10 5 to ground V us DACIOUT AO 0 1 Q Short circuit 5 at 10 5 at 10 5 to ground V us AOGND AO DGN
77. RCE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 National Instruments Corporation Index AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 14 description table 4 7 PFI9 GPCTRO_GATE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 14 description table 4 7 PFIs programmable function inputs 4 31 common questions about C 9 C 10 overview 4 30 signal routing 3 18 PGIA programmable gain instrumentation amplifier common mode signal rejection 4 26 differential connections floating signal sources 4 22 ground referenced signal sources 4 21 phone technical support D 1 physical specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 10 AT MIO 16E 10 and AT MIO 16DE 10 A 19 AT MIO 16XE 10 and AT AI 16XE 10 A 28 AT MIO 16XE 50 A 37 pin assignments See I O connectors Plug and Play systems configuring 2 2 to 2 3 polarity input polarity and range 3 7 output polarity selection 3 13 Port C signal assignments table 4 50 posttriggered data acquisition 4 32 power connections 4 29 AT E Series User Manual Index power requirement specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 10 AT MIO 16E 10 and AT MIO 16DE 10 A 19 AT MIO 16XE 10 and AT AI 16
78. S oren 255 kHz Settling time for full scale step Accuracy 0 00076 0 0015 0 0016 0 5 LSB 1 LSB 4 LSB 40 us max 20 us max 10 us max Accuracy values valid for source impedances lt 1 kQ Refer to the Multiple Channel Scanning Considerations section of Chapter 3 Hardware Overview for more information System noise LSB including quantization noise Range Bipolar Unipolar 2 to 20 V 0 6 0 8 1V 0 7 0 8 400 to 500 mV 1 1 1 1 200 mV 2 0 2 0 100 mV 3 8 National Instruments Corporation A 23 AT E Series User Manual Appendix A Specifications for AT MIO 16XE 10 and AT AI 16XE 10 Crosstalk DC to 100 kHz Adjacent channels 75 dB max All other channels ccccccceseeee 90 dB max Stability Offset temperature coefficient Pre Sain ninne eres et 5 uV C PoSt ain 2h set ese NA eae 120 pV C Gain temperature coefficient 7 ppm C Analog Output AT MIO 16XE 10 only Output Characteristics Number of channels eeceeceeeseeereeeee 2 voltage ReSOlution cccccccssssccceeesssseeeeeesssneeeees 16 bits 1 in 65 536 Max update rate oe eee eree 100 kS s Type ot DAC rriaren Double buffered PIFO buffer SiZecienurerennriieni 2 048 samples Data transfers cccceccccccesesesesereseeeees DMA interrupts programmed I O DMA modes gaviniae Single transfer demand transfer Transfer Characteristics Relative accura
79. Selection The AT E Series devices can increase bus efficiency by using an interrupt channel You can use an interrupt channel for event notification without the use of polling techniques AT E Series devices can use interrupt channels 3 4 5 7 10 11 12 and 15 These selections are all software configured and do not require you to manually change any settings on the device National Instruments Corporation 2 3 AT E Series User Manual Chapter 2 Installing and Configuring the Device AT E Series User Manual The following tables provide information concerning possible conflicts when configuring the AT E Series device Table 2 1 PC AT I O Address Map T O Address Range Hex Device 100 to 1EF 1F0 to 1F8 IBM PC AT Fixed Disk 200 to 20F PC and PC AT Game Controller reserved 210 to 213 PC DIO 24 default 218 to 21F 220 to 23F Previous generation of AT MIO devices default 240 to 25F AT DIO 32F default 260 to 27F Lab PC PC default 278 to 28F AT Parallel Printer Port 2 LPT2 279 Reserved for Plug and Play operation 280 to 29F WD EtherCard default 2A0 to 2BF 2E2 to 2F7 2F8 to 2FF PC AT Serial Port 2 COM2 300 to 30F 3Com EtherLink default 310 to 31F 320 to 32F ICM PC XT Fixed Disk Controller 330 to 35F 360 to 363 PC Network low address 364 to 367 Reserved 368 to 36B PC Network high address
80. The first level is the fastest easiest and least accurate whereas the last level is the slowest most difficult and most accurate Loading Calibration Constants The AT E Series device is factory calibrated before shipment at approximately 25 C to the levels indicated in Appendix A Specifications The associated calibration constants the values that were written to the CalDACs to achieve calibration in the factory are stored in the onboard nonvolatile memory EEPROM Because the CalDACs have no memory capability they do not retain calibration information when the device is unpowered Loading calibration constants refers to the process of loading the CalDACs with the values stored in the EEPROM NI DAQ determines when this is necessary and does it automatically If you are not using NI DAQ you must load these values yourself In the EEPROM there is a user modifiable calibration area in addition to the permanent factory calibration area This means that you can load the CalDACs with values either from the original factory calibration or from a calibration that you performed subsequently This method of calibration is not very accurate because it does not take into account the fact that the device measurement and output voltage errors can National Instruments Corporation 5 1 AT E Series User Manual Chapter 5 Calibrating the Device vary with time and temperature It is better to self calibrate when the device is installed in
81. Therefore it is susceptible to crosstalk from adjacent pins which can result in false triggering when the pin is left unconnected To avoid false triggering make sure this pin is connected to a low impedance signal source less than 10 kQ source impedance if you plan to enable this input using software Analog J Input PGIA ADC Channels Analog Mux Trigger DAQ STC PFIO TRIG1 Circuit Figure 3 8 Analog Trigger Block Diagram There are five analog triggering modes available as shown in Figures 3 9 through 3 13 You can set lowValue and highValue independently in software In below low level analog triggering mode the trigger is generated when the signal value is less than lowValue HighValue is unused National Instruments Corporation 3 15 AT E Series User Manual Chapter 3 Hardware Overview lowValue Trigger l aki Wes Figure 3 9 Below Low Level Analog Triggering Mode In above high level analog triggering mode the trigger is generated when the signal value is greater than high Value LowValue is unused highValue Trigger Figure 3 10 Above High Level Analog Triggering Mode In inside region analog triggering mode the trigger is generated when the signal value is between the lowValue and the highValue highValue lowValue Trigger y l l F
82. UT signal transitions shown in Figure 4 37 are referenced to the rising edge of the SOURCE signal This timing diagram assumes that the counters are programmed to count rising edges The same timing diagram but with the source signal inverted and referenced to the falling edge of the source signal would apply when the counter is programmed to count falling edges The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated signals on the AT E Series device Figure 4 37 shows the GATE signal referenced to the rising edge of a source signal The gate must be valid either high or low for at least 10 ns before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown by tesu and ty in Figure 4 37 The gate signal is not required to be held after the active edge of the source signal AT E Series User Manual Chapter 4 Connecting Signals If an internal timebase clock is used the gate signal cannot be synchronized with the clock In this case gates applied close to a source edge take effect either on that source edge or on the next one This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources The OUT output timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated clock signals on the AT E Series devices Figure 4 37 shows the OUT
83. Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI1 TRIG2 DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI2 CONVERT DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI3 GPCTR1_SOURCE DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI4 GPCTR1_GATE DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 GPCTR1_OUT DO 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI5 UPDATE DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI6 WFTRIG DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI7 STARTSCAN DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI8 GPCTRO_SOURCE DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI9 GPCTRO_GATE DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 GPCTRO_OUT DO 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 AT E Series User Manual 4 14 ni com Chapter 4 Connecting Signals Table 4 6 1 0 Signal Summary for the AT MIO 16XE 50 Continued Impedance Protection Rise Input Volts Source Sink Time Signal Name Drive Output On Off mA at V mA at V ns Bias FREQ_OUT DO 3 5 at 5 at 0 4 1 5 50 KQ pu Vec 0 4 1 DIO lt 6 7 gt are also pulled down with a 50 KQ resistor AI Analog Input DIO Digital Input Output pu pull up AO Analog Output DO Digital Output The tolerance on the 50 KQ pull up and pull down resistors is very large Actual value may range between 17 KQ and 100 KQ
84. XE 10 A 28 pretriggered data acquisition 4 32 professional services D 1 programmable function inputs PFIs See PFIs programmable function inputs programmable gain instrumentation amplifier See PGIA programmable gain instrumentation amplifier programming examples D 1 Q questions about AT E series boards analog input and analog output C 3 general information C 1 installation and configuration C 2 timing and digital I O C 7 R RD signal table 4 51 reference selection analog output 3 13 referenced single ended input RSE See RSE referenced single ended input register level programming 1 4 reglitch selection 3 14 related documentation xiii RSE referenced single ended input description table 3 7 single ended connections for floating signal sources 4 25 RTSI clocks 3 20 RTSI triggers overview 3 20 specifications AT E Series User Manual AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 10 AT MIO 16E 10 and AT MIO 16DE 10 A 18 AT MIO 16XE 10 and AT AI 16XE 10 A 27 AT MIO 16XE 50 A 36 S SCANCLK signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 6 timing connections 4 40 settling time 3 11 C 1 signal connections analog input 4 15 analog output 4 27 digital I O 4 28 field wiring considerations 4 55 I O connector
85. abilities Caution Exceeding the maximum input voltage ratings which are listed in Tables 4 3 through 4 6 can damage the AT E Series device and the PC NI is not liable for any damage resulting from such signal connections AT E Series User Manual 4 28 ni com Chapter 4 Connecting Signals Figure 4 11 shows signal connections for three typical DIO applications 5V A LED V7 DIO lt 4 7 gt D gt gt TTL Signal o DIO lt 0 3 gt 5V wp r Switch 1 O Connector Figure 4 11 DIO Connections Figure 4 11 shows DIO lt 0 3 gt configured for digital input and DIO lt 4 7 gt configured for digital output Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch shown in the figure Digital output applications include sending TTL signals and driving external devices such as the LED shown in the figure Power Connections Two pins on the I O connector supply 5 V from the PC power supply using a self resetting fuse The fuse resets automatically within a few seconds after the overcurrent condition is removed These pins are referenced to DGND and can be used to power external digital circuitry The combined total power rating for both pins should be between 4 65 VDC to 5 25 VDC at 1 A National Instruments Corporation 4 29 AT E Series User Manual Chapter
86. acquisitions as shown in Figure 3 7d eliminates both the added noise and the effects of quantization Dither has the effect of forcing quantization noise to become a zero mean random variable rather than a deterministic function of the input signal 3 10 ni com Chapter 3 Hardware Overview LSBs LSBs 6 0 6 0 4 0 4 0 2 0 2 0 0 0 E 4 0 0 2 0 4 E 2 0 ee 4 0 4 0 6 0 i 6 0 0 100 200 300 400 500 0 100 200 300 400 500 a Dither disabled no averaging b Dither disabled average of 50 acquisitions LSBs LSBs 6 0 6 0 4 0 4 0 20 2 0 wa 0 0 0 0 IL 2 0 2 0 r 4 0 4 0 6 0 4 6 0 0 100 200 300 400 500 0 100 200 300 400 500 c Dither enabled no averaging d Dither enabled average of 50 acquisitions Figure 3 7 Dither You cannot disable dither on the AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 This is because the resolution of the ADC is so fine that the ADC and the PGIA inherently produce almost 0 5 LSB ms of noise This is equivalent to having a dither circuit that is always enabled Multiple Channel Scanning Considerations All of the AT E Series devices can scan multiple channels at the same maximum rate as their single channel rate however you should pay careful attention to the settling times for each of the
87. ai ea oeoa EEE E eea aae i eE iE Power Connections esinen a ian E A Ne ta a Timms Connections nie R EE A Geeta E Programmable Function Input Connections ssesssessssesserereereeeersrrsrrsrsresresese DAQ Timing Connections seoor ran eeri a i a TRIGI Signal iee nna ee dase ee TRIGZ Signal norteia iA AEE EA REESE START SCAN Oa e e ie aia E E i CONVERT Signal r pi er REER E EE AIGATE Sigala oton a n E T ER AT E Series User Manual viii ni com Contents SISOURCE Signali oietan aeina a sae tees vee AES 4 39 SCANGLK Sistial seirena ria ae eaaa aariaa ina 4 40 EXTSTROBE Sigtial sicccisccceteci nid ache iii heen nt 4 4 Waveform Generation Timing Connections 0 0 0 eee eeeeseeeeeeeceeenseesees 4 41 WETRIG Sisiial issc iseinean nieni ii e aeea e R iad 4 41 UPDATE Signal a ea iia nnn iundinieiias 4 42 UISOURCE Signal lesi ninien eea a EO i 4 44 General Purpose Timing Signal Connections esseeesesreseersersrrsrerrsrsrrsreseres 4 44 GPCTRO SOURCE Sign l cisini iirinn irana 4 44 GPCTRO GATE Signalin conia aa Easa R TTE 4 45 GPCTRO OUT Signal cioinn i n le e 4 46 GPCTRO UP DOWN Sigial isiicsiiacion nani a er ness 4 46 GPCTR1_SOURCE Sig al eisite n a ae oas 4 47 GPCTRI GATE Signal ia A e eis aaa Tn 4 47 GPCTRI OUT Signal swit inina o E e E E ne 4 48 GPCTR1_UP_DOWN Signali secs cceecessceceeceeeeeceeenetseeneeneeaeeaees 4 48 FREO OUT Siftials 204 iss teint hie aa e E 4 50 Timing Specifications for Digital I O Ports A B an
88. al and timing I O devices for the PC AT series computers Supported functions include analog input AI analog output AO digital I O DIO and timing I O TIO lt gt 3 A The following conventions appear in this manual Angle brackets that contain numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example DIO lt 3 0 gt The symbol indicates that the following text applies only to a specific product a specific operating system or a specific software version This icon denotes a note which alerts you to important information This icon denotes a caution which advises you of precautions to take to avoid injury data loss or a system crash When this symbol is marked on the device see the Safety Information section of Chapter 1 Introduction for precautions to take National Instruments Corporation xi AT E Series User Manual About This Manual bold italic NI DAQ PC SCXI Bold text denotes items that you must select or click in the software such as menu items and dialog box options Bold text also denotes parameter names Italic text denotes variables emphasis a cross reference or an introduction to a key concept This font also denotes text that is a placeholder for a word or value that you must supply NI DAQ refers to the NI DAQ software for PC compatibles unless otherwise noted PC refers to the PC AT series computers SCXI st
89. al Timing ty 300to350ns_ Figure 4 29 UPDATE Output Signal Timing The DACs are updated within 100 ns of the leading edge Separate the UPDATE pulses with enough time that new data can be written to the DAC latches The AT E Series device UI counter normally generates the UPDATE signal unless you select some external source The UI counter is started by the WFTRIG signal and can be stopped by software or the internal Buffer Counter D A conversions generated by either an internal or external UPDATE signal do not occur when gated by the software command register gate National Instruments Corporation 4 43 AT E Series User Manual Chapter 4 Connecting Signals UISOURCE Signal Any PFI pin can externally input the UISOURCE signal which is not available as an output on the I O connector The UI counter uses the UISOURCE signal as a clock to time the generation of the UPDATE signal You must configure the PFI pin you select as the source for the UISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low Figure 4 30 shows the timing requirements for the UISOURCE signal tp 50 ns minimum ty 23 ns minimum Figure 4 30 UISOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 1
90. an output on the I O connector The AIGATE signal can mask off scans in a DAQ sequence You can configure the PFI pin you select as the source for the AIGATE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low In the level detection mode if AIGATE is active the STARTSCAN signal is masked off and no scans can occur The AIGATE signal can neither stop a scan in progress nor continue a previously gated off scan in other words once a scan has started AIGATE does not gate off conversions until the beginning of the next scan and conversely if conversions are being gated off AIGATE does not gate them back on until the beginning of the next scan SISOURCE Signal Any PFI pin can externally input the SISOURCE signal which is not available as an output on the I O connector The onboard scan interval counter uses the SISOURCE signal as a clock to time the generation of the STARTSCAN signal You must configure the PFI pin you select as the source for the SISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation National Instruments Corporation 4 39 AT E Series User Manual Chapter 4 Connecting Signals Either the 20 MHz or 100 kHz internal timebase generat
91. and timing I O devices for the PC AT and compatible computers This family of devices features 12 bit and 16 bit ADCs with 16 and 64 analog inputs 12 bit and 16 bit DACs with voltage outputs eight and 32 lines of TTL compatible DIO and two 24 bit counter timers for TIO Because the AT E Series devices have no DIP switches jumpers or potentiometers they are easily configured and calibrated using software The AT E Series devices are the first completely switchless and jumperless data acquisition DAQ devices This feature is made possible by the National Instruments DAQ PnP bus interface chip that connects the device to the AT I O bus The DAQ PnP implements the Plug and Play ISA Specification so that the DMA interrupts and base I O addresses are all software configurable This allows you to easily change the AT E Series device configuration without having to remove the device from the computer The DAQ STC makes possible such applications as buffered pulse generation equivalent time sampling and seamlessly changing the sampling rate The AT E Series devices use the National Instruments DAQ STC system timing controller for time related functions The DAQ STC consists of three timing groups that control AI AO and general purpose counter timer functions These groups include a total of seven 24 bit and three 16 bit counters and a maximum timing resolution of 50 ns A common problem with DAQ devices is that you cannot easily synchroniz
92. ands for Signal Conditioning eXtensions for Instrumentation and is a National Instruments product line designed to perform front end signal conditioning for NI plug in DAQ devices National Instruments Documentation AT E Series User Manual The AT MIO SAI E Series User Manual is one piece of the documentation set for the DAQ system You could have any of several types of manuals depending on the hardware and software in the system Use the manuals you have as follows e Getting Started with SCXI TIf you are using SCXI this is the first manual you should read It gives an overview of the SCXI system and contains the most commonly needed information for the modules chassis and software e The SCXI hardware user manuals If you are using SCXI read these manuals next for detailed information about signal connections and module configuration They also explain in greater detail how the module works and contain application hints e SCXI Chassis Manual If you are using SCXI read this manual for maintenance information on the chassis and installation instructions e The DAQ hardware user manuals These manuals have detailed information about the DAQ hardware that plugs into or is connected to the computer Use these manuals for hardware installation and configuration instructions specification information about the DAQ hardware and application hints e Software documentation Examples of software documentation you may have are
93. ar or more you may wish to externally calibrate the device An external calibration refers to calibrating the device with a known external reference rather than relying on the onboard reference Redetermining the value of the onboard reference is part of this process and the results can be saved in the EEPROM so you should not have to perform an external calibration very often You can externally calibrate the device by calling the NI DAQ calibration function To externally calibrate the device be sure to use a very accurate external reference The reference should be several times more accurate than the device itself For example to calibrate a 12 bit device the external reference should be at least 0 005 50 ppm accurate To calibrate 5 2 ni com Chapter 5 Calibrating the Device a 16 bit device the external reference should be at least 0 001 10 ppm accurate For a detailed calibration procedure for the AT E Series device refer to the E Series Calibration Procedure by clicking Manual Calibration Procedures at ni com calibration Other Considerations The CalDACs adjust the gain error of each AO channel by adjusting the value of the reference voltage supplied to that channel This calibration mechanism is designed to work only with the internal 10 V reference Thus in general it is not possible to calibrate the AO gain error when using an external reference In this case it is advisable to account for the nominal gain
94. are FCC Class A The FCC rules have restrictions regarding the locations where FCC Class A products can be operated FCC Class B products display either a FCC ID code starting with the letters EXN Trade Name Model Number or the FCC Class B compliance mark that appears as shown here on the right FE Tested to Comply with FCC Standards Consult the FCC Web site at http www fcc gov for more information FCC DOC Warnings This equipment generates and uses radio frequency energy and if not installed and used in strict accordance with the instructions in this manual and the CE Mark Declaration of Conformity may cause interference to radio and television reception Classification requirements are the same for the Federal Communications Commission FCC and the Canadian Department of Communications DOC Changes or modifications not expressly approved by National Instruments could void the user s authority to operate the equipment under the FCC Rules Class A Federal Communications Commission This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interfere
95. as a general purpose counter timer If you are using the NI DAQ language interface and a C compiler under DOS a new subdirectory called GPCTR which lies beneath the examples directory contains 16 examples of the most common uses of the DAQ STC Do the counter timer applications that I wrote previously work with the DAQ STC If you are using NI DAQ with LabVIEW some of your applications drawn using the CTR VIs do still run However there are many differences in the counters between the AT E Series and other devices the counter numbers are different timebase selections are different the DAQ STC counters are 24 bit counters unlike the 16 bit counters on devices without the DAQ STC If you are using NI DAQ or Measurement Studio the answer is no The counter time applications that you wrote previously do not work with the DAQ STC You must use the GPCTR functions ICTR and CTR functions do not work with the DAQ STC The GPCTR functions have the same capabilities as the ICTR and CTR functions plus more but you must rewrite the application with the GPCTR function calls I m using one of the general purpose counter timers on my AT E Series device but I do not see the counter timer output on the I O connector What am I doing wrong If you are using NI DAQ or Measurement Studio you must configure the output line to output the signal to the I O connector Use the Select Signal call in NI DAQ to configure the output line By default
96. ational Instruments Corporation All rights reserved Important Information Warranty The AT E Series devices are warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this document is accurate The document has been carefully reviewed for technical accuracy In the event
97. ational Instruments Corporation A 15 AT E Series User Manual Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 Digital 1 0 AT E Series User Manual Output impedance eee 0 1 Q max Current Ariye is teccesce segerns i 5 mA max Protect Oty issecscccscteve nesstweroetesstvecuveh ieee Short circuit to ground Power on State cccceesseesesteceesteeeeeeeees 0 V 200 mV External reference input Ranges Sent iene ee ats 11 V Overvoltage protection 0 0 0 0 35 V powered on 25 V powered off Input impedance 0 0 eee eee 10 kQ Bandwidth 3 dB 300 kHz Dynamic Characteristics Settling time for full scale step 10 us to 0 5 LSB accuracy Slew Tateins Acute nisiel Sede e 10 V us NOSE R E eatin 200 uV ms DC to 1 MHz Glitch energy at midscale transition Magnitidess nenene 100 mV D tatioNsspsenisieniieniaii 3 us Stability Offset temperature coefficient 50 uV C Gain temperature coefficient Internal reference eee 25 ppm C External reference eee 25 ppm C Number of channels AT MIO 16E 10 eee 8 input output AT MIO 16DE 10 0 ee 32 input output Compatibility scscsisisssirisisui eii TTL CMOS A 16 ni com Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current Vin 0 V 320 uA Input high
98. blish a local or onboard reference for the signal Otherwise the measured input signal varies as the source floats out of the common mode input range Ground Referenced Signal Sources A ground referenced signal source is one that is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the AT E Series device assuming that the PC is plugged into the same power system Nonisolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between and 100 mV but can be much higher if power distribution circuits are not properly connected If a grounded signal source is improperly measured this difference may appear as an error in the measurement The connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal National Instruments Corporation 4 17 AT E Series User Manual Chapter 4 Connecting Signals Input Configurations You can configure the AT E Series device for one of three input modes NRSE RSE or DIFF The following sections discuss the use of single ended and differential measurements and considerations for measuring both floating and ground referenced signal sources Figure 4 5 summarizes the recommended input conf
99. by the DACs in the AO circuitry and can be either the 10 Vonboard reference or an externally supplied reference between 10 and 10 V You do not need to configure both channels for the same range National Instruments Corporation 3 13 AT E Series User Manual Chapter 3 Hardware Overview Selecting a bipolar range for a particular DAC means that any data written to that DAC is interpreted as two s complement format In two s complement mode data values written to the AO channel can be either positive or negative If you select unipolar range data is interpreted in straight binary format In straight binary mode data values written to the AO channel range must be positive AT MIO 16XE 10 You can configure each AO channel for either unipolar or bipolar output A unipolar configuration has a range of 0 to 10 V at the analog output A bipolar configuration has a range of 10 to 10 V at the analog output You do not need to configure both channels for the same range Analog Output Reglitch Selection Analog Trigger AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 only In normal operation a DAC output glitches whenever it is updated with a new value The glitch energy differs from code to code and appears as distortion in the frequency spectrum Each analog output of the AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 contains a reglitch circuit that generates uniform glitch energy at every code rather than large glitches at
100. cates the initiation of the waveform generation PFI7 STARTSCAN DGND Input PFI7 Start of Scan As an input this is one of the PFIs Output As an output this is the STARTSCAN signal This pin pulses once at the start of each analog input scan in the interval scan A low to high transition indicates the start of the scan PFI8 GPCTRO_SOURCE DGND Input PFI8 Counter 0 Source As an input this is one of the PFIs Output As an output this is the GPCTRO_SOURCE signal This signal reflects the actual source connected to the general purpose counter 0 PFI9 GPCTRO_GATE DGND Input PFI9 Counter 0 Gate As an input this is one of the PFIs Output As an output this is the GPCTRO_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 0 National Instruments Corporation 4 7 AT E Series User Manual Chapter 4 Connecting Signals Table 4 2 1 0 Signal Summary for the AT E Series Continued Signal Name Reference Direction Description GPCTRO_OUT DGND Output Counter 0 Output This output is from the general purpose counter 0 output FREQ_OUT DGND Output Frequency Output This output is from the frequency generator output Table 4 3 1 0 Signal Summary for the AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Impedance Protection Rise Input Volts Source Sin
101. consuming and inefficient and is not recommended for most users Even if you are an experienced register level programmer consider using NI DAQ LabVIEW or LabWindows CVI to program the National Instruments DAQ hardware Using the NI DAQ LabVIEW or LabWindows CVI software is as easy and as flexible as register level programming and can save weeks of development time For more information refer to the AT E Series Register Level Programmer Manual AT E Series User Manual 1 4 ni com Chapter 1 Introduction Optional Equipment NI offers a variety of products to use with the AT E Series device including cables connector blocks and other accessories as follows Cables and cable assemblies shielded and ribbon Connector blocks shielded and unshielded 50 68 and 100 pin screw terminals RTSI bus cables SCXI modules and accessories for isolating amplifying exciting and multiplexing signals for relays and analog output With SCXI you can condition and acquire up to 3 072 channels Low channel count signal conditioning modules devices and accessories including conditioning for strain gauges and RTDs simultaneous sample and hold and relays For more specific information about these products refer to ni com catalog or call the office nearest you Custom Cabling National Instruments offers cables and accessories for you to prototype your application or to use if you frequently change device interconnections If
102. ct the appropriate product family followed by the product and a link to the DoC appears in Adobe Acrobat format Click the Acrobat icon to download or read the DoC AT E Series User Manual A 20 ni com Appendix A Specifications for AT MIO 16XE 10 and AT AI 16XE 10 AT MIO 16XE 10 and AT Al 16XE 10 Analog Input Input Characteristics Number of channels 0 0 0 0 eee eee 16 single ended or 8 differential software selectable Type of ADC nainis tegen as Successive approximation Resolution cccccsessecccesesseeceessssseeees 16 bits 1 in 65 536 Maximum sampling rate 100 kS s guaranteed Input signal ranges Input Range Range Software Selectable Bipolar Unipolar 20 V 10 V 10 V 5 V Oto 10 V 5V Oto5 V 4V 2 V 2V 1 V 0to2 V 1V 500 mV Otol V 500 mV 0 to 500 mV 400 mV 200 mV 200 mV 100 mV 0 to 200 mV 100 mV 0 to 100 mV Input coupling ee eee eeeeeeeeeereeeees DC Maximum working voltage Each input should remain within 11 V of ground Overvoltage protection eeeeeseeeees 25 V powered on 15 V powered off Inputs protected eee ACH lt 0 15 gt AISENSE National Instruments Corporation A 21 AT E Series User Manual Appendix A Specifications for AT MIO 16XE 10 and AT AI 16XE 10 AT E Series User Manual FIFO buffer size 512 samples Data transfers ccccccccccesseceeesssceeeeees DMA interrupts programme
103. ctions RSE configuration 4 25 FREQ_OUT signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 15 description table 4 8 waveform generation timing connections 4 50 frequently asked questions D 1 See also questions about AT E series boards fuse 4 6 AT E Series User Manual Index G general purpose timing signal connections FREQ _ OUT signal 4 50 GPCTRO_GATE signal 4 45 GPCTRO_OUT signal 4 46 GPCTRO_SOURCE signal 4 44 GPCTRO_UP_DOWN signal 4 46 GPCTR1_GATE signal 4 47 GPCTR1_OUT signal 4 48 GPCTR1_SOURCE signal 4 47 GPCTR1_UP_DOWN signal 4 48 GPCTRO_GATE signal 4 45 GPCTRO_OUT signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 14 description table 4 8 waveform generation timing connections 4 46 GPCTRO_SOURCE signal 4 44 GPCTRO_UP_DOWN signal 4 46 GPCTR1_GATE signal 4 47 GPCTR1_OUT signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 7 waveform generation timing connections 4 48 GPCTR1_SOURCE signal 4 47 GPCTR1_UP_DOWN signal 4 48 AT E Series User Manual l 6 ground r
104. current Vin 5 V 10 uA Output low voltage Ip 24 mA 0 4 V Output high voltage lop 13 mA 4 35 V PA lt 0 7 gt PB lt 0 7 gt PC lt 0 7 gt AT MIO 16DE 10 only Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current Vin 0 V 60 uA Input high current Vin 5 V 10 uA Output low voltage Io 2 5 mA 0 4 V Output high voltage Iop 2 5 mA 3 9 V Handshaking Modes AT MIO 16DE 10 only 0 2 wire Direction st iis esis hh los ish de aae Input or output Power on Stat ccceescceeeseeeeeseessteeees Input High Z Data transfers AT MIO 16E 10 eee Programmed I O AT MIO 16DE 10 00 ee Interrupts programmed I O Max transfer rate 1 word 8 bits 50 kwords s system dependent Constant sustainable rate 1 to 10 kwords s typical National Instruments Corporation A 17 AT E Series User Manual Appendix A Timing 1 0 Triggers AT E Series User Manual Number of channels Resolution Counter timers Frequency scalers Compatibility 0 Base clocks available Specifications for AT MIO 16E 10 and AT MIO 16DE 10 2 up down counter timers 1 frequency scaler 24 bits 4 bits TTL CMOS Counter timers cccccccssssscsssseeeeee 20 MHz 100 kHz Frequency scaler eee 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency
105. cy INL 0 0 0 0 5 LSB typ 1 LSB max DN biin E EES 1 LSB max Mon tonicity soiirci 16 bits guaranteed Offset error After calibration 305 uV max Before calibration ccccccccceceeeee 20 mV max AT E Series User Manual A 24 ni com Appendix A Specifications for AT MIO 16XE 10 and AT AI 16XE 10 Gain error relative to internal reference After calibration eee 30 5 ppm max Before calibration eee 2 000 ppm max Voltage Output Range ccscicvsiontenssinct aden a naa 10 V 0to 10 V software selectable Output coupling eeeeeeeeeeeee DC Output impedance eee eee 0 1 Q Current drive aeann e aad 5 mA Protectio inaasa Short circuit to ground Power on state eeeeesseeeeseeeeseeesseeees 0 V 20 mV Dynamic Characteristics Settling time for full scale step 10 us to 1 LSB accuracy Slew Tate epe a sin REE 5 V us NOLE saisan aS 60 UV ms DC to 1 MHz Stability Offset temperature coefficient 50 uV C Gain temperature coefficient 0 0 7 5 ppm C Digital 1 0 Number of channels 0 sees 8 input output Compatibility 0 0 eeeeeeeeeeeees TTL CMOS Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V National Instruments Corporation A 25 AT E Series User Manual Appendix A Specifications for AT MIO 16XE 10 and AT AI 16XE 10 Timing 1 0 AT E Series User Manual
106. d C oo eee 4 50 Mode 1 Input Timing nursinin naina s 4 52 Mode 1 Output Timing noinine ii aeieea 4 53 Mode 2 Bidirectional Timing eee eeeeeeceeeeeeeeeeeeeeeeaees 4 54 Field Wiring Considerations ec ceeeseesceceeseceseeeesseeseeeceaeeseeeaeceeeeaesneeeaesseensessees 4 55 Chapter 5 Calibrating the Device Loading Calibration Constants 2 00 0 cc eeeeeeseeseceeceseeeeesesseeesecseesaeeaecnseeaeeeeeaesneeeaeenaes 5 1 Self Calibration sesioni aa A e a E ar E Sania aed 5 2 External Calibration 248 s itn o E ne aie nin eae eee 5 2 Other Considerations 3 2 0 2 c scet aa Sil nah tees AA dented eden 5 3 Appendix A Specifications Appendix B Optional Cable Connector Descriptions Appendix C Common Questions National Instruments Corporation ix AT E Series User Manual Contents Appendix D Technical Support and Professional Services Glossary Index AT E Series User Manual X ni com About This Manual Conventions This manual describes the electrical and mechanical aspects of each device in the AT E Series product line and contains information concerning their operation and programming Unless otherwise noted text applies to all devices in the AT E Series The AT E Series includes the following devices e AT MIO 16E 1 e AT MIO 16E 2 e AT MIO 64E 3 e AT MIO 16E 10 e AT MIO 16DE 10 e AT MIO 16XE 10 e AT AI 16XE 10 e AT MIO 16XE 50 The AT E Series devices are high performance multifunction analog digit
107. d I O DMA modes 20 0 eceeeeeeeeeeeeeeeeenees Single transfer demand transfer Configuration memory Size 512 words Transfer Characteristics Relative accuracy 0 75 LSB typ 1 LSB max DND ernn a e E RAN 0 5 LSB typ 1 LSB max No missing codes eseeseeeeeeeeseeeeeee 16 bits guaranteed Offset error Pregain error after calibration 3 uV max Pregain error before calibration 2 2 mV max Postgain error after calibration 76 uV max Postgain error before calibration 102 mV max Gain error relative to calibration reference After calibration gain 1 30 5 ppm of reading max Before calibration 0 0 0 eee 2 150 ppm of reading max With gain error adjusted to 0 at gain 1 Gan A Ninnin nioena 200 ppm of reading Amplifier Characteristics Input impedance Normal powered on eee 100 GQ in parallel with 100 pF Powered Off stania anai renani 820 Q min OVE Oa insni nonan 820 Q min Input bias current eseeeeeeeeeeeeeeeeeeeeeee eee nA Input offset current 0 0 eee eeeeeeeseeeeeeeee 2 nA A 22 ni com Appendix A Specifications for AT MIO 16XE 10 and AT AI 16XE 10 CMRR DC to 60 Hz Range CMRR Bipolar CMRR Unipolar 20 V 92 dB 10 V 97 dB 92 dB 5V 97 dB 4V 101 dB 2V 104 dB 101 dB 1V 105 dB 104 dB 100 mV to 500 mV 105 dB 105 dB Dynamic Characteristics Bandwidth All gan
108. e Reference Direction Description AIGND Analog Input Ground These pins are the reference point for single ended measurements and the bias current return point for differential measurements All three ground references AIGND AOGND and DGND are connected together on the AT E Series device ACH lt 0 15 gt AIGND Input Analog Input Channels 0 through 15 Each channel pair ACH lt i i 8 gt i 0 7 can be configured as either one differential input or two single ended inputs ACH lt 16 63 gt AIGND Input Analog Input Channels 16 through 63 AT MIO 64E 3 only Each channel pair ACH lt i i 8 gt i 16 23 32 39 48 55 can be configured as either one differential input or two single ended inputs AISENSE AIGND Input Analog Input Sense This pin serves as the reference node for any of channels ACH lt 0 15 gt in NRSE configuration AISENSE2 AIGND Input Analog Input Sense AT MIO 64E 3 only This pin serves as the reference node for any of channels ACH lt 16 63 gt in NRSE configuration DACOOUT AOGND Output Analog Channel 0 Output This pin supplies the voltage output of analog output channel 0 This pin is not available on the AT AI 16XE 10 DAC1OUT AOGND Output Analog Channel 1 Output This pin supplies the voltage output of analog output channel 1 This pin is not available on the AT AI 16XE 10 EXTREF AOGND Input External Reference This is the external reference inpu
109. e for full scale step 3 us to 0 5 LSB accuracy Slew rates sii hat siniiaie miei 20 V us NOISE ninietan cus nous Geacitoniein E 200 UVims DC to 1 MHz Glitch energy at midscale transition Magnitude Reglitching disabled 200 mV Reglitching enabled 30 mV Duration eisisto iii 1 5 us Stability Offset temperature coefficient 50 uV C Gain temperature coefficient Internal reference 0 0 eee 25 ppm C External reference 0 eee 25 ppm C National Instruments Corporation A 7 AT E Series User Manual Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Digital 1 0 Number of channels cccceceseseeeees 8 input output Compatibility 000 eeceeeeeeeeeeeeeeees TTL CMOS Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current Vin 0 V 320 uA Input high current Vin 5 V 10 pA Output low voltage Io 24 mA 0 4 V Output high voltage lop 13 mA 4 35 V Power on state cccecessceeeseeeeseeeeeteeeees Data transfers cccccessceeesceeeseeeeeneeeees Max transfer rate 1 word 8 bits Constant sustainable rate Timing 1 0 Number of channels cccc0cceesseeeees Resolution Counter timers ccccccccsssscseseeeeees Frequency scaler cesceeseeeseeee C
110. e several measurement functions to a common trigger or timing event The AT E Series devices have the Real Time System Integration RTSI bus to solve this problem The RTSI bus consists of the RTSI bus National Instruments Corporation 1 1 AT E Series User Manual Chapter 1 Introduction interface and a ribbon cable to route timing and trigger signals between several functions on as many as five DAQ devices in the PC The AT E Series devices can interface to an SCXI system so that you can acquire over 3 000 analog signals from thermocouples RTDs strain gauges voltage sources and current sources You can also acquire or generate digital signals for communication and control SCXI is the instrumentation front end for plug in DAQ devices Detailed specifications of the AT E Series devices are in Appendix A Specifications What You Need to Get Started AT E Series User Manual To set up and use the AT E Series device you need the following One of the following devices AT MIO 16E 1 NI 6070E for ISA AT MIO 16E 2 NI 6060E for ISA AT MIO 64E 3 NI 6061E for ISA AT MIO 16E 10 NI 6020E for ISA AT MIO 16DE 10 NI 6021E for ISA AT MIO 16XE 10 NI 6030E for ISA AT AI 16XE 10 NI 6032E for ISA AT MIO 16XE 50 NI 6011E for ISA Q ATE Series User Manual Q One of the following software packages and documentation LabVIEW for Windows Measurement Studio NI DAQ for PC Co
111. each high impedance source before connecting up to the DAQ device or decrease the rate at which each channel is sampled Another common cause of channel crosstalk is due to sampling among multiple channels at various gains In this situation the settling times may increase For more information on charge injection and sampling channels at different gains refer to Chapter 3 Hardware Overview How are the AI channels of the AT MIO 64E 3 addressed when they are used in differential mode The 32 differential channel pairs are addressed as shown in the following table Differential Channel Name T O Terminals lt 0 7 gt ACH lt 0 8 7 15 gt lt 16 23 gt ACHK lt 16 24 23 31 gt lt 32 39 gt ACH lt 32 40 39 47 gt lt 44 58 gt ACH lt 48 56 55 63 gt How can I use STARTSCAN and CONVERT on my device to sample my AI channel s An E series device employs both the STARTSCAN and CONVERT signals to perform interval sampling The STARTSCAN signal of the DAQ STC controls the scan interval 1 scan interval scan rate shown in Figure C 2 The CONVERT signal controls the interchannel delay interchannel delay sampling rate This method allows multiple channels to be sampled relatively quickly in relationship to the overall scan rate providing a pseudo simultaneous effect with a fixed delay between channels AT E Series User Manual C 6 ni com Appendix C Common Questions Channel 0 Channel
112. eceseeesneceeeeseeceseeeeeecsareeseeeeaeeaes Device and RTSP GIOCKS wis ccsstts cents cates tas calunts censnutes webences iiaiai RESI Trig Bers case tes i eescthessasticeccsssheahag cate A a A a a A Chapter 4 Connecting Signals W O COnMC COR sn anae a as avd vs Rast sitha en A E eis aveden yeaa eed T O Connector Signal Descriptions 0 cies eeeeeeceseeseeeseeeeeseeaeeeeeeaeenees Analog Input Signal Connections cece eeeeceseceeceseeeeeeseceeeeaeeseeeaeeseeeaeeseseeeeaeenaes Lypes or Signal Sources a ale Wanita earn ee Raed Bloating Signal SourceS ionin aa E T este E Ground Referenced Signal Sources ssessesesesrseesesesrrsrrersereresreresreresresrsresre Inp tConfis ration Setna osna a e a a e N i ep a Ra Differential Connection Considerations DIFF Input Configuration Differential Connections for Ground Referenced Signal Sources Differential Connections for Nonreferenced or Floating Signal Sources rroia Single Ended Connection Considerations 00 0 0 ce eeeeeeceesseeeeeeeeetseeeseesees Single Ended Connections for Floating Signal Sources RSE Configuration ossia i eiieeii aas Single Ended Connections for Grounded Signal Sources NRSE Configuration eeneioe aee on a a E s Common Mode Signal Rejection Considerations seesseseseerereesrererrsreresreee Analog Output Signal Connections 0 cece ee eeeeseceeceseeseeeseeseceseeaeeseeeaecneesaeeseeeaeesees Digital I O Signal Connections ieee eee e aee
113. eed the UPDATE signal as an output on the I O connector software can turn on the output driver for the PFI5 UPDATE pin To use the PFI pins as outputs you must use the Route Signal VI to individually enable each of the PFI pins to output a specific timing signal Device and RTSI Clocks RTS Triggers AT E Series User Manual Many functions performed by the AT E Series devices require a frequency timebase to generate the necessary timing signals for controlling A D conversions DAC updates or general purpose signals at the I O connector An AT E Series device can use either its internal 20 MHz timebase or a timebase received over the RTSI bus In addition if you configure the device to use the internal timebase you can also program the device to drive its internal timebase over the RTSI bus to another device that is programmed to receive this timebase signal This clock source whether local or from the RTSI bus is used directly by the device as the primary frequency source The default configuration at startup is to use the internal timebase without driving the RTSI bus timebase signal You select this timebase through software The seven RTSI trigger lines on the RTSI bus provide a very flexible interconnection scheme for any AT E Series device sharing the RTSI bus These bidirectional lines can drive any of eight timing signals onto the RTSI bus and can receive any of these timing signals This signal connection scheme is shown in F
114. eeeeeeeeeees 68 pin male SCSI II type Maximum Working Voltage Maximum working voltage refers to the signal voltage plus the common mode voltage Channel to earth 0 0 eee eee eeeeereeee 42 V Installation Category II Channel to channel 0 eee 42 V Installation Category II AT E Series User Manual A 28 ni com Environmental Safety Appendix A Specifications for AT MIO 16XE 10 and AT AI 16XE 10 Operating temperature ee 0 to 55 C Storage temperature 0 eee 20 to 70 C H mni dity iicr ea 10 to 90 RH noncondensing Maximum altitude ccccceceeesseees 2 000 meters Pollution degree indoor use only 2 The DAQ device meets the requirements of the following standards for safety and electrical equipment for measurement control and laboratory use e EN 61010 1 1993 A2 1995 IEC 61010 1 1990 A2 1995 e UL3101 1 1993 UL 3111 1 1994 UL 3121 1998 e CAN CSA 22 2 no 1010 1 1992 A2 1997 Electromagnetic Compatibility CE C Tick and FCC Part 15 Class A Compliant Electrical EMissiOns cccceeeeeseeeeeee EN 55011 Class A at 10 m FCC Part 15A above 1 GHz Electrical immMuMItY eee eee eee eeeee Evaluated to EN 61326 1998 Table 1 3 Note For full EMC compliance you must operate this device with shielded cabling In addition all covers and filler panels must be installed Refer to the Declaration of Conformity DoC for this product for any additional regulatory compliance info
115. eferenced signal sources description 4 17 differential connections 4 21 single ended connections NRSE configuration 4 25 H hardware installation 2 1 hardware overview analog input considerations for selecting input ranges 3 10 dither 3 10 input modes 3 6 input polarity and range 3 7 multiple channel scanning considerations 3 11 analog output output polarity selection 3 13 reference selection 3 13 reglitch selection 3 14 analog trigger 3 14 block diagram 3 15 AT AI 16XE 10 block diagram 3 5 AT MIO 16E 1 and AT MIO 16E 2 block diagram 3 1 AT MIO 16E 10 and AT MIO 16DE 10 block diagram 3 3 AT MIO 16XE 10 block diagram 3 4 AT MIO 16XE 50 block diagram 3 6 AT MIO 64E 3 block diagram 3 2 digital I O 3 18 timing signal routing board and RTSI clocks 3 20 programmable function inputs 3 20 RTSI triggers 3 20 help professional services D 1 technical support D 1 ni com T O connectors 4 1 exceeding maximum ratings caution 4 15 4 17 4 28 T O signal summary table AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 4 8 AT MIO 16E 10 and AT MIO 16DE 10 4 10 AT MIO 16XE 10 and AT AI 16XE 10 4 12 AT MIO 16XE 50 4 13 signal descriptions table 4 5 IBF signal table 4 51 input characteristics AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 1 AT MIO 16E 10 and AT MIO 16DE 10 A 12 AT MIO 16XE 10 and AT AI 16XE 10 A 21 AT MIO 16XE 50 A 30 input configurations 4 18 available input modes
116. enerate a waveform but I discovered with a digital oscilloscope that there are glitches on the output signal Is this normal When it switches from one voltage to another any DAC produces glitches due to released charges The largest glitches occur when the most significant bit MSB of the D A code switches You can build a lowpass deglitching filter to remove some of these glitches depending on the frequency and nature of the output signal The AT MIO 16E 1 AT MIO 16E 2 and the AT MIO 64E 3 devices have built in reglitchers which can be enabled through software on their AO channels Refer to the Analog Output Reglitch Selection section of Chapter 3 Hardware Overview for more information about reglitching Can I synchronize a one channel AI data acquisition with a one channel AO waveform generation on my AT E Series device Yes One way to accomplish this synchronization is to use the waveform generation timing pulses to control the AI data acquisition To do this follow steps 1 through 4 in addition to the usual steps for data acquisition and waveform generation configuration 1 Enable the PFI5 line for output as follows If you are using NI DAQ call Select Signal deviceNumber ND_PFI_5 ND _OUT_UPDATE ND HIGH TO LOW If you are using LabVIEW invoke Route Signal VI with signal name set to PFIS and signal source set to AO Update 2 Setup DAQ timing so that the timing signal for A D conversion comes from PFIS5 as fol
117. ents in or voltages on the AT E Series device signal lines if they run in parallel paths at a close distance To reduce the magnetic coupling between lines separate them by a reasonable distance if they run in parallel or run the lines at right angles to each other e Do not run signal lines through conduits that also contain power lines e Protect signal lines from magnetic fields caused by electric motors welding equipment breakers or transformers by running them through special metal conduits For more information refer to the NI Developer Zone tutorial Field Wiring and Noise Consideration for Analog Signals at ni com zone National Instruments Corporation 4 55 AT E Series User Manual Calibrating the Device This chapter discusses the calibration procedures for the AT E Series device NI DAQ includes calibration functions for performing all of the steps in the calibration process Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments On the AT E Series devices these adjustments take the form of writing values to onboard calibration DACs CalDACs Some form of device calibration is required for all but the most forgiving applications If no device calibration were performed the signals and measurements could have very large offset gain and linearity errors Three levels of calibration are available to you and these are described in this chapter
118. eries User Manual Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 RTSI Trigger lines Calibration Recommended warm up time Calibration interval External calibration reference Onboard calibration reference Eeyelemennn ae dae Temperature coefficient Long term stability 0 00 eee Bus Interface Power Requirement 5 VDC 45 ossessi Power available at I O connector Physical Dimensions not including connectors T O connector AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT E Series User Manual 5 000 V 43 5 mV over full operating temperature actual value stored in EEPROM 5 ppm C max 15 ppm 1 000 h Slave 10A 4 65 VDC to 5 25 VDC at 1 A 33 8 by 9 9 cm 13 3 by 3 9 in 68 pin male SCSI II type 100 pin female 0 050 D type ni com Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Maximum Working Voltage Maximum working voltage refers to the signal voltage plus the common mode voltage Channel to earth eee eeeeeees 42 V Installation Category II Channel to channel 0 ieee 42 V Installation Category II Environmental Operating temperature ee 0 to 55 C Storage temperature oe 20 to 70 C Humidity c52ss esses secoeveesdideresszcgeedeasesiavens 10 to 90 RH noncondensing Maximum altitude ccccccccceeesseees 2 000 meters Pollution degree indoor use only 2 Safet
119. ersen Single transfer demand transfer Transfer Characteristics Relative accuracy INL After calibration eee 0 3 LSB typ 0 5 LSB max Before calibration cee ceeeeeeeeeee 4 LSB max DNL After calibration eee 0 3 LSB typ 1 0 LSB max Before calibration eee eeeeeeeeeeee 3 LSB max MOMOtonicity eee eeeeeseeeeteeeneeeeneeeeeeeee 12 bits guaranteed after calibration Offset error After calibration 1 0 mV max Before calibration 0 ccccccceceeeee 200 mV max Gain error relative to internal reference After calibration ccccceseeesees 0 01 of output max Before calibration ee 0 5 of output max Gain error relative to external reference 0 to 0 67 of output max not adjustable AT E Series User Manual A 6 ni com Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Voltage Output Rah ES ait E Coste eaten 10 V 0 to 10 V EXTREF 0 to EXTREF software selectable Output coupling eee eects DC Output impedance eee eters 0 1 Q max Current dTIVe iknin i a aie 5 mA max Protecto side het eee hae Short circuit to ground Power on Stat ccceesseeseseeseseeeeneeees 0 V 200 mV External reference input RAN Ehen nin eR 11 V Overvoltage protection 25 V powered on 15 V powered off Input impedance eee 10 kQ Bandwidth 3 dB 1 MHz Dynamic Characteristics Settling tim
120. erview for more information AT E Series User Manual A 4 ni com Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 System noise LSB not including quantization Noise Noise Gain Dither Off Dither On AT MIO 16E 1 0 5 to 10 0 25 0 5 20 0 4 0 6 50 0 5 0 7 100 0 8 0 9 AT MIO 16E 2 0 5 to 20 0 15 0 5 AT MIO 64E 3 50 0 3 0 6 100 0 5 0 7 Crosstalk DC to 100 kHz Adjacent channels 0 0 0 0 eee 75 dB All other channels 00 0 0 90 dB Stability Offset temperature coefficient Pree alts sie o actin eee 5 uV C Postga hostel 240 uV C Gain temperature coefficient 20 ppm C Analog Output Output Characteristics Number of channels csceeseeseeeeees 2 voltage Resolution cssssssveessceccccccceceesseseeees 12 bits 1 in 4 096 Max update rate FIFO mode waveform generation Internally timed 1 MS s per channel Externally timed wo 950 kS s per channel National Instruments Corporation A 5 AT E Series User Manual Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Non FIFO mode waveform generation 1 chanel sssini 800 kS s system dependent 2 Channel ese pide cessed 400 kS s system dependent Type of DAC ei icesesisadmncnineines Double buffered multiplying FIFO buffer size wo eee eens 2 048 samples Data transfers asirini eiorinn DMA interrupts programmed I O DMA modes
121. es User Manual Glossary GPCTR1_OUT GPCTRO_SOURCE GPCTR1_SOURCE H h hex Hz interchannel delay LASTCHAN LSB AT E Series User Manual general purpose counter output signal general purpose counter 0 clock source signal general purpose counter clock source signal hour hexadecimal hertz amount of time that passes between sampling consecutive channels The interchannel delay must be short enough to allow sampling of all the channels in the channel list within the scan interval The greater the interchannel delay the more time the PGIA is allowed to settle before the next channel is sampled The interchannel delay is regulated by CONVERT input output current output high current output low Industry Standard Architecture last channel bit least significant bit G 4 ni com NRSE OUT PC PFI PGIA ppm R reglitch rms RSE RTD RTSI Glossary megabytes of memory minimum minutes multifunction I O most significant bit nonreferenced single ended mode output personal computer Programmable Function Input Programmable Gain Instrumentation Amplifier parts per million to modify the glitches in a signal in order to make them less disruptive root mean square referenced single ended mode resistive temperature device Real Time System Integration National Instruments Corporation G 5 AT E Series User Manual Glossary S s S SCANCLK scan interval
122. es the SISSOURCE signal unless you select some external source Figure 4 23 shows the timing requirements for the SISOURCE signal tp 50 ns minimum ty 23 ns minimum Figure 4 23 SISOURCE Signal Timing SCANCLK Signal SCANCLK is an output only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A D conversion begins The polarity of this output is software selectable but is typically configured so that a low to high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and can be removed This signal has a 400 to 500 ns pulse width and is software enabled Figure 4 24 shows the timing for the SCANCLK signal aye Note When using NI DAQ SCANCLK polarity is low to high and cannot be changed programmatically CONVERT gt ty SCANCLK lt Pia N a 1 4 Ww ta 50 to 100 ns ty 400 to 500 ns Figure 4 24 SCANCLK Signal Timing AT E Series User Manual 4 40 ni com Chapter 4 Connecting Signals EXTSTROBE Signal EXTSTROBE is an output only signal that generates either a single pulse or a sequence of eight pulses in the hardware strobe mode An external device can use this signal to latch signals or to trigger events In the single pulse mode software controls the level of the EXTSTROBE signal A 10 us and a 1 2 us clock are available for generating a sequence of eight pulses in the hardware s
123. estion and connects you to the experts by phone discussion forum or email e Training Visit ni com custed for self paced tutorials videos and interactive CDs You also can register for instructor led hands on courses at locations around the world e System Integration If you have time constraints limited in house technical resources or other project challenges NI Alliance Program members can help To learn more call your local NI office or visit ni com alliance If you searched ni com and could not find the answers you need contact your local office or NI corporate headquarters Phone numbers for our worldwide offices are listed at the front of this manual You also can visit the Worldwide Offices section of ni com niglobal to access the branch office Web sites which provide up to date contact information support phone numbers email addresses and current events National Instruments Corporation D 1 AT E Series User Manual Glossary Prefix Meaning Value p pico 10 2 n nano 10 9 u micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 10 Numbers Symbols percent plus or minus degrees per positive of or plus negative of or minus Q ohms A square root of 5V 5 VDC source signal A amperes A D analog to digital National Instruments Corporation G 1 AT E Series User Manual Glossary AC ACH ADC AIGATE AIGND
124. estions about C 7 data acquisition timing connections AIGATE signal 4 39 CONVERT signal 4 38 EXTSTROBE signal 4 41 SCANCLK signal 4 40 SISOURCE signal 4 39 STARTSCAN signal 4 36 TRIGI signal 4 33 TRIG signal 4 34 digital ports A B and C mode input timing 4 52 mode 1 output timing 4 53 mode 2 bidirectional timing 4 54 Port C signal assignments table 4 50 timing signals table 4 51 general purpose timing signal connections FREQ OUT signal 4 50 GPCTRO_GATE signal 4 45 GPCTRO_OUT signal 4 46 GPCTRO_SOURCE signal 4 44 GPCTRO_UP_DOWN signal 4 46 GPCTR1_GATE signal 4 47 GPCTR1_OUT signal 4 48 National Instruments Corporation Index GPCTR1_SOURCE signal 4 47 GPCTR1_UP_DOWN signal 4 48 programmable function input connections 4 31 waveform generation timing connections UNISOURCE signal 4 44 UPDATE signal 4 42 WFTRIG signal 4 41 timing I O specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 8 AT MIO 16E 10 and AT MIO 16DE 10 A 18 AT MIO 16XE 10 and AT AI 16XE 10 A 26 AT MIO 16XE 50 A 35 timing signal routing board and RTSI clocks 3 20 programmable function inputs 3 20 RTSI triggers 3 20 training customer D 1 transfer characteristics analog input AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 3 AT MIO 16E 10 and AT MIO 16DE 10 A 13 AT MIO 16XE 10 and AT AI 16XE 10 A 22 AT MIO 16XE 50 A 31 analog output AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 6 AT MIO 16E 1
125. ether If you are using NI DAQ with LabVIEW and you want to connect external signal sources to the PFI lines you can use AI Clock Config AI Trigger Config AO Clock Config AO Trigger and Gate Config and Counter Set Attribute advanced level VIs to indicate which function the connected signal serves Use the Route Signal VI to enable the PFI lines to output internal signals Table C 1 Signal Name Equivalencies Hardware Signal Name LabVIEW Route Signal NI DAQ Select_Signal TRIG1 AI Start Trigger ND_IN_START_TRIGGER TRIG2 AI Stop Trigger ND_IN_STOP_TRIGGER STARTSCAN AI Scan Start ND_IN_SCAN_START SISOURCE ND_IN_SCAN_CLOCK_TIMEBASE CONVERT AI Convert ND_IN_CONVERT AIGATE ND_IN_EXTERNAL_GATE WFTRIG AO Start Trigger ND_OUT_START_TRIGGER UPDATE AO Update ND_OUT_UPDATE UISOURCE ND_OUT_UPDATE_CLOCK_TIMEBASE AOGATE ND_OUT_EXTERNAL_GATE UN Caution If you enable a PFI line for output do not connect any external signal source to it if you do you can damage the device the computer and the connected equipment National Instruments Corporation C 9 AT E Series User Manual Appendix C Common Questions AT E Series User Manual What are the power on states of the PFI and DIO lines on the I O connector At system power on and reset both the PFI and DIO lines are set to high impedance by the hardware This means that the device circuitry is not actively driving the
126. ew Figure 3 3 shows the block diagram for the AT MIO 16E 10 and AT MIO 16DE 10 Voltage Calibration REF Bi DACs Mux Mode Selection Switches 12 Bit Sampling A D Converter Data Transceivers I O Connector Calibration DACs Data 16 ms O Fa Calibration Dither Mux Circuitry oon Acar IRQ DMA T T DMA PFI Trigger i i Analog Input i Trigger Timing Control nterrupt Analog EEPROM DMA aie er AR A A Request_ Input Control Interface Bus Control i Timin Counter Ost 2 Timing vo DAQ STC interface ae Soe es ee es Interface 1 Analog Output 1 RTSI Bus Analog 8255 Bus Digital O 8 Digital O imit Output DIO g 8 g Timing Control Interface Control Control terface lt AT MIO 1 6DE 10 ONLY AO Control Data 8 AT 1 O Channel Figure 3 3 AT MIO 16E 10 and AT MIO 16DE 10 Block Diagram The primary differences between the AT MIO 16E 10 and the AT MIO 16DE 10 are in the 8255 DIO port which is not present on the AT MIO 16E 10 and the I O connector National Instruments Corporation AT E Series User Manual Chapter 3 Hardware Overview Figure 3 4 shows a block diagram for the AT MIO 16XE 10 id REF
127. fier output voltage is referenced to the ground for the device The AT E Series device A D converter ADC measures this output voltage when it performs A D conversions 4 16 ni com Chapter 4 Connecting Signals You must reference all signals to ground either at the source device or at the device If you have a floating source you should reference the signal to ground by using the RSE input mode or the DIFF input configuration with bias resistors See the Differential Connections for Nonreferenced or Floating Signal Sources section later in this chapter If you have a grounded source you should not reference the signal to AIGND You can avoid this reference by using DIFF or NRSE input configurations Types of Signal Sources When configuring the input channels and making signal connections you must first determine whether the signal sources are floating or ground referenced The following sections describe these two types of signals Floating Signal Sources A floating signal source is one that is not connected in any way to the building ground system but rather has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolator outputs and isolation amplifiers An instrument or device that has an isolated output is a floating signal source You must tie the ground reference of a floating signal to the AT E Series device AIGND to esta
128. figure the software Turn off and unplug the computer Remove the top cover or access port to the I O channel Remove the expansion slot cover on the back panel of the computer Sry eo I Ground yourself using a grounding strap or by holding a grounded object Follow the ESD protection precautions described in the Unpacking section of Chapter 1 Introduction National Instruments Corporation 2 1 AT E Series User Manual Chapter 2 Installing and Configuring the Device 6 Insert the AT E Series device into an EISA or 16 bit ISA slot It may be a tight fit but do not force the device into place 7 Screw the mounting bracket of the AT E Series device to the back panel rail of the computer 8 Visually verify the installation Make sure the device is not touching other devices or components and is fully inserted in the slot 9 Replace the cover 10 Plug in and turn on the computer The AT E Series device is installed You are now ready to install and configure the software Configuring the Device Bus Interface AT E Series User Manual Due to the DAQ PnP features the AT E Series devices are completely software configurable Two types of configuration must be performed on the AT E Series devices bus related configuration and data acquisition related configuration Bus related configuration includes setting the base I O address DMA channels and interrupt channels Data acquisition related configuration explained
129. ge installation This category refers to local level distribution such as that provided by a standard wall outlet Examples of Installation Category II are measurements on household appliances portable tools and similar equipment 1 MAINS is defined as the electricity supply system to which the equipment concerned is designed to be connected either for powering the equipment or for measurement purposes National Instruments Corporation 1 7 AT E Series User Manual Chapter 1 Introduction e Installation Category II is for measurements performed in the building installation This category is a distribution level referring to hardwired equipment that does not rely on standard building insulation Examples of Installation Category III include measurements on distribution circuits and circuit breakers Other examples of Installation Category III are wiring including cables bus bars junction boxes switches socket outlets in the building fixed installation and equipment for industrial use such as stationary motors with a permanent connection to the building fixed installation e Installation Category IV is for measurements performed at the source of the low voltage lt 1 000 V installation Examples of Installation Category IV are electric meters and measurements on primary overcurrent protection devices and ripple control units Below is a diagram of a sample installation Category IV Source of Low Voltage lt 1000
130. gnal rejection 4 26 configuration See also input configurations base I O address selection 2 3 bus interface 2 2 common questions about C 2 DMA channel selection 2 3 interrupt channel selection PC AT 16 bit DMA channel assignment map table 2 6 PC AT I O address map table 2 4 PC AT interrupt assignment map table 2 5 Plug and Play systems 2 2 switchless data acquisition 2 3 connectors See I O connectors contacting National Instruments D 1 conventions used in the manual xi CONVERT signal signal routing 3 18 timing connections 4 38 customer education D 1 professional services D 1 technical support D 1 D DACOOUT signal analog output connections 4 27 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT E Series User Manual Index AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 13 description table 4 5 DACIOUT signal analog output connections 4 27 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 13 description table 4 5 DAQ STC C 1 data acquisition timing connections AIGATE signal 4 39 CONVERT signal 4 38 EXTSTROBE signal 4 41 SCANCLK signal 4 40 SISOURCE signal 4 39 STARTSCAN signal 4 36 TRIGI signal 4 33 TRIG signal 4 34 DATA signal table
131. hould not supply one In single ended configurations more electrostatic and magnetic noise couples into the signal connections than in differential configurations The coupling is the result of differences in the signal path Magnetic coupling is proportional to the area between the two signal conductors Electrical coupling is a function of how much the electric field differs between the two conductors AT E Series User Manual 4 24 ni com Chapter 4 Connecting Signals Single Ended Connections for Floating Signal Sources RSE Configuration Figure 4 8 shows how to connect a floating signal source to an AT E Series device channel configured for RSE mode Floating Signal Vs Source ACH o o O so 9 os Programmable Gain Instrumentation Amplifier gt o A so Input Multiplexers o e AISENSE Misa uted Voltage I O Connector ee AIGND 7 O hd Selected Channel in RSE Configuration Figure 4 8 Single Ended Input Connections for Nonreferenced or Floating Signals Single Ended Connections for Grounded Signal Sources NRSE Configuration To measure a grounded signal source with a single ended configuration you must configure the AT E Series device in the NRSE input configuration The signal is then connected to the positive input of the AT E Series PGIA and the signal local ground reference is connected to the negative input of
132. ied to the positive input of the PGIA and its reference signal or return is tied to the negative input of the PGIA When you configure a channel for differential input each signal uses two multiplexer inputs one for the signal and one for its reference signal Therefore with a differential configuration for every channel up to eight AI channels are available up to 32 channels on the AT MIO 64E 3 In DIFF input mode the AI channels are paired with ACH lt i gt as the signal input and ACH lt i 8 gt as the signal reference For example ACHO is paired with ACH8 ACH 1 is paired with ACH9 and so on You should use differential input connections for any channel that meets any of the following conditions e The input signal is low level less than 1 V e The leads connecting the signal to the AT E Series device are greater than 10 ft 3 m e The input signal requires a separate ground reference point or return signal e The signal leads travel through noisy environments Differential signal connections reduce picked up noise and increase common mode noise rejection Differential signal connections also allow input signals to float within the common mode limits of the PGIA 4 20 ni com Chapter 4 Connecting Signals Differential Connections for Ground Referenced Signal Sources Figure 4 6 shows how to connect a ground referenced signal source to an AT E Series device channel configured in DIFF input mode
133. igital 1 0 imit Output DIO lt J 8 g 1 Timing Control Interface Control Control_1 terface f AO Control A Calibration 4 DACs Data 16 Analog Input Figure 3 6 AT MIO 16XE 50 Block Diagram Input Mode AT E Series User Manual The AI section of each AT E Series device is software configurable You can select different AI configurations through application software designed to control the AT E Series devices The following sections describe in detail each of the AI categories The AT E Series devices have three different input modes nonreferenced single ended NRSE input referenced single ended RSE input and differential DIFF input The single ended input configurations use up to 16 channels 64 channels on the AT MIO 64E 3 The DIFF input configuration uses up to eight channels 32 channels on the AT MIO 64E 3 Input modes are programmed on a per channel basis for multimode scanning For example you can configure the circuitry to scan 3 6 ni com Chapter 3 Hardware Overview 12 channels four differentially configured channels and eight single ended channels Table 3 1 describes the three input configurations Table 3 1 Available Input Configurations for the AT E Series Configuration Description DIFF A channel configured in DIFF mode uses two analog channel input lines One line connects to the positive input of the device programmable gain
134. iguration for both types of signal sources AT E Series User Manual 4 18 ni com Chapter 4 Connecting Signals Signal Source Type Floating Signal Source Grounded Signal Source Not Connected to Building Ground Examples Examples e Ungrounded Thermocouples e Plug in Instruments with Input e Signal Conditioning with Nonisolated Outputs Isolated Outputs e Battery Devices ACH PS _ Vy ACH S Differential DIFF 7 AIGND See text for information on bias resistors NOT RECOMMENDED ACH ACH Vy 1 Single Ended Ov gt T Ground h N Referenced RSE AIGND Ground loop losses Vg are added to measured signal ACH ACH AISENSE gt Ov AISENSE gt Single Ended Nonreferenced NRSE R 3 Wy AIGND AIGND See text for information on bias resistors Figure 4 5 Summary of Analog Input Connections National Instruments Corporation 4 19 AT E Series User Manual Chapter 4 Connecting Signals Differential Connection Considerations DIFF Input Configuration AT E Series User Manual A differential connection is one in which the AT E Series device AI signal has its own reference signal or signal return path These connections are available when the selected channel is configured in DIFF input mode The input signal is t
135. igure 3 11 Inside Region Analog Triggering Mode AT E Series User Manual 3 16 ni com Chapter 3 Hardware Overview In high hysteresis analog triggering mode the trigger is generated when the signal value is greater than highValue with the hysteresis specified by lowValue highValue lowValue Trigger Figure 3 12 High Hysteresis Analog Triggering Mode In low hysteresis analog triggering mode the trigger is generated when the signal value is less than lowValue with the hysteresis specified by highValue highValue __ berate Giese V A E ee lowValue X A r tests eos hy ts ao Sk Trigger Figure 3 13 Low Hysteresis Analog Triggering Mode The analog trigger circuit generates an internal digital trigger based on the AI signal and the user defined trigger levels This digital trigger can be used by any of the timing sections of the DAQ STC including the AI AO and general purpose counter timer sections For example the AI section can be configured to acquire n scans after the AI signal crosses a specific threshold As another example the AO section can be configured to update its outputs whenever the AI signal crosses a specific threshold National Instruments Corporation 3 17 AT E Series User Manual Chapter 3 Hardware Overview Digital 1 0 The AT E Series devices contain eight lines of DIO for general purpose use You can individua
136. igure 3 15 3 20 ni com Chapter 3 Hardware Overview a DAQ STC lt _ TRIG1 lt _ TRIG2 lt CONVERT lt gt UPDATE lt _ _ WFTRIG lt _ _ gt GPCTRO_SOURCE lt _ _ GPCTRO_GATE GPCTRO_OUT lt _ gt STARTSCAN AIGATE gt SISOURCE _UISOURCE gt GPCTR1_SOURCE lt gt GPCTR1_GATE Switch lt ______ RTSI_OSC 20 MHz Trigger A 7 RTSI Switch RTSI Bus Connector Clock V Figure 3 15 RTSI Bus Signal Connection Refer to the Timing Connections section of Chapter 4 Connecting Signals for a description of the signals shown in Figure 3 15 National Instruments Corporation 3 21 AT E Series User Manual Connecting Signals This chapter describes how to make input and output signal connections to the AT E Series device using the device I O connector Table 4 1 1 0 Connector Details Device with Numberof Cable for Connecting Cable for Connecting Cable for Connecting to T O Connector Pins to 100 pin Accessories to 68 pin Accessories 50 pin Signal Accessories 68 Pin AT E 68 N A SH6868 EP Shielded Cable SH6850 Shielded Cable Series Device R6868 Ribbon Cable R6850 Ribbon Cable SH6868R1 EP 100 Pin AT E 100 SH100100 Shielded SH1006868 Shielded Cable R1005050 Ribbon Cable Series Device Cable UN Caution Connect
137. in Chapter 3 Hardware Overview includes such settings as AI polarity and range AO reference source and other settings For more information about data acquisition related configuration refer to the NI DAQ user manual The AT E Series devices work in either a Plug and Play mode or a switchless mode These modes dictate how the base I O address DMA channels and interrupt channels are determined and assigned to the device Plug and Play The AT E Series devices are fully compatible with the industry standard Plug and Play ISA specification A Plug and Play system arbitrates and assigns resources through software freeing you from manually setting switches and jumpers These resources include the device base I O address DMA channels and interrupt channels Each AT E Series device is configured at the factory to request these resources from the Plug and Play Configuration Manager The Configuration Manager receives all of the resource requests at start up compares the available resources to those requested and assigns the available resources as efficiently as possible to the Plug and Play devices 2 2 ni com Chapter 2 Installing and Configuring the Device Application software can query the Configuration Manager to determine the resources assigned to each device without your involvement The Plug and Play software is installed as a device driver or as an integral component of the computer BIOS Switchless Data Acquisition You can
138. indows 3 1x or 5 1 or later for Windows 95 and Windows NT What is the best way to test my device without having to program the device If you are using Windows Measurement amp Automation Explorer MAX has a Test Panel option that is available by selecting Devices and Interfaces and then selecting the device The Test Panels are excellent tools for performing simple functional tests of the device such as analog input digital I O and counter timer tests I have several DAQ devices that use more total interrupt and DMA channels than I have available in my PC What should I do Visit ni com support daq for operating system specific troubleshooting instructions Analog Input and Output I m using my device in differential AI mode and I have connected a differential input signal but my readings are random and drift rapidly What s wrong Check the ground reference connections The signal may be referenced to a level that is considered floating with reference to the device ground reference Even if you are in differential mode the signal must still be referenced to the same ground level as the device reference There are various methods of achieving this while maintaining a high common mode rejection ratio CMRR These methods are outlined in Chapter 4 Signal Connections National Instruments Corporation C 3 AT E Series User Manual Appendix C Common Questions AT E Series User Manual I m using the DACs to g
139. installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks CVI DAQPad DAQ PnP DAQ STC LabVIEW Measurement Studio National Instruments NI ni com NI DAQ NI PGIA RTSI and SCXI are trademarks of National Instruments Corporation Product and company names mentioned herein are trademarks or trade names of their respective companies Patents For patents covering National Instruments products refer to the appropriate location Help Patents in your software the patents txt file on your CD or ni com patents WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS 1 NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT INJURY TO A HUMAN 2 IN A
140. ion Figure 4 7 Differential Input Connections for Nonreferenced Signals Figure 4 7 shows two bias resistors connected in parallel with the signal leads of a floating signal source If you do not use the resistors and the source is truly floating the source is not likely to remain within the common mode signal range of the PGIA and the PGIA saturates causing erroneous readings You must reference the source to AIGND The easiest way is simply to connect the positive side of the signal to the positive input of the PGIA and connect the negative side of the signal to AIGND as well AT E Series User Manual 4 22 ni com Chapter 4 Connecting Signals as to the negative input of the PGIA without any resistors at all This connection works well for DC coupled sources with low source impedance less than 100 Q However for larger source impedances this connection leaves the differential signal path significantly out of balance Noise that couples electrostatically onto the positive line does not couple onto the negative line because it is connected to ground Hence this noise appears as a differential mode signal instead of a common mode signal and so the PGIA does not reject it In this case instead of directly connecting the negative line to AIGND connect it to AIGND through a resistor that is about 100 times the equivalent source impedance The resistor puts the signal path nearly in balance so that about the same amount of noise
141. ion continues The device ignores the TRIG2 signal if it is asserted prior to the scan counter decrementing to zero After the selected edge of TRIG2 is received the device acquires a fixed number of scans and the acquisition stops This mode acquires data both before and after receiving TRIG2 As an output the TRIG2 signal reflects the posttrigger in a pretriggered acquisition sequence even if the acquisition is being externally triggered by another PFI The TRIG2 signal is not used in posttriggered data acquisition The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to high impedance at startup Figures 4 17 and 4 18 show the input and output timing requirements for the TRIG2 signal A Y Rising Edge Polarity 1 i Falling Edge Polarity tw 10 ns minimum Figure 4 17 TRIG2 Input Signal Timing ty 50 to 100 ns Figure 4 18 TRIG2 Output Signal Timing National Instruments Corporation 4 35 AT E Series User Manual Chapter 4 Connecting Signals AT E Series User Manual STARTSCAN Signal Any PFI pin can externally input the STARTSCAN signal which is available as an output on the PFI7 STARTSCAN pin Refer to Figures 4 13 and 4 14 for the relationship of STARTSCAN to the DAQ sequence As an input the STARTSCAN signal is configured in the edge detection mode You can select any PFI pin as the source for STARTSCAN and configure the po
142. ions that exceed any of the maximum ratings of input or output signals on the devices can damage the device and the computer Maximum input ratings for each signal are given in Tables 4 3 through 4 6 in the Protection column National Instruments is not liable for any damage resulting from such signal connections 1 0 Connector Caution Figure 4 1 shows the pin assignments for the 68 pin I O connector on the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 Figure 4 2 shows the pin assignments for the 100 pin I O connector on the AT MIO 64E 3 Figure 4 3 shows the pin assignments for the 100 pin I O connector on the AT MIO 16DE 10 Refer to Appendix B Optional Cable Connector Descriptions for the pin assignments for the 50 pin connectors A signal description follows the connector pinouts Connections that exceed any of the maximum ratings of input or output signals on the AT E Series devices can damage the AT E Series device and the PC Maximum input ratings for each signal are given in Tables 4 3 through 4 6 in the Protection column NI is not liable for any damage resulting from such signal connections National Instruments Corporation 4 1 AT E Series User Manual Chapter 4 Connecting Signals os ACHS8 34 68 ACHO ACH1 33 67 AIGND AIGND
143. is input has a 1 to 1 correspondence with the channels array input of the AI Config VI Therefore you must list all channels either individually or in groups of channels with the same input configuration For example if you want Channel 0 to be differential and Channels and 2 to be RSE Figure C 1 demonstrates how to program this configuration in LabVIEW coupling amp input config no change 0 no change Y no change differential ref single ended Figure C 1 Configuring Channels for Different Acquisition Modes in LabVIEW I am seeing crosstalk or ghost voltages when sampling multiple channels What does this mean You maybe experiencing a phenomenon called charge injection which occurs when you are sampling a series of high output impedance sources with a multiplexer Multiplexers contain switches usually made of switched capacitors When one of the channels for example channel 0 is selected in a multiplexer those capacitors accumulate charge When the National Instruments Corporation C 5 AT E Series User Manual Appendix C Common Questions next channel for example channel 1 is selected the accumulated charge current leaks backward through that channel If the output impedance of the source connected to channel 1 is high enough the resulting reading can somewhat reflect the voltage trends in channel 0 To circumvent this problem you must use a voltage follower op amp with unity gain for
144. k Time Signal Name Drive Output On Off mA at V mA at V ns Bias ACH lt 0 63 gt AI 100 GQ 25 15 200 pA in parallel with 100 pF AISENSE AISENSE2 AI 100 GQ 25 15 200 pA in parallel with 100 pF AIGND AO DACOOUT AO 0 1 Q Short circuit 5 at 10 5 at 10 20 to ground V us DACIOUT AO 0 1 Q Short circuit 5 at 10 5 at 10 20 to ground V us EXTREF AI 10 kQ 25 15 AOGND AO DGND DO VCC DO 01 Q Short circuit 1A to ground DIO lt 0 7 gt DIO Vec 0 5 13 at 24 at 0 4 1 1 50 kQ pu Vec 0 4 SCANCLK DO 3 5 at 5 at 0 4 1 5 50 KQ pu Vec 0 4 EXTSTROBE DO 3 5 at 5 at 0 4 1 5 50 KQ pu Vec 0 4 PFIO TRIG1 ADIO 10 kQ Vec 0 5 35 3 5at 5 at 0 4 1 5 50 kQ pu Vec 0 4 AT E Series User Manual 4 8 ni com Chapter 4 Connecting Signals Table 4 3 1 0 Signal Summary for the AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Continued AO Analog Output DO Digital Output 2 Also pulled down with a 10 kQ resistor Impedance Protection Rise Input Volts Source Sink Time Signal Name Drive Output On Off mA at V mAatV ns Bias PFI1 TRIG2 DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI2 CONVERT DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI3 GPCTR1_SOURCE DIO Vec 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI4 GPCTR1_GATE DIO
145. lained in the General Purpose Timing Signal Connections section later in this chapter All digital timing connections are referenced to DGND This reference is demonstrated in Figure 4 12 which shows how to connect an external TRIGI source and an external CONVERT source to two of the AT E Series device PFI pins AT E Series User Manual 4 30 ni com Chapter 4 Connecting Signals PFIO TRIG1 TRIG1 Source _ _ B PFI2 CONVERT CONVERT Source I O Connector Figure 4 12 TIO Connections Programmable Function Input Connections There are a total of 13 internal timing signals that you can externally control from the PFI pins The source for each of these signals is software selectable from any of the PFIs when you want external control This flexible routing scheme reduces the need to change the physical wiring to the device I O connector for different applications requiring alternative wiring You can individually enable each of the PFI pins to output a specific internal timing signal For example if you need the CONVERT signal as an output on the I O connector software can turn on the output driver for the PFI2 CONVERT pin You must be careful not to drive a PFI signal externally when it is configured as an output As an input you can individually configure each PFI for edge or level detection and for polarity selection as well You can
146. larity selection for either rising or falling edge The selected edge of the STARTSCAN signal initiates a scan The sample interval counter is started if you select internally triggered CONVERT As an output the STARTSCAN signal reflects the actual start pulse that initiates a scan even if the starts are being externally triggered by another PFI You have two output options The first is an active high pulse with a pulse width of 50 to 100 ns which indicates the start of the scan The second action is an active high pulse that terminates at the start of the last conversion in the scan which indicates a scan in progress STARTSCAN is deserted t after the last conversion in the scan is initiated This output is set to high impedance at startup Figures 4 19 and 4 20 show the input and output timing requirements for the STARTSCAN signal Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 19 STARTSCAN Input Signal Timing 4 36 ni com Chapter 4 Connecting Signals m Bo STARTSCAN ty 50 to 100 ns a Start of Scan Start Pulse CONVERT STARTSCAN tor 10 ns minimum tet b Scan in Progress Two Conversions per Scan Figure 4 20 STARTSCAN Output Signal Timing The CONVERT pulses are masked off until the device generates the STARTSCAN signal If you are using internally generated conversions the first C
147. libration 0 5 mV max Postgain error before calibration 100 mV max Gain error relative to calibration reference After calibration Gain 1 0 01 of reading max Before calibration ee 2 0 of reading max Gain with gain error adjusted to 0 at gain Lo 0 05 of reading max Amplifier Characteristics Input impedance Normal powered 00 eee 100 GQ in parallel with 50 pF Powered off 3 KQ min Ovetl0ad Samsun anon 3 KQ min Input bias current 0 eects 200 pA National Instruments Corporation A 13 AT E Series User Manual Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 Analog Output Input offset current eee 100 pA CMRR all input ranges ee 90 dB DC to 60 Hz Dynamic Characteristics Bandwidth Small signal 3 dB eeeeeeeeeeeee 150 kHz Large signal 1 THD 00 120 kHz Settling time for full scale step 10 us max to 0 5 LSB accuracy System noise not including quantization Gain Noise Dither Off Noise Dither On 0 5 to 10 0 07 LSB ms 0 5 20 0 12 LSB ms 0 5 50 0 25 LSB ms 0 6 100 0 5 LSB ims 0 7 Crosstalk DC to 100 kHz Adjacent channels cesceseeeeeeeeee 60 dB All other channels ceeeeeeeeeeee 80 dB Stability Offset temperature coefficient Pre Sains oo ssss sciences ea sree 15 uV C Postgatan RAs 240 pV C Gain temperature coefficient
148. lly configure each line through software for either input or output The AT MIO 16DE 10 has 24 additional DIO lines configured as three 8 bit ports PA lt 0 7 gt PB lt 0 7 gt and PC lt 0 7 gt You can configure each port for both input and output in various combinations with some handshaking capabilities At system startup and reset the digital T O ports are all high impedance The hardware up down control for general purpose counters 0 and 1 are connected onboard to DIO6 and DIO7 respectively Thus you can use DIO6 and DIO7 to control the general purpose counters The up down control signals are input only and do not affect the operation of the DIO lines Timing Signal Routing The DAQ STC provides a very flexible interface for connecting timing signals to other devices or external circuitry The AT E Series device uses the RTSI bus for interconnecting timing signals between devices and the Programmable Function Input PFD pins on the I O connector for connecting to external circuitry These connections are designed to enable the AT E Series device to both control and be controlled by other devices and circuits There are a total of 13 timing signals internal to the DAQ STC that can be controlled by an external source These timing signals can also be controlled by signals generated internally to the DAQ STC and these selections are fully software configurable For example the signal routing multiplexer for controlling the CO
149. lows If you are using NI DAQ call Select Signal deviceNumber ND_IN_ CONVERT ND PFI 5 ND HIGH TO LOW If you are using LabVIEW invoke AI Clock Config VI with clock source code set to PFI pin high to low and clock source string set to 5 3 Initiate AI data acquisition which starts only when the AO waveform generation starts For example if you are using NI DAQ you can call DAQ Start with appropriate parameters Similarly if you are using LabVIEW you can invoke AI Control VI with control code set to 0 start C 4 ni com Appendix C Common Questions 4 Initiate AO waveform generation If you are using NI DAQ call WFM_Group_Control1 with operation set to 1 start If you are using LabVIEW you can invoke AO Control VI with control code set to 0 start Can I programmatically enable different channels on an E Series board to acquire in different modes For example Channel 0 is differential and Channel 1 is RSE Different channels on an E Series device can be enabled to acquire in different modes However different pairs of channels are used in different modes In the example configuration given above ACHO and ACH8 would be configured in differential mode and ACH1 and AIGND would be configured in RSE mode In this configuration ACH8 could not be used in a single ended configuration To enable multi mode scanning in LabVIEW you would use the coupling amp input config cluster input of the AI Config VI Th
150. mpatibles VI Logger Q A computer 1 2 ni com Chapter 1 Introduction Software Programming Choices When programming National Instruments DAQ hardware you can use an NI application development environment ADE or other ADEs In either case you use NI DAQ NI DAQ NI DAQ which shipped with the AT E Series device has an extensive library of functions that you can call from the ADE These functions allow you to use all the features of the AT E Series device NI DAQ carries out many of the complex interactions such as programming interrupts between the computer and the DAQ hardware NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to the code Whether you are using LabVIEW Measurement Studio or other ADEs your application uses NI DAQ as illustrated in Figure 1 1 Conventional LabVIEW Programming lt _ gt Measurement Studio Environment or VI Logger NI DAQ Personal DAQ Hardware a Computer or Workstation Figure 1 1 The Relationship Between the Programming Environment NI DAQ and the Hardware To download a free copy of the most recent version of NI DAQ click Download Software at ni com National Instruments Corporation 1 3 AT E Series User Manual Chapter 1 Introduction National Instruments ADE Software LabVIEW features interactive graphics a state of
151. mputer Store the AT E Series device in the antistatic envelope when not in use Safety Information AT E Series User Manual The following section contains important safety information that you must follow during installation and use of the product Do not operate the product in a manner not specified in this document Misuse of the product can result in a hazard You can compromise the safety protection built into the product if the product is damaged in any way If the product is damaged return it to NI for repair If the product is rated for use with hazardous voltages gt 30 Vims 42 4 Vox or 60 Vac you may need to connect a safety earth ground wire according to the installation instructions Refer to Appendix A Specifications for maximum voltage ratings Do not substitute parts or modify the product Use the product only with the chassis modules accessories and cables specified in the installation instructions You must have all covers and filler panels installed during operation of the product Do not operate the product in an explosive atmosphere or where there may be flammable gases or fumes Operate the product only at or below the 1 6 ni com Chapter 1 Introduction pollution degree stated in Appendix A Specifications Pollution is foreign matter in a solid liquid or gaseous state that can produce a reduction of dielectric strength or surface resistivity The following is a description of pollution degrees
152. mum Signal Ratings for AT Series Devices If any signal should fall outside of the specified limits for any of the input signals do not connect it to the DAQ device Before proceeding add signal conditioning circuitry to the signal in question to either attenuate or clip the voltage signal If dynamic for example AC signals are connected to the inputs you must anticipate or calculate the maximum voltage that the signal may attain Again if you suspect it will exceed the maximum signal rating allowed for the selected signal you should add protection or signal conditioning circuitry to prevent damage to the DAQ device and computer AT E Series User Manual A 40 ni com Optional Cable Connector Descriptions This appendix describes the connectors on the optional cables for the AT E Series devices Figure B 1 shows the pin assignments for the 68 pin MIO connector This connector is available when you use the SH6868 EP or R6868 cable assemblies with the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 It is also one of the two 68 pin connectors available when you use the SH1006868 cable assembly with the AT MIO 16DE 10 or AT MIO 64E 3 National Instruments Corporation B 1 AT E Series User Manual Appendix B AT E Series User Manual Optional Cable Connector Descriptions ACH8 ACH1 AIGND ACH10 ACH3 AIGND ACH4 AIGND ACH13 ACH6 AIGND ACH15 DACOOUT DAC10UT EXTREF
153. n TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to high impedance at startup Figure 4 36 shows the timing requirements for the GPCTR1_OUT signal GPCTR1_SOURCE GPCTR1_OUT Pulse on TC GPCTR1_OUT Toggle Output on TC 1 TC i AT E Series User Manual Figure 4 36 GPCTR1_OUT Signal Timing GPCTR1_UP_DOWN Signal This signal can be externally input on the DIO7 pin and is not available as an output on the I O connector General purpose counter 1 counts down when this pin is at a logic low and counts up at a logic high This input can be disabled so that software can control the up down functionality and 4 48 ni com Chapter 4 Connecting Signals leave the DIO7 pin free for general use Figure 4 37 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of the AT E Series device V SOURCE V GATE t _ te ip it p D gt al tgsu lt gt ton lt lt tow gt lt lt tout gt Source Clock Period tee 50 ns minimum Source Pulse Width tsp 23 ns minimum Gate Setup Time tysu 10 ns minimum Gate Hold Time tyh O ns minimum Gate Pulse Width tyw 10 ns minimum Output Delay Time tout 80 ns maximum National Instruments Corporation 4 49 Figure 4 37 GPCTR Timing Summary The GATE and O
154. nce to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense FOR HOME OR OFFICE USE Canadian Department of Communications This Class A digital apparatus meets all requirements of the Canadian Interference Causing Equipment Regulations Cet appareil num rique de la classe A respecte toutes les exigences du R glement sur le mat riel brouilleur du Canada Class B Federal Communications Commission This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures e Reorient or relocate the receiving antenna Increase the separation between the equipment and receiver e Connect the equipmen
155. ng Signals AT E Series User Manual Figures 4 15 and 4 16 show the input and output timing requirements for the TRIG1 signal gt Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 15 TRIG1 Input Signal Timing ty 50 to 100 ns Figure 4 16 TRIG1 Output Signal Timing The device also uses the TRIGI signal to initiate pretriggered DAQ operations In most pretriggered applications the TRIG1 signal is generated by a software trigger Refer to the TRIG2 signal description for a complete description of the use of TRIG1 and TRIG2 in a pretriggered DAQ operation TRIG2 Signal Any PFI pin can externally input the TRIG2 signal which is available as an output on the PFI1 TRIG2 pin Refer to Figure 4 13 for the relationship of TRIG2 to the DAQ sequence As an input the TRIG2 signal is configured in the edge detection mode You can select any PFI pin as the source for TRIG2 and configure the polarity selection for either rising or falling edge The selected edge of the TRIG2 signal initiates the posttriggered phase of a pretriggered acquisition sequence In pretriggered mode the TRIGI signal initiates the data acquisition The scan counter indicates the minimum number of scans 4 34 ni com Chapter 4 Connecting Signals before TRIG2 can be recognized After the scan counter decrements to zero it is loaded with the number of posttrigger scans to acquire while the acquisit
156. not negative below 0 V unipolar input polarity is best However if the signal is negative or equal to zero inaccurate readings occur if you use unipolar input polarity When you enable dither you add approximately 0 5 LSB of white Gaussian noise to the signal to be converted by the ADC This addition is useful for applications involving averaging to increase the resolution of the AT E Series device as in calibration or spectral analysis In such applications noise modulation is decreased and differential linearity is improved by the addition of the dither When taking DC measurements such as when checking the device calibration you should enable dither and average about 1 000 points to take a single reading This process removes the effects of quantization and reduces measurement noise resulting in improved resolution For high speed applications not involving averaging or spectral analysis you may want to disable the dither to reduce noise You enable and disable the dither circuitry through software Figure 3 7 illustrates the effect of dither on signal acquisition Figure 3 7a shows a small 4 LSB sine wave acquired with dither off The quantization of the ADC is clearly visible Figure 3 7b shows what happens when 50 such acquisitions are averaged together quantization is still plainly visible In Figure 3 7c the sine wave is acquired with dither on There is a considerable amount of noise visible But averaging about 50 such
157. ompatibility ssscsisisssinisisni esas Base clocks available Counter timers cc00ccccsscscceeeeeeees Frequency scaler ceseeeseeeeeeeee Base clock accuracy Max source freqUuency eeceeeeeseereeees AT E Series User Manual A 8 Input High Z Programmed I O 50 kwords s system dependent 1 to 10 kwords s typical 2 up down counter timers 1 frequency scaler 20 MHz 100 kHz 10 MHz 100 kHz 0 01 ni com Appendix A Min source pulse duration Min gate pulse duration Data transfers DMA modes Triggers Analog Trigger Source JE EA A scsi AE eoves ceuch Sov EEEE Resolution Hysteresis Bandwidth 3 dB scccccssessesseseeseeessseee External input PFIO TRIG1 Impedance Coupling Protection Digital Trigger Compatibility Response Pulse width National Instruments Corporation A 9 Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 10 ns in edge detect mode 10 ns in edge detect mode DMA interrupts programmed I O Single transfer demand transfer ACH lt 0 63 gt PFIO TRIG1 full scale internal 10 V external Positive or negative software selectable 8 bits 1 in 256 Programmable 1 5 MHz internal 7 MHz external 10 KQ DC 0 5 to Vee 0 5 V when configured as a digital signal 35 V when configured as an analog trigger signal or disabled 35 V powered off Rising or falling edge 10 ns min AT E S
158. ontents About This Manual GOMVEMUONS 25 35ec555 see Uesbintia aged ea OEI EE E A E E EE cos pela coabaesin usenet xi National Instruments Documentation ccccccccccsssseccceeessseeeceeeessceccecesssseeeeeeessseeeeees xii Related Docuimen a O N ETS xiii Chapter 1 Introduction About the AT E Series ccccccccccccccsssscccceesssseeceeesssseeccecesseeececesssseeeecesssueeeceeessseeeeeens 1 1 What You Need to Get Started cccccccecccssscccccesssseeceeeessseeeeceesssseeeceessseeeceeessseeeeeens 1 2 Software Programming Choices sssseseosresesersesessersesesstsersirerscssrsereresruresesreeennesresesrese 1 3 N E Dye O EE E I PEE EEEE E E E BI 1 3 National Instruments ADE Software cccccccccccsssccccesesssceccecessseeceeeessseeeeeees 1 4 Register Level Programming cscceesccesceeseeeesceeseeceseeeacecsaeceseeesaeeeseeenneesaee 1 4 Optional Equipment s sssspno iiini sed gees a e Eea ee E E RE 1 5 Custom Cabling sis sates sieges sk ieee ects chen de cdbebbea EEEE EA EAER nied 1 5 Unpacking es ccesvesssasccstaveaies a aE aar a a E AE E R n ra 1 6 Safety Informattn senunni e a EE EEE EER E EA A 1 6 Chapter 2 Installing and Configuring the Device Installing the SoftWare snennenoupninnriraie nai a E A E E 2 1 Tnstallins the HatrdWarS monier niori E AA AA bers OAE AE OE 2 1 Configuring the Device sanin ein a AR p E N 2 2 Bus Mie a E od ae decent esheets aee ra ER E E AEs 2 2 Pl ug and Play ineine
159. or an output transfer in Mode 1 1 73 wR o o T4 OBF va OO i w r INTR T6 e gt ACK i T5 DATA b4 o Name Description Minimum Maximum Tl WR 0 to INTR 0 250 T2 WR 1 to Output 200 T3 WR 1 to OBF 0 150 T4 ACK 0 to OBF 1 150 T5 ACK Pulse Width 100 T6 ACK 1 to INTR 1 150 All timing values are in nanoseconds Figure 4 39 Mode 1 Output Timing National Instruments Corporation 4 53 AT E Series User Manual Chapter 4 Connecting Signals Mode 2 Bidirectional Timing Figure 4 40 details the timing specifications for bidirectional transfers in Mode 2 a lt gt WR T6 i OBF INTR i T7 i __ ACK o T3 f e i i STB pre i i i a gt T10 i i i i IBF i i E RD i T2 11S 4 io T8 ia T9 i e _ om lt gt lt gt Name Description Minimum Maximum T1 WR to OBF 0 150 T2 Data before STB 1 20 T3 STB Pulse Width 100 T4 STB 0 to IBF 1 150 T5 Data after STB 1 50 T6 ACK 0 to OBF 1 150 T7 ACK Pulse Width 100 T8 ACK 0 to Output 150 T9 ACK 1 to Output Float 20 250 T10 RD 1 to IBF 0 a 150 All timing values are in nanoseconds Figure 4 40 Mode 2 Bidirectional Timing
160. ormation on warranty coverage Connections that exceed any of the maximum ratings of input signals on the data acquisition DAQ devices listed in the table below can damage the computer and the device 3 Note These are the absolute maximum ratings of the input signals not the working ratings Refer to the user manual for the recommended operating conditions of the device Use the following specifications as definitive values Signal ratings change depending on whether the DAQ device is powered on or off AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16XE 10 AT AI 16XE 10 AT MIO 16E 10 AT MIO 16DE 10 AT MIO 16XE 50 Signal Name On Off On Off On Off ACH lt x gt 25 V 15 V 35 V 25 V 25 V 15 V AISENSE 25 V 15 V 35 V 25 V 25 V 15 V AT E Series User Manual ni com Appendix A Specifications for Maximum Signal Ratings for AT Series Devices AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16XE 10 AT MIO 16E 10 AT AI 16XE 10 AT MIO 16DE 10 AT MIO 16XE 50 Signal Name On Off On Off On Off EXTREF 25 V 15 V 35 V 25 V 25 V 15 V PFIO 5 5 to 0 5 V3 35 V4 5 5 to 0 5 V3 0 5 V5 5 5 to 0 5 V3 0 5 V5 PFI lt 1 9 gt 5 5 to 0 5 V3 0 5 V5 5 5 to 0 5 V3 0 5 V5 5 5 to 0 5 V3 0 5 V5 DIO lt x gt 5 5 to 0 5 V3 0 5 V5 5 5 to 0 5 V3 0 5 V5 5 5 to 0 5 V3 0 5 V5 PA PB PC lt x gt N A N A 5 5
161. output either high or low However these lines may have pull up or pull down resistors connected to them as shown in Tables 4 2 to 4 5 These resistors weakly pull the output to either a logic high or logic low state For example DIO 0 is in the high impedance state after power on and Table 4 2 1 0 Signal Summary for the AT E Series shows that there is a 50 kQ pull up resistor This pull up resistor sets the DIO 0 pin to a logic high when the output is in a high impedance state C 10 ni com Technical Support and Professional Services Visit the following sections of the National Instruments Web site at ni com for technical support and professional services e Support Online technical support resources include the following Self Help Resources For immediate answers and solutions visit our extensive library of technical support resources available in English Japanese and Spanish at ni com support These resources are available for most products at no cost to registered users and include software drivers and updates a KnowledgeBase product manuals step by step troubleshooting wizards hardware schematics and conformity documentation example code tutorials and application notes instrument drivers discussion forums a measurement glossary and so on Assisted Support Options Contact NI engineers and other measurement and automation professionals by visiting ni com ask Our online system helps you define your qu
162. pendently with timing resolutions of 50 ns or 10 us With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme is quite flexible and completely software configurable New capabilities such as buffered pulse generation equivalent time sampling and seamlessly changing the sampling rate are possible How fast is each AT E Series device The last numeral in the name of an AT E Series device specifies the settling time in microseconds for that particular device For example the AT MIO 16E 2 has a 2 us settling time which corresponds to a sampling rate of 500 kS s These sampling rates are aggregate one channel at 500 kS s or two channels at 250 kS s per channel illustrates the National Instruments Corporation C 1 AT E Series User Manual Appendix C Common Questions relationship Notice however that some AT E Series devices have settling times that vary with gain and accuracy Refer to Appendix A Specifications for exact specifications What type of 5 V protection do the AT E Series devices have The AT E Series devices have 5 V lines equipped with a self resetting 1 A fuse How do I use the AT E Series device with the NI DAQ C API The NI DAQ User Manual for PC Compatibles describes the general programming flow when using the NI DAQ C API as well as contains example code For a list of functions that support the AT E Series device you can refer to the N
163. put AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 The AT E Series devices supply two channels of AO voltage at the I O connector You can select the reference and range for the AO circuitry through software The reference can be either internal or external whereas the range can be either bipolar or unipolar e AT MIO 16XE 50 The AT MIO 16XE 50 supplies two channels of AO voltage at the I O connector The range is fixed at bipolar 10 V e AT MIO 16XE 10 The AT MIO 16XE 10 supplies two channels of AO voltage at the I O connector The range is software selectable between unipolar 0 to 10 V and bipolar 10 V Analog Output Reference Selection AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 only You can connect each D A converter DAC to the AT E Series device internal reference of 10 V or to the external reference signal connected to the external reference EXTREF pin on the I O connector This signal applied to EXTREF should be between 10 and 10 V You do not need to configure both channels for the same mode Analog Output Polarity Selection e AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 only You can configure each AO channel for either unipolar or bipolar output A unipolar configuration has a range of 0 to Vep at the AO A bipolar configuration has a range of V ef to V ef at the AO Vet is the voltage reference used
164. r and bipolar Unipolar input means that the input voltage range is between 0 and V where Vef is a positive reference voltage Bipolar input means that the input voltage range is between V ef and V ef The AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 have a unipolar input range of 10 V 0 to 10 V and a bipolar input range of 20 V 10 V You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely AT E Series User Manual 3 8 ni com Chapter 3 Hardware Overview 5 Note You can calibrate the AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 AI circuitry for either a unipolar or bipolar polarity If you mix unipolar and bipolar channels in the scan list and you are using NI DAQ then NI DAQ loads the calibration constants appropriate to the polarity for which AI channel 0 is configured The software programmable gain on these devices increases their overall flexibility by matching the input signal ranges to those that the ADC can accommodate The AT MIO 16XE 10 and AT AI 16XE 10 have gains of 1 2 5 10 20 50 and 100 and the AT MIO 16XE 50 has gains of 1 2 10 and 100 These gains are suited for a wide variety of signal levels With the proper gain setting you can use the full resolution of the ADC to measure the input signal Table 3 3 shows the overall input range and precision according to the input range configuration and gain used Table 3 3 Actual Range and Mea
165. rectional transfers Port C signal assignments table 4 51 timing specifications 4 54 multiple channel scanning 3 11 National Instruments customer education D 1 professional services D 1 system integration services D 1 technical support D 1 worldwide offices D 1 National Instruments documentation xii noise avoiding 4 55 NRSE nonreferenced single ended input description table 3 7 differential connections 4 22 single ended connections NRSE configuration 4 25 0 OBF signal table 4 51 online technical support D 1 operation of AT E series boards See hardware overview optional equipment 1 5 output characteristics AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 5 AT MIO 16E 10 and AT MIO 16DE 10 A 14 AT MIO 16XE 10 A 24 AT MIO 16XE 50 A 33 P PA lt 0 7 gt signal AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 description table 4 6 AT E Series User Manual 1 8 PB lt 0 7 gt signal AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 description table 4 6 PC lt 0 7 gt signal table 4 6 PFIO TRIG1 signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 6 PFI1 TRIG2 signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 5
166. rmation To obtain the DoC for this product click Declaration of Conformity at ni com hardref nsf This Web site lists the DoCs by product family Select the appropriate product family followed by the product and a link to the DoC appears in Adobe Acrobat format Click the Acrobat icon to download or read the DoC National Instruments Corporation A 29 AT E Series User Manual Appendix A Specifications for AT MIO 16XE 50 AT MIO 16XE 50 Analog Input Input Characteristics Number of channels 16 single ended or 8 differential software selectable Type of ADC Resolution Maximum sampling rate Input signal ranges Successive approximation 16 bits 1 in 65 536 20 kS s guaranteed Range Input Range Software Selectable Bipolar Unipolar 20 V 10 V 10 V 5 V 0to 10 V 5V 0to5V 2V 1 V 1V Otol V 200 mV 100 mV 100 mV 0 to 100 mV Input coupling orenen DC Maximum working voltage signal common mode Overvoltage protection eee Inputs protected FIFO buffer size AT E Series User Manual The average voltage of each differential pair should remain within 8 V of ground 25 V powered on 15 V powered off ACH lt 0 15 gt AISENSE 512 samples ni com Appendix A Specifications for AT MIO 16XE 50 Data transfers cccccecceseseeeeeseseseeees DMA interrupts programmed I O DMA mod s sninn s Single transfer
167. rotection column National Instruments Corporation AT E Series User Manual Chapter 4 Connecting Signals AT E Series User Manual In NRSE mode the AISENSE and AISENSE2 signals are connected internally to the negative input of the AT E Series device PGIA when their corresponding channels are selected In DIFF and RSE modes these signals are left unconnected AIGND is an AI common signal that is routed directly to the ground tie point on the AT E Series devices You can use this signal for a general analog ground tie point to the AT E Series device if necessary Connection of AI signals to the AT E Series device depends on the configuration of the AI channels you are using and the type of input signal source With the different configurations you can use the PGIA in different ways Figure 4 4 shows a diagram of the AT E Series device PGIA Programmable Gain Instrumentation V Gam ii x Amplifier PGIA Vm Measured Vin Voltage Vin Ving Vin Gain Figure 4 4 AT E Series PGIA The PGIA applies gain and common mode voltage rejection and presents high input impedance to the analog input signals connected to the AT E Series device Signals are routed to the positive and negative inputs of the PGIA through input multiplexers on the device The PGIA converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier The ampli
168. rrrrssesssrseee AN CCUT TO AEREE EREE NEEE ARTEN Digital Trigger Compatibility seseseesseeseeesesesresrssrseesrse RESPONSE sereen one neiet Pulse Width oo eee eeeeseceeeeeeees RTSI Trigger Nes esac sccesd sieve aiie National Instruments Corporation A 27 ACH lt 0 15 gt PFIO TRIG1 Full scale internal 10 V external Positive or negative software selectable 12 bits 1 in 4 096 Programmable 255 kHz internal 4 MHz external 10 KQ DC 0 5 to Vcc 0 5 V when configured as a digital signal 35 V when configured as an analog trigger signal or disabled 35 V powered off 1 of full scale range Rising or falling edge 10 ns min AT E Series User Manual Appendix A Specifications for AT MIO 16XE 10 and AT AI 16XE 10 Calibration Recommended warm up time 15 min Calibration interval s s s 1 year External calibration reference gt 6 and lt 9 999V Onboard calibration reference Tee A EE AE E E SEAE 5 000 V 1 0 mV over full operating temperature actual value stored in EEPROM Temperature coefficient 0 0 6 ppm C max Long term stability 0 0 6 ppm 1 000 h Bus Interface Typer atau cial ign awed Slave Power Requirement 5 VDOX45 isanne a 12A Power available at I O connector 4 65 VDC to 5 25 VDC atl A Physical Dimensions not including connectors 33 8 by 9 9 cm 13 3 by 3 9 in T O COMNECEOL Seoni eee
169. s Corporation 4 23 AT E Series User Manual Chapter 4 Connecting Signals Single Ended Connection Considerations A single ended connection is one in which the AT E Series device AI signal is referenced to a ground that can be shared with other input signals The input signal is tied to the positive input of the PGIA and the ground is tied to the negative input of the PGIA When every channel is configured for single ended input up to 16 analog input channels are available up to 64 channels on the AT MIO 64E 3 You can use single ended input connections for any input signal that meets the following conditions e The input signal is high level greater than 1 V e The leads connecting the signal to the AT E Series device are less than 10 ft 3 m e The input signal can share a common reference point with other signals DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions You can software configure the AT E Series device channels for two different types of single ended connections RSE configuration and NRSE configuration The RSE configuration is used for floating signal sources in this case the AT E Series device provides the reference ground point for the external signal The NRSE input configuration is used for ground referenced signal sources in this case the external signal supplies its own reference ground point and the AT E Series device s
170. scan rate SCXI SE SISOURCE STARTSCAN T TC THD TRIG TTL U UI UISOURCE UPDATE AT E Series User Manual seconds samples scan clock signal controls how often a scan is initialized The scan interval is regulated by STARTSCAN reciprocal of the scan interval Signal Conditioning eXtensions for Instrumentation single ended inputs SI counter clock signal start scan signal terminal count total harmonic distortion trigger signal transistor transistor logic update interval update interval counter clock signal update signal G 6 ni com WFTRIG volts volts direct current volts input high volts input low volts in volts output high volts output low reference voltage waveform generation trigger signal National Instruments Corporation G 7 Glossary AT E Series User Manual Index Symbols 5 V signal description 4 6 power connections 4 29 A about the manual xi ACH lt 0 15 gt signal analog input connections 4 15 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 13 description table 4 5 ACH lt 0 63 gt signal analog input connections 4 15 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 description table 4 5 ACK signal table 4 51 addresses base I O address selection 2 3 PC AT I O address map table 2 4 AIGATE signal 4 39 AIGND signal analog input connections 4
171. signal referenced to the rising edge of a source signal Any OUT signal state changes occur within 80 ns after the rising or falling edge of the source signal FREQ_OUT Signal This signal is available only as an output on the FREQ OUT pin The FREQ _ OUT signal is the output of the AT E Series device frequency generator The frequency generator is a 4 bit counter that can divide its input clock by the numbers 1 through 16 The input clock of the frequency generator is software selectable from the internal 10 MHz and 100 kHz timebases The output polarity is software selectable This output is set to high impedance at startup Timing Specifications for Digital 1 0 Ports A B and C e AT MIO 16DE 10 only In addition to its function as a digital I O port digital port C PC lt 0 7 gt can also be used for handshaking when performing data transfers with ports A and B The signals assigned to port C depend on the mode in which it is programmed In mode 0 port C is considered two 4 bit I O ports In modes 1 and 2 port C is used for status and handshaking signals with two or three additional I O bits Table 4 7 summarizes the signal assignments of port C for each programmable mode Refer to Table 4 7 for descriptions of the signals for port C Table 4 7 Port C Signal Assignments Group A Group B Programming Mode PC7 PC6 PCS PC4 PC3 PC2 PC1 PCO Mode 0 T O T O VO VO VO T O T O T O Mode 1 Input T O T O IBF STB INTR STBg I
172. surement Precision for the AT MIO 16XE 10 AT Al 16XE 10 and AT MIO 16XE 50 Range Configuration Gain Actual Input Range Precision 0 to 10 V 1 0 0 to 10 V 152 59 uV 2 0 0 to 5 V 76 29 uV 5 0 0 to 2 V 30 52 uV 10 0 Oto 1 V 15 26 uV 20 0 0 to 500 mV 63 uV 50 0 0 to 200 mV 3 05 uV 100 0 0 to 100 mV 1 53 uV 10 to 10 V 1 0 10 to 10 V 305 18 uV 2 0 5 to 5 V 152 59 uV 5 02 2 to 2 V 61 04 uV 10 0 lto 1V 30 52 uV 20 02 500 to 500 mV 15 26 uV 50 02 200 to 200 mV 6 10 uV 100 0 100 to 100 mV 3 05 uV The value of 1 LSB of the 16 bit ADC that is the voltage increment corresponding to a change of one count in the ADC 16 bit count 2 AT MIO 16XE 10 and AT AI 16XE 10 only Note Refer to Appendix A Specifications for absolute maximum ratings National Instruments Corporation 3 9 AT E Series User Manual Chapter 3 Hardware Overview Dither AT E Series User Manual Considerations for Selecting Input Ranges Which input polarity and range you select depends on the expected range of the incoming signal A large input range can accommodate a large signal variation but reduces the voltage resolution Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range For best results you should match the input range as closely as possible to the expected range of the input signal For example if you are certain the input signal is
173. t Double buffered DMA interrupts programmed I O Transfer Characteristics Relative accuracy INL ceeeeeseeeees 0 5 LSB max DND reiini rana eth Monotonicity eee eeeeeeeeeeneeeeneeeneeeeeees National Instruments Corporation 1 LSB max Single transfer demand transfer 12 bits guaranteed AT E Series User Manual Appendix A Digital 1 0 AT E Series User Manual Specifications for AT MIO 16XE 50 Offset error After calibration 00ccccceceeeee Before calibration ae 0 5 mV max oes 85 mV max Gain error relative to calibration reference After calibration Before calibration cccccccee Voltage Output Range nian tds cae Output coupling wo eee Output impedance eee Current diVerences Protections sisses onbidea anhs Power on state ooeec Dynamic Characteristics Settling time for full scale step Slew rate oo ecccecccessesssessserereeees Glitch energy at midscale transition Magnitude DUT ati ON sosna Stability Offset temperature coefficient Gain temperature coefficient Number of channels cccc0ceceeeee Compatibility sesser 0 01 of output max 1 of output max 10 V DC 0 1 Q max 5 mA Short circuit to ground 0 V 85 mV 50 us to 0 5 LSB accuracy 2 V us 40 UV ings DC to 1 MHz 30 mV 10 us 25 uV C 15 ppm C 8 input ou
174. t for the analog output circuitry This pin is not available on the AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 AOGND Analog Output Ground The analog output voltages are referenced to this node All three ground references AIGND AOGND and DGND are connected together on the AT E Series device DGND Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply All three ground references AIGND AOGND and DGND are connected together on the AT E Series device DIO lt 0 7 gt DGND Input or Digital I O signals DIO6 and 7 can control the up down Output signal of general purpose counters 0 and 1 respectively National Instruments Corporation 4 5 AT E Series User Manual Chapter 4 Connecting Signals Table 4 2 1 0 Signal Summary for the AT E Series Continued Signal Name Reference Direction Description PA lt 0 7 gt DGND Input or Output Port A These pins are port A of the extra digital I O signals on the AT MIO 16DE 10 PB lt 0 7 gt DGND Input or Output Port B These pins are port B of the extra digital I O signals on the AT MIO 16DE 10 PC lt 0 7 gt DGND Input or Output Port C These pins are port C of the extra digital I O signals on the AT MIO 16DE 10 5V DGND Output 5 VDC Source These pins are fused for up to 1 A of 5 V suppl
175. t into an outlet on a circuit different from that to which the receiver is connected e Consult the dealer or an experienced radio TV technician for help Canadian Department of Communications This Class B digital apparatus meets all requirements of the Canadian Interference Causing Equipment Regulations Cet appareil num rique de la classe B respecte toutes les exigences du R glement sur le mat riel brouilleur du Canada Compliance to EU Directives Readers in the European Union EU must refer to the Manufacturer s Declaration of Conformity DoC for information pertaining to the CE Mark compliance scheme The Manufacturer includes a DoC for most every hardware product except for those bought for OEMs if also available from an original manufacturer that also markets in the EU or where compliance is not required as for electrically benign apparatus or cables To obtain the DoC for this product click Declaration of Conformity at ni com hardref nsf This Web site lists the DoCs by product family Select the appropriate product family followed by your product and a link to the DoC appears in Adobe Acrobat format Click the Acrobat icon to download or read the DoC Certain exemptions may apply in the USA see FCC Rules 15 103 Exempted devices and 15 105 c Also available in sections of CFR 47 The CE Mark Declaration of Conformity will contain important supplementary information and instructions for the user or installer C
176. tegory II Channel to channel 0 0 0 eee eee 42 V Installation Category II National Instruments Corporation A 19 AT E Series User Manual Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 Environmental Operating temperature 0 0 eee 0 to 55 C Storage temperature ee eee 20 to 70 C H midity occ ccetsntdecseuessitcesiseieanessaeeseadesseast 10 to 90 RH noncondensing Maximum altitude cccccccecessseeeeees 2 000 meters Pollution degree indoor use only 2 Safety The DAQ device meets the requirements of the following standards for safety and electrical equipment for measurement control and laboratory use e EN 61010 1 1993 A2 1995 IEC 61010 1 1990 A2 1995 e UL3101 1 1993 UL 3111 1 1994 UL 3121 1998 e CAN CSA c22 2 no 1010 1 1992 A2 1997 Electromagnetic Compatibility CE C Tick and FCC Part 15 Class A Compliant Electrical emissions n EN 55011 Class A at 10 m FCC Part 15A above 1 GHz Electrical immunity 0 eee eee eeeeeeeeeeee Evaluated to EN 61326 1998 Table 1 Sy Note For full EMC compliance you must operate this device with shielded cabling In addition all covers and filler panels must be installed Refer to the Declaration of Conformity DoC for this product for any additional regulatory compliance information To obtain the DoC for this product click Declaration of Conformity at ni com hardref nsf This Web site lists the DoCs by product family Sele
177. the PGIA The ground point of the signal should therefore be connected to the AISENSE pin Any potential difference between the AT E Series ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the PGIA and this difference is rejected by the amplifier If the input circuitry of an AT E Series device were referenced to ground in this situation as in the RSE input configuration this difference in ground potentials would appear as an error in the measured voltage National Instruments Corporation 4 25 AT E Series User Manual Chapter 4 Connecting Signals Figure 4 9 shows how to connect a grounded signal source to an AT E Series device channel configured for NRSE mode Common Mode Noise and Ground Potential Signal Source Vs 1 0 Connector gt ACH o oo Ground Q co Referenced o s o Programmable Gain 2 Instrumentation ifi o so Amplifier PGIA ACH z 6 Ea Measured Voltage o s o A O so ot So Input Multiplexers o AISENSE AIGND Selected Channel in NRSE Configuration Figure 4 9 Single Ended Input Connections for Ground Referenced Signal Common Mode Signal Rejection Considerations AT E Series User Manual Figures 4 6 and 4 9 show connections for signal sources that are already referenced to some ground point
178. the art interface and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a series of virtual instruments for using Lab VIEW with National Instruments DAQ hardware is included with LabVIEW Measurement Studio which includes LabWindows CVI tools for Visual C and tools for Visual Basic is a development suite that allows you to use ANSI C Visual C and Visual Basic to design the test and measurement software For C developers Measurement Studio includes LabWindows CVI a fully integrated ANSI C application development environment that features interactive graphics and the LabWindows CVI Data Acquisition and Easy I O libraries For Visual Basic developers Measurement Studio features a set of ActiveX controls for using National Instruments DAQ hardware These ActiveX controls provide a high level programming interface for building virtual instruments For Visual C developers Measurement Studio offers a set of Visual C classes and tools to integrate those classes into Visual C applications The libraries ActiveX controls and classes are available with Measurement Studio and NI DAQ Using LabVIEW or Measurement Studio greatly reduces the development time for your data acquisition and control application Register Level Programming The final option for programming any National Instruments DAQ hardware is to write register level software Writing register level programming software can be very time
179. the environment in which it is used Self Calibration The AT E Series device can measure and correct for almost all of its calibration related errors without any external signal connections The NI software provides a self calibration method you can use This self calibration process which generally takes less than a minute is the preferred method of assuring accuracy in your application You should initiate self calibration to ensure that the effects of any offset gain and linearity drifts particularly those due to warmup are minimized Immediately after self calibration the only significant residual calibration error could be gain error due to time or temperature drift of the onboard voltage reference This error is addressed by external calibration which is discussed in the External Calibration section If you are interested primarily in relative measurements you can ignore a small amount of gain error and self calibration should be sufficient External Calibration AT E Series User Manual The AT E Series device has an onboard calibration reference to ensure the accuracy of self calibration Its specifications are listed in Appendix A Specifications The reference voltage is measured at the factory and stored in the EEPROM for subsequent self calibrations This voltage is stable enough for most applications but if you are using the device at an extreme temperature or if the onboard reference has not been measured for a ye
180. to 0 5 V36 0 5 V56 N A N A DACxOUT Output only EXTSTROBE Output only SCANCLK Output only GPCTRO_OUT Output only FREQ_OUT Output only VCC Output only 1 N A for AT MIO 16XE 10 and AT AI 16XE 10 2 N A for AT MIO 16XE 50 PCI MIO 16XE 50 and DAQPad MIO 16XE 50 3 When configured as a digital input 4 When PFIO is configured as an analog trigger or the DAQ device is powered off the input protection level is 35 V 5 The E Series devices guarantee a powered off input protection level of 0 5 V This level can be exceeded if the source of the input signal has a current limited output such as any member of the LS HC or HCT logic families 6 N A for AT MIO 16E 10 Test the Connections The easiest way to check the proper limits of the I O signals is to measure them with a voltmeter Be sure to check the signal levels before connecting them to the I O connector of the DAQ device Connect the negative lead usually black of the voltmeter to a ground terminal on the computer chassis This can be a grounding lug at the back of the computer or any part of the base metal computer chassis Then measure each signal input using the voltmeter s positive terminal usually red In the case of a differential signal measure each signal in the differential pair individually Measure both the DC and AC voltage of each signal National Instruments Corporation A 39 AT E Series User Manual Appendix A Specifications for Maxi
181. tput TTL CMOS ni com Timing 1 0 Appendix A Specifications for AT MIO 16XE 50 Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current Vin 0 V 320 uA Input high current Vin 5 V 10 uA Output low voltage Ip 24 mA 0 4 V Output high voltage lop 13 mA 4 35 V Power on state sehere ni Input high impedance Data transfers enient o ais Programmed I O Max transfer rate 1 word 8 bits 50 kwords s system dependent Constant sustainable rate 1 to 10 kwords s typical Number of channels 0 0 0 eee 2 up down counter timers 1 frequency scaler Resolution Counter timers cccccccscssseseseseeees 24 bits Frequency scaler eeeseeseeeeeees 4 bits Compatibility sin ssronip iiano ni TTL CMOS Base clocks available Counter timers ccccccsccceeesseees 20 MHz 100 kHz Frequency scaler oo eee 10 MHz 100 kHz Base clock accuracy n 0 01 Max source frequency eee eee 20 MHz Min source pulse duration 0 0 10 ns edge detect mode Min gate pulse duration 10 ns edge detect mode National Instruments Corporation A 35 AT E Series User Manual Appendix A Specifications for AT MIO 16XE 50 Data transfers miniis isee DMA interrupts programmed I O DMA modes hneisa Single transfer Triggers Digital Trigger Compatibility 00 eee eeeeereeeeeee TTL RESPO
182. trobe mode Figure 4 25 shows the timing for the hardware strobe mode EXTSTROBE signal 3 Note EXSTROBE cannot be enabled through NI DAQ Von i VoL lt lt lt 1 WwW 1 w t 600 ns or 5 us Figure 4 25 EXTSTROBE Signal Timing Waveform Generation Timing Connections The analog group defined for the AT E Series device is controlled by WFTRIG UPDATE and UISOURCE WFTRIG Signal Any PFI pin can externally input the WFTRIG signal which is available as an output on the PFI6 WFTRIG pin As an input the WFTRIG signal is configured in the edge detection mode You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising or falling edge The selected edge of the WFTRIG signal starts the waveform generation for the DACs The update interval UI counter is started if you select internally generated UPDATE As an output the WFTRIG signal reflects the trigger that initiates waveform generation even if the waveform generation is being externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to high impedance at startup National Instruments Corporation 4 41 AT E Series User Manual Chapter 4 Connecting Signals AT E Series User Manual Figures 4 26 and 4 27 show the input and output timing requirements for the WFTRIG signal Rising Edge Polarity 1 Falling Edge
183. use the polarity selection for any of the 13 timing signals but the edge or level detection National Instruments Corporation 4 31 AT E Series User Manual Chapter 4 Connecting Signals depends upon the particular timing signal being controlled The detection requirements for each timing signal are listed within the section that discusses that individual signal In edge detection mode the minimum pulse width required is 10 ns This applies for both rising edge and falling edge polarity settings There is no maximum pulse width requirement in edge detect mode In level detection mode there are no minimum or maximum pulse width requirements imposed by the PFIs themselves but there may be limits imposed by the particular timing signal being controlled These requirements are listed later in this chapter DAQ Timing Connections AT E Series User Manual The DAQ timing signals are TRIG TRIG2 STARTSCAN CONVERT AIGATE SISOURCE SCANCLK and EXTSTROBE Posttriggered DAQ allows you to view only data that is acquired after a trigger event is received A typical posttriggered DAQ sequence is shown in Figure 4 13 Pretriggered DAQ allows you to view data that is acquired before the trigger of interest in addition to data acquired after the trigger Figure 4 14 shows a typical pretriggered DAQ sequence The description for each signal shown in these figures is included later in this chapter TRIG1
184. ut characteristics A 12 stability A 14 transfer characteristics A 13 AT MIO 16XE 10 and AT AI 16XE 10 amplifier characteristics A 22 dynamic characteristics A 23 A 24 input characteristics A 21 stability A 24 transfer characteristics A 22 AT MIO 16XE 50 amplifier characteristics A 31 dynamic characteristics A 32 input characteristics A 30 transfer characteristics A 31 analog output common questions about C 3 output polarity selection 3 13 reference selection 3 13 reglitch selection 3 14 signal connections 4 27 analog output specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 5 dynamic characteristics A 7 output characteristics A 5 stability A 7 transfer characteristics A 6 voltage output A 7 AT E Series User Manual l 2 AT MIO 16E 10 and AT MIO 16DE 10 dynamic characteristics A 16 output characteristics A 14 stability A 16 transfer characteristics A 15 voltage output A 15 AT MIO 16XE 10 dynamic characteristics A 25 output characteristics A 24 stability A 25 transfer characteristics A 24 voltage output A 25 AT MIO 16XE 50 dynamic characteristics A 34 output characteristics A 33 stability A 34 transfer characteristics A 33 voltage output A 34 analog trigger block diagram 3 15 specifications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 9 specifications AT MIO 16XE 10 and AT AI 16XE 10 A 27 AOGND signal analog output connections 4 27 AT MIO 16E 1 AT MIO
185. w There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTR1_SOURCE unless you select some external source GPCTR1_GATE Signal Any PFI pin can externally input the GPCTR1_GATE signal which is available as an output on the PFI4 GPCTR1_GATE pin As an input the GPCTR1_GATE signal is configured in edge detection mode You can select any PFI pin as the source for GPCTR1_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform such actions as starting and stopping the counter generating interrupts saving the counter contents and so on National Instruments Corporation 4 47 AT E Series User Manual Chapter 4 Connecting Signals As an output the GPCTR1_GATE signal monitors the actual gate signal connected to general purpose counter 1 even if the gate is being externally generated by another PFI This output is set to high impedance at startup Figure 4 35 shows the timing requirements for the GPCTR1_GATE signal lt gt Rising Edge Polarity i Falling Edge Polarity tw 10 ns minimum Figure 4 35 GPCTR1_GATE Signal Timing in Edge Detection Mode GPCTR1_OUT Signal This signal is available only as an output on the GPCTR1_OUT pin The GPCTR1_OUT signal monitors the TC device general purpose counter 1 You have two software selectable output options pulse o
186. with gain error adjusted to 0 at gain 1 0 02 of reading max Amplifier Characteristics Input impedance Normal powered 00 0 0 eee 100 GQ in parallel with 100 pF POWered offis inen seuss teenies 820 Q min Overload is issccste chives iieri 820 Q min Input bias current 0 eee eters 200 pA Input offset current eee 100 pA CMRR DC to 60 Hz Range CMRR 20 V 95 dB 10 V 100 dB 100 mV to5 V 106 dB National Instruments Corporation A 3 AT E Series User Manual Appendix A Specifications for AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 Dynamic Characteristics Bandwidth Small Large Signal Signal 3dB 1 THD AT MIO 16E 1 1 6 MHz 1 MHz AT MIO 16E 2 1 MHz 300 kHz AT MIO 64E 3 Settling time for full scale step Accuracy 0 012 0 024 0 098 Gain 0 5 LSB 1 LSB 4 LSB AT MIO 16E 1 0 5 2 us typ 1 5 us typ 1 5 us typ 3 us max 2 us max 2 us max 1 2 us typ 1 5 us typ 1 3 us typ 3 us max 2 us max 1 5 us max 2to50 2 us typ 1 5 us typ 0 9 us typ 3 us max 2 us max 1 us max 100 2 us typ 1 5 us typ 1 us typ 3 us max 2 us max 1 5 us max AT MIO 16E 2 All 2 us typ 1 9 us typ 1 8 us typ 4 us max 2 us max 2 us max AT MIO 64E 3 All 3 us typ 2 us typ 1 8 us typ 5 us max 3 us max 2 us max Accuracy values valid for source impedances lt 1 KQ Refer to the Multiple Channel Scanning Considerations section of Chapter 3 Hardware Ov
187. y The DAQ device meets the requirements of the following standards for safety and electrical equipment for measurement control and laboratory use e EN 61010 1 1993 A2 1995 IEC 61010 1 1990 A2 1995 e UL3101 1 1993 UL 3111 1 1994 UL 3121 1998 e CAN CSA 22 2 no 1010 1 1992 A2 1997 Electromagnetic Compatibility CE C Tick and FCC Part 15 Class A Compliant Electrical EMISSIONS ccceeeeeeeeeeeeees EN 55011 Class A at 10 m FCC Part 15A above 1 GHz Electrical iMMUMNItY eee eeeeeeeeeeeees Evaluated to EN 61326 1998 Table 1 3 Note For full EMC compliance you must operate this device with shielded cabling In addition all covers and filler panels must be installed Refer to the Declaration of Conformity DoC for this product for any additional regulatory compliance information To obtain the DoC for this product click Declaration of Conformity at ni com hardref nsf This Web site lists the DoCs by product family Select the National Instruments Corporation A 11 AT E Series User Manual Appendix A Specifications for AT MIO 16E 10 and AT MIO 16DE 10 appropriate product family followed by the product and a link to the DoC appears in Adobe Acrobat format Click the Acrobat icon to download or read the DoC AT MIO 16E 10 and AT MIO 16DE 10 Analog Input Input Characteristics Number of channels 0 eee 16 single ended or 8 differential software selectable
188. y The fuse is self resetting SCANCLK DGND Output Scan Clock This pin pulses once for each A D conversion in the scanning modes when enabled The low to high edge indicates when the input signal can be removed from the input or switched to another signal EXTSTROBE DGND Output External Strobe This output can be toggled under software control to latch signals or trigger events on external devices PFIO TRIG1 DGND Input Output PFI0 Trigger 1 As an input this is either one of the Programmable Function Inputs PFIs or the source for the hardware analog trigger PFI signals are explained in the Timing Connections section later in this chapter The hardware analog trigger is explained in the Analog Trigger section of Chapter 3 Hardware Overview Analog trigger is available only on the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16XE 10 AT AI 16XE 10 and the AT MIO 64E 3 As an output this is the TRIG signal In posttrigger data acquisition sequences a low to high transition indicates the initiation of the acquisition sequence In pretrigger applications a low to high transition indicates the initiation of the pretrigger conversions PFI1 TRIG2 DGND Input Output PFI1 Trigger 2 As an input this is one of the PFIs As an output this is the TRIG2 signal In pretrigger applications a low to high transition indicates the initiation of the posttrigger conversions TRIG2 is not used in

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