Home

UM10375

1. 5 Qu ye r Do oO mn Er lt lt lt 8 gt z O Ske o o ol gt 2 o oA Nn NA N N pee ES O Q O n 2 2 2 0 a 0 E E ge ee A A E rrr or lt zmo terminal 1 SOO 2000s index area due uu PIO2_O0 DTR 1 24 TRST PIO1_2 AD3 CT32B1_MAT1 RESET PIOO0_0 2 23 TDO PIO1_1 AD2 CT32B1_MATO PIOO_1 CLKOUT CT32B0_MAT2 USB_FTOGGLE 3 22 TMS PIO1_0 AD1 CT32B1_CAPO XTALIN 4 21 TDI PIOO_11 AD0 CT32B0_MAT3 ES LPC1342FHN33 a e XTALOUT 5 LPC1343FHN33 20 PIO1_10 AD6 CT16B1_MAT1 Vppiio L6 G9 SWCLK PIO0_10 SCK CT16BO_MAT2 PIO1_8 CT16B1_CAPO 7 18 PIOO_9 MOSI CT16B0_MAT1 SWO PIOO_2 SSEL CT16B0_CAPO 8 17 PIOO_8 MISO CT16B0_MATO o f AAA E VIO ZA XV ae2 582 o E 002aae516 gt 9 D D 5 5 o BOGE EG 2aar Fa o 5 O Q O a 5 172 O gt o S o O a Transparent top view Fig 9 LPC1342 43 HVQFN33 package UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 93 of 290 NXP Semiconductors UM10375 3 LPC131x pin configuration Chapter 8 LPC13xx Pin configuration PIO2_6 PIO2_0 DTR RESET PIO0_0 PIOO_1 CLKOUT CT32B0_MAT2 Vssio XTALIN XTALOUT VDD 10 PIO1_8 CT16B1_CAPO PIOO_2 SSEL CT16B0_CAPO PIO2_7 PIO2_8 Fig 10 LPC1313 LQFP48 package Vss 47 PlO1_7 TXD CT32B0_MAT1 46 PIO1_6 RXD CT32B0_MATO 45 PIO1_5 RTS CT32B0_CAPO 48 PIO3_3 40 PIO1_4 AD5 CT32B1_MAT3 WAKEUP
2. UM10375 LPC13xx Preliminary user manual Rev 00 10 19 October 2009 User manual Document information Info Content Keywords ARM Cortex M3 microcontroller USB LPC1311 LPC1313 LPC1342 LPC1343 Abstract Preliminary user manual founded by Philips NXP Semiconductors U M1 0375 LPC13xx preliminary UM Revision history Rev Date Description 10 lt tbd gt Preliminary LPC13xx user manual version Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 2 of 290 UM10375 Chapter 1 LPC13xx Introductory information Rev 00 10 19 October 2009 User manual 1 Introduction The LPC13xx are ARM Cortex M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption The ARM Cortex M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration The LPC13xx operate at CPU frequencies of up to 72 MHz The ARM Cortex M3 CPU incorporates a 3 stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals The ARM Cortex M3 CPU also includes an internal prefetch unit that supp
3. 258 Table 257 ISP Set Baud Rate command 258 Table 258 ISP Echo command 259 Table 259 ISP Write to RAM command 259 Table 260 ISP Read Memory command 260 Table 261 ISP Prepare sector s for write operation command iii a 260 Table 262 ISP Copy command 00 261 Table 263 ISP Go command ooocooccoococooo oo 261 Table 264 ISP Erase sector command 262 Table 265 ISP Blank check sector command 262 Table 266 ISP Read Part Identification command 262 Table 267 LPC13xx part identification numbers 263 Table 268 ISP Read Boot Code version number command 263 Table 269 ISP Compare command 263 Table 270 ReadUID command 264 Table 271 ISP Return Codes Summary 264 Table 272 IAP Command Summary 266 Table 273 IAP Prepare sector s for write operation COMIMANG eie he iea eia a teens ioe 267 Table 274 IAP Copy RAM to flash command 267 Table 275 1AP Erase Sector s command 268 Table 276 IAP Blank check sector s command 268 Table 277 1AP Read Part Identification command 268 Table 278 IAP Read Boot Code version number command 269 Table 279 IAP Compare command 269 Table 280 Reinvoke ISP o ooocooooooooo o 269 Table 281 IAP ReadUID command 270 Table 282 IAP Status Codes Summary 2
4. Table 107 GPIO configuration Part Package GPIO port 0 GPIO port 1 GPIO port 2 GPIO port 3 Total GPIO pins LPC1311 HVQFN33 PIOO_Oto PIOO_11 PIO1_0OtoPIO1_11 PIO2_0 PIO3_2 PIO3_4 PIO3_5 28 LPC1313 LQFP48 PIOO_O0to PIOO_11 PIO1_0OtoPIO1_11 PIO2_0 to PIO2_11 PIO3_0 to PIO3_5 42 LPC1313 HVQFN33 PIOO_Oto PIOO_11 PIO1_0 to PIO1_11 PIO2_0 PIO3_2 PIO3_4 PIO3_5 28 LPC1342 HVQFN33 PIOO_Oto PIOO_11 PIO1_0 to PIO1_11 PIO2_0 PIO3_2 26 LPC1343 LQFP48 PIOO_0 to PIOO_11 PIO1_0toPIO1_11 PIO2_0 to PIO2_11 PIO3_0 to PIO3_3 40 HVQFN33 PIOO_Oto PIOO_11 PIO1_0toPIO1_11 PIO2_0 PIO3_2 26 2 Introduction 2 1 Features e Digital ports can be configured input output by software e Each individual port pin can serve as external interrupt input pin e Interrupts can be configured on single falling or rising edges and on both edges e Individual interrupt levels can be programmed All GPIO pins are inputs by default e Read and write data operations from to the port pins are maskable 3 Register description Table 108 Register overview GPIO base address port 0 0x5000 0000 port 1 0x5001 0000 port 2 0x5002 0000 port 3 0x5003 0000 Name Access Address offset Description Reset value GPIOnDATA R W 0x0000 to Ox3FFC Port n data register for pins PIOn_0 to 0x00 PIOn_11 as available 4096 locations each data register is 32 bit wide 0x4000 to Ox7FFC reserved GPIOnDIR R W 0x8000 Data direction register for port n
5. 258 Set Baud Rate lt Baud Rate gt lt stop bit gt 258 Echo lt S8tting gt ooooooooo 259 Write to RAM lt start address gt lt number of bytes gt 259 Read Memory lt address gt lt no of bytes gt 259 Prepare sector s for write operation lt start sector number gt lt end sector number gt 260 Copy RAM to flash lt Flash address gt lt RAM address gt lt no Of bytes gt 261 Go lt address gt lt mode gt 261 Erase sector s lt start sector number gt lt end sector number gt 0 200 0 005 262 Chapter 20 LPC13xx Supplementary information 12 10 12 11 12 12 12 13 12 14 12 15 13 13 1 13 2 13 3 13 4 13 5 13 6 13 7 13 8 13 9 13 10 14 15 Blank check sector s lt sector number gt lt end sector number gt 0000 4 eee 262 Read Part Identification number 262 Read Boot code version number 263 Compare lt address1 gt lt address2 gt lt no of bytes gt 263 ReadUID 0oooocccccc 264 ISP Return Codes oo oooooo 264 IAP commands 0occcocccoo 265 Prepare sector s for write operation 266 Copy RAM to flash 267 Erase Sector S 0 0 0 eee eee eee 268 Blank check sector S 268 Read Part Identification number 268 Read Boot code version number 269 Compare lt address1 gt lt address2 gt lt no of byt
6. 33 Table 25 UART clock divider register UARTCLKDIV Table 48 Start logic signal status register 1 STARTSRP1 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 278 of 290 NXP Semiconductors UM10375 Chapter 20 LPC13xx Supplementary information address 0x4004 821C bit description 34 address 0x4004 4040 bit description 63 Table 49 Deep sleep configuration register Table 78 IOCON_PIO2_5 register IOCON_PIO2_5 PDSLEEPCFG address 0x4004 8230 bit address 0x4004 4044 bit description 63 description ovciooinis roca eae 34 Table 79 IOCON_PIO3_5 register IOCON_PIO3_5 Table 50 Wake up configuration register PDAWAKECFG address 0x4004 4048 bit description 64 address 0x4004 8234 bit description 35 Table 80 IOCON_PIOO_6 register IOCON_PIOO_6 Table 51 Power down configuration register PDRUNCFG address 0x4004 404C bit description 64 address 0x4004 8238 bit description 37 Table 81 IOCON_PIO0_7 register IOCON_PIOO_7 Table 52 Device ID register DEVICE_ID address 0x4004 address 0x4004 4050 bit description 65 83F4 bit descripti0N o o 38 Table 82 IOCON_PIO2_9 register IOCON_PIO2_9 Table 53 LPC13xx power and clock control options 39 address 0x4004 4054 bit description 65 Table 54 PLL operating modes 43 Table 83
7. Bit Symbol Value Description Reset Value 7 Divisor 0 Disable access to Divisor Latches 0 Latch 4 Enable access to Divisor Latches Access Bit DLAB 31 Reserved 5 9 UART Line Status Register UOLSR 0x4000 8014 Read Only The UOLSR is a Read Only register that provides status information on the UART TX and RX blocks Table 163 UART Line Status Register UOLSR address 0x4000 8014 Read Only bit description Bit Symbol Value Description Reset Value O Receiver UOLSR 0 is set when the UORBR holds an unread character and 0 Data is cleared when the UART RBR FIFO is empty Ready 0 UORBR is empty RDR UORBR contains valid data 1 Overrun The overrun error condition is set as soon as it occurs AUOLSR 0 Error read clears UOLSR 1 UOLSR 1 is set when UART RSR has a OE new character assembled and the UART RBR FIFO is full In this case the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost O Overrun error status is inactive Overrun error status is active 2 Parity When the parity bit of a received character is in the wrong state a 0 Error parity error occurs A UOLSR read clears UOLSR 2 Time of PE parity error detection is dependent on UOFCR O Note A parity error is associated with the character at the top of the UART RBR FIFO O Parity error status is inactive Parity error status is active 3 Framing When the stop bit of a received character is a logic 0
8. Name Access Address Description Reset offset valuel l TMR32B1IR R W 0x000 Interrupt Register IR The IR can be written to clear interrupts The IR 0 can be read to identify which of five possible interrupt sources are pending TMR32B1TCR R W 0x004 Timer Control Register TCR The TCR is used to control the Timer 0 Counter functions The Timer Counter can be disabled or reset through the TCR TMR32B1TC R W 0x008 Timer Counter TC The 32 bit TC is incremented every PR 1 cycles of 0 PCLK The TC is controlled through the TCR TMR32B1PR R W 0x00C Prescale Register PR When the Prescale Counter below is equal to 0 this value the next clock increments the TC and clears the PC TMR32B1PC R W 0x010 Prescale Counter PC The 32 bit PC is a counter which is incremented 0 to the value stored in PR When the value in PR is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface TMR32B1IMCR R W 0x014 Match Control Register MCR The MCR is used to control if an 0 interrupt is generated and if the TC is reset when a Match occurs TMR32B1MRO R W 0x018 Match Register 0 MRO MRO can be enabled through the MCR to reset 0 the TC stop both the TC and PC and or generate an interrupt every time MRO matches the TC UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 226 of 290 NXP Semiconductors UM10375 Chapter 14 LPC13xx 32 bit counter timer
9. User manual Rev 00 10 19 October 2009 237 of 290 NXP Semiconductors U M1 0375 UM10375_0 5 2 5 3 5 4 Chapter 15 LPC13xx SysTick timer Table 233 System Timer Control and status register STCTRL 0xE000 E010 bit description Bit Symbol Description Reset value 15 3 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 16 COUNTFLAG System Tick counter flag This flag is set when the System Tick 0 counter counts down to 0 and is cleared by reading this register 31 17 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined System Timer Reload value register STRELOAD 0xE000 E014 The STRELOAD register is set to the value that will be loaded into the System Tick Timer whenever it counts down to zero This register is loaded by software as part of timer initialization The STCALIB register may be read and used as the value for STRELOAD if the CPU or external clock is running at the frequency intended for use with the STCALIB value Table 234 System Timer Reload value register STRELOAD 0xE000 E014 bit description Bit Symbol Description Reset value 23 0 RELOAD This is the value that is loaded into the System Tick counter when it 0 counts down to 0 31 24 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is n
10. Bit Symbol Value Description Reset value 0 IntStatus Interrupt status Note that UOIIR O is active low The 1 pending interrupt can be determined by evaluating UOIIR 3 1 O At least one interrupt is pending 1 No interrupt is pending 3 1 Intld Interrupt identification UOIER 3 1 identifies an interrupt 0 corresponding to the UART Rx FIFO All other combinations of UOIER 3 1 not listed below are reserved 100 101 111 011 1 Receive Line Status RLS 010 2a Receive Data Available RDA 110 2b Character Time out Indicator CTI 001 3 THRE Interrupt 000 4 Modem interrupt 5 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 7 6 FIFO Enable These bits are equivalent to UOFCR 0 0 ABEOInt End of auto baud interrupt True if auto baud has finished 0 successfully and interrupt is enabled 9 ABTOInt Auto baud time out interrupt True if auto baud has timed 0 out and interrupt is enabled 31 10 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined Bits UOIIR 9 8 are set by the auto baud function and signal a time out or end of auto baud condition The auto baud interrupt conditions are cleared by setting the corresponding Clear bits in the Auto baud Control Register If the IntStatus bit is one and no interrupt is pending and the Intld bits will be zero If the IntStatus is 0
11. description Bit Symbol Value Description Reset value 1 0 SEL USB PLL clock source 0x00 00 Reserved 01 System oscillator 10 Reserved 11 Reserved 31 22 Reserved 0x00 USB PLL clock source update enable register This register updates the clock source of the USB PLL with the new input clock after the USBPLLCLKSEL register has been written to In order for the update to take effect at the USB PLL input first write a zero to the USBPLLUEN register and then write a one to USBPLLUEN Remark The system oscillator must be selected in the USBPLLCLKSEL register in order to use the USB PLL and this register must be toggled to update the USB PLL clock with the system oscillator NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 20 of 290 NXP Semiconductors U M1 0375 UM10375_0 5 15 5 16 5 17 Chapter 3 LPC13xx System configuration Table 19 USB PLL clock source update enable register USBPLLUEN address 0x4004 804C bit description Bit Symbol Value Description Reset value 0 ENA Enable USB PLL clock source update 0x0 0 No change 1 Update clock source 31 1 Reserved 0x00 Main clock source select register This register selects the main system clock which can be either any input to the system PLL the output from the system PLL sys_pllclkout or the watchdog or IRC oscillators directly The main system clock clocks the core the peripherals and memories and
12. Input Start Address Address from where data bytes are to be read This address should be a word boundary Number of Bytes Number of bytes to be read Count should be a multiple of 4 Return Code CMD SUCCESS followed by lt actual data UU encoded gt ADDR_ERROR Address not on word boundary ADDR_NOT_MAPPED COUNT_ERROR Byte count is not a multiple of 4 PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to read data from RAM or flash memory This command is blocked when code read protection is enabled Example R 268435456 4 lt CR gt lt LF gt reads 4 bytes of data from address 0x1000 0000 Prepare sector s for write operation lt start sector number gt lt end sector number gt This command makes flash write erase operation a two step process Table 262 ISP Prepare sector s for write operation command Command P Input Start Sector Number End Sector Number Should be greater than or equal to start sector number Return Code CMD SUCCESS BUSY INVALID_SECTOR PARAM_ERROR Description This command must be executed before executing Copy RAM to flash or Erase Sector s command Successful execution of the Copy RAM to flash or Erase Sector s command causes relevant sectors to be protected again The boot block can not be prepared by this command To prepare a single sector use the same Start and End sector numbers Example P 0 0 lt CR gt lt LF gt prepares the
13. Interrupts during ISP The boot block interrupt vectors located in the boot block of the flash are active after any reset Interrupts during IAP The on chip flash memory is not accessible during erase write operations When the user application code starts executing the interrupt vectors from the user flash area are active The user should either disable interrupts or ensure that user interrupt vectors are active in RAM and that the interrupt handlers reside in RAM before making a flash erase write IAP call The IAP code does not use or disable interrupts RAM used by ISP command handler ISP commands use on chip RAM from 0x1000 017C to 0x1000 025B The user could use this area but the contents may be lost upon reset Flash programming commands use the top 32 bytes of on chip RAM The stack is located at RAM top 32 bytes The maximum stack usage is 256 bytes and grows downwards RAM used by IAP command handler Flash programming commands use the top 32 bytes of on chip RAM The maximum stack usage in the user allocated stack space is 128 bytes and grows downwards 8 USB communication protocol UM10375_0 The LPC134x is enumerated as a Mass Storage Class MSC device to a PC or another embedded system The MSC device presents an easy integration with the PC s Windows or Linux operating system The LPC134x flash memory space is represented as a drive in the host file system The entire available user flash is mapped to a file
14. NXP Semiconductors U M1 0375 Chapter 10 LPC13xx UART The interrupt interface contains registers UOIER and UOIIR The interrupt interface receives several one clock wide enables from the UOTX and UORX blocks Status information from the UOTX and UORX is stored in the UOLSR Control information for the UOTX and UORX is stored in the UOLCR 7 UOTHR ig UOTSR a IQ NBAUDOUT RCLK E UORBR 7 UORSR Bi oe E UOIIR UOSCR PA 2 0 PSEL PSTB PWRITE APB RPI 0 INTERFACE DDIS AR MR PCLK Fig 19 UART block diagram UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 154 of 290 UM10375 Chapter 11 LPC13xx SSP Rev 00 10 19 October 2009 User manual 1 How to read this chapter The SSP block is identical for all LPC13xx parts 2 Features e Compatible with Motorola SPI 4 wire TI SSI and National Semiconductor Microwire buses e Synchronous Serial Communication e Supports master or slave operation e Eight frame FIFOs for both transmit and receive e 4 bit to 16 bit frame 3 General description The SSP is a Synchronous Serial Port SSP controller capable of operation on a SPI 4 wire SSI or Microwire bus It can interact with multiple masters and slaves on the bus Only a single master and a single slave can communicate on the bus during a given data transfer Data transfers are in principle full duplex with fr
15. PIO01_8 CT16B1_CAPO PIO1_9 CT16B1_MATO UM10375_0 Pin 19111 2115 22181 2313 24131 25 5 2613 30H 311 3211 71 1211 Type 1 0 Description SWCLK Serial wire clock and test clock TCK for JTAG interface PIO0_10 General purpose digital input output pin SCK Serial clock for SSP CT16B0_MAT2 Match output 2 for 16 bit timer 0 TDI Test Data In for JTAG interface PIO0_11 General purpose digital input output pin ADO A D converter input 0 CT32B0_MAT3 Match output 3 for 32 bit timer 0 TMS Test Mode Select for JTAG interface PIO1_0 General purpose digital input output pin AD1 A D converter input 1 CT32B1_CAPO Capture input 0 for 32 bit timer 1 TDO Test Data Out for JTAG interface PIO1_1 General purpose digital input output pin AD2 A D converter input 2 CT32B1_MATO Match output O for 32 bit timer 1 TRST Test Reset for JTAG interface PIO1_2 General purpose digital input output pin AD3 A D converter input 3 CT32B1_MAT1 Match output 1 for 32 bit timer 1 SWDIO Serial wire debug input output PIO1_3 General purpose digital input output pin AD4 A D converter input 4 CT32B1_MAT2 Match output 2 for 32 bit timer 1 PIO1_4 General purpose digital input output pin AD5 A D converter input 5 CT32B1_MAT3 Match output 3 for 32 bit timer 1 WAKEUP Deep power down mode wak
16. The clock to the 12C bus interface PCLK_12C is provided by the system clock see Figure 3 3 This clock can be disabled through bit 5 in the AHBCLKCTRL register Table 3 23 for power savings 7 Register description Table 186 Register overview 12C base address 0x4000 0000 Name Access Address Description Reset offset valuel I2CONSET R W 0x000 12C Control Set Register When a one is written to a bit of this register 0x00 the corresponding bit in the IC control register is set Writing a zero has no effect on the corresponding bit in the 12C control register I2STAT RO 0x004 12C Status Register During 12C operation this register provides detailed OxF8 status codes that allow software to determine the next action needed I2DAT R W 0x008 12C Data Register During master or slave transmit mode data to be 0x00 transmitted is written to this register During master or slave receive mode data that has been received may be read from this register I2ADRO R W 0x00C 12C Slave Address Register 0 Contains the 7 bit slave address for 0x00 operation of the 12C interface in slave mode and is not used in master mode The least significant bit determines whether a slave responds to the General Call address I2SCLH R W 0x010 SCH Duty Cycle Register High Half Word Determines the high time of 0x04 the 12C clock I2SCLL R W 0x014 SCL Duty Cycle Register Low Half Word Determines the low time of 0x04 the 12C clock I2nSCLL and I2nSC
17. UM10375_0 See Figure 3 3 for an overview of the LPC13xx Clock Generation Unit CGU The LPC131x include three independent oscillators These are the system oscillator the Internal RC oscillator IRC and the Watchdog oscillator Each oscillator can be used for more than one purpose as required in a particular application Following reset the LPC111x will operate from the Internal RC oscillator until switched by software This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency The SYSAHBCLKCTRL register gates the system clock to the various peripherals and memories UART SSP0 1 the SysTick timer and the ARM trace clock have individual clock dividers to derive peripheral clocks from the main clock The USB clock if available and the watchdog clock can be derived from the oscillator output or the main clock The main clock and the clock outputs from the IRC the system oscillator and the watchdog oscillator can be observed directly on the CLKOUT pin NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 10 of 290 NXP Semiconductors UM10375 Chapter 3 LPC13xx System configuration sys_ahb_cik 0 system main clock CLOCK system clock DIVIDER sys_ahb_clk 1 ROM AHBCLKCTRL ROM enable E sys_ahb_clk 16 IOCON AHBCLKCTRL IOCON enable 4
18. 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved 2 Table 67 IOCON_PIO1_8 register IOCON_PIO1_8 address 0x4004 4014 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO1_8 001 Selects function CT16B1_CAPO 010to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved 7 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 59 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 68 IOCON_PIOO_2 register IOCON_PIOO_2 address 0x4004 401C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIOO_2 001 Selects function SSEL 010 Selects function CT16B0_CAPO 011to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 z
19. 120 Figure 8 9 Table 8 120 Figure 8 8 Table 8 119 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 91 of 290 NXP Semiconductors UM10375 2 LPC134x pin configuration Chapter 8 LPC13xx Pin configuration Vss 47 PlO1_7 TXD CT32B0_MAT1 48 PIO3_3 PIO2_6 PIO2_0 DTR RESET PIOO0_0 3T32B0_MAT2 USB_FTOGGLE Vssio XTALIN XTALOUT VDD 10 PIO1_8 CT16B1_CAPO PIOO_2 SSEL CT16B0_CAPO 46 PIO1_6 RXD CT32B0_MATO 45 PIO1_5 RTS CT32B0_CAPO 40 PIO1_4 AD5 CT32B1_MAT3 WAKEUP 42 PIO1_11 AD7 44 Vop av3 43 PIO3_2 41 LPC1343FBD48 39 SWDIO PIO1_3 AD4 CT32B1_MAT2 38 PlO2_3 RI 37 PIO3_1 PIO3_0 TRST PIO1_2 AD3 CT32B1_MAT1 TDO PIO1_1 AD2 CT32B1_MATO TMS PIO1_0 AD1 CT32B1_CAPO TD PIOO_11 ADO CT32B0_MAT3 PIO2_11 SCK PIO1_10 AD6 CT16B1_MAT1 SWCLK PIOO_10 SCK CT16B0_MAT2 PIOO_9 MOSI CT16B0_MAT1 SWO PIOO_8 MISO CT16B0_MATO PIO2_7 PIO2_2 DCD PIO2_8 PIO2_10 O Y jLo oj mifo DO O T N M lt ALE LE LEI LE LE LEI LS LS LS LSS 002aae505 enracorsan xn o oO EN E gagozala F5S gt 7702 gt 002pR al ca o o s a lo ol a o2068 gt ree o 2 aar 2a Sp E O o o O O a oo AS 8 a o Fig 8 LPC1343 LQFP48 package UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 92 of 290 NXP Semiconductors U M1 0375 Chapter 8 LPC13xx Pin configuration
20. 5 4 7 6 9 8 11 10 31 12 Symbol EMO EM1 EM2 EM3 EMCO EMC1 EMC2 EMC3 Description External Match 0 This bit reflects the state of output CT16BO_MAT0 CT16B1_MATO whether or not this output is connected to its pin When a match occurs between the TC and MRO this bit can either toggle go LOW go HIGH or do nothing Bits EMR 5 4 control the functionality of this output This bit is driven to the CT16BO_MAT0 CT16B1_MATO pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH External Match 1 This bit reflects the state of output CT16BO_MAT1 CT16B1_MAT1 whether or not this output is connected to its pin When a match occurs between the TC and MR1 this bit can either toggle go LOW go HIGH or do nothing Bits EMR 7 6 control the functionality of this output This bit is driven to the CT16BO_MAT1 CT16B1_MAT1 pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH External Match 2 This bit reflects the state of output CT16B0_MAT2 or match channel 2 whether or not this output is connected to its pin When a match occurs between the TC and MR2 this bit can either toggle go LOW go HIGH or do nothing Bits EMR 9 8 control the functionality of this output This bit is driven to the CT16B1_MATO pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH Note that on counter timer 0 this match channel is not pinned out External Match
21. SLA Slave Address El From master to slave O From slave to master Fig 31 A Master Receiver switches to Master Transmitter after sending Repeated START 8 3 Slave Receiver mode In the slave receiver mode data bytes are received from a master transmitter To initialize the slave receiver mode write any of the Slave Address registers 12ADRO 3 and write the 12C Control Set register I2CONSET as shown in Table 12 200 Table 200 I1I2CONSET used to configure Slave mode Bit 7 6 5 4 3 2 1 0 Symbol I2EN STA STO Sl AA Value 1 0 0 0 1 12EN must be set to 1 to enable the 12C function AA bit must be set to 1 to acknowledge its own slave address or the General Call address The STA STO and SI bits are set to 0 After I2ADR and I2CONSET are initialized the 12C interface waits until it is addressed by its own address or general address followed by the data direction bit If the direction bit is 0 W it enters slave receiver mode If the direction bit is 1 R it enters slave transmitter mode After the address and direction bit have been received the SI bit is set and a valid status code can be read from the Status register I2STAT Refer to Table 12 207 for the status codes and actions 0 write 1 read data transferred n Bytes Acknowledge A Acknowledge SDA low A Not acknowledge SDA high S START condition P STOP condition RS Repeated START condition from Mas
22. USBDevIntClr 0x20 CurFrameNum CurFrameNum Chapter 9 LPC13xx USB device coniroller CMD_CODE 0xF5 CMD_PHASE 0x02 Read Wait for CDFULL Read Frame number MSB byte Clear CDFULL interrupt bit Temp lt lt 8 Here is an example of the Set Address command writing 1 byte USBDevIntClr 0x10 USBCmdCode 0x00D00500 USBDevIntClr 0x10 USBCmdCode 0x008A0100 USBDevIntClr 0x10 while USBDevIntSt 0x10 while USBDevIntSt 0x10 Clear CCEMPTY CMD_CODE 0xD0 CMD_PHASE 0x05 Command Wait for CCEMPTY Clear CCEMPTY CMD_WDATA 0x8A DEV_EN 1 DEV_ADDR 0xA CMD_PHASE 0x01 Write Wait for CCEMPTY Clear CCEMPTY Table 139 SIE command code table Command name Device commands Set Address Configure Device Set Mode Read Interrupt Status Read Current Frame Number Read Chip ID Set Device Status Get Device Status Get Error Code Endpoint Commands Select Endpoint Select Endpoint Clear Interrupt Set Endpoint Status Clear Buffer Validate Buffer Recipient Code Hex Data phase Device DO Write 1 byte Device D8 Write 1 byte Device F3 Write 1 byte Device F4 Read 1 or 2 bytes Device F5 Read 1 or 2 bytes Device FD Read 2 bytes Device FE Write 1 byte Device FE Read 1 byte Device FF Read 1 byte Endpoint 0 00 Read 1 byte optional Endpoint 1 01 Read 1 byte optional Endpoint xx XX Read 1 byte optional End
23. eee 207 11 4 2C interrupt routine 0 000 203 11 8 8 State 0x98 eee 207 11 5 Non mode specific states 203 11 8 9 State OXAD ooooooocooooooooooooo 208 WBA State 0X00 ore2o2 dag eeeor thier dees 203 11 9 Slave Transmitter states 208 11 5 2 Master States oooooccccccccniacoos 203 11 9 1 State OxXA8 1 eee eee 208 11 5 3 State 0000s sccucsStaedntossieneeetes 203 11 9 2 State OxBO 6 1 208 11 5 4 State OO Vacas 204 11 9 3 State OXB8 6 eee eee 208 11 6 Master Transmitter stateS 204 11 9 4 State OxCO see eee 209 11 6 14 State WB arcas 204 11 9 5 State OxCB coccion 209 11 6 2 State 0X20 iii de 204 Chapter 13 LPC13xx 16 bit counter timer CT16B 1 How to read this chapter 210 7 6 Match Control Register TMR16BOMCR and 2 FRAUNGS neon be res ovens de 210 TMRIGBIMCR e coo cio ino acia ai 214 3 ApplicationS oocooooonoorommo m0 77 Match Registers TMR16B0MR0 1 2 3 4 Descripti0N ooooooomommmm o 210 A A C0181 C120 atang ek TMR16B1MRO0 1 2 3 addresses 0x4001 5 Pin descripti0N o oooooommo 211 0018 1C 20 24 0 cee eee 215 6 Clocking and power control 211 7 8 Capture Control Register TMR16BOCCR and 7 Register description 211 TMR16B1CCR seca aces soso 216 7 1 Interrupt Register TMR16BOIR and TMR16B1IR 7 9 Capture Register CT16B0CR0 address 0x4000 213 C02C and
24. lock criterion for more than eight consecutive input clock periods the lock output switches from low to high A single too large phase difference immediately resets the counter and causes the lock signal to drop if it was high Requiring eight phase measurements in a row to be below a certain figure ensures that the lock detector will not indicate lock until both the phase and frequency of the input and feedback clocks are very well aligned This effectively prevents false lock indications and thus ensures a glitch free lock signal Direct output mode In normal operating mode with the DIRECT bit set to 0 the CCO clock is divided by 2 4 8 or 16 depending on the value on the PSEL bits giving an output clock with a 50 duty cycle lf a higher output frequency is needed the CCO clock can be sent directly to the output by setting direct to 1 As the CCO does not directly generate a 50 duty cycle clock the output clock duty cycle in this mode can deviate from 50 Power down control To reduce the power consumption when the PLL clock is not needed a Power down mode has been incorporated This mode is enabled by setting the SYS_PLL_PD or USB_PLL_PD bits to one in the Power down configuration register Table 3 51 In this mode the internal current reference will be turned off the oscillator and the phase frequency detector will be stopped and the dividers will enter a reset state While in Power down mode the lock output
25. 0 Disable 1 Enable 6 5 Reserved 1 31 7 Reserved UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 75 of 290 NXP Semiconductors UM10375 Chapter 5 LPC13xx I O configuration Table 95 IOCON_PIO3_1 register IOCON_PIO3_1 address 0x4004 4088 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO3_1 001to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 z E Reserved 1 31 7 Reserved z Table 96 IOCON_PIO2_3 register IOCON_PIO2_3 address 0x4004 408C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO2_3 001 Selects function RI 010to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 76 of 290 NXP Semiconductors U M1 0375 UM10375_0 Chapter 5 LPC13xx I O configuration Table 97
26. 001 Selects function PIOO_10 010 Selects function SCK only if pin SWCLK PIOO_10 SCK CT16B0_MAT2 selected in Table 5 105 011 Selects function CT16BO_MAT2 100 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor control 10 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 70 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 88 IOCON_PIO1_10 register IOCON_PIO1_10 address 0x4004 406C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO1_10 001 Selects function AD6 010 Selects function CT16B1_MAT1 011to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 gt Reserved 1 7 ADMODE Select Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 31 8 a Reserved Table 89 IOCON_PIO2_11 register IOCON_PIO2_11 address 0x4004 4070 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 00
27. 0x1000 0800 to the flash address 0 Go lt address gt lt mode gt Table 264 ISP Go command Command Input Return Code Description Example G Address Flash or RAM address from which the code execution is to be started This address should be on a word boundary Mode T Execute program in Thumb Mode A Execute program in ARM mode CMD_SUCCESS ADDR_ERROR ADDR_NOT_MAPPED CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED This command is used to execute a program residing in RAM or flash memory It may not be possible to return to the ISP command handler once this command is successfully executed This command is blocked when code read protection is enabled G 0 A lt CR gt lt LF gt branches to address 0x0000 0000 in ARM mode O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 263 of 290 NXP Semiconductors U M1 0375 Chapter 18 LPC13xx Flash memory programming firmware 12 9 Erase sector s lt start sector number gt lt end sector number gt Table 265 ISP Erase sector command Command E Input Start Sector Number End Sector Number Should be greater than or equal to start sector number Return Code CMD_SUCCESS BUSY INVALID_SECTOR SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to erase one or more sector s of on chip flash memory The boo
28. 0x38 0x68 0x78 and OxBO see Figure 12 37 and Figure 12 38 If the STA flag in 12CON is set by the routines which service these states then if the bus is free again a START condition state 0x08 is transmitted without intervention by the CPU and a retry of the total serial transfer can commence 10 11 Forced access to the I2C bus In some applications it may be possible for an uncontrolled source to cause a bus hang up In such situations the problem may be caused by interference temporary interruption of the bus or a temporary short circuit between SDA and SCL UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 201 of 290 NXP Semiconductors U M1 0375 10 12 10 13 UM10375_0 Chapter 12 LPC13xx I2C bus interface If an uncontrolled source generates a superfluous START or masks a STOP condition then the 12C bus stays busy indefinitely If the STA flag is set and bus access is not obtained within a reasonable amount of time then a forced access to the 12C bus is possible This is achieved by setting the STO flag while the STA flag is still set No STOP condition is transmitted The 12C hardware behaves as if a STOP condition was received and is able to transmit a START condition The STO flag is cleared by hardware see Figure 12 42 12C bus obstructed by a LOW level on SCL or SDA An I2C bus hang up can occur if either the SDA or SCL line is held LOW by any device on the bus If t
29. 1 6 MHz 6 270 kHz Remark Any setting of the FREQSEL bits will yield a Fclkana value within 25 of the listed frequency value Table 13 Watchdog oscillator control register WDTOSCCTRL address 0x4004 8024 bit description Bit Symbol Value Description Reset value 4 0 DIVSEL Select divider for Fclkana to create wdt_osc_clk 0x000 00000 2 00001 4 00010 6 11111 64 8 5 FREQSEL Select watchdog oscillator analog output frequency 0x05 Fclkana 0001 0 5 MHz 0010 0 8 MHz NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 17 of 290 NXP Semiconductors U M1 0375 Chapter 3 LPC13xx System configuration Table 13 Watchdog oscillator control register WDTOSCCTRL address 0x4004 8024 bit description Bit Symbol Value Description Reset value 0011 1 1 MHz 0100 1 4 MHz 0101 1 6 MHz Reset value 0110 1 8 MHz 0111 2 0 MHz 1000 2 2 MHz 1001 2 4 MHz 1010 2 6 MHz 1011 2 7 MHz 1100 2 9 MHz 1101 3 1 MHz 1110 3 2 MHz 1111 3 4 MHz 31 9 Reserved 0x00 5 9 Internal resonant crystal control register This register is used to trim the on chip 12 MHz oscillator The trim value is factory preset and written by the boot code on start up Table 14 Internal resonant crystal control register IRCCTRL address 0x4004 8028 bit description Bit Symbol Value Description Reset value 7 0 TRIM Trim value 0x1000 0000 then flash will reprogram 31 9 Reserved 0x00 UM10375_
30. 180 Format of Slave Transmitter mode 181 12C serial interface block diagram 182 Arbitration procequre oooccoocccoooo 184 Serial clock synchronization 184 Format and states in the Master Transmitter mode 189 Format and states in the Master Receiver mode 190 Format and states in the Slave Receiver mode 191 Format and states in the Slave Transmitter mode 192 Simultaneous Repeated START conditions from two IMASTOMS o ia eos gavel ala Sm ie wee Geena 200 Forced access to a busy I2C bus 201 Recovering from a bus obstruction caused by a LOW level on SDA 20000000 201 Sample PWM waveforms with a PWM cycle length Fig 45 Fig 46 Fig 47 Fig 48 Fig 49 Fig 50 Fig 51 Fig 52 Fig 53 Fig 54 Fig 55 of 100 selected by MR3 and MAT3 0 enabled as PWM outputs by the PWCON register 220 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled 220 A timer cycle in which PR 2 MRx 6 and both interrupt and stop on match are enabled 16 bit counter timer block diagram 221 Sample PWM waveforms with a PWM cycle length of 100 selected by MR3 and MAT3 0 enabled as PWM outputs by the PWCON register 232 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled 232 A timer cycle in which PR 2 MRx 6 and both interrupt and stop on match are enabled 232
31. 2 Set the system oscillator control register SYSOSCCTRL see Table 3 12 to 0 3 Enable the system oscillator by clearing bit 5 in the PDAWAKECFG register see Table 3 50 then wait 200 us for system oscillator to stabilize 4 Select the system clock source by setting 0x01 use system oscillator in SYSPLLCLKSEL register see Table 3 16 5 Update the clock source by setting 1 in SYSPLLUEN register see Table 3 17 address 0x4004 8044 register and wait until clock source is updated O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 124 of 290 NXP Semiconductors U M1 0375 Chapter 9 LPC13xx USB device controller Boost system PLL to 192 MHz and then divide by 4 M 4 P 2 to obtain the 48 MHz main clock If the main clock is not 48 MHz then the USB PLL has to be used as USB clock Enable the main system PLL by clearing bit 7 in PDAWAKECFG see Table 3 50 then wait until the PLL clock is locked If the USB PLL is used as the USB clock do the following extra step Configure USB PLL identically to the System PLL and select system clock source by setting 0x01 use system oscillator in USBPLLCLKSEL see Table 3 18 address 0x4004 8048 register 9 Enable USB clock by clearing bit 8 in PDCTRL 11 12 Set USB clock by setting USBCLKSEL see Table 3 28 address 0x4004 80C0 to a 0x0 if USB PLL is used b 0x1 if main clock is used Update clock source by set
32. 34131 O TDO Test Data Out for JTAG interface AD2 CT32B1_MATO 1 0 PIO1_1 General purpose digital input output pin AD2 A D converter input 2 O CT32B1_MATO Match output O for 32 bit timer 1 TRST PIO1_2 3581 TRST Test Reset for JTAG interface AD3 CT32B1_MAT1 1 0 PIO1_2 General purpose digital input output pin AD3 A D converter input 3 O CT32B1_MAT1 Match output 1 for 32 bit timer 1 SWDIO PIO1_3 AD4 3915 1 0 SWDIO Serial wire debug input output CT32B1_MAT2 1 0 PIO1_3 General purpose digital input output pin AD4 A D converter input 4 O CT32B1_MAT2 Match output 2 for 32 bit timer 1 PIO1_4 AD5 4013 1 0 PIO1_4 General purpose digital input output pin CT32B1_MAT3 WAKEUP AD5 A D converter input 5 O CT32B1_MAT3 Match output 3 for 32 bit timer 1 WAKEUP Deep power down mode wake up pin PIO1_5 RTS 4511 1 0 PIO1_5 General purpose digital input output pin CT32B0_CAPO O RTS Request To Send output for UART CT32B0_CAPO Capture input O for 32 bit timer 0 PIO01_6 RXD 4611 1 0 PIO1_6 General purpose digital input output pin CT32B0_MATO RXD Receiver input for UART O CT32B0_MATO Match output 0 for 32 bit timer 0 PIO01_7 TXD 471 1 0 PIO1_7 General purpose digital input output pin CT32B0_MAT1 O TXD Transmitter output for UART O CT32B0_MAT1 Match output 1 for 32 bit timer 0 PIO1_8 CT16B1_CAPO 9E 1 0 PIO1_8 Gener
33. All rights reserved User manual Rev 00 10 19 October 2009 222 of 290 NXP Semiconductors U M1 0375 Chapter 13 LPC13xx 16 bit counter timer CT16B 9 Architecture UM10375_0 The block diagram for counter timerO and counter timer1 is shown in Figure 13 47 MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER CONTROL MATn 2 0 INTERRUPT CAPO INTERRUPT REGISTER STOP ON MATCH RESET ON MATCH LOAD 3 0 TIMER COUNTER CE CAPTURE REGISTER O TCI PCLK PRESCALE COUNTER reset enable MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER Fig 47 16 bit counter timer block diagram O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 223 of 290 UM10375 Chapter 14 LPC13xx 32 bit counter timer CT32B Rev 00 10 19 October 2009 User manual 1 How to read this chapter The 32 bit timer blocks are identical for all LPC13xx parts 2 Features 3 Applications Two 32 bit counter timers with a programmable 32 bit prescaler Counter or Timer operation One 32 bit capture channel that can take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt Four 32 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer on match
34. At these points a service routine must be executed to continue or complete the serial transfer These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software When a serial interrupt routine is entered the status code in I2STAT is used to branch to the appropriate service routine For each status code the required software action and details of the following serial transfer are given in tables from Table 12 205 to Table 12 209 Master Transmitter mode In the master transmitter mode a number of data bytes are transmitted to a slave receiver see Figure 12 37 Before the master transmitter mode can be entered I2CON must be initialized as follows Table 202 IZCONSET used to initialize Master Transmitter mode Bit 7 6 5 4 3 2 1 0 Symbol 12EN STA STO SI AA Value 1 0 0 0 x The 12C rate must also be configured in the I2SCLL and I2SCLH registers I2EN must be set to logic 1 to enable the 12C block If the AA bit is reset the 12C block will not acknowledge its own slave address or the General Call address in the event of another device becoming master of the bus In other words if AA is reset the 12C interface cannot enter a slave mode STA STO and SI must be reset The master transmitter mode may now be entered by setting the STA bit The 12C logic will now test the 12C bus and generate a START condition as soon as the bus becomes free When
35. Because of the A or a ASCII coding A 0x41 a 0x61 the UART Rx pin sensed start bit and the LSB of the expected character are delimited by two falling edges When the UOACR Start bit is set the auto baud protocol will execute the following phases 1 On UOACR Start bit setting the baud rate measurement counter is reset and the UART UORSR is reset The UORSR baud rate is switched to the highest rate 2 A falling edge on UART Rx pin triggers the beginning of the start bit The rate measuring counter will start counting UART_PCLK cycles 3 During the receipt of the start bit 16 pulses are generated on the RSR baud input with the frequency of the UART input clock guaranteeing the start bit is stored in the UORSR 4 During the receipt of the start bit and the character LSB for Mode 0 the rate counter will continue incrementing with the pre scaled UART input clock UART_PCLK 5 If Mode O the rate counter will stop on next falling edge of the UART Rx pin If Mode 1 the rate counter will stop on the next rising edge of the UART Rx pin 6 The rate counter is loaded into UODLM UODLL and the baud rate will be switched to normal operation After setting the UODLM UODLL the end of auto baud interrupt UOIIR ABEOInt will be set if enabled The UORSR will now continue receiving the remaining bits of the A a character UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 145
36. CT32B Table 223 Register overview 32 bit counter timer 1 CT32B1 base address 0x4001 8000 continued Name Access Address Description Reset offset valuel TMR32B1MR1 R W 0x01C Match Register 1 MR1 See MRO description 0 TMR32B1MR2 R W 0x020 Match Register 2 MR2 See MRO description 0 TMR32B1MR3 R W 0x024 Match Register 3 MR3 See MRO description 0 TMR32B1CCR R W 0x028 Capture Control Register CCR The CCR controls which edges of the 0 capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place TMR32B1CRO RO 0x02C Capture Register 0 CRO CRO is loaded with the value of TC when 0 there is an event on the CT32B1_CAPO input TMR32B1EMR R W 0x03C External Match Register EMR The EMR controls the match function 0 and the external match pins CT32B1_MAT 3 0 0x040 reserved z 0x06C TMR32B1CTCR R W 0x070 Count Control Register CTCR The CTCR selects between Timer and 0 Counter mode and in Counter mode selects the signal and edge s for counting TMR32B1PWMC R W 0x074 PWM Control Register PWMCON The PWMCON enables PWM 0 mode for the external match pins CT32B1_MATT 3 0 1 Reset value reflects the data stored in used bits only lt does not include reserved bits content 7 1 Interrupt Register TMR32BOIR and TMR32B1I R The Interrupt Register consists of four bits for the match interrupts and one bit for the capture interrupts If an interru
37. Connection of interrupt sources to the Vectored Interrupt Controller Exception Vector Number Offset 42 OxA8 43 OxAC 44 0xBO 45 0xB4 46 0xB8 47 0xBC 48 OxCO 49 0xC4 50 0xC8 51 OxCC 52 53 0xD4 54 0xD8 55 0xDC 56 OxEO Function CT16B1 CT32B0 CT32B1 SSP UART USB IRQ interrupt USB FIQ interrupt ADC WDT BOD PIO_3 PIO_2 PIO_1 PIO_O Flag s Match 0 1 Capture 0 Match 0 3 Capture 0 Match 0 3 Capture 0 Tx FIFO half empty Rx FIFO half full Rx Timeout Rx Overrun Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CT Modem Control Change End of Auto Baud ABEO Auto Baud Time Out ABTO USB low priority interrupt USB high priority interrupt A D Converter end of conversion Watchdog interrupt WDINT Brown out detect Reserved GPIO interrupt status of port 3 GPIO interrupt status of port 2 GPIO interrupt status of port 1 GPIO interrupt status of port 0 1 See Section 3 1 for wake up pins not used in the HVQFN package O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 84 of 290 l UM10375 Chapter 7 LPC13xx General Purpose l O GPIO Rev 00 10 19 October 2009 How to read this chapter User manual The number of GPIO pins available on each port depends on the LPC13xx part and the package See Table 7 107 for available GPIO pins
38. Contains individual interrupt enable 0x00 when bits for the 7 potential UART interrupts DLAB 0 UOIIR RO 0x008 Interrupt ID Register Identifies which interrupt s are pending 0x01 UOFCR WO 0x008 FIFO Control Register Controls UART FIFO usage and modes 0x00 UOLCR R W 0x00C Line Control Register Contains controls for frame formatting 0x00 and break generation UOMCR R W 0x010 Modem control register 0x00 UOLSR RO 0x014 Line Status Register Contains flags for transmit and receive 0x60 status including line errors UOMSR RO 0x018 Modem status register 0x00 UOSCR R W 0x01C Scratch Pad Register Eight bit temporary storage for software 0x00 UOACR R W 0x020 Auto baud Control Register Contains controls for the 0x00 auto baud feature 0x024 Reserved UOFDR R W 0x028 Fractional Divider Register Generates a clock input for the 0x10 baud rate divider 0x02C Reserved UOTER R W 0x030 Transmit Enable Register Turns off UART transmitter for use 0x80 with software flow control 0x034 Reserved 0x048 UORS485CTRL R W 0x04C RS 485 ElA 485 Control Contains controls to configure various 0x00 aspects of RS 485 ElA 485 modes UOADRMATCH R W 0x050 RS 485 ElA 485 address match Contains the address match 0x00 value for RS 485 ElA 485 mode UORS485DLY R W 0x054 RS 485 ElA 485 direction control delay 0x00 UOFIFOLVL RO 0x058 FIFO Level register Provides the current fill levels of the 0x00
39. IOCON_PIO2_10 register IOCON_PIO2_10 Table 55 PLL frequency parameters 44 address 0x4004 4058 bit description 66 Table 56 Register overview PMU base address 0x4003 Table 84 IOCON_PIO2_2 register IOCON_PIO2_2 8000 iuris a aa 47 address 0x4004 405C bit description 66 Table 57 Power control register PCON address 0x4003 Table 85 IOCON_PIOO_8 register IOCON_PIOO_8 8000 bit description 47 address 0x4004 4060 bit description 67 Table 58 General purpose registers 0 to 3 GPREGO Table 86 IOCON_PIOO_9 register IOCON_PIOO_9 GPREGS3 address 0x4003 8004 to 0x4003 8010 address 0x4004 4064 bit description 67 bit description ooooooooomoo 48 Table 87 IOCON_JTAG_TCK_PIO0_10 register Table 59 General purpose register 4 GPREG4 address IOCON_JTAG_TCK_PIO0_10 address 0x4004 0x4003 8014 bit description 48 4068 bit description 68 Table 60 1 O register configuration unused registers and Table 88 IOCON_PIO1_10 register IOCON_PIO1_ 10 FUNCIONS 00 bare ee do ee Re 50 address 0x4004 406C bit description 69 Table 61 Register overview I O configuration block base Table 89 IOCON_PIO2_11 register IOCON_PIO2_11 address 0x4004 4000 52 address 0x4004 4070 bit description 69 Table 62 I O configuration registers ordered by port number Table 90 IOCON_JTAG_TDI_PIOO_11 register 54 IOC
40. IOCON_SWDIO_PIO1_3 register IOCON_SWDIO_PIO1_3 address 0x4004 4090 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function SWDIO 001 Selects function PIO1_3 010 Selects function AD4 011 Selects function CT32B1_MAT2 100 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 7 ADMODE Select Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 31 8 Reserved NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 77 of 290 NXP Semiconductors UM10375 UM10375_0 Chapter 5 LPC13xx I O configuration Table 98 IOCON_PIO1_4 register IOCON_PIO1_4 address 0x4004 4094 bit description Bit Symbol 2 0 FUNCL 4 3 MODE 5 HYS 6 2 7 ADMODE 31 8 Value 000 001 010 100 to 011 00 01 10 11 Description Selects pin function Selects function PIO1_4 Selects function AD5 Selects function CT32B1_MAT3 Reserved Selects function mode on chip pull up pull down resistor control Inactive no pull down pull up resistor enabled Pull down resistor enabled Pull up resistor enabled Repeater mode Hysteresis Disable Enable Reserved Select Analog Digital mo
41. MS 1 If it is 1 this blocks this SSP controller from driving the transmit data line MISO 7 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 6 3 SSPO Data Register SSPODR 0x4004 0008 Software can write data to be transmitted to this register and read data that has been received Table 178 SSPO Data Register SSPODR address 0x4004 0008 bit description Bit Symbol Description Reset Value 15 0 DATA Write software can write data to be sent in a future frame to this 0x0000 register whenever the TNF bit in the Status register is 1 indicating that the Tx FIFO is not full If the Tx FIFO was previously empty and the SSP controller is not busy on the bus transmission of the data will begin immediately Otherwise the data written to this register will be sent as soon as all previous data has been sent and received If the data length is less than 16 bit software must right justify the data written to this register Read software can read data from this register whenever the RNE bit in the Status register is 1 indicating that the Rx FIFO is not empty When software reads this register the SSP controller returns data from the least recent frame in the Rx FIFO If the data length is less than 16 bit the data is right justified in this field with higher order bits filled with Os 6 4 SSPO Status Register SSPOSR 0x4004 000C This read
42. PIO0_2 SSEL Jul CT16B0_CAPO PIO0_3 USB_VBUS gli PIOO_4 SCL 1012 PIOO_5 SDA 112 PIO0_6 USB_CONNECT 151 SCK PIO0_7 CTS 1611 PIOO_8 MISO 1711 CT16B0_MATO PIOO_9 MOSI 184 CT16B0_MAT1 SWO UM10375_0 Type 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Description RESET External reset input A LOW on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 PIO0_0 General purpose digital input output pin PIOO_1 General purpose digital input output pin A LOW level on this pin during reset starts the ISP command handler or the USB device enumeration USB on LPC1342 43 only see description of PIOO_3 CLKOUT Clock out pin CT32B0_MAT2 Match output 2 for 32 bit timer 0 USB_FTOGGLE USB 1 ms Start of Frame signal LPC1342 43 only PIO0_2 General purpose digital input output pin SSEL Slave select for SSP CT16B0_CAPO Capture input 0 for 16 bit timer 0 PIOO_3 General purpose digital input output pin LPC1342 43 only A LOW level on this pin during reset starts the ISP command handler a HIGH level starts the USB device enumeration USB_VBUS Monitors the presence of USB bus power LPC1342 43 only PIOO_4 General purpose digital input output pin SCL 12C bus clock input output High current sink only if 12C Fast mode Plus is selected in
43. Reserved 1 31 7 Reserved Table 69 IOCON_PIO2_7 register IOCON_PIO2_7 address 0x4004 4020 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO2_7 001 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 60 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 70 IOCON_PIO2_8 register IOCON_PIO2_8 address 0x4004 4024 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO2_8 001 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 61 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 71 IOCON_PIO2_1 register IOCON_PIO2_1 address
44. The LSB GC is used to enable General Call address 0x00 recognition When multiple slave addresses are enabled the actual address received may be read from the I2DAT register at the state where the own slave address has been received Address mask registers I2MASKO to IZMASK3 The four mask registers each contain seven active bits 7 1 Any bit in these registers which is set to 1 will cause an automatic compare on the corresponding bit of the received address when it is compared to the I2ADDRn register associated with that mask register In other words bits in an I2ADDRn register which are masked are not taken into account in determining an address match If the IZADDRn bit O GC enable bit is as set and bits 7 1 are all zeroes then the part will respond to a received address 0000000 regardless of the state of the associated mask register When an address match interrupt occurs the processor will have to read the data register 12DAT to determine what the received address was that actually caused the match Comparator The comparator compares the received 7 bit slave address with its own slave address 7 most significant bits in 12ADR It also compares the first received 8 bit byte with the General Call address 0x00 If an equality is found the appropriate status bits are set and an interrupt is requested Shift register I2DAT This 8 bit register contains a byte of serial data to be transmitted or a byte whi
45. The data transfer follows the little endian format The first byte sent on the USB bus will be the LS byte of the transmit data register Remark USB is a host controlled protocol i e irrespective of whether the data transfer is from the host to the device or from the device to the host the transfer sequence is always initiated by the host During data transfer from the device to the host the host sends an IN token to the device following which the device responds with the data Interrupt based transfer Interrupt based data transfer is done through the interrupt issued from the USB core to the processor Reception of a valid error free data packet in any of the OUT non isochronous endpoint buffer generates an interrupt Upon receiving the interrupt the software can read the data using receive length and data registers When there is no empty buffer for a given non isochronous OUT endpoint any data arrival generates an interrupt only if Interrupt On NAK feature for that endpoint type is enabled and existing interrupt is cleared Similarly when a packet is successfully transferred to the host from any IN non isochronous endpoint buffer an interrupt is generated When there is no data available in any of the buffers for a given non isochronous IN endpoint a data request generates an interrupt only if Interrupt On NAK feature for that endpoint type is enabled and existing interrupt is cleared Upon receiving the interrupt the softwa
46. UART Transmitter Holding Register UOTHR 0x4000 8000 when DLAB 0 Write Only The UOTHR is the top byte of the UART TX FIFO The top byte is the newest character in the TX FIFO and can be written via the bus interface The LSB represents the first bit to transmit The Divisor Latch Access Bit DLAB in UOLCR must be zero in order to access the UOTHR The UOTHR is always Write Only Table 153 UART Transmitter Holding Register UOTHR address 0x4000 8000 when DLAB 0 Write Only bit description Bit Symbol Description Reset Value 7 0 THR Writing to the UART Transmit Holding Register causes the data NA to be stored in the UART transmit FIFO The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available 31 8 Reserved UART Divisor Latch LSB and MSB Registers UODLL 0x4000 8000 and UODLM 0x4000 8004 when DLAB 1 The UART Divisor Latch is part of the UART Baud Rate Generator and holds the value used along with the Fractional Divider to divide the UART_PCLK clock in order to produce the baud rate clock which must be 16x the desired baud rate The UODLL and UODLM registers together form a 16 bit divisor where UODLL contains the lower 8 bits of the divisor and UODLM contains the higher 8 bits of the divisor A 0x0000 value is treated like a Ox0001 value as division by zero is not allowed The Divisor Latch Access Bit DLAB in UOLCR must be one in order to access the UART Divisor Latches
47. UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 190 of 290 NXP Semiconductors U M1 0375 Chapter 12 LPC13xx I2C bus interface MT successful transmission to a Slave Receiver next transfer started with a Repeated Start gt condition Not Acknowledge l received after E l the Slave l address i to Master Not big Acknowledge A beste received after a i et Data byte E arbitration lost i ies i gt in Slave gt AOR A other Master LAOR other Master address or i continues 1 continues Data byte arbitration lost and other Master addressed as continues Slave to corresponding states in Slave mode from Master to Slave from Slave to Master A A N DATA 1 any number of data bytes and their associated Acknowledge bits this number contained in I2STA corresponds to a defined state of the PC bus Fig 37 Format and states in the Master Transmitter mode UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 191 of 290 NXP Semiconductors UM10375 Chapter 12 LPC13xx I2C bus interface reception of the own Slave address and one or more Data bytes all are acknowledged last data byte received is Not acknowledged arbitration lost as Master and addressed as Slave reception of the General Call address and one or more Data bytes last data byte is Not acknowledged arbitratio
48. Write 0x08 to I2CONCLR to clear the SI flag Set up Slave Transmit mode data buffer Increment Slave Transmit buffer pointer Exit ont Why 11 9 3 State 0xB8 Data has been transmitted ACK has been received Data will be transmitted ACK bit will be received 1 Load I2DAT from Slave Transmit buffer with data byte 2 Write 0x04 to 1I2CONSET to set the AA bit 3 Write 0x08 to I2CONCLR to clear the SI flag 4 Increment Slave Transmit buffer pointer NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 210 of 290 NXP Semiconductors U M1 0375 Chapter 12 LPC13xx I2C bus interface 5 Exit 11 9 4 State 0xCO Data has been transmitted NOT ACK has been received Not addressed Slave mode is entered 1 Write 0x04 to IZCONSET to set the AA bit 2 Write 0x08 to IZCONCLR to clear the SI flag 3 Exit 11 9 5 State 0xC8 The last data byte has been transmitted ACK has been received Not addressed Slave mode is entered 1 Write 0x04 to IZCONSET to set the AA bit 2 Write 0x08 to IZCONCLR to clear the SI flag 3 Exit UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 211 of 290 UM10375 Chapter 13 LPC13xx 16 bit counter timer CT16B Rev 00 10 19 October 2009 User manual 1 How to read this chapter The 16 bit timer blocks are identical for all LPC13xx parts 2 Features 3 Applications Two 16 bit
49. Write 0x24 to IZCONSET to set the STA and AA bits Write 0x08 to I2CONCLR to clear the SI flag Set up Slave Receive mode data buffer Initialize Slave data counter Exit ar O N gt State 0x80 Previously addressed with own Slave Address Data has been received and ACK has been returned Additional data will be read Read data byte from I2DAT into the Slave Receive buffer Decrement the Slave data counter skip to step 5 if not the last data byte Write 0x0C to IZCONCLR to clear the SI flag and the AA bit Exit Write 0x04 to IZCONSET to set the AA bit Write 0x08 to I2CONCLR to clear the SI flag Increment Slave Receive buffer pointer Exit ON AOR WD State 0x88 Previously addressed with own Slave Address Data has been received and NOT ACK has been returned Received data will not be saved Not addressed Slave mode is entered 1 Write 0x04 to IZCONSET to set the AA bit 2 Write 0x08 to IZCONCLR to clear the SI flag 3 Exit State 0x90 Previously addressed with General Call Data has been received ACK has been returned Received data will be saved Only the first data byte will be received with ACK Additional data will be received with NOT ACK 1 Read data byte from I2DAT into the Slave Receive buffer 2 Write 0x0C to IZCONCLR to clear the SI flag and the AA bit 3 Exit State 0x98 Previously addressed with General Call Data has been received NOT ACK has been returned
50. a framing 0 Error error occurs A UOLSR read clears UOLSR 3 The time of the FE framing error detection is dependent on UOFCRO Upon detection of a framing error the RX will attempt to re synchronize to the data and assume that the bad stop bit is actually an early start bit However it cannot be assumed that the next received byte will be correct even if there is no Framing Error Note A framing error is associated with the character at the top of the UART RBR FIFO O Framing error status is inactive Framing error status is active UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 141 of 290 NXP Semiconductors UM10375 UM10375_0 5 10 Chapter 10 LPC13xx UART Table 163 UART Line Status Register UOLSR address 0x4000 8014 Read Only bit description continued Bit Symbol 4 Break Interrupt Bl 5 _Transmitte r Holding Register Empty THRE 6 Transmitte r Empty TEMT 7 Errorin RX FIFO RXFE Value Description Reset Value When RXD1 is held in the spacing state all zeros for one full 0 i character transmission start data parity stop a break interrupt occurs Once the break condition has been detected the receiver goes idle until RXD1 goes to marking state all ones A UOLSR read clears this status bit The time of break detection is dependent on UOFCR O Note The break interrupt is associated with the character at the top of
51. a non auto baud interrupt is pending in which case the Intld bits identify the type of interrupt and handling as described in Table 10 158 Given the status of UOIIR 3 0 an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt The UOIIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine The UART RLS interrupt UOIIR 3 1 011 is the highest priority interrupt and is set whenever any one of four error conditions occur on the UART RX input overrun error OE parity error PE framing error FE and break interrupt BI The UART Rx error condition that set the interrupt can be observed via UOLSR 4 1 The interrupt is cleared upon a UOLSR read O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 135 of 290 NXP Semiconductors UM10375 UM10375_0 Chapter 10 LPC13xx UART The UART RDA interrupt UOIIR 3 1 010 shares the second level priority with the CTI interrupt UOIIR 3 1 110 The RDA is activated when the UART Rx FIFO reaches the trigger level defined in UOFCR7 6 and is reset when the UART Rx FIFO depth falls below the trigger level When the RDA interrupt goes active the CPU can read a block of data defined by the trigger level The CTI interrupt UOIIR 3 1 110 is a second level interrupt and is set when the UART Rx FIFO contains at least one character and no UART Rx FIFO activity has oc
52. and remains stable until the interrupt flag is cleared by software The three least significant bits of the status register are always zero If the status code is used as a vector to service routines then the routines are displaced by eight address locations Eight bytes of code is sufficient for most of the service routines see the software example in this section 10 Details of 12C operating modes UM10375_0 The four operating modes are e Master Transmitter e Master Receiver e Slave Receiver e Slave Transmitter Data transfers in each mode of operation are shown in Figure 12 37 Figure 12 38 Figure 12 39 Figure 12 40 and Figure 12 41 Table 12 201 lists abbreviations used in these figures when describing the 12C operating modes O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 187 of 290 NXP Semiconductors U M1 0375 UM10375_0 10 1 Chapter 12 LPC13xx I2C bus interface Table 201 Abbreviations used to describe an I2C operation Abbreviation Explanation S START Condition SLA 7 bit slave address R Read bit HIGH level at SDA W Write bit LOW level at SDA A Acknowledge bit LOW level at SDA A Not acknowledge bit HIGH level at SDA Data 8 bit data byte P STOP condition In Figure 12 37 to Figure 12 41 circles are used to indicate when the serial interrupt flag is set The numbers in the circles show the status code held in the I2STAT register
53. and in addition selected analog blocks are powered down The user can configure which blocks remain powered down during Deep sleep mode and which blocks will be running on wake up from Deep sleep mode The LPC13xx can wake up from Deep sleep mode without the use of interrupts from peripherals by monitoring the inputs to the start logic see Section 3 9 3 Most GPIO pins function as start logic inputs The start logic does not require any clocks and generates the interrupt to wake up from Deep sleep mode During Deep sleep mode the processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static Except for analog peripherals selected to remain powered in the PDSLEEPCFG register all peripherals are turned off The advantage of the Deep sleep mode is that the user can power down clock generating blocks such as oscillators and PLLs thereby gaining far greater dynamic power savings over Sleep mode In addition the flash may be powered down in Deep sleep mode resulting in savings in static leakage power however at the expense of longer wake up times for the flash memory O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 41 of 290 NXP Semiconductors U M1 0375 8 4 Chapter 3 LPC13xx System configuration Deep power down mode In Deep power down mode power and clocks are shut off to the entire chip with the exception of
54. skip to step 5 if not the last data byte Write 0x14 to I2CONSET to set the STO and AA bits Write 0x08 to I2CONCLR to clear the SI flag Exit Load I2DAT with next data byte from Master Transmit buffer Write 0x04 to I2CONSET to set the AA bit Write 0x08 to I2CONCLR to clear the SI flag Increment Master Transmit buffer pointer o XA AOR WD O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 206 of 290 NXP Semiconductors U M1 0375 11 6 4 11 6 5 11 7 11 7 1 11 7 2 11 7 3 UM10375_0 Chapter 12 LPC13xx I2C bus interface 9 Exit State 0x30 Data has been transmitted NOT ACK received A STOP condition will be transmitted 1 Write 0x14 to I2CONSET to set the STO and AA bits 2 Write 0x08 to IZCONCLR to clear the SI flag 3 Exit State 0x38 Arbitration has been lost during Slave Address Write or data The bus has been released and not addressed Slave mode is entered A new START condition will be transmitted when the bus is free again 1 Write 0x24 to IZCONSET to set the STA and AA bits 2 Write 0x08 to IZCONCLR to clear the SI flag 3 Exit Master Receive states State 0x40 Previous state was State 08 or State 10 Slave Address Read has been transmitted ACK has been received Data will be received and ACK returned 1 Write 0x04 to IZCONSET to set the AA bit 2 Write 0x08 to IZCONCLR to clear the SI flag 3 Exit State 0x48 S
55. transmit and receive FIFOs 1 Reset Value reflects the data stored in used bits only It does not include reserved bits content UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 132 of 290 NXP Semiconductors U M1 0375 UM10375_0 5 1 5 2 5 3 Chapter 10 LPC13xx UART UART Receiver Buffer Register UORBR 0x4000 8000 when DLAB 0 Read Only The UORBR is the top byte of the UART RX FIFO The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface The LSB bit 0 represents the oldest received data bit If the character received is less than 8 bits the unused MSBs are padded with zeroes The Divisor Latch Access Bit DLAB in UOLCR must be zero in order to access the UORBR The UORBR is always Read Only Since PE FE and BI bits see Table 10 163 correspond to the byte sitting on the top of the RBR FIFO i e the one that will be read in the next read from the RBR the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the UOLSR register and then to read a byte from the UORBR Table 152 UART Receiver Buffer Register UORBR address 0x4000 8000 when DLAB 0 Read Only bit description Bit Symbol Description Reset Value 7 0 RBR The UART Receiver Buffer Register contains the oldest received undefined byte in the UART RX FIFO 31 8 Reserved
56. 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 AA Next action taken by I2C hardware Switched to not addressed SLV mode no recognition of own SLA or General call address Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if 12ADR 0 logic 1 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if I2ADR 0 logic 1 A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode no recognition of own SLA or General call address Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if 12ADR 0 logic 1 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if I2ADR 0 logic 1 A START condition will be transmitted when the bus becomes free UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 198 of 290 NXP Semiconductors UM10375 Table 208 Slave Transmitter mode Chapter 12 LPC13xx I2C bus interface St
57. 00 10 19 October 2009 212 of 290 NXP Semiconductors UM10375 Chapter 13 LPC13xx 16 bit counter timer CT16B In PWM mode three match registers on CT16B0 and two match registers on CT16B1 can be used to provide a single edge controlled PWM output on the match output pins It is recommended to use the match registers that are not pinned out to control the PWM cycle length Remark The 16 bit counter timer0 CT16B0 and the 16 bit counter timer1 CT16B1 are functionally identical except for the peripheral base address 5 Pin description Table 13 210 gives a brief summary of each of the counter timer related pins Table 210 Counter timer pin description Pin CT16B0_CAPO CT16B1_CAPO CT16B0_MAT 2 0 CT16B1_MAT 1 0 Type Input Output Description Capture Signal A transition on a capture pin can be configured to load the Capture Register with the value in the counter timer and optionally generate an interrupt Counter Timer block can select a capture signal as a clock source instead of the PCLK derived clock For more details see Section 13 7 11 External Match Outputs of CT16B0 1 When a match register of CT16B0 1 MR3 0 equals the timer counter TC this output can either toggle go LOW go HIGH or do nothing The External Match Register EMR and the PWM Control Register PWMCON control the functionality of this output 6 Clocking and power control The peripheral clocks PCLK to t
58. 0x00 GPIOnIS R W 0x8004 Interrupt sense register for port n 0x00 GPIOnIBE R W 0x8008 Interrupt both edges register for port n 0x00 GPIOnIEV R W 0x800C Interrupt event register for port n 0x00 GPIOnIE R W 0x8010 Interrupt mask register for port n 0x00 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 85 of 290 NXP Semiconductors U M1 0375 Chapter 7 LPC13xx General Purpose I O GPIO Table 108 Register overview GPIO base address port 0 0x5000 0000 port 1 0x5001 0000 port 2 0x5002 0000 port 3 0x5003 0000 Name GPIONRIS GPIOnMIS GPIOnIC Access Address offset Description Reset value R 0x8014 Raw interrupt status register for port n 0x00 R 0x8018 Masked interrupt status register for port n 0x00 W 0x801C Interrupt clear register for port n 0x00 0x8020 Ox8FFF reserved 0x00 UM10375_0 3 1 3 2 3 3 GPIO data register The data register allows to read the values on the pins programmed as inputs and to program the values on pins configured as outputs The same data register appears at 4096 locations in the GPIO address space and 12 bits of the address bus can be used for bit masking see Section 7 4 1 Table 109 GPIOnDATA register GPIOODATA address 0x5000 0000 to 0x5000 3FFC GPIO1DATA address 0x5001 0000 to 0x5001 3FFC GPIO2DATA address 0x5002 0000 to 0x5002 3FFC GPIO3DATA address 0x5003 0000 to 0x5003 3FFC bit description Bit Symbol Access Descript
59. 0x4004 4028 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO2_1 001 Select function DSR 010to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved Table 72 IOCON_PIOO_3 register IOCON_PIOO_3 address 0x4004 402C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIOO_3 001 Selects function USB_VBUS 010to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 62 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 73 IOCON_PIOO_4 register IOCON_PIOO_4 address 0x4004 4030 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIOO_4 001 Selects 12C function SCL 010 to Reserved 111 7 3 Reserved 00000 9
60. 3 3 V supply voltage to the internal regulator and the ADC Also used as the ADC reference voltage Ground Input to the oscillator circuit and internal clock generator circuits Input voltage must not exceed 1 8 V Output from the oscillator amplifier Ground 1 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis 2 I2C bus pads compliant with the 12C bus specification for 12C standard mode and 2C Fast mode Plus 3 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors configurable hysteresis and analog input When configured as a ADC input digital section of the pad is disabled and the pin is not 5 V tolerant UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 98 of 290 NXP Semiconductors UM10375 Chapter 8 LPC13xx Pin configuration 4 Pad provides USB functions It is designed in accordance with the USB specification revision 2 0 Full speed and Low speed mode only 5 When the system oscillator is not used connect XTALIN and XTALOUT as follows XTALIN can be left floating or can be grounded grounding is preferred to reduce susceptibility to noise XTALOUT should be left floating 4 2 HVQFN33 packages Table 120 LPC1311 13 42 43 HVQFN33 pin description table Symbol Pin RESET PIO0_0 2 PIO0_1 CLKOUT 31 CT32B0_MAT2 USB_FTOGGLE
61. 32 bit counter timer block diagram 233 System tick timer block diagram 235 Watchdog block diagraM 248 Boot process flowchart 254 IAP parameter passing 266 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 283 of 290 NXP Semiconductors UM10375 5 Contents Chapter 20 LPC13xx Supplementary information Chapter 1 LPC13xx Introductory information 1 Introduction 0 0 cece eee eee 3 4 Ordering Opti0NS oooooooomo 4 2 How to read this manual 3 5 Block diagraM oo oooooccooommmmo o 5 3 Features e como iio OR 3 Chapter 2 LPC13xx Memory mapping 1 How to read this chapter 6 3 Memory reMappin9 o oooooooo 7 2 Memory Map 00 c seen eee ee eee 6 Chapter 3 LPC13xx System configuration 1 How to read this chapter 8 5 34 BOD control register 28 Input pins to the start logic 8 5 35 System tick counter calibration register 29 PIO reset status registerS 8 5 36 Start logic edge control registerO 29 USB clocking and power control 8 5 37 Start logic signal enable registerO 30 2 Introduction ccceee eee eee 9 ae ath aoe reset register y e giek Ed ae E tart logic status register O 3 on GeSsenplon ee ee ee ey
62. 40A8 bit description 79 Table 104 IOCON_PIO3_3 register IOCON_PIO3_ 3 address 0x4004 40AC bit description 79 Table 105 IOCON SCK location register IOCON_SCKLOC address 0x4004 40B0 bit description 80 Table 106 Connection of interrupt sources to the Vectored Interrupt Controller 81 Table 107 GPIO configurati0N o oo ooooooo 83 Table 108 Register overview GPIO base address port 0 0x5000 0000 port 1 0x5001 0000 port 2 0x5002 0000 port 3 0x5003 0000 83 Table 109 GPIONDATA register GPIOODATA address 0x5000 0000 to 0x5000 3FFC GPIO1DATA address 0x5001 0000 to 0x5001 3FFC GPIO2DATA address 0x5002 0000 to 0x5002 3FFC GPIO3DATA address 0x5003 0000 to 0x5003 3FFC bit description 84 Table 110 GPIOnDIR register GPIOODIR address 0x5000 8000 to GPIO3DIR address 0x5003 8000 bit GESCMPUON ss aise geek a cli ae a 84 Table 111 GPIOnIS register GPIOOIS address 0x5000 8004 to GPIOSIS address 0x5003 8004 bit description 2000 cece ee eee 84 Table 112 GPIOnIBE register GPIOOIBE address 0x5000 8008 to GPIOSIBE address 0x5003 8008 bit description 200 cee eee eee 85 Table 113 GPIOnIEV register GPIOOIEV address 0x5000 800C to GPIOSIEV address 0x5003 800C bit description 200 cee eee eee 85 Table 114 GPIOnNIE register GPIOOIE address 0x5000 8010 to GPIOSIE address 0x5003 8010 bit description Ta
63. 8 5 40 Start logic edge control register 1 32 4 General descripti0N oommoooomm 10 5 41 Start logic signal enable register 1 32 5 Register description oooooo o oo 11 5 42 Start logic reset register 1 33 5 1 System memory remap register 12 5 43 Start logic status register 1 34 5 2 Peripheral reset control register 13 5 44 Deep sleep mode configuration register 34 5 3 System PLL control register 13 5 45 Wake up configuration register 35 5 4 System PLL status register 14 546 Power down configuration register 36 5 5 USB PLL control register 14 547 Device ID register 38 P PLL es dd OA le 6 Reset on 38 ystem oscillator control register 5 8 Watchdog oscillator control register 16 f Brown ONE AEtECHON psoe 38 5 9 Internal resonant crystal control register 17 8 Power management 39 5 10 System reset status register 18 81 Sleep Mode 6 eee rro 40 5 11 System PLL clock source select register 18 8 2 Deep sleep Mode oooooooococorono o 40 5 12 System PLL clock source update enable register 8 3 Deep power down mode 0 40 19 9 Deep sleep mode oooococccc oo 40 5 13 USB PLL clock source select register 19 9 1 Entering Deep sleep mode 40 5 14 USB PLL clock sour
64. 8 I2CMODE Selects 12C mode 00 o0 l Standard mode Fast mode 12C 010 Standard I O functionality 10 Fast mode Plus 12C 11 Reserved 31 10 Reserved 1 Select Standard mode IZCMODE 00 default or Standard I O functionality IZCMODE 01 if the pin function is GPIO FUNC 000 Table 74 IOCON_PIOO_5 register IOCON_PIOO_5 address 0x4004 4034 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIOO_5 001 Selects 12C function SDA 010to Reserved 111 7 3 Reserved 00000 9 8 I2CMODE Selects 12C mode 00 ool Standard mode Fast mode 12C 010 Standard l O functionality 10 Fast mode Plus 12C 11 Reserved 31 10 Reserved 1 Select Standard mode I2CMODE 00 default or Standard I O functionality IZCMODE 01 if the pin function is GPIO FUNC 000 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 63 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 75 IOCON_PIO1_ 9 register IOCON_PIO1_9 address 0x4004 4038 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO1_9 001 Selects function CT16B1_MATO 010to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up re
65. CT16B1CRO address 0x4001 002C 7 2 Timer Control Register TMR16B0TCR and 216 TMRIG6B1ITCR 000 c ee eee eee 213 7 10 External Match Register TMR16BOEMR and 7 3 Timer Counter TMR16BOTC address 0x4000 TMRI6B1EMR 216 C008 and TMR16B1TC address 0x4001 0008 7 11 Count Control Register TMR16BOCTCR and 214 TMRI6BICTCR 0 00 e eee eee 217 7 4 Prescale Register TMR16BOPR address 7 12 PWM Control register TMR16BOPWMC and 0x4000 COOC and TMR16B1PR address TMR1I6B1PWMC ooo 218 0x4001 000C 0 00 214 7 13 Rules for single edge controlled PWM outputs 7 5 Prescale Counter register TMR16BOPC 219 address 0x4000 C010 and TMR16B1PC 8 Example timer operation 220 address 0x4001 0010 214 9 Architecture oooooccoccoccocconno 221 Chapter 14 LPC13xx 32 bit counter timer CT32B 1 How to read this chapter 222 7 Register descripti0N 223 2 FeatureS cooinioiicic cri 222 7 1 Interrupt Register TMR32BOIR and TMR32B1IR 3 Applicati0NS oooococoncooomom 222 e Control Register TMRS2BOTCR and aan imer Control Register an 4 Description repeat e 222 TMR32B1TCR 0 eee cece cece cece 225 5 Pin descripti0N o oooooomo o 223 6 Clocking and power control 223 UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 288 of 290 NXP Semiconductors UM
66. Code CMD SUCCESS PARAM_ERROR Description The default setting for echo command is ON When ON the ISP command handler sends the received serial data back to the host Example A 0 lt CR gt lt LF gt turns echo off Write to RAM lt start address gt lt number of bytes gt The host should send the data only after receiving the CMD_SUCCESS return code The host should send the check sum after transmitting 20 UU encoded lines The checksum is generated by adding raw data before UU encoding bytes and is reset after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes When the data fits in less then 20 UU encoded lines then the check sum should be of the actual number of bytes sent The ISP command handler compares it with the check sum of the received bytes If the check sum matches the ISP command handler responds with OK lt CR gt lt LF gt to continue further transmission If the check sum does not match the ISP command handler responds with RESEND lt CR gt lt LF gt In response the host should retransmit the bytes Table 260 ISP Write to RAM command Command Ww Input Start Address RAM address where data bytes are to be written This address should be a word boundary Number of Bytes Number of bytes to be written Count should be a multiple of 4 Return Code CMD SUCCESS ADDR_ERROR Address not on word boundary ADDR_NOT_MA
67. Copy RAM to flash command can not write to Sector 0 e Erase command can erase Sector 0 only when all sectors are selected for erase e Compare command is disabled e Read Memory command is disabled This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased Since compare command is disabled in case of partial updates the secondary loader should implement checksum mechanism to verify the integrity of the flash Access to chip via the JTAG pins is disabled The following ISP commands are disabled e Read Memory e Write to RAM e Go e Copy RAM to flash e Compare When CRP2 is enabled the ISP erase command only allows erasure of all user sectors Access to chip via the JTAG pins is disabled ISP entry by pulling PIO0_1 LOW is disabled if a valid user code is present in flash sector 0 This mode effectively disables ISP override using PIOO_1 pin lt is up to the user s application to provide a flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UARTO Caution If CRP3 is selected no future factory testing can be performed on the device Table 254 Code Read Protection hardware software interaction CRP option No No No CRP1 CRP1 CRP2 CRP2 CRP3 CRP1 CRP2 CRP3 User Code PIOO_1 pinat JTAG enabled LPC13xx partial flash Valid reset enters ISP Update in ISP mode mode No x Yes Yes Yes Yes High Yes No NA Yes Low Y
68. IOCON_PIO1_9 R W 0x038 I O configuration for pin PIO1_9 CT16B1_MATO OxDO IOCON_PIO3_4 R W 0x03C I O configuration for pin PIO3_4 OxDO IOCON_PIO2_4 R W 0x040 I O configuration for pin PIO2_4 0xDO IOCON_PIO2_5 R W 0x044 I O configuration for pin PIO2_5 0xDO IOCON_PIO3_5 R W 0x048 I O configuration for pin PIO3_5 OxDO IOCON_PIOO 6 R W 0x04C I O configuration for pin PIOO_6 USB_CONNECT SCK 0xDO IOCON_PIOO_7 R W 0x050 1 O configuration for pin PIOO_7 CTS OxDO IOCON_PIO2_9 R W 0x054 I O configuration for pin PlO2_9 OxDO IOCON_PIO2_10 R W 0x058 I O configuration for pin PlO2_10 OxDO IOCON_PIO2_2 R W 0x05C O configuration for pin PIO2_2 DCD OxDO IOCON_PIOO_8 R W 0x060 I O configuration for pin PIOO_8 MISO CT16B0_MATO 0xDO IOCON_PIOO_9 R W 0x064 I O configuration for pin PIOO_9 MOSI OxDO CT16B0_MAT1 SWO IOCON_JTAG_TCK_PIOO_10 R W 0x068 I O configuration for pin SWCLK PIOO_10 OxDO SCK CT16B0_MAT2 IOCON_PIO1_10 R W 0x06C I O configuration for pin PIO1_10 AD6 OxDO CT16B1_MAT1 IOCON_PIO2_11 R W 0x070 I O configuration for pin PIO2_11 SCK 0xDO IOCON_JTAG_TDI_PIOO_11 R W 0x074 1 O configuration for pin TDI PIOO_11 ADO0 CT32B0_MAT3 OxDO IOCON_JTAG_TMS_PIO1_0 R W 0x078 1 O configuration for pin TMS PIO1_0 AD1 OxDO CT32B1_CAPO IOCON_JTAG_TDO_PIO1_1 R W 0x07C I O configuration for pin TDO PIO1_1 AD2 CT32B1_MATO OxDO IOCON_JTAG_nTRST_PIO1_2 R W 0x080 O configuration for pin TRST PIO1_2 AD3 OxDO CT32B1_MAT1 IOCON_PIO3_0 R W 0x084 I O configuration
69. IOCON_PIO3_0 IOCON_PIO3_1 IOCON_PIO3_3 not used 2 Introduction The I O configuration registers control the electrical characteristics of the pins The following characteristics are configurable e pin function e internal pull up pull down or Repeater mode function e hysteresis e analog input or digital mode for pins hosting the ADC inputs 2C mode for pins hosting the 12C bus function 3 General description The IOCON registers control the function GPIO or peripheral function the input mode and the hysteresis of all PIO pins In addition the 12C bus pins can be configured for different I12C bus modes If a pin is used as input pin for the ADC an analog input mode can be selected UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 52 of 290 NXP Semiconductors U M1 0375 UM10375_0 3 1 3 2 3 3 Chapter 5 LPC13xx I O configuration enable z l output gt input Rpd ZX hysteresis control 002aae828 Fig 5 Standard I O pin configuration Pin function The FUNC bits in the IOCON registers can be set to GPIO FUNC 000 or toa peripheral function If the pins are GPIO pins the GPIOnDIR registers determine whether the pin is configured as an input or output see Table 7 110 For any peripheral function the pin direction is controlled automatically depending on the p
70. Interrupt on MR2 an interrupt is generated when MR2 matches the value in the TC This interrupt is disabled Reset on MR2 the TC will be reset if MR2 matches it Feature disabled Stop on MR2 the TC and PC will be stopped and TCR O will be set to 0 if MR2 matches the TC Feature disabled Interrupt on MR3 an interrupt is generated when MR3 matches the value in the TC This interrupt is disabled Reset on MR3 the TC will be reset if MR3 matches it Feature disabled Stop on MR3 the TC and PC will be stopped and TCR O will be set to 0 if MR3 matches the TC Feature disabled Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Reset value 0 NA UM10375_0 7 7 Match Registers TMR32BOMR0 1 2 3 addresses 0x4001 4018 1C 20 24 and TMR32B1MRO0 1 2 3 addresses 0x4001 8018 1C 20 24 The Match register values are continuously compared to the Timer Counter value When the two values are equal actions can be triggered automatically The action possibilities are to generate an interrupt reset the Timer Counter or stop the timer Actions are controlled by the settings in the MCR register O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 229 of 290 NXP Semiconductors U M1 0375 Chapter 14 LPC13xx 32 bit counter timer CT32B 7 8 Capture Control Register TMR32BOCCR and TMR32B1CCR The Capture Contro
71. LPC1311 0x0000 0000 002aae723 Fig 2 LPC13xx memory map 3 Memory remapping For details see Table 3 6 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 7 of 290 UM10375 Chapter 3 LPC13xx System configuration Rev 00 10 19 October 2009 User manual 1 How to read this chapter The system configuration registers apply to all LPC13xx parts with the following exceptions Input pins to the start logic For HVQFN packages the start logic control bits see Table 3 41 to Table 3 48 are reserved for port pins PIO2_1 to PIO2_11 and PIO3_0 PIO3_1 and PIO3_3 PIO reset status registers For HVQFN packages the reset status bits see Table 3 37 and Table 3 38 are reserved for port pins PIO2_1 to PIO2_11 and PIO3_0 and PIO3_1 and PIO3_3 USB clocking and power control Since the USB block is available on the LPC1342 and LPC1343 only the registers and register bits listed in Table 3 3 are reserved for parts LPC1311 and LPC1313 Table 3 USB related registers and register bits reserved for LPC1311 13 Name Access Address Description Register bits offset reserved for LPC1311 13 USBPLLCTRL R W 0x010 USB PLL control all USBPLLSTAT R 0x014 USB PLL status all USBPLLCLKSEL R W 0x048 USB PLL clock source select all USBPLLCLKUEN R W 0x04C USB PLL clock source update enable all SYSAHBCLKCTRL R W 0x080 System AHB clock control bit 14 USBCLKSEL R W 0x0C0 USB clock source select
72. M and P it is recommended to follow these steps O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 45 of 290 NXP Semiconductors U M1 0375 Chapter 3 LPC13xx System configuration Specify the input clock frequency Fclkin Calculate M to obtain the desired output frequency Fclkout with M Folkout Felkin Find a value so that FCCO 2 x P x Folkout Verify that all frequencies and divider values conform to the limits specified in Table 3 8 and Table 3 10 gt A OUO N 10 6 2 Mode 2 Direct CCO mode In this mode the post divider is bypassed and the CCO clock is sent directly to the output s leading to the following frequency equation Fclkout M x Fclkin FCCO To select the appropriate values for M and P it is recommended to follow these steps 1 Specify the input clock frequency Fclkin 2 Calculate M to obtain the desired output frequency Fclkout with M Fetkout Felkin 3 Verify that all frequencies and divider values conform to the limits specified in Table 3 8 and Table 3 10 Note that although the post divider is not used it is still running in this mode To reduce the current consumption to the lowest possible value it is recommended to set PSEL bits to 00 This will set the post divider to divide by two which causes it to consume the least amount of current 10 6 3 Mode 3 Power down mode In this mode the internal current reference wi
73. MRO the TC will be reset if MRO matches it Feature disabled Stop on MRO the TC and PC will be stopped and TCR O will be set to 0 if MRO matches the TC Feature disabled Interrupt on MR1 an interrupt is generated when MR1 matches the value in the TC This interrupt is disabled Reset on MR1 the TC will be reset if MR1 matches it Feature disabled Stop on MR1 the TC and PC will be stopped and TCR O will be set to 0 if MR1 matches the TC Feature disabled Interrupt on MR2 an interrupt is generated when MR2 matches the value in the TC This interrupt is disabled Reset on MR2 the TC will be reset if MR2 matches it Feature disabled Stop on MR2 the TC and PC will be stopped and TCR O will be set to 0 if MR2 matches the TC Feature disabled Interrupt on MR3 an interrupt is generated when MR3 matches the value in the TC This interrupt is disabled Reset on MR3 the TC will be reset if MR3 matches it Feature disabled Stop on MR3 the TC and PC will be stopped and TCR O will be set to 0 if MR3 matches the TC Feature disabled Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Reset value 0 NA UM10375_0 7 7 Match Registers TMR16BOMR0 1 2 3 addresses 0x4000 C018 1C 20 24 and TMR16B1MR0 1 2 3 addresses 0x4001 0018 1C 20 24 The Match register values are continuously compared to the Timer Counter value When the two val
74. NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 270 of 290 NXP Semiconductors UM10375 UM10375_0 Chapter 18 LPC13xx Flash memory programming firmware 13 6 Read Boot code version number 13 7 13 8 Table 279 IAP Read Boot Code version number command Command Input Return Code Result Description Read boot code version number Command code 5510 Parameters None CMD_SUCCESS Result0 2 bytes of boot code version number in ASCII format It is to be interpreted as lt byte1 Major gt lt byte0 Minor gt This command is used to read the boot code version number Compare lt address1 gt lt address2 gt lt no of bytes gt Table 280 IAP Compare command Command Input Return Code Result Description Compare Command code 56 0 Param0 DST Starting flash or RAM address of data bytes to be compared This address should be a word boundary Param1 SRC Starting flash or RAM address of data bytes to be compared This address should be a word boundary Param2 Number of bytes to be compared should be a multiple of 4 CMD_SUCCESS COMPARE_ERROR COUNT_ERROR Byte count is not a multiple of 4 ADDR_ERROR ADDR_NOT_MAPPED Result0 Offset of the first mismatch if the Status Code is COMPARE_ERROR This command is used to compare the memory contents at two locations The result may not be correct when the source or destination includes any of
75. Received data will not be saved Not addressed Slave mode is entered O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 209 of 290 NXP Semiconductors U M1 0375 UM10375_0 11 8 9 11 9 11 9 1 11 9 2 Chapter 12 LPC13xx I2C bus interface 1 Write 0x04 to I2CONSET to set the AA bit 2 Write 0x08 to IZCONCLR to clear the SI flag 3 Exit State 0xA0 A STOP condition or Repeated START has been received while still addressed as a Slave Data will not be saved Not addressed Slave mode is entered 1 Write 0x04 to IZCONSET to set the AA bit 2 Write 0x08 to IZCONCLR to clear the SI flag 3 Exit Slave Transmitter states State 0xA8 Own Slave Address Read has been received ACK has been returned Data will be transmitted ACK bit will be received Load I2DAT from Slave Transmit buffer with first data byte Write 0x04 to IZCONSET to set the AA bit Write 0x08 to I2CONCLR to clear the SI flag Set up Slave Transmit mode data buffer Increment Slave Transmit buffer pointer Exit O a A OON State 0xBO Arbitration lost in Slave Address and R W bit as bus Master Own Slave Address Read has been received ACK has been returned Data will be transmitted ACK bit will be received STA is set to restart Master mode after the bus is free again Load I2DAT from Slave Transmit buffer with first data byte Write 0x24 to IZCONSET to set the STA and AA bits
76. Remote wake up ooooooooorooomo o gt 106 3 Features A 101 85 Interrupts A E 106 4 Fixed endpoint configuration 101 i i a eee A cen ga a a hs ated evice interrupt registers i 1 T ps E N pe 9 1 1 USB Device Interrupt Status register F ee ke USBDevintSt 0x4002 0000 107 53 Sahe BANE Ep El adi s 102 9 1 2 USB Device Interrupt Enable register ESA EP ay EP_ a Popes nee ices kor USBDevintEn 0x4002 0004 107 55 Regist e A ARPA 102 9 1 3 USB Device Interrupt Clear register ES ane se A o ei eat ieee eee los USBDevintClr 0x4002 0008 108 a 9 GCI oi Ne ee 9 1 4 USB Device Interrupt Set register USBDevintSet 6 Operational overview 103 0x4002 000C csc vciieedewbecsohuds 108 7 Pin descripti0N o oooooommo 104 9 2 SIE command code registers 108 8 Clocking and power control 104 9 2 1 USB Command Code register USBCmdCode 8 1 Power requirements oo o 104 0x4001 8010 oooocccccccccoo 108 8 2 CIOCKS 3 a vee vt es wee Te pana ead ea 104 UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 285 of 290 NXP Semiconductors UM10375 Chapter 20 LPC13xx Supplementary information 9 2 2 USB Command Data register USBCmdData 10 6 Read Chip ID Command OxFD Data read 2 0x4002 0014 ooo 109 Bytes cocina ir ade Ae cas 117 9 3 USB data transfer regis
77. Semiconductors UM10375 9 3 Chapter 3 LPC13xx System configuration Start logic The Deep sleep mode is exited when the start logic indicates an interrupt to the ARM core All PIO port inputs except PIO3_4 and PIO3_5 are connected to the start logic and serve as wake up pins The user must program the start logic registers for each input to set the appropriate edge polarity for the corresponding wake up event Furthermore the interrupts corresponding to each input must be enabled in the NVIC Interrupts O to 39 in the NVIC correspond to 40 PIO pins see Section 3 5 36 The start logic does not require a clock to run because it uses the PIO input signals to generate a clock edge when enabled Therefore the start logic signals should be cleared see Table 3 43 before use The start logic can also be used in normal run mode i e not in Sleep or Deep sleep mode to provide a vectored interrupt using the LPC13xx s input pins 10 PLL System PLL and USB PLL functional description The LPC13xx uses the system PLL to create the clocks for the core and peripherals On the LPC134x parts there is a second identical PLL to create the USB clock DETECT pH LOCK JJ FCLKIN F al irc_osc_clk 1 sys_osc_clk FCLKIN a pa m a FCCO pd wat_osc_c PSEL lt 1 0 gt DIRECT PFD A SYSPLLCLKSEL or pd USBPLLCLKSEL LOCK pe FCLKOUT analog section pd
78. Simultaneous Repeated START conditions from 11 6 3 State Ox28 0 02 nnns 204 two masters ooocooooooooooo 199 11 6 4 State 0x30 o oooooooooo Ay 205 10 10 Data transfer after loss of arbitration 199 11 6 5 Slate 0x38 nakace dasa O 205 10 11 Forced access to the I C bus 199 11 7 Master Receive stateS 205 10 12 12C bus obstructed by a LOW level on SCL or SDA 11 7 1 State 0X40 ocio coi tae ae ew eee 205 200 11 7 2 State 0x48 0 00022 eee eee 205 10 13 BUS COR ii gceesiiaatacedsiey e aden ae en ae ee 200 11 7 3 State Ox50 2 0 0 eee eee 205 10 14 12C state service routines 201 11 7 4 State 0x58 oasis ed eed eek ede 206 10 15 InitialiZatiON oooooooocoooo 201 11 8 Slave Receiver states 206 10 16 12C interrupt service 202 11 8 1 State OxX60 0 00002 eee eee 206 10 17 The state service routines 202 11 8 2 State Ox68 0 00000 206 10 18 Adapting state services to an application 202 11 8 3 State 0X70 arun at ooo Ge tee Se 206 11 Software example Se eee a ah eran ag gente er 202 11 8 4 State 0X78 oooooooooooomooo 207 11 1 Initialization routine o on 202 11 8 5 State 0x80 1 eee 207 11 2 Start Master Transmit function 202 11 8 6 State 0x88 6 6 6 eee eee eee eee 207 11 3 Start Master Receive function 203 11 8 7 State 0x90
79. Terminal Ready output for UART PIO3_2 General purpose digital input output pin PIO3_4 General purpose digital input output pin LPC1311 13 only PIO3_5 General purpose digital input output pin LPC1311 13 only USB_DM USB bidirectional D line LPC1342 43 only USB_DP USB bidirectional D line LPC 1342 43 only 3 3 V input output supply voltage 3 3 V supply voltage to the internal DC DC converter and the ADC Also used as the ADC reference voltage Input to the oscillator circuit and internal clock generator circuits Input voltage must not exceed 1 8 V Output from the oscillator amplifier Thermal pad Connect to ground 11 2 3 4 5 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis 12C bus pads compliant with the 12C bus specification for 12C standard mode and 12C Fast mode Plus 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors configurable hysteresis and analog input When configured as a ADC input digital section of the pad is disabled and the pin is not 5 V tolerant Pad provides USB functions It is designed in accordance with the USB specification revision 2 0 Full speed and Low speed mode only When the system oscillator is not used connect XTALIN and XTALOUT as follows XTALIN can be left floating or can be grounded grounding is preferred to reduce
80. The timer is reset by the match register that is configured to set the PWM cycle length When the timer is reset to zero all currently HIGH match outputs configured as PWM outputs are cleared NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 220 of 290 NXP Semiconductors U M1 0375 Chapter 13 LPC13xx 16 bit counter timer CT16B Table 220 PWM Control Register TMR16BOPWMC address 0x4000 C074 and TMR16B1PWMC address 0x4001 0074 bit description Bit Symbol Description Reset value PWM enable When one PWM mode is enabled for CT16Bn_MATO 0 When zero CT16Bn_MATO is controlled by EMO PWM enable When one PWM mode is enabled for CT16Bn_MAT1 0 When zero CT16Bn_MAT1 is controlled by EM1 PWM enable When one PWM mode is enabled for match channel2 0 or pin CT16B0_MAT2 When zero match channel 2 or pin CT16B0_MAT2 is controlled by EM2 Match channel 2 is not pinned out on timer 1 PWM enable When one PWM mode is enabled for match channel 3 0 When zero match channel 3 is controlled by EM3 Note lt is recommended to use match channel 3 to set the PWM cycle because it is not pinned out 4 32 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 7 13 Rules for single edge controlled PWM outputs 1 All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle timer is set to zero unl
81. Timer s Prescale Counter PC or clear PC and increment Mode Timer Counter TC 00 Timer Mode every rising PCLK edge 01 Counter Mode TC is incremented on rising edges on the CAP input selected by bits 3 2 10 Counter Mode TC is incremented on falling edges on the CAP input selected by bits 3 2 11 Counter Mode TC is incremented on both edges on the CAP input selected by bits 3 2 3 2 Count In counter mode when bits 1 0 in this register are not 00 00 Input select pin CT16Bn_CAPO to be sampled for clocking Select Note If Counter mode is selected in the CTCR register bits 2 0 in the Capture Control Register CCR must be 00 programmed as 000 01 Reserved 10 Reserved 11 Reserved 31 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined PWM Control register TMR16B0PWMC and TMR16B1PWMC The PWM Control Register is used to configure the match outputs as PWM outputs Each match output can be independently set to perform either as PWM output or as match output whose function is controlled by the External Match Register EMR For timer 0 three single edge controlled PWM outputs can be selected on the CT16B0_MAT 2 0 outputs For timer 1 two single edged PWM outputs can be selected on the CT16B1_Mat 1 0 outputs One additional match register determines the PWM cycle length When a match occurs in any of the other match registers the PWM output is set to HIGH
82. V Software can then control the USB_CONNECT signal by writing to the CON bit using the SIE Set Device Status command Vpp 3v3 USB_CONNECT L H A soft connect switch LPC134x Ri 15kQ VBus USB B connector UsB_pP Ps 380 gt gt USB_DM RS 332 4 Vss 002aad939_1 Fig 13 USB SoftConnect interfacing 6 Operational overview UM10375_0 Transactions on the USB bus transfer data between device endpoints and the host The direction of a transaction is defined with respect to the host OUT transactions transfer data from the host to the device IN transactions transfer data from the device to the host All transactions are initiated by the host controller For an OUT transaction the USB ATX receives the bi directional USB_DP and USB_DM signals of the USB bus The Serial Interface Engine SIE receives the serial data from the ATX and converts it into a parallel data stream The parallel data is written to the corresponding endpoint buffer For IN transactions the SIE reads the parallel data from the endpoint buffer in EP_RAM converts it into serial data and transmits it onto the USB bus using the USB ATX NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 105 of 290 NXP Semiconductors U M1 0375 Chapter 9 LPC13xx USB device controller Once data has been received
83. WDT clock source update enable 0x00 Table 3 32 WDTCLKDIV R W 0x0D8 WDT clock divider 0x00 Table 3 33 0x0DC Reserved CLKOUTCLKSEL R W Ox0E0 CLKOUT clock source select 0x00 Table 3 34 CLKOUTUEN R W Ox0E4 CLKOUT clock source update enable 0x00 Table 3 35 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 12 of 290 NXP Semiconductors UM10375 Chapter 3 LPC13xx System configuration Table 5 Register overview system control block base address 0x4004 8000 continued Name Access Address offset Description Reset Reference value CLKOUTDIV R W Ox0E8 CLKOUT clock divider 0x00 Table 3 36 OxOEC OxOFC Reserved PIOPORCAPO R 0x100 POR captured PIO status 0 User Table 3 37 dependent PIOPORCAP1 R 0x104 POR captured PIO status 1 User Table 3 37 dependent 0x108 0x14C Reserved 0x00 E BODCTRL R W 0x150 BOD control 0x00 Table 3 39 0x154 Reserved SYSTCKCAL R W 0x158 System tick counter calibration lt tbd gt Table 3 40 0x15C 0x1FC Reserved STARTAPRPO R W 0x200 Start logic edge control register 0 bottom Table 3 41 32 interrupts STARTERPO R W 0x204 Start logic signal enable register 0 bottom Table 3 42 32 interrupts STARTRSRPOCLR W 0x208 Start logic reset register 0 bottom 32 n a Table 3 43 interrupts STARTSRPO R 0x20C Start logic status register 0 bottom 32 n a Table 3 44 interrupts STARTAPRP1 R W 0x210 Start logic edge control register 1 top 8 Table 3 45 inte
84. all USBCLKUEN R W 0x0C4 USB clock source update enable all USBCLKDIV R W 0x0C8 USB clock source divider all PDSLEEPCFG R W 0x230 Power down states in Deep sleep bits 8 and 10 mode PDAWAKECFG R W 0x234 Power down states after wake up from bits 8 and 10 Deep sleep mode PDRUNCFG R W 0x238 Power down configuration register bits 8 and 10 UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 8 of 290 NXP Semiconductors U M1 0375 Chapter 3 LPC13xx System configuration 2 Introduction The system configuration block controls oscillators the power management unit and clock generation of the LPC13xx Also included in this block are registers for setting the priority for AHB access and a register for remapping flash SRAM and ROM memory areas 3 Pin description UM10375_0 Table 3 4 shows pins that are associated with system control block functions Table 4 Pin summary Pin name Pin Pin description direction CLKOUT O Clockout pin PIOO_0 to PIOO_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_1111 PIO3_0 to PIO3_3L Wake up pins port 0 Wake up pins port 1 Wake up pins port 2 Wake up pins port 3 1 For HVQFN packages applies to P2_0 P3_2 and P3_3 only NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 9 of 290 NXP Semiconductors U M1 0375 Chapter 3 LPC13xx System configuration 4 Clocking and power control
85. and finds that the active buffer B_2 is empty FE 0 Both B_1 and B_2 are empty Software waits for the next endpoint interrupt to occur The active buffer is now B_2 The next data packet sent by the host will be placed in B 2 The following example illustrates how double buffering works for a Bulk IN endpoint in Slave mode Assume that both buffer 1 B_1 and buffer 2 B_2 are empty and that the active buffer is B_1 The interrupt on NAK feature is enabled 1 The host requests a data packet by sending an IN token packet The device responds with a NAK and generates an endpoint interrupt Software clears the endpoint interrupt The device has three packets to send Software fills B_1 with the first packet and sends a SIE Validate Buffer command The active buffer is switched to B_2 Software sends the SIE Select Endpoint command to read the Select Endpoint Register and test the FE bit It finds that B_2 is empty FE 0 and fills B_2 with the second packet Software sends a SIE Validate Buffer command and the active buffer is switched to B_1 4 Software waits for the endpoint interrupt to occur 5 The device successfully sends the packet in B_1 and clears the buffer An endpoint interrupt occurs O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 128 of 290 NXP Semiconductors U M1 0375 UM10375_0 13 2 10 11 Chapter 9 LPC13xx USB device controller Softwa
86. associated state services can be omitted as long as care is taken that the those states can never occur In an application it may be desirable to implement some kind of time out during 12C operations in order to trap an inoperative bus or a lost service routine 11 Software example UM10375_0 11 1 Initialization routine Example to initialize 12C Interface as a Slave and or Master 1 Load I2ADR with own Slave Address enable General Call recognition if needed 2 Enable 12C interrupt 3 Write 0x44 to IZCONSET to set the I2EN and AA bits enabling Slave functions For Master only functions write 0x40 to I2CONSET 11 2 Start Master Transmit function Begin a Master Transmit operation by setting up the buffer pointer and data count then initiating a START Initialize Master data counter Set up the Slave Address to which data will be transmitted and add the Write bit Write 0x20 to I2CONSET to set the STA bit Set up data to be transmitted in Master Transmit buffer Initialize the Master data counter to match the length of the message being sent Exit O oO A N NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 204 of 290 NXP Semiconductors U M1 0375 UM10375_0 Chapter 12 LPC13xx I2C bus interface 11 3 Start Master Receive function 11 5 11 5 1 11 5 2 11 5 3 Begin a Master Receive operation by setting up the buffer pointer and data count t
87. be produced with a bus reset For isochronous endpoints data transfer will happen even if an erroneous packet is received In this case DV bit will not be set for the packet 0 Data is invalid 1 Data is valid 31 11 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined USB Transmit Packet Length register USBTxPLen 0x4002 0024 This indicates the number of bytes still to be transferred from the processor to the RAM The processor has to program this register with the byte length of the packet to be sent before writing to the Transmit Data Register The processor can read this register to determine the number of bytes it has transferred to the memory Remark To transfer an empty packet this register has to be set to 0x00 and a single write operation has to be performed on the Transmit Data Register O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 112 of 290 NXP Semiconductors U M1 0375 UM10375_0 9 3 5 9 3 5 1 Chapter 9 LPC13xx USB device controller Table 136 USB Transmit Packet Length register USBTxPLen address 0x4002 0024 bit description Bit Symbol Value Description Reset value 9 0 PKT_LNGTH The remaining number of bytes to be written to the 0x000 selected endpoint buffer This field is decremented by 4 by hardware after each write to USBTxData When this field decrements to 0 the TxXENDPKT
88. can occur ADOGDR R W 0x004 A D Global Data Register Contains the result of the most recent A D NA conversion 0x008 Reserved ADOINTEN R W 0x00C A D Interrupt Enable Register This register contains enable bits that allow 0x0000 0100 the DONE flag of each A D channel to be included or excluded from contributing to the generation of an A D interrupt ADODRO R W 0x010 A D Channel 0 Data Register This register contains the result of the most NA recent conversion completed on channel 0 ADODR1 R W 0x014 A D Channel 1 Data Register This register contains the result of the most NA recent conversion completed on channel 1 ADODR2 R W 0x018 A D Channel 2 Data Register This register contains the result of the most NA recent conversion completed on channel 2 ADODR3 R W 0x01C A D Channel 3 Data Register This register contains the result of the most NA recent conversion completed on channel 3 ADODR4 R W 0x020 A D Channel 4 Data Register This register contains the result of the most NA recent conversion completed on channel 4 ADODR5 R W 0x024 A D Channel 5 Data Register This register contains the result of the most NA recent conversion completed on channel 5 ADODR6 R W 0x028 A D Channel 6 Data Register This register contains the result of the most NA recent conversion completed on channel 6 ADODR7 R W 0x02C A D Channel 7 Data Register This register contains the result of the most NA recent conversion completed on channel 7 ADOST
89. corresponding GPIODATA register bit is left unchanged ADDRESS 13 2 13 12 11 10 9 8 7 6 5 4 3 2 address 0x098 0 0 data OxFE4 GPIODATA register at address 0x098 ii 5 il z g 1 i 0 bl u unchanged Fig 6 Masked write operation to the GPIODATA register UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 89 of 290 NXP Semiconductors U M1 0375 UM10375_0 Chapter 7 LPC13xx General Purpose I O GPIO Read operation If the address bit associated with the GPIO data bit is HIGH the value is read If the address bit is LOW the GPIO data bit is read as 0 ADDRESS 13 2 13 12 11 10 9 8 7 6 5 4 3 2 address 0x0C4 port pin settings data read 0 0 0 0 0 0 1 o 0 0 0 0 Fig 7 Masked read operation NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 90 of 290 UM10375 Chapter 8 LPC13xx Pin configuration Rev 00 10 19 October 2009 1 How to read this chapter User manual UM10375_0 The LPC13xx parts are available in LQFP48 and HVQFN33 packages The LPC1342 43 parts have dedicated USB pins and additional USB functions on some pins Table 118 LPC13xx pin configuration overview Part LPC1311 LPC1313 LPC1342 LPC1343 HVQFN33 Pin description LQFP48 package Pin description package Figure 8 11 Table 8 120 Figure 8 11 Table 8 120 Figure 8 10 Table 8 119 Figure 8 9 Table 8
90. d cd Fig 4 1 Not on USB PLL System and USB PLL block diagram M Le MSEL lt 4 0 gt UM10375_0 The block diagram of this PLL is shown in Figure 3 4 The input frequency range is 10 MHz to 25 MHz The input clock is fed directly to the Phase Frequency Detector PFD This block compares the phase and frequency of its inputs and generates a control signal when phase and or frequency do not match The loop filter filters these control signals and drives the current controlled oscillator CCO which generates the main clock and optionally two additional phases The CCO frequency range is 156 MHz to 320 MHz These clocks are either divided by 2xP by the programmable post divider to create the output clock s or are sent directly to the output s The main output clock is NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 43 of 290 NXP Semiconductors U M1 0375 UM10375_0 10 1 10 2 10 3 10 4 10 5 Chapter 3 LPC13xx System configuration then divided by M by the programmable feedback divider to generate the feedback clock The output signal of the phase frequency detector is also monitored by the lock detector to signal when the PLL has locked on to the input clock Lock detector The lock detector measures the phase difference between the rising edges of the input and feedback clocks Only when this difference is smaller than the so called
91. flash sector 0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 262 of 290 NXP Semiconductors UM10375 UM10375_0 Chapter 18 LPC13xx Flash memory programming firmware 12 7 Copy RAM to flash lt Flash address gt lt RAM address gt lt no of bytes gt 12 8 Table 263 ISP Copy command Command Input Return Code Description Example c Flash Address DST Destination flash address where data bytes are to be written The destination address should be a 256 byte boundary RAM Address SRC Source RAM address from where data bytes are to be read Number of Bytes Number of bytes to be written Should be 256 512 1024 4096 CMD_SUCCESS SRC_ADDR_ERROR Address not on word boundary DST_ADDR_ERROR Address not on correct boundary SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR Byte count is not 256 512 1024 4096 SECTOR_NOT_PREPARED_FOR WRITE_OPERATION BUSY CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED This command is used to program the flash memory The Prepare Sector s for Write Operation command should precede this command The affected sectors are automatically protected again once the copy command is successfully executed The boot block cannot be written by this command This command is blocked when code read protection is enabled C 0 268467504 512 lt CR gt lt LF gt copies 512 bytes from the RAM address
92. for the peripheral base address 5 Pin description Table 14 221 gives a brief summary of each of the counter timer related pins Table 221 Counter timer pin description Pin Type Description CT32B0_CAPO Input Capture Signals CT32B1_CAPO A transition on a capture pin can be configured to load one of the Capture Registers with the value in the Timer Counter and optionally generate an interrupt The counter timer block can select a capture signal as a clock source instead of the PCLK derived clock For more details see Section 14 7 11 Count Control Register TMR32BOCTCR and TMR32B1TCR on page 231 CT32B0_MAT 3 0 Output External Match Output of CT32B0 1 CT32B1_MAT 3 0 When a match register TMR32B0 1MR3 0 equals the timer counter TC this output can either toggle go LOW go HIGH or do nothing The External Match Register EMR and the PWM Control register PWMCON control the functionality of this output 6 Clocking and power control The peripheral clocks PCLK to the 32 bit timers are provided by the system clock see Figure 3 3 These clocks can be disabled through bits 9 and 10 in the AHBCLKCTRL register Section 3 5 18 for power savings 7 Register description 32 bit counter timerO contains the registers shown in Table 14 222 and 32 bit counter timer1 contains the registers shown in Table 14 223 More detailed descriptions follow Table 222 Register overview 32 bit counter timer 0 C
93. formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 2 2 Disclaimers General Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof UM10375_0 Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in medical military aircraft space or life support equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion
94. is not possible to read or write the upper byte of a word register separately NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 6 of 290 NXP Semiconductors U M1 0375 Chapter 2 LPC13xx Memory mapping LPC1311 13 42 43 AHB peripherals 0x5020 0000 4GB OxFFFF FFFF 127 4 reserved Ss reserved SS 0x5004 0000 4 8 0x5003 0000 0x5002 0000 0x5020 0000 AHB peripherals pr AS i 0x5001 0000 0x5000 0000 reserved APB peripherals 0x4008 0000 0x4008 0000 1GB APB peripherals 0x4000 0000 AAT z reserved s 0x4004 C000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 i P 0x2400 0000 AHB SRAM bit band alias addressing 0x2200 0000 reserved MU 0x4003 8000 0 5 GB 0x2000 0000 10 13 reserved reserved a Ox1FFF 4000 0x4002 8000 0x4002 4000 USB LPC1342 43 only 0x4002 0000 reserved 16 kB boot ROM Ox1FFF 0000 Sas reserved e 0x1000 8000 0x4001 C000 reserved CT32B1 0x4001 8000 0x1000 2000 CT32B0 0x4001 4000 8 kB SRAM LPC1313 1343 cri6B1 0x4001 0000 I code D code 0x1000 1000 CT16B0 0x4000 C000 memory space 4kB SRAM LPC1311 1342 bo 000 0x4000 8000 reserved 0x4000 4000 0x4000 0000 0x0000 8000 32 kB on chip flash LPC1313 43 0x0000 4000 512 byte 16 kB on chip flash LPC1342 ox00002000 TF lt A 00000 0200 active interrupt vectors chi 0x0000 0000 0GB 8 kB on chip flash
95. it is compared to the I2ADDRn register associated with that mask register In other words bits in an I2ADDRn register which are masked are not taken into account in determining an address match On reset all mask register bits are cleared to 0 The mask register has no effect on comparison to the General Call address 0000000 Bits 31 8 and bit 0 of the mask registers are unused and should not be written to These bits will always read back as zeros When an address match interrupt occurs the processor will have to read the data register 12DAT to determine what the received address was that actually caused the match O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 179 of 290 NXP Semiconductors U M1 0375 Chapter 12 LPC13xx I2C bus interface Table 198 12C Mask registers IZMASK O 1 2 3 0x4000 00 30 34 38 3C bit description Bit Symbol Description Reset value 0 Reserved User software should not write ones to reserved bits 0 This bit reads always back as 0 7 1 MASK Mask bits 0x00 31 Reserved User software should not write ones to reserved bits 0 8 These bits read always back as 0 s 8 1 C operating modes UM10375_0 8 1 In a given application the 12C block may operate as a master a slave or both In the slave mode the 12C hardware looks for any one of its four slave addresses and the General Call address If one of these addresses
96. mode As described above this will prevent the module from having any control over the IC clock line 1 When this bit is set the I2C module may exercise the same control over the clock line that it would in normal operation This means that acting as a slave peripheral the 12 module can stretch the clock line hold it low until it has had time to respond to an 12C interrupt O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 177 of 290 NXP Semiconductors U M1 0375 UM10375_0 7 7 1 PAR 7 8 Chapter 12 LPC13xx I2C bus interface Table 195 I2C Monitor mode control register I2CMMCTRLO 0x4000 001C bit description Bit Symbol Value Description Reset value 3 MATCH_ALL Select interrupt register match 0 0 When this bit is cleared an interrupt will only be generated when a match occurs to one of the up to four address registers described above That is the module will respond as anormal slave as far as address recognition is concerned 1 When this bit is set to 1 and the 12C is in monitor mode an interrupt will be generated on ANY address received This will enable the part to monitor all traffic on the bus 1 When the ENA_SCL bit is cleared and the 12C no longer has the ability to stall the bus interrupt response time becomes important To give the part more time to respond to an 12C interrupt under these conditions a DATA _BUFFER register is used Se
97. modes For each mode a buffer is used for transmission and reception The initialization routine performs the following functions 2ADR is loaded with the part s own slave address and the General Call bit GC e The 12C interrupt enable and interrupt priority bits are set O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 203 of 290 NXP Semiconductors U M1 0375 Chapter 12 LPC13xx I2C bus interface The slave mode is enabled by simultaneously setting the I2EN and AA bits in I2CON and the serial clock frequency for master modes is defined by is defined by loading the I2SCLH and I2SCLL registers The master routines must be started in the main program The I2C hardware now begins checking the 12C bus for its own slave address and General Call If the General Call or the own slave address is detected an interrupt is requested and I2STAT is loaded with the appropriate state information 10 16 12C interrupt service When the 12C interrupt is entered I2STAT contains a status code which identifies one of the 26 state services to be executed 10 17 The state service routines Each state routine is part of the 12C interrupt routine and handles one of the 26 states 10 18 Adapting state services to an application The state service examples show the typical actions that must be performed in response to the 26 12C state codes If one or more of the four 12C operating modes are not used the
98. of 290 NXP Semiconductors U M1 0375 Chapter 10 LPC13xx UART A 0x41 or a 0x61 start bitO biti bit2 bit3 bit4 bits bit6 bit7 parity stop UARTn RX start bit UOACR start rate counter 16xbaud_rate 16 cycles 16 cycles a Mode 0 start bit and LSB are used for auto baud OAO 0x41 or a 0x61 start bitO biti bit2 bit8 bit4 bits bit6 bit7 parity stop UARTn RX start bit LSB of A or a UOACR start rate counter 16 cycles b Mode 1 only start bit is used for auto baud Fig 17 Auto baud a mode 0 and b mode 1 waveform 5 15 UART Fractional Divider Register UOFDR 0x4000 8028 The UART Fractional Divider Register UOFDR controls the clock pre scaler for the baud rate generation and can be read and written at the user s discretion This pre scaler takes the APB clock and generates an output clock according to the specified fractional requirements Important If the fractional divider is active DIVADDVAL gt 0 and DLM 0 the value of the DLL register must be 3 or greater UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 146 of 290 NXP Semiconductors U M1 0375 UM10375_0 5 15 1 Chapter 10 LPC13xx UART Table 167 UART Fractional Divider Register UOFDR address 0x4000 8028 bit description Bit Function Value Description Reset value 3 0 DIVADDVAL 0 Baud rate generation
99. of edges or no changes in the level of the selected CAP input Only if the identified event occurs and the event corresponds to the one selected by bits 1 0 in the CTCR register will the Timer Counter register be incremented Effective processing of the externally supplied clock to the counter has some limitations Since two successive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input the frequency of the CAP input can not exceed one half of the PCLK clock Consequently duration of the HIGH LOW levels on the same CAP input in this case can not be shorter than 1 2 x PCLK Table 230 Count Control Register TMR32BOCTCR address 0x4001 4070 and TMR32B1TCR address 0x4001 8070 bit description Bit Symbol Value Description Reset value 1 0 Counter This field selects which rising PCLK edges can increment 00 Timer Timer s Prescale Counter PC or clear PC and increment Mode Timer Counter TC 00 Timer Mode every rising PCLK edge 01 Counter Mode TC is incremented on rising edges on the CAP input selected by bits 3 2 10 Counter Mode TC is incremented on falling edges on the CAP input selected by bits 3 2 11 Counter Mode TC is incremented on both edges on the CAP input selected by bits 3 2 3 2 Count When bits 1 0 in this register are not 00 these bits select 00 Input which CAP pin is sampled for clocking Select CT32Bn 00 CAPO 01 Reserved 10 Reserved 11 Reserved Note If Counter mode is
100. of the size of the LPC134x flash in the host s folder with the default name firmware bin The firmware bin file can be deleted and a new file can be copied into the directory thereby updating the user code in flash Note that the name of the new flash image file is not important After a reset or a power cycle the new file is visible in the host s file system under it s default name firmware bin Remark The only Windows Linux commands supported for the LPC134x flash image folder are copy and delete Three Code Read Protection CRP levels can be enabled for flash images updated through USB see Section 18 11 for details The volume label on the MSCD indicates the CRP status O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 254 of 290 NXP Semiconductors UM10375 UM10375_0 Chapter 18 LPC13xx Flash memory programming firmware Table 251 CRP levels for USB boot images CRP status Volume label No CRP CRP DISABLD CRP1 CRP1 ENABLD CRP2 CRP2 ENABLD CRP3 CRP3 ENABLD Description The user flash can be read or written The user flash content cannot be read but can be updated The flash memory sectors are updated depending on the new firmware image The user flash content cannot be read but can be updated The entire user flash memory is erased before writing the new firmware image The user flash content cannot be read or updated The boot loader always exec
101. operates With respect to the SK rising edge previous to this edge CS must have a hold of at least one SK period tserup 2 tsk t SK HOLD amp SK CS Fig 27 Microwire frame format setup and hold details O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 169 of 290 UM10375 Chapter 12 LPC13xx I2C bus interface Rev 00 10 19 October 2009 User manual 1 How to read this chapter 2 Features The 12C bus block is identical for all LPC13xx parts 3 Applications Standard C compliant bus interfaces may be configured as Master Slave or Master Slave Arbitration is handled between simultaneously transmitting masters without corruption of serial data on the bus Programmable clock allows adjustment of 12C transfer rates Data transfer is bidirectional between masters and slaves Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization is used as a handshake mechanism to suspend and resume serial transfer Supports Fast mode Plus Optional recognition of up to four distinct slave addresses Monitor mode allows observing all 12C bus traffic regardless of slave address 12C bus can be used for test and diagnostic purposes The 12C bus contains a standard 2C compliant bus interface with two pins Interfaces to external 12C standard parts such as serial RAMs LCDs
102. optionally the USB block The MAINCLKUEN register see Section 3 5 16 must be toggled from LOW to HIGH for the update to take effect Table 20 Main clock source select register MAINCLKSEL address 0x4004 8070 bit description Bit Symbol Value Description Reset value 1 0 SEL Cock source for main clock 0x00 00 IRC oscillator 01 Input clock to system PLL 10 WDT oscillator 11 System PLL clock out 31 22 Reserved 0x00 Main clock source update enable register This register updates the clock source of the main clock with the new input clock after the MAINCLKSEL register has been written to In order for the update to take effect first write a zero to the MAINCLKUEN register and then write a one to MAINCLKUEN Table 21 Main clock source update enable register MAINCLKUEN address 0x4004 8074 bit description Bit Symbol Value Description Reset value 0 ENA Enable main clock source update 0x0 0 No change 1 Update clock source 31 1 Reserved 0x00 System AHB clock divider register This register divides the main clock to provide the system clock to the core memories and the peripherals The system clock can be shut down completely by setting the DIV bits to 0x0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 21 of 290 NXP Semiconductors UM10375 5 18 Chapter 3 LPC13xx System configuration Table 22 System AHB clock divider register SYSAHBCLKDIV ad
103. or sent the endpoint buffer can be read or written The CPU transfers data between RAM and the endpoint buffer using the register interface See Section 9 12 Functional description for a detailed description 7 Pin description The device controller can access one USB port Table 123 USB device pin description Name Direction Description Veus l Vgus status input When this function is not enabled via its corresponding IOCONFIG register it is driven HIGH internally USB _ CONNECT O SoftConnect control signal USB_FTOGGLE O USB 1 ms Sor signal USB_DP 1 0 Positive differential data USB_DM 1 0 Negative differential data 8 Clocking and power control This section describes the clocking and power management features of the USB Device Controller 8 1 Power requirements The USB protocol insists on power management by the device This becomes very critical if the device draws power from the bus bus powered device The following constraints should be met by a bus powered device 1 Adevice in the non configured state should draw a maximum of 100 mA from the bus 2 A configured device can draw only up to what is specified in the Max Power field of the configuration descriptor The maximum value is 500 mA 3 A suspended device can draw a maximum of 500 uA 8 2 Clocks The USB device controller clocks are shown in Table 9 124 Table 124 USB device controller clock sources Source Clock name Descri
104. pin of the slave device between each data transfer to enable the serial peripheral data write On completion of the continuous transfer the SSEL pin is returned to its idle state one SCK period after the last bit has been captured NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 166 of 290 NXP Semiconductors U M1 0375 7 2 5 7 3 UM10375_0 Chapter 11 LPC13xx SSP SPI format with CPOL 1 CPHA 1 The transfer signal sequence for SPI format with CPOL 1 CPHA 1 is shown in Figure 11 24 which covers both single and continuous transfers SCK SSEL MOSI MISO A 4to 16 bits gt Fig 24 SPI Frame Format with CPOL 1 and CPHA 1 In this configuration during idle periods e The CLK signal is forced HIGH e SSEL is forced HIGH e The transmit MOSI MISO pad is in high impedance If the SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW Master s MOSI is enabled After a further one half SCK period both master and slave data are enabled onto their respective transmission lines At the same time the SCK is enabled with a falling edge transition Data is then captured on the rising edges and propagated on the falling edges of the SCK signal After all bits have been transferred in the case of a single word transmission the SSEL line is returned to its idl
105. pre scaler divisor value If this field is 0 O fractional baud rate generator will not impact the UART baud rate 7 4 MULVAL 1 Baud rate pre scaler multiplier value This field must be 1 greater or equal 1 for UART to operate properly regardless of whether the fractional baud rate generator is used or not 31 8 NA Reserved user software should not write ones to reserved 0 bits The value read from a reserved bit is not defined This register controls the clock pre scaler for the baud rate generation The reset value of the register keeps the fractional capabilities of UART disabled making sure that UART is fully software and hardware compatible with UARTs not equipped with this feature The UART baud rate can be calculated as PCLK UART paudrate 16 x 256 x UODLM UODLL x 1 DivAddVal MulVal Where UART_PCLK is the peripheral clock UODLM and UODLL are the standard UART baud rate divider registers and DIVADDVAL and MULVAL are UART fractional baud rate generator specific parameters The value of MULVAL and DIVADDVAL should comply to the following conditions 1 1 lt MULVAL lt 15 2 0 lt DIVADDVAL lt 14 3 DIVADDVAL lt MULVAL The value of the UOFDR should not be modified while transmitting receiving data or data may be lost or corrupted If the UOFDR register value does not comply to these two requests then the fractional divider output is undefined If DIVADDVAL is zero then the fractional divider is
106. read 1 byte optional When an OUT packet sent by the host has been received successfully an internal hardware FIFO status Buffer_Full flag is set All subsequent packets will be refused by returning a NAK When the device software has read the data it should free the buffer by issuing the Clear Buffer command This clears the internal Buffer_Full flag When the buffer is cleared new packets will be accepted When bit 0 of the optional data byte is 1 the previously received packet was over written by a SETUP packet The Packet over written bit is used only in control transfers According to the USB specification a SETUP packet should be accepted irrespective of the buffer status The software should always check the status of the PO bit after reading the SETUP data If it is set then it should discard the previously read data clear the PO bit by issuing a Select Endpoint Clear Interrupt command read the new SETUP data and again check the status of the PO bit See Section 9 12 Functional description for a description of when this command is used O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 123 of 290 NXP Semiconductors U M1 0375 10 14 Chapter 9 LPC13xx USB device controller Table 149 Clear Buffer Register bit description Bit Symbol Value Description Reset value 0 PO Packet over written bit This bit is only applicable to the control 0 endpoint EPO 0 The previously
107. received packet is intact 1 The previously received packet was over written by a later SETUP packet 7 1 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined Validate Buffer Command OxFA Data none When the CPU has written data into an IN buffer software should issue a Validate Buffer command This tells hardware that the buffer is ready for sending on the USB bus Hardware will send the contents of the buffer when the next IN token packet is received Internally there is a hardware FIFO status flag called Buffer_Full This flag is set by the Validate Buffer command and cleared when the data has been sent on the USB bus and the buffer is empty A control IN buffer cannot be validated when its corresponding OUT buffer has the Packet Over written PO bit see the Clear Buffer Register set or contains a pending SETUP packet For the control endpoint the validated buffer will be invalidated when a SETUP packet is received See Section 9 12 Functional description for a description of when this command is used Remark For sending an empty packet the Validate Buffer command should also be used 11 USB device controller initialization UM10375_0 11 1 The LPC134x USB device controller initialization includes initialization of the USB clock and the device controller USB clock configuration 1 Enable the PLL for USB clock if the PLL is used
108. reserved User manual Rev 00 10 19 October 2009 172 of 290 NXP Semiconductors U M1 0375 Chapter 12 LPC13xx I2C bus interface Table 186 Register overview I2C base address 0x4000 0000 continued Name Access Address Description Reset offset valuel I2MASKO R W 0x030 12C Slave address mask register 0 This mask register is associated 0x00 I2MASK1 R W I2MASK2 R W 12MASK3 R W with 12ADRO to determine an address match The mask register has no effect when comparing to the General Call address 0000000 0x034 12C Slave address mask register 1 This mask register is associated 0x00 with 12ADRO to determine an address match The mask register has no effect when comparing to the General Call address 0000000 0x038 12C Slave address mask register 2 This mask register is associated 0x00 with 12ADRO to determine an address match The mask register has no effect when comparing to the General Call address 0000000 0x03C 12C Slave address mask register 3 This mask register is associated 0x00 with 12ADRO to determine an address match The mask register has no effect when comparing to the General Call address 0000000 1 Reset value reflects the data stored in used bits only lt does not include reserved bits content 7 1 UM10375_0 12C Control Set register IZCONSET 0x4000 0000 The IZCONSET registers control setting of bits in the I2CON register that controls operation of the
109. reset input A LOW on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 PIO0_0 General purpose digital input output pin PIO0_1 General purpose digital input output pin A LOW level on this pin during reset starts the ISP command handler or the USB device enumeration USB on LPC1343 only see description of PIOO_3 CLKOUT Clockout pin CT32B0_MAT2 Match output 2 for 32 bit timer 0 USB_FTOGGLE USB 1 ms Start of Frame signal LPC1343 only PIOO_2 General purpose digital input output pin SSEL Slave select for SSP CT16B0_CAPO Capture input 0 for 16 bit timer 0 PIO0_3 General purpose digital input output pin LPC1343 only A LOW level on this pin during reset starts the ISP command handler a HIGH level starts the USB device enumeration USB_VBUS Monitors the presence of USB bus power LPC1343 only PIOO_4 General purpose digital input output pin SCL 12C bus clock input output High current sink only if 12C Fast mode Plus is selected in the I O configuration register PIO0_5 General purpose digital input output pin SDA C bus data input output High current sink only if 12C Fast mode Plus is selected in the I O configuration register PIOO_6 General purpose digital input output pin USB_CONNECT Signal used to switch an external 1 5 KQ resistor under software control Us
110. reset status input PIO3_5 Reserved Reset value User implementation dependent User implementation dependent User implementation dependent User implementation dependent User implementation dependent User implementation dependent User implementation dependent User implementation dependent User implementation dependent User implementation dependent 5 34 BOD control register The BOD control register selects four separate threshold values for sending a BOD interrupt to the NVIC Only one level is allowed for forced reset Table 39 BOD control register BODCTRL address 0x4004 8150 bit description Bit 1 0 3 2 Symbol BODRSTLEV BODINTVAL BODRSTENA Value Description BOD reset level Reset value 0x00 00 The reset assertion threshold voltage is 1 49 V the reset de assertion threshold voltage is 1 64 V 01 11 Reserved BOD interrupt level 0x00 00 The interrupt assertion threshold voltage is 1 69 V the interrupt de assertion threshold voltage is 1 84 V 01 The interrupt assertion threshold voltage is 2 29 V the interrupt de assertion threshold voltage is 2 44 V 10 The interrupt assertion threshold voltage is 2 59 V the interrupt de assertion threshold voltage is 2 74 V 11 The interrupt assertion threshold voltage is 2 87 V the interrupt de assertion threshold voltage is 2 98 V BOD reset enable 0 Disable reset function 1 Enable reset function Reserved 0x0 0x00 U
111. s data exchange with a USB host controller Table 121 USB related acronyms abbreviations and definitions used in this chapter Acronym abbreviation Description AHB Advanced High performance bus ATLE Auto Transfer Length Extraction ATX Analog Transceiver EOP End Of Packet EP Endpoint EP_RAM Endpoint RAM FS Full speed LED Light Emitting Diode LS Low Speed MPS Maximum Packet Size NAK Negative Acknowledge PLL Phase Locked Loop RAM Random Access Memory SOF Start Of Frame SIE Serial Interface Engine UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 102 of 290 NXP Semiconductors U M1 0375 Chapter 9 LPC13xx USB device controller Table 121 USB related acronyms abbreviations and definitions used in this chapter Acronym abbreviation Description SRAM Synchronous RAM UDCA USB Device Communication Area USB Universal Serial Bus 3 Features e Fully compliant with the USB 2 0 specification full speed e Supports 10 physical 5 logical endpoints e Supports Control Bulk Interrupt and Isochronous endpoints e Supports SoftConnect feature e Double buffer implementation for one Bulk and one Isochronous endpoint 4 Fixed endpoint configuration Table 9 122 shows the supported endpoint configurations The packet size is fixed for each type of end point Table 122 Fixed endpoint configuration Logical Physical Endpoint type Direction Packet size Double bu
112. selected in the TnCTCR the 3 bits for that input in the Capture Control Register TnCCR must be programmed as 000 31 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined PWM Control Register TMR32BOPWMC and TMR32B1PWMC The PWM Control Register is used to configure the match outputs as PWM outputs Each match output can be independently set to perform either as PWM output or as match output whose function is controlled by the External Match Register EMR For each timer a maximum of three single edge controlled PWM outputs can be selected on the MATn 2 0 outputs One additional match register determines the PWM cycle length When a match occurs in any of the other match registers the PWM output is set to O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 232 of 290 NXP Semiconductors U M1 0375 Chapter 14 LPC13xx 32 bit counter timer CT32B HIGH The timer is reset by the match register that is configured to set the PWM cycle length When the timer is reset to zero all currently HIGH match outputs configured as PWM outputs are cleared Table 231 PWM Control Register TMR32BOPWMC 0x4001 4074 and TMR32B1PWWMC 0x4001 8074 bit description Bit Symbol Description Reset value 0 PWM enable When one PWM mode is enabled for CT32Bn_MATO 0 When zero CT32Bn_MATO is controlled by EMO 1 PWM enable When one PW
113. set to logic 1 to enable the 12C block The AA bit must be set to enable the 12C block to acknowledge its own slave address or the General Call address STA STO and SI must be reset When I2ADR and I2CON have been initialized the 12C block waits until it is addressed by its own slave address followed by the data direction bit which must be 0 W for the 12C block to operate in the slave receiver mode After its own slave address and the W bit have been received the serial interrupt flag Sl is set and a valid status code can be read from I2STAT This status code is used to vector to a state service routine The appropriate action to be taken for each of these status codes is detailed in Table 12 207 The slave receiver mode may also be entered if arbitration is lost while the 12C block is in the master mode see status 0x68 and 0x78 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 189 of 290 NXP Semiconductors U M1 0375 Chapter 12 LPC13xx I2C bus interface If the AA bit is reset during a transfer the 12C block will return a not acknowledge logic 1 to SDA after the next received data byte While AA is reset the 12C block does not respond to its own slave address or a General Call address However the 12C bus is still monitored and address recognition may be resumed at any time by setting AA This means that the AA bit may be used to temporarily isolate the 12C block from the 12C bus
114. slave data have been set the SCK master clock pin goes HIGH after one further half SCK period The data is captured on the rising and propagated on the falling edges of the SCK signal In the case of a single word transmission after all bits of the data word have been transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured However in the case of continuous back to back transmissions the SSEL signal must be pulsed HIGH between each data word transfer This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the CPHA bit is logic zero Therefore the master device must raise the SSEL pin of the slave device between each data transfer to enable the serial peripheral data write On completion of the continuous transfer the SSEL pin is returned to its idle state one SCK period after the last bit has been captured 7 2 3 SPI format with CPOL 0 CPHA 1 The transfer signal sequence for SPI format with CPOL 0 CPHA 1 is shown in Figure 11 22 which covers both single and continuous transfers UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 164 of 290 NXP Semiconductors U M1 0375 7 2 4 UM10375_0 Chapter 11 LPC13xx SSP SCK SSEL MOSI MISO lt M _ 4t0 16 bits gt Fig 22 SPI frame format with CPOL 0 and CPHA 1 In this co
115. stable USB clock see Table 3 18 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 38 of 290 NXP Semiconductors U M1 0375 6 Reset Chapter 3 LPC13xx System configuration 5 47 Device ID register This device ID register is a read only register and contains the device ID for each LPC13xx part This register is also read by the ISP IAP commands see Section 18 12 11 and Section 18 13 9 Table 52 Device ID register DEVICE_ID address 0x4004 83F4 bit description Bit Symbol Value Description Reset value 31 0 DEVICEID Device ID for LPC13xx parts part dependent 0x2C42 502B LPC1311FHN33 0x2C40 102B LPC1313FHN33 0x2C40 102B LPC1313FBD48 0x3D01 402B LPC1342FHN33 0x3D00 002B LPC1343FHN33 0x3D00 002B LPC1343FBD48 Reset has four sources on the LPC13xx the RESET pin Watchdog Reset Power On Reset POR and Brown Out Detect BOD In addition there is a software reset The RESET pin is a Schmitt trigger input pin Assertion of chip Reset by any source once the operating voltage attains a usable level starts the IRC causing reset to remain asserted until the external Reset is de asserted the oscillator is running and the flash controller has completed its initialization On the assertion of a reset source external to the Cortex M3 CPU POR BOD reset External reset and Watchdog reset the IRC starts up After the IRC start up time maximum of 6 us on power up
116. starting at the upper left corner with pin 1 PIO2_6 See Table 5 62 for a listing of IOCON registers ordered by port number Table 61 Register overview I O configuration block base address 0x4004 4000 Name Access Address Description Reset offset value IOCON_PIO2_6 R W 0x000 I O configuration for pin PlO2_6 OxDO R W 0x004 Reserved IOCON_PIO2_0 R W 0x008 O configuration for pin PIO2_0 DTR OxDO IOCON_RESET_PIO0_0 R W 0x00C O configuration for pin RESET PIO0_0 OxDO IOCON_PIOO_1 R W 0x010 I O configuration for pin PIOO_1 CLKOUT OxDO CT32B0_MAT2 USB_FTOGGLE IOCON_PIO1_8 R W 0x014 I O configuration for pin PIO1_8 CT16B1_CAPO 0xDO R W 0x018 Reserved IOCON_PIOO_2 R W 0x01C I O configuration for pin PIOO_2 SSEL OxDO CT16B0_CAPO IOCON_PIO2_7 R W 0x020 I O configuration for pin PIO2_7 0xDO IOCON_PIO2_8 R W 0x024 I O configuration for pin PlO2_8 0xDO UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 54 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 61 Register overview I O configuration block base address 0x4004 4000 Name Access Address Description Reset offset value IOCON_PIO2_1 R W 0x028 O configuration for pin PIO2_1 DSR 0xDO IOCON_PIOO_3 R W 0x02C I O configuration for pin PIOO_3 USB_VBUS OxDO IOCON_PIOO_4 R W 0x030 I O configuration for pin PIOO_4 SCL 0xCO IOCON_PIOO_5 R W 0x034 I O configuration for pin PlOO_5 SDA 0xCO
117. the I O configuration register PIOO_5 General purpose digital input output pin SDA I2C bus data input output High current sink only if 12 Fast mode Plus is selected in the I O configuration register PIOO_6 General purpose digital input output pin USB_CONNECT Signal used to switch an external 1 5 kQ resistor under software control Used with the SoftConnect USB feature LPC 1342 43 only SCK Serial clock for SSP PIO0_7 General purpose digital input output pin high current output driver CTS Clear To Send input for UART PIO0_8 General purpose digital input output pin MISO Master In Slave Out for SSP CT16B0_MATO Match output O for 16 bit timer 0 PIOO_9 General purpose digital input output pin MOSI Master Out Slave In for SSP CT16B0_MAT1 Match output 1 for 16 bit timer 0 SWO Serial wire trace output O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 99 of 290 NXP Semiconductors UM10375 Chapter 8 LPC13xx Pin configuration Table 120 LPC1311 13 42 43 HVQFN33 pin description table continued Symbol SWCLK PIOO_10 SCK CT16B0_MAT2 TDI PIOO_11 ADO CT32B0_MAT3 TMS PI01_0 AD1 CT32B1_CAPO TDO PIO1_1 AD2 CT32B1_MATO TRST PIO1_2 AD3 CT32B1_MAT1 SWDIO PIO1_3 AD4 CT32B1_MAT2 PIO1_4 AD5 CT32B1_MAT3 WAKEUP PIO1_5 RTS CT32B0_CAPO PIO1_6 RXD CT32B0_MATO PI01_7 TXD CT32B0_MAT1
118. the IRC provides a stable clock output 1 The boot code in the ROM starts The boot code performs the boot tasks and may jump to the flash 2 The flash is powered up This takes approximately 100 us Then the flash initialization sequence is started which takes about 250 cycles When the internal Reset is removed the processor begins executing at address 0 which is initially the Reset vector mapped from the boot block At that point all of the processor and peripheral registers have been initialized to predetermined values 7 Brown out detection UM10375_0 The LPC13xx includes four levels for monitoring the voltage on the Vpp 3va pin If this voltage falls below one of the four selected levels the BOD asserts an interrupt signal to the NVIC This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt if not software can monitor the signal by reading a dedicated status register An additional threshold level can be selected to cause a forced reset of the chip O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 39 of 290 NXP Semiconductors U M1 0375 Chapter 3 LPC13xx System configuration 8 Power management The LPC13xx support a variety of power control features Power and clocks to selected blocks of the LPC13xx can be optimized for power consumption when the chip is running In addition there are three special mo
119. the WAKEUP pin Deep power down mode is entered by using the ARM WIFI instruction and setting the DPDEN bit in the PCON register see Table 4 57 Pulsing the WAKEUP pin wakes up the LPC13xx from Deep power down During Deep power down mode the contents of the SRAM are not retained however the chip can retain data in four general purpose registers For details see Section 4 1 9 Deep sleep mode UM10375_0 9 1 9 2 The Deep sleep mode is a highly configurable mode for saving power see Section 3 8 3 Entering Deep sleep mode is controlled by the Deep sleep negotiator which is part of the ARM Cortex M3 core and the Deep sleep finite state machine The wake up process from Deep sleep mode is initiated by the start logic After wake up the power state of the analog blocks is determined by the PDAWAKECFG register Entering Deep sleep mode Deep sleep mode is entered by using the ARM WFI instruction and setting the SLEEPDEEP bit in the ARM Cortex M3 SCR register The Deep sleep negotiator causes the LPC13xx to hold entering Deep sleep mode until the ARM Cortex M3 core acknowledges the sleep hold request During the hold time the ARM core can still exit the Power down sequence Furthermore the ARM core can choose to de assert the hold request during sleep mode e g if required to do so by the debugger in which case the Deep sleep request will be de asserted as well The Deep sleep finite state machine ensures that while entering
120. the first 512 bytes starting from address zero The first 512 bytes can be re mapped to RAM Reinvoke ISP Table 281 Reinvoke ISP Command Input Return Code Result Description Compare Command code 5719 None None This command is used to invoke the bootloader in ISP mode It maps boot vectors sets PCLK CCLK configures UART pins RXD and TXD resets counter timer CT32B1 and resets the UOFDR see Table 10 167 This command may be used when a valid user program is present in the internal flash memory and the PIO0_1 pin is not accessible to force the ISP mode NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 271 of 290 NXP Semiconductors UM10375 Chapter 18 LPC13xx Flash memory programming firmware 13 9 ReadUID Table 282 IAP ReadUID command Command Input Return Code Compare Command code 589 CMD_SUCCESS Result Result0 The first 32 bit word at the lowest address Result1 The second 32 bit word Result2 The third 32 bit word Result3 The fourth 32 bit word Description This command is used to read the unique ID 13 10 IAP Status Codes Table 283 IAP Status Codes Summary Status Mnemonic Code 0 oD 10 11 CMD_SUCCESS INVALID_ COMMAND SRC_ADDR_ERROR DST_ADDR_ERROR SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR INVALID_ SECTOR SECTOR_NOT_BLANK SECTOR_NOT_PREPARED_ FOR_WRITE_OPERATION COMPARE_
121. the register is empty and the CCEMPTY bit of USBDevintSt register is set See Section 9 10 for details USBCmdCode is a write only register O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 110 of 290 NXP Semiconductors U M1 0375 UM10375_0 9 2 2 9 3 9 3 1 Chapter 9 LPC13xx USB device controller Table 131 USB Command Code register USBCmdCode address 0x4002 0010 bit description Bit Symbol Value Description Reset value 7 0 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 15 8 CMD_PHASE The command phase 0x00 0x01 Read 0x02 Write 0x05 Command 23 16 CMD_CODE This is a multi purpose field When CMD_PHASE is 0x00 CMD_WDATA Command or Read this field contains the code for the command CMD_CODE When CMD_PHASE is Write this field contains the command write data CMD_WDATA 31 24 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined USB Command Data register USBCmdData 0x4002 0014 This register contains the data retrieved after executing a SIE command When the data is ready to be read the CD_FULL bit of the USBDevintSt register is set See Table 9 126 for details USBCmdData is a read only register Table 132 USB Command Data register USBCmdData address 0x4002 0014 bit description Bit Symbol Description Reset valu
122. the same Software can set different duty cycles on SCL by setting these two registers For example the 12C bus specification defines the SCL low time and high time at different values for a Fast mode and Fast mode Plus 12C 12C Control Clear register IZCONCLR 0x4000 0018 The I2CONCLR registers control clearing of bits in the I2CON register that controls operation of the 12C interface Writing a one to a bit of this register causes the corresponding bit in the 12C control register to be cleared Writing a zero has no effect Table 194 I C Control Clear register IZCONCLR 0x4000 0018 bit description Bit Symbol Description Reset value 1 0 Reserved User software should not write ones to reserved bits The NA value read from a reserved bit is not defined 2 AAC Assert acknowledge Clear bit 3 SIC 12C interrupt Clear bit 0 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 176 of 290 NXP Semiconductors U M1 0375 UM10375_0 7 7 Chapter 12 LPC13xx I2C bus interface Table 194 I2C Control Clear register IZCONCLR 0x4000 0018 bit description Bit Symbol Description Reset value 4 Reserved User software should not write ones to reserved bits The NA value read from a reserved bit is not defined 5 STAC START flag Clear bit 6 I2ENC 12C interface Disable bit 7 Reserved User software should not write ones to reserved bits The NA value read from a reserved bit i
123. to change state It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge When the CPHA phase control bit is LOW data is captured on the first clock edge transition If the CPHA clock phase control bit is HIGH data is captured on the second clock edge transition SPI format with CPOL 0 CPHA 0 Single and continuous transmission signal sequences for SPI format with CPOL 0 CPHA 0 are shown in Figure 11 21 a Single transfer with CPOL 0 and CPHA 0 SCK SSEL MOSI MISO cm 4t016 bits gt UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 163 of 290 NXP Semiconductors U M1 0375 Chapter 11 LPC13xx SSP b Continuous transfer with CPOL 0 and CPHA 0 Fig 21 SPI frame format with CPOL 0 and CPHA 0 a Single and b Continuous Transfer In this configuration during idle periods e The CLK signal is forced LOW e SSEL is forced HIGH e The transmit MOSI MISO pad is in high impedance If the SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW This causes slave data to be enabled onto the MISO input line of the master Master s MOSI is enabled One half SCK period later valid master data is transferred to the MOSI pin Now that both the master and
124. up table The closest value for FRest 1 628 in the look up Table 10 168 is FR 1 625 It is equivalent to DIVADDVAL 5 and MULVAL 8 Based on these findings the suggested UART setup would be DLM 0 DLL 4 DIVADDVAL 5 and MULVAL 8 According to Equation 10 7 the UART s baud rate is 115384 This rate has a relative error of 0 16 from the originally specified 115200 UART Transmit Enable Register UOTER 0x4000 8030 In addition to being equipped with full hardware flow control auto cts and auto rts mechanisms described above UOTER enables implementation of software flow control When TxEn 1 UART transmitter will keep sending data as long as they are available As soon as TxEn becomes 0 UART transmission will stop NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 149 of 290 NXP Semiconductors U M1 0375 UM10375_0 5 17 Chapter 10 LPC13xx UART Although Table 10 169 describes how to use TxEn bit in order to achieve hardware flow control it is strongly suggested to let UART hardware implemented auto flow control features take care of this and limit the scope of TxEn to software flow control Table 10 169 describes how to use TXEn bit in order to achieve software flow control Table 169 UART Transmit Enable Register UOTER address 0x4000 8030 bit description Bit Symbol Description Reset Value 6 0 Reserved user software should not write ones to re
125. whether the capture function is enabled and whether a capture event happens on the rising edge of the associated pin the falling edge or on both edges 7 10 External Match Register TMR32B0EMR and TMR32B1EMR The External Match Register provides both control and status of the external match pins CAP32Bn_MAT 3 0 If the match outputs are configured as PWM output the function of the external match registers is determined by the PWM rules Section 14 7 13 Rules for single edge controlled PWM outputs on page 233 UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 230 of 290 NXP Semiconductors UM10375 Chapier 14 LPC13xx 32 bit counter timer CT32B Table 228 External Match Register TMR32BOEMR address 0x4001 403C and TMR32B1EMR address0x4001 803C bit description Bit 5 4 7 6 9 8 11 10 15 12 Symbol EMO EM1 EM2 EM3 EMCO EMC1 EMC2 EMC3 Description External Match 0 This bit reflects the state of output CT32Bn_MATO whether or not this output is connected to its pin When a match occurs between the TC and MRO this bit can either toggle go LOW go HIGH or do nothing Bits EMR 5 4 control the functionality of this output This bit is driven to the CT32BO_MAT0 CT32B1_MATO pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH External Match 1 This bit reflects the state of output CT32Bn_MAT1 w
126. with 0x00 This status code may be used to vector to a state service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in Table 12 209 OTHER MASTER SLA 1W1At DATA 1A CONTINUES ejs D Cat other Master sends repeated START earlier retry Fig 41 Simultaneous Repeated START conditions from two masters O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 202 of 290 NXP Semiconductors U M1 0375 10 14 10 15 UM10375_0 Chapter 12 LPC13xx I2C bus interface time limit STA flag i STO flag SDA line SCL line start condition Fig 42 Forced access to a busy I2C bus STA flag 4 9 SDA line p Y SCL line start gt condition 1 Unsuccessful attempt to send a START condition 2 SDA line is released 3 Successful attempt to send a START condition State 08H is entered Fig 43 Recovering from a bus obstruction caused by a LOW level on SDA I2C state service routines This section provides examples of operations that must be performed by various 12C state service routines This includes e Initialization of the 12C block after a Reset e 2C Interrupt Service e The 26 state service routines providing support for all four 12C operating modes Initialization In the initialization example the 12C block is enabled for both master and slave
127. 0 000 Selects function PIO2_11 001 Select function SCK only if pin PIO2_11 SCK selected in Table 5 105 010 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 71 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 90 IOCON_JTAG_TDI_PIOO_11 register IOCON_JTAG_TDI_PIO0_11 address 0x4004 4074 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function TDI 001 Selects function PIOO_11 010 Selects function ADO 011 Selects function CT32B0_MAT3 100 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 7 ADMODE Select Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 31 8 Reserved UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 72 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I
128. 0 NXP Semiconductors U M1 0375 UM10375_0 Chapter 3 LPC13xx System configuration 5 30 CLKOUT clock source update enable register 5 31 5 32 This register updates the clock source of the CLKOUT pin with the new clock after the CLKOUTCLKSEL register has been written to In order for the update to take effect at the input of the CLKOUT pin first write a zero to the CLKCLKUEN register and then write a one to CLKCLKUEN Table 35 CLKOUT clock source update enable register CLKOUTUEN address 0x4004 80E4 bit description Bit Symbol Value Description Reset value 0 ENA Enable CLKOUT clock source update 0x0 0 No change 1 Update clock source 31 1 Reserved 0x00 CLKOUT clock divider register This register determines the divider value for the clkout_clk signal on the CLKOUT pin Table 36 CLKOUT clock divider registers CLKOUTCLKDIV address 0x4004 80E8 bit description Bit Symbol Value Description Reset value 7 0 DIV Clock divider values 0x00 0 Gate 1 Divide by 1 to ane 255 Divide by 255 31 8 Reserved 0x00 POR captured PIO status register 0 The PIOPORCAPO register captures the state HIGH or LOW of the PIO pins of ports 0 1 and 2 pins PIO2_0 to PIO2_7 at power on reset Each bit represents the reset state of one GPIO pin This register is a read only status register Table 37 POR captured PIO status registers 0 PIOPORCAPO address 0x4004 8100 bit description Bit Symbol Descriptio
129. 0 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 103 IOCON_PIO1_7 register IOCON_PIO1_7 address 0x4004 40A8 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO1_7 001 Selects function UART_TXD 010 Selects function CT32BO_MAT1 011to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 z Reserved 1 31 7 Reserved Table 104 IOCON_PIO3_3 register IOCON_PIO3_3 address 0x4004 40AC bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO3_3 001 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 z Reserved 1 31 7 Reserved 4 1 1 IOCON SCK location register This register is used to select a pin among three possible choices for the SSP SCK function UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 81 of 290 NXP Semiconductors U M1 0375 UM10375_0 Chapter 5 LPC13xx
130. 0 Timeout condition occurs A Receive Timeout occurs when the Rx FIFO is not empty and no has not been read for a timeout period O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 160 of 290 NXP Semiconductors U M1 0375 UM10375_0 6 7 6 8 Chapter 11 LPC13xx SSP Table 181 SSPO Interrupt Mask Set Clear register SSPOIMSC address 0x4004 0014 bit description Bit Symbol Description Reset Value 2 RXIM Software should set this bit to enable interrupt when the Rx FIFO is at 0 least half full 3 TXIM Software should set this bit to enable interrupt when the Tx FIFO is at 0 least half empty 7 4 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined SSPO Raw Interrupt Status Register SSPORIS 0x4004 0018 This read only register contains a 1 for each interrupt condition that is asserted regardless of whether or not the interrupt is enabled in the SSPOIMSC Table 182 SSPO Raw Interrupt Status register SSPORIS address 0x4004 0018 bit description Bit Symbol Description Reset Value 0 RORRIS This bit is 1 if another frame was completely received while the 0 RxFIFO was full The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs 1 RTRIS This bit is 1 if the Rx FIFO is not empty and has not been read 0 for a timeout period 2 RXRIS This bit is 1 if the Rx FI
131. 0 1 2 1 750 3 4 1 067 1 15 1 267 4 15 1 533 8 15 1 769 10 13 1 071 1 14 1 273 3 11 1 538 7 13 1 778 7 9 1 077 1 13 1 286 2 7 1 545 6 11 1 786 11 14 1 083 1 12 1 300 3 10 1 556 5 9 1 800 4 5 1 091 1 11 1 308 4 13 1 571 4 7 1 818 9 11 1 100 1 10 1 333 1 3 1 583 7 12 1 833 5 6 1 111 1 9 1 357 5 14 1 600 3 5 1 846 11 13 1 125 1 8 1 364 4 11 1 615 8 13 1 857 6 7 1 133 2 15 1 375 3 8 1 625 5 8 1 867 13 15 1 143 1 7 1 385 5 13 1 636 7 11 1 875 7 8 1 154 2 13 1 400 2 5 1 643 9 14 1 889 8 9 1 167 1 6 1 417 5 12 1 667 2 3 1 900 9 10 1 182 2 11 1 429 3 7 1 692 9 13 1 909 10 11 1 200 1 5 1 444 4 9 1 700 7 10 1917 11 12 1 214 3 14 1 455 5 11 1 714 5 7 1923 12 13 1 222 2 9 1 462 6 13 1 727 8 11 1929 13 14 1 231 3 13 1 467 7 15 1 733 11 15 1 933 14 15 Example 1 UART_PCLK 14 7456 MHz BR 9600 According to the provided algorithm DL es PCLK 16 x BR 14 7456 MHz 16 x 9600 96 Since this DLgg is an integer number DIVADDVAL 0 MULVAL 1 DLM 0 and DLL 96 Example 2 UART_PCLK 12 MHz BR 115200 According to the provided algorithm DL es PCLK 16 x BR 12 MHz 16 x 115200 6 51 This DL gg is not an integer number and the next step is to estimate the FR parameter Using an initial estimate of FRest 1 5 a new DL eg 4 is calculated and FRest is recalculated as FReg 1 628 Since FRest 1 628 is within the specified range of 1 1 and 1 9 DIVADDVAL and MULVAL values can be obtained from the attached look
132. 0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 18 of 290 NXP Semiconductors U M1 0375 UM10375_0 Chapter 3 LPC13xx System configuration 5 10 System reset status register 5 11 The SYSRSTSTAT register shows the source of the latest reset event The bits are cleared by writing a one to any of the bits The POR event clears all other bits in this register but if another reset signal e g EXTRST remains asserted after the POR signal is negated then its bit is set to detected Table 15 System reset status register SYSRSTSTAT address 0x4004 8030 bit description Bit Symbol Value Description Reset value 0 POR POR reset status 0x0 0 no POR detected 1 POR detected 1 EXTRST Status of the external RESET pin 0x0 0 no RESET event detected 1 RESET detected 2 WDT Status of the Watchdog reset 0x0 0 no WDT reset detected 1 WDT reset detected 3 BOD Status of the Brown out detect reset 0x0 0 no BOD reset detected 1 BOD reset detected 4 SYSRST Status of the software system reset 0x0 0 no System reset detected 1 System reset detected 31 5 Reserved 0x00 System PLL clock source select register This register selects the clock source for the system PLL The SYSPLLCLKUEN register see Section 3 5 12 must be toggled from LOW to HIGH for the update to take effect Remark The system oscillator must be selected if the system PLL is used to generate a 48 MHz clock to the USB block Tab
133. 00 0 empty OxF FIFO full 7 4 Reserved The value read from a reserved bit is not defined NA 11 8 TXFIFOLVL Reflects the current level of the UART transmitter FIFO 0x00 0 empty OxF FIFO full 31 12 Reserved The value read from a reserved bit is not defined NA 6 Architecture UM10375_0 The architecture of the UART is shown below in the block diagram The APB interface provides a communications link between the CPU or host and the UART The UART receiver block UORX monitors the serial input line RXD for valid input The UART RX Shift Register UORSR accepts valid characters via RXD After a valid character is assembled in the UORSR it is passed to the UART RX Buffer Register FIFO to await access by the CPU or host via the generic host interface The UART transmitter block UOTX accepts data written by the CPU or host and buffers the data in the UART TX Holding Register FIFO UOTHR The UART TX Shift Register UOTSR reads the data stored in the UOTHR and assembles the data to transmit via the serial output pin TXD1 The UART Baud Rate Generator block UOBRG generates the timing enables used by the UART TX block The UOBRG clock input source is UART_PCLK The main clock is divided down per the divisor specified in the UODLL and UODLM registers This divided down clock is a 16x oversample clock NBAUDOUT NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 153 of 290
134. 000 C000 211 Table 211 Register overview 16 bit counter timer 1 CT16B1 base address 0x4001 0000 212 Table 212 Interrupt Register TMR16BOIR address 0x4000 C000 and TMR16B1IR address 0x4001 0000 bit description 213 Table 213 Timer Control Register TMR16BOTCR address 0x4000 C004 and TMR16B1TCR address 0x4001 0004 bit description 214 Table 214 Match Control Register TMR16BOMCR address 0x4000 C014 and TMR16B1MCR address 0x4001 0014 bit description Table 215 Capture Control Register TMR16BOCCR address 0x4000 C028 and TMR16B1CCR address 0x4001 0028 bit description 216 Table 216 External Match Register TMR16BOEMR address 0x4000 C03C and TMR16B1EMR address 0x4001 003C bit description 217 Table 217 External match control 217 Table 218 Count Control Register TMR16BOCTCR address 0x4000 C070 and TMR16B1CTCR address 0x4001 0070 bit description 218 Table 219 PWM Control Register TMR16BOPWMC NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 281 of 290 NXP Semiconductors UM10375 address 0x4000 C074 and TMR16B1PWMC address 0x4001 0074 bit description 219 Table 220 Counter timer pin description 223 Table 221 Register overview 32 bit counter timer 0 CT32B0 base address 0x4001 4000 Table 222 Register overview 32 bit counter timer 1 CT32B1 base ad
135. 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4 EA 3 Description Reset value Error Code 0x0 No Error PID Encoding Error Unknown PID Unexpected Packet any packet sequence violation from the specification Error in Token CRC Error in Data CRC Time Out Error Babble Error in End of Packet Sent Received NAK Sent Stall Buffer Overrun Error Sent Empty Packet ISO Endpoints only Bitstuff Error Error in Sync Wrong Toggle Bit in Data PID ignored data The Error Active bit will be reset once this register is read Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined Select Endpoint Command 0x00 0x09 Data read 1 byte optional The Select Endpoint command initializes an internal pointer to the start of the selected buffer in EP_RAM Optionally this command can be followed by a data read which returns some additional information on the packet s in the endpoint buffer s The command code of the Select Endpoint command is equal to the physical endpoint number In the case of a single buffered endpoint the B_2 FULL bit is not valid Table 147 Select Endpoint Register bit description Bit Symbol Value Description Reset value 0 FE Full Empty This bit indicates the full or empty status of the 0 endpoint buffer s For IN endpoints the FE bit gives the ANDed result of the B_1_FULL and B_2 FULL bits
136. 0020o cross ees 234 5 3 System Timer Current value register STCURR 4 Operation ects cocci e 234 0xE000 EOIS DE A ba 299 5 4 System Timer Calibration value register 5 Register description 235 STCALIB 0xE000 EO01C 236 5 1 System Timer Control and status register STCTRL 0xEO00E010 235 6 Example timer calculations 237 Chapter 16 LPC13xx Analog to Digital Converter ADC 1 How to read this chapter 238 5 3 A D Status Register ADOSTAT 0x4001 C030 2 Features pira aV uniia arai 238 241 l 3 Pin description 00ecsseeees 238 54 i P Register ADOINTEN oe 4 Clocking and power control 238 5 5 A D Data Registers ADODRO to ADODR7 5 Register description 239 0x4001 C010 to 0x4001 C02C 242 5 1 A D Control Register ADOCR 0x4001 C000 6 OperatioN lt o0ooscorsriararia ess 243 239 6 1 Hardware triggered conversion 243 5 2 A D Global Data Register ADOGDR 62 Interrupts 243 0x4001 C004 onanan anaana 241 i PS ae a Chapter 17 LPC13xx WatchDog timer WDT 1 How to read this chapter 244 6 2 Watchdog Timer Constant register WDTC 2 Fool octobre 244 0x4000 4004 e 247 3 Applicati0nS ooooocoroccooomo 244 63 ooo ds register WDFEED a 4 Description AAA Ran aRalraye waver 244 6 4 Watchdog Timer Value register WDTV 5 Clocking and power cont
137. 1 APRPIO2_11 Edge select for start logic input PIO2_11 to PIO2_9 0 ee 0 Falling edge 1 Rising edge 4 APRPIO3_0 Edge select for start logic input PIO3_0 0 0 Falling edge 1 Rising edge 7 55 APRPIO3_3 Edge select for start logic input PIO3_3 to PIO3_1 0 pone 0 Falling edge 1 Rising edge 31 8 Reserved 0 Start logic signal enable register 1 This STARTERP1 register enables or disables the start signal bits in the start logic The bit assignment is identical to Table 3 45 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 33 of 290 NXP Semiconductors U M1 0375 5 42 Chapter 3 LPC13xx System configuration Table 46 Start logic signal enable register 1 STARTERP1 address 0x4004 8214 bit description Bit Symbol Value Description Reset value 0 ERPIO2_8 Enable start signal for start logic input PIO2_8 0 0 Disabled 1 Enabled 3 11 ERPIO2_11to Enable start signal for start logic input PIO2_11 to 0 ERPIO2_9 PIO2_9 0 Disabled 1 Enabled 4 ERPIO3_0 Enable start signal for start logic input PIO3_0 0 0 Disabled 1 Enabled 7 5 ERPIO3_3 to Enable start signal for start logic input PIO3_3 to 0 ERPIO3_1 PIO1_1 0 Disabled 1 Enabled 31 8 Reserved 0 Start logic reset register 1 Writing a one to a bit in the STARTRSRP1CLR register resets the start logic state The bit assignment is identical to Table 3 45 The start up logic uses the input signals to generate a clock edge for register
138. 1 Enable 6 Reserved 1 7 ADMODE Select Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 31 8 Reserved UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 74 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 93 IOCON_JTAG_nTRST_PIO1_2 register IOCON_JTAG_nTRST_PIO1_ 2 address 0x4004 4080 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function TRST 001 Selects function PIO1_2 010 Selects function AD3 011 Selects function CT32B1_MAT1 100 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 7 ADMODE Select Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 31 8 Reserved Table 94 IOCON_PIO3_0 register IOCON_PIO3_0 address 0x4004 4084 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO3_0 001 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0
139. 1 How to read this chapter 81 3 FeatureS 2 0 00 cece eee eee eens 81 2 Introduction 0 0 cece eee eee 81 4 Interrupt SOUrCeS 2 6 cee eee 81 Chapter 7 LPC13xx General Purpose I O GPIO 1 How to read this chapter 83 3 6 GPIO interrupt mask register 85 2 Introduction cacon rr a 83 3 7 GPIO raw interrupt status register 85 21 FeALULES oo ea anaa 83 3 8 GPIO masked interrupt status register 86 3 Register description 83 33 ano interrupt asar FOUISIE areas erre 86 3 1 GPIO data register oo oooooo 84 4 Functional description TAS Se E 87 3 2 GPIO data direction register 84 4i Write read data operations 87 3 3 GPIO interrupt sense register 84 Write operation 0 essere eee 87 3 4 GPIO interrupt both edges sense register 85 Read operation esses 88 3 5 GPIO interrupt event register 85 Chapter 8 LPC13xx Pin configuration 1 How to read this chapter 89 4 Pin description oo ooooomoomm 93 2 LPC134x pin configuration 90 41 LQFP48 packages 22i0s2vit aires ees 94 3 LPC131x pin configuration 92 42 HVQFN33 packages ooooooocoooo 20 97 Chapter 9 LPC13xx USB device controller 1 How to read this chapter 100 8 3 Power management support 105 2 Introduction coocooccccccnco 100 84
140. 10 1011 1101 1110 1111 are reserved 2 For details see Section 10 5 9 UART Line Status Register UOLSR 0x4000 8014 Read Only 3 For details see Section 10 5 1 UART Receiver Buffer Register UORBR 0x4000 8000 when DLAB 0 Read Only 4 For details see Section 10 5 5 UART Interrupt Identification Register UOIIR 0x4004 8008 Read Only and Section 10 5 2 UART Transmitter Holding Register UOTHR 0x4000 8000 when DLAB 0 Write Only The UART THRE interrupt UOIIR 3 1 001 is a third level interrupt and is activated when the UART THR FIFO is empty provided certain initialization conditions have been met These initialization conditions are intended to give the UART THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start up The O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 136 of 290 NXP Semiconductors U M1 0375 5 6 5 7 UM10375_0 Chapter 10 LPC13xx UART initialization conditions implement a one character delay minus the stop bit whenever THRE 1 and there have not been at least two characters in the UOTHR at one time since the last THRE 1 event This delay is provided to give the CPU time to write data to UOTHR without a THRE interrupt to decode and service A THRE interrupt is set immediately if the UART THR FIFO has held two or more characters at one time and curren
141. 10375 Chapter 20 LPC13xx Supplementary information 7 3 Timer Counter TMR32BOTC address 7 8 Capture Control Register TMR32BOCCR and 0x4001 4008 and TMR32B1TC address TMR82B1CCR ooococccc Aa 228 0x4001 8008 00 226 7 9 Capture Register TMR32BOCRO address 7 4 Prescale Register TMR32BOPR address 0x4001 402C and TMR32B1CRO address 0x4001 400C and TMR32B1PR address 0x4001 8020 022005 228 0x4001 800C 00 eee eee 226 7 10 External Match Register TMR32BOEMR and 7 5 Prescale Counter Register TMR32BOPC TMR32B1EMR 5 228 address 0x4001 4010 and TMR32B1PC address 7 11 Count Control Register TMR32BOCTCR and 0x4001 8010 nananana aaa 226 TMR82B1TCR 2 2 22000e ee 229 7 6 Match Control Register TMR32BOMCR and 7 12 PWM Control Register TMR32BOPWMC and TMR32B1MCR 2 0 5 226 TMR32B1PWMC 2 230 7 7 Match Registers TMR32BOMRO0 1 2 3 7 13 Rules for single edge controlled PWM outputs addresses 0x4001 4018 1C 20 24 and 231 TMR32B1MRO0 1 2 3 addresses 0x4001 8 Example timer operation 232 8018 10 20 24 6 sees 227 9 Architecture 2 00ce eee eee eee 233 Chapter 15 LPC13xx SysTick timer 1 How to read this chapter 234 5 2 System Timer Reload value register STRELOAD 2 A E oiconsaecuasdecnenetnemtndeed 234 0xXE000 E014 aaa pd 236 3 Descripti0N lt lt lt lt
142. 12C interface Writing a one to a bit of this register causes the corresponding bit in the 12C control register to be set Writing a zero has no effect Table 187 12C Control Set register IZCONSET address 0x4000 0000 bit description Bit Symbol Description Reset value 1 0 Reserved User software should not write ones to reserved bits The NA value read from a reserved bit is not defined 2 AA Assert acknowledge flag 3 SI 12C interrupt flag 0 4 STO STOP flag 0 5 STA START flag 0 6 I2EN 12C interface enable 0 ES Reserved User software should not write ones to reserved bits The NA value read from a reserved bit is not defined 12EN 12C Interface Enable When 12EN is 1 the 12C interface is enabled I2EN can be cleared by writing 1 to the IZENC bit in the I2CONCLR register When I2EN is 0 the 12C interface is disabled When I2EN is 0 the SDA and SCL input signals are ignored the 12C block is in the not addressed slave state and the STO bit is forced to 0 12EN should not be used to temporarily release the 12C bus since when 12EN is reset the 12C bus status is lost The AA flag should be used instead STA is the START flag Setting this bit causes the I C interface to enter master mode and transmit a START condition or transmit a Repeated START condition if it is already in master mode NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 173 of 290 N
143. 1313FHN33 32 kB no yes LPC1342FHN33 16kB yes yes LPC1343FBD48 32 kB yes yes LPC1343FHN33 32 kB yes yes Remark For configuring flash memory access times see Section 18 15 2 Boot loader 3 Features The boot loader controls initial operation after reset and also provides the means to program the flash memory This could be initial programming of a blank device erasure and re programming of a previously programmed device or programming of the flash memory by the application program in a running system e In System Programming In System programming ISP is programming or reprogramming the on chip flash memory using the boot loader software and UART serial port This can be done when the part resides in the end user board e In Application Programming In Application IAP programming is performing erase and write operation on the on chip flash memory as directed by the end user application code e THe LPC134x supports booting from the USB port through enumeration as a Mass Storage Class MSC Device when connected to a USB host interface 4 Description UM10375_0 The boot loader code is executed every time the part is powered on or reset See Figure 18 54 The loader can either execute the ISP command handler or the user application code or it can obtain the boot image as an attached MSC device through USB A LOW level during reset at the PIOO_1 pin is considered an external hardware request to start the ISP comm
144. 19 Paramo0 Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number Param2 System Clock Frequency CCLK in kHz CMD_SUCCESS BUSY SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION INVALID_SECTOR None This command is used to erase a sector or multiple sectors of on chip flash memory The boot sector can not be erased by this command To erase a single sector use the same Start and End sector numbers Blank check sector s Table 277 IAP Blank check sector s command Command Input Return Code Result Description Blank check sector s Command code 5310 Paramo Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number CMD_SUCCESS BUSY SECTOR_NOT_BLANK INVALID_ SECTOR Result0 Offset of the first non blank word location if the Status Code is SECTOR_NOT_BLANK Result1 Contents of non blank word location This command is used to blank check a sector or multiple sectors of on chip flash memory To blank check a single sector use the same Start and End sector numbers Read Part Identification number Table 278 IAP Read Part Identification command Command Input Return Code Result Description Read part identification number Command code 54410 Parameters None CMD_SUCCESS Result0 Part Identification Number This command is used to read the part identification number
145. 19 October 2009 236 of 290 NXP Semiconductors UM10375 Chapter 15 LPC13xx SysTick timer Fig 52 System tick timer block diagram private peripheral bus Systick timer clock System Tick interrupt 5 Register description Table 232 System Tick Timer register map base address 0xE000 E000 Name Access Address Description Reset value offset STCTRL R W 0x010 System Timer Control and status register 0x4 STRELOAD R W 0x014 System Timer Reload value register 0 STCURR R W 0x018 System Timer Current value register 0 STCALIB R W 0x01C System Timer Calibration value register lt tbd gt 1 Reset Value reflects the data stored in used bits only It does not include content of reserved bits 5 1 System Timer Control and status register STCTRL 0xE000 E010 The STCTRL register contains control information for the System Tick Timer and provides a status flag Table 233 System Timer Control and status register STCTRL 0xE000 E010 bit description Bit Symbol 0 ENABLE 1 TICKINT 2 UM10375_0 Description Reset value System Tick counter enable When 1 the counter is enabled 0 When 0 the counter is disabled System Tick interrupt enable When 1 the System Tick interrupt 0 is enabled When 0 the System Tick interrupt is disabled When enabled the interrupt is generated when the System Tick counter counts down to 0 Reserved 1 NXP B V 2009 All rights reserved
146. 2009 14 of 290 NXP Semiconductors U M1 0375 5 4 5 5 UM10375_0 Chapter 3 LPC13xx System configuration Table 8 System PLL control register SYSPLLCTRL address 0x4004 8008 bit description Bit Symbol Value Description Reset value 6 5 PSEL Post divider ratio P The division ratio is 2 x P 0x00 00 P 1 01 P 2 10 P 4 11 P 8 7 DIRECT Direct CCO clock output control 0x0 0 Clock signal goes through post divider 1 Clock signal goes directly to output s 8 BYPASS Input clock bypass control 0x0 0 CCO clock is sent to post dividers 1 PLL input clock sys_pllclkin is sent to post dividers 31 9 Reserved 0x00 System PLL status register This register is a Read only register and supplies the PLL lock status see Section 3 10 1 Table 9 System PLL status register SYSPLLSTAT address 0x4004 800C bit description Bit Symbol Value Description Reset value 0 LOCK PLL lock status 0x0 0 PLL not locked 1 PLL locked 31 1 Reserved 0x00 USB PLL control register The USB PLL is identical to the system PLL and is used to provide a dedicated clock to the USB block if available see Section 3 1 This register connects and enables the USB PLL and configures the PLL multiplier and divider values The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources The input frequency is multiplied up to a high frequency then divided down to provide the actual clock 48 MHz clock used by the USB
147. 2009 185 of 290 NXP Semiconductors U M1 0375 UM10375_0 9 7 Chapter 12 LPC13xx I2C bus interface 1 1 2 i 3 gt SCL line 1 2 3 4 s o 1 Another device transmits serial data 2 Another device overrules a logic dotted line transmitted this 12C master by pulling the SDA line low Arbitration is lost and this 12C enters Slave Receiver mode 3 This 12C is in Slave Receiver mode but still generates clock pulses until the current byte has been transmitted This 12C will not generate clock pulses for the next byte Data on SDA originates from the new master once it has won arbitration Fig 35 Arbitration procedure The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device If two or more master devices generate clock pulses the mark duration is determined by the device that generates the shortest marks and the space duration is determined by the device that generates the longest spaces Figure 12 36 shows the synchronization procedure SDA line X X 1 3 1 y y y SCL line ko high low period period 1 Another device pulls the SCL line low before this 1 C has timed a complete high time The other device effectively determines the shorter HIGH period 2 Another device continues to pull the SCL line low after this 12C has timed a complete low time and released SCL The I2C cloc
148. 290 NXP Semiconductors UM10375 6 Register description Chapter 11 LPC13xx SSP Table 175 Register overview SSP base address 0x4004 0000 The register addresses of the SSP controller are shown in Table 11 175 Name SSPOCRO SSPOCR1 SSPODR SSPOSR SSPOCPSR SSPOIMSC SSPORIS SSPOMIS SSPOICR Access Address Description R W R W R W RO R W R W R W R W R W offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 Reset Valuel l Control Register 0 Selects the serial clock rate bus type and data size 0 Control Register 1 Selects master slave and other modes 0 Data Register Writes fill the transmit FIFO and reads empty the receive 0 FIFO Status Register Clock Prescale Register Interrupt Mask Set and Clear Register Raw Interrupt Status Register Masked Interrupt Status Register SSPICR Interrupt Clear Register oo NA 1 Reset Value reflects the data stored in used bits only It does not include reserved bits content UM10375_0 6 1 SSPO Control Register 0 SSPOCRO 0x4004 0000 This register controls the basic operation of the SSP controller Table 176 SSPO Control Register 0 SSPOCRO address 0x4004 0000 bit description Bit Symbol 3 0 DSS 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Value Description Reset Value Data Size Select This field controls the number of bits 0000 transferred in ea
149. 3 This bit reflects the state of output of match channel 3 When a match occurs between the TC and MR3 this bit can either toggle go LOW go HIGH or do nothing Bits EMR 11 10 control the functionality of this output There is no output pin available for this channel on either of the 16 bit timers External Match Control 0 Determines the functionality of External Match 0 Table 13 218 shows the encoding of these bits External Match Control 1 Determines the functionality of External Match 1 Table 13 218 shows the encoding of these bits External Match Control 2 Determines the functionality of External Match 2 Table 13 218 shows the encoding of these bits External Match Control 3 Determines the functionality of External Match 3 Table 13 218 shows the encoding of these bits Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Reset value 00 00 00 00 Table 218 External match control EMR 11 10 EMR 9 8 Function EMR 7 6 or EMR 5 4 00 01 10 11 Do Nothing Clear the corresponding External Match bit output to 0 CT16Bn_MATm pin is LOW if pinned out Set the corresponding External Match bit output to 1 CT16Bn_MATm pin is HIGH if pinned out Toggle the corresponding External Match bit output UM10375_0 7 11 Count Control Register TMR16BOCTCR and TMR16B1CTCR The Count Control Register CTCR is used to select be
150. 3 C010 bit description Bit Symbol Value Description Reset value 1 0 FLASHTIM Flash memory access time FLASHTIM 1 is equal to the 0x2 number of system clocks used for flash access 00 1 system clock flash access time for system clock frequencies of up to 20 MHz 01 2 system clocks flash access time for system clock frequencies of up to 40 MHz 10 3 system clocks flash access time for system clock frequencies of up to 72 MHz 11 Reserved 31 2 Reserved User software must not change the value of lt tbd gt these bits Bits 31 2 must be written back exactly as read NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 273 of 290 UM10375 Chapter 19 LPC13xx Serial Wire Debug SWD and trace port Rev 00 10 19 October 2009 User manual 1 How to read this chapter The debug functionality is identical for all LPC13xx parts 2 Features e Supports ARM Serial Wire Debug mode e Direct debug access to all memories registers and peripherals e No target resources are required for the debugging session e Trace port provides CPU instruction trace capability Output via a Serial Wire Viewer e Eight breakpoints Six instruction breakpoints that can also be used to remap instruction addresses for code patches Two data comparators that can be used to remap addresses for patches to literal values e Four data watchpoints that can also be used as trace triggers e Ins
151. 3 ERPIO1_11 to Enable start signal for start logic input PIO1_11 to 0 ERPIO1_1 PIO1_1 0 Disabled 1 Enabled 24 ERPIO2_0 Enable start signal for start logic input PIO2_0 0 0 Disabled 1 Enabled 31 25 ERPIO2_7 to Enable start signal for start logic input PIO2_7 to 0 ERPIO2_1 PIO2_1 0 Disabled 1 Enabled Start logic reset register 0 Writing a one to a bit in the STARTRSRPOCLR register resets the start logic state The bit assignment is identical to Table 3 41 The start up logic uses the input signals to generate a clock edge for registering a start signal This clock edge falling or rising sets the interrupt for waking up from Deep sleep mode Therefore the start up logic states must be cleared before being used Table 43 Start logic reset register 0 STARTRSRPOCLR address 0x4004 8208 bit description Bit Symbol Value Description Reset value 0 RSRPIOO_0O Start signal reset for start logic input PIOO_0 n a Write reset start signal NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 31 of 290 NXP Semiconductors UM10375 UM10375_0 5 39 Chapter 3 LPC13xx System configuration Table 43 Start logic reset register 0 STARTRSRPOCLR address 0x4004 8208 bit description continued Bit Symbol Value Description Reset value 11 1 RSRPIOO_11 Start signal reset for start logic input PIOO_11 to n a to PIOO_1 RSRPIOO_1 Write reset start signal 12 RSRPIO1_0 Start signal re
152. 33 Format of Slave Transmitter mode description 9 1 UM10375_0 Figure 12 34 shows how the on chip I C bus interface is implemented and the following text describes the individual blocks Input filters and output stages Input signals are synchronized with the internal clock and spikes shorter than three clocks are filtered out The output for 12C bus is a special pad designed to conform to the I2C bus specification O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 183 of 290 NXP Semiconductors U M1 0375 Chapter 12 LPC13xx I2C bus interface ADDRESS REGISTER INPUT COMPARATOR FILTER p lined SHIFT RE STAGE BIT COUNTER ARBITRATION amp SYNC LOGIC APB BUS TIMING amp CONTROL SCL LOGIC OUTPUT STAGE SERIAL CLOCK GENERATOR I2CONSET I2CONCLR CONTROL REGISTER amp SCL DUTY 12SCLH CYCLE REGISTERS l2SCLL STATUS DECODER STATUS REGISTER I2STAT Fig 34 1 C serial interface block diagram UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 184 of 290 NXP Semiconductors U M1 0375 UM10375_0 9 2 9 3 9 4 9 5 9 6 Chapter 12 LPC13xx I2C bus interface Address Registers I2ADDRO to 1LADDR3 These registers may be loaded with the 7 bit slave address 7 most significant bits to which the 12C block will respond when programmed as a slave transmitter or receiver
153. 44 Vop sv3 43 PIO3_2 42 PIO1_11 AD7 41 LPC1313FBD48 39 SWDIO PIO1_3 AD4 CT32B1_MAT2 38 PIO2_3 RI 37 PIO3_1 PIO3_0 TRST PIO1_2 AD3 CT32B1_MAT1 TDO PIO1_1 AD2 CT32B1_MATO TMS PIO1_0 AD1 CT32B1_CAPO TDI PIOO_11 AD0 CT32B0_MAT3 PIO2_11 SCK PIO1_10 AD6 CT16B1_MAT1 SWCLK PIOO_10 SCK CT16B0_MAT2 PIOO_9 MOSI CT16B0_MAT1 SWO PIOO_8 MISO CT16B0_MATO PIO2_2 DCD PIO2_10 002aae513 O TF LO O M 0O D O NU M lt Pani lla lalallala A o UN md A ll E o Bo O f TYAN Q Nn ol 22 oo oo eo JE ol oi aara fa nl o 008 Q a qpe aw a a a 3 e o O A UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 NXP Semiconductors UM10375 Chapter 8 LPC13xx Pin configuration Fig 11 PIOO_1 CLKOUT CT32B0_MAT2 PIO0_2 SSEL CT16B0_CAPO o iW Xx x 5 EER 2 lt L lt x S20 l oo o a n a a m a a a a co y io FRE E O29 nO a AJJ 0 x XxX xa E C E 5 lt s 646 307 am n 3 a terminal 1 0005000 QLoOA0 gt 000 index area SWDIO PIO1_3 AD4 CT32B1_MAT2 E E E Es Es ET Es 5 PIO2_0 DTR TRST PIO1_2 AD3 CT32B1_MAT1 R RESET PIO0_0 XTALIN XTALOUT VpD IO PIO1_8 CT16B1_CAPO LPC1311FHN33 LPC1313FHN33 33 Vss wo DO PIO1_1 AD2 CT32B1_MATO MS PIO1_0 AD1 CT32B1_CAPO DI PIOO_11 AD0 CT32B0_MAT3 01_10 AD6 CT16B1_MAT1 WCLK PIO0_10 SCK CT16B0_MAT2 00_
154. 47 Select Endpoint Register bit description 119 Table 148 Set Endpoint Status Register bit description 121 Table 149 Clear Buffer Register bit description 122 Table 150 UART pin descripti0N 128 Table 151 Register overview UART base address 0x4000 8000 reinicio can bebe ad oe bd 130 Table 152 UART Receiver Buffer Register UORBR address 0x4000 8000 when DLAB 0 Read Only bit description 131 Table 153 UART Transmitter Holding Register UOTHR address 0x4000 8000 when DLAB 0 Write Only bit descripti0N 131 Table 154 UART Divisor Latch LSB Register UODLL address 0x4000 8000 when DLAB 1 bit descripti0N ooocccoooccooo oo 132 Table 155 UART Divisor Latch MSB Register UODLM address 0x4000 8004 when DLAB 1 bit description 00000 2 eee eee 132 Table 156 UART Interrupt Enable Register UOIER address 0x4000 8004 when DLAB 0 bit description 132 Table 157 UART Interrupt Identification Register UOIIR address 0x4004 8008 Read Only bit description 133 Table 158 UART Interrupt Handling 134 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 280 of 290 NXP Semiconductors UM10375 Table 159 UART FIFO Control Register UOFCR address 0x4000 8008 Write Only bit description 135 Table 160 UARTO Modem Control Register UOMCR address 0x4000 8010 bit descr
155. 485 ElA 485 mode Table 171 UART RS 485 Address Match register U0RS485ADRMATCH address 0x4000 8050 bit description Bit Symbol Description Reset value 7 0 ADRMATCH Contains the address match value 0x00 31 8 Reserved UART1 RS 485 Delay value register U0RS485DLY 0x4000 8054 The user may program the 8 bit RS485DLY register with a delay between the last stop bit leaving the TXFIFO and the de assertion of RTS or DTR This delay time is in periods of the baud clock Any delay time from 0 to 255 bit times may be programmed Table 172 UART RS 485 Delay value register UORS485DLY address 0x4000 80454 bit description Bit Symbol Description Reset value 7 0 DLY Contains the direction control RTS or DTR delay value This 0x00 register works in conjunction with an 8 bit counter 31 8 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined RS 485 ElA 485 modes of operation The RS 485 EIA 485 feature allows the UART to be configured as an addressable slave The addressable slave is one of multiple slaves controlled by a single master The UART master transmitter will identify an address character by setting the parity 9th bit to 1 For data characters the parity bit is set to 0 Each UART slave receiver can be assigned a unique address The slave can be programmed to either manually or automatically reject data following an address whic
156. 70 Table 283 Flash configuration register FLASHCFG address 0x4003 C010 bit description 271 Table 284 JTAG pin description 273 Table 285 Serial Wire Debug pin description 273 Table 286 Abbreviations 0oooocoooooooo 274 CESCHIPUON sopa it ia 243 Table 243 Register overview Watchdog timer base address 0x4000 4000 02005 245 Table 244 Watchdog Mode register WDMOD address 0x4000 4000 bit description 246 Table 245 Watchdog operating modes selection 246 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 282 of 290 NXP Semiconductors UM10375 4 Figures Chapter 20 LPC13xx Supplementary information Fig 1 Fig 2 Fig 3 Fig 4 Fig 5 Fig 6 Fig 7 Fig 8 Fig 9 Fig 10 Fig 11 Fig 12 Fig 13 Fig 14 Fig 15 Fig 16 Fig 17 Fig 18 Fig 19 Fig 20 Fig 21 Fig 22 Fig 23 Fig 24 Fig 25 Fig 26 Fig 27 Fig 28 Fig 29 Fig 30 Fig 31 Fig 32 Fig 33 Fig 34 Fig 35 Fig 36 Fig 37 Fig 38 Fig 39 Fig 40 Fig 41 Fig 42 Fig 43 Fig 44 UM10375_0 LPC13xx block diagram 000 0 00 5 LPC13xx memory Map 0 eee eee eee 7 LPC13xx CGU block diagram 10 System and USB PLL block diagram 42 Standard I O pin configuration 51 Masked write operation to the GPIODATA register 87
157. 9 MOSI CT16B0_MAT1 SWO N Ls 7 D ED aBRABARBA T T T P S P P 00_8 MISO CT16B0_MATO PAAPA PIOO_4 SCL PIOO_3 PIOO_5 SDA PIO3_4 PIO3_5 PIOO_6 SCK PIO1_9 CT16B1_MATO Transparent top view LPC1311 13 HVQFN33 package PIOO_7 CTS 002aae517 4 Pin description In Table 8 119 and Table 8 120 the pins are listed in order of their port number Supply pins and special function pins appear at the end The default function of each pin is always the first function listed in the description column or the first function of each pin symbol Each pin function can be set through the corresponding IOCON register see Table 5 62 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 95 of 290 NXP Semiconductors UM10375 Chapter 8 LPC13xx Pin configuration 4 1 LQFP48 packages Table 119 LPC1313 43 LQFP48 pin description table Symbol RESET PIO0_0 PIOO_1 CLKOUT CT32B0_MAT2 USB_FTOGGLE PIO0_2 SSEL CT16BO_CAPO PIO0_3 USB_VBUS PIOO_4 SCL PIOO_5 SDA PIOO_6 USB_CONNECT SCK PIO0_7 CTS PIOO_8 MISO CT16B0_MATO PIOO_9 MOSI CT16BO_MAT1 SWO SWCLK PIOO_10 SCK CT16B0_MAT2 UM10375_0 Pin 3 1011 1411 1518 16 2 22111 23 2711 2elil 2901 Type 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Description RESET External
158. A D Global Data Register ADOGDR address 0x4001 C004 bit description Bit Symbol Description Reset Value 5 0 Unused These bits always read as zeroes They provide compatible expansion 0 room for future higher resolution A D converters 15 6 V Veer When DONE is 1 this field contains a binary fraction representing the X voltage on the ADn pin selected by the SEL field divided by the voltage on the Vop svs pin Zero in the field indicates that the voltage on the ADn pin was less than equal to or close to that on Vss while Ox3FF indicates that the voltage on ADn was close to equal to or greater than that on Vrer 23 16 Unused These bits always read as zeroes They allow accumulation of 0 successive A D values without AND masking for at least 256 values without overflow into the CHN field 26 24 CHN These bits contain the channel from which the LS bits were converted 29 27 Unused These bits always read as zeroes They could be used for expansion of 0 the CHN field in future compatible A D converters that can convert more channels 30 OVERU This bit is 1 in burst mode if the results of one or more conversions was 0 N were lost and overwritten before the conversion that produced the result in the LS bits In non FIFO operation this bit is cleared by reading this register 31 DONE This bit is set to 1 when an A D conversion completes It is cleared 0 when this register is read and when the ADCR is written If the ADCR is writ
159. A interrupt Enables the THRE interrupt for UART The status of this 0 interrupt can be read from UOLSR 5 0 Disable the THRE interrupt Enable the THRE interrupt Enables the UART RX line status interrupts The status of 0 this interrupt can be read from UOLSR 4 1 0 Disable the RX line status interrupts Enable the RX line status interrupts a Reserved Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined Reserved Enables the end of auto baud interrupt 0 Disable end of auto baud Interrupt Enable end of auto baud Interrupt Enables the auto baud time out interrupt 0 0 Disable auto baud time out Interrupt 1 Enable auto baud time out Interrupt Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 134 of 290 NXP Semiconductors U M1 0375 UM10375_0 Chapter 10 LPC13xx UART 5 5 UART Interrupt Identification Register UOIIR 0x4004 8008 Read Only UOIIR provides a status code that denotes the priority and source of a pending interrupt The interrupts are frozen during a UOIIR access If an interrupt occurs during a UOIIR access the interrupt is recorded for the next UOIIR access Table 157 UART Interrupt Identification Register UOIIR address 0x4004 8008 Read Only bit description
160. ADODR7 addresses 0x4001 C010 to 0x4001 C02C bit description Bit Symbol Description Reset Value 5 0 Unused Unused always 0 0 These bits always read as zeroes They provide compatible expansion room for future higher resolution ADCs 15 6 V VREF When DONE is 1 this field contains a binary fraction representing the NA voltage on the ADn pin divided by the voltage on the Vre_r pin Zero in the field indicates that the voltage on the ADn pin was less than equal to or close to that on Vrer while Ox3FF indicates that the voltage on AD input was close to equal to or greater than that on Vref 29 16 Unused These bits always read as zeroes They allow accumulation of 0 successive A D values without AND masking for at least 256 values without overflow into the CHN field 30 OVERRUN This bit is 1 in burst mode if the results of one or more conversions 0 was were lost and overwritten before the conversion that produced the result in the LS bits This bit is cleared by reading this register 31 DONE This bit is set to 1 when an A D conversion completes It is cleared 0 when this register is read 6 1 6 2 UM10375_0 Hardware triggered conversion If the BURST bit in the ADCRO is 0 and the START field contains 010 111 the A D converter will start a conversion when a transition occurs on a selected pin or timer match signal Interrupts An interrupt is requested to the interrupt controller when the ADINT bit in the A
161. AHB clock control register AHBCLKCTRL address 0x4004 8080 bit description continued Bit 10 11 12 13 14 15 16 31 17 Symbol CT16B0 CT16B1 CT32B0 CT32B1 SSP UART ADC USB_REG WDT IOCON Value Description Enables clock for 16 bit counter timer 0 Disabled Enabled Enables clock for 16 bit counter timer 1 Disabled Enabled Enables clock for 32 bit counter timer 0 Disabled Enabled Enables clock for 32 bit counter timer 1 Disabled Enabled Enables clock for SSP Disabled Enabled Enables clock for UART Note that the UART pins must be configured in the IOCON block before the UART clock can be enabled Disabled Enabled Enables clock for ADC Disabled Enabled Enables clock for USB_REG Disabled Enabled Enables clock for WDT Disabled Enabled Enables clock for IO configuration block Disabled Enabled Reserved Reset value 0 0x00 SSP clock divider register This register configures the SSP peripheral clock SSP_PCLK The SSP_PCLK can be shut down by setting the DIV bits to 0x0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 23 of 290 NXP Semiconductors U M1 0375 UM10375_0 5 20 5 21 5 22 Chapter 3 LPC13xx System configuration Table 24 SSP clock divider register SSPCLKDIV address 0x4004 8094 bit description Bit Symbol Value Description Reset value 7 0 DIV
162. ALIB OxE000 E01C bit description 236 Table 236 ADC pin description 238 Table 237 Register overview ADC base address 0x4001 CO00 corri edad ed 239 Table 238 A D Control Register ADOCR address 0x4001 C000 bit description 240 Table 239 A D Global Data Register ADOGDR address 0x4001 C004 bit description 241 Table 240 A D Status Register ADOSTAT address 0x4001 C030 bit description 242 Table 241 A D Interrupt Enable Register ADOINTEN address 0x4001 COOC bit description 242 Table 242 A D Data Registers ADODRO to ADODR7 addresses 0x4001 C010 to 0x4001 C02C bit Chapter 20 LPC13xx Supplementary information Table 246 Watchdog Constant register WDTC address 0x4000 4004 bit description 247 Table 247 Watchdog Feed register WDFEED address 0x4000 4008 bit description 247 Table 248 Watchdog Timer Value register WDTV address 0x4000 000C bit description 247 Table 249 LPC13xx flash configurations 249 Table 250 CRP levels for USB boot images 253 Table 251 LPC13xx flash SectorS 255 Table 252 Code Read Protection options 256 Table 253 Code Read Protection hardware software interaction oooocccocccoooo 256 Table 254 ISP commands allowed for different CRP levels 257 Table 255 ISP command summary 258 Table 256 ISP Unlock command
163. AT RO 0x030 A D Status Register This register contains DONE and OVERRUN flags for 0 all of the A D channels as well as the A D interrupt flag 1 Reset Value reflects the data stored in used bits only It does not include reserved bits content 5 1 A D Control Register ADOCR 0x4001 C000 The A D Control Register provides bits to select A D channels to be converted A D timing A D modes and the A D start trigger UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 241 of 290 NXP Semiconductors U M1 0375 Chapter 16 LPC13xx Analog to Digital Converter ADC Table 239 A D Control Register ADOCR address 0x4001 C000 bit description Bit Symbol Value Description Reset Value 7 0 SEL Selects which of the AD7 0 pins is are to be sampled and converted Bit 0 selects Pin 0x01 ADO bit 1 selects pin AD1 and bit 7 selects pin AD7 In software controlled mode BURST 0 only one channel can be selected i e only one of these bits should be 1 In hardware scan mode BURST 1 any numbers of channels can be selected i e any or all bits can be set to 1 If all bits are set to 0 channel 0 is selected automatically SEL 0x01 15 8 CLKDIV The APB clock PCLK is divided by CLKDIV 1 to produce the clock for the ADC which 0 should be less than or equal to 4 5 MHz Typically software should program the smallest value in this field that yields a clock of 4 5 MHz or sli
164. C oscillator or the Watchdog oscillator Available in LQFP48 and HVQFN33 packages 4 Ordering options Table 1 Ordering options for the LPC13xx parts Type number Flash Total USB UART PC SSP ADC Pins Package SRAM RS 485 Fast channels LPC1311FHN33 8 kB 4kB 1 1 1 8 33 HVQFN33 LPC1313FBD48 32kB 8kB 1 1 1 8 48 LQFP48 LPC1313FHN33 32kB 8kB 1 1 1 8 33 HVQFN33 LPC1342FHN33 16kB 4kB Device 1 1 1 8 33 HVQFN33 LPC1343FBD48 32kB 8kB Device 1 1 1 8 48 LQFP48 LPC1343FHN33 32kB 8kB Device 1 1 1 8 33 HVQFN33 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 4 of 290 NXP Semiconductors UM10375 Chapter 1 LPC13xx Introductory information 5 Block diagram SWD TEST DEBUG INTERFACE ARM CORTEX M3 I code D code system bus bus bus GPIO ports HIGH SPEED P100 1 2 3 GPIO SCK SSEL MOSI RXD XD UART lt DTR DSR 2 CTS DCD RI 2 RTS SCL 2 SDA PO au vi ccnp aL 92 ot couwrerrmmen on 2 bi NTER TIMER 0 1 ice 32 bit COU T 0 vi cape o iSt CouNTERTMER on E 16 bi NTER TIMER 0 1 CP 6 bit COU T 0 USB DEVICE CONTROLLER 1 LPC1342 43 only 2 LQFP48 package only Fig 1 LPC13xx block diagram XTALIN USB pins XTALOUT RESET LPC1311 13 42 43 USB PHY 1 IRC CLOCK t GENERATION POWER CONTROL SYSTEM FUNCTIONS clocks and controls slave St slave O U slave e AHBLite BUS slave U slave S
165. CLKUEN address 0x4004 80C4 bit description Bit Symbol Value Description Reset value 0 ENA Enable USB clock source update 0x0 0 No change 1 Update clock source 31 1 Reserved 0x00 USB clock divider register This register allows the USB clock usb_clk to be divided to 48 MHz The usb_clk can be shut down by setting the DIV bits to 0x0 Table 30 USB clock divider register USBCLKDIV address 0x4004 80C8 bit description Bit Symbol Value Description Reset value 7 0 DIV USB clock divider values 0x00 0 Gate 1 Divide by 1 to pet 255 Divide by 255 31 8 Reserved 0x00 WDT clock source select register This register selects the clock source for the watchdog timer The WOTCLKUEN register see Section 3 5 27 must be toggled from LOW to HIGH for the update to take effect Table 31 WDT clock source select register WDTCLKSEL address 0x4004 80D0 bit description Bit Symbol Value Description Reset value 1 0 SEL WDT clock source 0x00 00 IRC oscillator 01 Main clock 10 Watchdog oscillator 11 Reserved 31 22 Reserved 0x00 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 26 of 290 NXP Semiconductors U M1 0375 UM10375_0 Chapter 3 LPC13xx System configuration 5 27 WDT clock source update enable register 5 28 5 29 This register updates the clock source of the watchdog timer with the new input clock after the WDTCLKSEL register has been written t
166. CLOCK DIVIDER SSP_PCLK irc_osc_clk 4 CLOCK DIVIDER UART_PCLK wdt_osc_clk 4 CLOCK DIVIDER ARM trace clock MAINCLKSEL CLOCK SYSTICK irc_osc_clk sys_pllclkout f DIVIDER timer sys_osc_clk SYS PLL wdt_osc_clk sys_pllclkin irc_osc_clk CLOCK Ik DIVIDER wat_e SYSPLLCLKSEL wdt_osc_clk WDTUEN Ik lIclk syS_OSC_C USB PLL usb_pllclkout ER usb_pllclkin Ik i DIVIDER usb_c USBPLLCLKSEL USBUEN irc_osc_clk sys_osc_clk CLOCK clkout_clk wdt_osc_clk DIVIDER gt CLKOUTUEN USB is available in parts LPC134x only Fig 3 LPC13xx CGU block diagram 5 Register description All registers regardless of size are on word address boundaries Details of the registers appear in the description of each function UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 11 of 290 NXP Semiconductors UM10375 Chapter 3 LPC13xx System configuration Table 5 Register overview system control block base address 0x4004 8000 Name Access Address offset Description Reset Reference value SYSMEMREMAP R W 0x000 System memory remap 0x00 Table 3 6 PRESETCTRL R W 0x004 Peripheral reset control 0x00 Table 3 7 SYSPLLCTRL R W 0x008 System PLL control 0x00 Table 3 8 SYSPLLSTAT R 0x00C System PLL status 0x00 Table 3 9 USBPLLCTRL R W 0x010 USB PLL control 0x00 Table 3 10 USBPLLSTAT R 0x014 USB PLL status 0x00 Table 3 11 0x018 0x01C Reserved SYSOSCCTRL R W 0x020 System oscillat
167. C_PD 2 FLASH_PD 3 BOD_PD 4 ADC_PD 5 SYSOSC_PD 6 WDTOSC_PD 7 SYSPLL_PD 8 USBPLL_PD 9 MAINREG_PD 10 USBPAD_PD 31 11 Value Description IRC oscillator power down wake up configuration Powered down Powered Flash wake up configuration Powered down Powered BOD wake up configuration Powered down Powered ADC wake up configuration Powered down Powered System oscillator wake up configuration Powered down Powered Watchdog oscillator wake up configuration Powered down Powered System PLL wake up configuration Powered down Powered USB PLL wake up configuration Powered down Powered Main regulator power mode wake up configuration Main regulator in reduced power mode Main regulator in normal power mode USB pad wake up configuration USB PHY powered down USB PHY powered Reserved Reset value lt tbd gt Power down configuration register The bits in the PDRUNCFG register control the power to the various analog blocks This register can be written to at any time while the chip is running and a write will take effect immediately with the exception of the power down signal to the IRC To avoid glitches when powering down the IRC the IRC clock is automatically switched off at a clean point Therefore for the IRC a delay is possible before the power down state takes effect O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 37 of 290 NXP S
168. DSTAT register is 1 The ADINT bit is one when any of the DONE bits of A D channels that are enabled for interrupts via the ADINTEN register are one Software can use the Interrupt Enable bit in the interrupt controller that corresponds to the ADC to control whether this results in an interrupt The result register for an A D channel that is generating an interrupt must be read in order to clear the corresponding DONE flag O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 245 of 290 UM10375 Chapter 17 LPC13xx WatchDog timer WDT Rev 00 10 19 October 2009 User manual 1 How to read this chapter 2 Features The WDT block is identical for all LPC13xx parts 3 Applications Internally resets chip if not periodically reloaded Debug mode Enabled by software but requires a hardware reset or a Watchdog reset interrupt to be disabled Incorrect Incomplete feed sequence causes reset interrupt if enabled Flag to indicate Watchdog reset Programmable 32 bit timer with internal pre scaler Selectable time period from Twoctk x 256 x 4 to Twocik x 232 x 4 in multiples of Twocik x 4 The Watchdog clock WDCLK source is selected in the syscon block from the Internal RC oscillator IRC the main clock or the Watchdog oscillator see Table 3 31 This gives a wide range of potential timing choices for Watchdog operation under different power reduction conditions For increas
169. Deep power down flag 0x0 1 Read Deep power down mode entered 0x0 Write Clear the Deep power down flag 0 Read Deep power down mode not entered 0x0 Write No effect 31 12 Reserved Do not write ones to this bit 0x0 2 2 General purpose registers 0 to 3 The general purpose registers retain data through the Deep power down mode when power is still applied to the Vop zv3 pin but the chip has entered Deep power down mode Only a cold boot when all power has been completely removed from the chip will reset the general purpose registers UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 49 of 290 NXP Semiconductors U M1 0375 2 3 Chapter 4 LPC13xx Power Management Unit PMU Table 58 General purpose registers 0 to 3 GPREGO GPREG3 address 0x4003 8004 to 0x4003 8010 bit description Bit Symbol Description Reset value 31 0 GPDATA Data retained during Deep power down mode 0x0 General purpose register 4 The general purpose register 4 retains data through the Deep power down mode when power is still applied to the Vop zv3 pin but the chip has entered Deep power down mode Only a cold boot when all power has been completely removed from the chip will reset the general purpose registers Remark If the external voltage applied on pin Vpp 3v3 drops below lt tbd gt V the hysteresis of the WAKEUP input pin has to be disabled in order for the chip to wak
170. Deep sleep mode the start logic s wake up signals are ignored This guarantees that the Deep sleep mode is not entered for too short a time which could cause a glitch on the Power down signals Once the LPC13xx Deep sleep request is asserted the Syscon block will power down the core the PDRUNCFG register will be loaded with the PDSLEEPCFG value and the selected analog blocks will be powered down on subsequent clock edges After a further 30 ns delay the LPC13xx is in Deep sleep mode and can now accept start signals from the start logic to wake up Remark If the IRC is selected for power down the Deep sleep finite state machine will wait for a signal asserting that the IRC has been switched off safely before starting the 30 ns delay time see Section 3 9 2 Powering down the 12 MHz IRC oscillator The IRC employs a mechanism that ensures that the 12 MHz oscillator is always switched off without a glitch Once the 12 MHz oscillator is switched off within two 12 MHz clock cycles an acknowledge signal will be sent to the Syscon block Remark The IRC is the only oscillator on the LPC13xx that can always shut down glitch free Therefore it is recommended that the user switches the clock source to the 12 MHz IRC before the chip enters Deep sleep mode unless another clock source is selected to remain powered during Deep sleep mode NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 42 of 290 NXP
171. Details on how to select the right value for UODLL and UODLM can be found in Section 10 5 15 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 133 of 290 NXP Semiconductors UM10375 UM10375_0 5 4 Table 154 UART Chapter 10 LPC13xx UART Divisor Latch LSB Register UODLL address 0x4000 8000 when DLAB 1 bit description Bit Symbol 7 0 DLLSB 31 8 Description Reset value The UART Divisor Latch LSB Register along with the UODLM 0x01 register determines the baud rate of the UART Reserved Table 155 UART Divisor Latch MSB Register UODLM address 0x4000 8004 when DLAB 1 bit description Bit Symbol 7 0 DLMSB 31 8 Description Reset value The UART Divisor Latch MSB Register along with the UODLL 0x00 register determines the baud rate of the UART Reserved UART Interrupt Enable Register UOIER 0x4000 8004 when DLAB 0 The UOIER is used to enable the four UART interrupt sources Table 156 UART Interrupt Enable Register UOIER address 0x4000 8004 when DLAB 0 bit description Bit Symbol Value Description Reset value 0 RBR Enables the Receive Data Available interrupt for UART It 0 Interrupt also controls the Character Receive Time out interrupt Enable 1 THRE Interrupt Enable 2 RX Line Interrupt Enable 3 6 4 7 8 ABEOIntEn 9 ABTOIntEn 31 10 0 Disable the RDA interrupt Enable the RD
172. ERROR BUSY Description Command is executed successfully Invalid command Source address is not on a word boundary Destination address is not on a correct boundary Source address is not mapped in the memory map Count value is taken in to consideration where applicable Destination address is not mapped in the memory map Count value is taken in to consideration where applicable Byte count is not multiple of 4 or is not a permitted value Sector number is invalid Sector is not blank Command to prepare sector for write operation was not executed Source and destination data is not same flash programming hardware interface is busy 14 Serial Wire Debug SWD flash programming interface Debug tools can write parts of the flash image to the RAM and then execute the IAP call Copy RAM to flash repeatedly with proper offset 15 Flash memory access Depending on the system clock frequency access to the flash memory can be configured with various access times by writing to the FLASHCFG register at address 0x4003 C010 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 272 of 290 NXP Semiconductors UM10375 UM10375_0 Chapter 18 LPC13xx Flash memory programming firmware Remark Improper setting of this register may result in incorrect operation of the LPC13xx flash memory Table 284 Flash configuration register FLASHCFG address 0x400
173. FO is at least half full 0 TXRIS This bit is 1 if the Tx FIFO is at least half empty 1 7 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined SSPO Masked Interrupt Status Register SSPOMIS 0x4004 001C This read only register contains a 1 for each interrupt condition that is asserted and enabled in the SSPOIMSC When an SSP interrupt occurs the interrupt service routine should read this register to determine the cause s of the interrupt Table 183 SSPO Masked Interrupt Status register SSPOMIS address 0x4004 001C bit description Bit Symbol Description Reset Value 0 RORMIS This bit is 1 if another frame was completely received while the 0 RxFIFO was full and this interrupt is enabled 1 RTMIS This bit is 1 if the Rx FIFO is not empty has not been read for 0 a timeout period and this interrupt is enabled 2 RXMIS This bit is 1 if the Rx FIFO is at least half full and this interrupt 0 is enabled 3 TXMIS This bit is 1 if the Tx FIFO is at least half empty and this 0 interrupt is enabled 7 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 161 of 290 NXP Semiconductors U M1 0375 Chapter 11 LPC13xx SSP 6 9 SSPO Interrupt Clear Register SSPOICR 0x4004 0020 Software can w
174. Flash address gt lt RAM address gt lt number of bytes gt Described in Table 18 257 Table 18 258 Table 18 259 Table 18 260 Table 18 261 Table 18 262 Table 18 263 Table 18 264 Table 18 265 Table 18 266 Table 18 267 Table 18 269 Table 18 270 Table 18 271 Unlock lt Unlock code gt Table 257 ISP Unlock command Command U Input Unlock code 2313040 Return Code CMD SUCCESS INVALID_CODE PARAM_ERROR Description Example This command is used to unlock Flash Write Erase and Go commands U 23130 lt CR gt lt LF gt unlocks the Flash Write Erase amp Go commands Set Baud Rate lt Baud Rate gt lt stop bit gt Table 258 ISP Set Baud Rate command Command B Input Baud Rate 9600 19200 38400 57600 115200 230400 Stop bit 1 2 Return Code CMD SUCCESS INVALID_BAUD_RATE INVALID_STOP_BIT PARAM_ERROR Description This command is used to change the baud rate The new baud rate is effective after the command handler sends the CMD_SUCCESS return code Example B 57600 1 lt CR gt lt LF gt sets the serial port to baud rate 57600 bps and 1 stop bit NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 260 of 290 NXP Semiconductors U M1 0375 UM10375_0 12 3 12 4 12 5 Chapter 18 LPC13xx Flash memory programming firmware Echo lt setting gt Table 259 ISP Echo command Command A Input Setting ON 1 OFF 0 Return
175. For OUT endpoints the FE bit gives ORed result of the B_1_FULL and B_2 FULL bits For single buffered endpoints this bit simply reflects the status of B_1_ FULL For an IN endpoint at least one write endpoint buffer is empty For an OUT endpoint at least one endpoint read buffer is full Stalled endpoint indicator 0 The selected endpoint is not stalled The selected endpoint is stalled O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 121 of 290 NXP Semiconductors U M1 0375 UM10375_0 10 11 10 12 Chapter 9 LPC13xx USB device controller Table 147 Select Endpoint Register bit description Bit Symbol Value Description Reset value 2 STP SETUP bit the value of this bit is updated after each 0 successfully received packet i e an ACKed package on that particular physical endpoint 0 The STP bit is cleared by doing a Select Endpoint Clear Interrupt on this endpoint 1 The last received packet for the selected endpoint was a SETUP packet 3 PO Packet over written bit 0 0 The PO bit is cleared by the Select Endpoint Clear Interrupt command 1 The previously received packet was over written by a SETUP packet 4 EPN EP NAKed bit indicates sending of a NAK If the host sends an 0 OUT packet to a filled OUT buffer the device returns NAK If the host sends an IN token packet to an empty IN buffer the device returns NAK 0 The EPN bit is reset after the device has s
176. GH for one CLK period The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 162 of 290 NXP Semiconductors U M1 0375 7 2 7 2 1 7 2 2 Chapter 11 LPC13xx SSP transmit logic On the next rising edge of CLK the MSB of the 4 bit to 16 bit data frame is shifted out on the DX pin Likewise the MSB of the received data is shifted onto the DR pin by the off chip serial slave device Both the SSP and the off chip serial slave device then clock each data bit into their serial shifter on the falling edge of each CLK The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched SPI frame format The SPI interface is a four wire interface where the SSEL signal behaves as a slave select The main feature of the SPI format is that the inactive state and phase of the SCK signal are programmable through the CPOL and CPHA bits within the SSPCRO control register Clock Polarity CPOL and Phase CPHA control When the CPOL clock polarity control bit is LOW it produces a steady state low value on the SCK pin If the CPOL clock polarity control bit is HIGH a steady state high value is placed on the CLK pin when data is not being transferred The CPHA control bit selects the clock edge that captures data and allows it
177. I O configuration Remark Note that once the pin location has been selected the function still must be set to SCK in the corresponding IOCONF registers for the SCK to be usable on that pin Table 105 IOCON SCK location register OCON_SCKLOC address 0x4004 40B0 bit description Bit Symbol Value Description Reset value 1 0 SCKLOC Selects pin location for SCK pin 000 00 Selects SCK function for pin SWCLK PIO0_10 SCK CT16B0_MAT2 see Table 5 87 01 Selects SCK function for pin PIO2_11 SCK see Table 5 89 10 Selects SCK function for pin PIOO_6 USB_CONNECT SCK see Table 5 80 11 Reserved 31 2 Reserved NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 82 of 290 UM10375 Chapter 6 LPC13xx Interrupt controller Rev 00 10 19 October 2009 User manual 1 How to read this chapter Interrupts 47 and 48 in Table 6 106 are available on parts LPC 1342 43 with USB only These interrupts are reserved on parts LPC 1311 13 The implementation of start logic wake up interrupts depends on how many PIO port pins are available see Section 3 1 For HVQFN packages only wake up interrupts O to 24 and interrupt 38 are available 2 Introduction 3 Features The Nested Vectored Interrupt Controller NVIC is an integral part of the Cortex M3 The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts Refer to th
178. INREG_PD 10 USBPAD_PD 31 11 Value Description BOD power down control in Deep sleep mode Powered down Powered ADC power down control in Deep sleep mode Powered down Powered System oscillator power down control in Deep sleep mode Powered down Powered Watchdog oscillator power down control in Deep sleep mode Powered down Powered System PLL power down control in Deep sleep mode Powered down Powered USB PLL power down control in Deep sleep mode Powered down Powered Main regulator power mode in Deep sleep mode Main regulator in reduced power mode Main regulator in normal power mode USB pad power down control in Deep sleep mode USB PHY powered down USB PHY powered Reserved Reset value 0 lt tbd gt Wake up configuration register The bits in this register can be programmed to indicate the state the chip must enter when itis waking up from Deep sleep mode Table 50 Wake up configuration register PDAWAKECFG address 0x4004 8234 bit description Bit Symbol Value Description Reset value 0 IRCOUT_PD IRC oscillator output wake up configuration 0 Powered down Powered O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 36 of 290 NXP Semiconductors UM10375 UM10375_0 5 46 Table 50 Wake up configuration register PDAWAKECFG address 0x4004 8234 bit description Chapter 3 LPC13xx System configuration Bit Symbol 1 IR
179. LH together determine the clock frequency generated by an I C master and certain times used in slave mode I2CONCLR WO 0x018 12C Control Clear Register When a one is written to a bit of this register NA the corresponding bit in the I C control register is cleared Writing a zero has no effect on the corresponding bit in the 12C control register I2MMCTRL R W 0x01C Monitor mode control register 0x00 I2ADR1 R W 0x020 12C Slave Address Register 1 Contains the 7 bit slave address for 0x00 operation of the 12C interface in slave mode and is not used in master mode The least significant bit determines whether a slave responds to the General Call address I12ADR2 R W 0x024 12C Slave Address Register 2 Contains the 7 bit slave address for 0x00 operation of the 12C interface in slave mode and is not used in master mode The least significant bit determines whether a slave responds to the General Call address I12ADR3 R W 0x028 12C Slave Address Register 3 Contains the 7 bit slave address for 0x00 operation of the 12C interface in slave mode and is not used in master mode The least significant bit determines whether a slave responds to the General Call address I2DATA_ RO 0x02C Data buffer register The contents of the 8 MSBs of the I2DAT shift 0x00 BUFFER register will be transferred to the DATA_BUFFER automatically after every nine bits 8 bits of data plus ACK or NACK has been received on the bus UM10375_0 O NXP B V 2009 All rights
180. M mode is enabled for CT32Bn_MAT1 0 When zero CT32Bn_MAT1 is controlled by EM1 2 PWM enable When one PWM mode is enabled for CT32Bn_MAT2 0 When zero CT32Bn_MAT2 is controlled by EM2 3 PWM enable When one PWM mode is enabled for CT32Bn_MAT3 0 When zero CT32Bn_MAT3 is controlled by EM3 Note It is recommended to use match channel 3 to set the PWM cycle 4 32 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 7 13 Rules for single edge controlled PWM outputs 1 All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle timer is set to zero unless their match value is equal to zero 2 Each PWM output will go HIGH when its match value is reached If no match occurs i e the match value is greater than the PWM cycle length the PWM output remains continuously LOW 3 If a match value larger than the PWM cycle length is written to the match register and the PWM signal is HIGH already then the PWM signal will be cleared with the start of the next PWM cycle 4 If a match register contains the same value as the timer reset value the PWM cycle length then the PWM output will be reset to LOW on the next clock tick after the timer reaches the match value Therefore the PWM output will always consist of a one clock tick wide positive pulse with a period determined by the PWM cycle length i e the timer reload value 5 If a match re
181. M10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 29 of 290 NXP Semiconductors U M1 0375 UM10375_0 5 35 5 36 Chapter 3 LPC13xx System configuration System tick counter calibration register Table 40 System tick timer calibration register SYSTCKCAL address 0x4004 8158 bit description Bit Symbol Value Description Reset value 25 0 CAL System tick timer calibration value lt tbd gt 31 26 z Reserved 0x00 Start logic edge control register 0 The STARTAPRPO register controls the start logic inputs of ports 0 PIOO_0 to PIOO_11 and 1 PIO1_0 to PIO1_11 and the lower 8 inputs of port 2 PIO2_0 to PIO2_7 This register selects a falling or rising edge on the corresponding PIO input to produce a falling or rising clock edge respectively for the start logic see Section 3 9 3 Every bit in the STARTAPRPO register controls one port input and is connected to one wake up interrupt in the NVIC Bit 0 in the STARTAPRPO register corresponds to interrupt O bit 1 to interrupt 1 etc see Table 6 106 The bottom 32 interrupts are contained this register the top 8 interrupts are contained in the STARTAPRP1 register for total of 40 wake up interrupts Remark Each interrupt connected to a start logic input must be enabled in the NVIC if the corresponding PIO pin is used to wake up the chip from Deep sleep mode Table 41 Start logic edge control register 0 STARTAPRPO
182. MASK3 7 2 12C Status register I2STAT 0x4000 0004 173 183 7 3 12C Data register 12DAT 0x4000 0008 173 9 4 Comparator 2 00200e 2 eee 183 7 4 12 SCL HIGH duty cycle register and LOW duty 95 Shift register IZDAT o on aana 183 cycle register I2SCLH 0x4000 0010 and I2SCLL 96 Arbitration and synchronization logic 183 0x4000 0014 occ 173 9 7 Serial clock generator 184 7 4 1 Selecting the appropriate I C data rate and duty 9 8 Timing and control 185 pce Feet tet eters 173 99 Control register I2CONSET and I2CONCLR 185 75 o ed register I2CONCLR AS 9 10 Status decoder and status register 185 X4000 0018 ooo j 2 7 6 12C Monitor mode control register I2CMMCTRLO pe 1 ata aii ONE O Ox4000 001C 2 000 175 i a a AO 7 6 1 Interrupt in Monitor mode 176 o iaa a a A A i 7 6 2 Loss of arbitration in Monitor mode 176 10 4 cre Liane ad as DI 192 7 7 12C Data buffer register I2CDATA_BUFFER ae ecelar ao ios oe 0x4000 002C 20 02 eeeeee 176 ee ene ee ee eet Va dye tS eat 7 8 12C Slave Address registers I2ADR 1 2 3 ae eae PE ne A ren een ea icine iaehetass Ge 10 8 Some special cases 05 199 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 287 of 290 NXP Semiconductors UM10375 Chapter 20 LPC13xx Supplementary information 10 9
183. Masked read operation 88 LPC1343 LQFP48 package 90 LPC1342 43 HVQFN33 package 91 LPC1313 LQFP48 package 92 LPC1311 13 HVQFN33 package 93 USB device controller block diagram 102 USB SoftConnect interfacing 103 USB clocking 0 0 ee eee eee 105 Auto RTS Functional Timing 137 Auto CTS Functional Timing 138 Auto baud a mode 0 and b mode 1 waveform 144 Algorithm for setting UART dividers 146 UART block diagram o o ooooooo 152 Texas Instruments Synchronous Serial Frame Format a Single and b Continuous back to back Two Frames Transfer o ooooocoooo o 160 SPI frame format with CPOL 0 and CPHA 0 a Single and b Continuous Transfer 162 SPI frame format with CPOL 0 and CPHA 1 163 SPI frame format with CPOL 1 and CPHA 0 a Single and b Continuous Transfer 164 SPI Frame Format with CPOL 1 and CPHA 1 165 Microwire frame format single transfer 166 Microwire frame format continuos transfers 166 Microwire frame format setup and hold details 167 I12C bus configuration 169 Format in the Master Transmitter mode 178 Format of Master Receiver mode 179 A Master Receiver switches to Master Transmitter after sending Repeated START 179 Format of Slave Receiver mode
184. O flag will be reset STOP condition followed by a START condition will be transmitted STO flag will be reset Data byte will be transmitted ACK bit will be received Repeated START will be transmitted STOP condition will be transmitted STO flag will be reset STOP condition followed by a START condition will be transmitted STO flag will be reset 12C bus will be released not addressed slave will be entered A START condition will be transmitted when the bus becomes free UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 195 of 290 UM10375 Chapter 12 LPC13xx I2C bus interface NXP Semiconductors Table 206 Master Receiver mode Status Status of the I2C bus Application software response Next action taken by I2C hardware Code and hardware To From I2DAT To I2CON I2CSTAT STA STO SI AA 0x08 A START condition Load SLA R X 0 0 Xx SLA R will be transmitted ACK bit will be has been transmitted received 0x10 A Repeated START Load SLA R or Xx 0 0 Xx As above condition has been gag SLA W X 0 0 X SLA Wwillbe transmitted the I2C block transmitted will be switched to MST TRX mode 0x38 Arbitration lostin NOT No I2DAT action 0 0 0 Xx 12C bus will be released the 12C block will ACK bit or enter a slave mode No I2DAT action 1 0 0 X A START condition will be transmitted when the bus becomes free 0x40 SLA R has been No I2DAT action 0 0 0 0 Data byte will b
185. O configuration Table 91 IOCON_JTAG_TMS_PIO1_0 register IOCON_JTAG_TMS_PIO1_0 address 0x4004 4078 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function TMS 001 Selects function PIO1_0 010 Selects function AD1 011 Selects function CT32B1_CAPO 100 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 7 ADMODE Select Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 31 8 Reserved UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 73 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 92 IOCON_JTAG_TDO_PIO1_1 register IOCON_JTAG_TDO_ PIO1_1 address 0x4004 407C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function TDO 001 Selects function PIO1_1 010 Selects function AD2 011 Selects function CT32B1_MATO 100 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable
186. OD register take effect Table 245 Watchdog Mode register WDMOD address 0x4000 4000 bit description Bit Symbol Description Reset Value 0 WDEN WDEN Watchdog enable bit Set Only When 1 the 0 watchdog timer is running 1 WDRESET WDRESET Watchdog reset enable bit Set Only When 1 0 a watchdog time out will cause a chip reset 2 WDTOF WDTOF Watchdog time out flag Set when the watchdog 0 After any timer times out cleared by software reset except WDT 3 WDINT WDINT Watchdog interrupt flag Read Only not clearable 0 by software 7 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 31 8 reserved Once the WDEN and or WDRESET bits are set they can not be cleared by software Both flags are cleared by reset or a Watchdog timer underflow WDTOF The Watchdog time out flag is set when the Watchdog times out This flag is cleared by software or any reset except the WDT reset WDINT The Watchdog interrupt flag is set when the Watchdog times out This flag is cleared when any reset occurs Once the watchdog interrupt is serviced it can be disabled in the NVIC or the watchdog interrupt request will be generated indefinitely the intent of the watchdog interrupt is to allow debugging watchdog activity without resetting the device when the watchdog overflows Watchdog reset or interrupt will occur any time the watchdog is running and has an operating clock
187. ON_JTAG_TDI_PIOO_11 address 0x4004 Table 63 IOCON_PIO2_6 register IOCON_PIO2_6 4074 bit description 70 address 0x4004 4000 bit description 55 Table 91 IOCON_JTAG_TMS_PIO1_0 register Table 64 IOCON_PIO2_0 register IOCON_PIO2_0 IOCON_JTAG_TMS_PIO1_0 address 0x4004 address 0x4004 4008 bit description 55 4078 bit description 71 Table 65 IOCON_nRESET_PIOO_0 register Table 92 IOCON_JTAG_TDO_PIO1_1 register IOCON_nRESET_PIOO_0 address 0x4004 IOCON_JTAG_TDO_PIO1_1 address 0x4004 400C bit descripti0N o 56 407C bit description 72 Table 66 IOCON_PIO0_1 register IOCON_PIOO_1 Table 93 IOCON_JTAG_nTRST_PIO1_2 register address 0x4004 4010 bit description 57 IOCON_JTAG_nTRST_PIO1_ 2 address 0x4004 Table 67 IOCON_PIO1_8 register IOCON_PIO1_ 8 4080 bit description 73 address 0x4004 4014 bit description 57 Table 94 IOCON_PIO3_0 register IOCON_PIO3_0 Table 68 IOCON_PIOO_2 register IOCON_PIOO_2 address 0x4004 4084 bit description 73 address 0x4004 401C bit description 58 Table 95 IOCON_PIO3_1 register IOCON_PIO3_1 Table 69 IOCON_PIO2_7 register IOCON_PIO2_7 address 0x4004 4088 bit description 74 address 0x4004 4020 bit description 58 Table 96 IOCON_PIO2_3 register IOCON_PIO2_3 Table 70 IOCON_PIO2_8 register IOCON_PIO2_8 address 0x4004 408C bit descript
188. ON_PIOO_9 yes yes Table 5 86 IPIO0_10 IOCON_JTAG_TCK_PIOO_10 yes yes Table 5 87 PIO0_11 IOCON_JTAG_TDI_PIOO_11 yes yes Table 5 90 PIO1_0 IOCON_JTAG_TMS_PIO1_0 yes yes Table 5 91 IPIO1_1 IOCON_JTAG_TDO_PIO1_1 yes yes Table 5 92 IPIO1_2 IOCON_JTAG_nTRST_PIO1_2 yes yes Table 5 93 PIO1_3 IOCON_SWDIO_PIO1_3 yes yes Table 5 97 PIO1_4 IOCON_PIO1_4 yes yes Table 5 98 PIO1_5 IOCON_PIO1_5 yes yes Table 5 101 PIO1_6 IOCON_PIO1_6 yes yes Table 5 102 PIO1_7 IOCON_PIO1_7 yes yes Table 5 103 PIO1_8 IOCON_PIO1_8 yes yes Table 5 67 PIO1_9 IOCON_PIO1_9 yes yes Table 5 75 PIO1_10 IOCON_PIO1_10 yes yes Table 5 88 PIO1_11 lOCON_PIO1_11 yes yes Table 5 99 PIO2_0 IOCON_PIO2_0 yes yes Table 5 64 PIO2_1 IOCON_PIO2_1 yes no Table 5 71 PIO2_2 IOCON_PIO2_2 yes no Table 5 84 PIO2_3 IOCON_PIO2_3 yes no Table 5 96 IPIO24 lIOCON_PIO2_4 yes no Table 5 77 PIO2_5 IOCON_PIO2_5 yes no Table 5 78 PIO2_6 IOCON_PIO2_6 yes no Table 5 63 PIO2_7 IOCON_PIO2_7 yes no Table 5 69 PIO2_8 IOCON_PIO2_8 yes no Table 5 70 PIO2_9 IOCON_PIO2 9 yes no Table 5 82 PIO2 10 IOCON_PIO2_10 yes no Table 5 83 PIO2 11 lOCON_PIO2_11 yes no Table 5 89 IPIO3_0 IOCON_PIO3_0 yes no Table 5 94 PIO3_1 IOCON_PIO3_1 yes no Table 5 95 PIO3 2 IOCON_PIO3_ 2 yes yes Table 5 100 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 56 of 290 NXP Semiconductors UM10375 4 1 Chapter 5 LPC13xx I O configuration Table 62 1 O configuration registers ordered by port nu
189. P Semiconductors U M1 0375 Chapter 12 LPC13xx I2C bus interface Fig 40 Format and states in the Slave Transmitter mode reception of the own Slave address and l one or more Data DATA A PORS bytes all are I acknowledged Ge Ban D arbitration lost as l Master and gt A addressed as Slave 1 last data byte Bor transmitted Switched ones Pons to Not Addressed ALL ONES PORS Slave AA bit in 12CON 0 from Slave to Master DATA A any number of data bytes and their associated i Acknowledge bits this number contained in I2STA corresponds to a defined state of the PC bus from Master to Slave UM10375_0 10 4 Slave Transmitter mode In the slave transmitter mode a number of data bytes are transmitted to a master receiver see Figure 12 40 Data transfer is initialized as in the slave receiver mode When I2ADR and I2CON have been initialized the 12C block waits until it is addressed by its own slave address followed by the data direction bit which must be 1 R for the 12C block to operate in the slave transmitter mode After its own slave address and the R bit have been received the serial interrupt flag SI is set and a valid status code can be read from I2STAT This status code is used to vector to a state service routine and the appropriate action to be taken for each of these status codes is detailed in Table 12 208 The slave transmitter mode may als
190. PPED COUNT_ERROR Byte count is not multiple of 4 PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to download data to RAM Data should be in UU encoded format This command is blocked when code read protection is enabled Example W 268436224 4 lt CR gt lt LF gt writes 4 bytes of data to address 0x1000 0300 Read Memory lt address gt lt no of bytes gt The data stream is followed by the command success return code The check sum is sent after transmitting 20 UU encoded lines The checksum is generated by adding raw data before UU encoding bytes and is reset after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes When the data fits in less then 20 UU encoded lines then the check sum is of actual number of bytes sent The host should compare it with the checksum of the received bytes If the check sum matches then the host should respond with NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 261 of 290 NXP Semiconductors U M1 0375 12 6 UM10375_0 Chapter 18 LPC13xx Flash memory programming firmware OK lt CR gt lt LF gt to continue further transmission If the check sum does not match then the host should respond with RESEND lt CR gt lt LF gt In response the ISP command handler sends the data again Table 261 ISP Read Memory command Command R
191. R W or Data bytes To From I2DAT Load SLA W clear STA Load SLA W or Load SLA R Clear STA Load data byte or No I2DAT action or No I2DAT action or No I2DAT action Load data byte or No I2DAT action or No I2DAT action or No I2DAT action Load data byte or No I2DAT action or No I2DAT action or No I2DAT action Load data byte or No 12DAT action or No I12DAT action or No I2DAT action No I2DAT action or No I2DAT action To 12CON STA STO SI X 0 0 X 0 0 X 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 Next action taken by I2C hardware SLA W will be transmitted ACK bit will be received As above SLA W will be transmitted the 12C block will be switched to MST REC mode Data byte will be transmitted ACK bit will be received Repeated START will be transmitted STOP condition will be transmitted STO flag will be reset STOP condition followed by a START condition will be transmitted STO flag will be reset Data byte will be transmitted ACK bit will be received Repeated START will be transmitted STOP condition will be transmitted STO flag will be reset STOP condition followed by a START condition will be transmitted STO flag will be reset Data byte will be transmitted ACK bit will be received Repeated START will be transmitted STOP condition will be transmitted ST
192. RAM 4 8 kB AHB TO FLASH APB 8 16 32 kB BRIDGE y ee O a rra WDT 002aae722 CLKOUT ADI7 0 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 5 of 290 UM10375 Chapter 2 LPC13xx Memory mapping Rev 00 10 19 October 2009 User manual 1 How to read this chapter See Table 2 2 for LPC13xx memory configurations Table 2 LPC13xx memory configuration Part Flash Address range SRAM Address range LPC1311 8kB 0x0000 0000 0x0000 1FFF 4kB 0x1000 0000 0x1000 OFFF LPC1313 32kB 0x0000 0000 0x0000 7FFF 8kB 0x1000 0000 0x1000 1FFF LPC1342 16kB 0x0000 0000 0x0000 3FFF 4kB 0x1000 0000 0x1000 OFFF LPC1343 32 kB 0x0000 0000 0x0000 7FFF 8 amp kB 0x1000 0000 0x1000 1FFF 2 Memory map UM10375_0 Figure 2 2 shows the memory and peripheral address space of the LPC13xx The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals On the LPC13xx the GPIO ports are the only AHB peripherals The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals Each peripheral of either type is allocated 16 kB of space This allows simplifying the address decoding for each peripheral All peripheral register addresses are 32 bit word aligned regardless of their size An implication of this is that word and half word registers must be accessed all at once For example it
193. RPIO2_7 PIO2_7 0 No start signal received 1 Start signal pending 4 SRPIO3_0 Start signal status for start logic input PIO3_0 n a 0 No start signal received 1 Start signal pending 7 5 SRPIO3_3 to Start signal status for start logic input PIO3_3 to n a SRPIO3_1 PIO3_1 0 No start signal received 1 Start signal pending 31 8 Reserved n a Deep sleep mode configuration register The bits in this register can be programmed to indicate the state the chip must enter when the Deep sleep mode is asserted by the ARM The value of the PDSLEEPCFG register will be automatically loaded into the PDRUNCFG register when the Sleep mode is entered Table 49 Deep sleep configuration register PDSLEEPCFG address 0x4004 8230 bit description Bit Symbol Value Description Reset value 0 IRCOUT_PD IRC oscillator output power down control in 0 Deep sleep mode 1 Powered down 0 Powered 1 IRC_PD IRC oscillator power down control in Deep sleep 0 mode 1 Powered down 0 Powered 2 FLASH_PD Flash power down control in Deep sleep mode 0 1 Powered down 0 Powered O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 35 of 290 NXP Semiconductors UM10375 UM10375_0 5 45 Chapter 3 LPC13xx System configuration Table 49 Deep sleep configuration register PDSLEEPCFG address 0x4004 8230 bit description Bit Symbol 3 BOD_PD 4 ADC_PD 5 SYSOSC_PD 6 WDTOSC_PD 7 SYSPLL_PD 8 USBPLL_PD 9 MA
194. Reset offset valuel R W 0x014 Match Control Register MCR The MCR is used to control if an 0 interrupt is generated and if the TC is reset when a Match occurs R W 0x018 Match Register 0 MRO MRO can be enabled through the MCR to reset 0 the TC stop both the TC and PC and or generate an interrupt every time MRO matches the TC R W 0x01C Match Register 1 MR1 See MRO description 0 R W 0x020 Match Register 2 MR2 See MRO description 0 R W 0x024 Match Register 3 MR3 See MRO description 0 R W 0x028 Capture Control Register CCR The CCR controls which edges of the 0 capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place RO 0x02C Capture Register 0 CRO CRO is loaded with the value of TC when 0 there is an event on the CT32B0_CAPO input R W 0x03C External Match Register EMR The EMR controls the match function 0 and the external match pins CT32B0_MATT 3 0 0x040 reserved 0x06C R W 0x070 Count Control Register CTCR The CTCR selects between Timer and 0 Counter mode and in Counter mode selects the signal and edge s for counting R W 0x074 PWM Control Register PWMCON The PWMCON enables PWM 0 mode for the external match pins CT32B0_MAT 3 0 1 Reset value reflects the data stored in used bits only lt does not include reserved bits content Table 223 Register overview 32 bit counter timer 1 CT32B1 base address 0x4001 8000
195. SB clock configuration 122 115 11 2 USB device controller initialization 123 10 2 Configure Device Command 0xD8 Data write 1 12 Functional description 123 byte ee eee eee teens 15 121 Data flow from the Host to the Device 123 10 3 Set Mode Command OxF3 Data write 1 byte 12 2 Data flow from the Device to the Host 124 115 12 3 Interrupt based transfer 124 10 4 Read Interrupt Status Command OxF4 Data 12 4 Isochronous transfer 124 read 2 bytes 2 2 2 serene eee 116 12 5 Automatic stall feature 125 10 5 es ns mber Command ae 6 13 Double buffered endpoint operation 125 A E O ee 13 1 Bulk endpoints 2 0 125 13 2 Isochronous endpoints 127 Chapter 10 LPC13xx UART 1 How to read this chapter 128 5 9 UART Line Status Register UOLSR 2 A vedegxeddwnetse 128 0x4000 8014 Read Only 139 3 Pin description 0 00eeee 128 510 UART Modem Status Register 140 5 11 UART Scratch Pad Register UOSCR 4 Clocking and power control 128 0x4000 801C ese e cece ee nnu 141 5 Register description 129 5 12 UART Auto baud Control Register UOACR 5 1 UART Receiver Buffer Register UORBR Ox4000 8020 cece eee eee 141 0x4000 8000 when DLAB 0 Read Only 131 5 13 Aut o baud ccnescaene s
196. SSP_PCLK clock divider values 0x00 0 Disable SSP_PCLK 1 Divide by 1 to sil 255 Divide by 255 31 8 Reserved 0x00 UART clock divider register This register configures the UART peripheral clock UART_PCLK The UART_PCLK can be shut down by setting the DIV bits to 0x0 Remark Note that the UART pins must be configured in the IOCON block before the UART clock can be enabled Table 25 UART clock divider register UARTCLKDIV address 0x4004 8098 bit description Bit Symbol Value Description Reset value 7 0 DIV UART_PCLK clock divider values 0x00 0 Disable UART_PCLK 1 Divide by 1 to ate 255 Divide by 255 31 8 Reserved 0x00 Trace clock divider register This register configures the ARM trace clock The trace clock can be shut down by setting the DIV bits to 0x0 Table 26 TRACECLKDIV clock divider register TRACECLKDIV address 0x4004 80AC bit description Bit Symbol Value Description Reset value 7 0 DIV ARM trace clock divider values 0x00 0 Disable trace clock 1 Divide by 1 to wey 255 Divide by 255 31 8 Reserved 0x00 SYSTICK clock divider register This register configures the SYSTICK peripheral clock The SYSTICK timer clock can be shut down by setting the DIV bits to 0x0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 24 of 290 NXP Semiconductors U M1 0375 UM10375_0 5 23 Chapter 3 LPC13xx System configuration Table 27 SY
197. STICK clock divider register SYSTICKCLKDIV address 0x4004 80B0 bit description Bit Symbol Value Description Reset value 7 0 DIV SYSTICK clock divider values 0x00 0 Disable SYSTICK timer clock 1 Divide by 1 to ae 255 Divide by 255 31 8 Reserved 0x00 USB clock source select register This register selects the clock source for the USB usb_clk The clock source can be either the USB PLL output or the main clock and the clock can be further divided by the USBCLKDIV register see Table 3 30 to obtain a 48 MHz clock The USBCLKUEN register see Section 3 5 24 must be toggled from LOW to HIGH for the update to take effect Table 28 USB clock source select register USBCLKSEL address 0x4004 80C0 bit description Bit Symbol Value Description Reset value 1 0 SEL USB clock source 0x00 00 USB PLL out 01 Main clock 10 Reserved 11 Reserved 31 22 Reserved 0x00 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 25 of 290 NXP Semiconductors U M1 0375 UM10375_0 Chapter 3 LPC13xx System configuration 5 24 USB clock source update enable register 5 25 5 26 This register updates the clock source of the USB with the new input clock after the USBCLKSEL register has been written to In order for the update to take effect first write a zero to the USBCLKUEN register and then write a one to USBCLKUEN Table 29 USB clock source update enable register USB
198. Semiconductors U M1 0375 UM10375_0 5 40 5 41 Chapter 3 LPC13xx System configuration Table 44 Start logic status register 0 STARTSRPO address 0x4004 820C bit description Bit Symbol Value Description Reset value 24 SRPIO2_0 Start signal status for start logic input PIO2_0 n a 0 No start signal received 1 Start signal pending 31 25 SRPIO2_7 to Start signal status for start logic input PIO2_7 to n a SRPIO2_1 PIO2_1 0 No start signal received 1 Start signal pending Start logic edge control register 1 The STARTAPRP1 register controls the start logic inputs of ports 2 PIO2_8 to PIO2_11 and 3 PIO3_0 to PIO3_3 This register selects a falling or rising edge on the corresponding PIO input to produce a falling or rising clock edge respectively for the start up logic Every bit in the STARTAPRP1 register controls one port input and is connected to one wake up interrupt in the NVIC Bit 0 in the STARTAPRP1 register corresponds to interrupt 32 bit 1 to interrupt 33 up to bit 7 corresponding to interrupt 39 see Table 6 106 Remark Each interrupt connected to a start logic input must be enabled in the NVIC if the corresponding PIO pin is used to wake up the chip from Deep sleep mode Table 45 Start logic edge control register 1 STARTAPRP1 address 0x4004 8210 bit description Bit Symbol Value Description Reset value 0 APRPIO2_8 Edge select for start logic input PIO2_8 0 0 Falling edge 1 Rising edge 3
199. T action X 0 0 0 Data byte will be received and NOT ACK been received ACK or will be returned has been returned No 12DAT action X 0 0 1 Databyte will be received and ACK will be returned 0x68 Arbitration lost in No I2DAT action X 0 0 0 Data byte will be received and NOT ACK SLA R W as master or will be returned Own SLA W has No I2DAT action X 0 0 1 Databyte will be received and ACK will been received ACK be retumed returned 0x70 General call address No I2DAT action X 0 0 0 Data byte will be received and NOT ACK 0x00 has been or will be returned received ACK has Ni 12DAT action X 0 0 1 Databyte will be received and ACK will been returned be returned 0x78 Arbitration lost in No I2DAT action X 0 0 0 Data byte will be received and NOT ACK SLA R W as master or will be returned General call address No 2DAT action X 0 0 1 Databyte will be received and ACK wil has been received be returned ACK has been returned 0x80 Previously addressed Read data byte or X 0 0 0 Data byte will be received and NOT ACK with own SLV will be returned address DATA has Read data byte X 0 0 1 Databyte will be received and ACK will been received ACK be retumed has been returned 0x88 Previously addressed Read data byte or 0 0 0 0 Switched to not addressed SLV mode no with own SLA DATA recognition of own SLA or General call byte has been address received NOT ACK Read data byte or 0 0 0 1 Switched to not addressed SLV mode has been returned Own SLA wi
200. T32B0 base address 0x4001 4000 Name Access Address Description Reset offset valuel TMR32BOIR R W 0x000 Interrupt Register IR The IR can be written to clear interrupts The IR 0 can be read to identify which of five possible interrupt sources are pending TMR32BOTCR R W 0x004 Timer Control Register TCR The TCR is used to control the Timer 0 Counter functions The Timer Counter can be disabled or reset through the TCR TMR32BO0TC R W 0x008 Timer Counter TC The 32 bit TC is incremented every PR 1 cycles of 0 PCLK The TC is controlled through the TCR TMR32BOPR R W 0x00C Prescale Register PR When the Prescale Counter below is equal to 0 this value the next clock increments the TC and clears the PC TMR32BOPC R W 0x010 Prescale Counter PC The 32 bit PC is a counter which is incremented 0 to the value stored in PR When the value in PR is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 225 of 290 NXP Semiconductors UM10375 Chapter 14 LPC13xx 32 bit counter timer CT32B Table 222 Register overview 32 bit counter timer 0 CT32B0 base address 0x4001 4000 continued Name TMR32BOMCR TMR32BOMRO TMR32BOMR1 TMR32BOMR2 TMR32BOMR3 TMR32BO0CCR TMR32BO0CRO TMR32BOEMR TMR32BOCTCR TMR32BOPWMC Access Address Description
201. UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 114 of 290 NXP Semiconductors U M1 0375 Chapter 9 LPC13xx USB device controller Table 138 USB Device FIQ Select register USBDevFIQSel address 0x4002 002C bit description Bit Symbol Value Description Reset value 1 BULKOUT Interrupt routing for bulk out endpoints 1 0 0 BULKOUT interrupt will be routed to the low priority interrupt line IRQ 1 BULKOUT interrupt will be routed to the high priority interrupt line FIQ 2 BULKIN Interrupt routing for bulk in endpoints Li 0 0 BULKIN interrupt will be routed to the low priority interrupt line IRQ 1 BULKIN interrupt will be routed to the high priority interrupt line FIQ 31 3 Reserved 1 Remark For logical endpoint 3 physical endpoints 6 and 7 only 10 Serial interface engine command description The functions and registers of the Serial Interface Engine SIE are accessed using commands which consist of a command code followed by optional data bytes read or write action The USBCmdCode Table 9 131 and USBCmdData Table 9 132 registers are used for these accesses A complete access consists of two phases 1 Command phase the USBCmdCode register is written with the CMD_PHASE field set to the value 0x05 Command and the CMD_CODE field set to the desired command code On completion of the command the CCEMPTY bit of USBDevIntSt is set 2 Data phase optional
202. XP Semiconductors U M1 0375 UM10375_0 Chapter 12 LPC13xx I2C bus interface When STA is 1 and the 12C interface is not already in master mode it enters master mode checks the bus and generates a START condition if the bus is free If the bus is not free it waits for a STOP condition which will free the bus and generates a START condition after a delay of a half clock period of the internal clock generator If the 12C interface is already in master mode and data has been transmitted or received it transmits a Repeated START condition STA may be set at any time including when the I C interface is in an addressed slave mode STA can be cleared by writing 1 to the STAC bit in the I2CONCLR register When STA is 0 no START condition or Repeated START condition will be generated If STA and STO are both set then a STOP condition is transmitted on the 12C bus if it the interface is in master mode and transmits a START condition thereafter If the 12C interface is in slave mode an internal STOP condition is generated but is not transmitted on the bus STO is the STOP flag Setting this bit causes the 12C interface to transmit a STOP condition in master mode or recover from an error condition in slave mode When STO is 1 in master mode a STOP condition is transmitted on the 12C bus When the bus detects the STOP condition STO is cleared automatically In slave mode setting this bit can recover from an error condition In this case
203. a CT16Bn_CAPO event will 0 generate an interrupt This feature is disabled Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined UM10375_0 7 9 7 10 Capture Register CT16BOCRO address 0x4000 C02C and CT16B1CRO address 0x4001 002C Each Capture register is associated with a device pin and may be loaded with the counter timer value when a specified event occurs on that pin The settings in the Capture Control Register register determine whether the capture function is enabled and whether a capture event happens on the rising edge of the associated pin the falling edge or on both edges External Match Register TMR16BOEMR and TMR16B1EMR The External Match Register provides both control and status of the external match channels and external match pins CT16B0_MAT 2 0 and CT16B1_MAT 1 0 If the match outputs are configured as PWM output in the PWMCON registers Section 13 7 12 the function of the external match registers is determined by the PWM rules Section 13 7 13 Rules for single edge controlled PWM outputs on page 221 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 218 of 290 NXP Semiconductors UM10375 Chapter 13 LPC13xx 16 bit counter timer CT16B Table 217 External Match Register TMR16BOEMR address 0x4000 C03C and TMR16B1EMR address 0x4001 003C bit description Bit
204. a START condition is transmitted the serial interrupt flag SI is set and the status code in the status register I2STAT will be 0x08 This status code is used by the interrupt service routine to enter the appropriate state service routine that loads I2DAT with the slave address and the data direction bit SLA W The SI bit in I2CON must then be reset before the serial transfer can continue When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received the serial interrupt flag Sl is set again and a number of status codes in I2STAT are possible There are 0x18 0x20 or 0x38 for the master mode and also 0x68 0x78 or OxBO if the slave mode was enabled AA logic 1 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 188 of 290 NXP Semiconductors U M1 0375 UM10375_0 10 2 10 3 Chapter 12 LPC13xx I2C bus interface The appropriate action to be taken for each of these status codes is detailed in Table 12 205 After a Repeated START condition state 0x10 The 12C block may switch to the master receiver mode by loading I2DAT with SLA R Master Receiver mode In the master receiver mode a number of data bytes are received from a slave transmitter see Figure 12 38 The transfer is initialized as in the master transmitter mode When the START condition has been transmitted the interrupt service routine must load I2DAT with the 7 bit slav
205. able 191 12C SCL Low duty cycle register I2SCLL 0x4000 0014 bit description 173 Table 192 12SCLL I2SCLH values for selected 12C clock VAMOS italia a a ra bn 174 Table 193 12C Control Clear register I2CONCLR 0x4000 0018 bit description 174 Table 194 12C Monitor mode control register I2CMMCTRLO 0x4000 001C bit description 175 Table 195 12C Data buffer register I2CDATA_BUFFER 0x4000 002C bit description 176 Table 196 12C Slave Address registers IZADR 1 2 3 0x4000 00 20 24 28 bit description 177 Table 197 12C Mask registers I2MASKT O 1 2 3 0x4000 00 30 34 38 3C bit description 177 Table 198 12CONSET used to configure Master mode 178 Table 199 12CONSET used to configure Slave mode 180 Table 200 Abbreviations used to describe an 12C operation 186 Table 201 12CONSET used to initialize Master Transmitter MODO ies sean cad rat dona 186 Table 202 12ADR usage in Slave Receiver mode 187 Table 203 12CONSET used to initialize Slave Receiver mode 187 Table 204 Master Transmitter mode 193 Table 205 Master Receiver M0de 194 Table 206 Slave Receiver MOde 195 Table 207 Slave Transmitter mode 197 Table 208 Miscellaneous StateS 199 Table 209 Counter timer pin description 211 Table 210 Register overview 16 bit counter timer 0 CT16B0 base address 0x4
206. able 214 Timer Control Register TMR16BOTCR address 0x4000 C004 and TMR16B1TCR address 0x4001 0004 bit description Bit Symbol Description Reset value 0 Counter Enable When one the Timer Counter and Prescale Counter are 0 enabled for counting When zero the counters are disabled 1 Counter Reset When one the Timer Counter and the Prescale Counter 0 are synchronously reset on the next positive edge of PCLK The counters remain reset until TCR 1 is returned to zero 31 2 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 7 3 Timer Counter TMR16BOTC address 0x4000 C008 and TMR16B1TC address 0x4001 0008 The 16 bit Timer Counter is incremented when the Prescale Counter reaches its terminal count Unless it is reset before reaching its upper limit the TC will count up through the value 0x0000 FFFF and then wrap back to the value 0x0000 0000 This event does not cause an interrupt but a Match register can be used to detect an overflow if needed 7 4 Prescale Register TMR16BOPR address 0x4000 COOC and TMR16B1PR address 0x4001 000C The 16 bit Prescale Register specifies the maximum value for the Prescale Counter 7 5 Prescale Counter register TMR16BOPC address 0x4000 C010 and TMR16B1PC address 0x4001 0010 The 16 bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter This allows con
207. able 275 IAP Copy RAM to flash command Command Input Return Code Result Description Copy RAM to flash Command code 5110 Param0 DST Destination flash address where data bytes are to be written This address should be a 256 byte boundary Param1 SRC Source RAM address from which data bytes are to be read This address should be a word boundary Param2 Number of bytes to be written Should be 256 512 1024 4096 Param3 System Clock Frequency CCLK in kHz CMD_SUCCESS SRC_ADDR_ERROR Address not a word boundary DST_ADDR_ERROR Address not on correct boundary SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR Byte count is not 256 512 1024 4096 SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION BUSY None This command is used to program the flash memory The affected sectors should be prepared first by calling Prepare Sector for Write Operation command The affected sectors are automatically protected again once the copy command is successfully executed The boot sector can not be written by this command UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 269 of 290 NXP Semiconductors UM10375 UM10375_0 Chapter 18 LPC13xx Flash memory programming firmware 13 3 Erase Sector s 13 4 13 5 Table 276 IAP Erase Sector s command Command Input Return Code Result Description Erase Sector s Command code 52
208. able bit high and should program the logical endpoint number The control logic will first fetch the packet length to the receive packet length register Also the hardware fills the receive data register with the first word of the packet The software can now start reading the receive data register When the end of packet is reached the Read Enable bit will be disabled by the control logic and RXENDPKT bit is set in the Device interrupt status register O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 113 of 290 NXP Semiconductors U M1 0375 9 4 9 4 1 Chapter 9 LPC13xx USB device controller If the software makes the Read Enable bit low midway the reading will be terminated In this case the data will remain in the RAM When the Read Enable signal is made high again for this endpoint data will be read from the beginning For writing data to an endpoint buffer the Write Enable bit should be made high and software should write to the Tx Packet Length register the number of bytes it is going to send in the packet It can then write data continuously in the Transmit Data register When the control logic receives the number of bytes programmed in the Tx Packet length register it will reset the Write Enable bit If the software resets this bit midway writing will start again from the beginning Both Read Enable and Write Enable bits can be high at the same time for the same logical endpoint The in
209. address 0x4004 8200 bit description Bit Symbol Value Description Reset value 0 APRPIO0_0 Edge select for start logic input PIOO_0 0 0 Falling edge 1 Rising edge 11 1 APRPIOO_11 Edge select for start logic input PIOO_11 to PIOO_1 0 ReneS Falling edge Rising edge 12 APRPIO1_0 Edge select for start logic input PIO1_0 0 0 Falling edge 1 Rising edge 23 13 APRPIO1_11 Edge select for start logic input PIO1_11 to PIO1_1 0 ARERO Falling edge Rising edge 24 APRPIO2_0 Edge select for start logic input PIO2_0 0 0 Falling edge 1 Rising edge 31 25 APRPIO2_7 Edge select for start logic input PIO2_7 to PIO2_1 0 APREIGES Falling edge Rising edge NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 30 of 290 NXP Semiconductors UM10375 UM10375_0 Chapter 3 LPC13xx System configuration 5 37 Start logic signal enable register 0 This STARTERPO register enables or disables the start signal bits in the start logic The bit assignment is identical to Table 3 41 5 38 Table 42 Start logic signal enable register 0 STARTERPO address 0x4004 8204 bit description Bit Symbol Value Description Reset value 0 ERPIOO_0 Enable start signal for start logic input PIOO_0 0 0 Disabled 1 Enabled 11 1 ERPIOO_11 to Enable start signal for start logic input PIOO_11 to 0 ERPIO_0_1 PIOO_1 0 Disabled 1 Enabled 12 ERPIO1_0 Enable start signal for start logic input PIO1_0 0 0 Disabled 1 Enabled 23 1
210. ains any of the first 512 bytes starting from address zero First 512 bytes are re mapped to boot ROM Example M 8192 268468224 4 lt CR gt lt LF gt compares 4 bytes from the RAM address 0x1000 8000 to the 4 bytes from the flash address 0x2000 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 265 of 290 NXP Semiconductors UM10375 UM10375_0 12 14 12 15 Chapter 18 LPC13xx Flash memory programming firmware ReadUID Table 271 ReadUID command Command N Input None Return Code CMD_SUCCESS followed by four 32 bit words of E sort test information in ASCII format The word sent at the lowest address is sent first Description This command is used to read the unique ID ISP Return Codes Table 272 ISP Return Codes Summary Return Mnemonic Code 0 CMD_SUCCESS 1 INVALID COMMAND 2 SRC_ADDR_ERROR 3 DST_ADDR_ERROR 4 SRC_ADDR_NOT_MAPPED 5 DST_ADDR_NOT_MAPPED 6 COUNT_ERROR 7 INVALID_ SECTOR SECTOR_NOT_BLANK 9 SECTOR_NOT_PREPARED_FOR_ WRITE_OPERATION 10 COMPARE_ERROR 11 BUSY 12 PARAM_ERROR 13 ADDR_ERROR 14 ADDR_NOT_MAPPED 15 CMD_LOCKED 16 INVALID_CODE 17 INVALID_BAUD_RATE 18 INVALID_STOP_BIT 19 CODE_READ_PROTECTION_ ENABLED Description Command is executed successfully Sent by ISP handler only when command given by the host has been completely and successfully executed Invalid command Source address is not on word boundary Des
211. al purpose digital input output pin CT16B1_CAPO Capture input O for 16 bit timer 1 PIO1_9 CT16B1_MATO 171 1 0 PIO1_9 General purpose digital input output pin O CT16B1_MATO Match output O for 16 bit timer 1 PIO1_10 AD6 3013 1 0 PI01_10 General purpose digital input output pin CT16B1_MAT1 AD6 A D converter input 6 O CT16B1_MAT1 Match output 1 for 16 bit timer 1 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 97 of 290 NXP Semiconductors UM10375 Chapter 8 LPC13xx Pin configuration Table 119 LPC1313 43 LQFP48 pin description table continued Symbol PIO1_11 AD7 PIO2_0 DTR PIO2_1 DSR PIO2_2 DCD PIO2_3 RI PIO2 4 PIO2 4 PIO2_5 PIO2_5 PIO2_6 PIO2 7 PIO2_8 PIO2_9 PIO2_10 PIO2_11 SCK PIO3_0 PIO3_1 PIO3 2 PIO3 3 PIO3 4 PIO3_5 USB_DM USB_DP Vbo 10 VDp 3v3 Vssio XTALIN XTALOUT Vss Pin 42 26l gel 1811 1914 21 2011 8 1 1 11 1 114 121 2411 2511 31 36l 371 43 48111 elt 21 19 41 20 41 8 44 5 1 1 1 65 78l 41 Type 1 0 1 0 O 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 O l Description PIO1_11 General purpose digital input output pin AD7 A D converter input 7 PIO2_0 General purpose digital input output pi
212. ames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master In practice it is often the case that only one of these data flows carries meaningful data The LPC13xx has one Synchronous Serial Port controller UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 155 of 290 NXP Semiconductors U M1 0375 Chapter 11 LPC13xx SSP 4 Pin description Table 174 SSP pin descriptions Interface pin Pin Type name function Pin description name SPI SSI Microwire SCK VO SCK CLK SK Serial Clock SCK CLK SK is a clock signal used to synchronize the transfer of data It is driven by the master and received by the slave When SPI interface is used the clock is programmable to be active high or active low otherwise it is always active high SCK only switches during a data transfer Any other time the SSP interface either holds it in its inactive state or does not drive it leaves it in high impedance state SSEL VO SSEL FS CS Frame Sync Slave Select When the SSP interface is a bus master it drives this signal to an active state before the start of serial data and then releases it to an inactive state after the data has been sent The active state of this signal can be high or low depending upon the selected bus and mode When the SSP interface is a bus slave this signal qualifies the presence of data from the Master according to the protocol in u
213. and handler or the USB device enumeration without checking for a valid user code first The state of PIOO_3 determines whether the UART or USB interface will be used O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 251 of 290 NXP Semiconductors U M1 0375 Chapter 18 LPC13xx Flash memory programming firmware e If PIOO_3 is sampled HIGH the boot loader connects the LPC134x as a MSC USB device to a PC host The LPC134x flash memory space is represented as a drive in the host s Windows or Linux operating system If PIOO_3 is sampled LOW the boot loader configures the UART serial port and calls the ISP command handler Remark On the LPC131x parts no USB the state of pin PIOO_3 does not matter Assuming that power supply pins are at their nominal levels when the rising edge on RESET pin is generated it may take up to 3 ms before PIOO_1 is sampled and the decision on whether to continue with user code or ISP handler USB is made If PIOO_1 is sampled low and the watchdog overflow flag is set the external hardware request to start the ISP command handler is ignored If there is no request for the ISP command handler execution PIOO_1 is sampled HIGH after reset a search is made for a valid user program If a valid user program is found then the execution control is transferred to it If a valid user program is not found the auto baud routine is invoked Pin PIOO_1 is used as hardware req
214. and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from national authorities 2 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners 12C bus logo is a trademark of NXP B V O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 277 of 290 NXP Semiconductors UM10375 Chapter 20 LPC13xx Supplementary information 3 Tables Table 1 Ordering options for the LPC13xx parts 4 address 0x4004 8098 bit description 23 Table 2 LPC13xx memory configuration 6 Table 26 TRACECLKDIV clock divider register Table 3 USB related registers and register bits reserved TRACECLKDIV address 0x4004 80AC bit for LPC1311 13 0 0 00 2c eee eee 8 description usan c eee eee 23 Table 4 Pinsummary 00 0 e eee ee eee 9 Table 27 SYSTICK clock divider register Table 5 Register overview system control block base SYSTICKCLKDIV address 0x4004 80B0 b
215. ands UM10375_0 The following commands are accepted by the ISP command handler Detailed status codes are supported for each command The command handler sends the return code INVALID_ COMMAND when an undefined command is received Commands and return codes are in ASCII format CMD_SUCCESS is sent by ISP command handler only when received ISP command has been completely executed and the new ISP command can be given by the host Exceptions from this rule are Set Baud Rate Write to RAM Read Memory and Go commands O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 259 of 290 NXP Semiconductors UM10375 UM10375_0 12 1 12 2 Chapter 18 LPC13xx Flash memory programming firmware Table 256 ISP command summary ISP Command Usage Unlock U lt Unlock Code gt Set Baud Rate B lt Baud Rate gt lt stop bit gt Echo A lt setting gt Write to RAM W lt start address gt lt number of bytes gt Read Memory R lt address gt lt number of bytes gt Prepare sector s for P lt start sector number gt lt end sector number gt write operation Copy RAM to flash Go G lt address gt lt Mode gt Erase sector s E lt start sector number gt lt end sector number gt Blank check sector s lt start sector number gt lt end sector number gt Read Part ID J Read Boot code version K Compare M lt address1 gt lt address2 gt lt number of bytes gt ReadUID N C lt
216. anual Rev 00 10 19 October 2009 67 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 83 IOCON_PIO2_10 register IOCON_PIO2_10 address 0x4004 4058 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO2_10 001 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 3 Reserved 1 31 7 Reserved Table 84 IOCON_PIO2_2 register IOCON_PIO2_2 address 0x4004 405C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO2_2 001 Select function DCD 010to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 68 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 85 IOCON_PIOO_8 register IOCON_PIOO_8 address 0x4004 4060 bit description Bit Symbol Value Description Rese
217. are output to indicate the beginning and the end of a serial transfer The 12C interface will enter master transmitter mode when software sets the STA bit The 12C logic will send the START condition as soon as the bus is free After the START condition is transmitted the SI bit is set and the status code in the I2STAT register is 0x08 This status code is used to vector to a state service routine which will load the slave address and Write bit to the I2DAT register and then clear the SI bit Sl is cleared by writing a 1 to the SIC bit in the I2CONCLR register NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 180 of 290 NXP Semiconductors U M1 0375 UM10375_0 8 2 Chapter 12 LPC13xx I2C bus interface When the slave address and R W bit have been transmitted and an acknowledgment bit has been received the Sl bit is set again and the possible status codes now are 0x18 0x20 or 0x38 for the master mode or 0x68 0x78 or OxBO if the slave mode was enabled by setting AA to 1 The appropriate actions to be taken for each of these status codes are shown in Table 12 205 to Table 12 208 0 write 1 read data transferred n Bytes Acknowledge A Acknowledge SDA low A Not acknowledge SDA high S START condition P STOP condition O from Master to Slave O from Slave to Master Fig 29 Format in the Master Transmitter mode Master Receiver m
218. atus Code 12CSTAT OxA8 OxBO 0xB8 OxCO 0xC8 Status of the I2C bus Application software response and hardware To From 12DAT Own SLA R has been received ACK has been returned Load data byte or Load data byte Arbitration lost in SLA R W as master Own SLA R has been received ACK has been returned Data byte in I2DAT has been transmitted ACK has been received Load data byte or Load data byte Load data byte or Load data byte Data byte in l2DAT No I2DAT action has been transmitted or NOT ACK has been received No I2DAT action or No 12DAT action or No I2DAT action Last data byte in No I2DAT action I2DAT has been or transmitted AA 0 ACK has been received No l2DAT action or No 12DAT action or No I2DAT action To 12CON STA STO SI X 0 0 X 0 0 X 0 0 X 0 0 X 0 0 X 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 AA 01 Next action taken by I2C hardware Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted ACK will be received Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted ACK bit will be received Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted ACK bit will be received Switched to not addressed SLV mode no recognition of own SLA or General call address Switched to not addressed SLV
219. bit will be set in USBDeviIntSt 31 10 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined USB Control register USBCtrl 0x4002 0028 This register controls the data transfer operation of the USB device It selects the endpoint buffer that is accessed by the USBRxData and USBTxData registers and enables reading and writing them USBCtrl is a read write register Table 137 USB Control register USBCirl address 0x4002 0028 bit description Bit Symbol Value Description Reset value 0 RD_EN Read mode control Enables reading data fromthe OUT 0 endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register This bit is cleared by hardware when the last word of the current packet is read from USBRxData 0 Read mode is disabled 1 Read mode is enabled 1 WR_EN Write mode control Enables writing data to the IN 0 endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register This bit is cleared by hardware when the number of bytes in USBTxLen have been sent 0 Write mode is disabled 1 Write mode is enabled 5 2 LOG_ENDPOINT Logical Endpoint number 0x0 31 6 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined Data transfer When the software wants to read the data from an endpoint buffer it should make the Read En
220. ble 115 GPIOnIRS register GPIOOIRS address 0x5000 8014 to GPIOSIRS address 0x5003 8014 bit GOSCHIPUON vac shit ahah tie wale nus ade die awe Gs 86 Table 116 GPIOnMIS register GPIOOMIS address 0x5000 8018 to GPIO3MIS address 0x5003 8018 bit description scce oceanerne nperi iesi 86 Table 117 GPIOnIC register GPIOOIC address 0x5000 801C to GPIO3IC address 0x5003 801C bit CESCIIPUOMN osise drs so de adi deed 86 Table 118 LPC13xx pin configuration overview 89 Table 119 LPC1313 43 LQFP48 pin description table 94 Table 120 LPC1311 13 42 43 HVQFN33 pin description table siera bie Bad ee lr ee 97 Table 121 USB related acronyms abbreviations and definitions used in this chapter 100 Table 122 Fixed endpoint configuration 101 Table 123 USB device pin description 104 Table 124 USB device controller clock sources 104 Table 125 Register overview USB device base address 0x4002 0000 2 0005 106 Table 126 USB Device Interrupt registers bit allocation 107 Table 127 USB Device Interrupt Status register USBDevintSt address 0x4002 0000 bit description Table 128 USB Device Interrupt Enable register USBDevintEn address 0x4002 0004 bit UM10375_0 Chapter 20 LPC13xx Supplementary information description AD A 108 Table 129 USB Device Interrupt Clear register USBDevintClr address 0x4002 0008 bit GSSCriPLON sii vda rd A 108 Tab
221. bol Description Reset Value 7 0 CPSDVSR This even value between 2 and 254 by which SSP_PCLKis 0 divided to yield the prescaler output clock Bit O always reads as 0 Important the SSPOCPSR value must be properly initialized or the SSP controller will not be able to transmit data correctly In Slave mode the SSP clock rate provided by the master must not exceed 1 12 of the SSP peripheral clock selected in Section 3 5 19 The content of the SSPOCPSR register is not relevant In master mode CPSDVSR min 2 or larger even numbers only SSPO Interrupt Mask Set Clear Register SSPOIMSC 0x4004 0014 This register controls whether each of the four possible interrupt conditions in the SSP controller are enabled Note that ARM uses the word masked in the opposite sense from classic computer terminology in which masked meant disabled ARM uses the word masked to mean enabled To avoid confusion we will not use the word masked Table 181 SSPO Interrupt Mask Set Clear register SSPOIMSC address 0x4004 0014 bit description Bit Symbol Description Reset Value 0 RORIM Software should set this bit to enable interrupt when a Receive 0 Overrun occurs that is when the Rx FIFO is full and another frame is completely received The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs 1 RTIM Software should set this bit to enable interrupt when a Receive
222. ce update enable register 19 9 2 Powering down the 12 MHz IRC oscillator 41 5 15 Main clock source select register 20 9 3 Start logic 0 eee eee 41 5 16 Main clock source update enable register 20 10 PLL System PLL and USB PLL functional 5 17 System AHB clock divider register 20 description a so unnar ounn 41 5 18 System AHB clock control register 21 10 1 Lock detector n nuanua nananana 42 5 19 SSP clock divider register 22 10 2 Direct output mode e eee ee 42 5 20 UART clock divider register 23 10 3 Power down control 222 e 43 5 21 Trace clock divider register ee ee re 23 10 4 Operating modes 0 eeeeeeeee 43 5 22 SYSTICK clock divider register li 23 10 5 Divider ratio programming 43 5 23 USB clock source select register 24 Post divider LooLoo LLL 43 5 24 USB clock source update enable register 25 Feedback divider eeccccceeeee 43 5 25 USB clock divider register 25 Changing the divider values 43 5 26 WDT clock source select register 25 10 6 Frequency selection 0e00 43 5 27 WDT clock source update enable register 26 10 6 1 Mode 1 Normal mode 44 5 28 WDT clock divider register 26 10 6 2 Mode 2 Direct CCO mode 0005 44 5 29 CLKOUT clock source select register 26 10 6 3 Mode 3 Po
223. ceiver is disabled RS485CTRL bit 1 1 any received byte will be discarded if it is either a data byte OR an address byte which fails to match the RS485ADRMATCH value When a matching address character is detected it will be pushed onto the RXFIFO along with the parity bit and the receiver will be automatically enabled RS485CTRL bit 1 will be cleared by hardware The receiver will also generate an Rx Data Ready Interrupt While the receiver is enabled RS485CTRL bit 1 0 all bytes received will be accepted and stored in the RXFIFO until an address byte which does not match the RS485ADRMATCH value is received When this occurs the receiver will be automatically disabled in hardware RS485CTRL bit 1 will be set The received non matching address character will not be stored in the RXFIFO RS 485 ElA 485 Auto Direction Control RS485 EIA 485 mode includes the option of allowing the transmitter to automatically control the state of the DIR pin as a direction control output signal Setting RS485CTRL bit 4 1 enables this feature Direction control if enabled will use the RTS pin when RS485CTRL bit 3 0 It will use the DTR pin when RS485CTRL bit 3 1 When Auto Direction Control is enabled the selected pin will be asserted driven LOW when the CPU writes data into the TXFIFO The pin will be de asserted driven HIGH once the last bit of data has been transmitted See bits 4 and 5 in the RS485CTRL reg
224. ch frame Values 0000 0010 are not supported and should not be used 4 bit transfer 5 bit transfer 6 bit transfer 7 bit transfer 8 bit transfer 9 bit transfer 10 bit transfer 11 bit transfer 12 bit transfer 13 bit transfer 14 bit transfer 15 bit transfer 16 bit transfer NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 157 of 290 NXP Semiconductors UM10375 Chapter 11 LPC13xx SSP Table 176 SSPO Control Register 0 SSPOCRO address 0x4004 0000 bit description Bit Symbol Value 5 4 FRF 00 01 10 11 6 CPOL 0 1 7 CPHA 0 1 15 8 SCR Description Reset Value Frame Format 00 SPI Tl Microwire This combination is not supported and should not be used Clock Out Polarity This bit is only used in SPI mode 0 SSP controller maintains the bus clock low between frames SSP controller maintains the bus clock high between frames Clock Out Phase This bit is only used in SPI mode 0 SSP controller captures serial data on the first clock transition of the frame that is the transition away from the inter frame state of the clock line SSP controller captures serial data on the second clock transition of the frame that is the transition back to the inter frame state of the clock line Serial Clock Rate The number of prescaler output clocks per 0x00 bit on the bus minus one Given that CPSDVSR is the prescale divider and the APB clock PCLK clocks t
225. ch has just been received Data in I2DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of I2DAT While data is being shifted out data on the bus is simultaneously being shifted in I2DAT always contains the last byte present on the bus Thus in the event of lost arbitration the transition from master transmitter to slave receiver is made with the correct data in I2DAT Arbitration and synchronization logic In the master transmitter mode the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the 12C bus If another device on the bus overrules a logic 1 and pulls the SDA line low arbitration is lost and the 12C block immediately changes from master transmitter to slave receiver The 12C block will continue to output clock pulses on SCL until transmission of the current serial byte is complete Arbitration may also be lost in the master receiver mode Loss of arbitration in this mode can only occur while the 12C block is returning a not acknowledge logic 1 to the bus Arbitration is lost when another device on the bus pulls this signal low Since this can occur only at the end of a serial byte the 12C block generates no further clock pulses Figure 12 35 shows the arbitration procedure O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October
226. counter timers with a programmable 16 bit prescaler Counter or timer operation One 16 bit capture channel that can take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt Four 16 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Up to three CT16B0 or two CT16B1 external outputs corresponding to match registers with the following capabilities Set LOW on match Set HIGH on match Toggle on match Do nothing on match For each timer up to four match registers can be configured as PWM allowing to use up to three match outputs as single edge controlled PWM outputs 4 Description Interval timer for counting internal events Pulse Width Demodulator via capture input Free running timer Pulse Width Modulator via match outputs Each Counter timer is designed to count cycles of the peripheral clock PCLK or an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers Each counter timer also includes one capture input to trap the timer value when an input signal transitions optionally generating an interrupt UM10375_0 O NXP B V 2009 All rights reserved User manual Rev
227. ction 000 000 Selects function PIO2_5 001 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 65 of 290 NXP Semiconductors UM10375 Chapter 5 LPC13xx I O configuration Table 79 IOCON_PIO3_5 register IOCON_PIO3_5 address 0x4004 4048 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO3_5 001 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 3 Reserved 1 31 7 Reserved Table 80 IOCON_PIOO_6 register IOCON_PIOO_6 address 0x4004 404C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIOO_6 001 Selects function USB_CONNECT 010 Selects function SCK only if pin PIOO_6 USB_CONNECT SCK selected in Table 5 105 011 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive n
228. ction 12 7 9 to hold received data for a full 9 bit word transmission time Remark The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is 0 i e if the module is NOT in monitor mode Interrupt in Monitor mode All interrupts will occur as normal when the module is in monitor mode This means that the first interrupt will occur when an address match is detected any address received if the MATCH_ALL bit is set otherwise an address matching one of the four address registers Subsequent to an address match detection interrupts will be generated after each data byte is received for a slave write transfer or after each byte that the module thinks it has transmitted for a slave read transfer In this second case the data register will actually contain data transmitted by some other slave on the bus which was actually addressed by the master Following all of these interrupts the processor may read the data register to see what was actually transmitted on the bus Loss of arbitration in Monitor mode In monitor mode the 12C module will not be able to respond to a request for information by the bus master or issue an ACK Some other slave on the bus will respond instead This will most probably result in a lost arbitration state as far as our module is concerned Software should be aware of the fact that the module is in monitor mode and should not respond to any loss of arbitration state that is detected In additi
229. cts between Timer and 0 Counter mode and in Counter mode selects the signal and edge s for counting TMR16BOPWMC R W 0x074 PWM Control Register PWMCON The PWMCON enables PWM mode 0 for the external match pins CT16B0_MATT 2 0 oOo e Oo 1 Reset value reflects the data stored in used bits only It does not include reserved bits content Table 212 Register overview 16 bit counter timer 1 CT16B1 base address 0x4001 0000 Name Access Address Description Reset offset valuel TMR16B1IR R W 0x000 Interrupt Register IR The IR can be written to clear interrupts The IR 0 can be read to identify which of five possible interrupt sources are pending TMR16B1TCR R W 0x004 Timer Control Register TCR The TCR is used to control the Timer 0 Counter functions The Timer Counter can be disabled or reset through the TCR TMR16B1TC R W 0x008 Timer Counter TC The 16 bit TC is incremented every PR 1 cycles of 0 PCLK The TC is controlled through the TCR TMR16B1PR R W 0x00C Prescale Register PR When the Prescale Counter below is equal to 0 this value the next clock increments the TC and clears the PC TMR16B1PC R W 0x010 Prescale Counter PC The 16 bit PC is a counter which is incremented 0 to the value stored in PR When the value in PR is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface UM10375_0 NXP B V 2009 All rights reserved User manual Re
230. curred in 3 5 to 4 5 character times Any UART Rx FIFO activity read or write of UART RSR will clear the interrupt This interrupt is intended to flush the UART RBR after a message has been received that is not a multiple of the trigger level size For example if a peripheral wished to send a 105 character message and the trigger level was 10 characters the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts depending on the service routine resulting in the transfer of the remaining 5 characters Table 158 UART Interrupt Handling UOIIR 3 0 Priority Interrupt Interrupt source Interrupt valuel type reset 0001 a None None 0110 Highest RX Line OE or PEI or FEL or BIL UOLSR Status Readl2 Error 0100 Second RX Data Rx data available or trigger level reached in FIFO UORBR Available UOFCRO 1 Readll or UART FIFO drops below trigger level 1100 Second Character Minimum of one character in the RX FIFO and no UORBR Time out character input or removed during a time period Read indication depending on how many characters are in FIFO and what the trigger level is set at 3 5 to 4 5 character times The exact time will be word length x 7 2 x 8 trigger level number of characters x 8 1 RCLKs 0010 Third THRE THRE 2 UOIIR Readl4 if source of interrupt or THR write 1 Values 0000 0011 0101 0111 1000 1001 10
231. d control logic generates the timing and control signals for serial byte handling This logic block provides the shift pulses for I2DAT enables the comparator generates and detects START and STOP conditions receives and transmits acknowledge bits controls the master and slave modes contains interrupt request logic and monitors the 12C bus status Control register IZCONSET and I2CONCLR The 12C control register contains bits used to control the following 12C block functions start and restart of a serial transfer termination of a serial transfer bit rate address recognition and acknowledgment The contents of the 12C control register may be read as IZCONSET Writing to Il CONSET will set bits in the 12C control register that correspond to ones in the value written Conversely writing to Il CONCLR will clear bits in the 12C control register that correspond to ones in the value written Status decoder and status register The status decoder takes all of the internal status bits and compresses them into a 5 bit code This code is unique for each 12C bus status The 5 bit code may be used to generate vector addresses for fast processing of the various service routines Each service routine processes a particular bus status There are 26 possible bus states if all four modes of the I2C block are used The 5 bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set by hardware
232. d the contents of the data received on the bus If the processor reads the I2DAT shift register as it ordinarily would it could have only one bit time to respond to the interrupt before the received data is overwritten by new data To give the processor more time to respond a new 8 bit read only DATA_BUFFER register will be added The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits 8 bits of data plus ACK or NACK has been received on the bus This means that the processor will have nine bit transmission times to respond to the interrupt and read the data before it is overwritten The processor will still have the ability to read I2DAT directly as usual and the behavior of I2DAT will not be altered in any way Although the DATA_BUFFER register is primarily intended for use in monitor mode with the ENA_SCL bit 0 it will be available for reading at any time under any mode of operation Table 197 12C Data buffer register I2CDATA_BUFFER 0x4000 002C bit description Bit Symbol Description Reset value 7 0 Data This register holds contents of the 8 MSBs of the I2DAT shift 0 register I2C Mask registers IZMASK 0O 1 2 3 0x4000 00 30 34 38 3C The four mask registers each contain seven active bits 7 1 Any bit in these registers which is set to 1 will cause an automatic compare on the corresponding bit of the received address when
233. dback clock output is given by For M gt 1 Fdivo Fclkin M NXP B V 2009 All rights reserved UM10375_0 User manual Rev 00 10 19 October 2009 48 of 290 UM10375 Chapter 4 LPC13xx Power Management Unit PMU Rev 00 10 19 October 2009 User manual 1 Introduction The PMU controls the Deep power down mode Four general purpose register in the PMU can be used to retain data during Deep power down mode 2 Register description Table 56 Register overview PMU base address 0x4003 8000 Name Access Address Description Reset offset value PCON R W 0x000 Power control register 0x0 GPREGO R W 0x004 General purpose register 0 0x0 GPREG1 R W 0x008 General purpose register 1 0x0 GPREG2 R W 0x00C General purpose register 2 0x0 GPREG3 R W 0x010 General purpose register 3 0x0 GPREG4 R W 0x014 General purpose register 4 0x0 2 1 Power control register The power control register selects whether Sleep mode or Deep sleep mode is entered when using the ARM WFI instruction Table 57 Power control register PCON address 0x4003 8000 bit description Bit Symbol Value Description Reset value 0 z Reserved Do not write 1 to this bit 0x0 1 DPDEN Deep power down mode enable 0x0 1 ARM WFI will enter Deep power down mode ARM 0x0 Cortex M3 core powered down 0 ARM WFI will enter Sleep mode clock to ARM 0x0 Cortex M3 core turned off 10 2 Reserved Do not write ones to this bit 0x0 11 DPDFLAG
234. ddress 0 Control endpoint will be in the Stalled state Data toggling is reset for all endpoints All buffers are cleared There is no change to the endpoint interrupt status DEV_STAT interrupt is generated Note Bus resets are ignored when the device is not connected CON 0 0 This bit is cleared when read 1 This bit is set when the device receives a bus reset ADEV_STAT interrupt is generated 7 5 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined Get Device Status Command OxFE Data read 1 byte The Get Device Status command returns the Device Status Register Reading the device status returns 1 byte of data The bit field definition is same as the Set Device Status Register as shown in Table 9 145 Remark To ensure correct operation the DEV_STAT bit of USBDevIntSt must be cleared before executing the Get Device Status command Get Error Code Command OxFF Data read 1 byte Different error conditions can arise inside the SIE The Get Error Code command returns the last error code that occurred The 4 least significant bits form the error code O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 120 of 290 NXP Semiconductors UM10375 UM10375_0 10 10 Chapter 9 LPC13xx USB device controller Table 146 Get Error Code Register bit description Bit Symbol Value 3 0 EC 0000 0001 0010
235. de Analog input mode Digital functional mode Reserved Reset value 000 1 This pin functions as WAKEUP pin if the LPC13xx is in Deep power down mode regardless of the value of FUNC NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 78 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 99 IOCON_PIO1_11 register IOCON_PIO1_11 address 0x4004 4098 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO1_ 11 001 Selects function AD7 010to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 7 ADMODE Select Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 31 8 z Reserved 7 Table 100 IOCON_PIO3_2 register IOCON_PIO3_2 address 0x4004 409C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO3_2 001 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enabl
236. des of processor power reduction Sleep mode Deep sleep mode and Deep power down mode The PMU controls whether the Sleep mode or the Deep power down mode is entered see Section 4 2 1 For Sleep mode the user can configure the remaining power consumption to a large extend by selecting various analog blocks as well as the flash and the oscillators to remain powered or to be shut down This mode with reduced power to the analog blocks is called the Deep sleep mode The CPU clock rate may also be controlled as needed by changing clock sources re configuring PLL values and or altering the system clock divider value This allows a trade off of power versus processing speed based on application requirements Run time power control allows shutting down the clocks to individual o n chip peripherals allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application Selected peripherals UART SSP ARM trace clock SysTick timer Watchdog timer and USB have their for power control Table 53 LPC13xx power and clock control options own clock divider Register Power clock control function Power control Applies to modes PDRUNCFG Table 3 51 Controls power to ADC and analog blocks in any mode running or Run Deep sleep Deep sleep PDSLEEPCFG Table 3 49 Selects which analog blocks are shut down in Deep sleep mode The Deep sleep contents of this register
237. dge of SK At the end of the frame for single transfers the CS signal is pulled HIGH one clock period after the last bit has been latched in the receive serial shifter that causes the data to be transferred to the receive FIFO Note The off chip slave device can tristate the receive line either on the falling edge of SK after the LSB has been latched by the receive shiftier or when the CS pin goes HIGH For continuous transfers data transmission begins and ends in the same manner as a single transfer However the CS line is continuously asserted held LOW and transmission of data occurs back to back The control byte of the next frame follows directly after the LSB of the received data from the current frame Each of the received values is transferred from the receive shifter on the falling edge SK after the LSB of the frame has been latched into the SSP Setup and hold time requirements on CS with respect to SK in Microwire mode In the Microwire mode the SSP slave samples the first bit of receive data on the rising edge of SK after CS has gone LOW Masters that drive a free running SK must ensure that the CS signal has sufficient setup and hold margins with respect to the rising edge of SK Figure 11 27 illustrates these setup and hold time requirements With respect to the SK rising edge on which the first bit of receive data is to be sampled by the SSP slave CS must have a setup of at least two times the period of SK on which the SSP
238. disabled and the clock will not be divided Baud rate calculation UART can operate with or without using the Fractional Divider In real life applications it is likely that the desired baud rate can be achieved using several different Fractional Divider settings The following algorithm illustrates one way of finding a set of DLM DLL MULVAL and DIVADDVAL values Such set of parameters yields a baud rate with a relative error of less than 1 1 from the desired one O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 147 of 290 NXP Semiconductors U M1 0375 UM10375_0 Chapter 10 LPC13xx UART Calculating UART baudrate BR DL PCLK 16 x BR DL gy is an integer DIVADDVAL 0 MULVAL 1 Pick another FR gx from the range 1 1 1 9 DL s Int PCLK 16 x BR x FR p FR PCLK 16 x BR x DL 1 1 lt FR gy lt 1 9 DIVADDVAL table FR MULVAL table FR DLM DL 15 8 DLL DL 7 0 est Fig 18 Algorithm for setting UART dividers O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 148 of 290 NXP Semiconductors U M1 0375 UM10375_0 5 15 1 1 5 15 1 2 5 16 Chapter 10 LPC13xx UART Table 168 Fractional Divider setting look up table FR DivAddVal FR DivAddVal FR DivAddVal FR DivAddVal MulVal MulVal MulVal MulVal 1 000 0 1 1 250 1 4 1 50
239. dress 0x4001 8000 Table 223 Interrupt Register TMR32BOIR address 0x4001 4000 and TMR32B1IR address 0x4001 8000 bit description 225 Table 224 Timer Control Register TMR32BOTCR address 0x4001 4004 and TMR32B1TCR address 0x4001 8004 bit description 226 Table 225 Match Control Register TMR32BOMCR address 0x4001 4014 and TMR32B1MCR address 0x4001 8014 bit description 226 Table 226 Capture Control Register TMR32BOCCR address 0x4001 4028 and TMR32B1CCR address 0x4001 8028 bit description 228 Table 227 External Match Register TMR32BOEMR address 0x4001 403C and TMR32B1EMR address0x4001 803C bit description 229 Table 228 External match control 229 Table 229 Count Control Register TMR32BOCTCR address 0x4001 4070 and TMR32B1TCR address 0x4001 8070 bit description 230 Table 230 PWM Control Register TMR32BOPWMC 0x4001 4074 and TMR32B1PWMC 0x4001 8074 bit descripti0N 231 Table 231 System Tick Timer register map base address OxE000 E000 a iaa a ai E 235 Table 232 System Timer Control and status register STCTRL 0xE000 E010 bit description 235 Table 233 System Timer Reload value register STRELOAD OxE000 E014 bit description 236 Table 234 System Timer Current value register STCURR OxE000 E018 bit description 236 Table 235 System Timer Calibration value register STC
240. dress 0x4004 8078 bit description Bit Symbol Value Description Reset value 7 0 DIV System AHB clock divider values 0x01 0 System clock disabled 1 Divide by 1 to ie 255 Divide by 255 31 8 Reserved 0x00 System AHB clock control register The AHBCLKCTRL register enables the clocks to individual system and peripheral blocks The system clock sys_ahb_clk 0 bit O in the AHBCLKCTRL register provides the clock for the AHB to APB bridge the AHB matrix the ARM Cortex M3 the Syscon block and the PMU This clock cannot be disabled Table 23 System AHB clock control register AHBCLKCTRL address 0x4004 8080 bit description Bit Symbol Value Description Reset value 0 SYS Enables clock for AHB to APB bridge to the AHB 1 matrix to the Cortex M3 FCLK and HCLK to the SysCon and to the PMU This bit is read only 0 Reserved 1 Enabled 1 ROM Enables clock for ROM 1 0 Disabled 1 Enabled 2 RAM Enables clock for RAM 1 0 Disabled 1 Enabled 3 FLASHREG Enables clock for flash register interface 1 0 Disabled 1 Enabled 4 FLASHARRAY Enables clock for flash array access 1 0 Disabled 1 Enabled 5 12C Enables clock for 12C 0 0 Disabled 1 Enabled 6 GPIO Enables clock for GPIO 0 0 Disabled 1 Enabled UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 22 of 290 NXP Semiconductors UM10375 UM10375_0 5 19 Chapter 3 LPC13xx System configuration Table 23 System
241. e 6 Reserved 1 31 7 Reserved 7 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 79 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 101 IOCON_PIO1_5 register IOCON_PIO1_5 address 0x4004 40A0 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO1_5 001 Selects function RTS 010 Selects function CT32B0_CAPO 011to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 z Reserved 1 31 7 Reserved Table 102 IOCON_PIO1_6 register IOCON_PIO1_6 address 0x4004 40A4 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO1_6 001 Selects function UART_RXD 010 Selects function CT32BO_MATO 011 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved 7 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 80 of 29
242. e 7 0 CMD_RDATA Command Read Data 0x00 31 8 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined USB data transfer registers The registers in this group are used for transferring data between endpoint buffers and RAM in Slave mode operation See Section 9 12 Functional description USB Receive Data register USBRxData 0x4002 0018 For an OUT transaction the CPU reads the endpoint buffer data from this register Before reading this register the RD_EN bit and LOG_ENDPOINT field of the USBCtrl register should be set appropriately On reading this register data from the selected endpoint buffer is fetched The data is in little endian format the first byte received from the USB bus will be available in the least significant byte of USBRxData USBRxData is a read only register Table 133 USB Receive Data register USBRxData address 0x4002 0018 bit description Bit Symbol Description Reset value 31 0 RX_DATA Data received 0x0000 0000 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 111 of 290 NXP Semiconductors U M1 0375 UM10375_0 9 3 2 9 3 3 9 3 4 Chapter 9 LPC13xx USB device controller USB Transmit Data register USBTxData 0x4002 021C For an IN transaction the CPU writes the endpoint data into this register Before writing to this register the WR_EN bit and LOG_ENDPOINT field of the USBC
243. e Cortex M3 Technical Reference Manual for details of NVIC operation e Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex M3 e Tightly coupled interrupt controller provides low interrupt latency e Controls system exceptions and peripheral interrupts e In the LPC13xx the NVIC supports up to 56 vectored interrupts e 32 programmable interrupt priority levels with hardware priority level masking e Relocatable vector table e Non Maskable Interrupt NMI e Software interrupt generation 4 Interrupt sources UM10375_0 Table 6 106 lists the interrupt sources for each peripheral function Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller Each line may represent more than one interrupt source There is no significance or priority about what line is connected where except for certain standards from ARM Table 106 Connection of interrupt sources to the Vectored Interrupt Controller Exception Vector Function Flag s Number Offset 39 to 0 start logic wake up Each interrupt is connected to a PIO input pin serving interrupts as wake up pin from Deep sleep mode see Section 3 9 3 40 OXAO 12C0 SI state change 41 OxA4 CT16B0 Match 0 2 Capture 0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 83 of 290 NXP Semiconductors UM10375 UM10375_0 Chapter 6 LPC13xx Interrupt controller Table 106
244. e HIGH state one SCK period after the last bit has been captured For continuous back to back transmissions the SSEL pins remains in its active LOW state until the final bit of the last word has been captured and then returns to its idle state as described above In general for continuous back to back transfers the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer Semiconductor Microwire frame format Figure 11 25 shows the Microwire frame format for a single frame Figure 11 26 shows the same format when back to back frames are transmitted NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 167 of 290 NXP Semiconductors U M1 0375 UM10375_0 Chapter 11 LPC13xx SSP JUUUU UU UU e ES SI si Saul 0 msa ese 4 to 16 bis y of output data Fig 25 Microwire frame format single transfer 8 bit contro gt s lt 4 to 16 bits y lt 4 to 16 bits _y of output data of output data Fig 26 Microwire frame format continuos transfers Microwire format is very similar to SPI format except that transmission is half duplex instead of full duplex using a master slave message passing technique Each serial transmission begins with an 8 bit control word that is transmitted from the SSP to the off chip slave device During this transmission no incoming data is r
245. e address and the data direction bit SLA R The SI bit in I2CON must then be cleared before the serial transfer can continue When the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received the serial interrupt flag Sl is set again and a number of status codes in I2STAT are possible These are 0x40 0x48 or 0x38 for the master mode and also 0x68 0x78 or OxBO if the slave mode was enabled AA 1 The appropriate action to be taken for each of these status codes is detailed in Table 12 206 After a Repeated START condition state 0x10 the 12C block may switch to the master transmitter mode by loading I2DAT with SLA W Slave Receiver mode In the slave receiver mode a number of data bytes are received from a master transmitter see Figure 12 39 To initiate the slave receiver mode I2ADR and 12CON must be loaded as follows Table 203 I2ADR usage in Slave Receiver mode Bit 7 6 5 4 3 2 1 0 Symbol own slave 7 bit address GC The upper 7 bits are the address to which the 12C block will respond when addressed by a master If the LSB GC is set the 12C block will respond to the General Call address 0x00 otherwise it ignores the General Call address Table 204 IZCONSET used to initialize Slave Receiver mode Bit 7 6 5 4 3 2 1 0 Symbol 12EN STA STO SI AA Value 1 0 0 0 1 The 12C bus rate settings do not affect the 12C block in the slave mode I2EN must be
246. e of the UOSCR has occurred Table 165 UART Scratch Pad Register UOSCR address 0x4000 8014 bit description Bit Symbol Description Reset Value 7 0 Pad A readable writable byte 0x00 31 Reserved 8 UART Auto baud Control Register UOACR 0x4000 8020 The UART Auto baud Control Register UOACR controls the process of measuring the incoming clock data rate for the baud rate generation and can be read and written at user s discretion Table 166 Auto baud Control Register UOACR address 0x4000 8020 bit description Bit Symbol Value Description Reset value 0 Start This bit is automatically cleared after auto baud 0 completion 0 Auto baud stop auto baud is not running 1 Auto baud start auto baud is running Auto baud run bit This bit is automatically cleared after auto baud completion 1 Mode Auto baud mode select bit 0 0 Mode 0 1 Mode 1 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 143 of 290 NXP Semiconductors U M1 0375 UM10375_0 5 13 Chapter 10 LPC13xx UART Table 166 Auto baud Conirol Register UOACR address 0x4000 8020 bit description Bit Symbol Value Description Reset value 2 AutoRestart 0 No restart 0 1 Restart in case of time out counter restarts at next 0 UART Rx falling edge 7 3 NA Reserved user software should not write ones to 0 reserved bits The value read from a reserved bit is not defined 8 ABEOIntClr End of a
247. e received NOT ACK bit transmitted ACK has or will be returned been received No I2DAT action 0 0 O 1 Databyte will be received ACK bit will be returned 0x48 SLA R has been No I2DAT action 1 0 0 X Repeated START condition will be transmitted NOT ACK or transmitted has been received No I2DAT action 0 1 0 X STOP condition will be transmitted STO or flag will be reset No I2DAT action 1 1 0 X STOP condition followed by a START condition will be transmitted STO flag will be reset 0x50 Data byte has been Read data byte or 0 0 0 0 Data byte will be received NOT ACK bit received ACK has will be returned been returned Read data byte 0 0 0 1 Data byte will be received ACK bit will be returned 0x58 Data byte has been Read data byte or 1 0 0 Xx Repeated START condition will be received NOT ACK transmitted has been returned Read data byte or 0 1 0 Xx STOP condition will be transmitted STO flag will be reset Read data byte 1 1 0 X STOP condition followed by a START condition will be transmitted STO flag will be reset UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 196 of 290 NXP Semiconductors UM10375 Table 207 Slave Receiver mode Chapter 12 LPC13xx I2C bus interface Status Status of the I2C bus Application software response Next action taken by I2C hardware Coda and hardware To From I2DAT To I2CON I2CSTAT STA STO SI AA 0x60 Own SLA W has No I2DA
248. e up from Deep power down mode Table 59 General purpose register 4 GPREG4 address 0x4003 8014 bit description Bit Symbol Value Description Reset value 9 0 gt Reserved Do not write ones to this bit 0x0 10 WAKEUPHYS WAKEUP pin hysteresis enable 0x0 1 Hysteresis for WAKEUP pin enabled 0 Hysteresis for WAKUP pin disabled 31 11 GPDATA Data retained during Deep power down mode 0x0 3 Functional description UM10375_0 3 1 3 2 Entering Deep power down mode Follow these steps to enter Deep power down mode from normal Run mode 1 optional Save data to be retained during Deep power down to the DATA bits in the four general purpose registers Table 4 58 and Table 4 59 2 Set the DPDEN bit to one on the PCON register Table 4 57 to enable Deep power down mode 3 Issue ARM Cortex M3 WFI WFE instruction After step 3 the PMU turns off the on chip voltage regulator and waits for a wake up signal on the WAKEUP pin Exiting Deep power down mode Follow these steps to wake up the chip from Deep power down mode 1 On the WAKEUP pin transition from HIGH to LOW The PMU will turn on the on chip voltage regulator When the core voltage reaches the power on reset POR trip point a system reset will be triggered and the chip re boots All registers except the GPREGO to GPREG4 and PCON will be in their reset state O NXP B V 2009 All rights reserved User manual Rev 00 10 19 Oc
249. e up pin PIO1_5 General purpose digital input output pin RTS Request To Send output for UART CT32B0_CAPO Capture input O for 32 bit timer 0 PIO1_6 General purpose digital input output pin RXD Receiver input for UART CT32B0_MATO Match output O for 32 bit timer 0 PIO1_7 General purpose digital input output pin TXD Transmitter output for UART CT32B0_MAT1 Match output 1 for 32 bit timer 0 PIO1_8 General purpose digital input output pin CT16B1_CAPO Capture input O for 16 bit timer 1 PIO1_9 General purpose digital input output pin CT16B1_MATO Match output O for 16 bit timer 1 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 100 of 290 NXP Semiconductors UM10375 Chapter 8 LPC13xx Pin configuration Table 120 LPC1311 13 42 43 HVQFN33 pin description table continued Symbol Pin PIO1_10 AD6 20 31 CT16B1_MAT1 PIO1_11 AD7 27 3 PIO2_0 DTR 111 PIO3 2 2811 PIO3_4 131 PIO3_5 141 USB_DM 1314 USB_DP 14 4 Vbo 10 6 Voo av3 29 XTALIN 415 XTALOUT 5 5 Vss 33 Type 1 0 O 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Description PIO1_10 General purpose digital input output pin AD6 A D converter input 6 CT16B1_MAT1 Match output 1 for 16 bit timer 1 PIO1_11 General purpose digital input output pin AD7 A D converter input 7 PIO2_0 General purpose digital input output pin DTR Data
250. eceived by the SSP After the message has been sent the off chip slave decodes it and after waiting one serial clock after the last bit of the 8 bit control message has been sent responds with the required data The returned data is 4 to 16 bit in length making the total frame length anywhere from 13 to 25 bits In this configuration during idle periods e The SK signal is forced LOW e CS is forced HIGH e The transmit data line SO is arbitrarily forced LOW A transmission is triggered by writing a control byte to the transmit FIFO The falling edge of CS causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic and the MSB of the 8 bit control frame to be shifted out onto the SO pin CS remains LOW for the duration of the frame transmission The SI pin remains tristated during this transmission The off chip serial slave device latches each control bit into its serial shifter on the rising edge of each SK After the last bit is latched by the slave device the control byte is decoded during a one clock wait state and the slave responds by transmitting data back to the SSP Each bit is driven onto SI line on the falling edge of SK The SSP in turn O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 168 of 290 NXP Semiconductors U M1 0375 UM10375_0 7 3 1 Chapter 11 LPC13xx SSP latches each bit on the rising e
251. ed and ACK returned Write 0x04 to IZCONSET to set the AA bit Write 0x08 to IZCONCLR to clear the SI flag Set up Slave Receive mode data buffer Initialize Slave data counter Exit ar OO N gt State 0x68 Arbitration has been lost in Slave Address and R W bit as bus Master Own Slave Address Write has been received ACK has been returned Data will be received and ACK will be returned STA is set to restart Master mode after the bus is free again Write 0x24 to I2CONSET to set the STA and AA bits Write 0x08 to I2CONCLR to clear the SI flag Set up Slave Receive mode data buffer Initialize Slave data counter Exit aR U N gt State 0x70 General call has been received ACK has been returned Data will be received and ACK returned Write 0x04 to I2CONSET to set the AA bit Write 0x08 to I2CONCLR to clear the SI flag Set up Slave Receive mode data buffer Initialize Slave data counter Exit ar WP gt O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 208 of 290 NXP Semiconductors U M1 0375 UM10375_0 11 8 4 11 8 5 11 8 6 11 8 7 11 8 8 Chapter 12 LPC13xx I2C bus interface State 0x78 Arbitration has been lost in Slave Address R W bit as bus Master General call has been received and ACK has been returned Data will be received and ACK returned STA is set to restart Master mode after the bus is free again
252. ed reliability it also provides the ability to run the Watchdog timer from an entirely internal source that is not dependent on an external crystal and its associated components and wiring The Watchdog timer can be configured to run in Deep sleep mode 4 Description The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state When enabled the Watchdog will generate a system reset if the user program fails to feed or reload the Watchdog within a predetermined amount of time UM10375_0 The Watchdog consists of a divide by 4 fixed pre scaler and a 32 bit counter The clock is fed to the timer via a pre scaler The timer decrements when clocked The minimum value from which the counter decrements is OxFF Setting a value lower than OxFF causes OxFF to be loaded in the counter Hence the minimum Watchdog interval is TwocLk x 256 x 4 and the maximum Watchdog interval is TwociK x 2 x 4 in multiples of Twocik x 4 The Watchdog should be used in the following manner 1 Set the Watchdog timer constant reload value in WDTC register 2 Setup the Watchdog timer operating mode in WDMOD register O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 246 of 290 NXP Semiconductors U M1 0375 Chapter 17 LPC13xx WatchDog timer WDT 3 Enable the Watchdog by writing OxAA followed by 0x55 to the WDFEED register 4 The Watchd
253. ed with the SoftConnect USB feature LPC1343 only SCK Serial clock for SSP PIOO_7 General purpose digital input output pin high current output driver CTS Clear To Send input for UART PIO0_8 General purpose digital input output pin MISO Master In Slave Out for SSP CT16B0_MATO Match output 0 for 16 bit timer 0 PIO0_9 General purpose digital input output pin MOSI Master Out Slave In for SSP CT16B0_MAT1 Match output 1 for 16 bit timer 0 SWO Serial wire trace output SWCLK Serial wire clock and test clock TCK for JTAG interface PIOO_10 General purpose digital input output pin SCK Serial clock for SSP CT16B0_MAT2 Match output 2 for 16 bit timer 0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 96 of 290 NXP Semiconductors U M1 0375 Chapter 8 LPC13xx Pin configuration Table 119 LPC1313 43 LQFP48 pin description table continued Symbol Pin Type Description TDI PIOO_11 3219 TDI Test Data In for JTAG interface ADO CT32B0_MAT3 1 0 PIO0_11 General purpose digital input output pin ADO A D converter input 0 O CT32B0_MAT3 Match output 3 for 32 bit timer 0 TMS PIO1_0 33181 TMS Test Mode Select for JTAG interface AD1 CT32B1_CAPO 1 0 PIO1_0 General purpose digital input output pin AD1 A D converter input 1 CT32B1_CAPO Capture input O for 32 bit timer 1 TDO PIO1_1
254. eeps adda ee 142 5 2 UART Transmitter Holding Register UOTHR 5 14 Auto baud modes 0 5 143 0x4000 8000 when DLAB 0 Write Only 131 5 15 UART Fractional Divider Register UOFDR 5 3 UART Divisor Latch LSB and MSB Registers 0x4000 8028 00 e eee eee 144 UODLL 0x4000 8000 and UODLM 5 15 1 Baud rate calculation 145 0x4000 8004 when DLAB 1 131 5 15 1 1 Example 1 UART_PCLK 14 7456 MHz BR 5 4 UART Interrupt Enable Register UOIER Out ect Goad ying oe HeLa 147 0x4000 8004 when DLAB 0 132 5 15 1 2 Example 2 UART_PCLK 12 MHz BR 115200 5 5 UART Interrupt Identification Register UOIIR 147 0x4004 8008 Read Only gt jap andy Aa 1 la 133 5 16 UART Transmit Enable Register UOTER 5 5 6 UART FIFO Control Register UOFCR 0x4000 A A 147 0x4000 8008 Write Only 135 5 17 UART RS485 Control register UORS485CTRL 5 7 UART Modem Control Register 135 0x4000 804C ooo 148 5 7 1 Auto flow COntrol o ooo ooo o 136 5 18 UART RS 485 Address Match register 5 7 1 1 A toR DS escri av cata are 136 UORS485ADRMATCH 0x4000 8050 149 5 7 1 2 Auto CTS 0 20 e eee ieres 137 5 19 UART1 RS 485 Delay value register 5 8 UART Line Control Register UOLCR UORS485DLY 0x4000 8054 149 0x4000 800C n n nthe snipe a 138 5 20 RS 485 ElA 485 modes of operation 149 UM10375_0 O NXP B V 2009 All rights rese
255. egisters in order to get accurate voltage readings on the monitored pin For a pin hosting an ADC input it is not possible to have a have a digital function selected and yet get valid ADC readings An inside circuit disconnects ADC hardware from the associated pin whenever a digital function is selected on that pin 4 Clocking and power control UM10375_0 The peripheral clock to the ADC PCLK is provided by the system clock see Figure 3 3 This clock can be disabled through bit 13 in the AHBCLKCTRL register Section 3 5 18 for power savings The ADC can be powered down at run time using the PDRUNCFG register Section 3 5 46 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 240 of 290 NXP Semiconductors U M1 0375 Chapter 16 LPC13xx Analog to Digital Converter ADC Basic clocking for the A D converters is determined by the peripheral ADC clock PCLK A programmable divider is included in each converter to scale this clock to the 4 5 MHz max clock needed by the successive approximation process An accurate conversion requires 11 clock cycles 5 Register description The ADC contains registers organized as shown in Table 16 238 Table 238 Register overview ADC base address 0x4001 C000 Name Access Address Description Reset offset Valuel ADOCR R W 0x000 A D Control Register The ADOCR register must be written to select the 0x0000 0001 operating mode before A D conversion
256. elected peripherals UART SSP ARM trace clock USB WDT and the Systick timer have individual peripheral clocks with their own clock dividers in addition to the system clock The peripheral clocks can be shut down through the respective clock divider registers The power to various analog blocks PLLs oscillators the ADC the USB PHY the BOD circuit and the flash block can be controlled individually through the PDRUNCFG register Sleep mode When Sleep mode is entered the system clock to the ARM Cortex M3 core is stopped The Sleep mode is entered by using the ARM Cortex M3 Wait For Interrupt WF instruction Sleep mode is exited automatically when an interrupt arrives at the processor Peripheral functions if selected to be clocked in the AHBCLKCTRL register continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution Sleep mode eliminates dynamic power used by the processor itself memory systems and related controllers and internal buses The processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static Deep sleep mode Deep sleep mode is entered by using the ARM WFI instruction and setting the SLEEPDEEP bit in the ARM Cortex M3 SCR register see the ARM Cortex M3 user manual In Deep sleep mode see Section 3 9 for details the chip is in Sleep mode the main clock and the system clock are disabled
257. emiconductors UM10375 UM10375_0 Table 51 description Chapter 3 LPC13xx System configuration Power down configuration register PDRUNCFG address 0x4004 8238 bit Bit 10 31 11 Symbol IRCOUT_PD IRC_PD FLASH_ PDI BOD_PD ADC_PD SYSOSC_PDI2l WDTOSC_PD SYSPLL_PD USBPLL_PD MAINREG_PD USBPAD_PD Value Description Reset 0 value IRC oscillator output power down 0 Powered down Powered IRC oscillator power down 0 Powered down Powered Flash power down 0 Powered down Powered BOD power down 0 Powered down Powered ADC power down 1 Powered down Powered System oscillator power down 1 Powered down Powered Watchdog oscillator power down 1 Powered down Powered System PLL power down 1 Powered down Powered USB PLL power down 1 Powered down Powered Main regulator power mode lt tbd gt Main regulator in reduced power mode Main regulator in normal power mode USB pad power down configuration 1 USB PHY powered down suspend mode USB PHY powered Reserved 0 1 The flash power up sequence for waking up from Deep sleep mode takes 100 us Note that the flash does not need to be initialized in this case If the flash is powered down the user must wait for this time period before resuming flash operations The power up sequence after reset takes slightly longer to allow for the flash to initialize 2 The system oscillator must be powered up and selected for the USB PLL to create a
258. ent an ACK after an OUT packet or when the device has seen an ACK after sending an IN packet 1 The EPN bit is set when a NAK is sent and the interrupt on NAK feature is enabled 5 B 1 FULL The buffer 1 status 0 0 Buffer 1 is empty 1 Buffer 1 is full 6 B 2 FULL The buffer 2 status 0 0 Buffer 2 is empty 1 Buffer 2 is full 7 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined Select Endpoint Clear Interrupt Command 0x40 0x47 Data read 1 byte Commands 0x40 to 0x47 are identical to their Select Endpoint equivalents with the following differences They clear the bit corresponding to the endpoint in the USBEpIntSt register e Incase of a control OUT endpoint they clear the STP and PO bits in the corresponding Select Endpoint Register e Reading one byte is obligatory Set Endpoint Status Command 0x40 0x49 Data write 1 byte optional The Set Endpoint Status command sets status bits 7 5 and O of the endpoint The Command Code of Set Endpoint Status is equal to the sum of 0x40 and the physical endpoint number in hex Not all bits can be set for all types of endpoints O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 122 of 290 NXP Semiconductors U M1 0375 UM10375_0 10 13 Chapter 9 LPC13xx USB device controller Table 148 Set Endpoint Status Register bit description Bit Symbol Value De
259. equency should be greater than or equal to 10 MHz For more details on Reset PLL and startup boot code interaction see Section 3 6 Once the crystal frequency is received the part is initialized and the ISP command handler is invoked For safety reasons an Unlock command is required before executing the commands resulting in flash erase write operations and the Go command The rest of the commands can be executed without the unlock command The Unlock command is required to be executed once per ISP session The Unlock command is explained in Section 18 12 ISP commands on page 259 7 ISP IAP communication protocol UM10375_0 7 1 7 2 7 3 7 4 All ISP commands should be sent as single ASCII strings Strings should be terminated with Carriage Return CR and or Line Feed LF control characters Extra lt CR gt and lt LF gt characters are ignored All ISP responses are sent as lt CR gt lt LF gt terminated ASCII strings Data is sent and received in UU encoded format ISP command format Command Parameter_0 Parameter_1 Parameter_n lt CR gt lt LF gt Data Data only for Write commands ISP response format Return_Code lt CR gt lt LF gt Response_0 lt CR gt lt LF gt Response_1 lt CR gt lt LF gt Response_n lt CR gt lt LF gt Data Data only for Read commands ISP data format The data stream is in UU encode format The UU encode algorithm converts 3 bytes of binary data in to 4 bytes of
260. er will return an invalid value Device interrupt registers Table 9 126 shows the bit allocation for the device interrupt registers USBDevintSt USBDevintEn and USBDevintCir O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 108 of 290 NXP Semiconductors UM10375 Chapter 9 LPC13xx USB device controller Table 126 USB Device Interrupt registers bit allocation Bit 31 30 29 28 27 26 25 24 Symbol Bit 23 22 21 20 19 18 17 16 Symbol E s Bit 15 14 13 12 11 10 9 8 Symbol TxENDPKT RxENDPKT CD_FULL CC_EMPTY DEV_STAT Bit 7 6 5 4 3 2 1 0 Symbol gt 7 EP4 EP3 EP2 EP1 EPO FRAME 9 1 1 USB Device Interrupt Status register USBDevintSt 0x4002 0000 The USBDevintSt register holds the status of each interrupt whether it is enabled or not A O indicates no interrupt and 1 indicates the presence of the interrupt USBDevIntSt is a read only register Table 127 USB Device Interrupt Status register USBDevintSt address 0x4002 0000 bit description Bit Symbol Description Reset value 0 FRAME The frame interrupt occurs every 1 ms This is used in 0 isochronous packet transfers 1 EPO USB core interrupt for endpoint 0 2 EP1 USB core interrupt for endpoint 1 3 EP2 USB core interrupt for endpoint 2 4 EP3 USB core interrupt for endpoint 3 5 EP4 USB core interrupt for endpoint 4 8 6 E reserved 9 DEV_STAT Set when USB Bus reset USB suspe
261. errupt 1 Both successful and NAKed OUT transactions generate interrupts 3 INAK_AI Interrupt on NAK for Interrupt or bulk IN endpoint 0 0 Only successful transactions generate an interrupt 1 Both successful and NAKed IN transactions generate interrupts 4 INAK_AO Interrupt on NAK for Interrupt or bulk OUT endpoints 0 0 Only successful transactions generate an interrupt 1 Both successful and NAKed OUT transactions generate interrupts 7 5 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined Read Interrupt Status Command OxF4 Data read 2 bytes Table 143 Read interrupt Status byte 1 register bit description Bit Symbol Description Reset value 0 EPO EPO interrupt 0 1 EP1 EP1 interrupt 0 2 EP2 EP2 interrupt 0 3 EP3 EP3 interrupt 0 4 EP4 EP4 interrupt 0 7 5 reserved E Table 144 Read interrupt Status byte 2 register bit description Bit Symbol Value Description Reset value 1 0 reserved 2 D_ST Device Status change interrupt 0 7 3 reserved The device status change is cleared by issuing the Get device status command All other endpoint interrupts are cleared by issuing select endpoint clear interrupt command Read Current Frame Number Command OxF5 Data read 1 or 2 bytes Returns the frame number of the last successfully received SOF The frame number is eleven bits wide The frame number returns least significant byte first In ca
262. es Yes Yes Yes High No No NA Yes Low No Yes Yes Yes High No No NA Yes Low No Yes No Yes X No No NA No x No Yes Yes No xX No Yes No No xX No Yes No NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 258 of 290 NXP Semiconductors U M1 0375 Chapter 18 LPC13xx Flash memory programming firmware Table 255 ISP commands allowed for different CRP levels ISP command CRP1 CRP2 CRP3 no entry in ISP mode allowed Unlock yes yes n a Set Baud Rate yes yes n a Echo yes yes n a Write to RAM yes above 0x1000 0300 no n a only Read Memory no no n a Prepare sector s for yes yes n a write operation Copy RAM to flash yes not to sector 0 no n a Go no no n a Erase sector s yes sector 0 can only be yes allsectors n a erased when all sectors are only erased Blank check sector s no no n a Read Part ID yes yes n a Read Boot code version yes yes n a Compare no no n a ReadUID yes yes n a In case a CRP mode is enabled and access to the chip is allowed via the ISP an unsupported or restricted ISP command will be terminated with return code CODE_READ_PROTECTION_ENABLED ISP entry protection In addition to the three CRP modes the user can prevent the sampling of pin PIOO_1 for entering ISP mode and thereby release pin PIOO_1 for other uses This is called the NO_ISP mode The NO_ISP mode can be entered by programming the pattern 0x4E69 7370 at location 0x0000 02FC 12 ISP comm
263. es for different system configurations All of the examples calculate an interrupt interval of 10 milliseconds as the System Tick Timer is intended to be used lt tbd gt NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 239 of 290 UM10375 Chapter 16 LPC13xx Analog to Digital Converter ADC Rev 00 10 19 October 2009 User manual 1 How to read this chapter 2 Features The ADC block is identical for all LPC13xx parts e 10 bit successive approximation Analog to Digital Converter ADC e Input multiplexing among 8 pins e Power down mode e Measurement range 0 to 3 V typical Do not exceed the Vpp 3v3 voltage level e 10 bit conversion time gt 2 44 us e Burst conversion mode for single or multiple inputs e Optional conversion on transition on input pin or Timer Match signal e Individual result registers for each A D channel to reduce interrupt overhead 3 Pin description Table 16 237 gives a brief summary of the ADC related pins Table 237 ADC pin description Pin Type Description AD 7 0 Input Analog Inputs The A D converter cell can measure the voltage on any of these input signals Remark While the pins are 5 V tolerant in digital mode the maximum input voltage must not exceed Vpp3v3 3 3 V typical when the pins are configured as analog inputs VDD 3v3 Input Vrer Reference voltage The ADC function must be selected via the IOCON r
264. es gt 269 Reinvoke ISP 200000e o 269 ReaduiD 2 205 cece cies cr eeu neet 270 IAP Status Codes 005 270 Serial Wire Debug SWD flash programming INTO IT Cese iraina A eens gk hee a 270 Flash memory accesS oooo ooo 270 Chapter 19 LPC13xx Serial Wire Debug SWD and trace port 1 How to read this chapter 272 4 Description oo ooocooommcomo oo o 272 2 Features ieee cr 272 5 Pin description oooooooo 272 3 Introduction 0 0 cece eee eee eee 272 6 Debug Notes 200 c cece eee eee 273 Chapter 20 LPC13xx Supplementary information 1 Abbreviati0NS ooooooooomo o 274 3 TableS 1 ccc eee eee eee eres 276 2 Legal informati0n 275 4 PIQUICS sica 281 2 1 DefinitiONS ooooooooooo 275 5 Contents oi ssc ecicaseidss oon kebeeeeia 282 2 2 DisclalMerS o cee ees seh he ee ae 275 2 3 Trademarks unir ran ee dare 275 founded by Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2009 All rights reserved For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 19 October 2009 Document identifier UM10375_0
265. ess their match value is equal to zero Each PWM output will go HIGH when its match value is reached If no match occurs i e the match value is greater than the PWM cycle length the PWM output remains continuously LOW If a match value larger than the PWM cycle length is written to the match register and the PWM signal is HIGH already then the PWM signal will be cleared on the next start of the next PWM cycle Ifa match register contains the same value as the timer reset value the PWM cycle length then the PWM output will be reset to LOW on the next clock tick Therefore the PWM output will always consist of a one clock tick wide positive pulse with a period determined by the PWM cycle length i e the timer reload value If a match register is set to zero then the PWM output will go to HIGH the first time the timer goes back to zero and will stay HIGH continuously Note When the match outputs are selected to serve as PWM outputs the timer reset MRnR and timer stop MRnS bits in the Match Control Register MCR must be set to 0 except for the match register setting the PWM cycle length For this register set the MRnkR bit to 1 to enable the timer reset when the timer value matches the value of the corresponding match register UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 221 of 290 NXP Semiconductors U M1 0375 Chapter 13 LPC13xx 16 bit counter time
266. eturned to zero 31 2 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 7 3 Timer Counter TMR32BOTC address 0x4001 4008 and TMR32B1TC address 0x4001 8008 The 32 bit Timer Counter is incremented when the Prescale Counter reaches its terminal count Unless it is reset before reaching its upper limit the TC will count up through the value OXFFFF FFFF and then wrap back to the value 0x0000 0000 This event does not cause an interrupt but a Match register can be used to detect an overflow if needed 7 4 Prescale Register TMR32BOPR address 0x4001 400C and TMR32B1PR address 0x4001 800C The 32 bit Prescale Register specifies the maximum value for the Prescale Counter 7 5 Prescale Counter Register TMR32B0PC address 0x4001 4010 and TMR32B1PC address 0x4001 8010 The 32 bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter This allows control of the relationship between the resolution of the timer and the maximum time before the timer overflows The Prescale Counter is incremented on every PCLK When it reaches the value stored in the Prescale Register the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK This causes the TC to increment on every PCLK when PR 0 every 2 PCLKs when PR 1 etc 7 6 Match Control Register TMR32BOMCR and TMR32B1MCR The Match Contr
267. fer is implemented as an SRAM based FIFO Data is written to the buffers with the header showing how many bytes are valid in the buffer NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 125 of 290 NXP Semiconductors U M1 0375 UM10375_0 12 2 12 3 12 4 Chapter 9 LPC13xx USB device controller For non isochronous endpoints when a full data packet is received without any errors the endpoint generates a request for data transfer from its FIFO by generating an interrupt to the system Isochronous endpoint will have one packet of data to be transferred in every frame This requires the data transfer has to be synchronized to the USB frame rather than packet arrival The 1 KHz free running clock re synchronized on the incoming SoF tokens will generate an interrupt every millisecond The data transfer follows the little endian format The first byte received from the USB bus will be available in the LS byte of the receive data register Data flow from the Device to the Host For data transfer from an endpoint to the host the host will send an IN token to that endpoint If the FIFO corresponding to the endpoint is empty the device will return a NAK and will generate an interrupt assuming the interrupt on NAK is enabled On this interrupt the processor fills a packet of data in the endpoint FIFO The next IN token that comes after filling this packet will transfer this packet to the host
268. ffer endpoint endpoint byte 0 0 Control Out 64 No 0 1 Control In 64 No 1 2 Interrupt Bulk Out 64 No 1 3 Interrupt Bulk In 64 No 2 4 Interrupt Bulk Out 64 No 2 5 Interrupt Bulk In 64 No 3 6 Interrupt Bulk Out 64 Yes 3 7 Interrupt Bulk In 64 Yes 4 8 Isochronous Out 512 Yes 4 9 Isochronous In 512 Yes 5 General description The architecture of the USB device controller is shown below in Figure 9 12 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 103 of 290 NXP Semiconductors U M1 0375 Chapter 9 LPC13xx USB device controller APB BUS BUS Veus MASTER INTERFACE USB_CONNECT EP_RAM SERIAL E USB_DP ee ACCESS INTERFACE i CONTROL ENGINE D register 2 USB DM o AA i APB slave USB DEVICE BLOCK Fig 12 USB device controller block diagram UM10375_0 5 1 5 2 5 3 5 4 5 5 Analog transceiver The USB Device Controller has a built in analog transceiver ATX The USB ATX sends receives the bi directional USB_DP and USB_DM signals of the USB bus Serial Interface Engine SIE The SIE implements the full USB protocol layer It is completely hardwired for speed and needs no firmware intervention It handles transfer of data between the endpoint buffers in EP_RAM and the USB bus The functions of this block include synchronization pattern recognition parallel serial conversion bit stuffing de stuffing CRC checking generation PID verificat
269. for pin PIO3_0 OxDO IOCON_PIO3_1 R W 0x088 I O configuration for pin PIO3_1 0xDO IOCON_PIO2_3 R W 0x08C O configuration for pin PIO2_3 RI OxDO IOCON_SWDIO_PIO1_3 R W 0x090 I O configuration for pin SWDIO PIO1_3 AD4 OxDO CT32B1_MAT2 IOCON_PIO1_4 R W 0x094 1 O configuration for pin PIO1_4 AD5 CT32B1_MAT3 OxDO IOCON_PIO1_11 R W 0x098 I O configuration for pin PIO1_11 AD7 OxDO IOCON_PIO3_2 R W 0x09C I O configuration for pin PIO3_2 OxDO IOCON_PIO1_5 R W Ox0A0 1 O configuration for pin PIO1_5 RTS CT32B0_CAPO OxDO IOCON_PIO1_6 R W 0x0A4 1 0 configuration for pin PIO1_6 RXD CT32B0_MATO 0xDO IOCON_PIO1_7 R W 0x0A8 1 O configuration for pin PIO1_7 TXD CT32B0_MAT1 OxDO IOCON_PIO3_3 R W Ox0AC I O configuration for pin PIO3_3 OxDO OCON_SCKLOC R W O0x0BO SCK pin location select register 0x00 UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 55 of 290 NXP Semiconductors UM10375 Chapter 5 LPC13xx I O configuration Table 62 1 O configuration registers ordered by port number Port pin Pin name LQFP48 HVQFN33 Reference PIOO_0 IOCON_RESET_PIOO_0 yes yes Table 5 65 PIOO_1 IOCON_PIOO_1 yes yes Table 5 66 PIOO 2 IOCON_PIOO 2 yes yes Table 5 68 PIOO 3 IOCON_PIOO_3 yes yes Table 5 72 PIOO 4 IOCON_PIOO_4 yes yes Table 5 73 PIOO_5 IOCON_PIOO_5 yes yes Table 5 74 PIOO 6 IOCON_PIOO_ 6 yes yes Table 5 80 PIOO_7 IOCON_PIOO_7 yes yes Table 5 81 PIOO 8 IOCON_PIOO_ 8 yes yes Table 5 85 PIOO_9 IOC
270. for writes the USBCmdCode register is written with the CMD_PHASE field set to the value 0x01 Write and the CMD_WDATA field set with the desired write data On completion of the write the CCEMPTY bit of USBDevintSt is set For reads USBCmdCode register is written with the CMD_PHASE field set to the value 0x02 Read and the CMD_CODE field set with command code the read corresponds to On completion of the read the CDFULL bit of USBDevinSt will be set indicating the data is available for reading in the USBCmdData register In the case of multi byte registers the least significant byte is accessed first An overview of the available commands is given in Table 9 139 Here is an example of the Read Current Frame Number command reading 2 bytes USBDevIntClr 0x30 Clear both CCEMPTY amp CDFULL USBCmdCode 0x00F50500 CMD_CODE 0xF5 CMD_PHASE 0x05 Command while USBDevIntSt 0x10 Wait for CCEMPTY USBDevIntClr 0x10 Clear CCEMPTY interrupt bit USBCmdCode 0x00F50200 CMD_CODE 0xF5 CMD_PHASE 0x02 Read while USBDevIntSt amp 0x20 Wait for CDFULL USBDevIntClr 0x20 Clear CDFULL CurFrameNum USBCmdData Read Frame number LSB byte UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 115 of 290 NXP Semiconductors UM10375 USBCmdCode 0x00F50200 while USBDevIntSt 0x20 Temp USBCmdData
271. ftware to reset the SSP and I2C peripherals Writing a 0 to the SSP_RST_N or 12C_RST_N bits resets the SSP or 12C peripheral Writing a 1 de asserts the reset Table 7 Peripheral reset control register PRESETCTRL address 0x4004 8004 bit description Bit Symbol Value Description Reset value 0 SSP_RST_N SSP reset control 0x1 0 SSP reset enabled 1 SSP reset de asserted 1 12C_RST_N 12C reset control 0x1 0 12C reset enabled 1 12C reset de asserted 31 22 Reserved 0x00 System PLL control register This register connects and enables the system PLL and configures the PLL multiplier and divider values The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources The input frequency is multiplied up to a high frequency then divided down to provide the actual clock used by the CPU peripherals and optionally the USB subsystem Note that the USB subsystem has its own dedicated PLL The PLL can produce a clock up to the maximum allowed for the CPU which is 72 MHz The PLL operating mode is set by the DIRECT and BYPASS bits see Table 3 54 Table 8 System PLL control register SYSPLLCTRL address 0x4004 8008 bit description Bit Symbol Value Description Reset value 4 0 MSEL Feedback divider value The division value M is the 0x000 programmed MSEL value 1 00000 Division ratio M 1 11111 Division ration M 32 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October
272. g bit in the Device Interrupt Status USBDevIntSt register Table 9 126 is set USB Device Interrupt Clear register USBDevintCir 0x4002 0008 Writing one to a bit in this register clears the corresponding bit in USBDevlntSt Writing a zero has no effect USBDevintCir is a write only register Table 129 USB Device Interrupt Clear register USBDevintClr address 0x4002 0008 bit description Bit Symbol Value Description Reset value 31 0 See 0 No effect 0 Table 9 126 4 The corresponding bit in USBDevintSt Table 9 127 is cleared USB Device Interrupt Set register USBDevintSet 0x4002 000C Writing one to a bit in this register sets the corresponding bit in the USBDevintSt Writing a zero has no effect USBDevintSet is a write only register Table 130 USB Device Interrupt Set register USBDevintSet address 0x4002 000C bit description Bit Symbol Value Description Reset value 31 0 See 0 No effect 0 Table 9 126 The corresponding bit in USBDevintSt Table 9 127 is set SIE command code registers The SIE command code registers are used for communicating with the Serial Interface Engine See Section 9 10 Serial interface engine command description for more information USB Command Code register USBCmdCode 0x4001 8010 This register is used for sending the command and write data to the SIE The commands written here are propagated to the SIE and executed there After executing the command
273. ghtly less but in certain cases such as a high impedance analog source a slower clock may be desirable 16 BURST 0 Software controlled mode Conversions are software controlled and require 11 clocks 0 1 Hardware scan mode The AD converter does repeated conversions at the rate selected by the CLKS field scanning if necessary through the pins selected by 1s in the SEL field The first conversion after the start corresponds to the least significant bit set to 1 in the SEL field then the next higher bits pins set to 1 are scanned if applicable Repeated conversions can be terminated by clearing this bit but the conversion in progress when this bit is cleared will be completed Important START bits must be 000 when BURST 1 or conversions will not start 19 17 CLKS This field selects the number of clocks used for each conversion in Burst mode andthe 000 number of bits of accuracy of the result in the LS bits of ADDR between 11 clocks 10 bits and 4 clocks 3 bits 000 11 clocks 10 bits 001 10 clocks 9 bits 010 9 clocks 8 bits 011 8 clocks 7 bits 100 7 clocks 6 bits 101 6 clocks 5 bits 110 5clocks 4 bits 111 4 clocks 3 bits 23 20 Reserved user software should not write ones to reserved bits The value read from a NA reserved bit is not defined 26 24 START When the BURST bit is O these bits control whether and when an A D conversion is 0 started 000 No start this value should be used when clearing PDN
274. gister is set to zero then the PWM output will go to HIGH the first time the timer goes back to zero and will stay HIGH continuously Note When the match outputs are selected to function as PWM outputs the timer reset MRnR and timer stop MRnS bits in the Match Control Register MCR must be set to 0 except for the match register setting the PWM cycle length For this register set the MRnkR bit to 1 to enable the timer reset when the timer value matches the value of the corresponding match register UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 233 of 290 NXP Semiconductors U M1 0375 Chapier 14 LPC13xx 32 bit counter timer CT32B l PWM2 MAT2 l l l MR2 100 l l l l I PWM1 MAT1 J f MR1 41 f PWMo MATO i mro 65 1 T 1 1 I 1 I I AE MZ 0 41 65 100 counter is reset Fig 48 Sample PWM waveforms with a PWM cycle length of 100 selected by MR3 and MAT3 0 enabled as PWM outputs by the PWCON register 8 Example timer operation Figure 14 49 shows a timer configured to reset the count and generate an interrupt on match The prescaler is set to 2 and the match register set to 6 At the end of the timer cycle where the match occurs the timer count is reset This gives a full length cycle to the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value Figure 14 50
275. h CPOL 0 CPHA 0 161 6 4 SSPO Status Register SSPOSR 0x4004 000C 7 2 3 SPIformatwithCPOL 0 CPHA 1 162 157 l 7 2 4 SPl format with CPOL 1 CPHA 0 163 6 5 SSPO Clock Prescale Register SSPOCPSR 7 2 5 SPl format with CPOL 1 CPHA 1 165 0x4004 0010 0 0 2 meena 158 7 3 Semiconductor Microwire frame format 165 6 6 SSPO Interrupt Mask Set Clear Register 7 3 1 Setup and hold time requirements on CS with SSPOIMSC 0x4004 0014 158 respect to SK in Microwire mode 167 Chapter 12 LPC13xx I2C bus interface 1 How to read this chapter 168 7 9 12C Mask registers I2MASK O 1 2 3 2 Features 0 cecceceeeceeceaeeatees 168 0x4000 00 30 34 38 3C 177 3 Applications 0 0ceceeeeeaees 168 8 IC operating modes 177 4 General description 168 8 1 Master Transmitter mode 178 41 C Fastemode Plus sccecce 169 8 2 Master Receiver mode 179 5 Pin descripti 169 8 3 Slave Receiver M0Ode o oooo oo oo 179 Gi P OTa regeer auraen 8 4 Slave Transmitter mode 180 6 Clocking and power oo a 9 Functional description 181 7 des description A ett 170 9 1 Input filters and output stages 181 7 1 I C Control Set register I2CONSET 9 2 Address Registers I2ADDR0 to I2ADDR3 183 0x4000 0000 A AANA 171 9 3 Address mask registers I2 MASKO to I2
276. h is not theirs NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 151 of 290 NXP Semiconductors U M1 0375 UM10375_0 Chapter 10 LPC13xx UART RS 485 ElA 485 Normal Multidrop Mode NMM Setting the RS485CTRL bit 0 enables this mode In this mode an address is detected when a received byte causes the UART to set the parity error and generate an interrupt If the receiver is disabled RS485CTRL bit 1 1 any received data bytes will be ignored and will not be stored in the RXFIFO When an address byte is detected parity bit 1 it will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated The processor can then read the address byte and decide whether or not to enable the receiver to accept the following data While the receiver is enabled RS485CTRL bit 1 0 all received bytes will be accepted and stored in the RXFIFO regardless of whether they are data or address When an address character is received a parity error interrupt will be generated and the processor can decide whether or not to disable the receiver RS 485 ElA 485 Auto Address Detection AAD mode When both RS485CTRL register bits 0 9 bit mode enable and 2 AAD mode enable are set the UART is in auto address detect mode In this mode the receiver will compare any address byte received parity 1 to the 8 bit value programmed into the RS485ADRMATCH register If the re
277. h the device respond with an empty packet e Setup stage followed by a Status stage consisting of an IN transaction for which the device respond with empty packet A STALL will not occur in the following situations e Data stage consists of OUTs the status is a single IN transaction for which the device respond with a non empty packet e Setup stage followed by a Status stage consisting of an IN transaction for which the device respond with a non empty packet 13 Double buffered endpoint operation UM10375_0 13 1 The Bulk and Isochronous endpoints of the USB Device Controller are double buffered to increase data throughput For the following discussion the endpoint buffer currently accessible to the CPU for reading or writing is said to be the active buffer Bulk endpoints For Bulk endpoints the active endpoint buffer is switched by the SIE Clear Buffer or Validate Buffer commands The following example illustrates how double buffering works for a Bulk OUT endpoint in Slave mode Assume that both buffer 1 B_1 and buffer 2 B_2 are empty and that the active buffer is B 1 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 127 of 290 NXP Semiconductors U M1 0375 UM10375_0 10 11 Chapter 9 LPC13xx USB device controller The host sends a data packet to the endpoint The device hardware puts the packet into B_1 and generates an endpoint interrupt Softwa
278. h the host via the serial port UART or boots from the USB port PIOO_3 is sampled HIGH If the UART is selected the host should send a 0x3F as a synchronization character and wait for a response The host side serial port settings should be 8 data bits 1 stop bit and no parity The auto baud routine measures the bit time of the received synchronization character in terms of its own frequency and programs the baud rate generator of the serial port It also sends an ASCII string Synchronized lt CR gt lt LF gt to the Host In response to this host should send the same string Synchronized lt CR gt lt LF gt The auto baud routine looks at the received characters to NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 252 of 290 NXP Semiconductors U M1 0375 Chapter 18 LPC13xx Flash memory programming firmware verify synchronization If synchronization is verified then OK lt CR gt lt LF gt string is sent to the host Host should respond by sending the crystal frequency in kHz at which the part is running For example if the part is running at 10 MHz the response from the host should be 10000 lt CR gt lt LF gt OK lt CR gt lt LF gt string is sent to the host after receiving the crystal frequency If synchronization is not verified then the auto baud routine waits again for a synchronization character For auto baud to work correctly in case of user invoked ISP the CCLK fr
279. he prescaler the bit frequency is PCLK CPSDVSR x SCR 1 6 2 SSPO Control Register 1 SSPOCR1 0x4004 0004 This register controls certain aspects of the operation of the SSP controller Table 177 SSPO Control Register 1 SSPOCR1 address 0x4004 0004 bit description Bit Symbol Value 0 LBM 1 SSE UM10375_0 Description Reset Value Loop Back Mode 0 During normal operation Serial input is taken from the serial output MOSI or MISO rather than the serial input pin MISO or MOSI respectively SSP Enable 0 The SSP controller is disabled The SSP controller will interact with other devices on the serial bus Software should write the appropriate control information to the other SSP registers and interrupt controller registers before setting this bit O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 158 of 290 NXP Semiconductors U M1 0375 Chapter 11 LPC13xx SSP Table 177 SSPO Control Register 1 SSPOCR1 address 0x4004 0004 bit description Bit Symbol Value Description Reset Value 2 MS Master Slave Mode This bit can only be written when the 0 SSE bit is 0 0 The SSP controller acts as a master on the bus driving the SCLK MOSI and SSEL lines and receiving the MISO line 1 The SSP controller acts as a slave on the bus driving MISO line and receiving SCLK MOSI and SSEL lines 3 SOD Slave Output Disable This bit is relevant only in slave 0 mode
280. he 16 bit timers are provided by the system clock see Figure 3 3 These clocks can be disabled through bit 7 and 8 in the AHBCLKCTRL register Section 3 5 18 for power savings 7 Register description The 16 bit counter timerO contains the registers shown in Table 13 211 and the 16 bit counter timer1 contains the registers shown in Table 13 212 More detailed descriptions follow Table 211 Register overview 16 bit counter timer 0 CT16B0 base address 0x4000 C000 Name Access Address Description Reset offset valuel TMR16BOIR R W 0x000 Interrupt Register IR The IR can be written to clear interrupts The IR 0 TMR16BOTCR R W TMR16BOTC R W TMR16BOPR R W UM10375_0 0x004 0x008 0x00C can be read to identify which of five possible interrupt sources are pending Timer Control Register TCR The TCR is used to control the Timer 0 Counter functions The Timer Counter can be disabled or reset through the TCR Timer Counter TC The 16 bit TC is incremented every PR 1 cycles of 0 PCLK The TC is controlled through the TCR Prescale Register PR When the Prescale Counter below is equalto 0 this value the next clock increments the TC and clears the PC O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 213 of 290 NXP Semiconductors U M1 0375 Chapter 13 LPC13xx 16 bit counter timer CT16B Table 211 Register overview 16 bit counter timer 0 CT16B0 base add
281. he SCL line is obstructed pulled LOW by a device on the bus no further serial transfer is possible and the problem must be resolved by the device that is pulling the SCL bus line LOW Typically the SDA line may be obstructed by another device on the bus that has become out of synchronization with the current bus master by either missing a clock or by sensing a noise pulse as a clock In this case the problem can be solved by transmitting additional clock pulses on the SCL line see Figure 12 43 The 12C interface does not include a dedicated time out timer to detect an obstructed bus but this can be implemented using another timer in the system When detected software can force clocks up to 9 may be required on SCL until SDA is released by the offending device At that point the slave may still be out of synchronization so a START should be generated to insure that all 12C peripherals are synchronized Bus error A bus error occurs when a START or STOP condition is detected at an illegal position in the format frame Examples of illegal positions are during the serial transfer of an address byte a data bit or an acknowledge bit The 12C hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave When a bus error is detected the 12C block immediately switches to the not addressed slave mode releases the SDA and SCL lines sets the interrupt flag and loads the status register
282. he System Tick Timer is automatically stopped whenever the CPU is stopped Other peripherals are not affected UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 275 of 290 NXP Semiconductors UM10375 Chapter 20 LPC13xx Supplementary information UM10375 Chapter 20 LPC13xx Supplementary information Rev 00 10 19 October 2009 User manual 1 Abbreviations Table 287 Abbreviations Acronym A D AHB AMBA APB BOD DCC DSP EOP ETM GPIO 1 0 MSC PHY PLL SEO SPI SSI SoF TTL UART USB Description Analog to Digital Advanced High performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus BrownOut Detection Debug Communication Channel Digital Signal Processing End Of Packet Embedded Trace Macrocell General Purpose Input Output Input Output Mass Storage Class Physical Layer Phase Locked Loop Single Ended Zero Serial Peripheral Interface Serial Synchronous Interface Start of Frame Transistor Transistor Logic Universal Asynchronous Receiver Transmitter Universal Serial Bus UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 276 of 290 NXP Semiconductors UM10375 2 Legal information Chapter 20 LPC13xx Supplementary information 2 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to
283. he master receiver mode 2 A data byte has been received while the 12C is in the addressed slave receiver mode O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 174 of 290 NXP Semiconductors U M1 0375 7 2 7 3 7 4 7 5 Chapter 12 LPC13xx I2C bus interface 12C Status register IZSTAT 0x4000 0004 Each 12C Status register reflects the condition of the corresponding 12C interface The 12C Status register is Read Only Table 188 12C Status register I2STAT 0x4000 0004 bit description Bit Symbol Description Reset value 2 0 These bits are unused and are always 0 0 7 3 Status These bits give the actual status information about the 12C interface 0x1F The three least significant bits are always 0 Taken as a byte the status register contents represent a status code There are 26 possible status codes When the status code is OxF8 there is no relevant information available and the SI bit is not set All other 25 status codes correspond to defined 12C states When any of these states entered the SI bit will be set For a complete list of status codes refer to tables from Table 12 205 to Table 12 208 I2C Data register 12DAT 0x4000 0008 This register contains the data to be transmitted or the data just received The CPU can read and write to this register only while it is not in the process of shifting a byte when the SI bit is set Data in 12DAT remains stable as l
284. hen initiating a START Initialize Master data counter Set up the Slave Address to which data will be transmitted and add the Read bit Write 0x20 to IZCONSET to set the STA bit Set up the Master Receive buffer Initialize the Master data counter to match the length of the message to be received Exit ona FWD 12C interrupt routine Determine the 12C state and which state routine will be used to handle it 1 Read the 12C status from I2STA 2 Use the status value to branch to one of 26 possible state routines Non mode specific states State 0x00 Bus Error Enter not addressed Slave mode and release bus 1 Write 0x14 to IZCONSET to set the STO and AA bits 2 Write 0x08 to IZCONCLR to clear the SI flag 3 Exit Master States State 08 and State 10 are for both Master Transmit and Master Receive modes The R W bit decides whether the next state is within Master Transmit mode or Master Receive mode State 0x08 A START condition has been transmitted The Slave Address R W bit will be transmitted an ACK bit will be received Write Slave Address with R W bit to I2DAT Write 0x04 to IZCONSET to set the AA bit Write 0x08 to I2CONCLR to clear the SI flag Set up Master Transmit mode data buffer Set up Master Receive mode data buffer Initialize Master data counter Exit N On fF WD NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 205
285. hether or not this output is connected to its pin When a match occurs between the TC and MR this bit can either toggle go LOW go HIGH or do nothing Bits EMR 7 6 control the functionality of this output This bit is driven to the CT32B0_MAT1 CT32B1_MAT1 pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH External Match 2 This bit reflects the state of output CT32Bn_MAT2 whether or not this output is connected to its pin When a match occurs between the TC and MRz2 this bit can either toggle go LOW go HIGH or do nothing Bits EMR 9 8 control the functionality of this output This bit is driven to the CT32B0_MAT2 CT32B1_MAT 2 pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH External Match 3 This bit reflects the state of output CT32Bn_MAT3 whether or not this output is connected to its pin When a match occurs between the TC and MR3 this bit can either toggle go LOW go HIGH or do nothing Bits EMR 11 10 control the functionality of this output This bit is driven to the CT32B0_MAT3 CT32B1_MATS pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH External Match Control 0 Determines the functionality of External Match 0 Table 14 229 shows the encoding of these bits External Match Control 1 Determines the functionality of External Match 1 Table 14 229 shows the encoding of these bits External Match Control 2 Determines the functi
286. ights reserved User manual Rev 00 10 19 October 2009 175 of 290 NXP Semiconductors U M1 0375 7 5 1 Chapter 12 LPC13xx I2C bus interface Table 192 12C SCL Low duty cycle register IZ2SCLL 0x4000 0014 bit description Bit Symbol Description Reset value 15 0 SCLL Count for SCL low time period selection 0x0004 Selecting the appropriate I C data rate and duty cycle Software must set values for the registers I2SCLH and I2SCLL to select the appropriate data rate and duty cycle I2SCLH defines the number of PCLK_I2C cycles for the SCL HIGH time I2SCLL defines the number of PCLK_I2C cycles for the SCL low time The frequency is determined by the following formula PCLK_I2C is the frequency of the system clock Pc __PCLKI2C bufrequency IOSCLH I2SCLL The values for I2SCLL and I2SCLH must ensure that the data rate is in the appropriate 12C data rate range Each register value must be greater than or equal to 4 Table 12 193 gives some examples of 12C bus rates based on PCLK_I2C frequency and I2SCLL and I2SCLH values Table 193 I2SCLL 12SCLH values for selected I2C clock values 12C mode Standard mode Fast mode Fast mode Plus 12C bit PCLK_12C MHz frequency 8 10 12 16 20 30 40 50 60 70 12SCLH I2SCLL 100 kHz 60 80 100 120 160 200 300 400 500 600 700 400 kHz 15 20 25 30 40 50 75 100 125 150 175 1 MHz 8 10 12 16 20 30 40 50 60 70 7 6 I2SCLL and I2SCLH values should not necessarily be
287. in s functionality The GPIOnDIR registers have no effect for peripheral functions Pin mode The MODE bits in the IOCON register allow the selection of on chip pull up or pull down resistors for each pin or select the repeater mode The possible on chip resistor configurations are pull up enabled pull down enabled or no pull up pull down The default value is pull up enabled The repeater mode enables the pull up resistor if the pin is at a logic HIGH and enables the pull down resistor if the pin is at a logic LOW This causes the pin to retain its last known state if it is configured as an input and is not driven externally The state retention is not applicable to the Deep power down mode Repeater mode may typically be used to prevent a pin from floating and potentially using significant power if it floats to an indeterminate state if it is temporarily not driven Hysteresis The input buffer for digital functions can be configured with hysteresis or as plain buffer through the IOCON registers see the LPC 1311 13 43 44 data sheet for details If the external pad supply voltage Vppvio is between 2 5 V and 3 6 V the hysteresis buffer can be enabled or disabled If Vopgo is below 2 5 V the hysteresis buffer must be disabled to use the pin in input mode O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 53 of 290 NXP Semiconductors U M1 0375 3 4 3 5 Chapter 5 LPC13xx I O configu
288. ing a start signal This clock edge falling or rising sets the interrupt for waking up from Deep sleep mode Therefore the start up logic states must be cleared before being used Table 47 Start logic reset register 1 STARTRSRP1CLR address 0x4004 8218 bit description Bit Symbol Value Description Reset value 0 RSRPIO2_8 Start signal reset for start logic input PIO2_8 n a 0 1 Write reset start signal 3 1 RSRPIO2_11 Start signal reset for start logic input PIO2_11 to n a to RSPIO2_9 PIO2_9 0 1 Write reset start signal 4 RSRPIO3_0 Start signal reset for start logic input PIO3_0 n a 0 1 Write reset start signal 7 5 RSRPIO3_3 Start signal reset for start logic input PIO3_3 to PIO3_1 n a ASAPIOS 1 Write reset start signal 31 8 Reserved n a UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 34 of 290 NXP Semiconductors U M1 0375 UM10375_0 5 43 5 44 Chapter 3 LPC13xx System configuration Start logic status register 1 This register reflects the status of the enabled start signals The bit assignment is identical to Table 3 45 Table 48 Start logic signal status register 1 STARTSRP1 address 0x4004 821C bit description Bit Symbol Value Description Reset value 0 SRPIO2_8 Start signal status for start logic input PIO2_8 n a 0 No start signal received 1 Start signal pending 3 11 SRPIO2_11to Start signal status for start logic input PIO2_11 to n a S
289. ion 74 address 0x4004 4024 bit description 59 Table 97 IOCON_SWDIO_PIO1_3 register Table 71 IOCON_PIO2_1 register IOCON_PIO2_1 IOCON_SWDIO_PIO1_3 address 0x4004 4090 address 0x4004 4028 bit description 60 bit description 2 0 00000 75 Table 72 IOCON_PIOO_3 register IOCON_PIO0_3 Table 98 IOCON_PIO1_4 register IOCON_PIO1_4 address 0x4004 402C bit description 60 address 0x4004 4094 bit description 76 Table 73 IOCON_PIOO_4 register IOCON_PIOO_4 Table 99 IOCON_PIO1_11 register IOCON_PIO1_11 address 0x4004 4030 bit description 61 address 0x4004 4098 bit description 77 Table 74 IOCON_PIOO_5 register IOCON_PIOO_5 Table 100 IOCON_PIO3_2 register IOCON_PIO3_2 address 0x4004 4034 bit description 61 address 0x4004 409C bit description 77 Table 75 IOCON_PIO1_9 register IOCON_PIO1_9 Table 101 IOCON_PIO1_5 register IOCON_PIO1_5 address 0x4004 4038 bit description 62 address 0x4004 40A0 bit description 78 Table 76 IOCON_PIO3_4 register IOCON_PIO3_4 Table 102 IOCON_PIO1_6 register IOCON_PIO1_6 address 0x4004 403C bit description 62 address 0x4004 40A4 bit description 78 Table 77 IOCON_PIO2_4 register IOCON_PIO2_4 Table 103 IOCON_PIO1_7 register IOCON_PIO1_7 UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 279 of 290 NXP Semiconductors UM10375 address 0x4004
290. ion Reset value 11 0 DATA R W Input data read or output data write for pins PlOn_O to 0x00 PIOn_11 31 12 Reserved 0x00 GPIO data direction register Table 110 GPIOnDIR register GPIOODIR address 0x5000 8000 to GPIO3DIR address 0x5003 8000 bit description Bit Symbol Access Value Description Reset value 11 0 IO R W Selects pin x as input or output x 0 to 11 0x00 0 Pin PIOn_x is configured as input 1 Pin PIOn_x is configured as output 31 12 Reserved 7 GPIO interrupt sense register Table 111 GPIOnIS register GPIOOIS address 0x5000 8004 to GPIO3IS address 0x5003 8004 bit description Bit Symbol Access Value Description Reset value 11 0 ISENSE R W Selects interrupt on pin x as level or edge sensitive 0x00 x 0 to 11 0 Interrupt on pin PlOn_x is configured as edge sensitive 1 Interrupt on pin PlOn_x is configured as level sensitive 31 12 Reserved NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 86 of 290 NXP Semiconductors U M1 0375 UM10375_0 3 4 3 5 3 6 3 7 Chapter 7 LPC13xx General Purpose I O GPIO GPIO interrupt both edges sense register Table 112 GPIOnIBE register GPIOOIBE address 0x5000 8008 to GPIO3IBE address 0x5003 8008 bit description Bit Symbol Access Value Description Reset value 11 0 IBE R W Selects interrupt on pin x to be triggered on both 0x00 edges x 0 to 11 0 Interr
291. ion generation address recognition and handshake evaluation generation Endpoint RAM EP_RAM Each endpoint buffer is implemented as an SRAM based FIFO The SRAM dedicated for this purpose is called the EP_RAM Each endpoint has a reserved space in the EP_RAM The total EP_RAM space is fixed All endpoints are realized automatically EP_RAM access control The EP_RAM Access Control logic handles transfer of data from to the EP_RAM and the sources that can access it the CPU via the Register Interface and the SIE Register interface The Register Interface allows the CPU to control the operation of the USB Device Controller It also provides a way to write transmit data to the controller and read receive data from the controller NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 104 of 290 NXP Semiconductors U M1 0375 Chapter 9 LPC13xx USB device controller 5 6 SoftConnect The connection to the USB is accomplished by bringing USB_DP for a full speed device HIGH through a 1 5 kOhm pull up resistor The SoftConnect feature can be used to allow software to finish its initialization sequence before deciding to establish connection to the USB Re initialization of the USB bus connection can also be performed without having to unplug the cable To use the SoftConnect feature the USB_CONNECT signal should control an external switch that connects the 1 5 kOhm resistor between USB_DP and 3 3
292. iption 136 Table 161 Modem status interrupt generation 137 Table 162 UART Line Control Register UOLCR address 0x4000 800C bit description Table 163 UART Line Status Register UOLSR address 0x4000 8014 Read Only bit description 139 Table 164 UART Modem Status Register UOMSR address 0x4000 8018 bit description 140 Table 165 UART Scratch Pad Register UOSCR address 0x4000 8014 bit description 141 Table 166 Auto baud Control Register UOACR address 0x4000 8020 bit description 141 Table 167 UART Fractional Divider Register UOFDR address 0x4000 8028 bit description 145 Table 168 Fractional Divider setting look up table 147 Table 169 UART Transmit Enable Register UOTER address 0x4000 8030 bit description 148 Table 170 UART RS485 Control register UORS485CTRL address 0x4000 804C bit description Table 171 UART RS 485 Address Match register UORS485ADRMATCH address 0x4000 8050 bit description oooooooooooo 149 Table 172 UART RS 485 Delay value register UORS485DLY address 0x4000 80454 bit descriptio 0 id bidet 149 Table 173 UART FIFO Level register UOFIFOLVL address 0x4000 8058 Read Only bit description 151 Table 174 SSP pin descriptions 154 Table 175 Register overview SSP base address 0x4004 0000 c oooococo 155 Table 176 SSPO Control Register O SSPOCRO address 0x4004 0000 bit descri
293. is detected an interrupt is requested If the processor wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave operation is not interrupted If bus arbitration is lost in the master mode the 12C block switches to the slave mode immediately and can detect its own slave address in the same serial transfer Master Transmitter mode In this mode data is transmitted from master to slave Before the master transmitter mode can be entered the IZCONSET register must be initialized as shown in Table 12 199 I2EN must be set to 1 to enable the 12C function If the AA bit is O the 12C interface will not acknowledge any address when another device is master of the bus so it can not enter slave mode The STA STO and SI bits must be 0 The SI Bit is cleared by writing 1 to the SIC bit in the IZCONCLR register THe STA bit should be cleared after writing the slave address Table 199 IZCONSET used to configure Master mode Bit 7 6 5 4 3 2 1 0 Symbol 12EN STA STO SI AA Value 1 0 0 0 0 The first byte transmitted contains the slave address of the receiving device 7 bits and the data direction bit In this mode the data direction bit R W should be 0 which means Write The first byte transmitted contains the slave address and Write bit Data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is received START and STOP conditions
294. ister The RS485CTRL bit 4 takes precedence over all other mechanisms controlling the direction control pin with the exception of loopback mode O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 152 of 290 NXP Semiconductors U M1 0375 5 21 Chapter 10 LPC13xx UART RS485 ElA 485 driver delay time The driver delay time is the delay between the last stop bit leaving the TXFIFO and the de assertion of RTS This delay time can be programmed in the 8 bit RS485DLY register The delay time is in periods of the baud clock Any delay time from 0 to 255 bit times may be used RS485 ElA 485 output inversion The polarity of the direction control signal on the RTS or DTR pins can be reversed by programming bit 5 in the UORS485CTRL register When this bit is set the direction control pin will be driven to logic 1 when the transmitter has data waiting to be sent The direction control pin will be driven to logic O after the last bit of data has been transmitted UART FIFO Level register UOFIFOLVL 0x4000 8058 Read Only UOFIFOLVL register is a Read Only register that allows software to read the current FIFO level status Both the transmit and receive FIFO levels are present in this register Table 173 UART FIFO Level register UOFIFOLVL address 0x4000 8058 Read Only bit description Bit Symbol Description Reset value 3 0 RXFIFILVL Reflects the current level of the UART receiver FIFO 0x
295. it address 0x4004 8000 11 GOSCIIPUON somos eee eae eed a eee be 24 Table 6 System memory remap register Table 28 USB clock source select register USBCLKSEL SYSMEMREMAP address 0x4004 8000 bit address 0x4004 80C0 bit description 24 A O eeii 13 Table 29 USB clock source update enable register Table 7 Peripheral reset control register PRESETCTRL USBCLKUEN address 0x4004 80C4 bit address 0x4004 8004 bit description 13 descripti0N ooooooococcoroooo o 25 Table 8 System PLL control register SYSPLLCTRL Table 30 USB clock divider register USBCLKDIV address address 0x4004 8008 bit description 13 0x4004 80C8 bit description 25 Table 9 System PLL status register SYSPLLSTAT Table 31 WDT clock source select register WDTCLKSEL address 0x4004 800C bit description 14 address 0x4004 80D0 bit description 25 Table 10 USB PLL control register USBPLLCTRL address Table 32 WDT clock source update enable register 0x4004 8010 bit description 15 WDTCLKUEN address 0x4004 80D4 bit Table 11 USB PLL status register USBPLLSTAT address G SCrIPUON 4 2 esac eds e a ed ed 26 0x4004 8014 bit description 15 Table 33 WDT clock divider register WDTCLKDIV address Table 12 System oscillator control register SYSOSCCTRL 0x4004 80D8 bit description 26 address 0x4004 8020 bit description 16 Table 34 CLKOUT c
296. k generator is forced to wait until SCL goes HIGH The other device effectively determines the longer LOW period 3 The SCL line is released and the clock generator begins timing the HIGH time Fig 36 Serial clock synchronization A slave may stretch the space duration to slow down the bus master The space duration may also be stretched for handshaking purposes This can be done after each bit or after a complete byte transfer the 12C block will stretch the SCL space duration after a byte has been transmitted or received and the acknowledge bit has been transferred The serial interrupt flag Sl is set and the stretching continues until the serial interrupt flag is cleared Serial clock generator This programmable clock pulse generator provides the SCL clock pulses when the 12C block is in the master transmitter or master receiver mode It is switched off when the 12C block is in a slave mode The 12C output clock frequency and duty cycle is programmable O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 186 of 290 NXP Semiconductors U M1 0375 9 8 9 9 9 10 Chapter 12 LPC13xx I2C bus interface via the 12C Clock Control Registers See the description of the I2CSCLL and 12CSCLH registers for details The output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other SCL clock sources as described above Timing and control The timing an
297. kB 0x0000 0000 0x0000 OFFF 0x0000 1000 0x0000 1FFF 0x0000 2000 0x0000 2FFF 0x0000 3000 0x0000 3FFF 0x0000 4000 0x0000 4FFF 0x0000 5000 0x0000 SFFF 0x0000 6000 0x0000 6FFF 0x0000 7000 0x0000 7FFF N ODO of WYDNY O A A A A HR A RS LPC1311 LPC1313 yes yes yes yes yes yes yes yes yes yes LPC1342 LPC1343 yes yes yes yes yes yes yes yes yes yes yes yes 11 Code Read Protection CRP UM10375_0 Code Read Protection is a mechanism that allows the user to enable different levels of security in the system so that access to the on chip flash and use of the ISP can be restricted When needed CRP is invoked by programming a specific pattern in flash location at 0x0000 02FC IAP commands are not affected by the code read protection Important any CRP change becomes effective only after the device has gone through a power cycle O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 257 of 290 NXP Semiconductors UM10375 UM10375_0 Chapter 18 LPC13xx Flash memory programming firmware Table 253 Code Read Protection options Name Pattern programmed in 0x0000 02FC CRP1 0x12345678 CRP2 0x87654321 CRP3 0x43218765 Description Access to chip via the JTAG pins is disabled This mode allows partial flash update using the following ISP commands and restrictions e Write to RAM command cannot access RAM below 0x1000 0300 e
298. l continue transmitting a 1 bit as long as CTS is de asserted high As soon as CTS gets de asserted transmission resumes and a start bit is sent followed by the data bits of the next character 5 8 UART Line Control Register UOLCR 0x4000 800C The UOLCR determines the format of the data character that is to be transmitted or received Table 162 UART Line Control Register UOLCR address 0x4000 800C bit description Bit Symbol Value Description Reset Value 1 0 Word 00 5 bit character length 0 Length 4 6 bit character length Select 10 7 bit character length 11 8 bit character length 2 Stop Bit 0 1 stop bit 0 Select y 2 stop bits 1 5 if UOLCR 1 0 00 3 Parity 0 Disable parity generation and checking 0 Enable 4 Enable parity generation and checking 5 4 Parity 00 Odd parity Number of 1s in the transmitted character and the 0 Select attached parity bit will be odd 01 Even Parity Number of 1s in the transmitted character and the attached parity bit will be even 10 Forced 1 stick parity 11 Forced 0 stick parity 6 Break 0 Disable break transmission 0 Control 4 Enable break transmission Output pin UART TXD is forced to logic 0 when UOLCRI6 is active high UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 140 of 290 NXP Semiconductors U M1 0375 Chapter 10 LPC13xx UART Table 162 UART Line Control Register UOLCR address 0x4000 800C bit description
299. l Register is used to control whether the Capture Register is loaded with the value in the Timer Counter when the capture event occurs and whether an interrupt is generated by the capture event Setting both the rising and falling bits at the same time is a valid configuration resulting in a capture event for both edges In the description below n represents the Timer number 0 or 1 Table 227 Capture Control Register TMR32BOCCR address 0x4001 4028 and TMR32B1CCR address 0x4001 8028 bit description Bit Symbol Value Description Reset value 0 CAPORE 1 Capture on CT32Bn_CAPO rising edge a sequence of 0 then 1 on CT32Bn_CAPO will 0 cause CRO to be loaded with the contents of TC 0 This feature is disabled 1 CAPOFE 1 Capture on CT32Bn_CAPO falling edge a sequence of 1 then 0 on CT32Bn_CAPO will 0 cause CRO to be loaded with the contents of TC 0 This feature is disabled 2 CAPOI Interrupt on CT32Bn_CAPO event a CRO load due to a CT32Bn_CAPO event will 0 1 generate an interrupt 0 This feature is disabled 31 3 Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined 7 9 Capture Register TMR32B0CR0 address 0x4001 402C and TMR32B1CRO address 0x4001 802C Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin The settings in the Capture Control Register register determine
300. l data input for the shift register TDO Output JTAG Test Data Output This is the serial data output from the shift register Data is shifted out of the device on the negative edge of the TCK signal TRST Input JTAG Test Reset The TRST pin can be used to reset the test logic within the debug logic Table 286 Serial Wire Debug pin description Pin Name Type Description SWCLK Input Serial Wire Clock This pin is the clock for debug logic when in the Serial Wire Debug mode SWDCLK In JTAG mode this is the TCK SWDIO Input Serial wire debug data input output The SWDIO pin is used by an Output external debug tool to communicate with and control the LPC13xx SWO Output Serial Wire Output The SWO pin optionally provides data from the ITM and or the ETM for an external debug tool to evaluate 6 Debug Notes Important The user should be aware of certain limitations during debugging The most important is that due to limitations of the ARM Cortex M3 integration the LPC13xx cannot wake up in the usual manner from Deep sleep mode It is recommended not to use this mode during debug Another issue is that debug mode changes the way in which reduced power modes work internal to the ARM Cortex M3 CPU and this ripples through the entire system These differences mean that power measurements should not be made while debugging the results will be higher than during normal operation in an application During a debugging session t
301. lator can be powered down in the PDRUNCFG register Section 3 5 46 if it is not used The clock to the watchdog register block PCLK can be disabled in the AHBCLKCTRL register Section 3 5 18 for power savings 6 Register description UM10375_0 The Watchdog contains four registers as shown in Table 17 244 below Table 244 Register overview Watchdog timer base address 0x4000 4000 Name Access Address Description Reset offset Valuel WDMOD R W 0x000 Watchdog mode register This register contains the 0 basic mode and status of the Watchdog Timer WDTC R W 0x004 Watchdog timer constant register This register OxFF determines the time out value WDFEED wo 0x008 Watchdog feed sequence register Writing OxAA NA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC WDTV RO 0x00C Watchdog timer value register This register reads OxFF out the current value of the Watchdog timer 1 Reset Value reflects the data stored in used bits only It does not include reserved bits content O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 247 of 290 NXP Semiconductors U M1 0375 Chapter 17 LPC13xx WatchDog timer WDT 6 1 Watchdog Mode register WDMOD 0x4000 0000 The WDMOD register controls the operation of the Watchdog through the combination of WDEN and RESET bits Note that a watchdog feed must be performed before any changes to the WDM
302. lave Address Read has been transmitted NOT ACK has been received A STOP condition will be transmitted 1 Write 0x14 to I2CONSET to set the STO and AA bits 2 Write 0x08 to IZCONCLR to clear the SI flag 3 Exit State 0x50 Data has been received ACK has been returned Data will be read from I2DAT Additional data will be received If this is the last data byte then NOT ACK will be returned otherwise ACK will be returned Read data byte from I2DAT into Master Receive buffer Decrement the Master data counter skip to step 5 if not the last data byte Write 0x0C to IZCONCLR to clear the SI flag and the AA bit Exit Write 0x04 to IZCONSET to set the AA bit Write 0x08 to I2CONCLR to clear the SI flag oak wh NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 207 of 290 NXP Semiconductors U M1 0375 UM10375_0 11 7 4 11 8 11 8 1 11 8 2 11 8 3 Chapter 12 LPC13xx I2C bus interface 7 Increment Master Receive buffer pointer 8 Exit State 0x58 Data has been received NOT ACK has been returned Data will be read from I2DAT A STOP condition will be transmitted 1 Read data byte from I2DAT into Master Receive buffer 2 Write 0x14 to IACONSET to set the STO and AA bits 3 Write 0x08 to IACONCLR to clear the SI flag 4 Exit Slave Receiver states State 0x60 Own Slave Address Write has been received ACK has been returned Data will be receiv
303. le 130 USB Device Interrupt Set register USBDevintSet address 0x4002 000C bit description 108 Table 131 USB Command Code register USBCmdCode address 0x4002 0010 bit description 109 Table 132 USB Command Data register USBCmdData address 0x4002 0014 bit description 109 Table 133 USB Receive Data register USBRxData address 0x4002 0018 bit description 109 Table 134 USB Transmit Data register USBTxData address 0x4002 001C bit description 110 Table 135 USB Receive Packet Length register USBRxPlen address 0x4002 0020 bit description 110 Table 136 USB Transmit Packet Length register USBTxPLen address 0x4002 0024 bit ASSCTMIPIO Neo e eke e me See ad 111 Table 137 USB Control register USBCtrl address 0x4002 0028 bit description 111 Table 138 USB Device FIQ Select register USBDevFIQSel address 0x4002 002C bit description 112 Table 139 SIE command code table 114 Table 140 Device Set Address Register bit description 115 Table 141 Configure Device Register bit description 115 Table 142 Set Mode Register bit description 115 Table 143 Read interrupt Status byte 1 register bit ASSCHIPIION corr daras at 116 Table 144 Read interrupt Status byte 2 register bit GOSCIIPUON 20 5 fc gree gene a es 116 Table 145 Set Device Status Register bit description 117 Table 146 Get Error Code Register bit description 119 Table 1
304. le 16 System PLL clock source select register SYSPLLCLKSEL address 0x4004 8040 bit description Bit Symbol Value Description Reset value 1 0 SEL System PLL clock source 0x00 00 IRC oscillator 01 System oscillator 10 WDT oscillator 11 Reserved 31 22 Reserved 0x00 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 19 of 290 NXP Semiconductors U M1 0375 5 12 5 13 5 14 UM10375_0 Chapter 3 LPC13xx System configuration System PLL clock source update enable register This register updates the clock source of the system PLL with the new input clock after the SYSPLLCLKSEL register has been written to In order for the update to take effect first write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN Table 17 System PLL clock source update enable register SYSPLLUEN address 0x4004 8044 bit description Bit Symbol Value Description Reset value 0 ENA Enable system PLL clock source update 0x0 0 No change 1 Update clock source 31 1 Reserved 0x00 USB PLL clock source select register This register selects the clock source for the dedicated USB PLL The USBPLLCLKUEN register see Section 3 5 14 must be toggled from LOW to HIGH for the update to take effect Remark Always select the system oscillator to produce a stable 48 MHz clock for the USB block Table 18 USB PLL clock source select register USBPLLCLKSEL address 0x4004 8048 bit
305. le 18 277 Read Part ID 54 10 Table 18 278 Read Boot code version 5510 Table 18 279 Compare 5610 Table 18 280 Reinvoke ISP 5710 Table 18 281 Read UID 5810 Table 18 282 COMMAND CODE PARAMETER 1 PARAMETER 2 PARAMETER n command parameter table ARM REGISTER r0 ARM REGISTER r1 STATUS CODE RESULT 1 RESULT 2 RESULT n command result table Fig 55 IAP parameter passing 13 1 Prepare sector s for write operation This command makes flash write erase operation a two step process UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 268 of 290 NXP Semiconductors UM10375 Chapter 18 LPC13xx Flash memory programming firmware Table 274 IAP Prepare sector s for write operation command Command Input Return Code Result Description Prepare sector s for write operation Command code 5019 Paramo0 Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number CMD_SUCCESS BUSY INVALID_SECTOR None This command must be executed before executing Copy RAM to flash or Erase Sector s command Successful execution of the Copy RAM to flash or Erase Sector s command causes relevant sectors to be protected again The boot sector can not be prepared by this command To prepare a single sector use the same Start and End sector numbers 13 2 Copy RAM to flash T
306. ll be recognized General call address will be recognized if 12ADR 0O logic 1 Read data byte or 1 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Read data byte 1 0 0 1 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if 12ADR O logic 1 A START condition will be transmitted when the bus becomes free 0x90 Previously addressed Readdatabyte or X 0 0 0 Data byte will be received and NOT ACK with General Call will be returned DATA byte has been Read data byte X 0 0 1 Databyte will be received and ACK will received ACK has be tetumad been returned UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 197 of 290 NXP Semiconductors UM10375 Table 207 Slave Receiver mode Chapter 12 LPC13xx I2C bus interface Status Status of the I2C bus Application software response Code and hardware To From I2DAT 12CSTAT 0x98 Previously addressed Read data byte or with General Call DATA byte has been received NOT ACK Read data byte or has been returned Read data byte or Read data byte OxA0 A STOP condition or No STDAT action Repeated START or condition has been received while still No STDAT action addressed as or SLV REC or SLV TRX No STDAT action or No STDAT action To I2CON STA STO SI 0 0 0 0 0
307. ll be turned off the oscillator and the phase frequency detector will be stopped and the dividers will enter a reset state While in Power down mode the lock output will be low to indicate that the PLL is not in lock When the Power down mode is terminated by making pd low the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock 10 6 4 Mode 4 Bypass mode 3 Felkout Fclkin 2 x P For M gt 1 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 46 of 290 NXP Semiconductors U M1 0375 Chapter 3 LPC13xx System configuration 4 Fdivo Fclkout M Due to the particular construction of the feedback divider the divo output is not the feedback clock but only a signal that masks the feedback divider s input clock to generate the actual feedback clock As a consequence the divo output signal is 1 when M is set to 1 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 47 of 290 UM10375 Chapter 3 LPC13xx System configuration NXP Semiconductors 10 6 5 Mode 5 Direct bypass mode In this mode the analog part is placed in Power down the post divider is disabled and the input clock is sent directly to the output s This mode can e g be used to perform either a function test and or a scan test on the feedback divider In this mode the frequency of the fee
308. lock source select register Table 13 Watchdog oscillator control register CLKOUTCLKSEL address 0x4004 80E0 bit WDTOSCCTRL address 0x4004 8024 bit GESCHPLION siii ic 26 description 00 00 e eee eee 16 Table 35 CLKOUT clock source update enable register Table 14 Internal resonant crystal control register CLKOUTUEN address 0x4004 80E4 bit IRCCTRL address 0x4004 8028 bit description description 0 0 c eee eee 27 17 Table 36 CLKOUT clock divider registers Table 15 System reset status register SYSRSTSTAT CLKOUTCLKDIV address 0x4004 80E8 bit address 0x4004 8030 bit description 18 description 200 0c eee ee eee 27 Table 16 System PLL clock source select register Table 37 POR captured PIO status registers 0 SYSPLLCLKSEL address 0x4004 8040 bit PIOPORCAPO address 0x4004 8100 bit CESCHPUON ooo en dokee dense ae eee 18 descripto 2 etna Ca oa 27 Table 17 System PLL clock source update enable register Table 38 POR captured PIO status registers 1 SYSPLLUEN address 0x4004 8044 bit PIOPORCAP1 address 0x4004 8104 bit description s 5c0 0 ctu aden etd 19 description weet eee eed eed eee 28 Table 18 USB PLL clock source select register Table 39 BOD control register BODCTRL address 0x4004 USBPLLCLKSEL address 0x4004 8048 bit 8150 bit descripti0N 28 COSCHPUON ess teeta es pa Rae ee 19 Table 40 System tick timer calibration register Table 19 USB PLL clock so
309. mber Port pin Pin name LQFP48 HVQFN33 Reference PIO3 3 IOCON_PIO3_ 3 yes no Table 5 104 PIO3 4 IOCON_PIO3 4 yes on yes on Table 5 76 LPC1311 13 1 LPC1311 13 PIO3_5 IOCON_PIO3_5 yes on yes on Table 5 79 LPc1311 130l LPC1311 1811 1 On LPC134x PIO3_4 and PIO3_5 are not available The corresponding pins are used for the USB D and D functions 1 O configuration registers IOCON_PIOn For details on the I O configuration settings see Section 5 3 Table 63 IOCON_PIO2_6 register IOCON_PIO2_6 address 0x4004 4000 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO2_6 001 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved Table 64 IOCON_PIO2_0 register IOCON_PIO2_0 address 0x4004 4008 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO2_0 001 Select function DTR 010to Reserved 111 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 57 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 64 IOCON_PIO2_0 register IOCON_PIO2_0 address 0x4004 4008 bit descri
310. me pointer in registers rO and r1 The parameter table should be big enough to hold all the results in case if number of results are more than number of parameters Parameter passing is illustrated in the Figure 18 55 The number of parameters and results vary according to the IAP command The maximum number of parameters is 5 passed to the Copy RAM to FLASH command The maximum number of results is 4 returned by the ReadUID command The command handler sends the status code INVALID COMMAND when an undefined command is received The IAP routine resides at Ox1FFF 1FFO location and it is thumb code The IAP function could be called in the following way using C Define the IAP location entry point Since the Oth bit of the IAP location is set there will be a change to Thumb instruction set when the program counter branches to this address define IAP_LOCATION 0x1fff1ff1 Define data structure or pointers to pass IAP command table and result table to the IAP function unsigned long command 5 unsigned long result 4 or unsigned long command unsigned long result command unsigned long Ox result unsigned long Ox Define pointer to function type which takes two parameters and returns void Note the IAP returns the result with the base address of the table residing in R1 typedef void IAP unsigned int unsigned int IAP iap_entry Setting function pointer lap_entry IAP IAP_LOCATION Whenever y
311. mode Own SLA will be recognized General call address will be recognized if 12ADR 0 logic 1 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if I2ADR 0 logic 1 A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode no recognition of own SLA or General call address Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if 12ADR O logic 1 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if I2ADR 0 logic 1 A START condition will be transmitted when the bus becomes free UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 199 of 290 NXP Semiconductors U M1 0375 UM10375_0 10 5 10 6 10 7 Chapter 12 LPC13xx I2C bus interface Miscellaneous states There are two I2STAT codes that do not correspond to a defined 12C hardware state see Table 12 209 These are discussed below I2STAT OxF8 This status code indicates that no relevan
312. n DTR Data Terminal Ready output for UART PIO2_1 General purpose digital input output pin DSR Data Set Ready input for UART PIO2_2 General purpose digital input output pin DCD Data Carrier Detect input for UART PIO2_3 General purpose digital input output pin RI Ring Indicator input for UART PIO2_4 General purpose digital input output pin LPC1343 only PIO2_4 General purpose digital input output pin LPC1313 only PIO2_5 General purpose digital input output pin LPC1343 only LPC1313 only pa ee ene A PIO2_5 General purpose digital input output pin PIO2_6 General purpose digital input output pin PIO2_7 General purpose digital input output pin PIO2_8 General purpose digital input output pin PIO2_9 General purpose digital input output pin PIO2_10 General purpose digital input output pin PIO2_11 General purpose digital input output pin SCK Serial clock for SSP PIO3_0 General purpose digital input output pin PIO3_1 General purpose digital input output pin PIO3_2 General purpose digital input output pin PIO3_3 General purpose digital input output pin PIO3_4 General purpose digital input output pin LPC1313 only PIO3_5 General purpose digital input output pin LPC1313 only USB_DM USB bidirectional D line LPC1343 only USB_DP USB bidirectional D line LPC1343 only 3 3 V input output supply voltage
313. n Reset value 0 CAPPIO0_0 Raw reset status input PIOO_0 User implementation dependent 1 CAPPIO0_1 Raw reset status input PIOO_1 User implementation dependent 11 2 CAPPIOO_11to Raw reset status input PIOO_11to User implementation dependent CAPPIO0_2 PIO0_2 23 12 CAPPIO1_11to Raw reset status input PIO1_11to User implementation dependent CAPPIO1_0 PIO1_0 31 24 CAPPIO2_7to Raw reset status input PIO2_7to User implementation dependent CAPPIO2_0 PIO2_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 28 of 290 NXP Semiconductors UM10375 Chapter 3 LPC13xx System configuration 5 33 POR captured PIO status register 1 The PIOPORCAP1 register captures the state HIGH or LOW of the PIO pins of port 2 PIO2_8 to PIO2_11 and port 3 at power on reset Each bit represents the reset state of one PIO pin This register is a read only status register Table 38 POR captured PIO status registers 1 PIOPORCAP1 address 0x4004 8104 bit description W Oo AN Oa BO DN CO 31 10 Symbol CAPPIO2_8 CAPPIO2_9 CAPPIO2_10 CAPPIO2_11 CAPPIO3_0 CAPPIO3_1 CAPPIO3_2 CAPPIO3_3 CAPPIO3_4 CAPPIO3_5 Description Raw reset status input PIO2_8 Raw reset status input PIO2_9 Raw reset status input PIO2_10 Raw reset status input PIO2_11 Raw reset status input PIO3_0 Raw reset status input PIO3_1 Raw reset status input PIO3_2 Raw reset status input PIO3_3 Raw reset status input PIO3_4 Raw
314. n lost as Master and addressed as Slave by General Call _ 0 DATA PA any number of data bytes and their associated Acknowledge bits Fig 38 Format and states in the Master Receiver mode 88H Y gt GENERAL CALL DATA A PORS gt gt E from Master to Slave from Slave to Master this number contained in I2STA corresponds to a defined state of the IC bus UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 192 of 290 NXP Semiconductors UM10375 Chapter 12 LPC13xx I2C bus interface reception of the own Slave address and one or more Data bytes all are acknowledged last data byte received is Not acknowledged arbitration lost as l Master and addressed gt as Slave 88H gt l reception of the bytes last data byte is Not acknowledged Master and addressed l A as Slave by General l Call from Master to Slave from Slave to Master Ml DATA PA any number of data bytes and their associated Acknowledge bits l this number contained in I2STA corresponds to a defined state of the IC bus Fig 39 Format and states in the Slave Receiver mode General Call address GENERAL CALL DATA 1 A PORS and one or more Data l arbitration lost as sen UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 193 of 290 NX
315. n the status register The interrupt has to be cleared by writing 1 into the interrupt clear register 9 Register description UM10375_0 9 1 Table 9 125 shows the USB Device Controller registers directly accessible by the CPU The Serial Interface Engine SIE has other registers that are indirectly accessible via the SIE command registers See Section 9 10 Serial interface engine command description for more information Table 125 Register overview USB device base address 0x4002 0000 Name Access Address Description Reset valuel offset Device interrupt registers USBDevintSt RO 0x00 USB Device Interrupt Status 0x0000 0010 USBDevintEn R W 0x04 USB Device Interrupt Enable 0x0000 0000 USBDevintCir woll 0x08 USB Device Interrupt Clear 0x0000 0000 USBDevlntSet woll 0x0C USB Device Interrupt Set 0x0000 0000 SIE command registers USBCmdCode woll 0x10 USB Command Code 0x0000 0000 USBCmdData RO 0x14 USB Command Data 0x0000 0000 USB data transfer registers USBRxData RO 0x18 USB Receive Data 0x0000 0000 USBTxData woll 0x1C USB Transmit Data 0x0000 0000 USBRxPLen RO 0x20 USB Receive Packet Length 0x0000 0000 USBTxPLen Wok 0x24 USB Transmit Packet Length 0x0000 0000 USBCtrl R W 0x28 USB Control 0x0000 0000 Miscellaneous registers USBDevFlQSel woll 0x2C USB Device FIQ select 0x00 1 Reset value reflects the data stored in used bits only It does not include reserved bits content 2 Reading WO regist
316. n two 2C bus pins in Fast mode Plus O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 3 of 290 NXP Semiconductors U M1 0375 Chapter 1 LPC13xx Introductory information Four general purpose timers counters with a total of four capture inputs and 13 compare outputs Watchdog Timer WDT System tick timer Serial Wire Debug and Serial Wire Trace Port Integrated PMU Power Management Unit automatically adjusts internal regulators to minimize power consumption during Sleep Deep sleep and Deep power down modes Three reduced power modes Sleep Deep sleep and Deep power down Single 3 3 V power supply 2 0 V to 3 6 V 10 bit ADC with input multiplexing among 8 pins GPIO pins can be used as edge and level sensitive interrupt sources Clock output function with divider that can reflect the main oscillator clock IRC clock CPU clock or the Watchdog clock Processor wake up from Deep sleep mode via a dedicated start logic using up to 40 pins Brownout detect with four separate thresholds for interrupt and one threshold for forced reset Power On Reset POR Crystal oscillator with an operating range of 1 MHz to 25 MHz 12 MHz internal RC oscillator trimmed to 1 accuracy that can optionally be used as a system clock PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal May be run from the main oscillator the internal R
317. nIC register GPIOOIC address 0x5000 801C to GPIO3IC address 0x5003 801C bit description Bit Access Symbol Value Description Reset value 11 0 W CLR Selects interrupt on pin x to be cleared x 0 to 0x00 11 Clears the interrupt edge detection logic This register is write only Remark The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine 0 No effect 1 Clears edge detection logic for pin PIOn_x 31 12 Reserved UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 88 of 290 NXP Semiconductors UM10375 4 Functional description Chapter 7 LPC13xx General Purpose I O GPIO 4 1 Write read data operations In order for software to be able to set GPIO bits without affecting any other pins in a single write operation bits 13 2 of a 14 bit wide address bus are used to create a 12 bit wide mask for write and read operations on the 12 GPIO pins for each port The masked GPIODATA register can be located anywhere between address offsets 0x0000 to Ox3FFC in the GPIOn address space depending on the address chosen Write operation If the address bit associated with the GPIO data bit to be written is HIGH the value of the GPIODATA register bit is updated from the GPIO data bit If the address bit is LOW the
318. nd change or Connect 0 change event occurs Refer to Section 9 10 7 Set Device Status Command OxFE Data write 1 byte on page 119 10 CC_EMPTY The command code register USBCmdCode is empty New 1 command can be written 11 CD_FULL Command data register USBCmdData is full Data can be read 0 now 12 RxENDPKT The current packet in the endpoint buffer is transferred to the 0 CPU 13 TxENDPKT The number of data bytes transferred to the endpoint buffer 0 equals the number of bytes programmed in the TxPacket length register USBTxPLen 31 14 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 9 1 2 USB Device Interrupt Enable register USBDevintEn 0x4002 0004 Writing a one to a bit in this register enables the corresponding bit in USBDevintSt to generate an external interrupt when set If it s not set no external interrupt is generated but the interrupt will still be held in the Device Interrupt Status register UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 109 of 290 NXP Semiconductors U M1 0375 UM10375_0 9 2 9 2 1 Chapter 9 LPC13xx USB device controller Table 128 USB Device Interrupt Enable register USBDevintEn address 0x4002 0004 bit description Bit Symbol Value Description Reset value 31 0 See 0 No interrupt is generated 0 Table 9 126 4 An interrupt will be generated when the correspondin
319. nd even if the device is not configured in the default state Table 141 Configure Device Register bit description Bit Symbol Description Reset value 0 CONF_DEVICE Device is configured All enabled non control endpoints will respond This bit is cleared by hardware when a bus reset occurs When set the UP_LED signal is driven LOW if the device is not in the suspended state SUS 0 7 1 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined Set Mode Command 0xF3 Data write 1 byte Table 142 Set Mode Register bit description Bit Symbol Value Description Reset value O AP_CLK Always PLL Clock 0 0 USB_NEED_CLK is functional the 48 MHz clock can be stopped when the device enters suspend state 1 USB_NEED_CLK is fixed to 1 the 48 MHz clock cannot be stopped when the device enters suspend state 1 INAK_CI Interrupt on NAK for Control IN endpoint 0 0 Only successful transactions generate an interrupt 1 Both successful and NAKed IN transactions generate interrupts O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 117 of 290 NXP Semiconductors U M1 0375 UM10375_0 10 4 10 5 Chapter 9 LPC13xx USB device controller Table 142 Set Mode Register bit description Bit Symbol Value Description Reset value 2 INAK_CO Interrupt on NAK for Control OUT endpoint 0 0 Only successful transactions generate an int
320. nfiguration during idle periods e The CLK signal is forced LOW e SSEL is forced HIGH e The transmit MOSI MISO pad is in high impedance If the SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW Master s MOSI pin is enabled After a further one half SCK period both master and slave valid data is enabled onto their respective transmission lines At the same time the SCK is enabled with a rising edge transition Data is then captured on the falling edges and propagated on the rising edges of the SCK signal In the case of a single word transfer after all bits have been transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured For continuous back to back transfers the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer SPI format with CPOL 1 CPHA 0 Single and continuous transmission signal sequences for SPI format with CPOL 1 CPHA 0 are shown in Figure 11 23 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 165 of 290 NXP Semiconductors U M1 0375 Chapter 11 LPC13xx SSP SCK SSEL MOSI MISO cm fio 16 bits gt a Single transfer with CPOL 1 and CPHA 0 SCK SSEL MOSI MISO cm 4to 16 bits g
321. ng MST No I2DAT action 0 1 0 X Only the internal hardware is affected in or selected slave the MST or addressed SLV modes In all modes due to an cases the bus is released and the 12C illegal START or block is switched to the not addressed STOP condition State SLV mode STO is reset 0x00 can also occur when interference causes the 12C block to enter an undefined state 10 8 Some special cases The 12C hardware has facilities to handle the following special cases that may occur during a serial transfer 10 9 Simultaneous Repeated START conditions from two masters A Repeated START condition may be generated in the master transmitter or master receiver modes A special case occurs if another master simultaneously generates a Repeated START condition see Figure 12 41 Until this occurs arbitration is not lost by either master since they were both transmitting the same data If the 12C hardware detects a Repeated START condition on the 12C bus before generating a Repeated START condition itself it will release the bus and no interrupt request is generated If another master frees the bus by generating a STOP condition the 12C block will transmit a normal START condition state 0x08 and a retry of the total serial data transfer can commence 10 10 Data transfer after loss of arbitration Arbitration may be lost in the master transmitter and master receiver modes see Figure 12 35 Loss of arbitration is indicated by the following states in I2STAT
322. no STOP condition is transmitted to the bus The hardware behaves as if a STOP condition has been received and it switches to not addressed slave receiver mode The STO flag is cleared by hardware automatically SI is the 12C Interrupt Flag This bit is set when the I2C state changes However entering state F8 does not set SI since there is nothing for an interrupt service routine to do in that case While Sl is set the low period of the serial clock on the SCL line is stretched and the serial transfer is suspended When SCL is HIGH it is unaffected by the state of the SI flag SI must be reset by software by writing a 1 to the SIC bit in I2CONCLR register AA is the Assert Acknowledge Flag When set to 1 an acknowledge low level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 The address in the Slave Address Register has been received 2 The General Call address has been received while the General Call bit GC in IZADR is set 3 A data byte has been received while the 12C is in the master receiver mode 4 A data byte has been received while the 12C is in the addressed slave receiver mode The AA bit can be cleared by writing 1 to the AAC bit in the IACONCLR register When AA is O a not acknowledge HIGH level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 A data byte has been received while the 12C is in t
323. o In order for the update to take effect at the input of the watchdog timer first write a zero to the WDTCLKUEN register and then write a one to WDTCLKUEN Table 32 WDT clock source update enable register WDTCLKUEN address 0x4004 80D4 bit description Bit Symbol Value Description Reset value 0 ENA Enable WDT clock source update 0x0 0 No change 1 Update clock source 31 1 Reserved 0x00 WDT clock divider register This register determines the divider values for the watchdog clock wadt_clk Table 33 WDT clock divider register WDTCLKDIV address 0x4004 80D8 bit description Bit Symbol Value Description Reset value 7 0 DIV WDT clock divider values 0x00 0 Gate 1 Divide by 1 to sb 255 Divide by 255 31 8 Reserved 0x00 CLKOUT clock source select register This register configures the clkout_clk signal to be output on the CLKOUT pin All three oscillators and the main clock can be selected for the clkout_clk clock The CLKOUTCLKUEN register see Section 3 5 30 must be toggled from LOW to HIGH for the update to take effect Table 34 CLKOUT clock source select register CLKOUTCLKSEL address 0x4004 80E0 bit description Bit Symbol Value Description Reset value 1 0 SEL CLKOUT clock source 0x00 00 IRC oscillator 01 System oscillator 10 Watchdog oscillator 11 Main clock 31 22 Reserved 0x00 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 27 of 29
324. o CTS mode a change of the CTS signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set Delta CTS bit in the UOMSR will be set though Table 10 161 lists the conditions for generating a Modem Status interrupt Table 161 Modem status interrupt generation Enable CTSen CTS Delta CTS Delta DCD or trailing edge Modem modem UOMCR 7 interrupt UOMSR 0 RI or status status enable Delta DSR UOMSR 3 or interrupt interrupt UOIER 7 UOMSR 2 or UOMSR 1 VOER 3 0 x x x x No 1 0 x 0 0 No 1 0 Xx 1 x Yes 1 0 x x 1 Yes 1 1 0 Xx 0 No 1 1 0 Xx 1 Yes 1 1 1 0 0 No 1 1 1 1 x Yes 1 1 1 x 1 Yes O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 139 of 290 NXP Semiconductors U M1 0375 Chapter 10 LPC13xx UART The auto CTS function reduces interrupts to the host system When flow control is enabled a CTS state change does not trigger host interrupts because the device automatically controls its own transmitter Without Auto CTS the transmitter sends any data present in the transmit FIFO and a receiver overrun error can result Figure 10 16 illustrates the Auto CTS functional timing UART TX bitsO 7 bitsO 7 bitsO 7 CTS pin Fig 16 Auto CTS Functional Timing While starting transmission of the initial character the CTS signal is asserted Transmission will stall as soon as the pending transmission has completed The UART wil
325. o be entered if arbitration is lost while the 12C block is in the master mode see state 0xBO If the AA bit is reset during a transfer the 12C block will transmit the last byte of the transfer and enter state 0xC0 or OxC8 The 12C block is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer Thus the master receiver receives all 1s as serial data While AA is reset the 12C block does not respond to its own slave address or a General Call address However the I C bus is still monitored and address recognition may be resumed at any time by setting AA This means that the AA bit may be used to temporarily isolate the 12C block from the 12C bus NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 194 of 290 NXP Semiconductors UM10375 Table 205 Master Transmitter mode Chapter 12 LPC13xx I2C bus interface Status Code 12STAT 0x08 0x10 0x18 0x20 0x28 0x30 0x38 Status of the I2C bus Application software response and hardware A START condition has been transmitted A Repeated START condition has been transmitted SLA W has been transmitted ACK has been received SLA W has been transmitted NOT ACK has been received Data byte in l2DAT has been transmitted ACK has been received Data byte in l2DAT has been transmitted NOT ACK has been received Arbitration lost in SLA
326. o pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 z Reserved 1 31 7 Reserved UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 66 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 81 IOCON_PIOO_7 register IOCON_PIOO_7 address 0x4004 4050 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIOO_7 001 Select function CTS 010to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved Table 82 IOCON_PIO2_9 register IOCON_PIO2_9 address 0x4004 4054 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO2_9 001 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved UM10375_0 O NXP B V 2009 All rights reserved User m
327. ode In the master receiver mode data is received from a slave transmitter The transfer is initiated in the same way as in the master transmitter mode When the START condition has been transmitted the interrupt service routine must load the slave address and the data direction bit to the 12C Data register I2DAT and then clear the SI bit In this case the data direction bit R W should be 1 to indicate a read When the slave address and data direction bit have been transmitted and an acknowledge bit has been received the SI bit is set and the Status Register will show the status code For master mode the possible status codes are 0x40 0x48 or 0x38 For slave mode the possible status codes are 0x68 0x78 or OxBO For details refer to Table 12 206 0 write 1 read data transferred n Bytes Acknowledge A Acknowledge SDA low A Not acknowledge SDA high S START condition P STOP condition O from Master to Slave O from Slave to Master Fig 30 Format of Master Receiver mode After a Repeated START condition 12 may switch to the master transmitter mode O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 181 of 290 NXP Semiconductors U M1 0375 Chapter 12 LPC13xx I2C bus interface data transferred n Bytes Acknowledge A Acknowledge SDA low A Not acknowledge SDA high S START condition P STOP condition
328. of 290 NXP Semiconductors U M1 0375 UM10375_0 Chapter 12 LPC13xx I2C bus interface 11 5 4 State 0x10 11 6 11 6 1 11 6 2 11 6 3 A Repeated START condition has been transmitted The Slave Address R W bit will be transmitted an ACK bit will be received Write Slave Address with R W bit to I2DAT Write 0x04 to IZCONSET to set the AA bit Write 0x08 to I2CONCLR to clear the SI flag Set up Master Transmit mode data buffer Set up Master Receive mode data buffer Initialize Master data counter Exit NO oO fF OD Master Transmitter states State 0x18 Previous state was State 8 or State 10 Slave Address Write has been transmitted ACK has been received The first data byte will be transmitted an ACK bit will be received Load I2DAT with first data byte from Master Transmit buffer Write 0x04 to 1I2CONSET to set the AA bit Write 0x08 to I2CONCLR to clear the SI flag Increment Master Transmit buffer pointer Exit ar O N gt State 0x20 Slave Address Write has been transmitted NOT ACK has been received A STOP condition will be transmitted 1 Write 0x14 to I2CONSET to set the STO and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit State 0x28 Data has been transmitted ACK has been received If the transmitted data was the last data byte then transmit a STOP condition otherwise transmit the next data byte Decrement the Master data counter
329. og Constant register WDTC address 0x4000 4004 bit description Bit Symbol Description Reset Value 31 0 Count Watchdog time out interval 0x0000 OOFF Watchdog Feed register WDFEED 0x4000 4008 Writing OxAA followed by 0x55 to this register will reload the Watchdog timer with the WDTC value This operation will also start the Watchdog if it is enabled via the WOMOD register Setting the WDEN bit in the WDMOD register is not sufficient to enable the Watchdog A valid feed sequence must be completed after setting WDEN before the Watchdog is capable of generating a reset Until then the Watchdog will ignore feed errors After writing OxAA to WDFEED access to any Watchdog register other than writing 0x55 to WDFEED causes an immediate reset interrupt when the Watchdog is enabled The reset will be generated during the second PCLK following an incorrect access to a Watchdog register during a feed sequence Interrupts should be disabled during the feed sequence An abort condition will occur if an interrupt happens during the feed sequence Table 248 Watchdog Feed register WDFEED address 0x4000 4008 bit description Bit Symbol Description Reset Value 7 0 Feed Feed value should be OxAA followed by 0x55 NA 31 8 reserved Watchdog Timer Value register WDTV 0x4000 400C The WDTV register is used to read the current value of Watchdog timer When reading the value of the 32 bit timer the lock and synchronization procedure
330. og should be fed again before the Watchdog counter underflows to prevent reset interrupt When the Watchdog is in the reset mode and the counter underflows the CPU will be reset loading the stack pointer and program counter from the vector table as in the case of external reset The Watchdog time out flag WDTOF can be examined to determine if the Watchdog has caused the reset condition The WDTOF flag must be cleared by software 5 Clocking and power control The watchdog timer block uses two clocks PCLK and WDCLK PCLK is used for the APB accesses to the watchdog registers and is derived from the system clock see Figure 3 3 The WDCLK is used for the watchdog timer counting and is derived from the wdt_clk in Figure 3 3 Several clocks can be used as a clock source for wdt_clk clock the IRC the watchdog oscillator and the main clock The clock source is selected in the syscon block see Section 3 5 26 The WDCLK has its own clock divider Section 3 5 26 which can also disable this clock There is some synchronization logic between these two clock domains When the WDMOD and WDTC registers are updated by APB operations the new value will take effect in 3 WDCLK cycles on the logic in the WDCLK clock domain When the watchdog timer is counting on WDCLK the synchronization logic will first lock the value of the counter on WDCLK and then synchronize it with the PCLK for reading as the WDTV register by the CPU The watchdog oscil
331. ol Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter The function of each of the bits is shown in Table 14 226 Table 226 Match Control Register TMR32B0MCR address 0x4001 4014 and TMR32B1MCR address 0x4001 8014 bit description Bit Symbol Value Description Reset value 0 MROI 1 Interrupt on MRO an interrupt is generated when MRO matches the value in the TC 0 0 This interrupt is disabled UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 228 of 290 NXP Semiconductors UM10375 Chapter 14 LPC13xx 32 bit counter timer CT32B Table 226 Match Control Register TMR32BOMCR address 0x4001 4014 and TMR32B1MCR address 0x4001 8014 bit description Bit Symbol 1 MROR 2 MROS 3 MR1I 4 MR1R 5 MR1S 6 MR2I 7 MR2R 8 MR2S 9 MR3I 10 MR3R 11 MR3S 31 12 Value Description 4 O O O O O O O O 2 O 0 Reset on MRO the TC will be reset if MRO matches it Feature disabled Stop on MRO the TC and PC will be stopped and TCR O will be set to 0 if MRO matches the TC Feature disabled Interrupt on MR1 an interrupt is generated when MR1 matches the value in the TC This interrupt is disabled Reset on MR1 the TC will be reset if MR1 matches it Feature disabled Stop on MR1 the TC and PC will be stopped and TCR O will be set to 0 if MR1 matches the TC Feature disabled
332. on hardware may be designed into the module to block some all loss of arbitration states from occurring if those state would either prevent a desired interrupt from occurring or cause an unwanted interrupt to occur Whether any such hardware will be added is still to be determined 12C Slave Address registers IZADR 1 2 3 0x4000 00 20 24 28 These registers are readable and writable and are only used when an 12C interface is set to slave mode In master mode this register has no effect The LSB of I2ADR is the General Call bit When this bit is set the General Call address 0x00 is recognized O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 178 of 290 NXP Semiconductors U M1 0375 UM10375_0 7 9 7 10 Chapter 12 LPC13xx I2C bus interface Any of these registers which contain the bit 00x will be disabled and will not match any address on the bus All four registers will be cleared to this disabled state on reset Table 196 I C Slave Address registers IZADR 1 2 3 0x4000 00 20 24 28 bit description Bit Symbol Description Reset value 0 GC General Call enable bit 0 7 1 Address The I2C device address for slave mode 0x00 12C Data buffer register I2CDATA_BUFFER 0x4000 002C In monitor mode the 12C module may lose the ability to stretch the clock stall the bus if the ENA_SCL bit is not set This means that the processor will have a limited amount of time to rea
333. onality of External Match 2 Table 14 229 shows the encoding of these bits External Match Control 3 Determines the functionality of External Match 3 Table 14 229 shows the encoding of these bits Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Reset value 0 00 00 00 00 Table 229 External match control EMR 11 10 EMR 9 8 Function EMR 7 6 or EMR 5 4 00 01 10 11 Do Nothing Clear the corresponding External Match bit output to 0 CT32Bn_MATm pin is LOW if pinned out Set the corresponding External Match bit output to 1 CT32Bn_MATm pin is HIGH if pinned out Toggle the corresponding External Match bit output UM10375_0 7 11 Count Control Register TMR32BOCTCR and TMR32B1TCR The Count Control Register CTCR is used to select between Timer and Counter mode and in Counter mode to select the pin and edge s for counting NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 231 of 290 NXP Semiconductors U M1 0375 UM10375_0 7 12 Chapter 14 LPC13xx 32 bit counter timer CT32B When Counter Mode is chosen as a mode of operation the CAP input selected by the CTCR bits 3 2 is sampled on every rising edge of the PCLK clock After comparing two consecutive samples of this CAP input one of the following four events is recognized rising edge falling edge either
334. ong as the SI bit is set Data in I2DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of I2DAT Table 189 12C Data register 12DAT 0x4000 0008 bit description Bit Symbol Description Reset value 7 0 Data This register holds data values that have been received or are to 0 be transmitted 12C Slave Address register IZADRO 0x4000 000C These registers are readable and writable and are only used when an 12C interface is set to slave mode In master mode this register has no effect The LSB of I2ADR is the General Call bit When this bit is set the General Call address 0x00 is recognized Any of these registers which contain the bit 00x will be disabled and will not match any address on the bus All four registers will be cleared to this disabled state on reset Table 190 I2C Slave Address registers IZADRO 0x4000 000C bit description Bit Symbol Description Reset value 0 GC General Call enable bit 0 7 1 Address The 2C device address for slave mode 0x00 12C SCL HIGH duty cycle register and LOW duty cycle register 12SCLH 0x4000 0010 and I2SCLL 0x4000 0014 Table 191 12C SCL HIGH duty cycle register 12SCLH address 0x4000 0010 bit description Bit Symbol Description Reset value 15 0 SCLH Count for SCL HIGH time period selection 0x0004 UM10375_0 O NXP B V 2009 All r
335. only register reflects the current status of the SSP controller Table 179 SSPO Status Register SSPOSR address 0x4004 000C bit description Bit Symbol Description Reset Value 0 TFE Transmit FIFO Empty This bit is 1 is the Transmit FIFO is 1 empty 0 if not 1 TNF Transmit FIFO Not Full This bit is 0 if the Tx FIFO is full 1 if not 1 2 RNE Receive FIFO Not Empty This bit is 0 if the Receive FIFO is 0 empty 1 if not UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 159 of 290 NXP Semiconductors U M1 0375 UM10375_0 6 5 6 6 Chapter 11 LPC13xx SSP Table 179 SSPO Status Register SSPOSR address 0x4004 000C bit description Bit Symbol Description Reset Value 3 RFF Receive FIFO Full This bit is 1 if the Receive FIFO is full 0 if 0 not 4 BSY Busy This bit is 0 if the SSPO controller is idle or 1 if it is 0 currently sending receiving a frame and or the Tx FIFO is not empty 7 5 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined SSPO Clock Prescale Register SSPOCPSR 0x4004 0010 This register controls the factor by which the Prescaler divides the SSP peripheral clock SSP_PCLK to yield the prescaler clock that is in turn divided by the SCR factor in SSPOCRO to determine the bit clock Table 180 SSPO Clock Prescale Register SSPOCPSR address 0x4004 0010 bit description Bit Sym
336. or control 0x00 Table 3 12 WDTOSCCTRL R W 0x024 Watchdog oscillator control 0x00 Table 3 13 IRCCTRL R W 0x028 IRC control 0x80 Table 3 14 0x02C Reserved SYSRESSTAT R 0x030 System reset status register 0x00 Table 3 15 0x034 0x03C Reserved SYSPLLCLKSEL R W 0x040 System PLL clock source select 0x00 Table 3 16 SYSPLLCLKUEN R W 0x044 System PLL clock source update enable 0x00 Table 3 17 USBPLLCLKSEL R W 0x048 USB PLL clock source select 0x00 Table 3 18 USBPLLCLKUEN R W 0x04C USB PLL clock source update enable 0x00 Table 3 19 0x050 0x06C Reserved MAINCLKSEL R W 0x070 Main clock source select 0x00 Table 3 20 MAINCLKUEN R W 0x074 Main clock source update enable 0x00 Table 3 21 SYSAHBCLKDIV R W 0x078 System AHB clock divider 0x01 Table 3 22 0x07C Reserved SYSAHBCLKCTRL R W 0x080 System AHB clock control Ox1F Table 3 23 0x084 0x090 Reserved z SSPCLKDIV R W 0x094 SSP clock divder 0x00 Table 3 24 UARTCLKDIV R W 0x098 UART clock divder 0x00 Table 3 25 0x09C 0x0A8 Reserved a TRACECLKDIV R W 0x0AC ARM trace clock divider 0x00 Table 3 26 SYSTICKCLKDIV R W 0x0BO SYSTICK clock divder 0x00 Table 3 27 0x0B4 0xOBC Reserved USBCLKSEL R W 0x0C0 USB clock source select 0x00 Table 3 28 USBCLKUEN R W 0x0C4 USB clock source update enable 0x00 Table 3 29 USBCLKDIV R W 0x0C8 USB clock source divider 0x00 Table 3 30 0x0CC Reserved WDTCLKSEL R W Ox0DO WDT clock source select 0x00 Table 3 31 WDTCLKUEN R W 0x0D4
337. orts speculative branching The peripheral complement of the LPC13xx series includes up to 32 kB of flash memory up to 8 kB of data memory USB Device one Fast mode Plus FM 12C interface one UART four general purpose timers and up to 42 general purpose l O pins 2 Howto read this manual 3 Features This user manual describes parts LPC1311 LPC1313 LPC1342 LPC1343 Part specific features and registers are listed at the beginning of each chapter UM10375_0 e ARM Cortex M3 processor running at frequencies of up to 72 MHz ARM Cortex M3 built in Nested Vectored Interrupt Controller NVIC e Up to 32 kB on chip flash programming memory e In System Programming ISP and In Application Programming IAP via on chip bootloader software e Up to 8 kB of on chip static SRAM e Serial interfaces USB 2 0 full speed device controller with on chip PHY for device LPC1342 43 only UART with fractional baud rate generation internal FIFO and RS 485 ElA 485 support and modem control SSP controller with FIFO and multi protocol capabilities 12C bus interface supporting the full 12C bus specification and Fast mode Plus with a data rate of 1 Mbit s with multiple address recognition and monitor mode e Other peripherals Upto 42 General Purpose I O GPIO pins with configurable pull up pull down resistors High current output driver 20 mA on one pin High current sink drivers 20 mA o
338. ot defined System Timer Current value register STCURR 0xE000 E018 The STCURR register returns the current count from the System Tick counter when it is read by software Table 235 System Timer Current value register STCURR 0xE000 E018 bit description Bit Symbol Description Reset value 23 0 CURRENT Reading this register returns the current value of the System Tick 0 counter Writing any value clears the System Tick counter and the COUNTFLAG bit in STCTRL 31 24 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined System Timer Calibration value register STCALIB 0xE000 E01C lt tbd gt Table 236 System Timer Calibration value register STCALIB 0xE000 E01C bit description Bit Symbol Value Description Reset value 23 0 TENMS lt tbd gt lt tbd gt O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 238 of 290 NXP Semiconductors U M1 0375 Chapter 15 LPC13xx SysTick timer Table 236 System Timer Calibration value register STCALIB 0xE000 E01C bit description Bit Symbol Value Description Reset value 29 24 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 30 SKEW lt tbd gt 0 31 NOREF lt tbd gt 0 6 Example timer calculations UM10375_0 The following examples illustrate selecting System Tick Timer valu
339. ou wish to call IAP you could use the following statement lap_entry command result As per the ARM specification The ARM Thumb Procedure Call Standard SWS ESPC 0002 A 05 up to 4 parameters can be passed in the ro r1 r2 and r3 registers respectively Additional parameters are passed on the stack Up to 4 parameters can be returned in the rO r1 r2 and r3 registers respectively Additional parameters are returned indirectly via memory Some of the IAP calls require more than 4 parameters If the ARM O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 267 of 290 NXP Semiconductors U M1 0375 Chapter 18 LPC13xx Flash memory programming firmware suggested scheme is used for the parameter passing returning then it might create problems due to difference in the C compiler implementation from different vendors The suggested parameter passing scheme reduces such risk The flash memory is not accessible during a write or erase operation IAP commands which results in a flash write erase operation use 32 bytes of space in the top portion of the on chip RAM for execution The user program should not be use this space if IAP flash programming is permitted in the application Table 273 IAP Command Summary IAP Command Command Code Described in Prepare sector s for write operation 5010 Table 18 274 Copy RAM to flash 5110 Table 18 275 Erase sector s 5210 Table 18 276 Blank check sector s 5310 Tab
340. point 0 40 Read 1 byte Endpoint 1 41 Read 1 byte Endpoint xx xx 40 Read 1 byte Endpoint 0 40 Write 1 byte Endpoint 1 41 Write 1 byte Endpoint xx xx 40 Write 1 byte Selected Endpoint F2 Read 1 byte optional Selected Endpoint FA None O NXP B V 2009 All rights reserved Rev 00 10 19 October 2009 116 of 290 NXP Semiconductors U M1 0375 10 1 10 2 10 3 UM10375_0 Chapter 9 LPC13xx USB device controller Set Address Command 0xD0O Data write 1 byte The Set Address command is used to set the USB assigned address and enable the embedded function The address set in the device will take effect after the status stage of the control transaction After a bus reset DEV_ADDR is set to 0x00 and DEV_EN is set to 1 The device will respond to packets for function address 0x00 endpoint O default endpoint Table 140 Device Set Address Register bit description Bit Symbol Description Reset value 6 0 DEV_ADDR Device address set by the software After a bus reset this 0x00 field is set to 0x00 7 DEV_EN Device Enable After a bus reset this bit is set to 1 0 0 Device will not respond to any packets 1 Device will respond to packets for function address DEV_ADDR Configure Device Command 0xD8 Data write 1 byte A value of 1 written to the register indicates that the device is configured and all the enabled non control endpoints will respond Control endpoints are always enabled and respo
341. printable ASCII character set It is more efficient than Hex format which converts 1 byte of binary data in to 2 bytes of ASCII hex The sender should send the check sum after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes The receiver should compare it with the check sum of the received bytes If the check sum matches then the receiver should respond with OK lt CR gt lt LF gt to continue further transmission If the check sum does not match the receiver should respond with RESEND lt CR gt lt LF gt In response the sender should retransmit the bytes ISP flow control A software XON XOFF flow control scheme is used to prevent data loss due to buffer overrun When the data arrives rapidly the ASCII control character DC3 stop is sent to stop the flow of data Data flow is resumed by sending the ASCII control character DC1 start The host should also support the same flow control scheme O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 253 of 290 NXP Semiconductors U M1 0375 7 5 7 6 7 7 7 8 7 9 Chapter 18 LPC13xx Flash memory programming firmware ISP command abort Commands can be aborted by sending the ASCII control character ESC This feature is not documented as a command under ISP Commands section Once the escape code is received the ISP command handler waits for a new command
342. pt is generated then the corresponding bit in the IR will be HIGH Otherwise the bit will be LOW Writing a logic one to the corresponding IR bit will reset the interrupt Writing a zero has no effect Table 224 Interrupt Register TMR32BOIR address 0x4001 4000 and TMR32B1IR address 0x4001 8000 bit description Bit Symbol Description Reset value 0 MRO Interrupt Interrupt flag for match channel 0 0 1 MR1 Interrupt Interrupt flag for match channel 1 0 2 MRz2 Interrupt Interrupt flag for match channel 2 0 3 MR3 Interrupt Interrupt flag for match channel 3 0 4 CRO Interrupt Interrupt flag for capture channel 0 event 0 31 5 Reserved 7 2 Timer Control Register TMR32BOTCR and TMR32B1TCR The Timer Control Register TCR is used to control the operation of the counter timer UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 227 of 290 NXP Semiconductors U M1 0375 Chapter 14 LPC13xx 32 bit counter timer CT32B Table 225 Timer Control Register TMR32BOTCR address 0x4001 4004 and TMR32B1TCR address 0x4001 8004 bit description Bit Symbol Description Reset value 0 Counter Enable When one the Timer Counter and Prescale Counter are 0 enabled for counting When zero the counters are disabled 1 Counter Reset When one the Timer Counter and the Prescale Counter 0 are synchronously reset on the next positive edge of PCLK The counters remain reset until TCR 1 is r
343. ption 155 Table 177 SSPO Control Register 1 SSPOCR1 address 0x4004 0004 bit description 156 Table 178 SSPO Data Register SSPODR address 0x4004 0008 bit description 157 Table 179 SSPO Status Register SSPOSR address 0x4004 000C bit description 157 Table 180 SSPO Clock Prescale Register SSPOCPSR address 0x4004 0010 bit description 158 Table 181 SSPO Interrupt Mask Set Clear register SSPOIMSC address 0x4004 0014 bit CESCHPLION s r ecos oy dee ee 158 Table 182 SSPO Raw Interrupt Status register SSPORIS address 0x4004 0018 bit description 159 Table 183 SSPO Masked Interrupt Status register SSPOMIS address 0x4004 001C bit description 159 Table 184 SSPO interrupt Clear Register SSPOICR address 0x4004 0020 bit description 160 Table 185 12C bus pin description 169 Table 186 Register overview 12C base address 0x4000 0000 cil ed cee ea eee denne se ene 170 Table 187 12C Control Set register I2CONSET address 0x4000 0000 bit description 171 Table 188 12C Status register I2STAT 0x4000 0004 bit UM10375_0 Chapter 20 LPC13xx Supplementary information description A A 173 Table 189 12C Data register I2DAT 0x4000 0008 bit description o lt lt On 173 Table 190 12C SCL HIGH duty cycle register I2SCLH address 0x4000 0010 bit description 173 T
344. ption Bit Symbol Value Description Reset value 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved Table 65 IOCON_nRESET_PIOO_0 register IOCON_nRESET_PIOO_0 address 0x4004 400C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function RESET 001 Selects function PIOO_0 010to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 58 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 66 IOCON_PIOO_1 register IOCON_PIOO_1 address 0x4004 4010 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIOO_1 001 Selects function CLKOUT 010 Selects function CT32BO_MAT2 011 Selects function USB_FTOGGLE 100 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control
345. ption ahb_sys clk see PCLK This is the system bus clock Minimum frequency of this clock Table 3 23 is 16 MHz usb_clk see USB_MainClk USB_MainClk is the 48 MHz 500 ppm input clock This Table 3 30 clock does not need to be synchronized with the system clock PCLK Gating of this clock is possible by an external control block using the USB_NeedClk signal This clock will be used to recover the 12 MHz clock from the USB bus UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 106 of 290 NXP Semiconductors U M1 0375 Chapter 9 LPC13xx USB device controller The usb_clk clock can be either provided by the main clock or a dedicated USB PLL see Figure 3 3 The USB PLL can be powered down if it is not used for the usb_clk in the PDRUNCFG register Section 3 5 46 to conserve power 8 3 Power management support To help conserve power the USB device controller automatically disables PCLK and USB_MainCIk when not in use The assertion of USB_Suspend _N signal indicates that there was no activity on the USB bus for the last 3 ms At this time an interrupt is sent to the processor on which the software can start preparing the device for suspend If there is no activity again for the next 2 ms the USB_NeedClk signal will go low This shuts off the USB_MainClk automatically Once the USB_MainClk is switched off internal registers in the USB clock domain will not be visible to the softwa
346. r CT16B l PWM2 MAT2 l l l MR2 100 l l l l I PWM1 MAT1 J f MR1 41 f PWMo MATO i mro 65 1 T 1 1 I 1 I I AE MZ 0 41 65 100 counter is reset Fig 44 Sample PWM waveforms with a PWM cycle length of 100 selected by MR3 and MAT3 0 enabled as PWM outputs by the PWCON register 8 Example timer operation Figure 13 45 shows a timer configured to reset the count and generate an interrupt on match The prescaler is set to 2 and the match register set to 6 At the end of the timer cycle where the match occurs the timer count is reset This gives a full length cycle to the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value Figure 13 46 shows a timer configured to stop and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the next clock after the timer reaches the match value the timer enable bit in TCR is cleared and the interrupt indicating that a match occurred is generated PCLK counter timer counter timer counter reset interrupt Fig 45 A timer cycle prescale in which PR 2 MRx 6 and both interrupt and reset on match are enabled Fig 46 A timer cycle PCLK AR BA BA 4 5 o A AAA counter enable interrupt in which PR 2 MRx 6 and both interrupt and stop on match are enabled UM10375_0 NXP B V 2009
347. r example it may be desirable to use some A D channels to monitor sensors by continuously performing conversions on them The most recent results are read by the application program whenever they are needed In this case an interrupt is not desirable at the end of each conversion for some A D channels Table 242 A D Interrupt Enable Register ADOINTEN address 0x4001 COOC bit description Bit Symbol Description Reset Value 7 0 ADINTEN7 0 These bits allow control over which A D channels generate 0x00 interrupts for conversion completion When bit 0 is one completion of a conversion on A D channel 0 will generate an interrupt when bit 1 is one completion of a conversion on A D channel 1 will generate an interrupt etc 8 ADGINTEN When 1 enables the global DONE flag in ADDR to generate an 1 interrupt When 0 only the individual A D channels enabled by ADINTEN 7 0 will generate interrupts 31 9 Unused Unused always 0 0 A D Data Registers ADODRO to ADODR7 0x4001 C010 to 0x4001 C02C The A D Data Register hold the result when an A D conversion is complete and also include the flags that indicate when a conversion has been completed and when a conversion overrun has occurred O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 244 of 290 NXP Semiconductors U M1 0375 6 Operation Chapter 16 LPC13xx Analog to Digital Converter ADC Table 243 A D Data Registers ADODRO to
348. r level The reassertion of RTS signals the sending UART to continue transmitting data NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 138 of 290 NXP Semiconductors U M1 0375 Chapter 10 LPC13xx UART If Auto RTS mode is disabled the RTSen bit controls the RTS output of the UART If Auto RTS mode is enabled hardware controls the RTS output and the actual value of RTS will be copied in the RTS Control bit of the UART As long as Auto RTS is enabled the value of the RTS Control bit is read only for software Example Suppose the UART operating in type 550 mode has the trigger level in UOFCR set to 0x2 then if Auto RTS is enabled the UART will deassert the RTS output as soon as the receive FIFO contains 8 bytes Table 10 159 on page 137 The RTS output will be reasserted as soon as the receive FIFO hits the previous trigger level 4 bytes UART Rx RTS pin UART Rx FIFO read UART Rx FIFO level Fig 15 Auto RTS Functional Timing bitsO 7 UM10375_0 5 7 1 2 Auto CTS The Auto CTS function is enabled by setting the CTSen bit If Auto CTS is enabled the transmitter circuitry in the UOTSR module checks CTS input before sending the next data byte When CTS is active low the transmitter sends the next byte To stop the transmitter from sending the following byte CTS must be released before the middle of the last stop bit that is currently being sent In Aut
349. r level 3 14 characters or OxOE 31 8 Reserved UART Modem Control Register The UOMCR enables the modem loopback mode and controls the modem output signals NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 137 of 290 NXP Semiconductors U M1 0375 UM10375_0 5 7 1 5 7 1 1 Chapter 10 LPC13xx UART Table 160 UARTO Modem Control Register UOMCR address 0x4000 8010 bit description Bit Symbol Value Description Reset value 0 DTR Source for modem output pin DTR This bit reads as 0 when 0 Control modem loopback mode is active 1 RTS Source for modem output pin RTS This bit reads as 0 when 0 Control modem loopback mode is active 3 2 NA Reserved user software should not write ones to reserved bits 0 The value read from a reserved bit is not defined 4 Loopback The modem loopback mode provides a mechanism to perform 0 Mode diagnostic loopback testing Serial data from the transmitter is Select connected internally to serial input of the receiver Input pin RXD has no effect on loopback and output pin TXD is held in marking state The four modem inputs CTS DSR RI and DCD are _ disconnected externally Externally the modem outputs RTS DTR are set inactive Internally the four modem outputs are connected to the four modem inputs As a result of these connections the upper four bits of the UOMSR will be driven by the lower four bits of the UOMCR rather than
350. ration A D mode In A D mode the digital receiver is disconnected to obtain an accurate input voltage for analog to digital conversions This mode is available in those IOCON registers that control pins which can function as ADC inputs If A D mode is selected Hysteresis and Pin mode settings have no effect 12C mode If the 12C function is selected by the FUNC bits of registers IOCON_PIOO_4 Table 5 73 and IOCON_PIO0_5 Table 5 74 then the I2C bus pins can be configured for different 12C modes e Standard mode Fast mode I2C with input glitch filter this includes an open drain output according to the I2C bus specification e Fast mode Plus with input glitch filter this includes an open drain output according to the 12C bus specification In this mode the pins function as high current sinks e Standard I O functionality without input filter Remark Either Standard mode Fast mode 12C or Standard 1 O functionality should be selected if the pin is used as GPIO pin 4 Register description The I O configuration registers control the following pins PIO ports the 1 C bus pins and the ADC input pins The pin functions selectable in each IOCON register are listed in order function 0 function 1 function 2 in the description column in Table 5 61 Remark The IOCON registers are listed in order of their memory locations in Table 5 61 which correspond to the order of their physical pin numbers in the LQFP48 package
351. re When the activity is detected on the bus USB_Suspend _N is deactivated and USB_NeedClk signal is activated This process is fully combinatorial and hence no USB_MainCIk is required to activate the USB_NeedClk signal The usb_clk_enable signal is provided by the sys_ahb_clk 14 bit see Table 3 23 which enables the clock to the USB register block In addition the on chip device PHY can be powered down in the PDRUNCFG register Section 3 5 46 if USB operation is suspended USB block Clock control block usb_clk_enable USB_NeedClk i 48 Mhz USB_MainClk y SB_BitClk_Out USB_BitClk lt aa PCLK a eme AAA LL USB_NeedClk USB_MainCIk LL 22 UA U Fig 14 USB clocking UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 107 of 290 NXP Semiconductors UM10375 8 4 8 5 Chapter 9 LPC13xx USB device controller Remote wake up The USB block supports software initiated remote wake up Remote wake up involves a resume signal initiated from the device This is done by resetting the suspend bit in the Device Status register Before writing into the register both clocks to the USB block have to be enabled in the SysCon block Interrupts The external interrupt generation takes place only if the necessary enable bits are set in the Device Interrupt Enable register The raw interrupt status will be registered i
352. re Table 268 LPC13xx part identification numbers Device ASCIl dec coding Hex coding LPC1311FHN33 742543403 0x2C42 502B LPC1313FHN33 742395947 0x2C40 102B LPC1313FBD48 742395947 0x2C40 102B LPC1342FHN33 755056683 0x2D01 402B LPC1343FHN33 754974763 0x2D00 002B LPC1343FBD48 754974763 0x2D00 002B Read Boot code version number Table 269 ISP Read Boot Code version number command Command K Input None Return Code CMD _SUCCESS followed by 2 bytes of boot code version number in ASCII format It is to be interpreted as lt byte1 Major gt lt byte0 Minor gt Description This command is used to read the boot code version number Compare lt address1 gt lt address2 gt lt no of bytes gt Table 270 ISP Compare command Command M Input Address1 DST Starting flash or RAM address of data bytes to be compared This address should be a word boundary Address2 SRC Starting flash or RAM address of data bytes to be compared This address should be a word boundary Number of Bytes Number of bytes to be compared should be a multiple of 4 Return Code CMD _SUCCESS Source and destination data are equal COMPARE_ERROR Followed by the offset of first mismatch COUNT_ERROR Byte count is not a multiple of 4 ADDR_ERROR ADDR_NOT_MAPPED PARAM_ERROR Description This command is used to compare the memory contents at two locations Compare result may not be correct when source or destination address cont
353. re can load any data to be sent using transmit length and data registers Isochronous transfer Isochronous endpoints are double buffered and the buffer toggling will happen only on frame boundaries i e at every 1 ms Clear Buffer and Validate Buffer do not cause the buffer to toggle O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 126 of 290 NXP Semiconductors U M1 0375 12 5 Chapter 9 LPC13xx USB device coniroller For OUT isochronous endpoints the data will always be written irrespective of the buffer status For IN isochronous endpoints the data available in the buffer will be sent only if the buffer is validated otherwise an empty packet will be sent There will not be any interrupt generated specific to isochronous endpoints other than the frame interrupt It is assumed that the Isochronous pipe is open at the reception of a request Set Interface alternate setting gt 0 This request is sent to the interface to which the isochronous endpoint belongs This means that the device is expecting the first isochronous transfer within the millisecond Automatic stall feature The USB block includes a Hardware STALL mechanism H W STALL will occur in the following control transactions e Data stage consists of INs the status is a single OUT transaction with an empty packet sent by the host e Data stage consists of OUTs the status is a single IN transaction for whic
354. re clears the endpoint interrupt Software fills B_1 with the third packet and validates it using the SIE Validate Buffer command The active buffer is switched to B 2 The device successfully sends the second packet from B_2 and generates an endpoint interrupt Software has no more packets to send so it simply clears the interrupt The device successfully sends the third packet from B_1 and generates an endpoint interrupt Software has no more packets to send so it simply clears the interrupt Both B_1 and B_2 are empty and the active buffer is B_2 The next packet written by software will go into B_2 Isochronous endpoints For isochronous endpoints the active data buffer is switched by hardware when the FRAME interrupt occurs The SIE Clear Buffer and Validate Buffer commands do not cause the active buffer to be switched Double buffering allows the software to make full use of the frame interval writing or reading a packet to or from the active buffer while the packet in the other buffer is being sent or received on the bus For an OUT isochronous endpoint any data not read from the active buffer before the end of the frame is lost when it switches For an IN isochronous endpoint if the active buffer is not validated before the end of the frame an empty packet is sent on the bus when the active buffer is switched and its contents will be overwritten when it becomes active again NXP B V 2009 All rights rese
355. re clears the endpoint interrupt and begins reading the packet data from B_1 While B_1 is still being read the host sends a second packet which device hardware places in B_2 and generates an endpoint interrupt Software is still reading from B_1 when the host attempts to send a third packet Since both B_1 and B_2 are full the device hardware responds with a NAK Software finishes reading the first packet from B_1 and sends a SIE Clear Buffer command to free B_1 to receive another packet B_2 becomes the active buffer Software sends the SIE Select Endpoint command to read the Select Endpoint Register and test the FE bit Software finds that the active buffer B_2 has data FE 1 Software clears the endpoint interrupt and begins reading the contents of B 2 The host resends the third packet which device hardware places in B_1 An endpoint interrupt is generated Software finishes reading the second packet from B_2 and sends a SIE Clear Buffer command to free B_2 to receive another packet B_1 becomes the active buffer Software waits for the next endpoint interrupt to occur it already has been generated back in step 6 Software responds to the endpoint interrupt by clearing it and begins reading the third packet from B_1 Software finishes reading the third packet from B_1 and sends a SIE Clear Buffer command to free B_1 to receive another packet B_2 becomes the active buffer Software tests the FE bit
356. rement if a time out occurs the rate measurement counter overflows If this bit is set the rate measurement will restart at the next falling edge of the UART Rx pin The auto baud function can generate two interrupts e The UOIIR ABTOInt interrupt will get set if the interrupt is enabled UOIER ABToIntEn is set and the auto baud rate measurement counter overflows e The UOIIR ABEOInt interrupt will get set if the interrupt is enabled UOIER ABEOIntEn is set and the auto baud has completed successfully The auto baud interrupts have to be cleared by setting the corresponding UOACR ABTOIntClr and ABEOIntEn bits NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 144 of 290 NXP Semiconductors U M1 0375 Chapter 10 LPC13xx UART The fractional baud rate generator must be disabled DIVADDVAL 0 during auto baud Also when auto baud is used any write to UODLM and UODLL registers should be done before UOACR register write The minimum and the maximum baud rates supported by UART are function of UART_PCLK number of data bits stop bits and parity bits 6 ratemin eee lt UART EGER Le ne eee t 16 x 215 baudrate 16 x 2 databits paritybits stopbits cone 5 14 Auto baud modes When the software is expecting an AT command it configures the UART with the expected character format and sets the UOACR Start bit The initial values in the divisor latches UODLM and UODLM dont care
357. requirements have been met before they are allowed to trigger the GPIOIE Bits read as zero indicate that the corresponding input pins have not initiated an interrupt The register is read only NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 87 of 290 NXP Semiconductors UM10375 3 8 3 9 Chapter 7 LPC13xx General Purpose I O GPIO Table 115 GPIOnIRS register GPIOOIRS address 0x5000 8014 to GPIO3IRS address 0x5003 8014 bit description Bit Symbol Access Value Description Reset value 11 0 MASK R Selects interrupt on pin x to be masked x 0 to 11 0x00 0 No interrupt on pin PlOn_x 1 Interrupt requirements met on PIOn_x 31 12 a Reserved GPIO masked interrupt status register Bits read HIGH in the GPIOnMIS register reflect the status of the input lines triggering an interrupt Bits read as LOW indicate that either no interrupt on the corresponding input pins has been generated or that the interrupt is masked GPIOMIS is the state of the interrupt after masking The register is read only Table 116 GPIOnMIS register GPIOOMIS address 0x5000 8018 to GPIO3MIS address 0x5003 8018 bit description Bit Access Symbol Value Description Reset value 11 0 R MASK Selects interrupt on pin x to be masked x 0 to 11 0x00 0 No interrupt or interrupt masked on pin PIOn_x 1 Interrupt on PIOn_x 31 12 Reserved GPIO interrupt clear register Table 117 GPIO
358. ress 0x4000 C000 continued Name Access Address Description Reset offset valuel TMR16BOPC R W 0x010 Prescale Counter PC The 16 bit PC is a counter which is incremented 0 to the value stored in PR When the value in PR is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface TMR16BOMCR R W 0x014 Match Control Register MCR The MCR is used to control if an interrupt 0 is generated and if the TC is reset when a Match occurs TMR16BOMRO R W 0x018 Match Register 0 MRO MRO can be enabled through the MCR to reset 0 the TC stop both the TC and PC and or generate an interrupt every time MRO matches the TC TMR16BOMR1 R W 0x01C Match Register 1 MR1 See MRO description TMR16BOMR2 R W 0x020 Match Register 2 MR2 See MRO description TMR16BOMR3 R W 0x024 Match Register 3 MR3 See MRO description TMR16BOCCR R W 0x028 Capture Control Register CCR The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place TMR16BOCRO RO 0x02C Capture Register 0 CRO CRO is loaded with the value of TC when 0 there is an event on the CT16B0_CAPO input TMR16BOEMR R W 0x03C External Match Register EMR The EMR controls the match function 0 and the external match pins CT16B0_MATT 2 0 0x040 reserved s 0x06C TMR16BOCTCR R W 0x070 Count Control Register CTCR The CTCR sele
359. rite one or more one s to this write only register to clear the corresponding interrupt condition s in the SSP controller Note that the other two interrupt conditions can be cleared by writing or reading the appropriate FIFO or disabled by clearing the corresponding bit in SSPOIMSC Table 184 SSPO interrupt Clear Register SSPOICR address 0x4004 0020 bit description Bit Symbol Description Reset Value 0 RORIC Writing a 1 to this bit clears the frame was received when NA RxFIFO was full interrupt 1 RTIC Writing a 1 to this bit clears the Rx FIFO was not empty and NA has not been read for a timeout period interrupt 7 2 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 7 Functional description 7 1 Texas Instruments synchronous serial frame format Figure 11 20 shows the 4 wire Texas Instruments synchronous serial frame format supported by the SSP module CLK FS DX DR 4 to 16 bits a Single frame transfer 4 to 16 bits 4 to 16 bits b Continuous back to back frames transfer Fig 20 Texas Instruments Synchronous Serial Frame Format a Single and b Continuous back to back Two Frames Transfer For device configured as a master in this mode CLK and FS are forced LOW and the transmit data line DX is in 3 state mode whenever the SSP is idle Once the bottom entry of the transmit FIFO contains data FS is pulsed HI
360. rol 245 Ox4000 400C cece cece eee cues 247 6 Register description 245 7 Block diagraM ooooococccococo 247 6 1 Watchdog Mode register WDMOD 0x4000 0000 2 0 000 246 Chapter 18 LPC13xx Flash memory programming firmware 1 How to read this chapter 249 6 Criterion for Valid User Code 250 2 Bootloader oo ooooooocmoommooo 249 7 ISP IAP communication protocol 251 3 Features oo ica gi ere 249 7 1 ISP command format 251 4 Description 0 00000eeee0es 249 7 2 ISP response format 251 5 Memory map after any reset 250 e Eb oa A AO UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 289 of 290 NXP Semiconductors UM10375 7 5 7 6 7 7 7 8 7 9 8 9 10 11 11 1 12 12 1 12 2 12 3 12 4 12 5 12 6 12 7 12 8 12 9 ISP command abort 00 252 Interrupts during ISP o o o 252 Interrupts during IAP 252 RAM used by ISP command handler 252 RAM used by IAP command handler 252 USB communication protocol 252 Boot process flowchart 254 Sector numbers 2 00 cece eens 255 Code Read Protection CRP 255 ISP entry protection 257 ISP commands 0 0e eee eee eee 257 Unlock lt Unlock code gt
361. rrupts STARTERP1 R W 0x214 Start logic signal enable register 1 top 8 Table 3 46 interrupts STARTRSRPICLR W 0x218 Start logic reset register 1 top 8 interrupts n a Table 3 47 STARTSRP1 R 0x21C Start logic status register 1 top 8 n a Table 3 48 interrupts 0x220 0x22C Reserved E PDSLEEPCFG R W 0x230 Power down states in Deep sleep mode lt tbd gt Table 3 49 PDAWAKECFG R W 0x234 Power down states after wake up from lt tbd gt Table 3 50 Deep sleep mode PDRUNCFG R W 0x238 Power down configuration register lt tbd gt Table 3 51 0x23C 0x3F0 Reserved DEVICE_ID R Ox3F4 Device ID part Table 3 52 dependent 5 1 System memory remap register The system memory remap register selects whether the ARM interrupt vectors are read from the boot ROM the flash or the SRAM UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 13 of 290 NXP Semiconductors U M1 0375 UM10375_0 5 2 5 3 Chapter 3 LPC13xx System configuration Table 6 System memory remap register SYSMEMREMAP address 0x4004 8000 bit description Bit Symbol Value Description Reset value 1 0 MAP System memory remap 0x00 00 Boot Loader Mode Interrupt vectors are re mapped to Boot ROM 01 User RAM Mode Interrupt vectors are re mapped to Static RAM 10or User Flash Mode Interrupt vectors are not re mapped and 11 reside in Flash 31 22 Reserved 0x00 Peripheral reset control register This register allows so
362. rved User manual Rev 00 10 19 October 2009 286 of 290 NXP Semiconductors UM10375 Chapter 20 LPC13xx Supplementary information RS 485 ElA 485 Normal Multidrop Mode NMM RS485 ElA 485 driver delay time 151 150 RS485 EIA 485 output inversion 151 RS 485 ElA 485 Auto Address Detection AAD 5 21 UART FIFO Level register UOFIFOLVL MONO e rene a a a kaw tweed 150 0x4000 8058 Read Only 151 RS 485 ElA 485 Auto Direction Control 150 6 Architecture a an ounous onnan ennn 151 Chapter 11 LPC13xx SSP 1 How to read this chapter 153 6 7 SSPO Raw Interrupt Status Register SSPORIS 2 Features 0 ceccecececeeceaeeurees 153 0x4004 0018 coccion See 159 3 General descripti0N 153 68 o oooO Register 168 4 Pin description AE SEE ae DEE iE eae 154 6 9 SSPO Interrupt Clear Register SSPOICR 5 Clocking and power control 154 0x4004 0020 oooccocccccc 160 6 Register description sata trends 155 7 Functional description 160 6 1 SSPO Control Register 0 SSPOCRO 7 1 Texas Instruments synchronous serial frame 0x4004 0000 lt lt s si sas piid raean eiis 155 malas tate abs 160 6 2 SSPO Control Register 1 SSPOCR1 7 2 SPI frame format 22 2000005 161 0x4004 0004 e man eee 156 7 24 Clock Polarity CPOL and Phase CPHA control 6 3 SSPO Data Register SSPODR 0x4004 0008 161 157 7 2 2 SPl format wit
363. rved User manual Rev 00 10 19 October 2009 129 of 290 UM10375 Chapter 10 LPC13xx UART Rev 00 10 19 October 2009 User manual 1 How to read this chapter The UART block is identical for all LPC13xx parts The DSR DCD and RI modem signals are pinned out for the LQFP48 packages only 2 Features e 16 byte receive and transmit FIFOs e Register locations conform to 550 industry standard e Receiver FIFO trigger points at 1 4 8 and 14 bytes e Built in baud rate generator e UART allows for implementation of either software or hardware flow control e RS 485 EIA 485 9 bit mode support with output enable e Modem control 3 Pin description Table 150 UART pin description Pin RXD TXD RTS DTR DSR CTS pcolil RIL Type Input Output Output Output Input Input Input Input Description Serial Input Serial receive data Serial Output Serial transmit data Request To Send RS 485 direction control pin Data Terminal Ready Data Set Ready Clear To Send Data Carrier Detect Ring Indicator 1 LQFP48 packages only 4 Clocking and power control The clocks and power to the UART block are controlled by two registers 1 The UART block can be enabled or disabled through the System AHB clock control register bit 12 see Table 3 23 2 The UART peripheral clock UART_PCLK is enabled in the UART clock divider register see Table 3 25 This clock is u
364. s Detect AAD is disabled 0 Auto Address Detect AAD is enabled If direction control is enabled bit DCTRL 1 pin 0 RTS is used for direction control If direction control is enabled bit DCTRL 1 pin DTR is used for direction control 4 DCTRL 0 Disable Auto Direction Control 0 1 Enable Auto Direction Control 2 AADEN O 2 O O 3 SEL e 5 OINV This bit reverses the polarity of the direction 0 control signal on the RTS or DTR pin O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 150 of 290 NXP Semiconductors U M1 0375 UM10375_0 5 18 5 19 5 20 Chapter 10 LPC13xx UART Table 170 UART RS485 Control register UORS485CTRL address 0x4000 804C bit description continued Bit Symbol Value Description Reset value 0 The direction control pin will be driven to logic 0 when the transmitter has data to be sent It will be driven to logic 1 after the last bit of data has been transmitted 1 The direction control pin will be driven to logic 1 when the transmitter has data to be sent It will be driven to logic 0 after the last bit of data has been transmitted 31 6 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined UART RS 485 Address Match register U0RS485ADRMATCH 0x4000 8050 The UORS485ADRMATCH register contains the address match value for RS
365. s not defined AAC is the Assert Acknowledge Clear bit Writing a 1 to this bit clears the AA bit in the I2CONSET register Writing O has no effect SIC is the 12C Interrupt Clear bit Writing a 1 to this bit clears the SI bit in the l_CONSET register Writing O has no effect STAC is the START flag Clear bit Writing a 1 to this bit clears the STA bit in the I2CONSET register Writing O has no effect I2ZENC is the 12C Interface Disable bit Writing a 1 to this bit clears the I2EN bit in the I2CONSET register Writing O has no effect 12C Monitor mode control register IZCMMCTRLO 0x4000 001C This register controls the Monitor mode which allows the 12 module to monitor traffic on the 12C bus without actually participating in traffic or interfering with the 12C bus Table 195 I2C Monitor mode control register I2CMMCTRLO 0x4000 001C bit description Bit Symbol Value Description Reset value O MM _ENA Monitor mode enable 0 0 Monitor mode disabled 1 The 12C module will enter monitor mode In this mode the SDA output will be forced high This will prevent the 12C module from outputting data of any kind including ACK onto the 12C data bus Depending on the state of the ENA_SCL bit the output may be also forced high preventing the module from having control over the 12C clock line 1 ENA SCL SCL output enable 0 0 When this bit is cleared to 0 the SCL output will be forced high when the module is in monitor
366. s the signal and edge s for counting TMR16B1PWMC R W 0x074 PWM Control Register PWMCON The PWMCON enables PWM mode 0 for the external match pins CT16B1_MATT 1 0 oooO 1 Reset value reflects the data stored in used bits only lt does not include reserved bits content 7 1 Interrupt Register TMR16BOIR and TMR16B1IR The Interrupt Register IR consists of four bits for the match interrupts and one bit for the capture interrupt If an interrupt is generated then the corresponding bit in the IR will be HIGH Otherwise the bit will be LOW Writing a logic one to the corresponding IR bit will reset the interrupt Writing a zero has no effect Table 213 Interrupt Register TMR16BOIR address 0x4000 C000 and TMR16B1IR address 0x4001 0000 bit description Bit Symbol Description Reset value 0 MRO Interrupt Interrupt flag for match channel 0 0 1 MR1 Interrupt Interrupt flag for match channel 1 0 2 MRz2 Interrupt Interrupt flag for match channel 2 0 3 MR3 Interrupt Interrupt flag for match channel 3 0 4 CRO Interrupt Interrupt flag for capture channel 0 event 0 31 5 Reserved 7 2 Timer Control Register TMR16B0TCR and TMR16B1TCR The Timer Control Register TCR is used to control the operation of the counter timer UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 215 of 290 NXP Semiconductors U M1 0375 Chapter 13 LPC13xx 16 bit counter timer CT16B T
367. s with the dividers the risk exists that the counter will read in an undefined value which could lead to unwanted spikes or drops in the frequency of the output clock The recommended way of changing between divider settings is to power down the PLL adjust the divider settings and then let the PLL start up again Frequency selection The PLL frequency equations use the following parameters also see Figure 3 3 Table 55 PLL frequency parameters Parameter System PLL USB PLL FCLKIN Frequency of sys_pllcikin input clock Frequency of usb_pllclkin input clock to the system PLL from the to the USB PLL from the SYSPLLCLKSEL multiplexer see USBPLLCLKSEL multiplexer see Section 3 5 11 Section 3 5 23 FCCO Frequency of the Current Controlled Frequency of the Current Controlled Oscillator CCO 156 to 320 MHz Oscillator CCO 156 to 320 MHz FCLKOUT Frequency of sys_pllclkout Frequency of usb_pllclkout P System PLL post divider ratio PSEL USB PLL post divider ratio PSEL bits bits in SYSPLLCTRL see in USBPLLCTRL see Section 3 5 5 Section 3 5 3 M System PLL feedback divider register USB PLL feedback divider register MSEL bits in SYSPLLCTRL see MSEL bits in USBPLLCTRL see Section 3 5 3 Section 3 5 5 Mode 1 Normal mode In this mode the post divider is enabled giving a 50 duty cycle clock with the following frequency relations 1 Fclkout Mx Fclkin FCCO 2 xP To select the appropriate values for
368. scription Reset value 0 ST Stalled endpoint bit A Stalled control endpoint is automatically 0 unstalled when it receives a SETUP token regardless of the content of the packet If the endpoint should stay in its stalled state the CPU can stall it again by setting this bit When a stalled endpoint is unstalled either by the Set Endpoint Status command or by receiving a SETUP token it is also re initialized This flushes the buffer in case of an OUT buffer it waits for a DATA 0 PID in case of an IN buffer it writes a DATA 0 PID There is no change of the interrupt status of the endpoint When already unstalled writing a zero to this bit initializes the endpoint When an endpoint is stalled by the Set Endpoint Status command it is also re initialized 0 The endpoint is unstalled 1 The endpoint is stalled 4 1 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 5 DA Disabled endpoint bit 0 0 The endpoint is enabled 1 The endpoint is disabled 6 RF_MO Rate Feedback Mode 0 0 Interrupt endpoint is in the Toggle mode 1 Interrupt endpoint is in the Rate Feedback mode This means that transfer takes place without data toggle bit 7 CND_ST Conditional Stall bit 0 0 Unstalls both control endpoints 1 Stall both control endpoints unless the STP bit is set in the Select Endpoint register It is defined only for control OUT endpoints Clear Buffer Command OxF2 Data
369. se When there is just one bus master and one bus slave the Frame Sync or Slave Select signal from the Master can be connected directly to the slave s corresponding input When there is more than one slave on the bus further qualification of their Frame Select Slave Select inputs will typically be necessary to prevent more than one slave from responding to a transfer MISO O MISO DR M SI M Master In Slave Out The MISO signal transfers DX S SO S serial data from the slave to the master When the SSPO is a slave serial data is output on this signal When the SSPO is a master it clocks in serial data from this signal When the SSPO is a slave and is not selected by FS SSEL it does not drive this signal leaves it in high impedance state MOSI O MOSI DX M SO M Master Out Slave In The MOSI signal transfers DR S SI S serial data from the master to the slave When the SSPO is a master it outputs serial data on this signal When the SSPO is a slave it clocks in serial data from this signal 5 Clocking and power control The clocks and power to the SSP block are controlled by two registers 1 The SSP block can be enabled or disabled through the AHBCLKCTRL register see Table 3 23 2 The SSP_PCLK is enabled in the SSP clock divider register see Table 3 24 This clock is used by the SSP clock prescaler Table 11 180 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 156 of
370. se the user is only interested in the lower 8 bits of the frame number only the first byte needs to be read e Incase no SOF was received by the device at the beginning of a frame the frame number returned is that of the last successfully received SOF NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 118 of 290 NXP Semiconductors U M1 0375 Chapter 9 LPC13xx USB device controller e Incase the SOF frame number contained a CRC error the frame number returned will be the corrupted frame number as received by the device 10 6 Read Chip ID Command OxFD Data read 2 bytes The Chip ID is 16 bit wide It returns the value the chip ID LSB first 10 7 Set Device Status Command OxFE Data write 1 byte The Set Device Status command sets bits in the Device Status Register Table 145 Set Device Status Register bit description Bit Symbol Value Description Reset value 0 CON The Connect bit indicates the current connect status of the 0 device It controls the CONNECT output pin used for SoftConnect Reading the connect bit returns the current connect status This bit is cleared by hardware when the Vgus status input is LOW for more than 3 ms The 3 ms delay filters out temporary dips in the Vgus voltage 0 Writing a 0 will make the CONNECT pin go HIGH 1 Writing a 1 will make the CONNECT pin go LOW 1 CON_CH Connect Change 0 0 This bit is cleared when read 1 This bit is set when
371. sed by the UART baud rate generator Remark The UART pins must be configured in the corresponding IOCON registers before the UART clocks are enabled UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 130 of 290 NXP Semiconductors U M1 0375 Chapter 10 LPC13xx UART 5 Register description The UART contains registers organized as shown in Table 10 151 The Divisor Latch Access Bit DLAB is contained in UOLCR 7 and enables access to the Divisor Latches UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 131 of 290 NXP Semiconductors U M1 0375 Chapter 10 LPC13xx UART Table 151 Register overview UART base address 0x4000 8000 Name Access Address Description Reset Notes offset Value UORBR RO 0x000 Receiver Buffer Register Contains the next received character NA when to be read DLAB 0 UOTHR WO 0x000 Transmit Holding Register The next character to be transmitted NA when is written here DLAB 0 UODLL R W 0x000 Divisor Latch LSB Least significant byte of the baud rate 0x01 when divisor value The full divisor is used to generate a baud rate DLAB 1 from the fractional rate divider UODLM R W 0x004 Divisor Latch MSB Most significant byte of the baud rate 0x00 when divisor value The full divisor is used to generate a baud rate DLAB 1 from the fractional rate divider UOIER R W 0x004 Interrupt Enable Register
372. served bits NA The value read from a reserved bit is not defined 7 TXEN When this bit is 1 as it is after a Reset data written to the THR 1 is output on the TXD pin as soon as any preceding data has been sent If this bit cleared to 0 while a character is being sent the transmission of that character is completed but no further characters are sent until this bit is set again In other words a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register Software can clear this bit when it detects that the a hardware handshaking TX permit signal CTS has gone false or with software handshaking when it receives an XOFF character DC3 Software can set this bit again when it detects that the TX permit signal has gone true or when it receives an XON DC1 character 31 8 Reserved UART RS485 Control register UORS485CTRL 0x4000 804C The UORS485CTRL register controls the configuration of the UART in RS 485 ElA 485 mode Table 170 UART RS485 Control register U0RS485CTRL address 0x4000 804C bit description Bit Symbol Value Description Reset value 0 NMMEN 0 RS 485 ElA 485 Normal Multidrop Mode NMM 0 is disabled 1 RS 485 ElA 485 Normal Multidrop Mode NMM is enabled In this mode an address is detected when a received byte causes the UART to set the parity error and generate an interrupt 1 RXDIS The receiver is enabled 0 The receiver is disabled Auto Addres
373. set for start logic input PIO1_0 n a Write reset start signal 23 13 RSRPIO1_11 Start signal reset for start logic input PIO1_11 to n a to PIO1_1 RSRPIO1_1 Write reset start signal 24 RSRPIO2_0 Start signal reset for start logic input PIO2_0 n a Write reset start signal 31 25 RSRPIO2_7 Start signal reset for start logic input PIO2_7 to n a to RSRPIO2_1 PIO2_1 Write reset start signal Start logic status register 0 This register reflects the status of the enabled start signal bits The bit assignment is identical to Table 3 41 Each bit if enabled reflects the state of the start logic i e whether or not a wake up signal has been received for a given pin Table 44 Start logic status register 0 STARTSRPO address 0x4004 820C bit description Bit Symbol 0 SRPIOO_0 11 1 SRPIOO_11 to SRPIOO_1 12 SRPIO1_0 23 13 SRPIO1_11 to SRPIO1_1 Value Description Start signal status for start logic input PIOO_0 No start signal received Start signal pending Start signal status for start logic input PIOO_11 to PIO0_1 No start signal received Start signal pending Start signal status for start logic input PIO1_0 No start signal received Start signal pending Start signal status for start logic input PIO1_11 to PIO1_1 No start signal received Start signal pending Reset value n a n a n a O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 32 of 290 NXP
374. shows a timer configured to stop and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the next clock after the timer reaches the match value the timer enable bit in TCR is cleared and the interrupt indicating that a match occurred is generated PCLK counter timer counter timer counter reset interrupt Fig 49 A timer cycle prescale in which PR 2 MRx 6 and both interrupt and reset on match are enabled Fig 50 A timer cycle PCLK AR BA BA 4 5 o A AAA counter enable interrupt in which PR 2 MRx 6 and both interrupt and stop on match are enabled UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 234 of 290 NXP Semiconductors U M1 0375 Chapter 14 LPC13xx 32 bit counter timer CT32B 9 Architecture UM10375_0 The block diagram for 32 bit counter timerO and 32 bit counter timer1 is shown in Figure 14 51 CONTROL MAT 3 0 INTERRUPT CAPO STOP ON MATCH RESET ON MATCH LOAD 3 0 CAPTURE REGISTER O a o PCLK Mb PRESCALE COUNTER reset enable MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER Fig 51 32 bit counter timer block diagram O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 235 of 290 UM10375 Chapter 15 LPC13xx SysTick timer Rev 00 10 19 October 2009 User manual 1 How to read
375. sistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved Table 76 IOCON_PIO3_4 register IOCON_PIO3_4 address 0x4004 403C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO3_4 001 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 64 of 290 NXP Semiconductors U M1 0375 Chapter 5 LPC13xx I O configuration Table 77 IOCON_PIO2_4 register IOCON_PIO2_4 address 0x4004 4040 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIO2_4 001 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 3 Reserved 1 31 7 Reserved Table 78 IOCON_PIO2_5 register IOCON_PIO2_5 address 0x4004 4044 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin fun
376. slave transmitter mode and slave receiver mode The 12C interface complies with the entire 12C specification supporting the ability to turn power off to the ARM Cortex M3 without interfering with other devices on the same 12C bus pull up resistor pull up resistor SDA 2C bus SCL SDA SCL OTHER DEVICE WITH OTHER DEVICE WITH LPC13xx 12C INTERFACE 2C INTERFACE Fig 28 1 C bus configuration 12C Fast mode Plus Fast Mode Plus supports a 1 Mbit sec transfer rate to communicate with the 12C bus products which NXP Semiconductors is now providing In order to use Fast Mode Plus the 12C pins must be properly configured in the IOCONFIG register block see Table 5 73 and Table 5 74 In Fast mode Plus rates above 400 kHz and up to 1 MHz may be selected 5 Pin description UM10375_0 Table 185 I C bus pin description Pin Type Description SDA Input Output 12C bus Serial Data SCL Input Output 12C bus Serial Clock The 12C bus pins must be configured through the IOCON_PIOO_4 Table 5 73 and IOCON_PIO0_5 Table 5 74 registers for Standard Fast mode or Fast mode Plus In these modes the C bus pins are open drain outputs and fully compatible with the 12C bus specification O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 171 of 290 NXP Semiconductors U M1 0375 Chapter 12 LPC13xx I2C bus interface 6 Clocking and power control
377. source Any clock source works in Sleep mode and the IRC works in Deep sleep mode If a watchdog interrupt occurs in Sleep or Deep sleep mode it will wake up the device Table 246 Watchdog operating modes selection WDEN WDRESET Mode of Operation 0 X 0 or 1 Debug Operate without the Watchdog running 1 0 Watchdog interrupt mode debug with the Watchdog interrupt but no WDRESET enabled When this mode is selected a watchdog counter underflow will set the WDINT flag and the Watchdog interrupt request will be generated 1 1 Watchdog reset mode operate with the Watchdog interrupt and WDRESET enabled When this mode is selected a watchdog counter underflow will reset the microcontroller Although the Watchdog interrupt is also enabled in this case WDEN 1 it will not be recognized since the watchdog reset will clear the WDINT flag UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 248 of 290 NXP Semiconductors U M1 0375 6 2 6 3 6 4 Chapter 17 LPC13xx WatchDog timer WDT Watchdog Timer Constant register WDTC 0x4000 4004 The WDTC register determines the time out value Every time a feed sequence occurs the WDTC content is reloaded in to the Watchdog timer It s a 32 bit register with 8 LSB set to 1 on reset Writing values below OxFF will cause 0x0000 OOFF to be loaded to the WDTC Thus the minimum time out interval is TwpcLk x 256 x 4 Table 247 Watchd
378. subsystem The PLL operating mode is set by the DIRECT and BYPASS bits see Table 3 54 Remark The USB PLL should be always connected to the system oscillator to produce a stable USB clock O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 15 of 290 NXP Semiconductors U M1 0375 UM10375_0 5 6 Chapter 3 LPC13xx System configuration Table 10 USB PLL control register USBPLLCTRL address 0x4004 8010 bit description Bit Symbol Value Description Reset value 4 0 MSEL Feedback divider value The division value M is the 0x000 programmed MSEL value 1 00000 Division ratio M 1 11111 Division ration M 32 6 5 PSEL Post divider ratio P The division ratio is 2 x P 0x00 00 P 1 01 P 2 10 P 4 11 P 8 7 DIRECT Direct CCO clock output control 0x0 0 Clock signal goes through post divider 1 Clock signal goes directly to output s 8 BYPASS Input clock bypass control 0x0 0 CCO clock is sent to post dividers 1 PLL input clock usb_pllclkin is sent to post dividers 31 9 Reserved 0x00 USB PLL status register This register is a Read only register and supplies the PLL lock status see Section 3 10 1 Table 11 USB PLL status register USBPLLSTAT address 0x4004 8014 bit description Bit Symbol Value Description Reset value 0 LOCK PLL lock status 0x0 0 PLL not locked 1 PLL locked 31 1 Reserved 0x00 NXP B V 2009 All rights reserved User man
379. susceptibility to noise XTALOUT should be left floating UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 101 of 290 UM10375 Chapter 9 LPC13xx USB device controller Rev 00 10 19 October 2009 User manual 1 How to read this chapter The USB device controller is available on parts LPC1342 and LPC 1343 only 2 Introduction The Universal Serial Bus USB is a four wire bus that supports communication between a host and one or more up to 127 peripherals The host controller allocates the USB bandwidth to attached devices through a token based protocol The bus supports hot plugging and dynamic configuration of the devices All transactions are initiated by the host controller The host schedules transactions in 1 ms frames Each frame contains a Start Of Frame SOF marker and transactions that transfer data to or from device endpoints Each device can have a maximum of 5 logical or 10 physical endpoints There are four types of transfers defined for the endpoints Control transfers are used to configure the device Interrupt transfers are used for periodic data transfer Bulk transfers are used when the rate of transfer is not critical Isochronous transfers have guaranteed delivery time but no error correction For more information on the Universal Serial Bus see the USB Implementers Forum website The USB device controller on the LPC134x enables full speed 12 Mb
380. t mM 4to 16 bits gt b Continuous transfer with CPOL 1 and CPHA 0 Fig 23 SPI frame format with CPOL 1 and CPHA 0 a Single and b Continuous Transfer UM10375_0 In this configuration during idle periods e The CLK signal is forced HIGH e SSEL is forced HIGH e The transmit MOSI MISO pad is in high impedance If the SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW which causes slave data to be immediately transferred onto the MISO line of the master Master s MOSI pin is enabled One half period later valid master data is transferred to the MOSI line Now that both the master and slave data have been set the SCK master clock pin becomes LOW after one further half SCK period This means that data is captured on the falling edges and be propagated on the rising edges of the SCK signal In the case of a single word transmission after all bits of the data word are transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured However in the case of continuous back to back transmissions the SSEL signal must be pulsed HIGH between each data word transfer This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the CPHA bit is logic zero Therefore the master device must raise the SSEL
381. t value 2 0 FUNC Selects pin function 000 000 Selects function PIOO_8 001 Selects function MISO 010 Selects function CT16BO_MATO 011 Reserved 100 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 31 7 Reserved 2 Table 86 IOCON_PIOO_9 register IOCON_PIO0_9 address 0x4004 4064 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function PIOO_9 001 Selects function MOSI 010 Selects function CT16BO_MAT1 011 Selects function SWO 100 to Reserved 111 4 3 MODE Selects function mode on chip pull up pull down resistor 10 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 2 Reserved 1 31 7 Reserved UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 69 of 290 NXP Semiconductors UM10375 UM10375_0 Chapter 5 LPC13xx I O configuration Table 87 IOCON_JTAG_TCK_PIO0O_10 register IOCON_JTAG_TCK_PIO0O_10 address 0x4004 4068 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function 000 000 Selects function SWCLK
382. t block can not be erased using this command This command only allows erasure of all user sectors when the code read protection is enabled Example E 2 3 lt CR gt lt LF gt erases the flash sectors 2 and 3 12 10 Blank check sector s lt sector number gt lt end sector number gt Table 266 ISP Blank check sector command Command Input Start Sector Number End Sector Number Should be greater than or equal to start sector number Return Code CMD_SUCCESS SECTOR_NOT_BLANK followed by lt Offset of the first non blank word location gt lt Contents of non blank word location INVALID_SECTOR PARAM_ERROR Description This command is used to blank check one or more sectors of on chip flash memory Blank check on sector 0 always fails as first 64 bytes are re mapped to flash boot block Example 2 3 lt CR gt lt LF gt blank checks the flash sectors 2 and 3 12 11 Read Part Identification number Table 267 ISP Read Part Identification command Command J Input None Return Code CMD_SUCCESS followed by part identification number in ASCII see Table 18 268 LPC13xx part identification numbers Description This command is used to read the part identification number UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 264 of 290 NXP Semiconductors U M1 0375 12 12 12 13 UM10375_0 Chapter 18 LPC13xx Flash memory programming firmwa
383. t information is available because the serial interrupt flag Sl is not yet set This occurs between other states and when the 12C block is not involved in a serial transfer I2STAT 0x00 This status code indicates that a bus error has occurred during an I2C serial transfer A bus error is caused when a START or STOP condition occurs at an illegal position in the format frame Examples of such illegal positions are during the serial transfer of an address byte a data byte or an acknowledge bit A bus error may also be caused when external interference disturbs the internal 12C block signals When a bus error occurs Sl is set To recover from a bus error the STO flag must be set and SI must be cleared This causes the 12C block to enter the not addressed slave mode a defined state and to clear the STO flag no other bits in I2CON are affected The SDA and SCL lines are released a STOP condition is not transmitted NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 200 of 290 NXP Semiconductors U M1 0375 Chapter 12 LPC13xx I2C bus interface Table 209 Miscellaneous States Status Status of the I2C bus Application software response Next action taken by I2C hardware code andihardware To From l2DAT To I2CON 12CSTAT STA STO SI AA OxF8 No relevant state No I2DAT action No I2CON action Wait or proceed current transfer information available SI 0 0x00 Bus error duri
384. takes up to 6 WDCLK cycles plus 6 PCLK cycles so the value of WDTV is older than the actual value of the timer when it s being read by the CPU Table 249 Watchdog Timer Value register WDTV address 0x4000 000C bit description Bit Symbol Description Reset Value 31 0 Count Counter timer value 0x0000 OOFF 7 Block diagram UM10375_0 The block diagram of the Watchdog is shown below in the Figure 17 53 The synchronization logic PCLK WDCLK is not shown in the block diagram O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 249 of 290 NXP Semiconductors U M1 0375 Chapter 17 LPC13xx WatchDog timer WDT feed sequence feed ok feed error wdt_clk A J count SHADOW BIT N WMOD register y reset gt interrupt Fig 53 Watchdog block diagram UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 250 of 290 UM10375 Chapter 18 LPC13xx Flash memory programming firmware Rev 00 10 19 October 2009 User manual 1 How to read this chapter See Table 18 250 for different flash configurations and functionality The LPC131x parts do not have an USB interface and only the UART boot option is supported Table 250 LPC13xx flash configurations Type number Flash Boot from USB Boot from UART LPC1311FHN33 8 kB no yes LPC1313FBD48 32 kB no yes LPC
385. tected on modem input DSR State change detected on modem input DSR O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 142 of 290 NXP Semiconductors U M1 0375 UM10375_0 5 11 5 12 Chapter 10 LPC13xx UART Table 164 UART Modem Status Register UOMSR address 0x4000 8018 bit description Bit Symbol Value Description Reset Value 2 Trailing Set upon low to high transition of input RI Cleared on a UOMSR 0 Edge RI read O No change detected on modem input RI 1 Low to high transition detected on RI 3 Delta Set upon state change of input DCD Cleared on a UOMSR read 0 DCD O No change detected on modem input DCD 1 State change detected on modem input DCD 4 CTS Clear To Send State Complement of input signal CTS This bit is 0 connected to UOMCR 1 in modem loopback mode 5 DSR Data Set Ready State Complement of input signal DSR This bitis 0 connected to UOMCR O in modem loopback mode 6 RI Ring Indicator State Complement of input RI This bit is connected 0 to UOMCR 2 in modem loopback mode 7 DCD Data Carrier Detect State Complement of input DCD This bit is 0 connected to UOMCR 3 in modem loopback mode UART Scratch Pad Register UOSCR 0x4000 801C The UOSCR has no effect on the UART operation This register can be written and or read at user s discretion There is no provision in the interrupt interface that would indicate to the host that a read or writ
386. ten while a conversion is still in progress this bit is set and a new conversion is started 5 3 A D Status Register ADOSTAT 0x4001 C030 The A D Status register allows checking the status of all A D channels simultaneously The DONE and OVERRUN flags appearing in the ADDRn register for each A D channel are mirrored in ADSTAT The interrupt flag the logical OR of all DONE flags is also found in ADSTAT UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 243 of 290 NXP Semiconductors U M1 0375 5 4 5 5 UM10375_0 Chapter 16 LPC13xx Analog to Digital Converter ADC Table 241 A D Status Register ADOSTAT address 0x4001 C030 bit description Bit Symbol Description Reset Value 7 0 Done7 0 These bits mirror the DONE status flags that appear in the result 0 register for each A D channel 15 8 Overrun7 0 These bits mirror the OVERRRUN status flags that appear in the 0 result register for each A D channel Reading ADSTAT allows checking the status of all A D channels simultaneously 16 ADINT This bit is the A D interrupt flag It is one when any of the individual 0 A D channel Done flags is asserted and enabled to contribute to the A D interrupt via the ADINTEN register 31 17 Unused Unused always 0 0 A D Interrupt Enable Register ADOINTEN 0x4001 C00C This register allows control over which A D channels generate an interrupt when a conversion is complete Fo
387. ter to Slave O from Slave to Master Fig 32 Format of Slave Receiver mode UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 182 of 290 NXP Semiconductors U M1 0375 8 4 9 Functional Chapter 12 LPC13xx I2C bus interface Slave Transmitter mode The first byte is received and handled as in the slave receiver mode However in this mode the direction bit will be 1 indicating a read operation Serial data is transmitted via SDA while the serial clock is input through SCL START and STOP conditions are recognized as the beginning and end of a serial transfer In a given application 12 may operate as a master and as a slave In the slave mode the I2C hardware looks for its own slave address and the General Call address If one of these addresses is detected an interrupt is requested When the microcontrollers wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the master mode the 12C interface switches to the slave mode immediately and can detect its own slave address in the same serial transfer 0 write 1 read data transferred n Bytes Acknowledge A Acknowledge SDA low A Not acknowledge SDA high S START condition P STOP condition E from Master to Slave C from Slave to Master Fig
388. terleaved read and write operation is possible Remark It takes 3 clock cycle to fetch the packet length from the RAM after programming the USB control register There can be a corruption on the packet length value read if the reading of the packet length occurs immediately in the very next clock cycle after the programming of USB control register To avoid this problem a NOP instruction has to be inserted in between the programming of USBCirl registers and reading of packet length registers For example follow these steps 1 USBCtrl 0x01 2 delay 0 generate 1 clock cycle delay 3 pkt_length USBTxPLen or USBRxPlen Miscellaneous registers USB Device FIQ Select register USBDevFIQSel 0x4002 002C When a bit is set 1 the corresponding interrupt will be routed to the high priority interrupt line Setting all bits to 1 at the same time is not allowed If the software attempts to set all the bits to 1 none of them will be routed to the high priority interrupt line Table 138 USB Device FIQ Select register USBDevFIQSel address 0x4002 002C bit description Bit Symbol Value Description Reset value 0 FRAME This interrupt comes from a 1 KHz free running clock 0 resynchronized on the incoming SoF tokens This is to be used for isochronous packet transfer 0 FRAME interrupt will be routed to the low priority interrupt line IRQ 1 FRAME interrupt will be routed to the high priority interrupt line FIQ
389. ters 109 10 7 Set Device Status Command OxFE Data write 1 9 3 1 USB Receive Data register USBRxData 0x4002 Dyte ecer ie eta dees elie A 117 0018 2 0245 amip eet aue ian do 109 10 8 Get Device Status Command OxFE Data read 1 9 3 2 USB Transmit Data register USBTxData 0x4002 D C wie eteraeibehedee idee tdaanr eed 118 02 1G sete A eves okra taa Os 110 10 9 Get Error Code Command OxFF Data read 1 9 3 3 USB Receive Packet Length register A re ae ee 118 USBRxPLen 0x4002 0020 110 10 10 Select Endpoint Command 0x00 0x09 Data 9 3 4 USB Transmit Packet Length register read 1 byte optional 119 USBTxPLen 0x4002 0024 110 10 11 Select Endpoint Clear Interrupt Command 9 3 5 USB Control register USBCirl 0x4002 0028 0x40 0x47 Data read 1 byte 120 111 10 12 Set Endpoint Status Command 0x40 0x49 9 3 5 1 Data transfer 0 2 ee eee ee eee 111 Data write 1 byte optional 120 9 4 Miscellaneous registers 112 10 13 Clear Buffer Command OxF2 Data read 1 byte 9 4 1 USB Device FIQ Select register USBDevFIQSel optional 2 6 eee ee eee 121 0x4002 002C 0 eee eee 112 10 14 Validate Buffer Command OxFA Data none 10 Serial interface engine command description 122 113 11 USB device controller initialization 122 10 1 Set Address Command OxDO Data write 1 byte 11 1 U
390. the UART RBR FIFO Break interrupt status is inactive Break interrupt status is active THRE is set immediately upon detection of an empty UART THR 1 and is cleared on a UOTHR write UOTHR contains valid data UOTHR is empty TEMT is set when both UOTHR and UOTSR are empty TEMT is 1 cleared when either the UOTSR or the UOTHR contain valid data UOTHR and or the UOTSR contains valid data UOTHR and the UOTSR are empty UOLSR 7 is set when a character with a RX error such as framing 0 error parity error or break interrupt is loaded into the UORBR This bit is cleared when the UOLSR register is read and there are no subsequent errors in the UART FIFO UORBR contains no UART RX errors or UOFCR 0 0 UART RBR contains at least one UART RX error Reserved UART Modem Status Register The UOMSR is a read only register that provides status information on the modem input signals UOMSR 3 0 is cleared on UOMSR read Note that modem signals have no direct effect on the UART operation They facilitate the software implementation of modem signal operations Table 164 UART Modem Status Register UOMSR address 0x4000 8018 bit description Bit Symbol Value Description Reset Value O Delta Set upon state change of input CTS Cleared on a UOMSR read 0 CTS O No change detected on modem input CTS 1 State change detected on modem input CTS 1 Delta Set upon state change of input DSR Cleared on a UOMSR read 0 DSR 0 No change de
391. the device s pull up resistor is disconnected because Vgys disappeared The DEV_STAT interrupt is generated when this bit is 1 2 SUS Suspend The Suspend bit represents the current suspend state 0 When the device is suspended SUS 1 and the CPU writes a 0 into it the device will generate a remote wake up This will only happen when the device is connected CON 1 When the device is not connected or not suspended writing a 0 has no effect Writing a 1 to this bit has no effect 0 This bit is reset to 0 on any activity 1 This bit is set to 1 when the device hasn t seen any activity on its upstream port for more than 3 ms 3 SUS CH Suspend SUS bit change indicator The SUS bit can toggle 0 because e The device goes into the suspended state e The device is disconnected e The device receives resume signalling on its upstream port This bit is cleared when read 0 SUS bit not changed 1 SUS bit changed At the same time a DEV_STAT interrupt is generated UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 119 of 290 NXP Semiconductors UM10375 UM10375_0 10 8 10 9 Chapter 9 LPC13xx USB device controller Table 145 Set Device Status Register bit description Bit Symbol Value Description Reset value 4 RST Bus Reset bit On a bus reset the device will automatically go to 0 the default state In the default state Device is unconfigured Will respond to a
392. the four modem inputs in normal mode This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of UOMCR 0 Disable modem loopback mode 1 Enable modem loopback mode 5 NA Reserved user software should not write ones to reserved bits 0 The value read from a reserved bit is not defined 6 RTSen Disable auto rts flow control 0 Enable auto rts flow control 7 CTSen Disable auto cts flow control 0 Oo O Enable auto cts flow control Auto flow control If auto RTS mode is enabled the UART s receiver FIFO hardware controls the RTS output of the UART If the auto CTS mode is enabled the UART s UOTSR hardware will only start transmitting if the CTS input signal is asserted Auto RTS The auto RTS function is enabled by setting the RTSen bit Auto RTS data flow control originates in the UORBR module and is linked to the programmed receiver FIFO trigger level If auto RTS is enabled the data flow is controlled as follows When the receiver FIFO level reaches the programmed trigger level RTS is deasserted to a high value It is possible that the sending UART sends an additional byte after the trigger level is reached assuming the sending UART has another byte to send because it might not recognize the deassertion of RTS until after it has begun sending the additional byte RTS is automatically reasserted to a low value once the receiver FIFO has reached the previous trigge
393. this chapter The system tick timer SysTick timer is part of the ARM Cortex M3 core and is identical for all LPC13xx parts 2 Features e Times intervals of 10 milliseconds e Uses dedicated exception vector e Clocked internally by a dedicated system tick timer clock 3 Description The System Tick Timer is an integral part of the Cortex M3 The System Tick Timer is intended to generate a fixed 10 millisecond interrupt for use by an operating system or other system management software Since the System Tick Timer is a part of the Cortex MA3 it facilitates porting of software by providing a standard timer that is available on Cortex M3 based devices Refer to the Cortex M3 User Guide for details 4 Operation The System Tick Timer is a 24 bit timer that counts down to zero and generates an interrupt The intent is to provide a fixed 10 millisecond time interval between interrupts The System Tick Timer is clocked from the CPU clock In order to generate recurring interrupts at a specific interval the STRELOAD register must be initialized with the correct value for the desired interval A default value is provided in the STCALIB register and may be changed by software The default value gives a 10 millisecond interrupt rate if the CPU clock is set to lt tbd gt The block diagram of the System Tick Timer is shown below in the Figure 15 52 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10
394. tination address is not on a correct boundary Source address is not mapped in the memory map Count value is taken in to consideration where applicable Destination address is not mapped in the memory map Count value is taken in to consideration where applicable Byte count is not multiple of 4 or is not a permitted value Sector number is invalid or end sector number is greater than start sector number Sector is not blank Command to prepare sector for write operation was not executed Source and destination data not equal Flash programming hardware interface is busy Insufficient number of parameters or invalid parameter Address is not on word boundary Address is not mapped in the memory map Count value is taken in to consideration where applicable Command is locked Unlock code is invalid Invalid baud rate setting Invalid stop bit setting Code read protection enabled O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 266 of 290 NXP Semiconductors U M1 0375 Chapter 18 LPC13xx Flash memory programming firmware 13 IAP commands UM10375_0 For in application programming the IAP routine should be called with a word pointer in register r0 pointing to memory RAM containing command code and parameters Result of the IAP command is returned in the result table pointed to by register r1 The user can reuse the command table for result by passing the sa
395. ting 1 in USBPLLUEN see Table 3 19 0x4004 804C register and wait until USB clock source is updated Set USB clock divider register see Table 3 30 address 0x4004 80C8 to 1 meaning the USB clock is divided by 1 as the input is 48 MHz already 11 2 USB device controller initialization 1 Set bits 14 and 16 in the AHBCLKCTRL register see Table 3 23 address 0x40048080 to enable USB and lOConfig blocks The lOConfig is needed to configure lO pin multplexing In the lOConfig block set Port0 3 see Table 5 72 and Port0 6 see Table 5 80 to USB VBUS and USB CONNECT respectively Clear any device interrupts using USBDevintClr Table 9 129 then enable the desired endpoints by setting the corresponding bits in USBDevintEn Table 9 128 4 Install the USB interrupt handler in the NVIC 5 Set the default USB address to 0x0 and DEV_EN to 1 using the SIE Set Address command Set CON bit to 1 to make CONNECT active using the SIE Set Device Status command 12 Functional description UM10375_0 12 1 Data flow from the Host to the Device The USB ATX receives the bi directional USB_ DP and USB_DM lines of the USB bus It will put this data in the unidirectional interface between ATX and USB block The SIE protocol engine receives this serial data and converts it into a parallel data stream The parallel data is sent to the RAM interface which in turn will transfer the data to the endpoint buffer The endpoint buf
396. tly the UOTHR is empty The THRE interrupt is reset when a UOTHR write occurs or a read of the UOIIR occurs and the THRE is the highest interrupt UOIIR 3 1 001 UART FIFO Control Register UOFCR 0x4000 8008 Write Only The UOFCR controls the operation of the UART RX and TX FIFOs Table 159 UART FIFO Control Register UOFCR address 0x4000 8008 Write Only bit description Bit Symbol Value Description Reset value 0 FIFO 0 UART FIFOs are disabled Must not be used in the application 0 Enable Active high enable for both UART Rx and TX FIFOs and UOFCR 7 1 access This bit must be set for proper UART operation Any transition on this bit will automatically clear the UART FIFOs 1 RXFIFO 0 No impact on either of UART FIFOs 0 Reset y Writing a logic 1 to UOFCR 1 will clear all bytes in UART Rx FIFO reset the pointer logic This bit is self clearing 2 TX FIFO 0 No impact on either of UART FIFOs 0 Reset 4 Writing a logic 1 to UOFCR 2 will clear all bytes in UART TX FIFO reset the pointer logic This bit is self clearing Reserved 0 54 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 7 6 RX These two bits determine how many receiver UART FIFO 0 Trigger characters must be written before an interrupt is activated Level 00 Trigger level 0 1 character or 0x01 01 Trigger level 1 4 characters or 0x04 10 Trigger level 2 8 characters or 0x08 11 Trigge
397. to 0 001 Start conversion now 010 Start conversion when the edge selected by bit 27 occurs on PIOO_2 SSEL CT16B0_CAPO 011 Start conversion when the edge selected by bit 27 occurs on PI01_5 DIR CT32B0_CAPO 100 Start conversion when the edge selected by bit 27 occurs on CT32B0_MATO 101 Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1 110 Start conversion when the edge selected by bit 27 occurs on CT16B0_MATO 111 Start conversion when the edge selected by bit 27 occurs on CT16BO_MAT1 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 242 of 290 NXP Semiconductors U M1 0375 Chapter 16 LPC13xx Analog to Digital Converter ADC Table 239 A D Control Register ADOCR address 0x4001 C000 bit description Bit Symbol Value Description Reset Value 27 EDGE This bit is significant only when the START field contains 010 111 In these cases 0 1 Start conversion on a falling edge on the selected CAP MAT signal 0 Start conversion on a rising edge on the selected CAP MAT signal 31 28 Reserved user software should not write ones to reserved bits The value read from a NA reserved bit is not defined 5 2 A D Global Data Register ADOGDR 0x4001 C004 The A D Global Data Register contains the result of the most recent A D conversion This includes the data DONE and Overrun flags and the number of the A D channel to which the data relates Table 240
398. tober 2009 50 of 290 NXP Semiconductors U M1 0375 Chapter 4 LPC13xx Power Management Unit PMU 2 Once the chip has booted read the deep power down flag in the PCON register Table 4 56 to verify that the reset was caused by a wake up event from Deep power down and was not a cold reset 3 Clear the deep power down flag in the PCON register Table 4 56 4 Optional Read the stored data in the general purpose registers Table 4 58 and Table 4 59 5 Set up the PMU for the next Deep power down cycle see Section 4 3 1 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 51 of 290 UM10375 Chapter 5 LPC13xx I O configuration Rev 00 10 19 October 2009 User manual 1 How to read this chapter The implementation of the I O configuration registers varies for different LPC13xx parts and packages See Table 5 60 and Table 5 62 for IOCON registers and register bits which are not used in all parts or packages Table 60 1 O register configuration unused registers and functions Part USB specific functions pins HVQFN33 package reduced pinout LPC1311 USB function in IOCON_PIOO_1 IOCON_PIO2_1 to IOCON_PIO2_11 LPC1313 IOCON_PIO0_3 IOCON_PIOO_6 not IOCON_PIO3_0 IOCON_PIO3_1 used Corresponding register bits are IOCON_PIO3_3 not used reserved LPC1342 IOCON_PIO3_4 and IOCON_PIO3_5 IOCON_PIO2_1 to IOCON_PIO2_11 LPC1343 not used pins used for USB_D
399. tone generators other microcontrollers etc 4 General description UM10375_0 A typical I12C bus configuration is shown in Figure 12 28 Depending on the state of the direction bit R W two types of data transfers are possible on the I2C bus e Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 170 of 290 NXP Semiconductors U M1 0375 4 1 Chapter 12 LPC13xx I2C bus interface with a STOP condition or with a Repeated START condition Since a Repeated START condition is also the beginning of the next serial transfer the 12C bus will not be released The 12C interface is byte oriented and has four operating modes master transmitter mode master receiver mode
400. trl register should be set appropriately and the packet length should be written to the USBTxPlen register On writing this register the data is written to the selected endpoint buffer The data is in little endian format the first byte sent on the USB bus will be the least significant byte of USBTxData USBTxData is a write only register Table 134 USB Transmit Data register USBTxData address 0x4002 001C bit description Bit Symbol Description Reset value 31 0 TX_DATA Transmit Data 0x0000 0000 USB Receive Packet Length register USBRxPLen 0x4002 0020 This gives the number of bytes remaining in the RAM for the current packet being transferred and whether the packet is valid or not This register will get updated at every word that gets transferred to the system The processor can use this register to get the number of bytes to be transferred When the number of bytes reaches zero an end of packet interrupt is generated Table 135 USB Receive Packet Length register USBRxPlen address 0x4002 0020 bit description Bit Symbol Value Description Reset value 9 0 PKT_LNGTH The remaining number of bytes to be read from the 0 currently selected endpoint s buffer When this field decrements to 0 the RxENDPKT bit will be set in USBDevintSt 10 DV Data valid This bit is useful for isochronous endpoints 0 Non isochronous endpoints do not raise an interrupt when an erroneous data packet is received But invalid data packet can
401. trol of the relationship between the resolution of the timer and the maximum time before the timer overflows The Prescale Counter is incremented on every PCLK When it reaches the value stored in the Prescale Register the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK This causes the TC to increment on every PCLK when PR 0 every 2 PCLKs when PR 1 etc 7 6 Match Control Register TMR16BOMCR and TMR16B1MCR The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter The function of each of the bits is shown in Table 13 215 Table 215 Match Control Register TMR16BOMCR address 0x4000 C014 and TMR16B1MCR address 0x4001 0014 bit description Bit Symbol Value Description Reset value 0 MROI 1 Interrupt on MRO an interrupt is generated when MRO matches the value in the TC 0 0 This interrupt is disabled UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 216 of 290 NXP Semiconductors UM10375 Chapter 13 LPC13xx 16 bit counter timer CT16B Table 215 Match Control Register TMR16BOMCR address 0x4000 C014 and TMR16B1MCR address 0x4001 0014 bit description continued Bit Symbol 1 MROR 2 MROS 3 MR1I 4 MR1R 5 MR1S 6 MR2I 7 MR2R 8 MR2S 9 MR3I 10 MR3R 11 MR3S 31 12 Value Description 4 O O O O O O O O 2 O 0 Reset on
402. trumentation Trace Macrocell allows additional software controlled trace 3 Introduction Debug and trace functions are integrated into the ARM Cortex M3 Serial wire debug and trace functions are supported The ARM Cortex M3 is configured to support up to eight breakpoints and four watchpoints 4 Description Debugging with the LPC13xx uses the Serial Wire Debug mode Trace can be done using the Serial Wire Output When the Serial Wire Output is used less data can be traced but it uses no application related pins Note that the trace function available for the ARM Cortex M3 is functionally very different than the trace that was available for previous ARM7 based devices 5 Pin description The tables below indicate the various pin functions related to debug and trace Some of these functions share pins with other functions which therefore may not be used at the same time Trace using the Serial Wire Output has limited bandwidth UM10375_0 NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 274 of 290 NXP Semiconductors U M1 0375 Chapter 19 LPC13xx Serial Wire Debug SWD and trace port Table 285 JTAG pin description Pin Name Type Description TCK Input JTAG Test Clock This pin is the clock for debug logic when in the JTAG debug mode TMS Input JTAG Test Mode Select The TMS pin selects the next state in the TAP state machine TDI Input JTAG Test Data In This is the seria
403. tween Timer and Counter mode and in Counter mode to select the pin and edge s for counting NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 219 of 290 NXP Semiconductors U M1 0375 UM10375_0 7 12 Chapter 13 LPC13xx 16 bit counter timer CT16B When Counter Mode is chosen as a mode of operation the CAP input selected by the CTCR bits 3 2 is sampled on every rising edge of the PCLK clock After comparing two consecutive samples of this CAP input one of the following four events is recognized rising edge falling edge either of edges or no changes in the level of the selected CAP input Only if the identified event occurs and the event corresponds to the one selected by bits 1 0 in the CTCR register will the Timer Counter register be incremented Effective processing of the externally supplied clock to the counter has some limitations Since two successive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input the frequency of the CAP input can not exceed one half of the PCLK clock Consequently duration of the HIGH LOW levels on the same CAP input in this case can not be shorter than 1 2 x PCLK Table 219 Count Control Register TMR16BOCTCR address 0x4000 C070 and TMR16B1CTCR address 0x4001 0070 bit description Bit Symbol Value Description Reset value 1 0 Counter This field selects which rising PCLK edges can increment 00 Timer
404. ual Rev 00 10 19 October 2009 16 of 290 NXP Semiconductors U M1 0375 UM10375_0 Chapter 3 LPC13xx System configuration 5 7 System oscillator control register 5 8 This register configures the frequency range for the system oscillator Table 12 System oscillator control register GYSOSCCTRL address 0x4004 8020 bit description Bit Symbol Value Description Reset value 0 BYPASS Bypass system oscillator 0x0 0 Oscillator is not bypassed 1 Bypass enabled PLL input sys_osc_clk is fed directly from the XTALIN and XTALOUT pins 1 FREQRANGE Determines frequency range for Low power 0x0 oscillator 0 1 20 MHz frequency range 1 15 25 MHz frequency range 31 22 Reserved 0x00 Watchdog oscillator control register This register configures the watchdog oscillator The oscillator consists of an analog anda digital part The analog part contains the oscillator function and generates an analog clock Fclkana With the digital part the analog output clock Fclkana can be divided to the required output clock frequency wdt_osc_clk The analog output frequency Fclkana can be adjusted with the FREQSEL bits between 500 kHz and 3 7 MHz With the digital part Fclkana will be divided divider ratios 2 4 64 to wdt_osc_clk using the DIVSEL bits The output clock frequency of the watchdog oscillator can be calculated as wdt_osc_clk Felkanay 4 pivgeL The reset value of the watchdog oscillator is wdt_osc_clk
405. ues are equal actions can be triggered automatically The action possibilities are to generate an interrupt reset the Timer Counter or stop the timer Actions are controlled by the settings in the MCR register O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 217 of 290 NXP Semiconductors U M1 0375 7 8 Chapter 13 LPC13xx 16 bit counter timer CT16B Capture Control Register TMR16BOCCR and TMR16B1CCR The Capture Control Register is used to control whether the Capture Register is loaded with the value in the Counter timer when the capture event occurs and whether an interrupt is generated by the capture event Setting both the rising and falling bits at the same time is a valid configuration resulting in a capture event for both edges In the description below n represents the Timer number 0 or 1 Table 216 Capture Control Register TMR16BOCCR address 0x4000 C028 and TMR16B1CCR address 0x4001 0028 bit description Bit Symbol Value Description Reset 0 CAPORE 1 1 CAPOFE 1 2 CAPOI 31 3 value Capture on CT16Bn_CAPO rising edge a sequence of 0 then 1 on CT16Bn_CAPO will 0 cause CRO to be loaded with the contents of TC This feature is disabled Capture on CT16Bn_CAPO falling edge a sequence of 1 then 0 on CT16Bn_CAPO will 0 cause CRO to be loaded with the contents of TC This feature is disabled Interrupt on CT16Bn_CAPO event a CRO load due to
406. uest for ISP UART USB and requires special attention Since PIOO_1 is in high impedance mode after reset it is important that the user provides external hardware a pull up resistor or other device to put the pin in a defined state Otherwise unintended entry into ISP mode could occur Remark The sampling of pin PIOO_1 can be disabled through programming flash location 0x0000 02FC see Section 18 11 1 5 Memory map after any reset The boot block is 16 kB in size and is located in the memory region starting from the address Ox1FFF 0000 The boot loader is designed to run from this memory area but both the ISP and IAP software use parts of the on chip RAM The RAM usage is described later in this chapter The interrupt vectors residing in the boot block of the on chip flash memory also become active after reset e the bottom 512 bytes of the boot block are also visible in the memory region starting from the address 0x0000 0000 6 Criterion for Valid User Code UM10375_0 The reserved ARM Cortex M3 exception vector location 7 offset 0x0000 001C in the vector table should contain the 2 s complement of the check sum of table entries 0 through 6 This causes the checksum of the first 8 table entries to be 0 The boot loader code checksums the first 8 locations in sector 0 of the flash If the result is 0 then execution control is transferred to the user code If the signature is not valid the auto baud routine synchronizes wit
407. upt on pin PIOn_x is controlled through register GPIOnIEV 1 Both edges on pin PlOn_x trigger an interrupt 31 12 Reserved GPIO interrupt event register Table 113 GPIOnIEV register GPIOOIEV address 0x5000 800C to GPIO3IEV address 0x5003 800C bit description Bit Symbol Access Value Description Reset value 11 0 JEV R W Selects interrupt on pin x to be triggered rising or 0x00 falling edges x 0 to 11 0 Depending on setting in register GPIOnIS see Table 7 111 Rising edges or HIGH level on pin PIOn_x trigger an interrupt 1 Depending on setting in register GPIOnIS see Table 7 111 falling edges or LOW level on pin PIOn_x trigger an interrupt 31 12 Reserved GPIO interrupt mask register Bits set to HIGH in the GPIOnIE register allow the corresponding pins to trigger their individual interrupts and the combined GPIOnINTR line Clearing a bit disables interrupt triggering on that pin Table 114 GPIOnIE register GPIOOIE address 0x5000 8010 to GPIOSIE address 0x5003 8010 bit description Bit Symbol Access Value Description Reset value 11 0 MASK RW Selects interrupt on pin x to be masked x 0 to 11 0x00 0 Interrupt on pin PlOn_x is masked 1 Interrupt on pin PlOn_x is not masked 31 12 Reserved 3 GPIO raw interrupt status register Bits read HIGH in the GPIOnIRS register reflect the raw prior to masking interrupt status of the corresponding pins indicating that all the
408. urce update enable register SYSTCKCAL address 0x4004 8158 bit USBPLLUEN address 0x4004 804C bit description 22 0200 eee eee 29 COSCHDLON sos paria ek ieee Mee es 20 Table 41 Start logic edge control register 0 STARTAPRPO Table 20 Main clock source select register MAINCLKSEL address 0x4004 8200 bit description 29 address 0x4004 8070 bit description 20 Table 42 Start logic signal enable register 0 STARTERPO Table 21 Main clock source update enable register address 0x4004 8204 bit description 30 MAINCLKUEN address 0x4004 8074 bit Table 43 Start logic reset register 0 STARTRSRPOCLR CESCHPLON 6 2 1 ae nera pra Pea ee ewes 20 address 0x4004 8208 bit description 30 Table 22 System AHB clock divider register Table 44 Start logic status register O STARTSRPO SYSAHBCLKDIV address 0x4004 8078 bit address 0x4004 820C bit description 31 CESCHPUON ceeds a a Kalen es 21 Table 45 Start logic edge control register 1 STARTAPRP1 Table 23 System AHB clock control register address 0x4004 8210 bit description 32 AHBCLKCTRL address 0x4004 8080 bit Table 46 Start logic signal enable register 1 STARTERP1 description sacraro 000 eee ees 21 address 0x4004 8214 bit description 33 Table 24 SSP clock divider register SSPCLKDIV address Table 47 Start logic reset register 1 STARTRSRP1CLR 0x4004 8094 bit description 23 address 0x4004 8218 bit description
409. utes the user application if valid NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 255 of 290 NXP Semiconductors U M1 0375 Chapter 18 LPC13xx Flash memory programming firmware 9 Boot process flowchart RESET INITIALIZE CRP 1 2 3 ENABLED M ENABLE DEBUG WATCHDOG yes FLAG SET USER CODE VALID CRP3 NO_ISP no ENABLED yes ENTER ISP EXECUTE INTERNAL MODE USER CODE PIOO_1 LOW boot from USB LPC134x only USB BOOT PIOO_3 HIGH ENUMERATE AS MSC DEVICE TO PC boot from RUN AUTO BAUD UART AUTO BAUD SUCCESSFUL RECEIVE CRYSTAL FREQUENCY RUN ISP COMMAND HANDLER 1 For details on handling the crystal frequency see Section 18 13 8 2 For details on available ISP commands based on the CRP settings see Section 18 11 USER CODE VALID Fig 54 Boot process flowchart UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 256 of 290 NXP Semiconductors UM10375 Chapter 18 LPC13xx Flash memory programming firmware 10 Sector numbers Some IAP and ISP commands operate on sectors and specify sector numbers The following table shows the correspondence between sector numbers and memory addresses for LPC13xx devices Table 252 LPC13xx flash sectors Sector Sector Address range number size
410. uto baud interrupt clear bit write only 0 accessible 0 Writing a O has no impact 1 Writing a 1 will clear the corresponding interrupt in the UOIIR 9 ABTOIntClr Auto baud time out interrupt clear bit write only 0 accessible 0 Writing a 0 has no impact 1 Writing a 1 will clear the corresponding interrupt in the UOIIR 31 10 NA Reserved user software should not write ones to 0 reserved bits The value read from a reserved bit is not defined Auto baud The UART auto baud function can be used to measure the incoming baud rate based on the AT protocol Hayes command If enabled the auto baud feature will measure the bit time of the receive data stream and set the divisor latch registers UODLM and UODLL accordingly Auto baud is started by setting the UOACR Start bit Auto baud can be stopped by clearing the UOACR Start bit The Start bit will clear once auto baud has finished and reading the bit will return the status of auto baud pending finished Two auto baud measuring modes are available which can be selected by the UOACR Mode bit In Mode 0 the baud rate is measured on two subsequent falling edges of the UART Rx pin the falling edge of the start bit and the falling edge of the least significant bit In Mode 1 the baud rate is measured between the falling edge and the subsequent rising edge of the UART Rx pin the length of the start bit The UOACR AutoRestart bit can be used to automatically restart baud rate measu
411. v 00 10 19 October 2009 214 of 290 NXP Semiconductors U M1 0375 Chapter 13 LPC13xx 16 bit counter timer CT16B Table 212 Register overview 16 bit counter timer 1 CT16B1 base address 0x4001 0000 continued Name Access Address Description Reset offset valuel TMR16BIMCR R W 0x014 Match Control Register MCR The MCR is used to control if an interrupt 0 is generated and if the TC is reset when a Match occurs TMR16B1MRO R W 0x018 Match Register 0 MRO MRO can be enabled through the MCR to reset 0 the TC stop both the TC and PC and or generate an interrupt every time MRO matches the TC TMR16B1MR1 R W 0x01C Match Register 1 MR1 See MRO description TMR16BiMR2 R W 0x020 Match Register 2 MR2 See MRO description TMR16B1MR3 R W 0x024 Match Register 3 MR3 See MRO description TMR16BiCCR R W 0x028 Capture Control Register CCR The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place TMR16B1CRO RO 0x02C Capture Register 0 CRO CRO is loaded with the value of TC when 0 there is an event on the CT16B1_CAPO input TMR16B1EMR R W 0x03C External Match Register EMR The EMR controls the match function 0 and the external match pins CT16B1_MATT 1 0 0x040 reserved 0x06C TMR16B1CTCR R W 0x070 Count Control Register CTCR The CTCR selects between Timer and 0 Counter mode and in Counter mode select
412. wer down mode 45 5 30 CLKOUT clock source update enable register 27 10 6 4 Mode 4 Bypass mode 0 0 45 5 31 CLKOUT clock divider register 27 10 6 5 Mode 5 Direct bypass mode 46 5 32 POR captured PIO status register 0 27 5 33 POR captured PIO status register 1 28 UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 284 of 290 NXP Semiconductors UM10375 Chapter 20 LPC13xx Supplementary information Chapter 4 LPC13xx Power Management Unit PMU 1 Introduction 0 0 cece eee eee 47 2 3 General purpose register 4 0 48 2 Register description 47 3 Functional description 48 2 1 Power control register 47 3 1 Entering Deep power down mode 48 2 2 General purpose registers0to3 47 3 2 Exiting Deep power down mode 48 Chapter 5 LPC13xx I O configuration 1 How to read this chapter 50 3 4 A D mode tout ta 52 2 Introduction rra 50 35 a A ts ipsc E enipe iaa 52 3 General description 50 4 Register description 52 3 1 PI rara 51 41 I O configuration registers IOCON_PIOn 55 3 2 Pin mode cccecccccccceeceeee 51 4 1 1 IOCON SCK location register 79 3 3 Hysteresis annaua 00 cece eee 51 Chapter 6 LPC13xx Interrupt controller
413. will be low to indicate that the PLL is not in lock When the Power down mode is terminated by setting the SYS_PLL_PD or USB_PLL_PD bits to zero the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock Operating modes Table 54 PLL operating modes Mode Description PD bit BYPASS bit DIRECT bit 1 Normal mode 0 0 0 2 Direct CCO mode 0 0 0 3 Power down mode 1 0 x 4 Bypass model x 1 0 5 Direct bypass model x 1 1 1 Analog part of the PLL is powered down automatically Divider ratio programming Post divider O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 44 of 290 NXP Semiconductors U M1 0375 10 6 10 6 1 UM10375_0 Chapter 3 LPC13xx System configuration The division ratio of the post divider is controlled by the PSEL bits The division ratio is two times the value of P selected by PSEL bits as shown in Table 3 8 and Table 3 10 This guarantees an output clock with a 50 duty cycle Feedback divider The feedback divider s division ratio is controlled by the MSEL bits The division ratio between the PLL s output clock and the input clock is the decimal value on MSEL bits plus one as specified in Table 3 8 and Table 3 10 Changing the divider values Changing the divider ratio while the PLL is running is not recommended As there is no way to synchronize the change of the MSEL and PSEL value
414. will get loaded into PDRUNCFG when the chip enters Sleep mode PDAWAKECFG Table 3 50 Selects which analog blocks are powered when the chip wakes up Run from Deep sleep mode The contents of this register will get loaded into PDRUNCFG when the chip exits Deep sleep mode Clock control AHBCLKCTRL Table 3 23 Controls clocks to the ARM Cortex M3 CPU memories and individual Run APB peripherals SYSAHBCLKDIV Table 3 22 Disables or configures the system clock Run SSPCLKDIV Table 3 24 Disables or configures the SSP peripheral clock Run UARTCLKDIV Table 3 25 Disables or configures the UART peripheral clock Run USBCLKDIV Table 3 30 Disables or configures the USB 48 MHz clock Run WDTCLKDIV Table 3 33 Disables or configures the watchdog timer clock Run CLKOUTDIV Table 3 36 Disables or configures the clock on the CLKOUT pin Run Power down modes control PMU PCON Table 4 57 Controls which power down mode is entered Sleep Deep power down UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 40 of 290 NXP Semiconductors U M1 0375 UM10375_0 8 1 8 2 8 3 Chapter 3 LPC13xx System configuration Run mode In Run mode the main clock is enabled and the ARM Cortex M3 core as well as memories and peripherals are clocked by the system clock The AHBCLKCTRL register controls which memories and peripherals are running The system clock frequency can be selected by the AHBCLKDIV register S
415. with optional interrupt generation Reset timer on match with optional interrupt generation Four external outputs corresponding to match registers with the following capabilities Set LOW on match Set HIGH on match Toggle on match Do nothing on match For each timer up to four match registers can be configured as PWM allowing to use up to three match outputs as single edge controlled PWM outputs 4 Description Interval timer for counting internal events Pulse Width Demodulator via capture input Free running timer Pulse Width Modulator via match outputs Each Counter timer is designed to count cycles of the peripheral clock PCLK or an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers Each counter timer also includes one capture input to trap the timer value when an input signal transitions optionally generating an interrupt In PWM mode three match registers can be used to provide a single edge controlled PWM output on the match output pins One match register is used to control the PWM cycle length UM10375_0 O NXP B V 2009 All rights reserved User manual Rev 00 10 19 October 2009 224 of 290 NXP Semiconductors U M1 0375 Chapter 14 LPC13xx 32 bit counter timer CT32B Remark 32 bit counter timer0 CT32B0 and 32 bit counter timer1 CT32B1 are functionally identical except

UM10375

Contents

Download Pdf Manuals

Related Search

Related Contents