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Precision RTL Synthesis Users Manual

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1. I0 ak 25 Design Browser The Design Browser is a graphical representation of the in memory design database and allows you to traverse through the design hierarchy to observe and set constraints such as Input Delay False Path Constraint on ports and Don t Touch attributes on modules You can also use the Design Browser to flatten or preserve the design hierarchy Objects selected and highlighted may also be then that line of code is highlighted in your HDL source code ee 3 Impl pseudorandom impl_ Fe 2 Clocks H E Input Files Siac Ports 3 rE Constraint Files o BA Inputs Trace to Hierarchy A pseudorandom _constrai ofo a y Set Attributes a Script Files 1 Selectand reset H Log File Warnings 6 I i seedi 4 0 B RTL Schematic o E intin porna a Siete sul Port Constraints Port Bus seed 24 0 xX Timing Report highlighted in the schematic viewer Furthermore if the selected object initiates cross probing Right Click Set Input Constraints oF Output Files HE write Y Technology Schematic H Outputs Map All Input Flops onto 10 Re Timing Violation Re Timing Constraints Please select clock i ta Clipboard Re Constraints Repor Clock Name Auto select a BA pseudorandom ed a slins Floorplanner AT silin Tir 3 Enter va E a Pad Report Precision RTL Synthesis Users Manual 2003c Update1 1 5 March 2004 Integrated Creation and Analysis Tools Introduc
2. Click and Sprout the Trace Path You may want to examine the fan in and fan out of a block in more detail Use the menu pick method 1 Select an object in the trace path 2 Right click and select Trace Forward or Trace Backward one or more levels Each time you do this you will see the circuitry around the object grow and grow Use the double click method Double click on a primitive to trace back one level Shift double click on a primitive to trace forward one level 5 14 Precision RTL Synthesis Users Manual 2003c Update 1 March 2004 Viewing a Schematic Using the Find Window Features Using the Find Window Features Conducting a Simple Search for Objects The Find Window allows you to search the in memory database for the name s of one or more objects When the objects are found a list of object pathnames are displayed at the bottom of the window This list is active and by double clicking on a pathname you can view the object in a schematic window The graphic below provides an example of searching the statemachine block of this design for all the inverters entor Graphics Precision RTL Synthesis Find sn ol x l 1 Click ls Window Help _ F x keele je es U 2 Enter Search Criteria NY select search starting paint 3 Select MEISIT 1 E A simplemath main XRTLI a Needle a er cE Clocks Ports 3 Inputs Find Instances Find Fins Find Ports 2
3. Sinplernathsrc Zt This action adds a set_input_delay command to the generated sdc file and applies an Input Delay constraint to the specified port The basic syntax of the set_input_delay command is set_input_delay design lt view_type gt clock lt defined_clock gt lt value gt lt port gt After the action in Figure 3 5 you should see the following command in the Transcript Window and the generated constraint file Precision RTL Synthesis Users Manual 2003c Update 3 11 March 2004 Setting Timing Constraints Setting Constraints and Synthesizing set_input_delay design rtl clock clkl 6 a 3 0 The set_input_delay Command The set_input_delay command applies an Input Delay constraint to the specified input port or instance pin The reference clock must be defined prior to executing this command Input ports are assumed to have undefined Input Delay unless otherwise specified This means that if you don t specify the Input Delay constraints no timing will be checked for input to register paths This can be a handy way to declare False Paths Often a reset input is left unconstrained for this reason For inout bidirectional ports you can specify the Input Delay with the set_input_delay command and specify the Output Delay with the set_output_delay command To describe a path delay from a level sensitive latch you should use the level_sensitive option in the Master Constraint File If the latch 1s positive enable
4. P amp Rintegrator P amp RIntegrator automatically sub invokes vendor backend place and route tools from within Precision RTL Synthesis Currently the following environments are supported Actel Designer Altera MAX PLUS II Altera Quartus II Lattice ispLEVER Lattice ispLEVER ORCA and Xilinx ISE The vendor s backend tools then create a binary program file which is used to 1 6 Precision RTL Synthesis Users Manual 2003c Update March 2004 Introducing Precision RTL Synthesis Documentation Available Online program FPGA and CPLD devices Refer to Chapter 4 Running Physical Implementation for more information on a particular Vendor environment slins VIR TEX AW 40s 44 6 Frequency 10 Project Files Design Hierarchy Flay Project pseudorandom EAF pseudorandom rtlXRTL El a Impl pseudorandom _impl 1 H IE Clocks Er co Input Files E a Ports DE vill pseudorandom hd Warning Et aa Inputs 2i E Constraint Files FE pseudorandom_constraints sdc Script Files Cut e5 Ooi H A seediz4 0 cooled faa File Warnings 6 Infos 9 H E initf4 0 fe B RTL Schematic o E E Outputs ga Technology Schematic T Nets Click to Invoke Jado Toots 7 t al mer ceee a epart si ra Blocks RPT Timing Violation Report H 10 fdlatrg 25 oo REPT Constraints Report E I1 priority encoder 25 EF pseudorandom edf I fram 8 5 a Sailing Floorplanner I4 lFsr_8 A ilins Timing Report fo 15 divide by mn MS xil
5. A Quick Way to Bring Up a Schematic Typically you ll bring up a number of windows as you explore the in memory design The figure below illustrates the quickest way to bring up views on various parts of your design including and RTL schematic a Technology mapped schematic and a Critical Path schematic Figure 5 1 A Quick Way to Bring Up a Schematic ta Statemachine Mentor Graphics Precision RTL Synthesis Design Center File View Tools Window Help aS EERE iin VIRTES L 2V400ce1 44 6 Frequency 100 MHZ ojo Fies Dei Hin E E Project statemachine E A simplemath_top main_XRTL Design Analysis ie Impl statemachine_impl_1 unsaved aj aq Clocks ou 5 J Input Files 2 ai fF Constraint Files Ap DE FF statemachine_constraints sdc Amer Gnas LL Script Files E ia sae EAR IEP E en a Output Files a go Log File Infos i outble Click for RTL Schematic RTL Schematic a oF aso View RTL c ete erie Y Technology Schematic lt q Double Click for Tech a J ee Area Report B 2 gr Timing Report i 5 3 0 E RET Timing Violation Report A Outputs Report Missing Constraints Re Constraints Report Ao yOFg gi statemachine edf tL Nets a on ilins User Constraint File Instances Blacks Eerie Click for Critical Path Schematic H A U1 fstatemachin E Ue fdatapath H E Mets View Critical Path See Instances Precision RTL Synthesis Users Manual 2003c Up
6. Activating an Implementation from the Command Line The following activate_imp1 command example will activate the implementation named uart_top_imp1_1 and discard any unsaved changes in the currently active implementation activate impl impl uart_top_impl_1 discard You can use get_project_imp1s to get a list of all implementations in the current project Copying an Implementation The copy command creates and activates a new implementation that is in exactly the same state as the original implementation The easiest way to make a copy of an implementation 1s to right click on the implementation to be copied and choose Copy Implementation from the popup menu Alternatively click on the Copy Implementation icon in the Design Bar or the File gt 4 14 Precision RTL Synthesis Users Manual 2003c Update March 2004 Managing Projects Using the Project Manager Interactively Copy Implementation pulldown menu item to open the Select Implementation dialog box and choose an implementation to be copied Precision creates a new implementation of the same name as the source implementation but increments the _ lt n gt suffix At the same time a new implementation directory of the new name is created in the Project Folder and all of the files in the source implementation are copied into the new implementation folder The new implementation becomes the active implementation If the currently active implementation has unsaved changes Preci
7. By default the name of a new implementation is composed of the project name with the _impl_ lt n gt suffix where lt n gt is an integer that is incremented to ensure the name is unique within the project A directory is created in the project folder for each implementation The project s temp directory consists of the project name_temp_ lt m gt to identify it as a temp directory and includes a unique number Warning The Precision RTL Synthesis tool cannot track if more than one user is using the same project If two users have the same project open and both are making changes then it is possible that one of the users will lose their changes We recommend that you do not let two users work on the same project at the same time The Precision Temp Directory When working on a project using Precision Synthesis your synthesis design work files output to the implementation folder are not automatically saved to the implementation directory but are held in a temporary directory in the project folder until you save your work using the Save Active Implementation command For more information see Saving the Active Implementation Once you save the implementation the Precision Synthesis tool empties the implementation directory and copies the temp directory into the implementation directory For example if you are working in a project with an implementation named impl_1 Precision stores the information for this implementation in the temp directory
8. compiler Software that are linked into a composite program as an integral part of your compiled computer program provided that you distribute these files only in conjunction with your compiled computer program Mentor Graphics does NOT grant you any right to duplicate or incorporate copies of Mentor Graphics real time operating systems or other ESD Software except those explicitly granted in this section into your products without first signing a separate agreement with Mentor Graphics for such purpose 3 BETA CODE Portions or all of certain Software may contain code for experimental testing and evaluation Beta Code which may not be used without Mentor Graphics explicit authorization Upon Mentor Graphics authorization Mentor Graphics grants to you a temporary nontransferable nonexclusive license for experimental use to test and evaluate the Beta Code without charge for a limited period of time specified by Mentor Graphics This grant and your use of the Beta Code shall not be construed as marketing or offering to sell a license to the Beta Code which Mentor Graphics may choose not to release commercially in any form If Mentor Graphics authorizes you to use the Beta Code you agree to evaluate and test the Beta Code under normal conditions as directed by Mentor Graphics You will contact Mentor Graphics periodically during your use of the Beta Code to discuss any malfunctions or suggested improvements Upon completion of your evalua
9. ns Trace to Hierarchy Optimization Constrajhts Set Attributes M Insert Pad Set Output Constraints Pad Type False Path Constraint he Pint Number Report Timing Map All Output Flops onto J 0 STANDARD LVTTL Sort by name DRIVE 12 m Copy Query Info to Clipboe CLEW RATE stow Port Bus viram Cancel Help Input Directory Sinplenma This action adds a set_output_delay command to the generated sdc file and applies an Output Delay constraint to the specified port The basic syntax of the set_output_delay command is set_output_delay design lt view_type gt clock lt defined_clock gt lt value gt lt port gt After the action in Figure 3 7 you should see the following command in the Transcript Window and the generated constraint file set_output_delay design rtl clock clkl 4 y 7 0 3 14 Precision RTL Synthesis Users Manual 2003c Update March 2004 Setting Constraints and Synthesizing Setting Timing Constraints The set_output_delay Command The set_output_delay command applies and Output Delay constraint to the specified output port or instance pin The reference clock must be defined prior to executing this command Output ports are assumed to have undefined Output Delay unless otherwise specified This means that if you don t specify the Output Delay constraints no timing will be checked for register to output paths For inout bidirectional ports you can
10. FITNESS FOR A PARTICULAR PURPOSE MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL INDIRECT SPECIAL OR CONSEQUENTIAL DAMAGES WHATSOEVER INCLUDING BUT NOT LIMITED TO LOST PROFITS ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED INIT EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES RESTRICTED RIGHTS LEGEND 03 97 U S Government Restricted Rights The SOFTWARE and documentation have been developed entirely at private expense and are commercial computer software provided with restricted rights Use duplication or disclosure by the U S Government or a U S Government subcontractor is subject to the restrictions set forth in the license agreement provided with the software pursuant to DFARS 227 7202 3 a or as set forth in subparagraph c 1 and 2 of the Commercial Computer Software Restricted Rights clause at FAR 52 227 19 as applicable Contractor manufacturer is Mentor Graphics Corporation 8005 S W Boeckman Road Wilsonville Oregon 97070 7777 This is an unpublished work of Mentor Graphics Corporation Table of Contents Table of Contents ABODE EDR Man eins capatccts vey E 1X Chapter 1 Introducing Precision RTL Synthesis 00 0 0 cccessesssesceeeeeecceeeeeeeeeeeaeaaasassssesseesseseeeeees 1 1 Peccon RIL a irc acca terrirsaneressancanessecccasnspanenenieattaciammeateeet A hi eis E nanni l 1 eE T 2 ocean ene ree E EA l 1 a D T e EAA EE ETA AEETI EE
11. Once you save the implementation Precision Synthesis copies the contents from the temp directory to impl_1 4 6 Precision RTL Synthesis Users Manual 2003c Update March 2004 Managing Projects Using the Project Manager Interactively The sdc and log files are always updated and current However the database file xdb is only written after synthesis and the 1xdb is only written after a compile Because of the how files are written you should always save after the synthesis and compile steps Temp Directories The tool contains a preference that determines whether new projects use temp directories When a new project is created the preference is stored in the psp file as a project property When the project is loaded the value is read and used to determine whether to use temp dirs when impls are activated The default is that projects use temp directories If you do not want the project to use a temp directory use the following command set_project_property usetempdir value false Use the following command to set the global preference for new projects set_preference pref project usetempdir value true Turning Off the Temp Directory You can turn off the option that causes the Precision RTL Synthesis tool to save to the temp directory Large projects can take a long time to save you can turn off saving to the temp directory by issuing the following global preference command The set_preference command sets all new proj
12. You must explicitly activate or create another implementation If you close the project with no active implementation it will be restored in the same state when reopened Deleting an Implementation from the Command Line The delete_imp1 command deletes the specified implementation If no implementation is specified the active implementation is deleted The following command example deletes the implementation uart_xilinx Note that Precision does not prompt you to confirm the delete command when executed from the command line delete_impl impl uart_xilinx You can use get_project_imp1s to get a list of all implementation in the current project Creating a Script from a Precision log File A quick way to create a preliminary script is to convert the current session log file into a Tcl command file First open the Precision Transcript window then choose the File gt Save Command File pulldown menu In the dialog box specify the name of the script to be created and click OK Precision takes the contents of the current session log file removes all lines that are not commands and saves the results in the named file You can also invoke a log file as a script from the command line The following 2 examples show how to invoke the session log file and an implementation log file dofile lt project_dir gt precision log dofile lt project_dir impl_dir gt precision log You can run this file by opening the Precision Transcript window and
13. that any constraints entered this way will not be saved to the generated sdc file If you want to save one of these constraints for the next synthesis run you must manually type the constraint directly into the Master Constraint File Adding a Xilinx UCF File to the Input File List Precision Synthesis has the ability to read the timing constraints from a Xilinx UCF file and apply those constraints to the in memory design This is handy for example if you have a design that was generated by another synthesis tool and you have timing constraints that are expressed in Xilinx UCF format You can include only one UCF file in the Input File List and to read the UCF timing constraints you must remove the Excluded attribute from the file as shown in the figure below The procedure is to right click on the file from the Design Browser and select Properties Click off the Precision RTL Synthesis Users Manual 2003c Update 2 17 March 2004 Synthesizing the Design Setting Up a Design and Compiling Exclude file from Compile Phase then click OK When the Design is compiled the UCF timing constraints will be applied to the in memory design Figure 2 3 Preparing the Input UCF File colli pecularaulene Yhd 1 Right click and Constraint Files i r ag Ennan select Properties E Script Files E lt Outout Input File Properties Full Path fo Design src pseudorandom uct M Exclude file from Compile Phas
14. y siinz Mapping Report oo Xilinx User Constraint File wo vilin DLY File Input Files Bypassing the Project Manager As mentioned earlier Precision s Project Manager is well suited for interactive sessions in which you are exploring and trying multiple versions implementations of the same design In other situations you might prefer to run Precision without using the Project Manager Bypassing the Project Manager is desirable when you are using scripted flows in which a known set of inputs and the outputs of a single pass are all that is required For example if you are using Precision to automatically setup a known design and generate output files for downstream tools You can work interactively without the Project Manager by entering commands at the shell command line or the Precision Transcript command line However the Design Center GUI window will not be available Also you will be responsible for managing all of the input and output files of your synthesis work To bypass the Project Manager simply set the results directory by calling the set_results_dir command All Project Manager commands will be unavailable until the results directory is unset by the close_results_dir command After the results directory is 4 2 Precision RTL Synthesis Users Manual 2003c Update 1 March 2004 Managing Projects Using the Project Manager Interactively set you can proceed with your synthesis flow setup the design compile synthesi
15. 2003c Update 1 March 2004 Setting Constraints and Synthesizing Setting Timing Constraints Setting Input Delay from the GUI To specify Input Delay on an input port using the GUI follow the steps in Figure 3 5 Figure 3 5 Setting Input Delay from the GUI la x leaa e U Timing Constraints Please select clock alins VIRTESL A 40c 44 6 Frequency 100 M Slat Heme cik Design Hierarchy Input Delay lq riz t statemachine F a _top fmain pl statemachine_impl 1 Output Delay Input Files pij datapath vhd E Ports E a poet Kil tapana o T Infa i1 ES Inputs M Rising Edge Select an Input T 3 Enter value vi Soll port and right click TF Ofset Constraint Files E statemachine_constraints sde i Set False Path from E statemachine_constraints sdc og EE E c3 a I Set Multi Cycle Path fran cycles J Script Files 2 Select o E La d 3 0 y Output Files ae M Sethin Delay 4 Click rig l Trace to a hod Log File Infos 7 i Set Max Dela ae EBJ RTL Schematic Set Attributes m Ins Rel Constraints Report Set Input Constraints False Path Constraint Report Timing IW Insert Pad Pad Type Map All Input Flops onto Ii Pin Number Optimization Constraints Sort by name Copy Query Info to Clipbo g STANDARD LVTTL Port Bus ata ror DAME mA Fri E m rir K Cancel Help Pg Design Center Tt Directory
16. Harness Capital Harness Systems Capital Insight Capital Integration Capital Manager Capital Manufacture Capital Support Capital Systems Capture Station Celaro Cell Builder Cell Station CellPloor CellGen CellGraph Cell Place CellPower CellRoute Centricity CEOC Chase X Check Mate CHEOS Chip Station ChipGraph ChipLister Circuit PathFinder Co Veri fication Environment COLsim Code lab CommLib CommLib BMC Concurrent Design Environment Connectivity Dataport Continuum Continuum Power Analyst Core Alliance CoreBIST Core Builder Core Factory CTI ntegrator DataCentric Model DataFusion Datapath Data Solvent BUG Debug Detective DC Analyzer Deltacore DeltaV Design Architect Design Architect 1C Design Architect Elite Design Capture Design Exchange Design Manager Design Station DesignBook Design View DesktopASIC Destination PCB Destiny RE DPTAdvisor DPTArchitect DFTInsight DMS Xchange DxAnalog DxDataBook DxDesigner DxLibraryStudio DxParts Dx PDF Dx ViewOnly Dx VariantManager Direct System Verification DSW Documentation Station DSS Decision Support System Dx Analog Dx DataManager Dx Designer Dx Enterprise for Agile DxMatrix Dx ViewDraw ESLcable EDA Tech ForumEDT Eldo EldoNet ePartners EPartsi EPlanner EProduct Designer EProduct Services Empowering Solutions Engineer s Desktop EngineerView Enterprise Librarian ENRead EN Write EsSim Exemplar Exemp
17. IO Pad Scenarios ssec tease rsceistencsvanssnnnenceannneiamsastonnnciciwsateasiceess 3 19 Table 3 3 Handling Different Clock Buffering Scenarios ssssssssseseessssssosererssssssseceresssss 3 21 Table 4 1 Deprecated Ge cca ancncernnesscsaaaessapinannacasatasiamateantntasinasienntesstineeatesentasnanntenss 4 21 Precision RTL Synthesis Users Manual 2003c Update1 vii March 2004 Table of Contents List of Tables cont vill Precision RTL Synthesis Users Manual 2003c Update March 2004 About This Manual Precision RTL Synthesis is a comprehensive tool suite providing design capture in the form of VHDL and Verilog entry advanced register transfer level logic synthesis constraint based optimization state of the art timing analysis schematic viewing and encapsulated place and route This manual describes the synthesis design process using the Precision RTL Synthesis Graphical User Interface GUI and provides information on how to perform synthesis tasks and analysis procedures Precision RTL Synthesis Users Manual 2003c Updatet Ix March 2004 About This Manual Precision RTL Synthesis Users Manual 2003c Update March 2004 Chapter 1 Introducing Precision RTL Synthesis Precision RTL Synthesis is a synthesis platform the maximizes the performance of both existing programmable logic devices CPLDs and FPGAs and next generation multi million gate field programmable system on chip FPSoC devices Precision RTL
18. Navigate to and select a source file s then click Open 2 6 Precision RTL Synthesis Users Manual 2003c Update March 2004 Setting Up a Design and Compiling Setting up the Design Environment Since Precision analyzes all of the files in the input file list together the order that you add the files is usually not important Precision RTL Synthesis will auto detect the top level If your design files reference a standard library or package such as an IEEE library then Precision RTL Synthesis will automatically open and load that library or package file which is located in the lt precision install directory gt pkgs techdata vhdl directory If you include Xilinx Coregen files in this list Precision will read the coregen block and mark it as a dont_touch block so Precision will not optimize it but will consider it for fanout and timing analysis For more information refer to Including Xilinx Coregen Generated Modules in the Precision Synthesis Reference Manual 3 optional Adjust the file type by right clicking on the file name and selecting Properties Precision detects the file type based on the file extension Valid values are vhdl vhd vhG Verilog V lt V76 se0dit edit edn edf syn tcl xni xdb and sdf If a file does not use a valid extension then you can use this form to specify the file type 4 Apply the Add Input Files setting by clicking on the Apply button This dialog box may execute a seri
19. Places INFOR M IFX Inexia Innovate PCB Innoveda Integrated Product Development Integra Station Integration Tool Kit IT INTELLITEST Interactive LAYOUT Interconnect Table Interface Based Design IB Inventra Inventra IPX Inventra Soft Cores IP Engine IF Evaluation Kit IP Factory IP PCB IP QuickUse PSim 15 Analyzer 15 Floorplanner 1S MultiBoard IS Optimizer IS Synthesizer iSolve IV locity Language Neutral Licensing Latium LAYOUT LNL LBIST LBISTArchitect Le Lcore Leaf Cell Toolkit Led LED Layout Leonardo Leonardolnsight LeonardoSpectrum Librarian Library Builder LineSim Logic Analyzer on a Chip Logic Builder Logical Cable LogicLib logio Lsim Lsim DSM Lsim Gate LsimNet Lsim Power Analyst Lsim Review Lsim Switch Lsim XL Mach PA Mach TA Manu factureView Manufacturing Advisor Manufacturing Cable MaskCompose MaskKPE MBIST MBISTArchitect MBIST Full Speed MBISTFlex MBIST In Place MBIST Manager MCM Designer MCM Station MOV MeeaFunction Memory Builder Memory Builder Conductor Memory Builder Mozart Memory Designer Memory Model Builder Mentor Mentor Graphics MicroPlan MicroRoute Microtec Mixed Signal Pro ModelEditor ModelSim ModelSim LN ModelSim VHDL ModelSim VLOG ModelSim SE ModelStation Model Technology Model Viewer Model ViewerPlus MODGEN Monet Mslab Msview MS Analyzer MSArchitect MS Ex press MSIMON Nanokernal NetCheck NETED Nucleus
20. Style Guide for more information on how to set these options Setting Output Options Precision saves the output netlists for the implementation tools along with area and timing reports in the current implementation directory These file are also listed in the Project File pane of the Design Center window By default the base name leaf name of the generated output file is taken from the name of the last HDL input file to be read You can change this name by specifying a new name from the pulldown menu Tools gt Set Options gt Output gt Output File Base Name Generating Output Files in Different Formats If you need Precision RTL Synthesis to generate additional netlists e g an HDL netlist for simulation you need to set this additional output netlist option from the pulldown menu Tools gt Set Options gt Output A separate file is generated for each type that is selected EDIF Verilog VHDL 2 12 Precision RTL Synthesis Users Manual 2003c Update 1 March 2004 Setting Up a Design and Compiling Compiling the Design Compiling the Design Once you have specified the target technology and your source HDL files Precision RTL Synthesis can compile the design into a technology independent implementation To compile your design click on the Compile icon in the Design Bar If the Compile icon does not appear verify that you on using the Design Center tab and that you have specified a target technology in the design set
21. Update1 5 3 March 2004 Viewing the Critical Path Schematic Viewing a Schematic Viewing the Critical Path Schematic After Synthesis you may also view a Critical Path Schematic by clicking on the Critical Path icon in the Design Analysis pane of the Design Bar Figure 5 4 Viewing the Critical Path Schematic F simplemath main a Clocks A clk HS Ports AG Inputs MU YLL Ai Mets MERR MUXCY_L 5 Instances H Flip Flops 5 I0 Pads LO Primitives B Cl m A Outputs ili oO Go Lah ln Li cl 2 yr i _ ey 5 4 Precision RTL Synthesis Users Manual 2003c Update 1 March 2004 Viewing a Schematic Understanding the Left Mouse Button Actions Understanding the Left Mouse Button Actions ZOOM TO AREA Left Click Drag release draws bounding box to zoom in on SELECT OBJECT Left Click on Object selects and highlights a single object like instance net pin port SELECT AREA SHIFT Left Click Drag and Release selects all non filtered objects in the bounding box UNSELECT ALL Left Click in Window not on an object UNSELECT OBJECT SHIFT Left Click on Object unselects a single object without unselecting others Traversing the Schematic with Strokes You can click on the Design Bar icons to accomplish many of the actions described in this section However many people find strokes the fastest and most convenient method of traversing a schematic A stroke is an action where you press the Left Mouse Butt
22. are automatically saved in the Precision generated sdc file The constraints are later reapplied to subsequent compile synthesis iterations NOTE For the purpose maintaining the integrity of the sac file only constraint settings applied to the in memory RTL design are saved to the sac file If you add or edit constraints on the gate level in memory design your changes are applied to the design but not saved in the sdc file Based on this policy the Design Hierarchy pane of the Design Center window always displays the RTL design Additionally all of the constraint related commands now provide the design option This option takes one of two arguments rt1 or gatelevel that specifies the design file to which the constraint will be applied The default value is rt1 Although setting constraints can be as simple as specifying a target design frequency or as powerful as indicating several multi cycle paths at a minimum you should define the clock period on every detected clock pin Precision displays these clocks in the right side of the Design Center By default Precision does not check timing paths from inputs to registers or registers to outputs unless you specify timing constraints on the top level input and output ports NOTE As defined by the industry standard SDC format since timing constraints must be set relative to defined clocks you must specify your clocks prior to applying any other timing constraints Clocks Overvie
23. depending on where you are in the flow and reveal the possible next steps 2 2 Precision RTL Synthesis Users Manual 2003c Update 1 March 2004 Setting Up a Design and Compiling Setting up the Design Environment Figure 2 1 The Design Center Window ft wart top Mentor Graphics Precision RTL Synthesis Design Center P iol x Fie wiew Tools Window Help x slins VIRTE I 2 40cs144 6 Frequency 100 MHZ Froject Files M Design Hierarchie Editor _ design A Input Files fo Bae vil address decode y ae i clock divider Pee ei uart_top Baw ei mit _rc _controly a e Constraint Files i AR Wart bop constraints sde C Script Files a Output Files NE bit plof Log File Warnings 1 I Setup Design AO Ae oe RTL Schematic ERS 1 Control the RRP Constraints Report o a Compie B Design anatysis Transcript_ 4 Design Cen 2 Manage the constraints roject fil a project es Set Input Directo Add Input Files T addri 0 J data int 0 4 a Outputs Input Directory Cis 2 The following list shows some hints for using the Precision GUI If you don t know what to do try right clicking on a folder file or object The Design Center window is right click driven Right clicking on the folders and files in the Project Files pane will pop up a menu of commands specific
24. designs The proper handling of multiple clocks is a major feature of Precision RTL Synthesis For clocks of different frequency Precision finds the clock period where the clocks most closely approach each other The timing report shows the clock period where this occurs when reporting violations For example worst case timing might be found at the 3rd rising edge of the source clock and the 6th rising edge of the destination clock In general the greatest common divisor of the 2 clock periods is usually the clock period used for analysis Clocks without small integer common multiples are probably not related and any paths between these clocks are probably false paths If there is no guaranteed timing relationship between them then Precision considers the clocks to be asynchronous or in different clock domains Generally this occurs when clocks are driven by different oscillators Two clocks in different domains may have exactly the same frequency may have identical latencies etc but they cannot be analyzed because there is no common zero point to which these edges and latencies are measured By default Precision places these clocks in different domains Since SDC does not support the concept of clock domains Precision RTL Synthesis has added a switch to the create_clock command to model this behavior See the following syntax create_clock period lt value gt name lt value gt domain lt domain_name gt The lt domain_name g
25. effective register balancing algorithm This algorithm is disabled by default in RTL synthesis and enabled by default in physical synthesis To enable retiming in the entire design setup_design retiming true Retiming will affect the observability of internal registers If observability of a particular internal register is an issue then set a don t_retime attribute on those specific registers For example set_attribute name DONT_RETIME value TRUE instance Ul reg_pipe Incorrect constraints Typically setting the input output constraints incorrectly may over constrain the design such that Precision reports a negative slack that can never be corrected Setting constraints incorrectly is usually the result of not understanding the relationship between Input Delay and setup time as shown in Figure 2 1 Basically the Input Delay is defined with respect to the first clock edge and the setup time is defined with respect to the last edge of one clock cycle The difference delta between these two times is the delay available for the circuit When this delta is zero or when the times overlap Precision reports an un correctable negative slack Figure 2 1 The Constraint Relationship LL 0 l 100 Inputs gt Input Delay g ______ Delta Setup Fine tune constraints Refine the constraints to meet the real world conditions of the complete design Flatten blocks If the area
26. enemies 5 9 viewing the Internals of a Hierarchy BIOK qaeeenaenee nn nenr eunTeyentn irae e Caer never Teese rs rtrnemen tren nr 5 10 Traversing the Schematic Using Keyboard shortcuts iccissiccscicescisvassssessesecersienssesercuertoreaseevciess 5 11 emne me Cross Frobe Pei i seseina oon mn nen ne Tree ER 5 12 Cross Probing from Schematic to the HDL Source nssesesosoneesessssessreesssssssssereessssssesses 5 12 Cross Probing to HDL Designer from Precision RTL Synthesis eneesssoeeeeesssssssesereees 5 12 Yenne ee T aE A a Sete e vt Tene net DEn TTC ene ve ane ter ery ee nom 5 13 ier Tere be 6 NATET nee te nee ere eat AAEE ATIAEINA TEPPE ETS ree irae re rt er 5 13 Oe eateries ENEE E AEE A O E 5 14 Giek and Sprout tme Tae PA ss sescceeccessnqnsntasnsnaneenncesaeensnasttasensexenssananeeeoatannasssasitaaentinensatns 5 14 Ume wo rimad V indow Poari anasiri iA 5 15 Condociny a Simpie Scarch T0 Ob o airnn n nena sinr rene en Ren nt eer er kEi iane SES 5 15 Searching tor Objects Using RKegular Expressi usrsissirnnid 5 16 sona CR VEn IDE Up OOS scerriiorerreiriarni iran EEEE EEE A 5 18 Loderstmmdins he Temi ser Sng saererirersnridr r E E EN 5 18 Viewing Bundled Instances and Net Buses ccccccccccccesssessececeecccaaeeseeecceeeeeaaeensneeeeess 5 19 Ara the Schematic Printing Dermilessssiscisrsiriieiionisns a i 5 19 Changing the Way 5ymbols are Handled esscrinsacicenidnredidnr 5 20 Changing the Placement of Output De
27. in the VHDL or Verilog code IRL BURG GCuK PAD gt rd gt Cock Distribution Gisk nA Note The actual cell inserted is a BUFGP which is equivalent to an IBUFG and a BUFG combination in Virtex II 3 20 Precision RTL Synthesis Users Manual 2003c Update 1 March 2004 Setting Constraints and Synthesizing Setting Other Constraints After viewing the Area Report and the transcript you can determine how many and where the clock buffers were used If you have some global buffers still available you can use the buffer_sig attribute to specify a hierarchical net pathname s These attributes should be added to your design constraint sac file so that you can consistently reproduce the results Table 3 3 Handling Different Clock Buffering Scenarios To assign a clock buffer toa A Select a clock port in the Design Hierarchy pane top level port or internal net or the Schematic Viewer right click and select Set Clock Constraints Select one of the options from the Clock Buffer dialog box B Attach a buf fer_sig attribute to a top level port net or internal net with a value of the global buffer name Mapping Operators Counters and Memory to Chip Resources Although you can instantiate technology specific modules into your HDL source code Precision RTL Synthesis has a module generator called Modgen that creates efficient technology specific implementations of arithmetic and relational operators counters and memory RAM an
28. included in Precision for efficiency and serves as more intuitive way to describe purely asynchronous clocks clocks that do not interact 3 8 Precision RTL Synthesis Users Manual 2003c Update1 March 2004 Setting Constraints and Synthesizing Setting Timing Constraints The Clock Constraint dialog box adds a create_clock command to the generated sdc file and applies the constraint to the specified input port or instance pin in the in memory design The basic syntax of the create_clock constraint 1s create_clock design lt view_type gt name lt clock_name gt period lt value gt waveform lt edge_list gt lt port_list gt Using Figure 3 2 as an example the logic between FF1 and FF2 is constrained to one clock period If the clock period is 10ns then the Logic Cloud has approximately 10ns minus the clk to D timing arc of FF1 and the setup constraint of FF2 to meet timing Therefore to accurately define the clock you must apply the following constraint gt create_clock design rit name sysclk period 10 clk If you are entering the create_clock command directly into the Master Constraint File you can use the find_clocks command to quickly define all clocks in the design before you have time to determine whether they may be driven by other logic e g clock dividers For example gt create_clock design rit name sysclk period 10 find_clocks Handling Multiple Clocks Multiple clocks are common in today s circuit
29. open a project if a results directory is currently set Setting the Results Directory You set the location of the results directory by calling the set_results_dir command This command is not available if a project is already open Within scripts it must be the first command called in order for Precision to run without using the Project Manager When the results directory is set no Project Manager commands are available until you call the close_results_ dir command Setting the Input Directory The input directory is the location where Precision will look for input files by default The input directory can be independent of the project directory When you ask Precision to access an input file you can give it the full pathname of the file or a partial pathname If you specify a partial pathname that pathname must be relative to the input directory In other words the full path to the file must be equivalent to the combination of the input directory path and the partial file path lt input_dir gt lt partial_path gt You can change the input directory at any time either from the GUI or by calling the set_input_dir command Resetting the input directory while you are working in Precision can be a useful strategy For example you can create multiple input directories that contains variations of the same set of input files Then you can easily switch back and forth as you experiment For this strategy to work all of the input files that hav
30. results are acceptable begin to flatten hierarchical blocks in order to improve timing results on subsequent synthesis runs Turn off resource sharing If you have a large operator in the critical path that is resource shared try turning off resource sharing Click off the radio button Tools gt Set Options Input gt Resource Sharing and click Synthesize again The additional operators may increase the area but the eliminated mux circuitry may solve the timing problem Precision RTL Synthesis Users Manual 2003c Update 2 21 March 2004 Performing Initial Place and Route Setting Up a Design and Compiling Return to the HDL source design and re implement You might have to re design a critical path in the HDL source in order to create a parallel faster design or you may have to increase the latency of the path by a cycle or two Switch speed grades Last check with your vendor to determine if there is a faster version of the chip available that represents a higher performance technology Determining the Next Step If your design meets the specified performance requirements then move on to Place amp Route If your design is still not meeting performance requirements you can either loosen the timing constraints or select the Register Retiming option and re run Synthesis If you are within 10 of your timing goals you may want to run the design through the physical implementation tools to get accurate post place route timing
31. should follow these steps if you have moved the project location input directory or input files If the Project Directory Moves If you move the project but the input directory has not moved then browse to the new project directory using File gt Open from within the Precision Synthesis tool The project opens and the files are accessible If the Input Directory Moves If you move the input directory the Precision RTL Synthesis tool displays with the files greyed out inaccessible Select File gt Set Input Directory from the File menu to set the new location for the input directory All relative file paths will now be relative to this new location and Precision will resolve all input files automatically If the Input Files Move If the input file has been moved or renamed it will display greyed out If you hover over a file the tool displays the message file cannot be found Remove the file by selecting it right clicking to display a menu and then select Remove File Click the Add Input Files icon to browse to the desired input file location and select the file When the project is completed the Precision RTL Synthesis tool automatically saves the project input directory and input files to the new locations We recommend that you save the implementation after changing the input directory or removing then adding an input file 4 20 Precision RTL Synthesis Users Manual 2003c Update March 2004 Managing Proje
32. synthesis process and onto the physical implementation tools Work Library Specifies the name of the work library for compiling the content of the VHDL file If not specified then the work library name work is assumed 2 8 Precision RTL Synthesis Users Manual 2003c Update March 2004 Setting Up a Design and Compiling Setting up the Design Environment Include File Search Path Specifies additional directories that are pre pended to the global search path that is specified from the pulldown menu Tools gt Set Options gt Input Searching for Verilog include Files If a Verilog file is being added and additional files are referenced via the include directive then the search for the include file is conducted in the following order 1 The directory of the file that specifies the include directive 2 The directories that are specified for this file in the Input File Properties dialog box 3 The directories that are specified for global searches in the pulldown menu Tools gt Set Options Input Assume for example that the file being added is located in the directory F design src and this search path is set to the following Cr my_include files F more include tiles During the compile operation for this file Precision RTL Synthesis first searches for any specified include files starting in directory F design src then C my_include_files then directory F more_include_files If the file is no
33. 00 Height f 1 MW Show Bundled Instances Landscape IY Show Net Buses f Portrait Name Enter a file pathname Fitpage Browse 4 Enter a file pathname to save the schematic to a file Precision RTL Synthesis Users Manual 2003c Update 5 19 March 2004 Setting Schematic Viewing Options Viewing a Schematic Changing the Way Symbols are Handled The Symbol handling options allow you to control the viewers ability to do the following Permute pins Switch the placement of pins on a symbol to reduce net congestion The default is true You may want to turn this off if you are using a symbol standard that doesn t allow the changing of pin positions lO buffer Specifies that IO buffers should be placed in the outside edges of the schematic sheet The default is true Changing the Placement of Output Devices The Feedback levels dialog controls the placement of output devices on the right side of the schematic sheet Forcing output devices to the right side may make the schematic easier to read but may also increase the page count of a multi page schematic Output Specifies the number of logic levels from the right side where output drivers components directly connected to an output connector are placed The number of levels can be specified from 0 to 500 and defaults to 2 Latch Specifies the number of logic levels from the right side where latches are placed The number of levels defaults to 100 effec
34. 04 Chapter 4 Managing Projects Performing FPGA synthesis can be an iterative process where constraints and optimization settings are constantly adjusted until the desired result 1s achieved Each of these iterations will generate a result based on a specific set of inputs constraints and synthesis options When you perform these iterations often you will save multiple versions of your design for future reference Precision Synthesis includes the Project Manager to help you manage the data created during the iterative synthesis process The Project Manager The Project Manager offers a framework that supports and promotes a design process based on experimentation The Project Manager system is based on projects which contain multiple implementations Each implementation within a project is a separate workspace in which you can experiment with different synthesis strategies and configurations Implementations keep track of all of the design settings input files and output files that comprise its configuration The Project Manager facilitates your design efforts by allowing you to create delete copy edit and save implementations After creating a project and its implementation s proceed with your synthesis design flow Before closing the project save the current state of the active implementation Then the next time you open the project it will be restored to the state it was in when you closed it The Project Manager is accessible in al
35. 20 Don t over constrain paths Precision RTL Synthesis will spend a lot of CPU time trying to obtain an impossible goal while greatly increasing the size of the design Check for asynchronous signals exist on the critical path Asynchronous signals such as set or reset cause negative slack because they typically arrive well before the data to the synchronous device is available for clocking Examine your timing report for the following statement with the Source or Dest fields in order to determine the existence of asynchronous signals Combinational path through sequential primitive Probably an asynchronous set reset Since asynchronous signals are usually connected to external ports you can correct the negative slack by setting the input constraint on the port to 1 clock cycle e g 100ns Then the asynchronous signal is a static value 1 clock cycle before the input to the synchronous device is available Multi cycle paths exist on the critical path You can detect multi cycle paths in timing reports by observing a negative slack value that is greater than the clock cycle You will also notice that the path starts with and ends with a synchronous device Examine the type of logic boolean or operators Effective use of operators Check fanout Precision RTL Synthesis Users Manual 2003c Update March 2004 Setting Up a Design and Compiling Synthesizing the Design Consider using Retiming Precision includes a highly
36. Compile phase 2 8 Exporting your Settings 4 20 F False Paths setting constraints 3 15 false_path attribute 3 16 Fastest Design strategy for obtaining 2 20 Files sdc 2 4 ucf 2 17 in the project directory 4 5 passing from input to output 2 8 Find Window simple search 5 15 Finding Objects using regular expressions 5 16 FSM encoding 2 12 safe 2 12 FSM Options 2 12 Full Case Verilog 2 11 G Generating Reports 2 20 2 22 get_lib_ports command 2 15 Global Buffers 3 20 H help online 1 7 hierarchy attribute 3 19 I I O Mapping 3 18 IEEE Libraries auto loading 2 10 Implementation Index 2 Index Index cont Activating 4 14 Commenting 4 15 Copying 4 14 Creating 4 10 Deleting 4 17 Renaming 4 13 Saving 4 11 Include Files specifying search path for 2 9 Verilog 2 11 Inferring counters 3 21 operators 3 21 pipelined multipliers 3 21 Input Delay constraint 3 11 setting the global default 2 6 Input Directory Moves 4 20 Input Files adding to the project 2 6 excluding from Compile phase 2 8 specifying properties of 2 8 types 2 8 Input Files Move 4 20 Interactive Command Line Shell how to bring up 2 3 Introducing 1 1 L Latches transparent 2 14 Library Clauses 2 10 Loading a technology library 2 5 LogicLock mapping blocks to regions 3 21 M Mapping I O mapping 3 18 Precision RTL Synthesis Users Manual 2003c Update Mar
37. Features Viewing a Schematic Using the Cross Probe Features Cross Probing from Schematic to the HDL Source l 2 Select an object on the schematic like an INV instance Right click then select Trace to HDL Source The HDL source comes up highlighted in an edit window At this point you can edit the source save and re Read the file to correct errors If changes cause the schematic to be grayed out just click in the Schematic window right click then select Reload Schematic NOTE Not all objects initiate cross probing The following is a list of objects that do initiate cross probing l Zz Instances IF statements and Conditional Signal Assignment CASE statements and selected signal assignment Expressions with arithmetic boolean or logical operators Declaration statements Procedure calls Variable array indexing Cross Probing to HDL Designer from Precision RTL Synthesis l 2 5 12 Open a schematic in Precision RTL Synthesis that was created in HDL Designer Click on an instance and from the RMB menu select Trace to HDL Designer The same instance will highlight in the HDL Designer schematic Precision RTL Synthesis Users Manual 2003c Update1 March 2004 Viewing a Schematic Viewing Schematic Fragments Viewing Schematic Fragments Tracing a Signal Schematic viewing allows you to select a signal and trace that signal forward or backward through one or more levels of instances Once trac
38. Nucleus All You Need Opsim OutNet P amp RIntegrator PACKAGE PADS PARADE ParallelRoute Autocells ParallelRoute MicroRoute Parts SpeciaList PathLink PCB Gen PCB Generator PCB IGES PCB Mechanical Interface POLSim PE GMAC PE MAC Personal Learning Program Physical Cable Physical Test Manager SITE PLA Lcompiler Platform Express PX PLDSynthesis PLD Synthesis I Power Analyst Power Analyst Station Power To Create PowerLogic PowerPCB Precision Pre Silicon ProjectXpert ProtoBoard ProtoView QDS QO Net QualityIBIS QuickCheck QuickFault QuickConnect QuickGrade QuickKHDL QuickKHDL Express QuickHDL Pro QuickPart Builder QuickPart Tables QuickParts QuickPath QuickSim QuickStart QuickUse QuickUse Development System QuickVHDL Quiet Quiet Ex pert RAM Lcompiler RC Delay RC Reduction RapidEx pert REAL Time Solutions Registrar Reliability Advisor Reliability Manager REMEDI Renoir RF Architect RF Gateway RISE ROM Lcompiler RTL X Press Satellite PCB Station scaleable Models Scaleable Verification SCAP Scan Sequential Scepter Scepter DFF Schematic View Compiler SVC Schemgen SDF Software Data Formatter SDL2000 Leompiler Seamless Seamless ASAP Seamless C Bridge Selective Promotion Sheet Planner Signal Spy Signal Vision SignaMask OPC Signature Synthesis Simulation Manager SimPilot SimView Smartgrid SmartMask SmartParts SmartRouter SmartScripts Smartshape SNX SneakPath Analyzer
39. Outputs Find Nets F E Mets E Instances Case Sensitive Sia Flip Flops Match whole word only o H 0 reg_add_reg 0 Regular Expression J reg_mul_regt7 0 T reg_sub_regi3 0 Operators I Object Path Object Type Description w19 1 1159 Instance ma UT etS Instance HE KBE Instance 6 Double click to open schematic window ES Tranecript 4 Design Center Find o it Directory projectiSimpl 2 Precision RTL Synthesis Users Manual 2003c Update1 5 15 March 2004 Using the Find Window Features Viewing a Schematic The sequence is as follows 1 Knowing that inverter primitives are named INV enter INV in the Search Criteria entry box 2 Select the statemachine object as the place to start the search 3 Set the search filters to only look for instances 4 Click FIND The Find function returns the pathnames of two inverters in the statemachine block At this point you can double click on an object s pathname to view it in a schematic window If you select the object again it will highlight in the schematic window Searching for Objects Using Regular Expressions The concept of regular expressions in the Tcl language is a powerful pattern matching capability You can think of a regular expression as a template that matches a group of strings A regular expression can contain special characters that represent subparts of a string For example if the wildcard asterisk character 1s plac
40. Precision RTL Synthesis Users Manual 2003c Update March 2004 Copyright Mentor Graphics Corporation 2002 2004 All rights reserved This document contains information that is proprietary to Mentor Graphics Corporation The original recipient of this document may duplicate this document in whole or in part for internal business purposes only provided that this entire notice appears in all copies In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information End User License Agreement Trademark Information This document is for information and instruction purposes Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice and the reader should in all cases consult Mentor Graphics to determine whether any changes have been made The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OR MERCHANTABILITY AND
41. See Figure 5 3 for an example of how the number is displayed for multi page schematics Precision RTL Synthesis Users Manual 2003c Update1 5 7 March 2004 Traversing the Schematic with Strokes Viewing a Schematic Tracing a Signal to the Next Page When you are viewing a page in a multi page schematic you can double click on an output port and the viewer will jump to the connected input port on the next page Page 2 of Page 5 of 6 modgen_ add 9 ix37 2 Si clk gt rst gt mul_out 7 1 JUMP mul_out 7 1 Double click Panning the Schematic There are two ways to pan the schematic 1 Press the center mouse button on a 3 button mouse and drag the schematic around underneath the window Press and hold both buttons on a two button mouse 2 Use the side scroll bars to change the view 5 8 Precision RTL Synthesis Users Manual 2003c Update 1 March 2004 Viewing a Schematic Traversing the Schematic with Strokes Centering an Object in the Schematic View When you double click on an object in the Hierarchy pane the design object is centered in the Schematic pane J reg sub regi 0 a Operators 3 E 09 todgen_sub_6 sub iv modgen_mult_7 mul a Pins aj Inputs af H E be7 0 1 Click here L Primitives H E ix15_bus 3 0 E va i23 _bus 3 0 H A ix23_bus 3 MU Bae ie23_bust2 MU AD ix23_bus 1 MU fF AD ix23_pus 0 MU rH TU ined i TLIC a F 4 ES T
42. SpeedGate SpeedGate DSV Speed Wave SOS Initiative Source Explorer SpiceNet SST Velocity Standard Power Model Format SP MP Structure Recovery Super C Super IC Station Supermax ECAD Symbol Genie Symbolscript SymGen SYMED SynthesisWizard System Architect System Design Station System Modeling Blocks Systems on Board Initiative SystemVision TargetManager Tau TeamPCB TeraCell TeraPlace TeraPl ace GF TechNotes TestKompress Test Station Test Structure Builder The Ultimate Site For HDL Simulation The Ultimate Tool For HDL Simulation TimeCloser Timing Builder TNX ToolBuilder Tran sable Truetiming Utopia Vlog V Express V Net VHDLnet VWHDLwrite Verinex View Base ViewDraw ViewCreator ViewLogic ViewSim ViewWare Viking Virtual Library VirtuaLogic Virtual Target Virtual Test Manager TOP Virtual Wire Voyager VETA VETA me VRTXoc VRTXsa VRTX32 VStation VStation 30M Waveform DataPort We Make TMN Easy Wiz o matic WorkX pert xCalibre xCalibrate Xconfig AlibCreator XMLZ2AXEL Xpert Apert API XperBuilder Apert Dialogs Xpert Profiler XRAY XRAY MasterWorks XSH Xtrace Xtrace Daemon A trace Protocol Xtreme Design Client Xtreme Design Session AtremePCB ATK Zeelan Zero Tolerance Verification and Libs are trademarks or registered trademarks of Mentor Graphics Corporation or its affiliated companies in the United States and other countries The f
43. Synthesis is a comprehensive tool suite providing design capture in the form of VHDL and Verilog entry advanced register transfer level logic synthesis constraint based optimization state of the art timing analysis schematic viewing and encapsulated place and route Precision RTL Synthesis runs on PC platforms using Windows 2000 NT XP and Linux RedHat and UNIX Sun and HP platforms Refer to the Precision Synthesis Installation Guide for detailed information about supported system configurations and requirements Precision RTL Synthesis Features Intuitive User Interface The graphical Design Bar and the Design Center window guides both novice and expert users alike easily through the synthesis process A progressive disclosure paradigm presents only valid next steps reducing frustration and confusion When optimization completes additional design bars appear to assist you with design analysis and place and route Project Manager The Project Manager offers a framework that supports and promotes a design process based on experimentation The Project Manager system is based on projects which contain multiple implementations Each implementation within a project is a separate workspace in which you can experiment with different synthesis strategies and configurations Implementations keep track of all of the design settings input files and output files that comprise its configuration The Project Manager facilitates your design efforts by allo
44. T EA E TET T l 1 A ra Wed T r nets eee rie Won e sere mn anreeenene te retenn tet enen Terr tren 1 2 Constan Oinen Sy OE raa AEE E AE EEEE REEE 1 2 Boundaries PAO esia EE 1 2 Be T T nd oe A E E AE 1 2 Proce DOme Tomin Ana testes EETA 1 3 Deren n a E er senr eran Nan romney cor atr oni er tert he on eeee eee 1 3 Korn EO oes viper cennacada valine EE E EEEE 1 3 Schematic Viewing with Critical Path Fragment Filtering eeeeeessseeeenessssssesserrrssssssess 1 3 Integrated Creation and Analysis 1G ai rctiesiss cichcentinaceatsentcnncqtarnariacanaaraceseiaeeeantenedonceinnaes 1 3 De IA EE cannes PE A aed nie gan iene E ENEE E A neem PEE 1 4 Baier gcse stars pce ess EAE OAOE AIONE ONEN A PAE A AEE N A A T 1 4 P E E E A eet AEEA 1 5 Bo aee o A E E E E E E AA E OE A IE EE NTE ET 1 5 DEME T E a E A 1 6 PE E a EE E E EEA E OE EAT TEE OEA O 1 6 Pocmien ele ewig cis OaE ae eee One teina iaeaea Ana l 7 Wise S lol a A O l 7 Poo DE a E E a 1 8 Chapter 2 Setting Up a Design and Compiling cin ceric nnn eee 2 1 avokim Prenon RIL oni ea E E 2 1 Mrok mo Preoron GU I eerren ariar EE 2 1 Dorme Teenan oana 0 Co ra ween na Renee hnee sneer nc eee my rse mate eT 2 2 Setting up the Design Environment sesssosoeeessssssosererssssssessstrerssssssssecerressssssesereresssssseeeereo 2 2 The Project Directory and the Kemlis Direchoty sespe ohai 2 4 S A e A Di e g AE EEE E S ATE EO E AAAA 2 5 S e T 1215 8 4 a ServerName rene re neater tere tremens me
45. T OR TRADE SECRET MISAPPROPRIATION BY ANY SOFTWARE LICENSED UNDER THIS AGREEMENT TERM This Agreement remains effective until expiration or termination This Agreement will automatically terminate if you fail to comply with any term or condition of this Agreement or if you fail to pay for the license when due and such failure to pay continues for a period of 30 days after written notice from Mentor Graphics If Software was provided for limited term use this Agreement will automatically expire at the end of the authorized term Upon any termination or expiration you agree to cease all use of Software and return it to Mentor Graphics or certify deletion and destruction of Software including all copies to Mentor Graphics reasonable satisfaction EXPORT Software is subject to regulation by local laws and United States government agencies which prohibit export or diversion of certain products information about the products and direct products of the products to certain countries and certain persons You agree that you will not export any Software or direct product of Software in any manner without first obtaining all necessary approval from appropriate local and United States government agencies RESTRICTED RIGHTS NOTICE Software was developed entirely at private expense and is commercial computer software provided with RESTRICTED RIGHTS Use duplication or disclosure by the U S Government or a U S Government subcontractor is subject to the rest
46. TS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS LIABILITY UNDER THIS AGREEMENT EXCEED THE AMOUNT PAID BY YOU FOR THE SOFTWARE OR SERVICE GIVING RISE TO THE CLAIM IN THE CASE WHERE NO AMOUNT WAS PAID MENTOR GRAPHICS AND ITS LICENSORS SHALL HAVE NO LIABILITY FOR ANY DAMAGES WHATSOEVER 10 11 12 LIFE ENDANGERING ACTIVITIES NEITHER MENTOR GRAPHICS NOR ITS LICENSORS SHALL BE LIABLE FOR ANY DAMAGES RESULTING FROM OR IN CONNECTION WITH THE USE OF SOFTWARE IN ANY APPLICATION WHERE THE FAILURE OR INACCURACY OF THE SOFTWARE MIGHT RESULT IN DEATH OR PERSONAL INJURY INDEMNIFICATION YOU AGREE TO INDEMNIFY AND HOLD HARMLESS MENTOR GRAPHICS AND ITS LICENSORS FROM ANY CLAIMS LOSS COST DAMAGE EXPENSE OR LIABILITY INCLUDING ATTORNEYS FEES ARISING OUT OF OR IN CONNECTION WITH YOUR USEOF SOFTWARE AS DESCRIBED IN SECTION 7 INFRINGEMENT 9 1 Mentor Graphics will defend or settle at its option and expense any action brought against you alleging that Software infringes a patent or copyright or misappropriates a trade secret in the United States Canada Japan or member state of the European Patent Office Mentor Graphics will pay any costs and damages finally awarded against you that are attributable to the infringement action You understand and agree that as conditions to Mentor Graphics obligations under this section you must a notify Mentor Graphics promptly in
47. This functionality currently applies to all Xilinx Virtex I H Pro and Spartan technologies The equivalent functionality for other technologies is exercised by selecting the popup menu item Force Register into IO which sets the attribute named map_complex Mapping Clocks to Dedicated Clock Resources Most FPGA technologies contain dedicated clock routing channels to handle high fanout nets such as clock and enable lines These device resources are usually hard wired into the chip so using the global buffers typically does not utilize any extra area Since these global buffers are designed to handle high fanout loads you should attempt to use all of these resources for clock signals to minimize skew and slew and then use the remaining global buffering resources for high fanout signals in the design If you do not have extra global buffering resources available Precision will fix the fanout using either buffering or logic replication Precision assigns clock buffers to top level and internal signals that drive clock pins Since the technology contains the maximum number of global clock buffers for each technology and die size Precision does not exceed the maximum number of available global clock buffers Typically you will let Precision automatically insert clock buffers on the initial synthesis run As shown in the figure below Precision automatically infers the IBUFG and BUFG clock buffers when the corresponding input signal is used as a clock
48. ally for the selected object Also you can set constraints by right clicking on design objects in the Design Hierarchy pane Thus you can drive the entire flow from the Design Center window View messages by double clicking on the Log File Doubling clicking on the Log File brings up the Transcript window and its associated Interactive Command Line pane You can scroll up and down the transcript to read messages and review the history of the current session Double clicking on an error message in the transcript brings up the associated HDL source file for review and editing Precision commands executed from the GUI are recorded in the transcript These commands are highlighted in blue The transcript is saved in Precision log files precision 1log A session log records all commands executed during an entire Precision session and is saved in the project directory In addition an implementation Precision RTL Synthesis Users Manual 2003c Update 2 3 March 2004 Setting up the Design Environment Setting Up a Design and Compiling log is saved inside the active implementation directory which records only the commands executed while that implementation is active If the results directory was set using the set_results_dir command only the session log file is created and it is saved in the results directory Note View Schematics Reports by double clicking on Schematic Report Files Doubling clicking on a Schematic File or a Repo
49. am Input Files Right Click vill datapath vhd fal statemachine vhd Infos 1 TE e ret Trace to Hierarchy a g Constraint Files E af o hE statemachine_constraints sdc i G E b 3 0 C Script Files ob EG an Set Attributes Trace to HDL Source A E Output Files 7 E df Set Input Constraintgs i E A e 3 0 False Fath Constraint Ld Fao Report Timing H Oukputs vir Map All Input Flaps onto I5 lai Sort by name 3j Instances Copy Query Info to Clipboard Ob Ut stater Porti rst uz datapa H E Pins T Mets T Instances J Flip Flops l E Operators H E Primitives anecript fq Design Center Input Directory Simplenathisre This action adds a set_false_path command to the generated sdc file and applies a false_path attribute to the specified port or pin The basic syntax of the set_false_path command is set_false_path design lt view_type gt from lt from_list gt to lt to_list gt 3 16 Precision RTL Synthesis Users Manual 2003c Update 1 March 2004 Setting Constraints and Synthesizing Setting Timing Constraints After the action in Figure 3 8 you should see the following command in the Transcript Window and the generated constraint file set Talse path design rtl from rst If you identify a false path between two registers FF1 and FF2 for example and you are you manually entering a set_false_path command into the Master Constraint File the command might
50. amples OK Cancel Bley Folder ZA If the directory displayed is the directory where you want input files stored then click OK If you want to select another directory find and select the directory then click OK If you want a new directory click New Folder a new folder is added with the name New Folder Overtype this name with the desired folder name You can also set the input directory by entering the set_input_directory command See the Precision Synthesis Reference Manual for information on this command Opening a Project Opening a project restores the project to the state it was in when it was closed Restoring a project will reactivate the last active implementation and set the input directory and results directory settings The input directory is reset to the value saved in the implementation file The results directory is set to the temporary output directory in the Project Folder It also restores all synthesis binary databases and place and route files If the project being opened is a pre 2003c format file Precision will automatically convert it to the current format as it is loaded To open a project either click on the Open Project icon in the Design Bar or choose the File gt Open Project pulldown menu Only one project can be open at a time If a project is currently open Precision will prompt you to close the project before it will open another project 4 8 Precision RTL Synthesis Users Manual 2003c U
51. and The following example sets the comment property of implementation uart_top_alternate_1 to the phrase First alternatives of uart_top_impl_1 If you do not use the imp1 option set_impl_property operates on the active implementation set_impl_ property impl uart_top_alternate_l comment First alternatative or uart top impl 1 To retrieve the property values of an implementation call the get_impl_property command The following command example gets the comment property of implementation uart_top_alternate_l get impl property impl uart top alternate 1 comment 4 16 Precision RTL Synthesis Users Manual 2003c Update1 March 2004 Managing Projects Using the Project Manager Interactively Deleting an Implementation To delete an implementation do either of the following Right click on the implementation in the Project Files pane of the Design Center window and choose Delete Implementation from the popup menu Or choose the File gt Delete Implementation pulldown menu item to open the Select Implementation dialog box Select and implementation and OK the dialog box Precision prompts you to confirm the deletion before executing it Choosing Yes removes the implementation from the project and immediately deletes the implementation directory from file system Note that all files in the directory will be deleted not just those placed there by Precision Deleting the active implementation leaves no implementation active
52. ation of timing analysis technologies to correctly handle even the most complex circuits Interactive Timing Analysis A designer s information about device timing should not be limited to a few pre selected paths in a synthesis report Interactive timing analysis can instantaneously generate detailed timing reports from any port pin or instance in the design Timing queries can be initiated throughout the user interface including selected objects in the schematic viewer Register Retiming Precision Synthesis includes a powerful optimization algorithm called register retiming for improving performance in FPGA designs Retiming allows the optimizer to move registers across combinatorial logic to improve circuit performance Improvements of up to 50 are not uncommon when using this algorithm Refer to the topic Register Retiming on page 4 12 of the Precision Synthesis Reference Manual for more information Schematic Viewing with Critical Path Fragment Filtering An integrated schematic viewer provides a clear visualization of the synthesis process High level RTL schematics help you determine the impact of coding styles while detailed technology schematics show where and how device specific resources such as RAM and ROM are utilized Patented path viewing and filtering technology displays concise fragments of timing critical logic Integrated Creation and Analysis Tools The following additional standard features allow you to complete the
53. because Precision RTL Synthesis loads the technology library prior to compiling the VHDL source code LIBRARY IEEE USE ITEEE std_logic_1ll64 all USE IEEE umeric std all pragma translate_off USE a42mx components all pragma translate_on Case Sensitivity Although VHDL is not case sensitive in order to handle mixed language designs VHDL and Verilog Precision RTL Synthesis considers VHDL to be case sensitive Since most cell and port names in the technology libraries are uppercase the case of instantiated technology cells must also be uppercase 2 10 Precision RTL Synthesis Users Manual 2003c Update March 2004 Setting Up a Design and Compiling Setting up the Design Environment Verilog Considerations Before you use Precision to perform Verilog synthesis you should already have a good understanding of the syntax and semantics of Verilog Using Verilog synthesis also requires knowledge of the guidelines presented in the Precision RTL Synthesis Style Guide Auto Top Detection Precision RTL Synthesis auto detects the top level of the design and automatically determined the compile order of the input Verilog files Include Files If additional Verilog files are referenced via the include directive in an input file then the file is searches for in a pre defiled order This search order was described in the previous topic Include File Search Path Full Case When a case statement is used in your Ve
54. cessary if the instance is a blackbox without any underlying logic Precision can not determine the timing through the block Keep related critical paths in the same block of hierarchy Keep in mind that Precision RTL Synthesis performs area and timing optimization separately By separating timing critical logic into one block it may be possible to perform aggressive area optimizations on a greater percentage of the design thus creating a smaller circuit that meets timing Place registers at end of hierarchical boundaries Since optimization tools can only reduce combinational logic there are two barriers that constrain optimization hierarchical boundaries and registers When designing hierarchically you should attempt to place registers at either the front or back end of the hierarchical boundary This register placement essentially combines the two barriers 3 22 Precision RTL Synthesis Users Manual 2003c Update March 2004 Setting Constraints and Synthesizing Setting Other Constraints into one thus minimizing the impact to overall results when optimizing hierarchical designs Keep state machines into separate blocks of hierarchy This partitioning will speed the optimization and provide greater control over encoding Place tristate drivers at the same level of hierarchy This allows you and Precision RTL Synthesis more flexibility in handling implementing tristates By default Precision RTL Syn
55. ch 2004 Index Index cont Mapping Operators to Dedicated Resources 3 21 Master Constraint File 2 12 Memory Mapping Altera 3 21 Xilinx Virtex 3 21 ModGen 3 21 Module Generation 3 21 move_input_file command 2 7 Mulitplier pipelined 3 21 N nopad attribute 3 19 O Opening a Project 4 8 Operators inferring a pipelined multiplier 3 21 mapping to dedicated resources 3 21 Output Delay constraint 3 14 setting the global default 2 6 P P amp RIntegrator 1 6 Parallel Case Verilog 2 11 Pipelined multiplier 3 21 Pragmas Verilog 2 18 precision command 2 1 precision shell command 2 2 Precision Synthesis invoking from a shell 2 2 Invoking the GUI 2 1 precision log File 2 3 Project save and restore 1 7 Project Directory file structure 4 5 Project Directory Moves 4 20 Project Management 4 1 actvating implementations 4 13 backward compatibility 4 21 bypassing 4 2 closing a project 4 9 commenting implementations 4 15 copying implementations 4 14 creating a new implementation 4 10 creating a new project 4 3 deleting implementations 4 17 opening a project 4 8 output directory 2 4 overview l 1 4 1 renaming implementations 4 12 saving implementations 4 11 setting the project directory 2 5 setting the results directory 2 5 Project Input Directory or Input Files Move 4 20 Projects Created with a Script 4 7 R Reading VHDL files 2 10 Register Retiming 1 3 R
56. count reg lt data_in else count reg count reg OL end if end if end process divide 1 when count_reg maz_count else 0 end RTL Library IEEE use IEEE std_logic_1i 4 all use IEEE std_ logic_arith all entity dlatrg i generic data_width natural 16 3 port f data in in UNSIGNHEDidata_width 1 downto t clk an Sia logic 1 4 Precision RTL Synthesis Users Manual 2003c Update March 2004 Introducing Precision RTL Synthesis Integrated Creation and Analysis Tools The HDLInventor interactively highlights syntax and synthesis construct errors found during the Compile process You can make your edits in this window and if required insert template s of HDL code that you frequently use Project Browser The Project SONT TE you fully visibility and access to your input files and output files wie 4 Impi pseudorandom impi_i ma z a Input Files Double Click to Edit HDL File ii pseudorandom thd arning h Es t E 0 Constraint Files Double Click to Edit Constraint File FF pseudorandom_ constraints sde Double Click for Transcript Window ie PLE C Script Files AS Output Files Double Click for RTL Schematic 1 Log File Warnings 6 Infos o MN imti PTL Schematic Double Click for Tech Schematic i Technology Schematic A Bs 3 Area Report Double Click for Timing Report Timing Report a Timing Meta Report
57. ct name with the _impl_ lt n gt suffix where lt n gt is an integer that is incremented to ensure the name is unique within the project The new implementation is automatically activated Precision creates a new implementation directory of the same name in the Project Folder Creating an Implementation from the Command Line When creating a new implementation by using the new_imp1 command you can supply a name for the new implementation or not If you don t specify a name a default name is provided The default name of the new implementation is composed of the project name with the _iImpl_ lt n gt suffix where lt n gt is an integer that is incremented to ensure the name is unique within the project Precision RTL Synthesis Users Manual 2003c Update March 2004 Managing Projects Using the Project Manager Interactively The following command example does three things 1 Deactivates the active implementation if one exists 2 Discards any unsaved changes in the active implementation before closing it 3 Creates and activates a new implementation named uart_xilinx new impl name uart_xilinx discard Figure 4 8 New uart_xilinx Implementation E Project uart top H B Impl uart top impli 9 Impl uart bop imnpl_2 Impl uart _xilinx 3 E Input Files FE constraint Files C Script Files Output Files shad Log File Infos 5 If the discard option is omitted and the current implementation has unsaved chang
58. cts Backward Compatibility with Pre 2003c Projects Backward Compatibility with Pre 2003c Projects Precision version 2003c introduced a number of enhancements to the Project Manager The Project Manager is more flexible and more tightly integrated into the work flow As described throughout this chapter Precision now provides new graphical user interface features specifically for the Project Manager such as new command icons menus and dialog boxes In addition an assortment of new Project Manager Tcl commands are now provided In most cases the Project Manager is backward compatible with pre 2003c project files and scripts The format of project files and implementation files has changed Now when you open a pre 2003c project Precision automatically converts it to the new format and creates a project directory structure for it The new project file 1s not a script of Tcl commands as was the old format The new format is more like a registry of objects in the project A good usage model with the new Project Manager is to always open or create a project as your first step Once the project is open you can run any or your scripts as you did in the past Your pre 2003c scripts will run with only a few minor differences The differences are due to modifications made to older Precision commands so that they will behave properly in the new environment In some cases the new Project Manager commands replace functionality that was provided by old com
59. d set the Input Delay relative to the rising clock edge 1f it is negative enabled set the Input Delay relative to the falling clock edge Assuming that the current design is a module in a bigger design the Input Delays must be obtained from the system designer based on the chip environment described in the system functional spec If you don t know the Input Delay it is common to specify zero delay at first to ensure that the circuit successfully completes Place amp Route on the first run On future synthesis runs you can tighten up the Input Delays to more closely model the real environment This is a much better technique than leaving Input Delays undefined If you are you manually entering a set_input_delay command into the Master Constraint File you can use wildcards with the get_ports command to simplify the specification of external delays on bus pins For example gt set_input_delay design rtl clock clkl 6 get_ports waddr And you can utilize the all_inputs command to set a default value on all top level input ports gt SeLc_input_delay desiagn rtl clock sysclk 3 all inputs 3 12 Precision RTL Synthesis Users Manual 2003c Update March 2004 Setting Constraints and Synthesizing Setting Timing Constraints Specifying Output Delay What is Output Delay Output Delay is the delay required outside of the current design in order to properly clock the driven device Output Delay is the inverse of the term require
60. d you can set design constraints on the design so that Precision can address the critical timing paths in your design At a minimum you should set the global frequency Since Precision automatically detects all of the clocks in the design after compile it is highly recommended that you specify clock constraints on each detected clock This method will insure that Precision focuses on the critical timing paths in the design Constraints can be set from the using any combination of the following methods Adding an SDC File to the Input File List This file is called the Master Constraint File but the filename may be any name you specify as long as it have an sdc extension As previously described if you don t have a Master Constraint File you can use Precision RTL Synthesis to generate one for you on the first synthesis run Technically you can have more than one sdc file in the Input File List however it is a common practice to maintain only one Master Constraint File Entering Constraints from the Precision GUI You can manually add constraints to the in memory design objects with the GUI A record of the changes are saved in a generated sac file that is placed in the current implementation directory Entering Constraints from the Command Line You can use the Interactive Command Line Shell to add constraints to the in memory design You may do this while experimenting with different constraint sets You must realize however
61. d ROM For detailed explanations and coding examples refer to the following topics in the Precision RTL Synthesis Style Guide Inferring Operators and Counters Inferring a Pipelined Multiplier Mapping Operators to Dedicated Resources Mapping Blocks to Altera LogicLock Regions Mapping to Altera Memory Resources Mapping to Xilinx Memory Resources Setting Other Constraints Controlling Hierarchy Synthesis tools create a block of hierarchy for every component instantiation in an HDL based design Although hierarchy is an excellent method for reducing a complex engineering problem into reasonable understandable blocks it does constrain the optimizer from obtaining the best possible results For example if an AND gate and inverter are in separate blocks of hierarchy Precision RTL Synthesis Users Manual 2003c Update1 3 21 March 2004 Setting Other Constraints Setting Constraints and Synthesizing synthesis tools would traditionally not be able to optimize the logic into a single NAND gate Designers want to keep as much hierarchy as possible to aid in debugging the design The synthesis tools wants to flatten all of the design hierarchy within the constraints of the RAM and CPU speed of the computer so they will have the best chance of obtaining the fastest smallest design Unfortunately flat designs with their inherently long abstract instance and net names may be difficult to examine To try to achieve both of these conflicting hi
62. d _ ign Regular Expression ELSE i AD modge E Blocks 3 Click Find Help PROCESS fclk ret BEGIN add out lt addl mu EHD PROCESS asynchronous reset clears Dbject Path Object Type IF rst O THEN modgen add 6 modgen_add o Instance Show Hierarchy modgen_ SU Ul modgen_e U Instance l modgen_mun 7 modgen_mult_7 Instance Show LUT Information e Reload Schematic t lla an 5 Click again to select and highlight view Trace Schematic SHU WOrkK SIMpien ath Main Ab Update Schematic oom d zin mougen_ad Trace to Hierarchy ace to Physical et Attributes source Sharing 6 Right click and select Pg Design Center Pg Design Brow ES simplemath Report Timing Trace Forward b Trace Backward b Copy Query Info to Clipboard Instance modgen_add S Precision RTL Synthesis Users Manual 2003c Update1 5 17 March 2004 Setting Schematic Viewing Options Viewing a Schematic Setting Schematic Viewing Options Understanding the Term Bused Instance The term bused instance refers to an instance that is connected in parallel with one or more identical instances Each bused instance must be a group of instances of the same cell and the same view and each pin on the instance must be connected in parallel to the same scalar net or net array bus as the other instances in the group The following illustration shows a group of
63. d time that may be used in other Mentor Graphics tool environments As shown in Figure 3 6 if the reference clock period is 10 ns and the Output Delay is specified as 4 ns then Precision RTL Synthesis will constrain the combinational path from the clock pin of the internal register of the current design to the specified output port to 6 ns Figure 3 6 Output Delay Defined output delay 4ns constraint ae outside Current design virtual circuit Logic Cloud data_out clock period 10 ns set_output_delay clock ciki 4 data_out Precision RTL Synthesis Users Manual 2003c Update1 3 13 March 2004 Setting Timing Constraints Setting Constraints and Synthesizing Setting Output Delay from the GUI To specify Output Delay on an output port using the GUI follow the steps in Figure 3 7 Figure 3 7 Setting Output Delay from the GUI 3 Ul siline VIRATE 244008144 6 Frequency 100 MHZ Timing Constraints Please select clock Design Hierarchy Clock Mame eki UF simplemath_top main emu Welew ns Output Delay dl ng e_impl_ 1 unsaved d a e vhd Infos 1 3 an Add Delay lv Rising Edge Offset 3 Enter value sob e_ constraints sde HL bf 3 0 e Set False Path to 1 Select an Output a C lt 3 0 m Ck 05 pen and right click 2 ER I Set MultiCycle Path t0 cycles E E Fao F Sethin Delay ns uts 4 Click y 3 Set Max Delay
64. d view the output files of inactive implementations by clicking on its icon but you cannot modify the contents The easiest way to activate an implementation is to double Precision RTL Synthesis Users Manual 2003c Update1 4 13 March 2004 Using the Project Manager Interactively Managing Projects click on it Alternatively you can right click on the implementation you want to activate and choose Activate Implementation from the popup menu A third method that doesn t require you to have an implementation already selected is also available Click on the Activate Implementation icon in the Project pane of the Design Bar This command opens the Select Implementation dialog box Figure 4 11 which lists the inactive implementations within the project Select one and OK the dialog box Figure 4 11 Dialog Box Listing all Inactive Implementations ch TO aa eae Select Implementation x H Impl uart top impli LE Impl uart ilinx Select an implementation E Impl uart _top alternate _1 e E Input Files uart_top_impl_ FF Constraint Files uart silir C Script Files E E Output Files 7 Lid Log File Infos 9 Cancel When you activate an implementation Precision first closes the currently active implementation If you have unsaved work in the active implementation Precision prompts you to either save or discard the work Then the implementation hierarchy is collapsed and the selected inactive implementation is opened
65. d with a respective third party Use of third party Marks is intended to inure to the benefit of the respective third party Rev 040109
66. date1 5 1 March 2004 Viewing the RTL Schematic Viewing a Schematic Viewing the RTL Schematic When you initially compile a design the in memory database is created with generic gates As shown below if you invoke the Design Browser at this point the RTL Schematic is a reflection of this database JJ TL Schematic Figure 5 2 Design Browser with 5 2 Precision RTL Synthesis Users Manual 2003c Update1 March 2004 Viewing a Schematic Viewing the Technology Schematic Viewing the Technology Schematic After Synthesis a technology mapped database is created in addition to the generic database When you double click on the Technology Schematic file a schematic of the technology mapped design comes up You can choose to view either schematic by selecting the appropriate view as shown below Figure 5 3 Design Browser with Technology Schematic srecision RTL Synthesis Design Browser sx0O work simplemath main Page 1 of 4 ja a lS ma Sn y Indicates Multi Design Mapped to Page Schematic Technology Cells plemath ma Clocks d Inkai z a sb eg pezen _s meg Instances fa Flip Flops H reg_add SO reg_rnul H reg_sub j Sz Operators FOGC_S 0 B C_i_C LA_i_a_e I 10 Pads F 4 Select Technology Schematic P Design C Ad Design Br Input Directory sharedexamples Select Design Center Precision RTL Synthesis Users Manual 2003c
67. ddition Precision will likely insert unnecessary circuitry and may view real violations as a lower priority You can use a False Path definition in these cases to avoid the false violation False paths occur for a variety of reasons A path may be false because you know that the path will never pass data forward or that the circuitry involved will operate slower than your constraints indicate For example test logic can usually be operated at a lower frequency if necessary Paths from master reset signals are often false for a similar reason Often reset sequences occur over many clock cycles and it doesn t matter exactly when a particular register 1s reset Another possible reason for using a False Path definition is to exclude paths that exist in the circuit but because of the operation of the system they never interact Static analysis cannot not Precision RTL Synthesis Users Manual 2003c Update1 3 15 March 2004 Setting Timing Constraints Setting Constraints and Synthesizing know the relationship of states of your circuit so False Path definitions are used to help PreciseTime ignore these paths Setting a False Path from the GUI To specify a False Path using the GUI follow the steps in Figure 3 8 Figure 3 8 Setting a False Path from the GUI alins VIR ESI a40ics 44 gt 6 Frequency 100 MHZ Design Hierarchy J Project statemachine E simplemath_top main an Impl statemachine_impl_1 unsaved a Clocks 1 Select and El
68. design You use the set_ attribute command to set attributes in the Master Constraint File Precision RTL Synthesis Users Manual 2003c Update1 3 19 March 2004 Setting Mapping Constraints Setting Constraints and Synthesizing Mapping Internal Registers to IO Block Registers By default Precision Synthesis maps all internal candidate registers to registers located in IO Pads This maximizes the performance at the interface of the chip but may result in a longer delay path from the IO block to a register in the chip core You can disable this automatic IO Pad mapping on a selective basis to increase the performance on internal critical paths From the GUI you Compile the design select an IO port and right click to bring up the popup menu Select Force Input Flop onto Input Pad gt FALSE This sets an attribute on the port that tells Precision how to map the IO register One of three attributes are set depending on the type of port inff for input ports out ff for output ports and triff for tri state ports The commands that are recorded in the SDC constraint file might look like the following set_attribute design rtl name INTFF value FALSE port data_in 1 s t _ attribute design rtl name OUTFF value FALSE port data_out 1 set attribute design rtl name TRIFF value FALSE port data inout 1 You may also set these attributes on ports in the source HDL Refer to the Precision Synthesis Reference Manual for details and examples
69. disclose it or use it except as permitted by this Agreement Except as otherwise permitted for purposes of interoperability as specified by applicable and mandatory local law you shall not reverse assemble reverse compile reverse engineer or in any way derive from Software any source code You may not sublicense assign or otherwise transfer Software this Agreement or the rights under it whether by operation of law or otherwise attempted transfer without Mentor Graphics prior written consent and payment of Mentor Graphics then current applicable transfer charges Any attempted transfer without Mentor Graphics prior written consent shall be a material breach of this Agreement and may at Mentor graphics option result in the immediate termination of the Agreement and licenses granted under this Agreement The provisions of this section 4 shall survive the termination or expiration of this Agreement LIMITED WARRANTY 5 1 Mentor Graphics warrants that during the warranty period Software when properly installed will substantially conform to the functional specifications set forth in the applicable user manual Mentor Graphics does not warrant that Software will meet your requirements or that operation of Software will be uninterrupted or error free The warranty period is 90 days starting on the 15th day after delivery or upon installation whichever first occurs You must notify Mentor Graphics in writing of any nonconformity withi
70. e h 1 Select a Clock port achi and right click F E Mets d Trace to Hierarch 7 2 Select H 3 Enter value Ee achine_constraints sde Trace Se eee 4 Click M Asunchronous Domains Set Attributes Domain ClockDomaind Set Clock Constraints Offset Warnings 1 Infos 16 Report Timing Emre report Sort by name iolation Report l 5 0 10 0 Copy Query Info to Clip Port ced Optimization Constraints I Insert Clock Buffer Clock Buffer Fin Humber Cancel Help nput Directory ints Report achine edf ser Constraint File Center When you set a clock constraint from the GUI the default Clock Name is the same as the port name You can change the Clock Name later 1f you wish by changing the name switch in the create_clock command in the Master Constraint File If you want to set the same constraint on all clocks you can select just the Clock folder which selects all objects in the contents of the folder Within the folder you can select more than one port by pressing the Control key when you select addition ports optional Specify the clock domain By default Precision assumes that registers that are triggered by different clocks do not interact If you have multiple clocks in your design that contain logic that may interact you should define these clocks in the same domain Clock domains do not exist within standard SDC This characteristic is
71. e File Type alins UCF File OF Cancel You may include other SDC constraint files with the UCF input file however you should make sure that the constraints in different files don t conflict If a conflict occurs the constraints in the last file read last file in the list prevail Specifying Attributes or Pragmas in the HDL Source Constraints that rarely change can be added directly to the HDL source files by using VHDL attributes or Verilog pragmas An example might be a physical pin number assignment that is set by the system specification or a dont_touch attribute that is set on a block of IP Intellectual Property Refer to the chapter titled Attributes in the Precision Synthesis Reference Manual for details and examples For more information on setting a specific timing or design constraint refer to Setting Constraints and Synthesizing on page 3 1 Synthesizing the Design During synthesis Precision performs the following high level tasks 1 Implement operators 2 Perform intelligent auto dissolve on smaller hierarchical blocks 3 Perform initial quick optimization of each block 4 Determine the blocks that do not meet timing and perform additional optimizations where necessary 2 18 Precision RTL Synthesis Users Manual 2003c Update March 2004 Setting Up a Design and Compiling Synthesizing the Design 5 Write out netlists and reports to the implementation directory Evaluating the Results A
72. e 4 4 Hierarchical Project File Struct re ag sac ceeteis snc vsearanasacivccenanepeccenitasbarenenactnertessiansases 4 6 Pomego aie ri ee ec ees 4 8 Figure 4 6 Project Manager Icons on the Design Bal cccccccccceeeeeeeeneeseeseseeesseeeeeeeees 4 9 Pawnee og G6 lt 6 og 10 a Let 1 eee eee en nmr nee Pe nyt eer Sev Se Terre waren nye ney yer seperate Tener at 4 10 Figure 4 8 New uart_xilinx Implementation 2 0 0 0 ceeecceecceccececeneeseeesceeceeeseeeesseeceeeeeeaeas 4 1 Figure 4 9 Menu and Dialog for Renaming the Active Implementation 00008 4 12 Figure 4 10 Select Implementation Dialog BOX asicositienicincaenenarenedinieanenienss 4 13 Figure 4 11 Dialog Box Listing all Inactive Implementations ce eeeeeeeeeeeeeeeeeeees 4 14 Figure 4 12 Menu and Dialog for Editing Implementation Comment Property 4 16 Figure 5 1 A Quick Way to Bring Up a Schematic cc ceececcccccccccessseeeeeeececeecaeeseseseeeeeeneas 5 1 Figure 3 4 Desion browser witb KIL SCH assisar n 5 2 Figure 5 3 Design Browser with Technology Schematic eesseesessesssssseesererressrsssssssssssssesee 5 3 Figure 3 4 Viewing ibe Critical Path SCS NIAC sacsascscmsintnaariniceticninaeneirdaesann 5 4 vi Precision RTL Synthesis Users Manual 2003c Update1 March 2004 Table of Contents List of Tables Table 3 1 Technology Fin Name AttriDUTES erctreinnsscaaaeseeeneieecomennanenent 3 18 Table 3 2 Handling Different
73. e Project Manager Interactively Managing Projects Renaming an Implementation Implementation names are arbitrary You can use any name that 1s meaningful to you The project keeps track of all file associations To rename an implementation right click on the implementation in the Project Files pane of the Design Center window and choose Rename Implementation from the popup menu That opens the Set Implementation Name dialog box Enter the new implementation name and OK the dialog box Figure 4 9 Figure 4 9 Menu and Dialog for Renaming the Active Implementation Project uart_top H E Impl uart top impli E Impl uart_xilinx Impl uart_top_impl_2 9 Input Files 5 Constraint Files 9 Script Files H Output Files Lid Log File Infos 5 Setup Design Ctrl T Add Input Files Ctrl 4 Remove 4ll InpubliGonstraint Files Script Files Etri DEL Compile Sy these Place amp Route Save Implementation Copy Implementation Rename Implementation Set Implementation Comment Delete Implementation Set Implemenation Name Rename implementation wart top impl 2 Juart_top_altemate_1 Cancel 4 12 Precision RTL Synthesis Users Manual 2003c Update March 2004 Managing Projects Using the Project Manager Interactively Alternatively you can use the File gt Rename Implementation pulldown menu item This menu choice opens the Select Implementation dialog box which when in rename context lists the implementa
74. e and retain all rights not expressly granted by this Agreement Mentor Graphics grants to you subject to payment of appropriate license fees a nontransferable nonexclusive license to use Software solely a in machine readable object code form b for your internal business purposes and c on the computer hardware or at the site for which an applicable license fee is paid or as authorized by Mentor Graphics A site is restricted to a one half mile 800 meter radius Mentor Graphics standard policies and programs which vary depending on Software license fees paid or service plan purchased apply to the following and are subject to change a relocation of Software b use of Software which may be limited for example to execution of a single session by a single user on the authorized hardware or for a restricted period of time such limitations may be communicated and technically implemented through the use of authorization codes or similar devices c support services provided including eligibility to receive telephone support updates modifications and revisions Current standard policies and programs are available upon request 2 ESD SOFTWARE If you purchased a license to use embedded software development ESD Software Mentor Graphics grants to you a nontransferable nonexclusive license to reproduce and distribute executable files created using ESD compilers including the ESD run time libraries distributed with ESD C and C
75. e the same name must be added to the project using a relative pathname relative to the input directory Setting the Technology In order for Precision RTL Synthesis to map your design to a specific technology you must specify a target technology Precision RTL Synthesis provides a number of CPLD and FPGA libraries from major vendors These libraries includes the technology specific cell definitions and custom operator implementations They also contain global library defaults such as route tables and fanout constraints To specify the technology and global options you should follow these steps 1 Click on the Setup Design icon in the Design Bar left side of the GUI This action displays the Setup Technology dialog box containing all technology libraries that are included with Precision RTL Synthesis Precision RTL Synthesis Users Manual 2003c Update1 2 5 March 2004 Setting up the Design Environment Setting Up a Design and Compiling 2 Select the target technology by clicking on the vendor and technology name This action adds a set of default technology settings that you can modify 3 Verify and or modify the default technology settings 4 Optionally set a global design frequency This value serves as a starting point for clock constraints on all clocks After the Compile step you will be able to select each clock in the Design Hierarchy pane and adjust the constraints accordingly 5 Optionally set the default Input Delay and Outp
76. ects so that they do not use the temp directory If you want to change the current project so that it either saves or does not save to the temp directory use the set_project_property command set_preference pref project usetempdir value false Warning If your session is interrupted and you are using a temp directory you can delete the temp directory and start work where you last saved If there is no temp directory then the implementation will not be recoverable Projects Created with a Script Projects that are created when a script runs without using new_project or open_project commands do not automatically use temp dirs and that fact is persisted in the psp file For more information on using scripts see the Scripts for Creating New Projects or Reusing Existing Projects or Creating a Script from a Precision log File sections Setting the Input Directory You can set the input directory for files loaded into the project from the graphical user interface or by entering the set_input_dir command Select File gt Set Input Directory to display the following dialog box Precision RTL Synthesis Users Manual 2003c Update1 4 7 March 2004 Using the Project Manager Interactively Managing Projects Figure 4 5 Setting the Input Directory Set Input Directory 2 x Set Input Directory EH shared hete E examples 9 include 2 pdfdocs BC pkgs aD registry 21 systest z E training Ei A an Folder ex
77. ed you can View Trace Schematic and bring up a schematic view that only contains the traced elements Examine the following procedure Set Attributes Sek Wel Constraints Set Preserve Signal Set Preserve Driver Report Wet Info reg preset stie Oja Assign to Lowskew es ERA N 1 Leve Trace Forward 2 Levels j Trace Backward 3 Levels 1 Right click LLL Looe bevels E Levels i reg preset ate iT Copy Query Info to Clipboard Het sel oo to Qukputs In the frame above the sel net is selected and the signal is traced back two levels of instances The results are shown below Notice that the signal and the first two levels of instances are high lighted in orange Notice also that the signal crosses a hierarchy block so the border of that block is highlighted of instances Traceback 2 sag Precision RTL Synthesis Users Manual 2003c Update1 5 13 March 2004 Viewing Schematic Fragments Viewing a Schematic Viewing a Trace Schematic After you have traced a signal one or more levels you can view just the traced elements by clicking the View Trace Schematic icon on the Standard Schematic toolbar or you can right click and select View Trace Schematic from the menu The results are shown below 1 Click to View Trace Schematic ES ie U clk rst sel statemachine 2 Click to return to RTL Schematic 3 Click to unhighlight all traces
78. ed and opened in the Design Center window as shown in Figure 4 2 Precision RTL Synthesis Users Manual 2003c Update1 4 3 March 2004 Using the Project Manager Interactively Managing Projects The default project name is project_n The project name will change automatically as you change the project folder You can rename the project by typing the name of the project in the Project Name field If you rename the project the project name will not change as you change the project folder The system will warn you when you press the OK button on the New Project dialog box when the following occurs Blank If the name field is blank you must enter a name for the project Folder does not exist If the folder does not exist then you have the option of letting the tool create the folder You may also use the Browse button to display a directory and then scroll to the desired folder Project name already exists If you receive a message that the project already exists enter a new project name in the Project Name field Creating a Project from the Command Line The following new_project command example creates the same project as in Figure 4 2 new_project name uart_top folder G sb project uarts createimpl When executed from the Precision Transcript window it opens the Design Center window When executed from the shell command line the GUI is not used The createimp1 option will create a default implementation If omit
79. ed at the beginning of an expression the asterisk represents any number of characters preceding it if placed at the end of the expression the asterisk represents any number of characters to the end of the string To illustrate the regular expression or tells the find function to find all object names that contain the substring or no matter how many characters come before or after the substring NOTE You can find a complete description of regular expressions and the special characters they contain in a Tcl reference manual 5 16 Precision RTL Synthesis Users Manual 2003c Update March 2004 Viewing a Schematic Using the Find Window Features The graphic below illustrates a regular expression search for all the generated operators in the design Because every operator s name contains the string modgen you can search using the regular expression gen simplemath hd _ O x gt Find 0 x a VARIABLE mul signed 3 1 Enter BEGIN Search Criteria gen IF sel 1 THEN mull a ea Select search starting point mul h T eed eac heuha hian nae E simplemath rain Edict rog lIETaic i mu Ll al sub reg I Find all objects mule f EHD IF M Find Instances Find Pine IM Finc mul_out lt muli mule END PROCESS IM Find Nets PROCESS 3 b c f add_reg VARIABLE addi signe Case Sensitive BEGIN oes IF isel THEN P Match whole word orn 7 Source highlighte
80. en you read a new block into the overall design and that block matches an empty or existing cell However you should investigate these messages to make sure you have not unintentionally overwritten an in memory block Precision RTL Synthesis Users Manual 2003c Update1 2 13 March 2004 Compiling the Design Setting Up a Design and Compiling 2 14 Messages about the sensitivity list arbiter v line 873 Warning interleave should be present in the always condition Because sensitivity lists are ignored during synthesis Precision builds combinational logic as if such missing signals are present in the sensitivity list This can lead to simulation mismatches Messages about unused nets arbiter v line 441 Warning extranet is never used These warnings indicate local nets that were declared but never used within the design Such nets are dissolved during constant propagation Often the indicated nets lead to expected unused output ports from instantiated blocks Consider removing such unused internal nets However you should analyze the nets to ensure that a design error does not exist Messages about unused ports arbiter v line 441 Warning input extraport is never used Warnings about unused ports are more specific cases of the preceding warning about unused nets You should consider removing any ports that are declared but never used within the Verilog code Messages about latches arbi
81. enaming an Implementation 4 12 Reports generating 2 20 2 22 Retiming 1 3 RTL Schematic viewing 5 2 S Safe FSM 2 12 Saving the Active Implementation 4 11 Schematic Viewing bused instance defined 5 18 Precision RTL Synthesis Users Manual 2003c Update1 Index 3 March 2004 Index Index cont centering an object 5 9 changing the display colors 5 21 changing the printed sheet size 5 19 changing the selection radius 5 21 click and sproutl 5 14 cross probing from HDL Designer to Precision Synthesis 5 12 cross probing from schematic to HDL 5 12 how to unbundle instances 5 19 how to unbundle net buses 5 19 invoking Critical Path Schematic 5 1 invoking RTL Schematic 5 1 invoking Technology Schematic 5 1 left mouse button 5 5 moving up the hierarchy 5 7 object selection 5 5 paging forward backward 5 7 panning around the schematic 5 8 permuting symbol pins 5 20 placement of latches 5 20 placement of output drivers 5 20 placing IO buffers 5 20 saving a schematic to a file 5 19 select area 5 5 selection modes 5 5 showing the internals of blocks 5 10 tracing a signal to the next page 5 8 tracing through schematic fragments 5 13 unhighlight all traces U icon 5 14 unselect all 5 5 unselect object 5 5 view trace schematic VT icon 5 14 XRTL extension 5 3 zooming in 5 6 zooming out 5 6 zooming to area 5 5 zooming to fit 5 6 Scripts Creating from a P
82. entire synthesis task within Precision RTL Synthesis Precision RTL Synthesis Users Manual 2003c Update 1 3 March 2004 Integrated Creation and Analysis Tools Introducing Precision RTL Synthesis Design Bar The Design Bar provides you with a visual path through the synthesis flow Progressive discloser in the Design Bar a you determine what to do next T H 15 e counter L i B 15_modgen_counter Report Missing Constraints A 15_modgen_counter H E Operators S z 1G Pads i H E Blocks Report Timing J E Primitives B H agal LUT H ey View Critical Path H A i380ex1 LUTZ H E esfaxl LUT H E id 95Fx3 LUTZ fe i951 LUT fe Cr id 95Fx2 LUT aD idd44x1 LUTS i i 3 TAS Possible Action to Perform Next PTE oy H E ie 129x2 LUTS ae AD ieSQext LUTS Report Timing Yiclations ce eat aren an 4 lOr View Schematic HDLInventor The HDLInventor is an interactive source code editor in Precision RTL Synthesis You can double click on errors warnings and information red green and blue dots in the Transcript window or click on the name of your input file to bring up the HDLInventor signal count _reg UNSIGNED data_width 1 downto t constant max _ count UNSIGHED data_width 1 downto U fothers gt hegin cont it process clk reset begin 1f reset 1 then count reg lt fothers U elsif clk 1 and clk event then if load 1 then
83. era mapping blocks to LogicLock regions 3 21 memory mapping 3 21 Asynchronous signals detecting 2 20 Attributes buffer_sig 3 19 dont_touch 2 11 2 18 false_path 3 16 hierarchy 3 19 nopad 3 19 VHDL 2 18 Auto Top detection 2 10 B buffer_sig attribute 3 19 Buffers global 3 20 C Case Sensitivity 2 10 Clocks oOverview 3 3 Command Line entering constraints 2 12 Commands add_input_file 2 7 compile 2 13 get_lib_ports 2 15 move_input_file 2 7 precision 2 1 Set_attribute 3 18 3 19 Precision RTL Synthesis Users Manual 2003c Update March 2004 set_false_path 3 16 set_input_delay 3 11 set_input_file 2 7 set_output_delay 3 14 setup_design 2 6 Commands for derived clocks 3 6 Commenting an Implementation 4 15 Compatibility with Pre 2003c Projects 4 21 compile command 2 13 Constraints conflicts between files 2 18 Incorrect 2 21 input delay 3 11 ouput delay 3 14 reading from UCF file 2 17 Copying an Implementation 4 14 Counter Inferrencing 3 21 Inferring Counters 3 21 Creating a new Implementation 4 10 Creating a New Project 4 3 D Deleting an Implementation 4 17 Derived clocks 3 5 Derived clocks commands 3 6 Derived Clocks within the Graphical User Interface 3 5 Design Bar 2 2 Design Browser display options 5 21 Design Center Window 2 2 Design Files opening 2 6 dont_touch attribute 2 11 2 18 E Encoding state machines 2 12 Excluding Index 1 files from
84. erarchy goals Precision performs intelligent auto dissolving of smaller blocks of hierarchy By examining the instance count and type of logic within a hierarchical block Precision will only flatten the hierarchy of a lower level block if the block contain less than 50 instances and there is a high likelihood that removing the hierarchy will improve the synthesis results Precision reports a message prior to optimizing each hierarchical block to the transcript whenever it auto dissolves a block of hierarchy Prior to running synthesize you can override the hierarchy control on any block in the design by placing a hierarchy attribute on a specific instance Before you create or change the design hierarchy you should consider these ramifications Gate counts in leaf blocks should not exceed 50K gates Optimization can be performed on much larger designs provided that the sub hierarchy falls within this guideline The maximum size of a single level of hierarchy is difficult to define since it is so dependent on the design and technology Number of operators type style of RTL code amount of random logic etc all play a role in the maximum size that Precision can handle Precision RTL Synthesis characterizes constraints down through hierarchy And if you wish you can constrain each block individually if you want to override the characterized constraints through hierarchy Typically applying constraints to lower level blocks is only ne
85. ermore depending on the current state of Precision Synthesis set_working_dir will behave differently The following is a list of the three states of Precision Synthesis and the corresponding behavior of set_working_dir 1 Running with Project Manager a project is open Behavior Set the current working directory and the input directory to the specified path The output directory has already been set by the project 2 Running without Project Manager a results directory is set Behavior Set the working directory and the input directory to the specified path The output directory has already been set by set_results_dir 3 Running without Project Manager and no results directory 1s set Behavior Set the current working directory and the input directory to the specified path and create a default project and implementation in the current working directory The following is a simple example of how a pre 2003c script can be adjusted to use the new Project Manager commands Pre 2003c Script 2003c Script set_working_dir new_project name test folder 246 eae ley 46h commie ye el ree new_impl name my_test_impl_1 setup_design add_input_file compile setup_design synthesize compile setup_design increment synthesize place_and_route save_impl copy_impl name my_test_impl_2 place_and_route save_impl close_project 4 22 Precision RTL Synthesis Users Manual 2003c Update 1 March 2004 Chapter 5 Viewing a Schematic
86. es the new_imp1 command aborts and displays an error message in the transcript If you want to save the changes call the save_imp command Saving the Active Implementation As you work in the active implementation all of your work is held in the project s temporary directory until you choose to save it Precision indicates that you have unsaved work by displaying unsaved next the active implementation name in the Project Files pane of the Design Center window The Save Implementation command copies the contents of the temporary directory into the active implementation directory Do not save files directly into an implementation directory because those files A N will be deleted during the save_impl operation That is because save_impl Caution eletes all files inside the implementation directory before it copies the files from the temporary directory If you want to write files into the active implementation directory save them to the results directory use get_results_dir to obtain the pathname which is actually the temporary directory when an implementation is active To save your work either right click on the active implementation in the Project Files pane of the Design Center window and chose Save Implementation from the popup menu or choose the File gt Save Active Implementation pulldown menu From the command line call the save_impl command Precision RTL Synthesis Users Manual 2003c Update 4 11 March 2004 Using th
87. es of add_input_file move_input_file and set_input_file commands depending on how you add the files Precision RTL Synthesis Users Manual 2003c Update 2 March 2004 Setting up the Design Environment Setting Up a Design and Compiling Setting Input File Properties Once you include a file in the Input File List you can right click on the file in the Project Files pane and specify the Properties of the file Figure 2 2 illustrates the dialog box options and the text following the Figure explains the options in detail Figure 2 2 Specifying Input File Properties x Full Path ie br project S implenath sre datapath vhd Exclude file from Compile Phase File Type VHDL E work Library hak Include File Search Path Add Before File Type Allows you to specify the file type for file names that don t have the proper extension If this option is not used and a valid extension exists then the file type will be automatically detected Passing Files from Input to Output You can use this option when you wish to add one or more files to the Input File List but exclude them from the Compile phase Files marked with the exclude property are copied into the implementation directory after the synthesis phase is complete Also files of an unknown type are automatically marked as Exclude and copied to the implementation directory This mechanism is handy for passing a file such as a place and route control file around the
88. es that you Il want to change and refine on future synthesis runs Creating a Master Constraint File The recommended methodology is to create a Master Constraint File sac file and add this file as the last item in the Input File List You can create this file with a common text editor or use Precision to generate one for you on the first synthesis run You then add this generated file to the Input File List as your Master Constraint File During the Compile phase on a future synthesis run the in memory design is created from the HDL source files then the Master Constraint File is read and the constraints are applied to in memory design objects Maintaining a Master Constraint File Typically you will add and change constraints on future synthesis runs Constraint changes that that are made to the RTL in memory design from the GUI are logged to a newly generated constraint file This sac file is saved to the current implementation directory As previously Precision RTL Synthesis Users Manual 2003c Update1 3 1 March 2004 Setting Timing Constraints Setting Constraints and Synthesizing stated on the first run you can use this file as a template for your Master Constraint File On subsequent runs you should regard this file only as a record of constraint changes Some of the constraints will be a record of your experimentation while other constraints are changes you Il want to keep by adding them to your Master Constraint File The me
89. esiieorsadices teeetteesticatudeet taeen nies 3 17 Pe cance EE E eres eens 3 18 Mapping Ports to Pin Numbers and IO Pads cc eesccsceeeccecceceeeeseeecceeeeesaaeeeseeceeeeeeaeas 3 18 Mapping Operators Counters and Memory to Chip Resources cccccceceeessseeeeeeeeees 3 21 Speed ca ip E 11 5 ee omen oon pene cet E Eater ee ty Menta re rmanet 3 21 Bee eco UTE ey gis 2 yo 1 gaan neem ne eae Oe ne en Re ne Nene ae eeneene iar etn itty arat i wn tsnorm Re emrnente tte emree rt 3 21 Protecting Blocks from Change dont_touch essssssssseeeersssssssseeerressssssssseressssssssseerees 3 23 Contone T monton Dara Ne a i 3 23 Chapter 4 vaa Pa 5 Gf a rn 4 1 NC at oe D e EEEE EAEE A EAE A NN A TE E T 4 1 Boonie be mR aa ET a E 4 2 Dame the Project Miata or Inierichively serirririnintin s enn nirre E EARE ER EEA 4 3 Wi T Da PERE A AEE AA EEIE AEST E EN E AAE AE 4 3 Besi ue Bg ce E E A E T E AA EE AEE sre A E nee E T 4 8 OU TLE Beg cs a a E E AEEA 4 9 seme Up hie Imre meni A een one R 4 10 Cr ealine a Now ImpiementatiOn ssssiirrirsirriisrnretridhirankedirr rna AEn EEA RE EA 4 10 Creating an Implementation from the Command Line cc eeccccecccceeeeeessseeeeeeeeeceeaeaenees 4 10 Savine the Active Miplementalign aera scenester dahon cecederadinrd easdonmaiscecdaneisaniceieesaasas 4 1 ry ai Impe mno O aaee EE E 4 12 E ae a e ELT n AAA TPE EEE E E E E 4 13 Cope an apeme nA aE REEE E Tener rr errr err reer 4 14 Co
90. four multiplexors connected in parallel Each instance in the following illustration is a bused instance This group of four bused instances are bundled in the second illustration Bused Instances that are unbundled ch modgen sub G a cont g E 5 18 Precision RTL Synthesis Users Manual 2003c Update1 March 2004 Viewing a Schematic Setting Schematic Viewing Options Viewing Bundled Instances and Net Buses By default bused instances are automatically bundled and buses are displayed as a bold line to make viewing easier You can turn off the bundling feature by following these steps 1 From the Menu Bar select Tools gt Set Options Select the Schematic Viewer 2 3 Click off Show Bundled Instances and or Show Net Buses 4 Right click and select Reload Schematic Ti Schematic Viewer Sheet size Symbol handling Feedback levels i Fermute pins Output f2 lA width a5 i 10 Buther Latch 100 Size Click here I Show Bundled Instances Landscape Show Net Buses Portrait Hame E Fitpage Browse Changing the Schematic Printing Defaults 1 From the Menu Bar select Tools gt Options 2 Select the Schematic Viewer 3 Change the Printing Defaults are shown in the following illustration Printing Defaults f Schematic Viewer Sheet size Symbol handling Feedback levels Size A M Pernute pins Output 2 Width e s i 10 Butfer Latch 1
91. fter the synthesis run is complete you should evaluate the quality of the results Although the natural inclination is to look at the maximum frequency this value can be mis leading until you verify that your clock distribution is correct To get a complete view of the synthesis quality you should check the areas described below Analyzing the Cell Usage As part of the evaluation of your synthesis results you should use the Area Report and Schematic Viewer to verify that key resources were utilized to their fullest potential The following list shows some areas that you should check Empty IP blocks Clock Buffers IO cell usage Memories Unexpectedly removed ports or instances Analyzing the Timing Results After you run Synthesize you can view a timing report Timing reports display timing paths through hierarchical boundaries The following list provides the typical results of initially analyzing critical paths and the actions that you should take based upon the results Positive slack time If the design produces a positive slack time for critical paths you do not have to perform any further performance optimization steps and you can proceed to Place and Route Small negative slack time If your design produces a negative slack time for critical paths that 1s about 10 or less than the overall cycle time you should perform a quick check of the hints in the following two sections and proceed to Place and Route Since the initia
92. g the Project The following script combines the methods used in the previous scripts This script creates a project if one does not exist opens a project if it does exist and then produces results LCL script to Create project ir necessary Open it af it exists and produce results parameters open project or create it if file exists Sproj_folder Sproj_name psp open project and activate impl else create project and impl configure settings produce results save results to imple folder results are now in directory Sproj_folder Simpl_name Precision RTL Synthesis Users Manual 2003c Update1 4 19 March 2004 Using the Project Manager Interactively Managing Projects Exporting your Settings This option exports all the project settings in your project log and saves them to a tcl file First open the Precision Transcript window then choose the File gt Export Settings Script pulldown menu In the dialog box specify the name of the script to be created and click OK You can then edit the script file to modify existing implementation settings or add information for a new implementation You can run this file by opening the Precision Transcript window and selecting the Run Script option Actions to Take if the Project Input Directory or Input Files Move The Precision RTL Synthesis tool automatically tracks the location of the project input directory and input files You
93. gn references custom libraries and packages then you must include these package source files for reading before your design files are read The methods for doing this are fully discussed in the Precision RTL Synthesis Style Guide The following list shows some common issues when loading VHDL designs into memory Read source not compiled VHDL files Precision RTL Synthesis can not read compiled HDL databases from any simulator or synthesis tool You must read the VHDL source code including libraries and packages Auto Loading IEEE Libraries Precision RTL Synthesis automatically loads the IEEE standard std_logic_1164 and numeric_std packages It also loads if necessary the Synopsys std_logic_arith std_logic_unsigned and std_logic_signed packages in the IEEE library You do not have to include these packages in the Input File List in Precision RTL Synthesis Auto Top Detection In most simulators you must compile the VHDL code using a bottom up order Precision RTL Synthesis should auto detect the top level of the design and automatically determine the compile order of the input VHDL files Library Use Clauses for referring to technology cells Because synthesis tools use a different scheme to locate technology cell instantiations compared to simulators you should pragma out any VHDL Library and Use clauses for these cells using translate_on and translate_off Precision RTL Synthesis will still locate these cell instantiations
94. h the cell and port names in the technology library in Precision RTL Synthesis All port names must be included You can display this information using the get_lib_cell and get_lib ports commands The case of these names must also match even for VHDL which is not case sensitive Precision RTL Synthesis must maintain case sensitivity on all objects to support mixed HDL designs If the instantiation uses positional association to map the net to the cell port compared to including the port name and net name in the instantiation you should verify that Precision RTL Synthesis 1s making the same assumptions about pin ordering Evaluating Quality of Initial Results After you have fixed any errors and have a satisfactory explained of the warnings produced during the compile run you should examine the quality of the compiled design Although you can not generate a timing report on the technology independent design examining the compiled design will give you an early opportunity to address any Quality of Results issues To help you evaluate the design the following features are available The session transcript in the Transcript Window double click on the Log File The RTL schematic double click on the RTL Schematic file Cross probing features To evaluate the quality of the initial results double click on the Area Report in the Output File list and examine the following issues Check for latches in the transcript during the comp
95. he same level of hierarchy Use the Tools gt Set Options gt Optimization dialog box Click off the Add IO Pads radio button then click Apply This adds the command setup_design addio false to the Project File A Select an IO port in the Design Hierarchy pane or the Schematic Viewer right click and select Set Input Constraints Click off the Insert Pad radio button B Attach a nopad attribute to the port in the HDL source This situation typically occurs when you are using IP blocks that includes special instantiated IO pads in the IP core e g PCI cores A Select an IO port in the Design Hierarchy pane or the Schematic Viewer right click and select Set Input Constraints Select one of the options from the Pad Type dialog box B Attach a buffer_sig attribute to the top level port with a value set to the name of the IO pad A Select an IO port in the Design Hierarchy pane or the Schematic Viewer right click and select Set Input Constraints Click on the radio button Force Register into IO B Attach a buffer_sig attribute to the top level port with a value set to the name of the IO pad Precision only moves internal registers to complex IOs when the registers exists on the top level of hierarchy If the register is buried in hierarchy you must either instantiate the complex IO in the lower level block or flatten the hierarchy using the hierarchy attribute so that the buried registers are moved to the top level of the
96. ic design needs The following subsections describe the four common areas that you should check Mapping Ports to Pin Numbers and IO Pads Mapping to Pin Numbers Most place route tools allow you to assign pin numbers to ports in either the EDIF netlist file or in a Separate constraint file Precision supports assigning device pin numbers to top level ports These pin numbers are transferred to the synthesized netlist as a technology specific attribute which is recognized by the place and route tool Like all attributes you can specify the pin number constraints in your HDL code or use the set_at tribute command in the Master Constraint File You can use either the technology specific attribute name e g Xilinx uses LOC or you can use the generic pin_number attribute and Precision will map this generic attribute to the technology specific attribute during synthesis Table 3 1 Technology Pin Name Attributes Pin Number Attribute Name Use Altera pin_lock attribute LOC Xilinx Mapping to IO Pads Since some Vendor implementation tools require that IO pads be added to the design prior to running Place and Route Precision assigns IO pads to all ports in the top level of a design by default Precision can map input buffers output buffers tri state buffers bi directional buffers and complex I O IOs with registers cells The IO pads are defined in the target technology library If the technology includes more than one IO cell
97. ign during synthesis Boundaryless Optimization Precision s advanced optimization technology breaks down performance limiting design barriers such as register hierarchy and operator boundaries A powerful retiming algorithm balances logic across register boundaries hierarchy optimization minimizes logic between modules and pipelining moves registers into multipliers Precision understands when and where to employ these algorithms which can improve circuit performance by up to 70 FSM Optimization Finite state machines are automatically detected and optimized by Precision Complete analysis is performed on each FSM to locate and eliminate all unnecessary states A variety of encoding styles are then evaluated to determine the best implementation for the design and target technology If you choose you can override the automatic feature and specify a specific state machine encoding You can even specify a safe state machine for radiation environments Refer to the Precision Synthesis RTL Style Guide for more detailed information on state machine synthesis 1 2 Precision RTL Synthesis Users Manual 2003c Update 1 March 2004 Introducing Precision RTL Synthesis Integrated Creation and Analysis Tools PreciseTime Timing Analysis Precision s PreciseTime timing analysis is capable of finding the true critical paths in even the most complicated designs and clocking schemes PreciseTime employs the concept of clock domains a combin
98. iling of each cell In FPGA designs synthesis tools infer latches due to incomplete signal assignments Unintended latches have two negative affects on the design One they increase the size of the design because these sequential cells prevent the optimizer from combining boolean logic on either side of the latch Two unintended latches block timing analysis Precision RTL Synthesis Users Manual 2003c Update1 2 15 March 2004 Compiling the Design Setting Up a Design and Compiling Verify the number of inferred flip flops in each block in the Area Report Since synthesis tools only optimize boolean logic it is very important that you verify that each block is inferring the approximate number of flip flops that you expected Once a flip flop or latch is part of the design the synthesis tool will not optimize it away as long as it affects the design During optimization Precision RTL Synthesis will only add remove flip flops in your design in the following cases Register replication for timing or DRC fixes Register removal due to D input being driven by a constant these situations will be reported in the transcript Verify the number and type of inferred operators in the Design Browser in the Operators folders Since the critical path within most designs propagates through operators it is very important that you verify you are inferring the correct number size of operators Verify the number of inferred memorie
99. iner ite meet hymen 2 5 Anas DMU FEET me PO O errian a ei 2 6 a O a R 2 12 Ber alno a cal 8 T E OAA E A TAE ONIE AT AA 2 13 Evae e RS o EE A 2 13 semma Dimmi ond Desin Cons TAN cenre i innn an ER 2 17 SDENT e Bo e aE T 2 18 E a R E E E eet Tene ee trent fr 2 19 Precision RTL Synthesis Users Manual 2003c Update1 March 2004 Table of Contents Table of Contents cont err at Foe nd E E cia rier eer 2 22 Chapter 3 Setting Constraints and Synthesizing 00 0 0 ccc cec ccc ccc ccc eesesseeeecccceeeesaueseecececeeseauaneneeeceeeeeeaas 3 1 PAS a Master Constant Oise entena dharani sacndaeeasintn eect tadasuasncte aici esectebanens 3 1 Croatie a PiE innr 3 1 Maminni a Manter Consmant FIE seesi daren Ena sa areia rea aa a 3 1 me D a T a A 3 2 Ort Global Timing Constraints ss snscsnnnttarsnsrantadecresdatieasandbenadienedibaadeesexsriiacieienetanent 3 2 E T E ne nese ey ane rarer peneeresy aT emer cherry ren area cers 3 3 Dor COCKS nde ene i 3 5 Konor TO cae chee Qi E Seen er ne eee r ee ene ee eeere eve nten Nena Eaten nt aeeee re eterene rT teeter reer 3 6 A oc Vi gh E BG 1 N00 11 6 ener ne eee eee EE EEE 3 7 Homie Amone Gils 6 a ae Senne nt Tenner ste peer tr nttn fer tre nr inrre Var krse trereitret eter lerte npr tre tren Teeter 3 9 i Ti East cetera ie A E A 3 10 atest 3 13 ee MNT a aes LE lod gf ie ae eee nee Set en eee net men ene T Cr eer Feet rm ear en a men ene ne Sree ee penT ere 3 15 Be ee sacs paeneistetein sane sacaetaanenici
100. ing Precision RTL Synthesis Schematic Viewing Schematic Viewing is integrated with the advanced debug and analysis environment As shown below the advanced features allow you to select an object in a path and generate an instant timing report on that path pseudorandom rtl oo Show Hierarchy Clocks Show LUT Information 1 Select and MultiPage Schematics Right Click oa Instances Reload Schematic H Flip Flops View Trace Schematic J Operators F 10 Pads Update Schematic E Blocks H E Primitives H D eal LTS Goto Page BOF i380ex1 LUTZ Trace to Hierarchy H D iegf3x1 LUTS H D ida5Fx3 LUTZ H A ido5Fx1 LUTS H A id95fx2 LUT4 zoom Trace Forward The schematic viewer also allows you for example to 1 Cross probe between HDL source code RTL schematic and Technology schematic This correlation allows for easy debugging In addition you can cross probe a schematic generated in HDL Designer with a schematic generated in Precision RTL Synthesis 2 You can view the whole critical path in one window even if the path traverses multiple levels of hierarchy 3 You can view fanout and fanin cones of logic from a selected net or instance 4 When the critical path viewer is in query mode detailed timing popup information is displayed for the objects in the critical path 5 The schematic viewer search utility allows you to search for instance net and port and lists these items for you in a window
101. ints If you do not specify timing constraints Precision will map your design to technology cells but will not perform timing optimization When you specify timing constraints you only need to specify constraints on the top level ports and Precision will characterize the top level timing constraints through the lower level blocks of hierarchy With timing constraints Precision can make informed decisions about how to implement logic using technology cells After the design is mapped PreciseTime preforms static timing analysis to identify the paths that do not meet timing If there are violations Precision performs additional synthesis on these timing paths to increase the speed This usually results in more hardware on the critical paths due to an increase in parallel structures but only the critical paths are affected not the whole design Setting Global Timing Constraints As a Starting point you can set the default global timing during the Design Setup step After you Compile the design you can add refine and finalize the constraints before the Synthesize step 3 2 Precision RTL Synthesis Users Manual 2003c Update March 2004 Setting Constraints and Synthesizing Setting Timing Constraints You do this by selecting design objects in either the Design Browser or Schematic Viewer and use the right mouse button to display the timing constraint dialog box Constraints that you apply to the an in memory RTL design from the Precision GUI
102. inx Pad Report H EE Primitives l vilin PAR Report gr Sailing Mapping Report silin User Constraint File Place amp Route h Documentation Available Online Context Sensitive Help Precision RTL Synthesis has context sensitive help throughout the GUI You can press F1 to open a context sensitive help or press the HELP button The GUI window must be selected first to be in current focus when using F1 Note F1 does not work on UNIX Online help is available in Windows 95 format You can view frames of help text and graphics by moving your cursor to the Help pulldown menu and selecting Help gt Help Contents You can expand the Table of Contents and select from a variety of topics or do a full index search for keywords Precision RTL Synthesis Users Manual 2003c Update1 1 7 March 2004 Documentation Available Online Introducing Precision RTL Synthesis Product Manuals All Precision RTL Synthesis product manuals are available for on screen viewing and printing with the Adobe Acrobat Reader after Precision RTL Synthesis and the Adobe Acrobat Reader are installed from the Precision RTL Synthesis CD ROM You can view the manuals by selecting the following pulldown menu from the Main menu Help gt Open Manuals Bookcase The PDF manuals and the Manuals Bookcase also contain HyperText links that guide you to related vendor documentation on the Web provided your web browser is operational and properly configured T
103. ision s Project Manager Therefore the project directory is hierarchical in structure The top level is the project level and it contain multiple sub directories each of which 1s dedicated to a different implementation of your design For detailed information about the file structure of a project directory refer to Creating a Project on page 4 3 The purpose of the results directory is simply a repository for single implementation usage of Precision Synthesis This type of usage 1s typically carried out by batch scripts or from the command line interface Because this usage model deals with only a single implementation it does not require the organizational structure provided by the Project Manager Therefore the file structure is flat All output files are stored in the results directory without hierarchy When working with the project synthesis design work is not automatically saved to the implementation directory but is held in a temp directory until you save your work For more information see The Precision Temp Directory 2 4 Precision RTL Synthesis Users Manual 2003c Update 1 March 2004 Setting Up a Design and Compiling Setting up the Design Environment Setting the Project Directory You specify the location of a project directory when you first create the project Once the project is created the location is implicitly set each time you reopen the project because the project file resides inside the project directory You cannot
104. ject by calling the close_project command Precision RTL Synthesis Users Manual 2003c Update1 4 9 March 2004 Using the Project Manager Interactively Managing Projects Setting Up the Implementation Setting up the implementation consists of two steps that implement the add_input_files and setup_design commands which are shown graphically as icons in the Design Bar in Figure 4 2 For detailed information about these steps refer to Setting up the Design Environment on page 2 2 Creating a New Implementation Precision provides a few ways for you to create a new implementation You can choose the File gt New Implementation menu or right click on the project in the Project Files pane of the Design Center window and choose New Implementation from the popup menu The New Implementation command first closes the currently active implementation then creates and activates the new implementation If the current implementation has unsaved changes Precision will prompt you to save or discard the changes before creating the new implementation Figure 4 7 shows the Project popup menu and a new implementation named uart_top_imp1_2 Figure 4 7 Project Popup Menu E Project uart_top H E Impl uart top impli H Impl uart_top_impl_2 E Input Files Close Project New Implementation FE Constraint Files CI Script Files Output Files Lid Log File Infos 5 The default name of the new implementation 1s composed of the proje
105. ks of Mentor Graphics Corporation 3D Desion ABIST Arithmetic BIST Accelerated Technology AccuPARTner AccuParts AccuSim ADEPT ADVance ADVance MS ADVanceRFIC AMPLE Analog Analyst Analog Station Ares ARTerid ArtRouter ARTshape ASICPlan ASIC Vector Interfaces Aspire AuthEx press AutoActive AutoCells AutoDissolve AutoF ilter AutoPlow AutoLib AutoLinear AutoLink AutoLogic AutoLogic BLOCKS AutoLogic FPGA AutoLogic VHDL AutomotiveLib AutoPAR AutoTherm AutoTherm Duo Auto ThermMCM AutoView Autowire Station AXEL AXEL Symbol Genie BISTArchitect BLAST Blaze BlazeRouter Board Station Consumer Board Architect Board Designer Board Layout Board Process Library BoardSim Board Station BOLD Administrator BOLDBrow ser BOLD Composer BSDArchitect BSPBuilder Buy on Demand Cable Analyzer Cable Station CAECO Designer CAEFOR M Calibre Calibre DRC Calibre DRC H Calibre DESIGNrev Calibre CB Calibre PFRACTUREh Calibre FRACTURE Calibre PFRACTUREm Calibre FRACTURE Calibre PFRACTURER Calibre LITHOview Calibre LVS H Calibre MTflex Calibre OPCsbar Calibre OPCpro Calibre ORC Calibre PRINTimage Calibre PSMegate Calibre PSMcheck Calibre TDope Calibre WOR Kbench Calibre RVE Calibre MGC Calibre Interactive Calibre MDPview Calibre xRC CAM Station Capital Capital Analysis Capital Archive Capital Bridges Capital Documents Capital H Capital H the complete desktop engineer Capital
106. l synthesis pass uses pre layout timing estimates it is possible that small negative violates can be fixed in placement during Place Route Precision RTL Synthesis Users Manual 2003c Update1 2 19 March 2004 Synthesizing the Design Setting Up a Design and Compiling Large negative slack time If your design produces a negative slack time for critical paths that is 10 or greater than the overall cycle time you need to verify you are reporting a true critical path not a multicycle false path or invalid clock interaction and then analyze the elements within the critical paths Using the hints in the following two subsections you need to identify the HDL code that is causing the critical path and possibly make adjustments in the HDL code If your design is still not meeting performance requirements you can either loosen your timing constraints or re synthesis using a faster speed grade for the device If you are within 10 of your timing goals you may want to run the design through the vendor implementation tools to get more accurate post place route timing values Precision RTL Synthesis calculates delays using a conservative pre layout estimate If you are close to meeting your timing constraint according to Precision s estimate you may have actually met the timing constraint according to the accurate post layout value produced by the physical implementation tools To obtain the fastest design consider doing the following 2
107. l user interface modes Graphical User Interface GUD Tcl command line in the Transcript window or the shell window and Tcl scripts when running Precision in batch mode Precision provides Tcl commands that correspond to all of the Project Manager menus and Design Bar icons as well as other supporting commands The Tcl commands are detailed in Chapter 3 Commands in the Precision Synthesis Reference Manual Refer to Table 3 2 Project and File Management Commands Precision RTL Synthesis Users Manual 2003c Update 4 1 March 2004 The Project Manager Managing Projects Figure 4 1 shows an example of how the contents of a project are displayed in the Project Files pane of the Precision Design Center window The example project name is uart_top and it has 2 implementations uart_top_impl_1 and uart_top_impl_2 Figure 4 1 Organization of Project Files by the Project Manager 1a Project uart top Impl uart _top_impl_1 Multiple lt E Impl uart_top_impl_2 I E J Input Files plementations i i a Constraint Files Constraint Files 0 E uart_top_constraints sdc j 9 Script Files Script Files gt Sl Cutput Files Lal Log File RTL Schematic Technology Schematic 3 Area Report Timing Report All Synthesis and PnR Timing violation Report output and report files 3 Constraints Report Foi uart _top edf iF silinx Floorplanner tilings Timing Report ilinx Pad Report 7 yilin PAR Report
108. larLogic Expedition Explorer CAECO Layout Explorer CheckMate Explorer Datapath Explorer Lsim Explorer Lsim C Explorer Lsim S Explorer Ltime Explorer Schematic Explorer VHDLsim Expressl O EZwave FabLink Falcon Falcon Framework PastScan FastStart FIRE First Pass Design Success First Pass Success FlexSim PlexTest FOL Plow Definition Language FlowTabs FlowX pert FORMA FormalF mo FPGA Advantage FPG Advisor FPGA BoardLink FPGA Builder FPPGASim FPGA Station FPGA Xchange FrameConnect Fusion Galileo GateStation GateGraph GatePlace GateRoute Gemini GDT GDT Core GDT Designer GDT Developer GENIE Gen Ware Geom Genie HOL2Graphics HDL Architect HDL Architect Station HDL Assistant HDL Author HDL Designer HOL Designer Series HDL Detective HDL Inventor HDL Link HDL Pilot HDL Processor HDOLSim HDLWrite Hierarchial Injection Hierarchy Injection HIC rules Hardware Modeling Library HotPlot Hybrid Designer Hybrid Station HyperLinx HyperSuite IC Design Station IC Designer IC Layout Station IC Station Streamview ICbasic Cblocks Ccheck Ccompact ICdevice Cextract CGen Ceraph CLink IClister ICplan IERT Controller Leompiler Crules Ctrace C verify Cview ICX 1ICX Active ICX Plan ICX Pro IEX Sentry ICX Tau ICX Verify ICX Vision ICX Custom Model ICX Custom Modeling ICX Project Modeling ICX Standard Library IDEA Series Idea Station IKOS In All The Right
109. lculates the delay value of clocks generated by the DCM See the following figure for an example of the derived clock Derived Within the Precision tool you can specify constraints on clock inputs to a DCM If you specify global clock constraints on an input to the DCM for example Precision RTL Synthesis will propagate the timing constraints to the outputs of the DCM including transferring the proper constraints to the clock multiplier and divider ports The Precision tool uses a Common Timing Engine to construct a graph of all clocks that indicates the parent children clocks of every clock Every time any clock 1s updated with a lower clock frequency the parent and child clocks will be updated as well depending on their relationship For example Suppose you have a design that has DCM o p clocks CLKO and CLK2X whose parent clock is CLKIN If Precision RTL reports CLKIN to be run at 100Mhz then CLKO will also be run at 1OOMhz and CLK2X will be run at 200Mhz Displaying Derived Clocks within the Graphical User Interface The tool displays the design in the Design Input windows Once you load the design you set Architectural Constraints and compile the design Once the design 1s compiled the generated clocks display in the design window Clocks that were derived from the DCM are identified by the label Derived Clock To display information associated with the derived clock select the clock and hover the cursor over it Infor
110. lkl name myclk period 10 This will cause any register or input clock referenced by clk1 to reference the source of the timing path for the clock you have renamed myclk Specifying Clock Constraints Precision uses clock constraints to define the timing between registers Precision displays the auto detected clock sources in the clocks folder in the Design Hierarchy pane When a clock is not defined all combinational logic between the registers driven by the undefined clock is ignored during timing optimization Thus if you do not define any clocks Precision will not run timing analysis or attempt to increase the speed of your design As soon as you define a clock you have effectively constrained the combinational logic between all registers to one clock period as shown in Figure 3 2 Figure 3 2 The Clock Period Defines the Maximum Delay Between Flip Flops AM clock alleen lige i the maximum delay for eee T all logic between flip flops Precision RTL Synthesis Users Manual 2003c Update1 3 7 March 2004 Setting Timing Constraints Setting Constraints and Synthesizing To constrain a clock using the GUI follow the steps in Figure 3 3 Figure 3 3 Setting the Clock Constraints from the GUI Clock Constraints Port clk x lin YIRTES I 2V40ce144 6 Frequency 100 MHZ a Timing Constraints Design Hierarchy E E statemachine moore RT achine_impl 1 unsaved a Clocks Beri Clock Mam
111. look like the following gt set_false_path from U1 FFl1 clk to U1 FF2 data_in Setting Multicycle Paths Logic that you know will take more than one clock to propagate through is quite common When you set a multicycle constraint you identify a path to PreciseTime to prevent the tool from reporting invalid violations and to prevent timing optimization from wasting time and resources trying to correct valid but falsely reported paths Single point multicycle path definitions are much more efficient for PreciseTime to process both in terms of analysis time and memory utilization If you have a design with hundreds of multicycle paths it is sometimes worthwhile to see if a single point constraint would suffice Figure 3 9 Multicycle Path Defined Data only changes every Need to relax timing other clock cycle requirement for logic cloud to 2 cycles data valid for 2 clock cycles 2 To appropriately constrain the design in Figure Figure 3 9 you should place the following set_multicycle path command in the Master Constraint File set_multicycle_path from FF1 to FF2 value 2 Precision RTL Synthesis Users Manual 2003c Update1 3 17 March 2004 Setting Mapping Constraints Setting Constraints and Synthesizing Setting Mapping Constraints To get the best results from Precision RTL Synthesis you should verify the default assumptions that Precision makes during the synthesize process to meet your specif
112. mands The old commands and certain options for the setup_design command are now deprecated and are labeled as such in the command reference pages in the Precision RTL Synthesis Reference Manual Deprecation means they are being phased out Precision continues to support them at this time but support may be dropped in the future The table below lists the commands that deprecated and the new replacement commands Table 4 1 Deprecated Commands close_project or close_results_dir close_project or close_results_dir Many existing scripts were written to configure a design s inputs and settings as a means of saving time and eliminating errors Typically these script do nothing more than add input files Precision RTL Synthesis Users Manual 2003c Update 4 21 March 2004 Backward Compatibility with Pre 2003c Projects Managing Projects to the design choose technology settings set constraints and attributes and so on These scripts will run just the same as they did before The scripts that you might want to adjust are those that begin by calling set_working_dir The old behavior of set_working_dir was threefold set the input directory set the current working directory and set the results directory to the path specified with set_working_dir The three functions are now separate commands and you should call each command explicitly You will only call set_results_dir when you want your script to run without the Project Manager Furth
113. mation associated with the clock is display in a pop up window For example a derived clock might be named U_DCM_CLKO Note You cannot edit the constraints on a derived clock For a sample of how a design and a derived clock appear in the graphical user interface see the following figure Precision RTL Synthesis Users Manual 2003c Update1 3 5 March 2004 Setting Timing Constraints Setting Constraints and Synthesizing El dem_2x struct EF dem_2x struct gal Clocks ee OOCL Derived Clock Hame W_DCM CLEO Hame W Doms CLES H E Ports ce f F Period 10 Peri ads LO Orfeet O H E Nets offeet Clack High Time i Clack High Time amp a LoInstances etesk Demain GiecskDema H E Instances closk Domain CloskDoma S ives Sy ere Pott TE amp D ae CLEO Lir ezt in OOT PTIT mire Direction OUTPUT Fir OC an the soe i aar s CLES e CLE FEE Pin Gonnecttion CLEO gt CLE_FEE Commands for Derived Clocks The following commands relate to derived clocks find_clock derived set_false_path set_multicycle_path remove_propagated_clock report_timing For more information see the text associated with these commands in the Precision Synthesis Reference Manual Report Timing and Clock Names It is a general practice within the tool for clocks to share the same name as the object on which they are set If a port and clock have the same and you enter the report_timing command then the tool applie
114. mmenti an mopem entao seinh aan EE EAE EE 4 15 IV Precision RTL Synthesis Users Manual 2003c Update March 2004 Table of Contents Table of Contents cont eena a Rt restates eee R E 4 17 Creating a Script irom a Precision log PING iso ccc conc inwtnonsnccatbeaeunanwasaandivopeindbinaNeenaqiceniesincieans 4 17 Scripts for Creating New Projects or Reusing Existing Projects cc cccesesssceceeeeceeeeneeees 4 18 PE FOU e iA 4 20 Actions to Take if the Project Input Directory or Input Files Move ce eeeeeeeeeeeeees 4 20 Backward Compatibility with Pre 200 36 Proje is issicecacsccdccstirsiseaneietsternexaleesieretcindeaeacenneianss 4 2 Chapter 5 Bed a ke en oI o E E E Occ AAE EE E E een eee N eee Se eee eee etre 5 1 Pa Tar GEE Up a cede N 5 1 TEV TO RTL S e e EEE O En R TETN 5 2 venne me eeno Se me a OF itn meer eee ner TT Serer heme n tt te mere trate nee 5 3 Mie me CE Pati enem eiiean ET RE 5 4 Und rstanding the Left Mouse Button ACHONS piace insarrieneremnnrinnanenmarainene 5 5 Pe De hte ER 5 5 C O A a AE E E E EE 5 5 C a A A E 5 6 E 1 i EEE 5 6 C O E E A 5 6 Moving Up and Down the Hierarchy nsssesssooeersssssssseeerrrssssssseserressssssssseressssssseserersssssss 5 7 Parmi Fowadi aad Paame BEE erneak EE E 5 7 fbeste Tug Beare Ce Bd ol odli Fo 4 TE ee en nee eee er a aE 5 8 Ne ee ire cece cee anaatimeseenuende 5 8 Conteris an Object 1 ING Schematie VY 16 Wiciecstcssenserersernrommumoninveestiomemamae
115. n in the top level design you can set a dont_touch attribute on the technology mapped blocks and only optimize the level above Controlling Fanout on Data Nets Fanout is the maximum number of pins being driven by an instance or top level port High fanout nets can potentially cause significant delays on wires and or make a net un routable On a critical paths high fanout nets can cause significant delays in a single net segment and cause the timing constraints to fail To limit these issues technology libraries have a global fanout value set in the library with possible individual overrides on specific cells designed for high fanout situations e g global buffers Precision RTL Synthesis Users Manual 2003c Update1 3 23 March 2004 Setting Other Constraints Setting Constraints and Synthesizing To eliminate routability and timing issues associated with high fanout nets Precision also allows you override the library default value on a global or pre net basis You can override the library value by setting a max_fanout attribute on the net Depending on the technology Precision can address fanout violations by splitting the net and replicating the driving cell If replication is not possible e g the driver is an input port Precision will add buffers By using the technology default values with selective user defined overrides Precision can control the fanout on a net 3 24 Precision RTL Synthesis Users Manual 2003c Update March 20
116. n menu item to open the Select Implementation dialog box and choose an implementation as shown in Figure 4 12 In the Set Implementation Comment dialog edit the comment string and click OK to set the comment property The comment setting is immediately saved to the project implementation file in your file system To view an implementation s comment hover the curser over the implementation in the Project Files pane of the Design Center window and a popup box will display the comment The popup box will display only if the comment property has been set Precision RTL Synthesis Users Manual 2003c Update 4 15 March 2004 Using the Project Manager Interactively Managing Projects Figure 4 12 Menu and Dialog for Editing Implementation Comment Property Project uart_top J Impl uart_top_impl_1 C Impl uart _xilinx Setup Design Ctrl T Impl uart_top_alternate_1 Add Input Files Ctrl 4 Cy Input Files Remove All InpubliGonstraint Files Script Files Gtr DEL Constraint Files Compile no Script Files Synthesize A A Output Files Place amp Route had Log File Infos 10 Save Implementation Copy Implementation Rename Implementation Set Implementation Comment Delete Implementation Set Implemenation Comment Set Comment for implementation Wart top alternate 1 Experimental Cancel Setting an Implementation Comment from the Command Line To edit an implementation comment property use the set_imp1l_property comm
117. n the warranty period This warranty shall not be valid if Software has been subject to misuse unauthorized modification or installation MENTOR GRAPHICS ENTIRE LIABILITY AND YOUR EXCLUSIVE REMEDY SHALL BE AT MENTOR GRAPHICS OPTION EITHER A REFUND OF THE PRICE PAID UPON RETURN OF SOFTWARE TO MENTOR GRAPHICS OR B MODIFICATION OR REPLACEMENT OF SOFTWARE THAT DOES NOT MEET THIS LIMITED WARRANTY PROVIDED YOU HAVE OTHERWISE COMPLIED WITH THIS AGREEMENT MENTOR GRAPHICS MAKES NO WARRANTIES WITH RESPECT TO A SERVICES B SOFTWARE WHICH IS LICENSED TO YOU FOR A LIMITED TERM OR LICENSED AT NO COST OR C EXPERIMENTAL BETA CODE ALL OF WHICH ARE PROVIDED AS IS 5 2 THE WARRANTIES SET FORTH IN THIS SECTION 5 ARE EXCLUSIVE NEITHER MENTOR GRAPHICS NOR ITS LICENSORS MAKE ANY OTHER WARRANTIES EXPRESS IMPLIED OR STATUTORY WITH RESPECT TO SOFTWARE OR OTHER MATERIAL PROVIDED UNDER THIS AGREEMENT MENTOR GRAPHICS AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND NON INFRINGEMENT OF INTELLECTUAL PROPERTY LIMITATION OF LIABILITY EXCEPT WHERE THIS EXCLUSION OR RESTRICTION OF LIABILITY WOULD BE VOID OR INEFFECTIVE UNDER APPLICABLE LAW IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS BE LIABLE FOR INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES INCLUDING LOST PROFITS OR SAVINGS WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY EVEN IF MENTOR GRAPHICS OR I
118. nd set_output delay commands are defined with respect to a defined clock Clocks can also be used in exception commands to specify a group of endpoints For example the command set_false_path from c1k1 will remove timing violations which begin at all registers clocked by that particular clock The report_timing command also accepts clock names which are used similarly Note If a clock and a port in the design have the exact same name an ambiguity occurs In most cases the Precision Synthesis tool will resolve this ambiguity in favor of the clock name You may need to pick unique names for your clocks to allow some operations Signals that require clocks are automatically found by the system Before clocks are defined clocks are displayed in the design browser with no properties This is done to help you find the points that must be constrained with clock definitions Clocks will be traced back to primary design ports when possible If clocks are gated sometimes this is impossible so in this case internal signals will appear in the clock folder 3 4 Precision RTL Synthesis Users Manual 2003c Update1 March 2004 Setting Constraints and Synthesizing Setting Timing Constraints Derived Clocks The Precision tool automatically generates derived clocks for clocks that feed a Xilinx Digital Clock Manager DCM When a clock feeds a DCM the DCM has clock output such as clk0O clk2 clkfx which clock other registers Precision automatically ca
119. o ensure that the product manuals come up full size you should verify set the Acrobat Default Zoom preference to Actual Note File gt Preferences gt General Magnification Default Zoom Actual 1 8 Precision RTL Synthesis Users Manual 2003c Update March 2004 Chapter 2 Setting Up a Design and Compiling Invoking Precision RTL Synthesis You can run Precision RTL Synthesis from the Graphical User Interface GUI or from a Shell command line Typically you will use the GUI while you are learning to use the tool and for setting up your initial synthesis runs Once your design is setup and the initial constraints are specified you can easily generate a Project File and a Master Constraint File You will typically do the remaining synthesis runs by opening the Project File and making minor adjustments to the Master Constraint File Invoking the Precision GUI You invoke the Precision RTL Synthesis GUI by entering the precision command from a Windows shell or a Unix shell In a Windows environment you can optionally create a Shortcut on your Desktop and set the Shortcut Properties similar to that shown in the following figure General Shortcut Security precizio Edme Enter precision_gui instead of precision to eliminate the shell from the desktop Target type Application Target location bin C precision shige home bin precision gui ere Target R
120. o tools XDB Considerations Precision RTL Synthesis can only read and properly interpret an xdb file that was first generated by Precision RTL Synthesis Precision RTL Synthesis Users Manual 2003c Update 2 11 March 2004 Setting up the Design Environment Setting Up a Design and Compiling SDC considerations By default Precision RTL Synthesis saves all timing constraints and attributes generated from the GUI in a file named lt design_name gt sdc located in the current implementation directory If you added any additional constraints or attributes via the command line you must manually add these commands to the Master Constraint File if you want them included in the next synthesis run Setting Synthesis Options You direct and refine the behavior of the synthesis process by selecting options from the pulldown menu Tools gt Set Options The options are described online if you click on the HELP button at the bottom of each dialog box The following list describes some of the common options that you should verify the default settings Set State Machine encoding You can allow Precision Synthesis to automatically select a Finite State Machine encoding style for you the default or you can specify a specific encoding style Precision Synthesis also supports the ability to create a Safe State Machine A safe state machine is a state machine in which a transition will always be to a valid state Refer to the Precision Synthesis RTL
121. of a particular class e g multiple output buffers for different voltage standards the technology vendor will specify a default IO pad to use for that class of IO pad Although moving registers into the IO ring can decrease the input to register and register to output delay it can also increase the delay from the complex IO to the registers in the core of the chip You should consider this trade off and make sure that you are not trading off one timing problem for another 3 18 Precision RTL Synthesis Users Manual 2003c Update 1 March 2004 Setting Constraints and Synthesizing Setting Mapping Constraints If these IO assignments do not meet your design constraints then you can override the default assignments by adding attributes to the ports or with some vendors you can manually instantiate the IOs in your design Since each technology has different constraints on the usage of complex I Os for manually assigned I Os you are responsible for the validity of the output design Precision does not preform checks to verify that instantiated IO cells meet the constraints of the technology Table 3 2 Handling Different IO Pad Scenarios Situation To prevent Precision from adding any IO pads To prevent Precision from adding IO pads ona top level port To assign a non default IO pad to a top level port To force the first register in the path into the Complex IO To infer a complex IO when the associated register is not in t
122. oj_name folder Sproj_folder new_impl name Simpl_name configure settings set input dir Sinput dir add_input_file setup_design setup_place_and_route produce results compile synthesize place_and_route save results to impl folder save_impl results are now in directory Sproj_folder Simpl_name 4 18 Precision RTL Synthesis Users Manual 2003c Update March 2004 Managing Projects Using the Project Manager Interactively Script for Reusing an Existing Project You would use the following script if you have a project file and an impl folder and you intend to build the project and impl once and then reuse them each time The script assumes the project exists opens it and then uses it This may be preferable if you intend to maintain the project and its settings For example if you want to set a constraint you open the project in the GUI set the constraint save the project then copy off the constraints file to a location where it can be preserved and reused by others Tcl script to open project and produce results parameters set proj folder c temp projects set proj_name a_project set impl_name a_project_impl_1l open project and activate impl open_project Sproj_folder Sproj_name psp activate_impl impl Simpl_name produce results compile synthesize place_and_route save results to impl folder save_impl results are now in directory Sproj_folder Simpl_name Script for Creating a Project and Reusin
123. ollowing are service marks of Mentor Graphics Corporation A World of Learning ADAPT AppNotes Assess2000 BIST Compiler BIST In Place BIST Ready Concurrent Board Process DirectConnect ECO Immunity EDGE Engineering Design Guide for Excellence Expert2000 FastTrack Consulting IntraStep ISD Creation It s More than Just Tools Knowledge Center Knowledge Sourcing Mentor Graphics Support CD Mentor Graphics SupportBulletin Mentor Graphics SupportCenter Mentor Graphics SupportPax Mentor Graphics SupportNet Email Mentor Graphics SupportNet FTP Mentor Graphics SupportNet Telnet Mentor Graphics We Mean Business MTPI Online Knowledge Center OpenDoor Reinstatement 2000 SiteLine2000 SupportNet KnowlegeBase Support Services BaseLine Support Services ClassLine Support Services Latitudes Support Services OpenLine Support Services PrivateLine Support Services SiteLine SupportServices TechLine Support Services RemoteLine and VR Process Mentor Graphics trademarks may only be used with express written permission from Mentor Graphics Fair use of Mentor Graphics trademarks in advertising and promotion of Mentor Graphics products requires proper acknowledgement Nutcracker is a registered trademark of MKS Mentor sometimes refers to products by using trademarks Marks owned by a third party and such use is not an attempt to indicate Mentor Graphics as a source of that product but is intended to indicate a product from or associate
124. on draw a line or bounding box then release the button The direction of the line indicates what action you want to take For zooming strokes the length of the line controls the amount of zoom The longer the line the more zoom Zooming to Area Draw a bounding box with the Left Mouse Button r Brisas E Ports C Nets L Cells ul statemachine 40 modgern_sub_6 sub t J modgen_mult_r mult J modgen_add_ add_ M4 TORS Precision RTL Synthesis Users Manual 2003c Update1 5 5 March 2004 Traversing the Schematic with Strokes Viewing a Schematic Zooming Out Draw a line lower left to upper right Pa Length determines amount of zoom Zooming In Draw a line upper right to lower left S Length determines amount of zoom Zooming to Fit Draw a line lower right to upper left 5 6 Precision RTL Synthesis Users Manual 2003c Update1 March 2004 Viewing a Schematic Traversing the Schematic with Strokes Moving Up and Down the Hierarchy Double click Gr up _ to descend to ascen Paging Forward and Paging Back lt q If you have a multi page schematic you can move to the next page by using a horizontal stroke left to right then move back to the previous page with a horizontal stroke lt right to left If there is a multi page schematic the toolbar indicates page 1 of x where x indicates the number of pages in the schematic
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126. pdate March 2004 Managing Projects Using the Project Manager Interactively Opening a Project from the Command Line To open a project by using the Tcl command line interface call the open_project command and specify the full path to a project file psp The following command example open the project uart_top psp and sets the current working directory to g sb project uarts Open project g sb project uarts uart top Ps3p Closing a Project The Precision GUI provides the Close Project command in 3 places as an icon in the Project pane of the Design Bar on the File gt Close Project pulldown menu and on the popup menu when you right click on the project object in the Project Files pane of the Design Center window If the active implementation has unsaved changes Precision will prompt you to save those changes before closing the project Figure 4 6 shows the additional project management icons that appear in the Project pane of the Design Bar when a project is open It also shows the project popup menu Figure 4 6 Project Manager Icons on the Design Bar fs uart_top Mentor Graphics Precision RTL Synthesis Design Center File view Tools Window Help Design Hierarchy gt oe Impl uart top Se aia ta E Input Files Mew Project New Implementation C Script Files lL Output Files os Lad Log File Infos 9 Ha Open Project 7 Close Project a You can also close the pro
127. ranecript Pg Design Center Pg Design Brow Input Directory project Simplernath Precision RTL Synthesis Users Manual 2003c Update1 5 9 March 2004 Traversing the Schematic with Strokes Viewing a Schematic Viewing the Internals of a Hierarchy Block The Schematic Viewer has the capability to display the internal schematic of a block in the context of the current schematic To display the internal schematic do the following 1 Right click anywhere in the schematic window and select Show Hierarchy Show Hierarchy Hierarchy block Hierarchy block after as Show Hierarchy 5 10 Precision RTL Synthesis Users Manual 2003c Update March 2004 Viewing a Schematic Traversing the Schematic Using Keyboard shortcuts Traversing the Schematic Using Keyboard shortcuts You can click on the Design Bar icons to accomplish many of the actions described in this section However you can also use the keyboard to traverse a schematic The following keyboard shortcuts for Precision s Schematic Viewer are based on the shortcuts from the Block Diagram editor in HDLDesigner Zoom if Views entire diagram Scroll wine up SCO eirda di Sertoli werneclaw teft Scroll window tight scroll window view left fone window width ocroll window view right one window width Next page Page DONT Previous page Precision RTL Synthesis Users Manual 2003c Update 5 11 March 2004 Using the Cross Probe
128. recision log File 4 17 Index 4 Creating New Projects or Reusing Existing Projects 4 18 Search Path for include files 2 9 for VHDL files 2 9 set_attribute command 3 18 3 19 set_false_path command 3 16 set_input_delay command 3 11 set_input_file command 2 7 set_output_delay command 3 14 Setting synthesis options 2 12 the default Input Delay 2 6 the default Output Delay 2 6 the global frequency 2 6 Setting Constraints on false paths 3 15 Setting the Input Directory 4 7 Setting Up the technology 2 5 setup_design command 2 6 Strategy for obtaining fastest design 2 20 Synthesis setting options 2 12 T Tcl startup scripts 2 13 Technology Library loading for a synthesis run 2 5 Technology Schematic viewing 5 3 Temp Directories 4 7 Timing analysis Asynchronous signals 2 20 Incorrect constraints 2 21 Multi Cycle paths 2 20 Transparent latches 2 14 Precision RTL Synthesis Users Manual 2003c Update March 2004 Index U Use Clauses 2 10 V Verification Reports see Reports VHDL synthesis 2 13 Verilog Full Case 2 11 Parallel Case 2 11 Verilog 2001 Support 2 11 VHDL attributes 2 18 Index cont Examining synthesis results 2 13 VHDL Files specifying search path for 2 9 VHDL Libraries reading 2 10 VHDL Packages reading 2 10 W Work Library specifying 2 8 X Xilinx using UCF file as input 2 17 Xilinx Virtex memory mapping 3 21 Preci
129. rictions set forth in the license agreement under which Software was obtained pursuant to DFARS 227 7202 3 a or as set forth in subparagraphs c 1 and 2 of the Commercial Computer Software Restricted Rights clause at FAR 52 227 19 as applicable 13 14 15 16 17 Contractor manufacturer is Mentor Graphics Corporation 8005 SW Boeckman Road Wilsonville Oregon 97070 7777 USA THIRD PARTY BENEFICIARY For any Software under this Agreement licensed by Mentor Graphics from Microsoft or other licensors Microsoft or the applicable licensor is a third party beneficiary of this Agreement with the right to enforce the obligations set forth in this Agreement AUDIT RIGHTS With reasonable prior notice Mentor Graphics shall have the right to audit during your normal business hours all records and accounts as may contain information regarding your compliance with the terms of this Agreement Mentor Graphics shall keep in confidence all information gained as a result of any audit Mentor Graphics shall only use or disclose such information as necessary to enforce its rights under this Agreement CONTROLLING LAW AND JURISDICTION THIS AGREEMENT SHALL BE GOVERNED BY AND CONSTRUED UNDER THE LAWS OF OREGON USA IF YOU ARE LOCATED IN NORTH OR SOUTH AMERICA AND THE LAWS OF IRELAND IF YOU ARE LOCATED OUTSIDE OF NORTH AND SOUTH AMERICA All disputes arising out of or in relation to this Agreement shall be submitted to the exclusive jurisdicti
130. rilog design the Full Case switch tells Precision that all conditions of the case statement are specified If a default assignment is not used for example then this option prevents the implementation of extraneous latches This switch is set from the pulldown menu Tools gt Set Options gt Input gt Verilog Parallel Case When using a CASE statement in your Verilog design and the case conditions are mutually exclusive a multiplexer is often the preferred implementation instead of priority encoding a state machine You should select Parallel Case to direct Precision RTL Synthesis to treat case conditions as mutually exclusive and implement a multiplexer logic structure This switch is set from the pulldown menu Tools gt Set Options gt Input gt Verilog Verilog 2001 Support Precision Synthesis provides support for Verilog 2001 constructs Refer the to Precision RTL Synthesis Style Guide for details EDIF Considerations Precision RTL Synthesis only supports the reading of EDIF files that were generated by Mentor Graphics synthesis tools or FPGA place route tools If Precision determines that the EDIF file 1s from Xilinx CoreGen Precision RTL Synthesis automatically applies a dont_t ouch attribute to the instantiated CoreGen block Although Precision RTL Synthesis supports the EDIF format you may not be able to read EDIF from other tools e g schematic capture because the cell sets and pin names may not match between the tw
131. rt File in the Design Center window brings up the the content of that file in a separate window Constraints that are Set in the GUI are Saved to an SDC File The synthesis process is constraint driven and your objective is to create a Master Constraint File that can be read as part of the Input File List The constraint file format is Synopsys Design Constraints SDC One of the easiest ways to create an initial constraint file is to manually set constraints on design objects in the Design Hierarchy window As you do so the constraints are automatically saved to a generated sac file and placed in your implementation directory For future synthesis runs you can include this generated constraint file as one of your input files The Project Directory and the Results Directory Generally speaking a project directory and a results directory are user specified locations where Precision saves output files during a particular session A project directory is created by the Precision s Project Manager when you create a new project On the other hand if you want to work without using the Project Manager you must set the results directory location by calling the set_results_dir command In this case all output files go into the results directory The structure and organization of each type of output directory is different and reflects purpose of the directory The purpose of the project directory is support the organizational functions of Prec
132. ry The project directory contains the project file psp Each implementation is stored in its own subdirectory that has the same name as the implementation Inside each implementation directory is the implementation file psi The temporary directory is created each time a project implementation is activated and deleted when it is deactivated when the implementation is closed or another implementation is activated or created You can rename implementations to more descriptive names if you wish Refer to Renaming an Implementation for instructions Precision RTL Synthesis Users Manual 2003c Update1 4 5 March 2004 Using the Project Manager Interactively Managing Projects Figure 4 4 Hierarchical Project File Structure Master project file created Project Folder a by new_project command lt project_name gt psp precision log 4 lt project_name gt _impl_1 lt project_name gt _temp_1 precision log lt project_name gt _impl_1 psi lt output_file gt Project s temporary lt output_file gt results directory Implementation directory with user specified name lt impl_name gt Default Implementation Pe Implementation Log File Session log file Implementation File created by the project In the example above the master project folder contains the project file psp The implementation directories lt impl_name gt and lt project_name gt _impl_1 are where work is performed
133. s and counters in transcript after the pre_optimize operation Precision RTL Synthesis utilizes special mapping algorithms to target counters and memories from your HDL code If Precision does not infer the correct number of RAMs ROMs or Counters refer to the Precision RTL Synthesis Style Guide to verify that the HDL code matches the coding style that Precision expects For RAMs that do not infer properly try to cut and paste one of the examples For counters verify that the reset condition is either all zeros or all ones The Precision RTL Synthesis counter operator only has an asynchronous reset or set no asynchronous load You can work around this issue by muxing the data and reset value If your compiled design meets expectations you can continue by setting constraints on your design as described in the next chapter You may also want to save the present state of the implementation Simply right click on the implementation in the Project Files pane of the Design Center window then choose Save Implementation from the popup menu If your compiled design does not meet your expectations you will probably need to make changes to your HDL source code and follow the recommendations in the Precision RTL Synthesis Style Guide 2 16 Precision RTL Synthesis Users Manual 2003c Update March 2004 Setting Up a Design and Compiling Setting Timing and Design Constraints Setting Timing and Design Constraints After the design has been compile
134. s the command with regard to the clock and not on the physical item associated with the clock There are extra steps you need to take when a clock and a port have the same name so that the tool can provide the correct output information using the report_ timing command or when you use the set_false_path command For example let s assume that you have a design where both the port and clock are named CLK1 In this case you would need to do the following 1 You should rename the clock using the create_clock command and also specify the desired clock period 2 You should constrain the clock port like a data port with the appropriate input delay using the set_input_delay command Entering report_timing from clk1 should report 3 6 Precision RTL Synthesis Users Manual 2003c Update 1 March 2004 Setting Constraints and Synthesizing Setting Timing Constraints timing paths that begin at the primary input clk1 and end at the constrained data pins on flip flops It is likely that paths won t fit this criteria The Precision tool would only report this path if clk1 had a set_input_delay constraint defined on it or if the max_delay constraint was defined with clk1 in the from list Example If you have both a clock and a port named CLK1 and you want to set a false path on the PORT named CLK1 then you need to issue a create clock command to rename the clock and to specify the period setting for this clock create_clock c
135. selecting the Run Script option See the Scripts for Creating New Projects or Reusing Existing Projects section for information on scripts you can use to create new projects reuse existing projects and produce results Precision RTL Synthesis Users Manual 2003c Update1 4 17 March 2004 Using the Project Manager Interactively Managing Projects Scripts for Creating New Projects or Reusing Existing Projects Some users like to use scripts to automate commonly performed tasks The following are examples of scripts that can be used to 1 create new projects 2 reuse existing projects or 3 create a script that combines the two methods Script for Creating a New Project The sample script below clears the project and its impls and then creates the a new project and its impls You would use this script if you intend to rebuild the project and go through the entire flow every time you run the script This may be preferable if you don t intend to reuse the project but only intend to maintain your script For example if you want to set a constraint you ll add a tcl command to do this to your script Tcl script to clean up create project and produce results parameters set proj _folder c temp projects set proj_name a_project set impl_name a_project_impl_1l set input_dir c HDL clean up file delete force Sproj_folder S proj_name psp file delete force Sproj_folder Simpl_name create project and impl new_project name Spr
136. sion RTL Synthesis Users Manual 2003c Update1 March 2004 Index 5 Index Index cont Index 6 Precision RTL Synthesis Users Manual 2003c Update March 2004 End User License Agreement IMPORTANT USE OF THIS SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS CAREFULLY READ THIS LICENSE AGREEMENT BEFORE USING THE SOFTWARE This license is a legal Agreement concerning the use of Software between you the end user either individually or as an authorized representative of the company acquiring the license and Mentor Graphics Corporation and Mentor Graphics Ireland Limited acting directly or through their subsidiaries or authorized distributors collectively Mentor Graphics USE OF SOFTWARE INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH IN THIS AGREEMENT If you do not agree to these terms and conditions promptly return or if received electronically certify destruction of Software and all accompanying items within five days after receipt of Software and receive a full refund of any license fee paid END USER LICENSE AGREEMENT GRANT OF LICENSE The software programs you are installing downloading or have acquired with this Agreement including any updates modifications revisions copies documentation and design data Software are copyrighted trade secret and confidential information of Mentor Graphics or its licensors who maintain exclusive title to all Softwar
137. sion prompts you to either save or discard the changes before closing it If the source implementation name does not end with _ lt n gt where lt n gt is an integer Precision will append _1 to the new implementation name Note Copying an Implementation from the Command Line When calling the copy_imp1 command if you don t specify the name for the new implementation a default name is provided The default name is composed of the source implementation name but its _ lt m gt suffix is incremented to the next higher integer that makes the name unique within the project Alternatively you can specify a name for the new implementation The name you choose is arbitrary The following copy_imp1 command example will copy the implementation named uart_top_imp1_2 to anew implementation named uart_top_alternative Any unsaved work in the active implementation is discarded The new implementation is automatically activated If you want to save the changes call the save_imp command copy_impl name uart_top_alternative from uart_top_impl_2 discard You can use get_project_imp1s to get a list of all implementation in the current project Commenting an Implementation Each implementation has a comment property which takes a string value To edit the comment property right click on an implementation and choose Set Implementation Comment from the popup menu Alternatively choose the File gt Comment Implementation pulldow
138. specify the Output Delay with the set_output_delay command and specify the Input Delay with the set_input_delay command To describe a path delay from a level sensitive latch you should use the level_sensitive option Output Delays must be obtained from the system designer based on the chip environment described in the system functional spec If you don t know the Output Delay it is common to specify zero delay at first to ensure that the circuit successfully completes Place amp Route On future synthesis runs you can tighten up the Output Delays to more closely model the real environment This is a much better technique than leaving Output Delays undefined If you are you manually entering a set_output_delay command into the Master Constraint File you can use wildcards with the get_ports command to simplify the specification of external delays on bus pins For example gt set_output_delay clock clkl 6 get_ports data_out And you can utilize the all1_outputs command to set a default value on all top level output ports gt set_output_delay clock sysclk 3 all_outputs Setting False Paths False paths are design paths that you want Precision to ignore for timing optimization purposes Timing optimization focuses it s efforts on paths in the design that violate timing constraints If a path is seen in violation but is in fact not a problem then Precision RTL Synthesis will waste time trying to fix the false violation In a
139. t argument can be any name that you want If two clocks have the same domain name they are modeled as synchronous If no lt domain_name gt 1s specified the domain name ClockDomainO is used Precision RTL Synthesis Users Manual 2003c Update1 3 9 March 2004 Setting Timing Constraints Setting Constraints and Synthesizing Other tools that use SDC constraints may require you to use False Path definitions to model asynchronous clocks Although Precision RTL Synthesis supports this method it is much less efficient in terms of runtime and memory utilization For large designs it is well worth the effort to convert False Path definitions to domains Specifying Input Delay What is Input Delay Input Delay is the delay consumed outside of the current design before a data signal arrives at the input port or pin Input Delay is equivalent to the term arrival time that may be used in other Mentor Graphics tool environments As shown in the following illustration if the reference clock period is 10 ns and the Input Delay is specified as 6 ns then Precision RTL Synthesis will constraint the combinational path from the input port dat a_in to the first register to 4 ns minus the register setup time Figure 3 4 Input Delay Defined input delay 6 ns constraint outside ae virtual circuit current design data_in clock period 10 ns set_input_delay clock clkl 6 data_in 3 10 Precision RTL Synthesis Users Manual
140. t found the directories specified in the pulldown menu Tools gt Set Options Input are searched As soon as the file 1s found the search ends Searching for VHDL files When the file being added is compiled and it references a VHDL library or a package that has not yet been compiled a search is conducted for this package file by that library or package name so it can be compiled first Assume for example that this input file contains the following the clause use lib my_package all When the file is compiled Precision RTL Synthesis looks in the library work to see if my_package has been compiled If not a search begins in the directory where this input file resides then the search directories that are specified for this file The search continues in the global directories that are specified in the pulldown menu Tools gt Set Options Input and finally the directory lt precision install directory gt pkgs techdata vhdl is searched As soon as the file is found the search ends the package file is compiled and the specified input file is compiled If the package file 1s not found Precision RTL Synthesis issues an error message Precision RTL Synthesis Users Manual 2003c Update1 2 9 March 2004 Setting up the Design Environment Setting Up a Design and Compiling VHDL Considerations Before you use Precision to perform VHDL synthesis you should already have a good understanding of the syntax and semantics of VHDL If your desi
141. ted only the project is created You can create an implementation later by calling the new_impl command 4 4 Precision RTL Synthesis Users Manual 2003c Update March 2004 Managing Projects Using the Project Manager Interactively New Project and Implementation Figure 4 3 Newly Created Project and Implementation Fey Hie View ools window Help jor x O cS mele e leama 2 v xilinx VIRTEXAL 2W40cs144 6 Frequency 50 MHZ Project Files Design Hierarchy Ella Project project_s ELF uart NTERFACE_ RTL Aa Impl project_3_impl H E Clocks H 6 Input Files I Ports Add Input Files Si Constraint Files j Nets EE uart constraints J Instances I Script Files I Output Files D setuo Design i Q x 4 N Vieng k TF Compile ah EF hiia z a synthesize Design Analysis As the project is created the project directory structure is also created in the specified Project Folder of your file system All Project Manager commands operate directly on the project files and folders in your file system No save project command exists Note that the actions performed by your synthesis design work files output to the implementation folder are not automatically saved to the implementation directory but are held in a temporary directory in the project folder Refer to Saving the Active Implementation on page 4 11 for more information Figure 4 4 shows the file structure of a project directo
142. ter v line 638 Warning start_dir_ras_tmp is not always assigned latches could be needed Warnings about latches may be given when Precision inserts transparent latches for combinational processes This circuitry is inferred from code the lack of else statements typically that does not account for all the possible conditions within a conditional construct Precision infers that it needs to store the states for these conditions which results in unexpected circuitry Messages about parallel case arbiter v line 1028 Warning case choices are not mutually exclusive parallel_case pragma may induce simulation mismatch Warnings about parallel case may be given when Precision encounters case structures that you have specified as having conditions that are not to be prioritized during synthesis This can lead to simulation mismatches Precision RTL Synthesis Users Manual 2003c Update March 2004 Setting Up a Design and Compiling Compiling the Design Messages about black boxes Warning cell xcve DLL INTERFACE marked black box Make sure that the black boxes represent empty modules for incremental synthesis or vendor cell instantiation use the Area Report to examine results Otherwise these messages indicate that Precision could not find certain cells in the design If the design is read in but you see unexpected black boxes on technology cell instantiations verify that the cell and port names in the HDL code matc
143. thesis will not move tristate drivers across hierarchy because it would require changing the port interface on the hierarchical block to pass the enable signal You should also be aware of whether your target technology has tristate cells available internally and or in the IO ring For example Altera technologies only have tristates on the IO ring no internal tristates The entire design hierarchy can be controlled by applying the hierarchy attribute to the top level of the design and then compiling the design Then in the Design Center window you can right click on the top level and choose either Flatten Hierarchy or Preserve Hierarchy To flatten preserve one hierarchical block in the design select the block then right click and select Flatten Hierarchy or Preserve Hierarchy Protecting Blocks from Change dont_touch You may have portions of your design that have been hand implemented and you want to prevent Precision RTL Synthesis from performing any optimizations on those blocks or instances For example you would not want Precision to optimize an technology specific IP blocks e g CoreGen or ACTGen cells or you may want to create a fast transition clock signal To do this you could specify the buffer as a technology instantiation and retain it through optimization This method of protecting hierarchy is also very useful when you are gluing lower level blocks together into a larger design You can optimize a low level block the
144. thodology is to use a text editor to manually copy and paste the new or modified constraints to the Master Constraint File For the purpose maintaining the integrity of the sdc file the only time the Precision GUI will save constraint settings in the sdc file is when you apply the constraints to the in memory RTL design If you add or edit constraints on the gate level in memory design your changes are applied to the design but not saved in the sac file For your convenience the Design Hierarchy pane of the Design Center window always displays the RTL design To view a gate level design after synthesizing double click on the Technology Schematic file in the Project Files pane of the Design Center window Likewise when you manually enter constraints into a sac file be sure to use the design option that is available on all constraint related commands That option takes one of two arguments rtl or gatelevel that specifies the design file to which the constraint will be applied The default value is rtl Continually managing the Master Constraint File is a primary task and you should be diligent to maintain the accuracy and content of the file To properly edit the file you ll need to learn the syntax of the SDC commands These commands are fully documented in the section titled Commands in the Precision Synthesis Reference Manual In addition examples of SDC commands will be presented in this Chapter Setting Timing Constra
145. tion and testing you will send to Mentor Graphics a written evaluation of the Beta Code including its strengths weaknesses and recommended improvements You agree that any written evaluations and all inventions product improvements modifications or developments that Mentor Graphics conceives or made during or subsequent to this Agreement including those based partly or wholly on your feedback will be the exclusive property of Mentor Graphics Mentor Graphics will have exclusive rights title and interest in all such property The provisions of this subsection shall survive termination or expiration of this Agreement RESTRICTIONS ON USE You may copy Software only as reasonably necessary to support the authorized use Each copy must include all notices and legends embedded in Software and affixed to its medium and container as received from Mentor Graphics All copies shall remain the property of Mentor Graphics or its licensors You shall maintain a record of the number and primary location of all copies of Software including copies merged with other software and shall make those records available to Mentor Graphics upon request You shall not make Software available in any form to any person other than employees and contractors excluding Mentor Graphics competitors whose job performance requires access You shall take appropriate action to protect the confidentiality of Software and ensure that any person permitted access to Software does not
146. tions in the project that you can rename see Figure 4 10 Figure 4 10 Select Implementation Dialog Box Select Implementation x Select an implementation uart_top_impl_ uart_top_impl_2 uart silin When you OK the Set Implementation Name dialog box the name change appears in the Project Files pane of the Design Center window Precision also immediately renames the implementation folder and the implementation file ps1 in the file system Any unsaved work is retained in the temporary directory and will be saved to the renamed directory when you save the implementation Renaming an Implementation from the Command Line An implementation s name is actually a property of the implementation To change that property use the set_impl_property command The following example sets the name property of implementation uart_top_imp1_2 to uart_top_alternate_1 If you do not use the imp1 option set_impl_property operates on the active implementation set impl property impl uart top impl 2 name uart top alternate 1 To retrieve the property values of an implementation call the get_impl_property command The following example gets the name property of the active implementation get impl property name Activating an Implementation Inactive implementations are displayed in the Project Files pane of the Design Center window with a closed folder icon next to them and their hierarchy is collapsed You can expand the hierarchy an
147. tively disabled 5 20 Precision RTL Synthesis Users Manual 2003c Update1 March 2004 Viewing a Schematic Setting Schematic Viewing Options Changing the Viewer Display and Color Options As shown below the Schematic Viewer Display options dialog allows you to filter out certain objects from the schematic view change the font style and specify the mouse selection radius The Color options dialog allows you to change the schematic color scheme Input Optimization H Analysis OuUrpue Hl ISE 6 1 7 Session Settings J Schematic viewer Input Optimization Hl Analysis MUpuUe H ISE 6 1 i 5ession Settings Schematic Viewer Display Colors Show Attributes Net names Font Cell names Aria Regular Change Instance names Pin names Mouse HierPin names Selection radius fz All invisibles backgroundcolor rubberbandcolor netcolor buscaolor overlapcolor Instances Sequential Elements Hierarchical IU Pads Precision RTL Synthesis Users Manual 2003c Update1 March 2004 Ehange Selected olor Set to Default Colors Set to Black Background Colors 5 21 Setting Schematic Viewing Options Viewing a Schematic 5 22 Precision RTL Synthesis Users Manual 2003c Update March 2004 Index Index sdc File generated 2 4 ucf File 2 17 A Activating an Implementation 4 13 add_input_file command 2 7 Adding IO Pads 3 19 Adobe Acrobat Reader 1 8 Alt
148. tomated Place amp Route flow or you can invoke the Vendor s project browser and manually step through the implementation process You can also view Vendor generated reports and invoke Vendor tools such as timing analyzers and power analyzers 2 22 Precision RTL Synthesis Users Manual 2003c Update 1 March 2004 Chapter 3 Setting Constraints and synthesizing When you Compile a design a technology independent database is created in memory The next step involves setting constraints and mapping the design to technology specific cells By default Precision RTL Synthesis maps the design to the fastest possible implementation that meets your timing constraints In order to accomplish this you must at a minimum specify timing on the automatically determined clock sources With this information Precision performs static timing analysis to determine the location of the critical timing paths Although Precision will map your design to the target technology without any timing information Precision will produce the best results with this information Managing a Master Constraint File Typically you will make more than one synthesis run before you achieve the best results During this process you guide Precision toward the ideal solution by setting constraints The constraints will be timing constraints mapping constraints and constraints that control the structure of the implemented design The constraints you specify first are usually estimat
149. un in separate memory Enter path for starting yp Working Directory Statin Fama desgne Shortcut kep None Rur Normal window Comment P Find T arget Change Icon cect fon Precision RTL Synthesis Users Manual 2003c Update1 2 1 March 2004 Setting up the Design Environment Setting Up a Design and Compiling Invoking Precision from a Shell You can invoke Precision in non GUI mode by using the command precision shell In this mode you can source Tcl scripts or you can interactively enter commands from the shell prompt A typical command line entry might be the following where a Tcl command file is specified to set constraints and guide the tool through the synthesis process 0 lt precision shell file dofile tcl You can also export your script settings For more information see Exporting your Settings The precision command and its optional switches is fully documented in the section titled Commands in the Precision Synthesis Reference Manual Setting up the Design Environment As shown Figure 2 1 the Main window has three primary control areas The Design Bar on the left controls the synthesis flow You will manage your project files from the Project pane center and apply constraints to design objects in the Design Hierarchy pane right The Design Bar provides a visual indicator of the sequential steps in the synthesis flow Using progressive disclosure the icons in the Design Bar change
150. up If you get any errors or warnings you can edit the source file by double clicking on either the message in the Transcript window or on the file name in the Design Center An in memory design database is created by reading one or more source files into memory Precision converts any of the initial input formats into an intermediate representation which permits the tool to efficiently optimize designs Within the views Precision RTL Synthesis uses the following naming convention for different types of logic ix instance name for boolean gate reg_signal flip flop with the q output driving signal or unknown power ground net lat_signal latch with the q output driving signal modgen_ cell used to implement an operator Evaluating the Results By examining the transcript and viewing the RTL Schematic you can determine whether Precision has created the generic gate level implementation that you expect You can analyze both the warnings in the transcript and the quality of the initial results Even though the output of the compile command is technology independent the quality of the compiled design is a precursor to the quality of the final technology design Reviewing Warnings and Errors in the Transcript The following list shows some typical warning messages and their causes Messages about overwriting designs Warning Overwriting netlist work comb INTERFACE Typically you expect these warnings wh
151. ut Delay Input Delay refers to the delay consumed outside the design before a data signal reaches the input port of your design Output Delay is the delay required outside the design in order to properly clock the device being driven by your design These optional default values serve as a starting point for setting I O constraints After the Compile step you will be able to select each I O port in the Design Hierarchy pane and adjust the constraints accordingly 6 Apply the Setup Technology dialog box This action executes a series of setup_design commands that inform Precision RTL Synthesis about the technology and the global options you entered Precision RTL Synthesis does not actually load the synthesis library into memory until the command to Compile is executed After you specify the technology and verify the options you can add your design files to the project Adding Input Files to the Project Precision RTL Synthesis does not read or reference pre compiled HDL libraries packages or designs from disk Instead the library and package source files and the design source files are read directly into memory where Precision builds an EDIF like in memory database The design source files may reside in any location and may even reside in more than one location To add your input files to the project from the GUI follow these steps 1 Click on the Add Input Files icon in the Design Bar This action opens the Add Input Files dialog box 2
152. values Precision RTL Synthesis calculates delays using a conservative pre layout estimate If you are close to meeting your timing constraints according to Precision s estimate you may have actually met the timing constraints according to the accurate post layout value produced by the physical implementation tools Performing Initial Place and Route Precision RTL Synthesis has a built in Place amp Route environment that allows you to move seamlessly from synthesis to the physical implementation of your design Once your design 1s synthesized icons for the Vendor s implementation tools appear in the Precision Design Bar The current implementation directory becomes the project directory for the Vendor tools and you can proceed to Place and Route Like the synthesis process the place and route process is controlled by two primary commands Synthesis options are set by the setup_design command and the flow is executed with the synthesize command In a parallel way place and route options are set by the setup_place_and_route command and the flow is executed with the place_and_route command The Precision GUI interface to the setup_place_and_route command appears after you select the target technology The pulldown menu Tools gt Set Options gt Vendor Environment Name becomes available After Precision output files are written to the implementation directory the Vendor Tools icons are revealed in the Design Bar You can invoke the au
153. vices ssseseeesssssssssserersesssssserererssssssesereresssssseeses 5 20 Changing the Viewer Display and Color Options ssesssssssoeeesesssssseeseresssssssssereessssssesses 5 21 Precision RTL Synthesis Users Manual 2003c Update1 V March 2004 Table of Contents List of Figures Poesi cree i ect 2 3 Pre 2 4 i Input File Properts tra ets sarancetaenasirnsa seas cc Ei 2 8 Ficus 2 5 Prepare ie rai ULT PG sospesi nr uaa 2 18 Fiene 2 1 The Constraint Relations senscasinaranctaenarscumesviesaiensatectanssdeneaassiatinapbameeasnssaneanesse 2 21 PES d EE E a N ee ener ener eee Renee Caner tees 3 4 Figure 3 2 The Clock Period Defines the Maximum Delay Between Flip Flops 3 7 Figure 3 3 Setine ihe Clock Consiramts irom the GUL open ce cenisnsccstterecieeenmasvereiestiaanewa 3 8 Pome s i TRIGA Donne wnisemanmsoenrarnsnaniicaeniarianierianetnmiaernenisnin 3 10 Pure 3 3 Sonme Mia Deis Ton me OU Drsni 3 11 Fome Sa o De or DEE eaaa eee 3 13 Pire 3 7 Berane Uumtot Dely Tom Me TLU Dospan E 3 14 Piae oS Snug a Pike Pain Com Te OUD eeens 3 16 Piute Bere Pati Domed seoreninsridirr a 3 17 Figure 4 1 Organization of Project Files by the Project Manager nnnenensssssseerersssssseseeees 4 2 Figure 4 2 Initial Session Window and New Project Dialog BOX ssesssssseseneesssssssessesessssssese 4 3 Figure 4 3 Newly Created Project and Implementation seeeeseeeessesssssseesererreserssessssssssssess 4 5 Figur
154. w A clock is an abstract design object created within your design database to allow you to constrain your design for timing Ideal clocks are not part of your design but clocks can be associated with signals and ports in your design Defining a clock defines the period and edge positions of a recurring waveform When a clock is associated with a port or signal it is referred to as a real clock If no such assignments are made the clock is considered a virtual clock Virtual clocks are useful for describing timing synchronized by external circuitry In addition to user defined clocks the system will automatically create clocks for you to model the behavior of clocking components e g Xilinx DCM components or Altera DLL components The clocks are referred to as derived clocks since their properties are determined based on the input clock properties and the function of the clocking component Derived clocks can be used everywhere a defined clock is used but they cannot be modified by the user Precision RTL Synthesis Users Manual 2003c Update1 3 3 March 2004 Setting Timing Constraints Setting Constraints and Synthesizing They will appear in the clock folder of the design browser along with the user defined clocks See the following figure for an example of clocks Figure 3 1 Clocks Example Derived Clock Internal iin gt clk_int gt Clocks are used as reference objects for constraint commands The set_input_delay a
155. wing you to create delete copy edit and save implementations For more information refer to Chapter 4 Managing Projects Precision RTL Synthesis Users Manual 2003c Update 1 1 March 2004 Precision RTL Synthesis Features Introducing Precision RTL Synthesis Advanced Synthesis Algorithms Precision RTL Synthesis includes a suite of unique algorithms called Architecture Signature Extraction A S E optimization that automatically focus specific optimizations on areas of the design that are most likely to hinder overall performance such as finite state machines FSM cross hierarchical paths or paths with excessive combinational logic ASE uses an automated heuristic approach to deliver smaller and faster designs without the need for iterative manual user intervention Constraint Driven Synthesis As FPGAs continue to grow in size and complexity designers need a synthesis tool that delivers excellent results the first time Timing constraints based on the industry standard Synopsys Design Constraint SDC format are all the information Precision needs to deliver correct results without endless iterations Missing timing constraints result in incomplete timing analysis and may allow timing errors to go undetected Precision eliminates this by performing a complete constraint analysis prior to synthesis to insure that designs are fully and accurately constrained First time success in the lab requires a fully and accurately constrained des
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157. ze place and route and so on The set_results_dir command is not available if a project is open Using the Project Manager Interactively The following sections describe how to use the various Project Manager commands In each section the graphical user interface is presented first followed by the equivalent Tcl command interface Creating a Project The Project Manager is enabled by opening or creating a project From that point until you close the project all of your work is carried out in the context of the active implementation in that project When you invoke Precision the session window displays the Design Bar and the transcript window The Design Bar displays the Project pane which is where all project related icons are found Initially it contains only 2 icons New Project and Open Project More appear after a project is open To create a project either click on the New Project icon on the Design Bar or choose the File gt New Project menu Precision opens the New Project dialog box as shown in Figure 4 2 Figure 4 2 Initial Session Window and New Project Dialog Box i Mentor Graphics Transcript Window ES File Edit wiew Tools Window Help Copyright c Mentor Graphics Corporation 19 g New Project E I Hew Froject Project Name Juart_top ne Project Folder G sb project uarts Open Project roa When you OK the dialog box the project and an initial implementation are creat

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