RL78/G14 Recommended PCB Layout for Reducing Noise
Contents
1. e Connect the MCU and REGC circuit with the shortest possible wiring 2 6 Wiring of TOOLO Pin e Connect the TOOLO pin to VDD via a 1 kQ resistor as the MCU user s manual recommends e Place the TOOLO circuit close to the MCU e Connect the MCU and TOOLO circuit with the shortest possible wiring RO1AN1876EC0100 Rev 1 00 Page 4 of 14 Feb 28 2014 RENESAS RL78 G14 Recommended PCB Layout for Reducing Noise 3 Description of the Test Board This section shows examples of the recommended layout and non recommended layout Both the recommended board and non recommended board are made with the same schematics and components Only the PCB layouts are different With the recommended methods the recommended PCB board can achieve higher reducing noise performance 3 1 Schematics of the Test Board The recommended layout and the non recommended one are designed with the same schematics Figure 3 1 shows the schematics of the circuits around the MCU P41 P40 TOOLO RESET ET PI24 XT2 EXCLKS P x2 XI n 1 a G REGC 12 0 47uF 13 5 IND 14 Ld l RL78 G14 64 pin Figure 3 1 Schematics of the Circuits around the MCU 3 2 PCB Layout of the Two Test Boards This section shows examples of the recommended layout and non recommended layout The PCB layout should be designed in accordance with recommended one to achieve higher reducing noise performance The reasons why the PCB layout on2. Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction When exporting the Renesas Electronics products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations 10 Itis the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the 11 contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics 12 Please contact a Renesas Electronics sales office if you hav
3. The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release
4. is shorter than the non recommended one On the non recommended board the leads of R1 D1 and C6 are not directly connected to the MCU VDD and VSS wiring but connected to the main power supply VDD and VSS wiring Reason The reset signal initializes the internal MCU state If fine noise like pulses pass through the reset signal wiring the MCU may not completely initialize partially initialize It is better to shorten the wiring of the reset circuit to reduce the noise effect 3 3 5 Wiring of REGC Pin The REGC circuit C3 on the recommend board is closer to the MCU than the non recommended one And the wiring from the REGC circuit to the MCU is shorter than the non recommended one On the non recommended board the VSS of C3 is connected to VSS lines before the MCU bypass capacitor C4 Reason The long wiring between C3 and the MCU REGC pin may become a noise antenna The REGC should be connected to VSS wiring after the bypass capacitor otherwise the bypass capacitor effect will be weakened 3 3 6 Wiring of TOOLO Pin The TOOLO circuit R2 on the recommend board is closer to the MCU than the non recommended one And the wiring from the TOOLO circuit to the MCU is shorter than the non recommended one On the non recommended board the VDD of R2 is not connected to the MCU VDD but connected to the main power VDD wiring Reason The long wiring between R2 and the MCU TOOLO pin may become a noise antenna If the potential difference is caused by
5. noise between TOOLO VDD and MCU VDD level it may affect the MCU working status 3 4 Block Diagram of the Test Board The test board will perform some sample functions under noise test The MCU operation status can be shown by the two groups of LEDs Red and Yellow After the MCU resets all LEDs will blink for 5 seconds Then the two groups of LEDs will light from 0000 to 1111 by 12 One group is controlled by the main loop the other group is controlled by timer interrupt routine These two groups of LEDs will blink synchronously Figure 3 3 shows the block diagram of the test board RO1AN1876EC0100 Rev 1 00 Page 7 of 14 Feb 28 2014 RENESAS RL78 G14 Recommended PCB Layout for Reducing Noise System initialization Interrupt initialization All LEDs ON for 5 sec x S A 0 All LEDs OFF OOOO e 6 96 handler Illuminated LEDs O e O w ow eo e o o o o 2 D 2 a O O jo jo O Illuminated LEDs OOO OOXO O OX X E NO LEDOFF WX LEDON x Note OOOO The red LEDs are controlled by the main loop and the yellow LEDs are controlled by the interrupt handler The red and yellow LEDs blink synchronously eDueuo oas G0 Figure 3 3 Block Diagram of the Test Board RO1AN1876EC0100 Rev 1 00 Page 8 of 14 Feb 28 2014 RENESAS RL78 G14 Recommended PCB Layout for Reducing Noise 4 Reducing Noise Test of Different Layout 4
6. the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to a product with a different part number confirm that the change will not lead to problems The characteristics of an MPU or MCU in the same group but having a different part number may differ in terms of the internal memory capacity layout pattern and other factors which can affect the ranges of electrical characteristics such as characteristic values operating margins immunity to noise and amount of radiated noise When changing to a product with a different part number implement a system evaluation test for the given product Notice Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuit
7. 1 Test Description In this test two types of PCB were used One is designed according to the countermeasures The other is designed without the countermeasures The PCB layouts around the MCU are shown as Figure 3 2 The peripheral circuits on the two boards are same Same noise interference is input to the two test boards through the power supply for 1 minute The peak value of noise interference steps up in 100 V increments from 100 V to 4000 V in every test On the target boards there are two groups of LEDs that blink to show the MCU status All LEDs will be ON for 5 seconds after the MCU resets Then the two groups of LEDs will blink from 0000 to 1111 by 15 One group is controlled by the main loop the other group is controlled by timer interrupt These two groups of LEDs will blink synchronously The MCU status can be evaluated by observing these LEDs e Ifthe MCU operates normally within 1 minute the result is considered good and the table is filled with a v e Ifthe MCU generates an abnormal phenomena reset program runaway or LEDs blink asynchronously within 1 minute the result is considered not good and the table is filled with a x Figure 4 1 shows the diagram of test environment Av Isolated Power supply for transformer test circuit NoisesGenerator Power input lt p 2 vu Power supply for noise generator Figure 4 1 Diagram of Test Environment 4 2 Test Conditi
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9. 2tEN ESAS APPLICATION NOTE RL78 G14 RO1AN1876EC0100 Rev 1 00 Recommended PCB Layout for Reducing Noise Feb 28 2014 Introduction The purpose of this document is to help the user understand how to design a good PCB layout with high reducing noise performance A thorough system evaluation is necessary after taking the countermeasures mentioned in this document This document provides an explanation using RL78 G14 sample boards Target Device RL78 G14 The test results are applied to the following conditions e MCU RL78 G14 64 pin e PCBtype Single side printed board without a polygon RO1AN1876EC0100 Rev 1 00 Page 1 of 14 Feb 28 2014 RENESAS RL78 G14 Recommended PCB Layout for Reducing Noise Contents Vs PROTA CC E 3 2 Recommended PCB Layout iesus txkekads dUR OAM Ur Lx Ora a ix EEVbS E Lt S MER SQUE DU IR KE dK a RR 4 2 1 Wiring of VDD and VSS ssassn aaraa 4 2 2 Oscillator Concerns oocace eter er aea aa aana iaaa RT RUE REO nen aaia aa aiaia 4 2 3 BYPASS Capac itOl ys isicccasssecscetacsnncanscnciectaxasaase ARERR RAKRARQRRR E ER ARRTRRNRERSRO AREARRIARRARRRREEERARERRKRERERSERRRRKRTRARRR 4 2 4 Wiring of RESET Pin suiiin iie tein Sends mesic Ra REDE EN Ka tei o DN a RERO CR Ra ERES NK ERR RR eats 4 2 5 Wiring of REGC Pili iri enero De RE IX a ROO D AEE LERNAR K RUE DXX RERO EX XXX ERE EN NEN EX RN N ERE R NR RAE ERAS 4 20 WiringofTOOLO Tp 4 3 Descript
10. RU REUE INR KKERNRRRE E ERE CXEEKERARERAMSEDR DNA REA eNA ER 10 44 Test Conclusions Rx RRRa Y RE MRERKERKEEN Nn Raum ERRERE EEE Eaa NBN HR e ERXKRRRRNRREEEKEERRAAR S 11 5 Improve the Non recommended Board LLeeeee sees sees esee seeeeuee 12 5 1 Modification of the Non recommended Board eese 12 5 2 Test Results of the Modified Board ccccccesseeseeeceeeeeeeeeeeeeeeeeeeeeseeeeesseeneeeeeeseeeeesneneeeeeeeneees 13 5 3 Recommendations for PCB Board Improvement eese 13 6 Documents for Reference ecce oiu ier eia En eter eec tno P scere E Era EE PR an mra ao E rain rpRirs 14 R01AN1876ECO0100 Rev 1 00 Page 2 of 14 Feb 28 2014 RENESAS RL78 G14 Recommended PCB Layout for Reducing Noise 1 Preface This application note describes how to design PCB layout to achieve high reducing noise performance The countermeasures of recommended PCB layout are shown in this application note And the AC line noise contrast test with two types of PCB layout boards is introduced to verify these countermeasures Subsequently the improvement test which is based on the non recommended board is also introduced in this application note RO1AN1876EC0100 Rev 1 00 Page 3 of 14 Feb 28 2014 RENESAS RL78 G14 Recommended PCB Layout for Reducing Noise 2 Recommended PCB Layout Good PCB layout is very important in reducing noise design S
11. ducing Noise 4 4 Test Conclusions The test results only show the reducing noise performance of the tested boards As is shown in Table 4 1 the result of noise interference test on the recommended board is about 4000 V the maxim value of test condition and the non recommended one is below 2500 V Conclusions from this test are as follows e Higher reducing noise performance can be achieved by designing a PCB layout according to the recommendations e Due to the high reducing noise performance of the MCU the worst phenomenon reset can not be released did not occur even in the non recommended board noise test Note Keep the MCU away from high voltage noise even if it is designed with the recommended PCB layout The test results are available only to distinguish the noise effects on different layouts and do not represent the MCU performance RO1AN1876EC0100 Rev 1 00 Page 11 of 14 Feb 28 2014 RENESAS RL78 G14 Recommended PCB Layout for Reducing Noise 5 Improve the Non recommended Board After the above test modifications were made on the non recommended board and retested under the same conditions In this test the non recommended PCB board was modified provisionally to improve reducing noise performance When developing a product the PCB layout should be redesigned according to the recommended layout for high performance 5 1 Modification of the Non recommended Board Modified items are listed below e VDD and VSS Remo
12. e any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries N N ote 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries ote 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics SALES OFFICES Renesas Electronics Corporation http www renesas com 21 NE S AS Re er to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 651 700 Fax 44 1628 651 804 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 65030 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd 7th Tel Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 301 Tower A Central Towers 555 LanGao Rd Putuo District Shanghai China Tel 86 21 2
13. he MCU than the non recommended one The wiring from oscillator circuit to the MCU on the recommended board is shorter than the non recommended one On the non recommended board the oscillator circuit is not at the terminal of VSS wiring and not separated from other VSS wiring Reason Long wiring may have an antenna effect to catch noise If noise enters the clock pins clock waveform may be deformed This may cause program failure or runaway Also if the potential difference is caused by the noise between the oscillator VSS level and the MCU VSS level the correct clock will not be input to the MCU 3 3 3 Bypass Capacitor Bypass capacitor C4 on the recommend board is closer to the MCU than the non recommended one And the wiring from the bypass capacitor to the MCU is shorter than the non recommended one Especially on the non recommended board the leads of C4 are not directly connected to the VDD and VSS trunk wiring Reason Longer wiring will generate larger impedance for noise signal Longer wiring may resist the noise current through the noise return circuit Also long wiring between the bypass capacitor and the MCU may become a noise antenna RO1AN1876EC0100 Rev 1 00 Page 6 of 14 Feb 28 2014 RENESAS RL78 G14 Recommended PCB Layout for Reducing Noise 3 3 4 Wiring of RESET Pin Reset circuits R1 D1 and C6 on the recommend board are closer to the MCU than the non recommended one And the wiring from the reset circuit to the MCU
14. hortest wiring pattern to connect resistor capacitor and diode e REGC and TOOLO Place the capacitor and resistor as close to the MCU as possible RO1AN1876EC0100 Rev 1 00 Page 13 of 14 Feb 28 2014 RENESAS RL78 G14 Recommended PCB Layout for Reducing Noise 6 Documents for Reference User s Manual RL78 G14 User s Manual Hardware RO1UHOI86EJ RL78 Family User s Manual Software R01USO015EJ The latest versions can be downloaded from the Renesas Electronics website Technical Updates Technical News The latest information can be downloaded from the Renesas Electronics website Website and Support Renesas Electronics Website http www renesas com index jsp Inquiries http www renesas com contact All trademarks and registered trademarks are the property of their respective owners RO1AN1876EC0100 Rev 1 00 Page 14 of 14 Feb 28 2014 RENESAS Revision History Description Rev Date Page Summary 1 00 Feb 28 2014 First edition issued A 1 General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this document refer to the relevant sections of the document as well as any technical updates that have been issued for the products 1 Handling of Unused Pins Handle unused pins in accordance with the directions given under Handling of Unused Pins in the manual
15. iation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS
16. ion of the Test Board s sssssssssnsnnnsnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnnnnn nnmnnn nenne 5 3 4 Schematics Of the Test BOA neret bk utu n n Eun SERE HARRTR NARRA MERE ARR RRERRRERNR SRARRRRRRRRRA EE 5 3 2 PCB Layout of the Two Test Boards eese nnne enn nnne nennen nennen 5 3 3 Differences between Recommended Layout and Non recommended Layout 6 334 Wiring of VDD and VSS eiue eer n renes cin rna oae teins 6 3 3 2 Oscillator GOnCOrhs irre x e ert o eite eda rea rn deae dene havea 6 39 3 9 Bypass CapacltOr iiiid etas e Cents ned tle nth sd ees bo ong Ed lo alae e erudi ln edad emnt da 6 cR B seto sizi i adiune 7 3396 WiringiOt REOG PIN sasas peeneks nk kansu FENERE ENS KENAAN EE AARE EA ENEE AE E AAEE 7 3 3 6 Wiringot TOOLO PIM sicccvsisesscadteciacascdsdstatacscataccssiasdecdsisiiuadasdidecysseaessdiseidecustetaveSyasetasadiveaelcnies 7 3 4 Block Diagram of the Test Board eeeeeeeeeeeeeeeeeen eene enne nennen nennen nnn nnne nnns 7 4 Reducing Noise Test of Different Layout eese 9 4 1 TestDescriptiOD ssia ORAE RRRRRIR ERR EFRRERNRR ES UCER M a E aara aeaa aE AEKA Rara 9 4 2 Test CORGILIODS eir REA RARE ERREKXRRRARRRRRER AR ERKRERRRRRARSREREERKERRARHRARRRSRERRERRARRKARRRRESR KRRRRRRRNRERRERKR RRARE 9 4 3 Test Results eite Den eh nhe ee EBD ERRRR ARR
17. ome countermeasures of improving reducing noise performance are shown below 2 1 Wiring of VDD and VSS e Connect the MCU and main power supply with the shortest possible wiring e Make the VDD and VSS wiring equal in length e Make the wiring for the VDD and VSS wider than other signal wiring e Separate the wiring for the VDD and VSS on the MCU from the wiring for the peripheral function power supply And try to separate them at the entrance of the main power supply 2 2 Oscillator Concerns e Place the oscillator circuit close to the MCU e Connect the MCU and oscillator circuit with the shortest possible wiring e Separate the VSS wiring between the MCU and the oscillator from the VSS wiring for the other peripherals 2 3 Bypass Capacitor e Place the bypass capacitor between VSS wiring and VDD wiring close to the MCU And make power supply wiring connect to the MCU via the bypass capacitor leads e Make the wiring length between the bypass capacitor and VDD pin or VSS pin equal and as short as possible 2 4 Wiring of RESET Pin e Place the reset circuit close to the MCU e Connect the MCU and reset circuit with the shortest possible wiring e Separate the VDD wiring and VSS wiring of reset circuit from the VSS and VDD wiring for the other peripherals 2 5 Wiring of REGC Pin e Connect the REGC pin to VSS via a 0 47 to 1 uF default 0 47 uF capacitor as the MCU user s manual recommends e Place the REGC circuit close to the MCU
18. onics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat rad
19. ons e Test tools Noise generator NoiseKen INS 4040 Target board Recommended board and non recommended board e Test conditions Target board power 220 V 50 Hz MCU type RSFIO04LEAFA Oscillation frequency 20 MHz MCU power source 5 V MCU bypass capacitor 0 1 uF Noise period 16 ms Noise pulse width 50 ns Noise polarity plus and minus Noise peak value 100 to 4000 V Test time 1 minute RO1AN1876EC0100 Rev 1 00 Page 9 of 14 Feb 28 2014 RENESAS RL78 G14 Recommended PCB Layout for Reducing Noise 4 3 Test Results Table 4 1 Test Results of Recommended Board and Non recommended Board Recommended Board Test Results Non recommended Board Test Results Voltage x x x x x x x x x x x x x x x x S555 Seeeeeeeeleeeeeeee x x x x x x x x x x x x x x x x x x i rereereseeeaeeagS T v v v v v v v v v v v v v v v v v v v v v ALA AY AY SENN AY NESTS AY SESS AY SESE STEN Note Voltage Noise value Unit V higher value shows higher reducing noise capability Polarity Noise polarity added to target board power source v Normal MCU operation x 1 Reset cannot be released 2 Reset Rerun Reset 3 Main loop error or runaway RO1AN1876EC0100 Rev 1 00 Page 10 of 14 Feb 28 2014 RENESAS RL78 G14 Recommended PCB Layout for Re
20. s software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electr
21. the left in Figure 3 2 is recommended are explained in next section Figure 3 2 shows the PCB layout around the MCU of two test boards R01AN1876EC0100 Rev 1 00 Page 5 of 14 Feb 28 2014 RENESAS RL78 G14 Recommended PCB Layout for Reducing Noise Recommended Non recommended RSF104LEAFA RSF104LEAFA 88ES BO Figure 3 2 Recommended Layout Left and Non recommended Layout Right 3 3 Differences between Recommended Layout and Non recommended Layout This section introduces the main differences between the recommended layout and the non recommended layout 3 3 1 Wiring of VDD and VSS The VDD and VSS wiring of the recommended board are separated from peripheral power supply wiring at the entrance of the main power supply And the VDD wiring and VSS wiring of the recommended board are closer to each other than the non recommended board Especially on the non recommended board the VDD wiring of the MCU is connected to main power supply through jumper J1 before filter capacitor C9 Reason It is better to separate the MCU power supply wiring and peripheral power supply wiring In this way it can avoid the noise into the MCU through peripherals The MCU power supply wiring should be connected to main power supply after connecting to filter capacitors Otherwise the filter capacitors will not work effectively 3 3 2 Oscillator Concerns Oscillator circuits X1 C1 and C2 on the recommended board are closer to t
22. ve J1 and connect the MCU VDD to C9 with a jumper line to modify the VDD wiring connection Cutoff the VSS wiring of oscillator circuit and reset circuit to modify the VSS connection Refer to the red section in Figure 5 1 e Oscillator concerns Cutoff the original wiring which connects the VSS of oscillator circuit to the MCU VSS pin Connect them with a jumper to shorten the VSS wiring of the oscillator circuit Refer to the orange section in the Figure 5 1 e Bypass capacitor Move C4 close to the MCU Refer to the violet section in the Figure 5 1 e Reset circuit Cutoff the original wiring of reset circuit which connects to the VDD and VSS Connect these components R1 D1 C6 to the MCU VDD and VSS with jumper lines Refer to the blue section in the Figure 5 1 e REGC circuit Move C3 close to the MCU Refer to the gold section in the Figure 5 1 e TOOLO circuit Move R2 close to the MCU Refer to the green section in the Figure 5 1 Improvement RSF104LEAFA Red VDD amp VSS Orange OSC concerns Violet Bypass capacitor Blue Reset circuit Gold REGC circuit Green TOOLO circuit Figure 5 1 Improving the Non recommended Board RO1AN1876EC0100 Rev 1 00 Page 12 of 14 Feb 28 2014 RENESAS RL78 G14 Recommended PCB Layout for Reducing Noise 5 2 Test Results of the Modified Board Table 5 1 Test Results of Non recommended Board Improvement HOnaeconmmended After Modification Before Modification La
23. yout Voltage x x x x x x x x x x x x x x x x S555 Seeeeeeeeleeeeeeee x x x x x x x x x x x KK x x x x x SSisiseesiceesiseeegsgys v v v v v v v v v v v v v v v v v v v v v SEA AY AT SSN AY SESS AY SMES AY SESE SN Note Voltage Noise Value Unit V Higher value shows higher reducing noise capability Polarity Noise polarity added to target board power source Y Normal MCU operation x 1 Reset can not be released 2 Reset Rerun Reset 3 Main loop error or runaway 5 3 Recommendations for PCB Board Improvement After modifications are made on the non recommended board the results of reducing noise performance improved drastically But when developing a product the PCB should be redesigned according to the recommended layout Note the following precautions for designing the PCB layout e VDD and VSS Separate the MCU VDD and VSS wiring from peripherals VDD and VSS wiring Connect to the main power supply after the filter capacitors e Oscillator concerns Use the shortest possible wiring to connect the oscillator capacitor and MCU Separate oscillator s VSS from other peripherals VSS wiring e Bypass capacitor Place the bypass capacitor as close to the MCU as possible Make sure the leads of the bypass capacitor are set on the VDD and VSS trunk wiring e Reset circuit Use the s
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