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Multi-Channel High Speed Counter

1. MEQ Masked Equal Source Mask Compare DATA BLOCK PTR HSCE2_XMIT HSCE2_ACK EQU O 1 I1 Equal Source A N11 0 15 1746 HSCE2 15 1746 HSCE2 Source B If the programming error bit or the module fault bit is set set the HSCE2 error bit When the last block is completed block data offset max block offset copy the Counter Control Block to the HSCE2 Note The Counter Control Block does not require a 0 1 positive transition of the transmit bit to operate ock to the HSCE2 and set transmit bit 0 e 0 15 HSCE2_CFG_BLK COP Copy File Source N10 N11 0 Dest 0 1 0 HSCE2 XMIT 1746 HSCE2 HSCE2 XMIT O 1 15 1746 HSCE2 DATA_BLOCK_PTR ADD Add Source A Source B Dest HSCE2_CFG_BLK COP Copy File Source N10 N11 0 Dest 0 1 0 Length 8 HSCE2_INIT_DONE B3 0 CL 0 HSCE2_ACK HSCE2_PERR HSCE2_ERROR 11 1 11 B3 0 Hb CL 15 13 1 1746 HSCE2 1746 HSCE2 HSCE2_FAULT I1 14 1746 HSCE2 END 5 Publication 1746 UM002B EN P August 2004 6 10 X Application Examples Data Table for N10 File hexidecimal Programming Blocks Offset 0 1 2 3 4 5 6 1 8 9 Module Setup N10 0 1 101 8 0 0 0 0 0 0 0 Counter Configuration N10 10 302 C 0 C 0 0 0 0 0 0 Min Max Count Value Counter 1 N10 20 4 0 0 2 30 0 0 0 0 0 Min Max Count Value Counter 2 N10 30 104 0 0 7 C8 0 0 0 0 0 Min Max Rate Value N10 40
2. All Output Ranges Not programmed Interrupt Enable Interrupt disabled Rate Value Format Integer Publication 1746 UM002B EN P August 2004 4 32 Configuration and Programming Publication 1746 UM002B EN P August 2004 Start Up Normal Operation Chapter 5 Start Up Operation Troubleshooting and Debug Mode This chapter provides start up operation and troubleshooting information as well as detailing the operation of the debug mode The following steps will assist you in the start up of your 1746 HSCE2 module 1 Install the module in the chassis 2 Wire the input and output devices 3 Configure and program your SLC processor to operate with the module Apply power to the SLC system and to the attached inputs and outputs When power is applied to the SLC system the processor and the module run through a power up diagnostic sequence After the diagnostics are successfully completed the SLC processor enters run mode and normal operation begins If the SLC processor was in the program mode when power was removed it returns to the program mode when power is reapplied Place the SLC processor into run mode using an SLC programming device or keyswitch During normal operation the LEDs are illuminated as follows e The fault LED FLT is off e LEDs A1 A2 B1 B2 Z1 and Z2 illuminate indicating the inputs are energized e LEDs 1 2 3 and 4 illuminate indicating the s
3. BTW 0001 Block Transfer Write Module Type Generic Block Transfer Rack 001 Group 0 Module 0 Control Block BT20 1 Data File N12 10 Length 8 Continuous No Continuously re trigger 8 word block transfers to the remote HSCE2 BTR TRIGGER BT20 0 BT 0002 Block Transfer Read EN EN Module Type Generic Block Transfer Rack 001 DN gt Group 0 Module 0 ER Control Block BT20 0 Data File N12 0 Length 8 Continuous No Prior to running the HSCE2 configuration hand shaking ladder file 9 finish the first BTR BTR_DONE 1ST_BTR_DONE BT20 0 B3 0 0003 HALL DN 3 Jump to the HSCE2 initialization subroutine if 1ST BTR DONE HSCE2 INIT DONE HSCE2 ERROR INITIALIZE HSCE2 B3 0 B3 0 B3 0 JS 0004 Jump To Subroutine 0 1 Prog File Number U 9 0005 END Publication 1746 UMO002B EN P August 2004 Application Examples 6 13 0000 0001 0002 0003 0004 Ladder File 9 HSCE2 Initialization Routine Programming ladder file 9 shows the block transfer function required to set up the programming blocks in this example If the blocks have not all been transmitted block data pointer max block offset copy next block to the HSCE2 and set transmit bit N12 10 15 DATA_BLOCK_POINTER HSCE2 TRNSMIT HSCE2 ACK 28TW DATA N12 10 N12 0 O Less Than A lt B Copy File Source A Source N10 N11 0 Dest N12 10 Source B Length 8 HSCE2_TRNSMIT N12 10 gt 15 When HSCEZ sets its acknowle
4. Maximum Min Value 1 to 32 767 Maximum Min Value 1 to 1 000 000 If the calculated rate value is less than the minimum value a rate underflow bit is set in the input image table If the calculated rate value is greater than the maximum value a rate overflow bit is set in the input image table Outputs assigned to the counter still function normally Operating Class The format of the minimum maximum rate values depends on the operating class of the module Class 1 When the module is operating as Class 1 the minimum maximum rate values are programmed in two word integer format Configuration and Programming 4 19 Class 4 When the module is operating as Class 4 the data format of the minimum maximum rate values is determined by the rate value format bit in the Module Setup programming block When this bit specifies that the rate value be in floating point format the minimum maximum rate values are also programmed in floating point format When the rate value format bit specifies integer format the minimum maximum rate value is also in two word integer format When programmed in integer format the data has the same format as described in Integer Format on page 4 3 TIP The minimum maximum rate values can be changed after output ranges have been programmed The new values are checked against the ranges If the new values are outside the range boundaries the new values are not accepted and the pro
5. 3 its interrupt ability and 4 the limits for the count and rate values debug mode A mode of operation that allows the user to view the current configuration settings in the input data file instead of showing counts or rates dynamic parameter A configuration parameter that can be altered while the counter is running gate preset mode The gate preset mode determines what if any gating is applied to the counter and what conditions if any preset the counter to the preset value input configuration Input configuration determine how the A and B inputs cause the counter to increment or decrement operating mode The operating mode determines the number of available counters and which inputs are attached to them overflow counter The module s status when the maximum count would be exceeded overflow rate The module s status when the maximum rate is exceeded rate period The interval in time or in counts during which pulses are counted Publication 1746 UM002B EN P August 2004 Glossary 2 Publication 1746 UM002B EN P August 2004 rate value The counts per second H2 value that the module reports to the processor real outputs The actual physical outputs on the module static parameter A parameter that must not be altered while the counter is running underflow counter The module s status when the count value would be less than the minimum value underflow rate The module s sta
6. Operating Mode Module Set Range Allocation Steti odule Setu atic p Interrupt Enable Rate Value Format Counter Type Counter Configuration Input Configuration Static Gate Preset Mode Minimum Count Static Min Max Count Value Maximum Count Static Preset Value Dynamic Min Max Rate Value Minimum Rate Dynamic Maximum Rate Counter Number Range Type Range Number Program Range Dynamic Start Value Stop Value Output Image Enabled Soft Preset Only Internal Direction Counter Control Output ON Mask Dynamic Output OFF Mask Count or Rate Value Range Enable Mask 1 STATIC the associated counter must be disabled to set this parameter DYNAMIC this parameter may be changed while the associated counter is running 2 Only the selected counter must be disabled 3 Under specific conditions this parameter is dynamic See page 4 15 for more information Publication 1746 UM002B EN P August 2004 1 4 Module Overview Operating Class Publication 1746 UMO002B EN P August 2004 Module operation differs slightly based on the operating class The operating class is selected via the module ID code Class 1 Class 1 operation is compatible with all SLC 500 processors In Class 1 operation the module uses 8 input and 8 output words and has an associated ID code of 3511 A maximum of four 16 bit counters are
7. 1000 3 5 The destination is in the floating point file F8 Configuration and Programming 4 5 Converting from Floating Point to Two word Integer Format RSLogix500 programming software can also be used to convert from floating point to two word integer format as shown F8 4 holds the number to be converted It is divided by 1000 and the result is placed in F8 3 TWO WORD 1 TEMP DIV 0001 Divide Source A F8 4 0 0 Source B 1000 0 1000 0 Dest The value in F8 3 is moved to N7 34 yielding the upper word Most Significant Word MSW 0002 Rung 3 is used only when the original value in F8 4 is positive If the value in N7 34 was rounded up as determined by comparing it to the floating point version in F8 3 the value must be adjusted by subtracting one from it The lower Least Significant Word LSW is then calculated by subtracting MSW multiplied by 1000 from the original value FLOAT TO TWO WORD INT VALUE TWO WORD INT 1 MSW TWO WORD INT 1 MSW GEQ GRT SUB 0003 Grtr Than or Eql A gt B Greater Than A gt B Subtract Source A F8 4 Source A N7 34 Source A N7 34 0 0 0 lt 0 lt Source B 0 0 Source B F8 3 Source B 1 0 0 lt 0 0 lt 1 lt Dest 0 TWO WORD INT 1 LSW CPT Compute Dest N7 35 0 Expression F8 4 N7 34 1000 0 Rung 4 is used only when the original value in F8 4 is negative If the value in N7 34 was rounded up as determined by comparing it to the floating point version in F8 3 th
8. 0 for normal operation 1 for debug mode Figure C 4 Minimum Maximum Rate Value Block see pages 4 16 to 4 19 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Hex Format co zjojojojo W o oloo 1 0 0 O Wodo lofe E e s E Word 1 Minimum Rate Value in integer or floating point notation Word 2 nS i Word 3 Maximum Rate Value in integer or floating point notation Word 4 RESERVED Must equal zero Word5 0 0 0 0 RESERVED Must equal zero Word6 0 0 0 0 RESERVED Must equal zero Word7 0 0 0 0 1 O0 for normal operation 1 for debug mode Figure C 5 Program Ranges Block see pages 4 19 to 4 23 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Hex Format E 0 0 l3 0 82 CNTR I 0 0 0 1 0 0 0 0 WordO 1 110 ES amp No a cc Range Number Word 1 Range Start Value Word 2 Word 3 Range Stop Value Word 4 Word 5 0 0 0 0 0 0 0 0 Output State Word6 0 0 0110 Virtual Real RESERVED Must equal zero Word7 0 0 0 0 1 0 for normal operation 1 for debug mode Publication 1746 UMO002B EN P August 2004 Module Programming Quick Reference C 3 Figure C 6 Counter Control Block see pages 4 23 to 4 28 15 14 13 12 11 10 09 08 0
9. 2 19 fuse status bits 2 17 module fault bit 2 17 operating mode bits 2 18 output state byte 2 18 programming error bit 2 17 counter number min max count value block 4 15 min max rate value block 4 18 counter overflow bit 2 19 counter state bits 2 19 counter status bytes 5 2 counter type programming bit settings 4 12 counter types linear counter 2 9 ring counter 2 10 counter underflow hit 2 19 C UL listed A 1 D data format minimum maximum count values 4 3 minimum maximum rate values 4 19 preset value 4 15 range start and stop value 4 22 See also floating point format See also integer format debug mode activating 5 7 operation 5 7 5 9 debug mode bit 2 15 2 16 2 17 debug mode selection bit counter configuration block 4 11 min max count value block 4 14 min max rate value block 4 17 module setup block 4 6 program ranges block 4 20 definition of terms G 1 diagnostic error 5 2 differential encoder output waveforms 3 8 wiring 3 8 B 1 Publication 1746 UM002B EN P August 2004 2 Index E EMC Directive 3 1 encoder wiring 3 8 3 10 errors diagnostic 5 2 programming 5 2 European Union 3 1 F fault LED 5 2 floating point converting from 4 5 converting to 4 4 floating point format reading 4 4 writing 4 4 fuses 2 17 G gate preset mode programming bit settings 4 13 summary 2 8 gate preset modes 2 6 2 8 gate and preset limitations 2 8 no preset 2 6 soft preset 2 6 store continue 2 6 stor
10. A programming error is caused by improper set up of a module parameter The module responds to a programming error by setting the programming error bit When this bit is set the entire programming block is rejected The programming error bit is set when a reserved bit is set It is also set under the following conditions Table 5 1 Error Conditions by Programming Block Programming Error Conditions Block Module Setup e Operating mode bits are not set to a valid pattern e A counters range allocation value is greater than 16 e The sum of all range allocation values is greater than 16 e The range allocation value for Counter 2 and or Counter 3 is nonzero and the programmed operating mode has the counter disabled e A counter or counters were running when the block was sent e he INT bit was set in Class 1 e The RVF bit was set in Class 1 Counter e Counter number bits are not set to a valid number Configuration Operating mode may be incorrect e Input configuration is invalid for the counter Operating mode may be incorrect e G P mode is invalid for the counter Operating mode may be incorrect e The selected counter was running when the block was sent e he program counter number bits are not set for a counter that has one or more bits set in its corresponding counter setup word Min Max e Counter number bits are not set to a valid number Operating Count Value Mode may be incorrect e he minimum
11. Bit ana i 4 25 IDn Internal Direction n Bit 2 Vu ow ers cxx xv 4 25 C ROD Count or Rate Value Bit i uade eR 4 26 Pn Program Counter n Bit ridus da bp ks 4 26 Output ON OR Masies 4 26 Output Enable Mask 04 bed pats pata e 4 26 Enable Ria dais 4 27 Determining Actual Output State o o 4 27 Programming Block Default Values 4 28 O A A A ES E EY 4 28 HA E O ons 4 30 Chapter 5 DLE DID O O eS ER QE A Lin Un RANE 5 1 Normal ODBF AUOD pe ane wr Sere 8 ere Poe Y OPI t 5 1 Troubleshooting ee taei o d n e EO Doe 5 2 Module Diagnostic Errors lll sess 5 2 Module Programming BEEOES ecu weed rada ee 5 3 Application ESFORS ie ka rure ur RO p ore da 5 4 Debug Mode Opera vacio ita imet eh C a CE 5 7 Activating Debug Mode 6i eos s ry ed 5 7 Chapter 6 Example 1 Direct Addressing ese Bae Rx 6 2 Data Table for N10 File Chexidecimal 6 7 Data Table for N11 File decimal aaa vex 6 7 Example 2 Indirect Addressing s vs verde praia ES 6 7 Data Table for N10 File hexidecimal 6 10 Data Table for N11 File decimaD 6 10 Example 3 Block Transit sea cm v LAT en 6 10 Data Table for N10 File hexidecimab 6 14 Data Table for N11 File decimaD 6 14 Example 4 Using Soft Presets evi para Ed 6 14 Ladder File 9 HSCE2 Initialization Routine 6 17 Data Table for N10 File hexidecimab 6 18 Data
12. Vcc Pull upResistor Value R 5V dc 127 Q 12V dc 238 Q 24V dc 2140 Q Single Ended Encoder Output Waveforms The figure below shows the single ended encoder output waveforms When the waveform is low the encoder output transistor is on When the waveform is high the encoder output transistor is off Figure 3 8 Single Ended Encoder Output Waveforms Publication 1746 UM002B EN P August 2004 3 10 Installation and Wiring Publication 1746 UM002B EN P August 2004 Single Ended Wiring Discrete Devices Figure 3 9 Discrete Device Wiring Proximity Sensor vs Ak our COM Solid State Photo electric Sensor with Open Collector Sinking Output Module Inputs 1 Calculate the value of the pull up resistor R as shown below Re Vcc Vmin For 5V dc jumper position Imin For 24V de jumper position R Pe mm a Ka Imin where R pull up resistor value Vcc power supply voltage Vmin 4 2 V de Imin 6 3 mA Power Supply Voltage Vcc Pull up Resistor Value R 5V de 127 Q 12V de 238 Q 24V dc 21400 Selecting Operating Class Power up Reset Module Programming Chapter Configuration and Programming This chapter provides information about e selecting operating class e module programming e programming blocks e programming block default values The 1746 HSCE2 module has two operating classes which are determined by the ID code used
13. a task by task manner how to install configure program operate and troubleshoot an SLC 500 based system using the 1746 HSCE2 module Publication 1746 UM002B EN P August 2004 2 Preface Related Documentation The table below provides a listing of publications that contain important information about SLC products For Read this document Document number A reference manual containing status file data instruction SLC 500 Instruction Set Reference 1747 RM001 set and troubleshooting information Manual A description of how to install and use your Modular SLC 500 Modular Hardware Style 1747 UM011 SLC 500 programmable controller User Manual An overview of the SLC 500 family of products SLC 500 Systems Selection Guide 1747 SG001 In depth information on grounding and wiring Allen Bradley Programmable Controller 1770 4 1 Allen Bradley programmable controllers Grounding and Wiring Guidelines A description of important differences between solid state Application Considerations for SGI 1 1 programmable controller products and hard wired electromechanical devices Solid State Controls An article on wire sizes and types for grounding electrical equipment National Electrical Code Published by the National Fire Protection Association of Boston MA A glossary of industrial automation terms and abbreviations Allen Bradley Industrial Automation Glossary AG 7 1 If you would like a m
14. words Appendix E Comparing 1746 HSCE2 to 1746 HSCE 1746 HSCE High Speed Counter 1746 HSCE2 Multi Channel High Speed Counter Number of Counters 1 2t04 Counter Capability 16 bit 32 767 24 bit 48 388 607 Operating Class Class 3 only Class 1 or Class 4 Input Voltage 2 8 to 5 5V dc 4 2 to 30V dc Output Current 0 125 A 1 0A Input Frequency 50K Hz 1M Hz Response Backplane Response 60 ms 0 7 to 1 6 ms Time Module Compatibility Uses M files Supports handshaking Not compatible with SLC5 01 and 5 02 Compatible with SLC 5 01 and 5 02 or 1747 ASB and 1747 ASB Rate Periods Programmable Self determined Sequence Mode 24 step n a Count Rate Modes 12 ranges 16 ranges Preset Inputs Multiple preset inputs for 1 counter Hard preset disable 1 preset input for counters 1 and 2 only No preset input for counters 3 and 4 No hard preset disable 1 In Class 1 only Publication 1746 UM002B EN P August 2004 E 2 Comparing 1746 HSCE2 to 1746 HSCE Publication 1746 UM002B EN P August 2004 Glossary The following terms and abbreviations are used throughout this manual For definitions of terms not listed here refer to Allen Bradley s Industrial Automation Glossary Publication AG 7 1 class The class of the module Class 1 or Class 4 determines 1 its compatibility with various processors 2 the number of I O words
15. 0 0 0 1F4 0 0 0 0 0 Min Max Count Value Counter 3 N10 40 204 0 0 0 258 0 0 0 0 0 Min Max Count Value Counter 4 N10 50 304 0 0 0 2BC 0 0 0 0 0 Counter 1 Program Ranges N10 60 10 1 0 0 0 31 1 0 0 0 Counter 1 Program Ranges N10 70 10 2 0 32 0 63 2 0 0 0 Counter 1 Program Ranges N10 80 10 4 0 64 0 95 4 0 0 0 Counter 1 Program Ranges N10 90 10 8 0 96 0 C7 8 0 0 0 Counter 1 Program Ranges N10 100 10 10 0 C8 0 F9 1 0 0 0 Counter 1 Program Ranges N10 110 10 20 0 FA 0 12B 2 0 0 0 Counter 1 Program Ranges N10 120 10 40 0 12C 0 15D 4 0 0 0 Counter 1 Program Ranges N10 130 10 80 0 15E 0 190 8 0 0 0 Counter Control N10 140 80 8001 8001 8001 8001 FF00 FF 0 0 0 Data Table for N11 File decimal Offset 0 1 2 3 4 5 6 7 8 9 N11 0 140 140 14 0 256 Example 4 Using Soft This example illustrates the use of soft presets with the Counter Presets Control Block A soft preset loads the specific counter with a preset count value This preset value is determined by the last min max Count Value Block for that counter This block is normally loaded during HSCE2 initialization but the preset can be changed dynamically as shown in Example 5 1 The ladder logic uses the Example 2 program SLC 5 03 or higher processor in Class 4 mode 1 2 The example soft presets Counter 1 whenever the soft preset trigger bit B3 6 sees a positive 0 to 1 transition 3 The soft preset must wait until after the HSCE2 initialization process is complete B3 0 is set 4 The
16. 08 07 06 05 04 03 02 01 00 E E sr cO ITN 2 0 0j5 3 13 3 38 0 0 0 0 0 0 1 0 e Ca a a As a 0 0 0 0 0 0 0 0 0 G PMode Input Config amp Hou ae 5 Counter RESERVED Must equal 0 0 0 0 0 0 0 0 0 0 G PMode Input Config pele ee E Counter 2 RESERVED Must equal 0 opopofjo o o s S o 0 0 0 0 0 lS counter 3 or 4 a c as indicated Counter 4 Counter 3 RESERVED Must equal 0 RESERVED Must equal 0 Programming Block Identification Bit Word 0 Bit 01 This bit identifies the type of block TRMT Transmit Bit Word 0 Bit 15 A 0 to 1 transition starts a programming cycle DEBUG Debug Mode Selection Bit Word 0 Bit 12 When this bit is set the debug mode is activated Debug mode returns the input data file showing current settings in the counter configuration block See Debug Mode Operation on page 5 7 Publication 1746 UM002B EN P August 2004 4 12 Configuration and Programming Publication 1746 UMO002B EN P August 2004 PGMn Program Counter Number Bits Word 0 Bits 08 to 11 These four bits select the counters to which the programming block is applied If the bit is reset the associated counter is not programmed and the counter can be running when this block is sent In addition the associated programming words must be zero or a programming error occurs A counter must be stopped when pr
17. 11 below 60 Hz Clarified operation of Module Fault MFLT bit 2 17 Updated resistor information in single ended wiring diagrams 3 9 and 3 10 Clarified programming cycle 4 2 Modifications to the COP instruction example for reading and writing 4 4 floating point data Corrected bit identification in Output State Byte 4 22 Example showing how to activate debug mode 5 10 Corrected bit identification table for Program Ranges Block C 2 Publication 1746 UM002B EN P August 2004 2 Summary of Changes Publication 1746 UM002B EN P August 2004 Who Should Use This Manual Purpose of This Manual Preface Read this preface to familiarize yourself with the rest of the manual This preface covers the following topics e who should use this manual e how to use this manual e related publications e conventions used in this manual e Rockwell Automation support Use this manual if you are responsible for designing installing programming or troubleshooting control systems that use Allen Bradley small logic controllers You should have a basic understanding of SLC 500 products You should understand programmable controllers and be able to interpret the ladder logic instructions required to control your application If you do not contact your local Rockwell Automation representative for information on available training courses before using this product As much as possible we organized this manual to explain in
18. 40 10 50 10 60 10 70 10 80 10 90 120 130 140 150 160 170 E W 22220202026 RIR Ladder File 9 HSCE2 Initialization Routine Application Examples 6 25 See the ladder logic from Example 2 on page 6 9 Data Table for N10 File hexidecimal 0 1 302 o ER Sah gt gt gt gt gt gt gt gt gt gt gt gt gt gt OOO OOOO OOOO Oo co ce Data Table for N11 File decimal Offset N11 0 8001 0 170 gt 0M0000000m N o mo pT 170 NWN OO CO o ER CcOcccocococococo 17 3 O o0 m 5 6 1 8 9 0 0 0 0 0 0 0 0 0 0 0 82 0 0 0 0 0 0 0 0 0 0 0 0 0 3E7 0 0 0 3E7 2 0 0 0 3E7 1 0 0 0 3E7 2 0 0 0 3E7 1 0 0 0 3E7 2 0 0 0 3E7 1 0 0 0 3E7 2 0 0 0 31F 4 0 0 0 257 8 0 0 0 18F 4 0 0 0 C7 8 0 0 0 FFOD FFF 0 0 0 Publication 1746 UM002B EN P August 2004 6 26 Application Examples Publication 1746 UM002B EN P August 2004 General Specifications Appendix A Operating Temperature 0 C to 60 C 32 F to 140 F Storage Temperature 40 C to 85 C 40 F to 185 F Humidity 5 to 95 without condensation Backplane Current Consumption 250 mA at 5V dc power supply loading 0 mA at 24V dc Backplane Isolation 1000V dc Maximum Cable Length 300m 1000 ft Agency Certification UL listed C UL listed Class 1 Division 2 Groups A B C and D CE certified for all applicable directives C Tick marked for all app
19. B3 0 and B3 6 are set However it also clears the bit if the rung condition is false when either B3 0 or B3 6 is reset The result is that this logic when scanned manipulates the module s output image even if it was only intended to run after initialization was complete Figure 5 2 OTE Instruction SOFT_PRESET_TRGR HSCE2 CFG BLK 1 1 B3 0 O 1 1 E ooo 6 1 Most programming errors are easy to locate since the 1746 HSCE2 error bit B3 1 is set and the configuration block pointer N11 0 points at the configuration block during which the error occurred However errors that affect initialization are often very difficult to find Debug Mode Operation Start Up Operation Troubleshooting and Debug Mode 5 7 due to their unpredictable nature Even if the configuration block looks satisfactory in the N10 data file the data block in the module s output image may not be satisfactory The best way to check for this problem is to individually search the ladder logic program for all module output words O e 0 O e 1 etc Carefully check all ladder logic which manipulates the 1746 HSCE2 output image to ensure that the output image is not corrupted during initialization The debug mode allows you to look at the existing module setup of the programming blocks When invoked debug mode echoes back the programming data instead of showing counts and rates in the input data file The Counter Control block does not support the IMPORTANT IMPO
20. Byte These bits correspond to the real or virtual state of the outputs Bits 00 through 03 represent real outputs Bits 04 through 07 represent virtual outputs Counter Status Bytes Each counter has an associated status byte The format of the byte depends on the module s class of operation as shown below Figure 2 14 Class 1 Counter Status Byte Format 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 C R 0 ROvF RUdF COvF CUdF CState Figure 2 15 Class 4 Counter Status Byte Format 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 0 ROvF RUdF COvF CUdF CState Module Operation 2 19 C R Count Rate Bit The count rate bit is used only in Class 1 operating mode Because only one data word is available for Counters 2 and 3 in operating mode 2 and one data word for each of the four counters in operating mode 3 the module transfers either the counter s count or rate value When this bit is reset 0 the data in the corresponding word is the count value When this bit is set D the data in the corresponding word is the rate value ROvF Rate Overflow Bit This bit is set when the rate is greater than the maximum rate value RUdF Rate Underflow Bit This bit is set when the rate is less than the minimum rate value COVF Counter Overflow Bit When the counter is configured as a linear counter this bit is set when the count would become one over the maximum count value TIP Counter overflow or underflow bits are reset
21. Counter Configuration Block N10 10 to N10 17 gate preset mode for Counter 1 must allow soft presets In this case N10 11 was changed from 0C No Preset to 1C Soft Preset Only Publication 1746 UMO002B EN P August 2004 Application Examples 6 15 5 The example assumes that the controller control block is in the HSCE2 output image when the soft preset is implemented Additional logic for example preset change latch XIO from example 5 is needed to delay the soft preset logic if other ladder logic changes the output image For example example 5 dynamically changes the preset values and temporarily puts the min max count value block in the output image 6 Rung 3 unlatches the HSCE2 Counter 1 soft preset bit O 1 1 1 when the soft preset is completed Since the Counter 1 count value may be changing we have created a count range using the preset value N10 25 1000 N10 26 10 counts to determine if the soft preset is within range If the Counter 1 count value is static during the soft preset the ladder logic could simply compare the Counter 1 count value with the preset value Publication 1746 UM002B EN P August 2004 6 16 Application Examples Ladder File 8 HSCE2 Prior to use the programmer sets N11 2 to the total number of data blocks which will be entered into file N10 not including the Counter Control Block and initializes the data blocks in file N10 Ten integer data blocks are used instead of eight to simplify
22. HSCE2 inputs may accept false pulses particularly when using low frequency input signals with slowly sloping pulse edges To minimize the effects of high frequency noise on low frequency signals the user can do the following e Identify and remove noise sources e Route 1746 HSCE2 input cabling away from noise sources e Install low pass filters on input signals Filter values are dependent on the application and can be determined empirically e Use devices which output differential signals like differential encoders to minimize the possibility that a noise source will cause a false input Publication 1746 UM002B EN P August 2004 3 6 Installation and Wiring Electronic Protection Publication 1746 UMO002B EN P August 2004 The electronic protection of the 1746 HSCE2 has been designed to provide protection for the module from overload current conditions The protection is based on a thermal cut out principle In the event of a short circuit or overload current condition on an output channel all channels will turn off within milliseconds after the thermal cut out temperature has been reached IMPORTANT The module does not provide protection against reverse polarity wiring or wiring to AC power sources Electronic protection is not intended to replace fuses circuit breakers or other code required wiring protection devices Auto Reset Operation IMPORTANT 1746 HSCE2 outputs perform auto reset under
23. MAX_BLOCK_ADDR MUL Multiply Source A 10 10 lt Source B N11 2 17 lt Dest N11 1 170 lt While the HSCEZ is not initialized and the HSCE2 has not errored call the HSCE2 initialization routine FHRST PASS HSCE2 INIT DONE HSCE2 ERROR S 1 B3 0 B3 0 JSR 0001 2t Jt TE Jump To Subroutine 15 0 1 SBR File Number U 9 Publication 1746 UM002B EN P August 2004 6 20 Application Examples 0002 0003 0004 Ladder File 8 Continued This rung triggers a dynamic change of the Counter 1 preset The preset trigger bit B3 2 sets the preset change latch bit B3 4 The preset change latch bit B3 4 remains latched until the Counter Control Block is restored to the 1746 HSCE2 output image Use B3 4 to ensure that other logic soft presets do not write to the output image until the Counter Control Block is restored The preset enable bit B3 5 allows the first handshake rung ladder file 14 rung 0000 to run just once HSCE2 INIT DONE SOFT PRESET TRGR PRESET CHANGE LATCH PRESET CHANGE LATCH B3 0 B3 0 B3 0 B3 0 dE J E JOSRE L 0 2 3 4 PRESET_ENABLE B3 0 Jump to the preset change subroutine ladder file 14 until the preset change handshaking is L complete B3 4 is reset PRESET CHANGE LATCH B3 0 JSR JE Jump To Subroutine 4 SBR File Number U 14 Ladder File 9 HSCE2 Initialization Routine See the ladder logic from Example 2 on page 6 9 Publicat
24. Value Word 3 Counter 1 Rate Value Word 4 Counter 1 Capture Value Word 5 Counter 2 Count or Rate Value Word 6 8 p 09 OR 0 O 9 o Counter 3 Status Word 7 Counter 3 Count or Rate Value 1 See page 2 6 for a description of capture values Figure 2 12 Mode 3 Input Data Format 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Word 0 mm c 0 OP Output State S S ES t En MODE Virtual Real Word 1 Counter 2 Status Counter 1 Status Word 2 Counter 1 Count or Rate Value Word 3 Counter 2 Count or Rate Value Word 4 Counter 4 Status Counter 3 Status Word 5 Counter 3 Count or Rate Value Word 6 Counter 4 Count or Rate Value Word 7 Not Used Set equal to 0000H Publication 1746 UM002B EN P August 2004 2 16 Module Operation Class 4 Operation In Class 4 operation the counter data consist of a maximum of 23 words Figure 2 13 Class 4 Data Format 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Word 0 i la E OP Output State S E ES tn Eo 0 MODE Virtual Real Word 1 Counter 2 Status Counter 1 Status Word 2 Upper 4 digits Counter 1 Count Value Word 3 Lower 3 digits Counter 1 Count Value Word 4 Counter 1 Rate Value Word 5 Word 6 Upper 4 digits Counter 1 Capture Value Word 7 Lower 3 digits Counter 1 Capture Value S Word 8 Upper 4 digits Counter 2 C
25. always available for Counters 1 and 2 IMPORTANT In Class 1 Operating Mode 2 Counter 2 does not have a capture value available In Class 1 Operating Mode 3 no capture values are available Gate and Preset Considerations Z pulse Preset Operation In applications where the Z pulse of the encoder is being used to preset the position and where the Z pulse of the encoder is aligned with either the A or B pulses the capture or count value may be affected by 1 count If the Z pulse is edge aligned with the A pulse preset operations may not be performed accurately in any of the quadrature modes If the Z pulse is edge aligned with the B pulse preset operation may not be performed accurately in the X4 quadrature mode only A small capacitor for example 0 01 pF across the Z inputs will dis align these inputs and should correct this condition The table below summarizes the input configurations and gate preset modes available for all counters based on operating mode Operating Counter Input Configuration Gate Preset Mode Mode 1 1 All All 2 All All 2 1 All All 2 Pulse Internal Direction All 3 Pulse Internal Direction No Preset or Soft Preset Only 3 1 Pulse Internal Direction All 2 Pulse Internal Direction All 3 Pulse Internal Direction No Preset or Soft Preset Only 4 Pulse Internal Direction No Preset or Soft Preset Only Module Operation 2 9 Counter Types Each counter can be progr
26. available in this operating class Class 4 Class 4 operation is compatible with SLC 5 03 and above systems In Class 4 operation the module uses 23 input and 8 output words and has an associated ID code of 15912 A maximum of four 24 bit counters are available in this class Class 1 vs Class 4 Comparison Class Class 1 Class 4 Counters 16 bit 32 767 24 bit 48 388 607 Input Words 8 with limited information 23 with all information Backplane Interrupts Not permitted Permitted Use in RIO Chassis Permitted Not permitted Use in ControlNet Chassis Not permitted Permitted Module ID Code 3511 15912 Hardware Features Module Overview 1 5 The module s hardware features are illustrated below Refer to Chapter 3 for detailed information on installation and wiring Figure 1 1 Hardware Features OUTPUT STATUS 4 Output Status LEDs 0000 a En run Running Status LED Fault Status LED Input Status LEDs amp 9 amp 9 OI al la el el el I ll le Terminals 98 la al al la la le LEDs The front panel has a total of twelve indicator LEDs as shown in Figure 1 1 on page 1 5 LED Color Indicates 0 OUT Green ON OFF status of real output 1 OUT Green ON OFF status of real output 2 OUT Green ON OFF status of real output 3 OUT Green ON OFF status of real output RUN Green Running stat
27. by the module Class 1 operation uses 8 input and 8 output words and is compatible with SLC 5 01 and above processors and the 1747 ASB module Enter ID Code 3511 to select Class 1 operation Class 4 operation uses 23 input and 8 output words and is compatible with SLC 5 03 and above processors and with 1747 ACN15 and ACNR15 modules Enter ID Code 15912 to select Class 4 operation See Operating Class on page 1 4 for more information on Class 1 and Class 4 operation Whenever power is cycled or the processor mode is switched to RUN all counters are reset to their defaults The counters ranges presets etc need to be reprogrammed See the default settings on page 4 28 Module programming consists of the following six blocks e Module Setup e Counter Configuration e Minimum Maximum Count Value e Minimum Maximum Rate Value e Program Ranges e Counter Control Publication 1746 UM002B EN P August 2004 4 2 Configuration and Programming Publication 1746 UMO002B EN P August 2004 Each block is made up of eight words The first word is the control word The remaining seven words are data words The control word determines which parameters are in the data words This programming method applies to both classes of operation The programming blocks are described on pages 4 6 through 4 23 Programming Cycle Except for the Counter Control Block all programming blocks are written to the module with a programming cycle Programmi
28. count is outside its valid range e he maximum count is outside its valid range e he maximum count is less than or equal to Minimum Count e Programmed output count ranges are outside the bounds of the new minimum maximum count values e he preset value is outside its valid range e Counter was running when the minimum maximum count value was changed Publication 1746 UM002B EN P August 2004 5 4 Start Up Operation Troubleshooting and Debug Mode Publication 1746 UMO002B EN P August 2004 Table 5 1 Error Conditions by Programming Block Programming Error Conditions Block Min Max e Counter number bits are not set to a valid number Rate Value Operating Mode may be incorrect e he minimum rate is outside its valid range e The maximum rate is outside its valid range e he maximum rate is less than or equal to the Minimum Rate e Programmed output rate ranges are outside the boundaries of the new minimum maximum rate values e Rate values may be in the wrong format Program e The counter number bits are not set to a valid number Ranges Operating mode may be incorrect e The range number is greater than the programmed range allocation value e The range start value is outside its valid range e he range stop value is outside its valid range e Range values may be in the wrong format Counter e The soft preset bit is set while in No Preset mode Control e The internal direction bit is s
29. eder ES S he Ok BO he ees 1 2 Operating Clases soa Heal eter aos c teda d oar etes 1 4 Class nio rr a ed Ma eae EA AS i SR 1 4 Bcc sore ARCA bad 1 4 Glass 1 vs Class 4 Comparison o2 3p EE bes 1 4 Hardware Features d uou ede a XR EASX QD qM 1 5 PEDS EA prania angr E pue Kt Pu disp EM ex 1 5 NO AEN ERE AN IA A 1 6 Chapter 2 Operating Modes cu s ob dap Vet Gund doy Mavi We SG ak Ba gt 2 1 Input Configurations aou ee ga Xue Uwe ee OG 2 2 Pulse External Direction Mei oed ae eoe pee 2 2 Pulse Intetnat Directions 2m dte ea PENS OR aed 2 3 p and D wn Pulses eann ore arar Ehre qd ad teas 2 3 X1 Quadrature Encoder y idas ri y 2 4 X2 Quadrature Encodet usario vai a 2 4 X4 Quadrature Encoder o 2 4 Int Preggene oos pea ade Raa ead cae erate Sry 2 5 Gate Presst Modes o oo ow KE T OES Pee SEE ER 2 6 INO Preset aca Vra EAS UB SURE d SUA EC Dp RR QOO 2 6 Soft Preset OBS A uns uds etnies dea i gs 2 6 blOre GOLD Errar 2 6 Store Holey RESUME c9 Gs p qo ese e te a 2 7 Store Preset Hold Resumie va iac Vw Rr ek 2 7 Store Presea St eis O DEE a A OG 2 7 Gate and Preset Limitations ooo o 2 8 Gate and Preset Considerations scared 2 8 Summary of Available Counter Configurations 2 8 Publication 1746 UM002B EN P August 2004 Table of Contents ii Installation and Wiring Configuration and Programming Publication 1746 UM002B EN P August 2004 Co nter Types ev pv yocp d dent ated nor a
30. ee opua oor Hee E qj wee Dod 4 15 Minimum Maximum Count Value Words 4 15 Counter TU DO S e v a uS EMO PA RR Rea ph eee oen 4 16 Minimum Maximum Rate Value Block 4 16 Programming Block Identification Bit 4 17 TRMT Transmit Bit rests ek Ex Get TNR ES 4 17 DEBUG Debug Mode Selection Bit 4 17 CNTR No Counter Number Bits 4 18 Minimum Maximum Rate Value WordS 4 18 Operating Class rro SS t ERN ae SCIES aa tA 4 18 Program Ranges Block 5 lt 2 5 5 tau ha ees BA Re eo eee Bee 4 19 Programming Block Identification Bit 4 20 TRMT Transmit Bit nc rom ot oce edet 4 20 DEBUG Debug Mode Selection Bit 4 20 CNTR No Counter Number Bits 4 21 Riype Range Types rra xo ation des eee ae 4 21 Range No Range Number Bits 4 21 Range Start Value Range Stop Value 4 22 Output State Output State Byte 4 22 Publication 1746 UM002B EN P August 2004 Table of Contents iv Start Up Operation Troubleshooting and Debug Mode Application Examples Publication 1746 UM002B EN P August 2004 Counter Control Block ava amp qoe Ye eroe dnt 4 23 Transmit B Doa qeu Rare atte bo Ge Qa est do an ect Qe 4 24 Programming Block Identification Bit 4 24 Control Words cereo ESE ES a 4 24 ENn Enable Counter n Bit 2 2 a G04 5 4 24 SP Soft Preset Only n
31. example shows how to store the count values and use the auto preset bit to load the preset during 1746 HSCE2 initialization 1 The following procedure uses the Example 2 program SLC 5 03 or higher processor in Class 4 mode 1 The ladder logic stores and reloads the Counter 1 count value 2 The Counter 1 min max count value block auto preset bit N10 20 10 was set to automatically download the preset value during 1746 HSCE2 initialization 3 Rung 0002 was added to ladder file 8 to copy the Counter 1 count value to the preset value during each program scan IMPORTANT The ladder logic will simulate a retentive counter best if the counter is either static or changing slowly during power down If the Counter 1 count value is changing rapidly the module s internal count value and the count value in the processor s input image could differ due to the time delays in the system including 1 5 ms in the module and processor scan time Publication 1746 UM002B EN P August 2004 6 24 Application Examples Ladder File 8 HSCE2 Prior to use the programmer sets N11 2 to the total number of data blocks which will be entered into file N10 not including the Counter Control Block and initializes the data blocks in file N10 Ten integer data blocks are used instead of eight to simplify the display in data windows The first pass of the program initializes the following values 1 The HSCE2 initialization done bit B3 0 is unlat
32. module detects a positive transition on the Z input of the counter The capture value is made available to the backplane A stored status bit is set in the input image table to signal the processor that a new value is available This bit is active until the capture value is read by the processor Therefore it is on for a maximum of 10 ms in Class 1 and a maximum of one scan or 10 ms whichever is shorter in Class 4 The preset counter value is held as long as the Z input remains active Because the count value is not changing the rate value equals zero while the preset value is held Store Preset Start The counter is set to its programmed preset value when the module detects a positive transition on the Z input of the counter The capture value is made available to the backplane A stored status bit is set in the input image table to signal the processor that a new value is available This bit is active until the capture value is read by the processor Therefore it is on for a maximum of 10 ms in Class 1 and a maximum of one scan or 10 ms whichever is shorter in Class 4 Publication 1746 UM002B EN P August 2004 2 8 Module Operation Summary of Available Counter Configurations Publication 1746 UMO002B EN P August 2004 Gate and Preset Limitations Because only the Z inputs are used for external gating and presetting the only gate preset modes available for Counters 3 and 4 are No Preset and Soft Preset Only All six modes are
33. not specified IMPORTANT The number of ranges for the last configured counter used must equal zero otherwise the module fills in the value and errors even if the value is correct Figure 4 4 Module Setup in Mode 3 Showing Hex Format 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Hex 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Word 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 Word 1 0 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Word 2 0 00 4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Word 3 0 00 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Word 4 0 00 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Word 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Word 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Word 7 0 0 0 0 Counter Configuration Figure 4 5 shows the format of the Counter Configuration Block This Block block programs the following parameters of the selected counters e Counter Type e Input Configuration e Gate Preset Mode All four counters can be programmed with one block When this programming block is sent to the module the selected counter s cannot be running or a programming error results Sending this programming block to the module erases all programmed output ranges of the selected counter s Publication 1746 UMO002B EN P August 2004 Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7 Configuration and Programming 4 11 Figure 4 5 Counter Configuration Block Format 15 14 13 12 11 10 09
34. of the programmed ranges and the state of the Output ON Mask When a bit in this mask is one the Configuration and Programming 4 27 output turns on based on the programmed ranges the state of the enabled ranges byte and the Output ON Mask TIP The outputs do not turn on if the corresponding bits are not set here Enable Range Word 6 When a bit in this word is reset 0 the corresponding range 1 16 is disabled and the output state for the range is ignored When a bit in this word is set 1 the corresponding output state for the range is used to determine the state of the eight outputs Bits in this word should be zero unless you want to specifically enable the range Determining Actual Output State The actual state of an output is determined in five steps as follows 1 The enable range bits determine if a range should be checked to see if it is active 2 The output state bytes of all active ranges that are enabled are logically ORed 3 The Output ON Mask is logically ORed with the results of step 2 4 The Output Enable Mask is logically ANDed with the results of step 3 5 The result is applied to the outputs a Outputs are always off when the SLC processor is in Program mode The outputs are only enabled when the processor is in the Run mode Outputs not assigned to a counter can only be turned on with the Output ON Mask Publication 1746 UM002B EN P August 2004 4 28 Configuration and
35. other ranges are automatically assigned to Counter 2 Set words 3 and 4 to 0 e In Mode 2 three counters are used The Counter 1 and Counter 2 allocation values are read All other ranges are automatically assigned to Counter 3 Set word 4 to 0 e In Mode 3 all four counters are used The Counter 1 Counter 2 and Counter 3 allocation values are read All other ranges are automatically assigned to Counter 4 The sum of the range allocation values cannot exceed 16 or the module responds with a programming error Unused range allocation words in Modes 1 and 2 must equal zero or an error occurs IMPORTANT The number of ranges for the last configured counter used must equal zero otherwise the module fills in the value and errors even if the value is correct Configuration and Programming 4 9 Range Allocation Examples Mode 1 Example In the Module Setup block below 4 ranges are assigned to Counter 1 The remaining 12 are assigned to Counter 2 The last counter is not specified Figure 4 2 Module Setup in Mode 1 Showing Hex Format 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Hex GeO i RE ee ah Ge 0 Oe E IF TU AR ee leg Word 0 0 0 0 1 EE 3 A e Me OUEST iO pg O ese OE OE n E De E Word 1 0 x 0 1 Be OF 507 habe L a8 7 D En rst PO AG EC o9 11 eB e de loa 0 Word 2 0 0 0 4 0olo olo olololo jojlololojololo o Word 3 0 0 0 0 0olo olo ololojlo jlolo
36. range allocation values module setup block 4 8 range control 2 12 2 14 count range 2 12 range enable block C 3 enable range words 4 27 range start value 4 20 4 22 C 2 range stop value 4 20 4 22 C 2 rate calculation 2 10 rate overflow bit 2 19 rate range 2 14 range type programming bit 4 21 with linear counter 2 14 rate underflow bit 2 19 rate value 2 9 2 10 4 22 accuracy 2 11 in class 1 4 18 in class 4 4 19 minimum maximum 4 16 4 19 real outputs 2 11 removing the module 3 4 ring counter 2 10 4 12 4 16 S soft preset only 2 6 specifications A 1 store continue 2 6 store hold resume 2 7 Publication 1746 UM002B EN P August 2004 4 Index store preset hold resume 2 7 store preset start 2 7 T temperature A 1 terminal wiring 3 7 throughput A 3 timing A 3 transmit bits 4 2 turn off time A 3 turn on time A 3 U UL listed A 1 underflow 5 4 counter underflow bit 2 19 linear counter 2 9 4 16 rate underflow bit 2 19 rate value 4 18 up and down pulses 2 3 Publication 1746 UM002B EN P August 2004 V virtual outputs 2 11 W wiring differential encoder 3 8 encoder wiring 3 8 grounding 3 5 important considerations 3 4 input and output connections 3 7 terminal wiring 3 7 terminals 3 7 X X1 quadrature encoder 2 4 X2 quadrature encoder 2 4 X4 quadrature encoder 2 4 Rockwell Automation Support www rockwellautomation com Rockwell Automation provides technical information on the web to as
37. the Counter Configuration Block The required bits for debug mode in the Counter Configuration Block are the transmit bit the debug bit and the block type byte Bits 13 and 14 must be zero The values of words 1 through 7 are ignored by the module while in debug mode The PGM n bits word 0 bits 08 to 11 are never set in this block Figure 5 4 Required Bits for Counter Configuration Block 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Word 0 0 0 010100 BLOCK TYPE TRMT DEBUG In the Minimum Maximum Count Value Block For this block the transmit bit the debug bit the block type byte and the counter number are required for each configured counter Word 0 must be used for each configured counter individually Bit 10 is ignored and bits 11 13 and 14 must be zero The values of words 1 through 7 are ignored by the module while in debug mode Figure 5 5 Required Bits for Min Max Count Value Block 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 E de wedo 3 0 013 0 x W BLOCK TYPE ke Ca TIP If the counter number entered is not valid the debug mode returns a programming error Start Up Operation Troubleshooting and Debug Mode 5 9 In the Minimum Maximum Rate Value Block For this block the transmit bit the debug bit the block type byte and the counter number are required for each configured counter Word 0 must be used for each configured coun
38. the display in data windows The first pass of the program initializes the following values 1 The HSCE2 initialization done bit B3 0 is unlatched 2 The HSCE2 error bit B3 1 is cleared 3 The Counter Configuration Block is cleared Note The init HSCE2 routine ladder file 9 is bypassed during the first pass to ensure the Configuration Data Block is reset prior to transfer of the first configuration data block FIRST PASS S 1 MOV 0000 J E Move 15 Source 0 0 Dest B3 0 000000001 1000001 HSCE2_CFG_BLK FLL Fill File Source 0 Dest 0 1 0 Length 8 DATA_BLOCK_OFFSET MOV Move Source Dest MAX_BLOCK_ADDR MUL Multiply Source A 10 10 lt Source B N11 2 17 lt Dest N11 1 170 lt While the HSCEZ is not initialized and the HSCE2 has not errored call the HSCEZ initialization routine FIRST_PASS HSCE2 INIT DONE HSCE2 ERROR S 1 B3 0 B3 0 JSR 0001 Jump To Subroutine SBR File Number U 9 Publication 1746 UM002B EN P August 2004 0002 0003 0004 Application Examples 6 17 Ladder File 8 Continued This rung implements a soft preset of counter 1 when the soft preset trigger bit sees a positive change 0 to 1 The rung assumes that the Counter Control Block last configuration block is still in the output image to the 1746 HSCE2 and that Counter 1 permits soft presets HSCE2 INIT DONE SOFT PRESET TRGR SOFT_PRESET_OSR B3 0 B3 0 B3 0 JL
39. when a pulse in the opposite direction is received CUdF Counter Underflow Bit When the counter is configured as a linear counter this bit is set when the count would become one under the minimum count value CState Counter State Bits These two bits show the operational state of the counter Table 2 3 Counter State Bit Settings Bits 09 or 01 Bits 08 or 00 Operating State 0 0 Stopped 0 1 Running 1 0 Hold 1 1 Reserved Publication 1746 UM002B EN P August 2004 2 20 Module Operation Publication 1746 UM002B EN P August 2004 Chapter 3 Compliance to European Union Directives Installation and Wiring This chapter provides the following information e compliance to European Union Directives e module installation e wiring considerations e input output connections e encoder wiring e switch wiring If this product has the CE mark it is approved for installation within the European Union and EEA regions It has been designed and tested to meet the following directives EMC Directive This product is tested to meet Council Directive 89 336 EED Electromagnetic Compatibility EMC and the following standards in whole or in part documented in a technical construction file EN50081 2 EMC Generic Emission Standard Part 2 Industrial Environment EN50082 2 EMC Generic Emission Standard Part 2 Industrial Environment This product is intended for use in an industrial enviro
40. 0 Maximum Rate 1 000 000 1 000 000 Preset Value 0 0 All Output Ranges Not programmed Interrupt Enable Interrupt disabled Rate Value Format Integer Table 4 15 Class 4 Mode 2 Default Values Parameter Counter 1 Counter 2 Counter 3 Debug Mode Selection Inactive Range Allocation 8 4 4 Counter Type Ring Ring Ring Input Configuration X1 Quadrature Pulse Internal Pulse Internal Gate Preset Mode Store Preset Start No Preset No Preset Minimum Count 8 388 607 8 388 607 8 388 607 Maximum Count 8 388 607 8 388 607 8 388 607 Minimum Rate 1 000 000 1 000 000 1 000 000 Maximum Rate 1 000 000 1 000 000 1 000 000 Preset Value 0 0 0 All Output Ranges Not programmed Interrupt Enable Interrupt disabled Rate Value Format Integer Publication 1746 UMO002B EN P August 2004 Table 4 16 Class 4 Mode 3 Default Values Configuration and Programming 4 31 Parameter Counter 1 Counter 2 Counter 3 Counter 4 Debug Mode Selection Inactive Range Allocation 4 4 4 4 Counter Type Ring Ring Ring Ring Input Configuration Pulse Internal Pulse Internal Pulse Internal Pulse Internal Gate Preset Mode No Preset No Preset No Preset No Preset Minimum Count 8 388 607 8 388 607 8 388 607 8 388 607 Maximum Count 8 388 607 8 388 607 8 388 607 8 388 607 Minimum Rate 1 000 000 1 000 000 1 000 000 1 000 000 Maximum Rate 1 000 000 1 000 000 1 000 000 1 000 000 Preset Value 0 0 0 0
41. 0 is unlatched 2 The HSCE2 error bit B3 1 is cleared 0000 0001 0002 FRST PASS HSCE2 INIT DONE S1 B3 0 L 4 U 0 HSCE2 ERROR B3 0 U5 15 HSCE2_CFG_BLK FLL Fill File Source 0 Dest 0 1 0 Length DATA_BLK_PTR MOV Move Source Dest MUL Multiply Source A Source B Dest If the HSCE2 initialization is not done and the HSCE2 has not errored call the HSCE2 initialization routine FIRST_PASS HSCE2_INIT_DONE HSCE2_ERROR S 1 B3 0 B3 0 JSR 2t E d Jump To Subroutine 15 0 1 SBR File Number U 9 Publication 1746 UM002B EN P August 2004 Application Examples 6 9 Ladder File 9 HSCE2 Initialization Routine Programming ladder file 9 shows the indirect addressing required to set up the programming blocks in this example 0000 0001 0002 0003 0004 DATA_BLOCK_PTR HSCE2_XMIT HSCE2_ACK LES O 1 I1 Less Than A B Source A N11 0 15 15 1746 HSCE2 1746 HSCE2 Source B N11 1 HSCE2 XMIT HSCE2_ACK O 1 I1 3i 15 15 1746 HSCE2 1746 HSCE2 If the blocks have not all been transmitted block data offset max block offset copy b When HSCE2 sets its acknowledge bit l e 0 15 reset the module transmit bit 0 e 0 15 and check HSCE2 error bits l n 1 If no error bits are ON increment the block counter to permit the next move to start
42. 0 4 0 64 0 95 4 0 0 0 N10 90 10 8 0 96 0 C7 8 0 0 0 N10 100 10 10 0 C8 0 F9 1 0 0 0 N10 110 10 20 0 FA 0 B 2 0 0 0 N10 120 10 40 0 120 0 15D 4 0 0 0 N10 130 10 80 0 1E 0 190 8 0 0 0 N10 140 80 8001 8001 8001 8001 FFOO FF 0 0 0 N10 150 0 0 0 0 0 0 0 0 Data Table for N11 File decimal Offset 0 1 2 3 4 5 6 7 8 9 N11 0 140 140 14 In this example the module is set up in Class 4 mode 1 using only two counters This example uses indirect addressing which is compatible only with SLC 5 03 or higher processors TIP This example may be used with any mode 1 2 or 3 and with any SLC 5 03 or higher processor as long as the module is in a local chassis However the N10 and N11 data files would need to be modified for a different configuration Publication 1746 UM002B EN P August 2004 6 8 Application Examples Ladder File 8 HSCE2 Prior to use the programmer sets N11 2 to the total number of data blocks which will be entered into file N10 not including the Counter Control Block adds one rung for each configuration block including the Counter Control Block and initializes the data blocks in file N10 Ten integer data blocks are used instead of eight to simplify the display in data windows Note The Counter Control Block rung differs from the other rungs because the Counter Control Block does not require hand shaking The first pass of the program initializes the following values 1 The HSCE2 initialization done bit B3
43. 0 lt 110 110 lt HSCE2_XMIT O 1 15 1746 HSCE2 HSCE2 ACK I1 15 1746 HSCE2 COP Copy File Source N10 110 Dest 0 1 0 Length 8 HSCE2_XMIT O 1 15 1746 HSCE2 Publication 1746 UM002B EN P August 2004 6 6 X Application Examples Ladder File 9 Continued When the previous block is completed transmit and acknowledge bit are reset copy Programming Ranges Block 8 for counter 1 to the HSCE2 and set transmit bit 0 e 0 15 DATA BLOCK PTR HSCE2_XMIT HSCE2_ACK EQU O 1 I1 COP 0012 Equal Copy File Source A N11 0 15 15 Source N10 120 140 z Dest 0 1 0 Source B 120 1746 HSCE2 1746 HSCE2 Length 8 120 lt HSCE2_XMIT O 1 When the previous block is completed transmit and acknowledge bit are reset copy Counter 15 Configuration Block to the HSCE2 and set transmit bit 0 e 0 15 1746 HSCE2 DATA_BLOCK_PTR HSCE2_XMIT HSCE2_ACK EQU O 1 I COP 0013 Equal Copy File Source A 15 15 Source N10 130 1746 HSCE2 1746 HSCE2 Dest 0 1 0 Source B Length 8 HSCE2_XMIT O 1 When HSCE2 sets its acknowledge bit l e 0 15 reset transmit bit 0 e 0 15 SP and check HSCE2 programming error bit l e 0 13 If the error bit is clear 1746 HSCE2 increment the block counter to permit the next block move to start HSCE2_XMIT HSCE2_ACK HSCE2_XMIT O 1 1 1 O 1 14 n 15
44. 1 operation Depending on the operating mode the module only transmits the counter s count or rate value The count value is transmitted when the C R n bit is reset The rate value is transmitted when the C R n bit is set When configured for Class 4 setting these bits generates a programming error P n Program Counter n Bit Words 1 to 4 Bit 15 If this bit is reset bits 1 to 14 must be zero or a programming error results This bit must be set before the counter control bits are updated for the counter This allows the user to write 0000H into unused words in the block without inadvertently changing the state of a counter When this bit is zero all other bit values in the word are retained inside the module This affects the soft preset SP n as described in the note on page 4 25 Output ON OR Mask Word 5 Bits 00 to 07 This is a bit pattern which allows the user program to globally turn on outputs regardless of the programmed ranges and Enable Ranges bytes When a bit in this byte is zero the output will turn on based on the programmed ranges the state of the enable ranges byte and Output Enable Mask When this bit is one the output is on if the corresponding bit in the Output Enable Mask equals one Output Enable Mask Word 5 Bits 08 to 15 This is a bit pattern to globally turn off outputs regardless of the programmed ranges and enable ranges bytes When a bit in this mask is zero the output is off regardless
45. 15 15 1746 HSCE2 1746 HSCE2 1746 HSCE2 DATA BLOCK PTR MEQ ADD Masked Equal Add Source Source A N11 0 Mask Source B Compare Dest Note The Counter Control Block does not require a 0 1 positive transition of the transmit bit 0 3 0 15 to operate DATA BLOCK PTR HSCE2 XMIT HSCE2_ACK EQU O 1 I COP 0015 Equal Copy File Source A N11 0 15 15 Source N10 140 140 lt 1746 HSCE2 1746 HSCE2 Dest 0 1 0 Source B N11 1 Length 8 140 lt HSCE2_INIT_DONE B3 0 If the PERR bit or HSCE2 fault bit is set set the HSCE2 error bit B3 1 Qo HSCE2_ACK HSCE2_PERR HSCE2 ERROR 1 I B3 0 0016 J E J L5 15 13 1 1746 HSCE2 1746 HSCE2 HSCE2_FAULT 1 1 14 1746 HSCE2 0017 CEND gt Publication 1746 UM002B EN P August 2004 Programming Blocks Module Setup Counter Configuration Min Max Count Value Counter 1 Min Max Count Value Counter 2 Min Max Count Value Counter 3 Min Max Count Value Counter 4 Program Program Program Program Program Program Program Program Ranges Ranges Ranges Ranges Ranges Ranges Ranges Ranges Counter Control Example 2 Indirect Addressing Application Examples 6 7 Data Table for N10 File hexidecimal Offset 0 1 2 3 4 5 6 7 8 9 N10 0 1 100 8 0 0 0 0 0 0 0 N10 10 FOZ 6 0 6 0 0 0 0 0 0 N10 20 4 0 0 0 199 0 0 0 0 0 N10 30 104 0 0 0 1M 0 0 0 0 0 N10 40 204 0 0 0 28 0 0 0 0 0 N10 50 304 0 0 0 2B0 0 0 0 0 0 N10 60 10 1 0 0 0 31 1 0 0 0 N10 70 10 2 0 32 0 63 2 0 0 0 N10 80 1
46. 2 B2 A2 B2 Z2 OUTPUT COMMON OUTPUT 1 OUTPUT 3 Z2 OUTPUT 0 OUTPUT 2 OUTPUT Vde e la la la al e le la je sa al amp 9 la la la a el el Release Screw Removing the Terminal Block Remove the terminal block by turning the slotted terminal block release screws counterclockwise The screws are attached to the terminal block so it will follow as the screws are turned out ATTENTION To avoid cracking the removable terminal block alternate turning the slotted terminal block release SCrews Publication 1746 UM002B EN P August 2004 3 8 Installation and Wiring Encoder Wiring Publication 1746 UM002B EN P August 2004 Differential encoders provide the best immunity to electrical noise We recommend whenever possible to use differential encoders The wiring diagrams on the following pages are provided to support the Allen Bradley encoders you may already own Differential Encoder Wiring Figure 3 5 Differential Encoder Wiring Cable Allen Bradley 845H Series differential encoder Shield shield housing Connect only if housing is electronically isolated from the motor and ground Module Inputs 1 Refer to your encoder manual for proper cable type The type of cable used should be twisted pair individually shielded cable with a maximum length of 300m 1000 ft Differential Encoder Output Waveforms The Fi
47. 2 767 32 767 32 767 Maximum Count 132 767 132 767 132 767 Minimum Rate 32 767 32 767 32 767 Maximum Rate 132 767 132 767 132 767 Preset Value 0 0 0 All Output Ranges Not programmed Interrupt Enable Interrupt disabled Rate Value Format Integer not programmable Table 4 13 Class 1 Mode 3 Default Values Parameter Counter 1 Counter 2 Counter 3 Counter 4 Debug Mode Selection Inactive Range Allocation 4 4 4 4 Counter Type Ring Ring Ring Ring Input Configuration Pulse Internal Pulse Internal Pulse Internal Pulse Internal Gate Preset Mode No Preset No Preset No Preset No Preset Minimum Count 32 767 32 767 32 767 32 767 Maximum Count 132 767 132 767 132 767 132 767 Minimum Rate 32 767 32 767 32 767 32 767 Maximum Rate 32 767 32 767 32 767 32 767 Preset Value 0 0 0 0 All Output Ranges Not programmed Interrupt Enable Interrupt disabled Rate Value Format Integer not programmable Publication 1746 UM002B EN P August 2004 4 30 Configuration and Programming Class 4 Table 4 14 Class 4 Mode 1 Default Values Parameter Counter 1 Counter 2 Debug Mode Selection Inactive Range Allocation 8 8 Counter Type Ring Ring Input Configuration X1 Quadrature X1 Quadrature Gate Preset Mode Store Preset Start Store Preset Start Minimum Count 8 388 607 8 388 607 Maximum Count 8 388 607 8 388 607 Minimum Rate 1 000 000 1 000 00
48. 3 E B E S SERT After the soft preset is complete unlatch the soft preset bit 0 1 1 1 To determine if the soft lt lt lt preset is complete compute the current counter 1 count value F8 0 compute the valid preset J HSCE2 CFG BLK 17 range this example uses 10 PRESET VALUE from the Min Max Count block and compare O1 SOFT_PRESET_OSR HSCE2_CFG_BLK 17 L B3 0 O 1 17 J E E 1746 HSCE2 6 17 1746 HSCE2 CTR1 COUNTS CPF Compute Dest F8 0 130 0 lt Expression 1000 0 1 2 1 1 3 PRESET_UPPER_LIMIT CPF Compute Dest F8 1 140 0 lt Expression N10 25 1000 0 N10 26 10 0 PRESET LOWER LIMIT CPT Compute Dest F8 2 120 0 Expression N10 25 1000 0 N10 26 10 0 CTR1 COUNTS HSCE2 CFG BLK 17 LIM O 1 Limit Test I CU Low Lim F8 2 17 120 0 1746 HSCE2 Test F8 0 130 0 High Lim F8 1 140 0 CEND gt Ladder File 9 HSCE2 Initialization Routine See the ladder logic from Example 2 on page 6 9 Publication 1746 UM002B EN P August 2004 6 18 Application Examples Programming Blocks Module Setup Counter Configuration Min Max Count Value Counter 1 Min Max Count Value Counter 2 Min Max Rate Value Program Program Program Program Program Program Program Program Program Program Program Program Ranges Ranges Ranges Ranges Ranges Ranges Ranges Ranges Ranges R
49. 7 06 05 04 03 02 01 00 Hex Format ojo ojlolojojolo 1 o o o o o 0o 0 Wedo o o 8 O P 0l0 0 0 0 0 amp 0 0 0 0 0 BS E Z Wordt 0 ce LL 72 0j0 0 0 0 0 2 0 0 0 0 0 S amp 2 Word2 0 c zl LL 50 0 0 0 0 0 2 0 0 0 0 0 E Z Word3 0 cC PE Lu P40 0 0 0 0 0 amp 0 0 0 0 0 ES IS Z words 0 cC ase Lu Output Enable Mas Output ON OR Mask Word 5 Enable Ranges Word 6 RESERVED Must equal zero Word7 0 0 0 0 Publication 1746 UM002B EN P August 2004 C 4 Module Programming Quick Reference Publication 1746 UM002B EN P August 2004 Appendix D Frequently Asked Questions This appendix presents some of the more commonly asked questions about application and operation of the Multi channel High Speed Counter Module The following questions and answers do not cover all possible questions but are representative of the more common ones Q What happens when my processor faults All outputs will turn off In a remote chassis the status of the outputs when the processor faults is dependent upon the last state bit Q What happens to my outputs if place the processor in program mode All outputs turn off The inputs remains active and the module keeps counting When the processor is returned to RUN mode all defaults are restored 0 What does it mean when the indicator for a particular input is on If the indicator is on it means that input voltage is present If the indicator is of
50. 8 FF9C 0 64 0 0 0 0 0 0 Program Ranges N10 50 410 1 0 0 4 3E7 1 0 0 0 Program Ranges N10 60 410 2 5 0 9 3E7 2 0 0 0 Program Ranges N10 70 410 4 A 0 E 3E7 1 0 0 0 Program Ranges N10 80 410 8 F 0 13 3E7 2 0 0 0 Program Ranges N10 90 410 10 14 0 18 3E7 1 0 0 0 Program Ranges N10 100 410 20 19 0 1D 3E7 2 0 0 0 Program Ranges N10 110 410 40 1E 0 22 3E7 1 0 0 0 Program Ranges N10 120 410 80 23 0 21 3E7 2 0 0 0 Program Ranges N10 130 110 100 0 0 1 31F 4 0 0 0 Program Ranges N10 140 110 200 1 320 3 257 8 0 0 0 Program Ranges N10 150 110 400 3 258 5 18F 4 0 0 0 Program Ranges N10 160 110 800 5 190 7 C7 8 0 0 0 Counter Control N10 170 80 8001 8001 0 0 FFOO FFF 0 0 0 Data Table for N11 File decimal Offset 0 1 2 3 4 5 6 7 8 9 N11 0 170 170 17 Example 3 Block Transfers In this example the module is set up in Class 1 Mode 3 using two counters This example uses indirect addressing and block transfers with a PLC 5 scanner Three rungs are added to ladder file 8 the HSCE2 routine 1 Repeating block transfer writes BTW to send eight words of data to the remote 1746 HSCE2 module 2 Repeating block transfer reads BTR to read eight words of data from the remote 1746 HSCE2 module 3 A rung to latch the first BTR done bit when it was satisfactory to start the 1746 HSCE2 initialization ladder file 9 The 1746 HSCE2 initialization routine ladder file 9 is nearly the same as the local examples examples 1 and 2 except the I O image Pu
51. Allen Bradley Multi Channel High Speed Counter Catalog Number 1746 HSCE 2 User Manual Rockwell Automation Important User Information Because of the variety of uses for the products described in this publication those responsible for the application and use of these products must satisfy themselves that all necessary steps have been taken to assure that each application and use meets all performance and safety requirements including any applicable laws regulations codes and standards In no event will Rockwell Automation be responsible or liable for indirect or consequential damage resulting from the use or application of these products Any illustrations charts sample programs and layout examples shown in this publication are intended solely for purposes of example Since there are many variables and requirements associated with any particular installation Rockwell Automation does not assume responsibility or liability to include intellectual property liability for actual use based upon the examples shown in this publication Allen Bradley publication SGI 1 1 Safety Guidelines for the Application Installation and Maintenance of Solid State Control available from your local Rockwell Automation office describes some important differences between solid state equipment and electromechanical devices that should be taken into consideration when applying products such as those described in this publication Repr
52. CE2 routine ladder file 8 Before and after the Min max Count Block with the new preset value is transferred to the 1746 HSCE2 the Counter Control Block with the transmit bit reset is in the 1746 HSCE2 s output image Leaving the Counter Control Block in the module s output image allows for easy disabling of the counters and implementing of soft presets Application Examples 6 19 4 Data word N10 11 was changed from 000C hex to 001C hex to change the Counter 1 gate preset mode from No Presets 000 to Soft Presets Only 001 Ladder File 8 HSCE2 Prior to use the programmer sets N11 2 to the total number of data blocks which will be entered into file N10 not including the Counter Control Block and initializes the data blocks in file N10 Ten integer data blocks are used instead of eight to simplify the display in data windows The first pass of the program initializes the following values 1 The HSCE2 initialization done bit B3 0 is unlatched 2 The HSCE2 error bit B3 1 is cleared 3 The Counter Configuration Block is cleared Note The init HSCE2 routine ladder file 9 is bypassed during the first pass to ensure the Configuration Data Block is reset prior to transfer of the first configuration data block HRST PASS S 1 MOV 0000 E Move 15 Source 0 0 Dest B3 0 000000001 1000001 HSCE2_CFG_BLK FLL Fill File Source 0 Dest MOV Move Source Dest
53. Data Publication 1746 UM002B EN P August 2004 1 Bits 0 through 3 are real outputs Bits 4 through 7 are virtual outputs The format of the counter input data table depends on the module s mode and class of operation The status data formats for Class 1 and Class 4 are shown below followed by explanations of the programming bits and status bytes Mode 1 is the default for both Class 1 and Class 4 operation Module Operation 2 15 Class 1 Operation In this operating class the input data consists of eight words The counters are sixteen bits The data stored in an input word change based on the module s operating mode Figure 2 10 Mode 1 Input Data Format 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Word 0 T E 0 OP Output State E ES to E MODE Virtual Real Word 1 Counter 2 Status Counter 1 Status Word 2 Counter 1 Count Value Word 3 Counter 1 Rate Value Word 4 Counter 1 Capture Value Word 5 Counter 2 Count Value Word 6 Counter 2 Rate Value Word 7 Counter 2 Capture Value 1 See page 2 6 for a description of capture values Figure 2 11 Mode 2 Input Data Format 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Word 0 NEM E 0 OP Output State S ES e amp MODE Virtual Real Word 1 Counter 2 Status Counter 1 Status Word 2 Counter 1 Count
54. Operating Class as d bee dre HU HR FI n 4 1 POWEEUD Resetos s coi eig ae ae ab C ILE tea 4 1 Module Programming 2621 4 ou pee ey hy ad Re Eon cs 4 1 Programming CVC Es FAA 4 2 Data Format ache Zap Colt oe ee Rode S eed 4 3 Table of Contents iii Module Setup Block cuerpo PRESS 4 6 Programming Block Identification Bit 4 6 TRMT Transmit Bit o ooo ee 4 6 DEBUG Debug Mode Selection Bit 4 6 INT Interrupt Enable 5 5 2 irr E RI TR PRETEREA 4 7 RVF Rate Value Forti ad ad 4 7 PRA Program Range Allocation 4 7 Op Mode Operating Mode ono on sa 4 8 Range Allocation Values coss du eR RE den 4 8 Range Allocation Examples dardo 4 9 Counter Configuration Block datada P a 4 10 Programming Block Identification Bit 4 11 TRMT Transmit Bit o ERO Qe PER ex ER 4 11 DEBUG Debug Mode Selection Bit 4 11 PGMn Program Counter Number Bits 4 12 CIvpe Counter Type Bit uu ni do DR Eme f oe 4 12 Input Config Input Configuration Bits 4 12 G P Mode Gate Preset Mode Bits 4 13 Minimum Maximum Count Value Block 4 13 Programming Block Identification Bit 4 14 TRMT Transmit Bis as eta eae AEESARtSPITRSAS 4 14 DEBUG Debug Mode Selection Bit 4 14 AUTO PRESET Automatic Preset Bit 4 14 CNTR No Counter Number Bits 4 15 Preset Value y
55. P4 A2 JP5 B2 JP6 Z2 OL Jumper Settings 5V dc 24V dc 4 2 12V dc 10 30V dc default IMPORTANT Beh 12V dc encoder signal use the 24V dc jumper setting ATTENTION If jumpers are not set to match the encoder type the A module may be damaged The 5V dc settings respond to inputs with an active voltage between 4 2 and 12 volts The 24V dc settings respond to inputs with active or high settings between 10 and 30 volts ATTENTION Disconnect power before attempting to install remove or wire the module Publication 1746 UM002B EN P August 2004 3 4 Installation and Wiring 1 Make sure your SLC power supply has adequate reserve current capacity The module requires 250 mA at 5V dc 2 Align the full sized circuit board with the chassis card guide as shown in Figure 3 2 The first slot of the first chassis is reserved for the processor 3 Slide the module into the chassis until the top and bottom latches catch To remove the module press the release clips at the top and bottom of the module and slide it out 4 Cover all unused card slots with the Card Slot Filler catalog number 1746 N2 Figure 3 2 Installing the Module piv WwW Ww WwW y Y Sy w WN 5 cx x gt ngun Important Wiring Use the following guidelines when planning the system wiring for the dule Consider
56. Programming Figure 4 10 Determining Actual Outputs Range Bit Setting 1 1 0 0 1 1 0 0 Output ON Mask 0 0 0 1 0 0 0 1 Output Enable Mask 0 0 0 0 1 1 1 1 Actual Outputs 0 0 0 0 1 1 0 1 Programming Block Default The following tables list the default values for all of the programmed Values parameters in each class and operating mode The default operating mode for each class is mode 1 Class 1 Table 4 11 Class 1 Mode 1 Default Values Parameter Counter 1 Counter 2 Debug Mode Selection Inactive Range Allocation 8 8 Counter Type Ring Ring Input Configuration X1 Quadrature X1 Quadrature Gate Preset Mode Store Preset Start Store Preset Start Minimum Count 32 767 32 767 Maximum Count 32 767 32 767 Minimum Rate 32 767 32 767 Maximum Rate 32 767 32 767 Preset Value 0 0 All Output Ranges Not programmed Interrupt Enable Interrupt disabled Rate Value Format Integer not programmable Publication 1746 UM002B EN P August 2004 Table 4 12 Class 1 Mode 2 Default Values Configuration and Programming 4 29 Parameter Counter 1 Counter 2 Counter 3 Debug Mode Selection Inactive Range Allocation 8 4 4 Counter Type Ring Ring Ring Input Configuration X1 Quadrature Pulse Internal Pulse Internal Gate Preset Mode Store Preset Start No Preset No Preset Minimum Count 3
57. Pw Gre eed x 2 9 Linear Counter es onc cai ld eer cede e dot ar 2 9 Ring Counter tod ad lie doia 2 10 R te Valie poira A ear A AS ES 2 10 a A IN E 2 11 Output Control aasa aasa aaa 2 11 Range Contolera Pax rE E PEREA PERA 2 12 Count Range eedem quee bog daa pisan 2 12 Rate Range u sequi ta da Hitt tt Ate dapi Baden Ge Bes 2 14 Counter Input EIS consensu Ys arn koe chat 2 14 Class T Operador aos SO iau Pate oS d 2 15 Class v ODER ares eno d uir dor oce de ELA 2 16 Input Word Bit Values llle oo 2 17 Output AS ByE C uua See eed a ee dee te 2 18 Counter Status Bytes V ew Sd eA tu SV See Eas 2 18 Chapter 3 Compliance to European Union DirectiveS 3 1 EMCIDITGCLUVO my rm qe A EATER SS 3 1 Low Voltage Directive a vu eae br y pop eiae 3 1 Prevent Electrostatic Discharge sees 3 2 Setting the TUmpets ian qeu t ap Co a P 3 2 Installing the Module siu eo REMEESIDE RA ES a PS 3 3 Important Wiring Considerations lille 3 4 Considerations for Reducing Noise 3 5 Flectronic Protection o n ac totns ded A ee 3 6 Auto Reset Operation 15 a4 4G os gd FE pot pines 3 6 Input and Output Connections llle 3 7 Removing the Terminal Blocs Se AS 3 7 ENCORE WING siirre hee Oh APENAS EEES e 3 8 Differential Encoder Wiring oonan anaana 3 8 Single Ended Encoder Wiring Open Collector 3 9 Single Ended Wiring Discrete Devices 3 10 Chapter 4 Selecting
58. RTANT debug mode Setting the debug bit word 0 bit 12 in the Counter Control block causes the block to ignore all commands However rates and counts continue to be counted When the debug bit is reset the module resumes accepting commands Activating Debug Mode Setting the debug bit word 0 bit 12 in the programming block activates the debug mode You must also set the block type code the low byte of word 0 to identify the programming block The transmit TRMT acknowledge ACK and programming error PERR bit operation is unaffected by debug mode Depending upon the programming block other bits may also be required as described below In the Module Setup Block For the Module Setup Block the required bits for the debug mode are the transmit bit the debug bit and the block type byte All other bits in the module setup word O must be set to 0 Words 1 through 7 are ignored by the module while in debug mode Publication 1746 UM002B EN P August 2004 5 8 Start Up Operation Troubleshooting and Debug Mode Publication 1746 UMO002B EN P August 2004 Figure 5 3 Required Bits for Module Setup and Counter Configuration Blocks 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Word 0 0 0 0 0 0 0 BLOCK TYPE TRMT DEBUG The debug view of this block shows the range allocation of all four counters The fourth counter is shown in word 5 The PRA bit Gword 0 bit 08 is never set In
59. Source N10 40 140 lt 1746 HSCE2 1746 HSCE2 Dest 0 1 0 Source B 40 Length 8 40 lt HSCE2_XMIT O 1 CL 15 When the previous block is completed transmit and acknowledge bit are reset copy Programming 1746 HSCE2 Range Block 1 for counter 1 to the HSCE2 and set transmit bit 0 e 0 15 DATA_BLOCK_PTR HSCE2_XMIT HSCE2_ACK EQU 0 1 I COP 0005 Equal Copy File Source A N11 0 15 15 Source N10 50 140 lt 1746 HSCE2 1746 HSCE2 Dest 0 1 0 Source B 50 Length 8 50 lt HSCE2_XMIT O 1 15 1746 HSCE2 When the previous block is completed transmit and acknowledge bit are reset copy Programming Ranges Block 2 for counter 1 to the HSCE2 and set transmit bit 0 e 0 15 DATA BLOCK PTR HSCE2_XMIT HSCE2_ACK EQU O 1 I1 COP 0006 Equal Lf V1 Copy File Source A N11 0 15 15 Source N10 60 140 lt 1746 HSCE2 1746 HSCE2 Dest 0 1 0 Source B 60 Length 8 60 lt HSCE2_XMIT O 1 15 1746 HSCE2 When the previous block is completed transmit and acknowledge bit are reset copy Programming Ranges Block 3 for counter 1 to the HSCE2 and set transmit bit 0 e 0 15 DATA BLOCK PTR HSCE2_XMIT HSCE2_ACK EQU O 1 I COP 0007 Equal Vt Vt Copy File Source A N11 0 15 15 Source N10 70 140 lt 1746 HSCE2 1746 HSCE2 Dest 0 1 0 Source B 70 Length 8 70 lt HSCE2_XMIT O 1 CL 15 1746 HSCE2 Publication 1746 UM002B EN P August 2004 Application Examples 6 5 Ladder File 9 Continued When t
60. Table for N11 File decimaD 6 18 Example 5 Change Presets Dynamically 6 18 Data Table for N10 File hexidecimab 6 22 Data Table for N11 File decimaD 6 22 Specifications Connecting a Differential Encoder Module Programming Quick Reference Frequently Asked Questions Comparing 1746 HSCE2 to 1746 HSCE Table of Contents v Example 6 Retentive Counters noonoo uaaa 6 23 Data Table for N10 File hexidecimab 6 25 Data Table for N11 File decimaD 6 25 Appendix A General hg bie end pecs O E AO A 1 Inputs A B and Z ok poke one pos RO RR A 2 Outputs Sourcing cu aa 4 oo we b CT Re aot iden a OE A 2 On State Current Derating o o o o ooooo o o A 3 Throughput and Timing 141 us ra PEIPER a A 3 Appendix B Appendix C Appendix D Appendix E Glossary Index Publication 1746 UM002B EN P August 2004 Table of Contents vi Publication 1746 UM002B EN P August 2004 Summary of Changes The information below summarizes the changes to this manual since the last printing To help you find new information and updated information in this release of the manual we have included change bars as shown to the right of this paragraph New Information The table below lists sections that include new information For this new information See page s Note on limitations of rate value calculation at input frequencies 2
61. UM011 for more information on transient pulses and guidelines to reduce inadvertent processor operation Specifications A 3 On State Current Derating E 20A e Ss 15A ce o 55 10A 52 E 0 5 A OC 20 C 40 C 60C Temperature Throughput and Timing Timing us Operation Description Minimum Typical Maximum Throughput The delay between the time the module receives a pulse and when 300 700 1600 its real outputs and the SLC backplane are updated based on a count range Input File Update The delay between the time the module receives a pulse and when 300 600 1500 Time the backplane count value is updated including setting the 1 0 interrupt Output Turn on The time it takes for the real output to reach 9096 output voltage 10 Time after commanded by the module not including SLC scan time Output Turn off The time it takes for the real output to reach 10 output voltage zs 100 Time after commanded by the module not including SLC scan time Inductive Turn off The time between the module receiving an input pulse and breaking 50 Time contact in a BULLETIN 110 contactor Rate Accuracy The accuracy of the reported rate as compared to actual input rate in 0 005 0 015 the equation reported rate actual input rate Publication 1746 UM002B EN P August 2004 A 4 Specifications Publication 1746 UM002B EN P August 2004 Appendix B Connecting a Differential Enco
62. Value Word 4 Lower 3 digits Maximum Count Value Word 5 Upper 4 digits Preset Value Word 6 Lower 3 digits Preset Value Word 7 RESERVED Must equal zero Programming Block Identification Bit Word 0 Bit 02 This bit identifies the type of block TRMT Transmit Bit Word 0 Bit 15 A 0 to 1 transition starts a programming cycle DEBUG Debug Mode Selection Bit Word 0 bit 12 When this bit is set the debug mode is activated Debug mode returns the input data file showing current settings in the Min Max Count Value block For details see Debug Mode Operation on page 5 7 AUTO PRESET Automatic Preset Bit Word 0 bit 10 This bit is used to automatically preset the count value If this bit is set CD when the programming block is sent the count value is set to its preset value If the bit is reset 0 the count value is not changed Configuration and Programming 4 15 CNTR No Counter Number Bits Word 0 Bit 08 and 09 These two bits select the counter to which this programming block is applied Table 4 6 Counter Number Bit Settings Bit 09 Bit 08 Counter Number 0 0 Counter 1 0 1 Counter 2 1 0 Counter 3 1 1 Counter 4 Preset Value Words 5 and 6 The preset value can be programmed to any number between the minimum count value and the maximum count value If the preset value does not fall between the minimum and maximum count values a programming error results The preset value
63. ammed to operate as a linear or ring counter Both types are described below Linear Counter The figure below demonstrates linear counter operation In linear operation the count value must remain within the programmed minimum maximum values If the count value goes above or below these values the counter stops counting and an overflow underflow bit is set In the overflow or underflow condition the rate value continues to be updated and valid The number of pulses accumulated in an overflow underflow state are ignored The counter begins counting again when pulses are applied in the proper direction For example if you exceed the maximum by 1 000 counts you do not need to apply 1 000 counts in the opposite direction before the counter begins counting down The first pulse in the opposite direction decrements the counter Figure 2 5 Linear Counter Diagram Minimum Value 0 Maximum Value Count Up r Counter Value lt Count Down Underflow Overflow Publication 1746 UM002B EN P August 2004 2 10 Module Operation Rate Value Publication 1746 UM002B EN P August 2004 Ring Counter Figure 2 6 demonstrates ring counter operation In ring counter operation the count value changes between programmable minimum and maximum values If when counting up the counter reaches the maximum value it rolls over to the minimum value If when counting down the counter reaches the minimum value it rolls over to the ma
64. amming Block Identification Bit Word 0 Bit 0 This bit identifies the type of block TRMT Transmit Bit Word 0 Bit 15 A 0 to 1 transition starts a programming cycle This bit is not set until all words are in the output table DEBUG Debug Mode Selection Bit Word 0 Bit 12 When this bit is set the debug mode is activated Debug mode returns the input data file showing current settings in the module setup block Up to three sets of ranges can be allocated The last set is always allocated automatically If three sets of ranges are allocated the fourth and last set is shown in word 5 in debug mode For details see Debug Mode Operation on page 5 7 Configuration and Programming 4 7 INT Interrupt Enable Word 1 Bit 10 aa Interrupt mode is not available in Class 1 Setting this bit while using Class 1 causes a programming error In Class 4 when this bit is set 1 the module generates an I O interrupt to the SLC processor whenever one of the eight outputs changes state When this bit is reset 0 the module will not generate an interrupt IMPORTANT Ae I O interrupt must be defined if the INT bit is set The I O interrupt subroutine number is defined in the advanced configuration window of the program s I O configuration See the SLC 500 Instruction Set Reference Manual publication number 1747 RMO001 for more information on I O interrupts RVF Rate Value Format Word 1 Bit 09 IMPORTANT This bit
65. amming block is applied The counter number and range number must correspond to a valid combination as determined by the information in the Module Setup Block See Range Allocation Values on page 4 8 Table 4 9 Counter Number Programming Bit Settings Bit09 Bit 08 Counter Number 0 0 Counter 1 0 1 Counter 2 1 0 Counter 3 1 1 Counter 4 The valid range of this parameter is dependent on the programmed operating mode Rtype Range Type Word 0 Bit 10 When this bit equals zero the range specified in this block is a count range The output state is active when the count value of the associated counter is within the programmed range When this bit equals one the range specified is a rate range The output state is active when the rate value of the associated counter is within the programmed range Range No Range Number Bits Word 1 Bits 00 to 15 These bits define which ranges 0 15 will be programmed or reset If a bit is set 1 the corresponding range is programmed The number of ranges available is programmed with the range allocation parameters in the Module Setup programming block Publication 1746 UM002B EN P August 2004 4 22 Configuration and Programming Publication 1746 UMO002B EN P August 2004 The range number word is subject to the following special conditions e If the range start value equals the range stop value and word 6 equals zero the range indicated is reset e If a range o
66. anges Ranges Ranges Counter Control Offset 10 0 10 10 10 20 10 30 10 40 10 50 10 60 10 70 10 80 10 90 120 130 140 150 160 170 Za E A A A EA A E A A ZA 2222235 2C i X Data Table for N10 File hexidecimal 0 1 302 o O gt ER er er hh HH gt gt gt gt gt gt N gt gt gt gt gt OOO OOOOoOOoOoosoOo co o 1 2 3 4 5 6 1 8 9 101 8 0 0 0 0 0 0 0 1C 0 C 0 0 0 0 0 0 0 0 2 30 0 82 0 0 0 0 0 7 C8 0 0 0 0 0 FF9C 0 64 0 0 0 0 0 0 1 0 0 4 3E7 1 0 0 0 2 5 0 9 3E7 2 0 0 0 4 A 0 E 3E7 1 0 0 0 8 F 0 13 3E7 2 0 0 0 10 14 0 18 3E7 1 0 0 0 20 19 0 1D 3E7 2 0 0 0 40 1E 0 22 3E7 1 0 0 0 80 23 0 27 3E7 2 0 0 0 100 0 0 1 31F 4 0 0 0 200 1 320 3 257 8 0 0 0 400 3 258 5 18F 4 0 0 0 800 5 190 7 C7 8 0 0 0 8001 8001 0 0 FF00 FFF 0 0 0 Data Table for N11 File decimal Offset N11 0 0 1 2 3 4 5 6 1 8 9 170 170 17 Example 5 Change Presets This example shows the user how to dynamically change the preset Dynamically Publication 1746 UM002B EN P August 2004 value 1 using the Min max Count Block The following procedure uses the Example 2 program SLC 5 03 or higher processor in Class 4 mode 1 The Min max Count Value requires the use of handshaking bits to get the preset values into the 1746 HSCE2 Therefore the handshaking code is in a separate subroutine ladder file 14 The ladder rungs which trigger the dynamic preset change are in the 1746 HS
67. anual you can e view and download a free electronic version from the internet at www rockwellautomation com literature e purchase a printed manual by contacting your local Allen Bradley distributor or Rockwell Automation sales office Publication 1746 UM002B EN P August 2004 Preface 3 Conventions Used In This The following conventions are used throughout this manual Manual e Bulleted lists like this one provide information not procedural steps e Numbered lists provide sequential steps or hierarchical information e Italic type is used for emphasis e Text in this ont indicates words or phrases you should type Your Questions or If you find a n Mas this Mice Sree a us If e e any suggestions for how this manual could be made more useful to Comments on the Manual you please contact us at the address below Rockwell Automation Automation Control and Information Group Technical Communication Dept A602V P O Box 2086 Milwaukee WI 53201 2086 Publication 1746 UM002B EN P August 2004 4 Preface Publication 1746 UM002B EN P August 2004 Chapter 1 Multi Channel High Speed Counter Module Overview Module Overview This chapter contains the following e multi channel high speed counter module overview e operating class e hardware features The 1746 HSCE2 is an intelligent counter module with its own microprocessor and I O that is capable of reacting to high speed input signals without the interventio
68. ations tmm e Install the SLC500 system in a NEMA rated enclosure e Disconnect power to the SLC processor and the module before wiring e Make sure the system is properly grounded e Group this module and low voltage DC modules away from AC I O or high voltage DC modules e Shielded cable is required for high speed input signals A B and Z Use individually shielded twisted pair cable lengths up to 300 m 1000 ft Publication 1746 UM002B EN P August 2004 Installation and Wiring 3 5 e Shields should be grounded only at one end Ground the shield wire outside the module at the chassis mounting screw Connect the shield at the encoder end only if the housing is electronically isolated from the motor and ground Figure 3 3 Grounding the Shield Wire at the Chassis Mounting Screw Spade Connector N y p Mounting Screw ao Chassis Mounting Tab Star Washer e If you have a junction in the cable treat the shields as conductors at all junctions Do not ground them to the junction box e If your application requires only low frequency inputs you can use a filter to minimize high frequency noise e If the Z pulse is edge aligned with A or B pulses capture preset operation may be affected by 1 count A small capacitor 0 01 F across the Z inputs will dis align these inputs and should correct this condition See Z pulse Preset Operation on page 2 8 Considerations for Reducing Noise In high noise environments the 1746
69. blication 1746 UMO002B EN P August 2004 Application Examples 6 11 addresses e g 1 1 0 have been replaced with block transfer data file addresses e g N12 0 TIP The only changes necessary to permit a different 1746 HSCE2 configuration are to the data files N10 and N11 Ladder File 8 HSCE2 Prior to use the programmer sets N11 2 to the total number of data blocks which will be entered into file N10 not including the Counter Control Block adds one rung for each configuration block including the Counter Control Block and initializes the data blocks in file N10 Ten integer data blocks are used instead of eight to simplify the display in data windows The first pass of the program initializes the following values The first pass of the program initializes the following values 1 The HSCE2 initialization done bit B3 0 is cleared 2 The HSCE2 error bit B3 1 is cleared FIRST SCAN OF LADDER OR SFC STEP HSCE2 INIT DONE 1 B3 0 0000 JE CU 15 0 HSCE2 ERROR B3 0 C 1 1ST BTR DONE B3 0 RS 3 DATA_BLOCK_POINTER MOV Move Source Dest 28TW DATA FLL Fill File Source 0 Dest N12 10 Length 8 LAST_DATA_BLOCK MUL Multiply Source A Source B Dest Publication 1746 UM002B EN P August 2004 6 12 Application Examples Ladder File 8 Continued Continuously re trigger 8 word block transfers to the remote HSCE2 BT20 1
70. c3 jv alolololololol lolololol st c3 jv Output Enable Mask Output ON OR Mas Enable Ranges RESERVED Must Equal Zero Publication 1746 UM002B EN P August 2004 4 24 Configuration and Programming Publication 1746 UMO002B EN P August 2004 Transmit Bit The transmit bit is not used A programming cycle is not needed to program these bits The block is acted upon for every program scan that bit 07 of word 0 is set Therefore a transmit bit is not used TIP If an invalid condition exists the PERR and ACK bits are set and all data in the block is considered invalid Programming Block Identification Bit Word 0 Bit 07 This bit identifies the type of block Control Words Words 1 to 4 Each counter has its own control word Table 4 10 Control Word Assignments Control Words Counter Number Word 1 Counter 1 Word 2 Counter 2 Word 3 Counter 3 Word 4 Counter 4 In the following programming bits n equals the counter number ENn Enable Counter n Bit Words 1 to 4 Bit 00 On power up or when the EN n bit is reset the counter is in a frozen state The counter is free to run when the EN n bit is set All of the counters must be disabled before transmitting a Module Setup programming block The affected counters must be disabled before transmitting a Counter Configuration programming block The affected Configuration and Programming 4 25 counter must also be disabled before s
71. ched 2 The HSCE2 error bit B3 1 is cleared 3 The Counter Configuration Block is cleared Note The init HSCE2 routine ladder file 9 is bypassed during the first pass to ensure the FIRST PASS S 1 MOV 0000 HH Move 15 Source 0 0 lt Dest B3 0 000000001 1000001 lt HSCE2_CFG_BLK FLL Fill File Source 0 Dest 0 1 0 Length 8 DATA_BLOCK_OFFSET MOV Move Source Dest MAX_BLOCK_ADDR MUL Multiply Source A Source B While the HSCE2 is not initialized and the HSCE2 has not errored call the HSCE2 initialization routine FRST PASS HSCE2 INIT DONE HSCE2 ERROR S1 B3 0 B3 0 JSR 0001 Jump To Subroutine 15 0 1 SBR File Number U 9 This rung copies the count value to the preset value demonstrating how to retain counts The rung assumes that the counter control block last configuration block is still in the output image HSCE2 INIT DONE Copy File B3 0 Source 1 1 2 mee A Dest N10 25 Length 2 0003 Publication 1746 UM002B EN P August 2004 Programming Blocks Module Setup Counter Configuration Min Max Count Value Counter 1 Min Max Count Value Counter 2 Min Max Rate Value Program Program Program Program Program Program Program Program Program Program Program Program Ranges Ranges Ranges Ranges Ranges Ranges Ranges Ranges Ranges Ranges Ranges Ranges Counter Control Offset 10 0 10 10 10 20 10 30 10
72. configured as pulse internal direction In mode 3 all counters have the pulse internal direction configuration See the Summary of Available Counter Configurations on page 2 8 Input frequency is determined by the input configuration as shown in the table below Input Configuration Input Frequency X4 Quadrature Encoder 250 kHz X2 Quadrature Encoder 500 kHz All Other Configurations 1 MHz IMPORTANT The minimum high and low times for the pulse train are 475 ns Therefore the input pulse train must fall between a 47 5 to 52 5 percent duty cycle at 1 MHz Publication 1746 UM002B EN P August 2004 2 6 Module Operation Gate Preset Modes store continue counting Publication 1746 UMO002B EN P August 2004 A counter s gate preset mode determines what if any gating is applied to the counter and what if any conditions will preset the counter to the preset value The Z inputs are the only inputs used for gating or presetting The six gate preset modes are described below No Preset The counter is not preset under any conditions The Z inputs are not used Soft Preset Only The counter is preset when the matching preset bit in the SLC 500 output image table experiences a positive transition but not in response to the Z input TIP The soft preset bit operates in all the gate preset modes except No Preset Store Continue The count value is captured when the module detects an inactive to acti
73. de Programming Bit Settings for Counters 1 and 2 Bit 06 Bit 05 Bit 04 Gate Preset Mode 0 0 0 No Preset 0 0 1 Soft Preset Only 0 1 0 RESERVED 0 1 1 RESERVED 1 0 0 Store Continue Soft Preset 1 0 Store Hold Resume Soft Preset 1 1 0 Store Preset Hold Resume Soft Preset 1 1 1 Store Preset Start Soft Preset TIP All configurations and modes are not available to all counters See the Summary of Available Counter Configurations on page 2 8 Figure 4 6 shows the format of the Minimum Maximum Count Value block This programming block programs the minimum and maximum counter value and preset value parameters of the selected counter As long as the min max counter values are not changed from their currently programmed values the counter can be running when this block is sent to the module If the minimum maximum values are changed the counter must be stopped when this block is sent or a programming error is generated The preset values can be changed with the counter running Publication 1746 UM002B EN P August 2004 4 14 Configuration and Programming Publication 1746 UMO002B EN P August 2004 Figure 4 6 Minimum Maximum Count Value Block 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Word 0 m H HEU AS a z Word 1 Upper 4 digits Minimum Count Value Word 2 Lower 3 digits Minimum Count Value Word 3 Upper 4 digits Maximum Count
74. de bit Set the transmit bit Once the steps above are complete you can reference the input image words to reflect the block s configuration NOTE Only the first eight words in the input image have meaning in Class 4 Chapter 6 Application Examples This chapter contains the following application examples e Example 1 uses the 1746 HSCE2 in Class 1 mode 3 to count four single ended high speed pulse train inputs using direct addressing only SLC 5 01 or SLC 5 027 e Example 2 tracks counts and speeds from two quadrature encoders with indirect addressing SLC 5 03 and above The module is used in Class 4 mode 1 e Example 3 uses the 1746 HSCE2 in Class 1 mode 3 to count two single ended high speed inputs with indexed addressing and the multi channel high speed counter in a remote I O chassis PLC 5 scanner e Example 4 illustrates the use of soft presets expanding on Example 2 e Example 5 changes presets dynamically using the min max count block and working from the Example 2 program e Example 6 shows how you can use the Min max Count block preset value to simulate retentive counters by modifying the Example 2 program In these examples if a programming error occurs PERR 1 the error bit B3 0 1 is set and N11 0 points to the configuration block that was last sent to the module TIP Any parameters which are defaults see Programming Block Default Values on page 4 28 need not be program
75. der This appendix describes the wiring procedures for connecting a differential encoder to the 1746 HSCE2 module For proper module operation wire the encoder so that the Z input signal is high true at the same time the A and B input signals are low false If this condition is not met inconsistent homing may occur If you are using an Allen Bradley Bulletin 845H differential encoder this condition is met by following the wiring diagrams in the manual The following five steps describe how to connect a differential encoder to the module 1 Obtain the encoder output timing diagram from the encoder data sheets The timing diagram for the 845H encoder is shown below for example purposes only Figure B 1 845H Encoder Timing Diagram 1 Cycle 90 22 lt Logic 1 Channel A Channel A Logic 2 Channel s T L T L T Channel A pc GUS 1 Index Channel Z 2 Channel Z Counter clockwise Rotation Shown 2 Look at the Z input signal and its complement Z signal on the timing diagram Whichever signal is low for most of the encoder revolution and pulses high for the marker interval should be wired into the Z terminal The remaining signal should be wired into the ZC terminal 3 Look at the B input signal and its complement B signal Whichever signal is low for at least part of the marker interval should be wired to the B terminal If both signals meet this condition either signal may be wired to the B ter
76. dge bit N12 0 15 reset the module handshaking bit N12 10 15 and check HSCE2 programming error bit N12 0 13 If no error bits are ON increment the block counter to permit the next block move to start HSCE2_TRNSMIT HSCE2_ACK HSCE2_TRNSMIT N12 10 N12 0 N12 10 J JE Qo 15 15 15 DATA BLOCK POINTER ADD ME Masked Equal Source Add Source A N11 0 Mask Source B Compare Dest When the last block is completed block data offset max block offset copy the Counter Control Block to the HSCE2 Note The Counter Control Block does not require a 0 1 positive transition of the transmit bit to operate DATA_BLOCK_POINTER HSCE2 TRNSMIT HSCE2 ACK 28TW DATA EQU 4 N12 10 N12 0 O Equal Copy File Source A N11 0 Source N10 N11 0 140 lt Dest N12 10 Source B N11 1 Length 8 140 lt HSCE2 INIT DONE B3 0 SY 0 If BTR returns a programming error bit set HSCE2 error bit B3 3 HSCE2_ACK HSCE2_PERR HSCE2 ERROR N12 0 N12 0 B3 0 E L gt _ 15 13 1 HSCE2_FAULT N12 0 14 CEND gt Publication 1746 UM002B EN P August 2004 6 14 Application Examples Data Table for N10 File hexidecimal Programming Blocks Offset 0 1 2 3 4 5 6 1 8 9 Module Setup N10 0 1 103 8 0 0 0 0 0 0 0 Counter Configuration N10 10 F02 6 0 6 0 0 0 0 0 0 Min Max Count Value Counter 1 N10 20 4 0 0 0 190 0 0 0 0 0 Min Max Count Value Counter 2 N10 30 104
77. e 1746 HSCE2 module is located in slot 3 The rate value in floating point rate value format is located in input data file words 4 and 5 1 3 4 and 1 3 5 To view the rate value for counter 1 use the copy instruction as shown below COP Copy File Source 1 3 4 Dest F8 1 Length 1 The source is the input data file and the destination is the floating point file The length is 1 the number of elements of the destination file in the COP instruction Writing the Data In the following example the floating point value is copied into integer words 1 and 2 of the Minimum Maximum Rate Value programming block N10 0 7 The 1746 HSCE2 module is located in slot 3 COP Copy File Source F8 1 Dest N10 1 Length 2 The source is the floating point file and the destination is an integer data file The length is 2 the number of elements being copied into the destination file using the copy instruction Converting from Two Word Integer to Floating Point Format You can use RSLogix500 programming software to convert the values from integer to floating point notation using the compute instruction as shown In this example the 1746 HSCE2 module is located in slot 3 the upper 4 digits of the rate value are stored in the input data file word 4 1 3 4 and the lower 3 digits of the rate value are stored in input data file word 5 1 3 5 The compute instruction is as follows CPF Compute Dest F8 1 Expression 1 3 4
78. e Block 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Word 0 co EMEN E mE M 6 ce m 0 Word 1 La en Minimum Rate Value in integer or floating point notation Word 2 Word 3 e T Maximum Rate Value in integer or floating point notation Word 4 Word 5 7 RESERVED Must equal zero Programming Block Identification Bit Word 0 Bit 03 This bit identifies the type of block TRMT Transmit Bit Word 0 Bit 15 A 0 to 1 transition starts a programming cycle DEBUG Debug Mode Selection Bit Word 0 bit 12 When this bit is set the debug mode is activated Debug mode returns the input data file showing current settings in the Min Max Rate Value block For details see Debug Mode Operation on page 5 7 Publication 1746 UM002B EN P August 2004 4 18 Configuration and Programming Publication 1746 UMO002B EN P August 2004 CNTR No Counter Number Bits Word 1 Bits 08 and 09 These two bits select the counter to which this programming block is applied Table 4 8 Counter Number Bit Settings Bit09 Bit 08 Counter Number 0 0 Counter 1 0 1 Counter 2 1 0 Counter 3 1 1 Counter 4 Minimum Maximum Rate Value Words Words 1 to 4 The valid range of this parameter is dependent on the operating class of the module Class 1 Rate Value Hz Class 4 Rate Value Hz Minimum 32 767 to 32 766 Minimum 1 000 000 to 999 999
79. e hold resume 2 7 store preset hold resume 2 7 store preset start 2 7 grounding 3 5 H hardware features 1 5 humidity A 1 ID code 1 4 Input Configuration Pulse External Direction 2 2 input configuration programming bit settings 4 12 summary 2 8 Input Configurations Pulse External Direction 2 2 input configurations pulse external direction 2 2 pulse internal direction 2 3 Publication 1746 UM002B EN P August 2004 up and down pulses 2 3 X1 quadrature encoder 2 4 X2 quadrature encoder 2 4 X4 quadrature encoder 2 4 input filter programming bit settings 4 13 input frequency 2 5 X2 quadrature encoder 2 5 X4 quadrature encoder 2 5 input voltage 3 2 installing the module 3 3 integer format 4 3 converting from 4 4 converting to 4 5 J jumpers 1 6 settings 3 2 L LEDs 1 5 5 1 linear counter 4 12 4 16 linearcounter 2 9 minimum maximum count value block 4 13 C 2 counter number bits 4 15 debug mode selection bit 4 14 error conditions 5 3 minimum maximum count value words 4 15 transmit bit 4 14 minimum maximum count values data format 4 3 minimum maximum rate value block 4 16 C 2 counter number bits 4 18 debug mode selection bit 4 17 error conditions 5 4 minimum maximum rate value words 4 18 transmit bit 4 17 minimum maximum rate values data format 4 19 module ID code 1 4 module installation 3 3 module programming blocks See programming blocks module removal 3 4 module setup block 4 6 C 1 debug mode
80. e value must be adjusted by adding one to it The lower LSW is then calculated by adding MSW multiplied by 1000 to the original value FLOAT TO TWO WORD INT VALUE TWO WORD INT 1 MSW TWO WORD INT 1 MSW LES LES ADD 0004 Less Than A B Less Than A B Add Source A F8 4 Source A N7 34 Source A 0 0 lt 0 lt 0 lt Source B 0 0 Source B F8 3 Source B 0 0 lt 0 0 lt 1 0 TWO WORD INT 1 LSW CPT Compute Dest 0 Expression F8 4 N7 34 Publication 1746 UM002B EN P August 2004 4 6 Configuration and Programming Module Setup Block Publication 1746 UMO002B EN P August 2004 Figure 4 1 shows the format of the Module Setup block This block sets the module s basic configuration and range allocation to the counters Counters cannot be running when this block is sent to the module or a programming error results Sending this block to the module sets all other module parameters to their default values See Programming Block Default Values on page 4 28 Figure 4 1 Module Setup Block Format 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Word 0 E c5 MUSEI za ER 609 09 HE RR 504 6059 EDDIE 1 ES ca Word 1 c la l lt Op aooo 0 RIERA Oooo O Mode Word 2 olololo AA Counter 1 l Range Allocation Word 3 aa AA Counter 2 l Range Allocation Word 4 Counter 3 OOo ED fecal de M e d Range Allocation Words 5 7 RESERVED Must equal 0 Progr
81. ending new minimum maximum count values TIP Disabling a counter does not cause an output with the counter to turn off As long as the count value is within the programming range the output remains active TIP Enabling a counter that is not present causes a programming error SPn Soft Preset Only n Bit Words 1 to 4 Bit 01 When the counter has its gate preset mode set to any mode except No Preset the counter is set to its preset value when the corresponding bit makes a 0 to 1 transition Setting this bit in No Preset mode causes a programming error TIP Soft preset does not work when the counter s P n bit is changed from 1 to 0 to 1 at the same time that the SP n bit is changed from 1 to 0 to 1 For example when word 1 goes from 8003H to 0000H and back to 8003H counter 1 is not preset IDr Internal Direction n Bit Words 1 to 4 Bit 02 When the counter has its input configuration set to Pulse Internal Direction the state of this bit determines the direction in which the counter counts When this bit is reset the counter increments When this bit is set the counter decrements Setting this bit in other than the Pulse Internal Direction mode causes a programming error Publication 1746 UM002B EN P August 2004 4 26 Configuration and Programming Publication 1746 UMO002B EN P August 2004 C R n Count or Rate Value Bit Words 1 to 4 Bit 08 These bits are only used when the module is configured for Class
82. eration Input Configurations Input configurations determine how the A and B inputs cause the counter to increment or decrement The six available configurations are e Pulse External Direction e Pulse Internal Direction e Up and Down Pulses e X1 Quadrature Encoder e X2 Quadrature Encoder e X4 Quadrature Encoder See the Summary of Available Counter Configurations on page 2 8 for the input configurations available for the counters based on operating mode Pulse External Direction With this configuration the B input controls the direction of the counter as shown below If the B input is low 0 the counter increments on the rising edges of input A If the input B is high 1 the counter decrements on the rising edges of input A Figure 2 2 Pulse External Direction Configuration 4 Count Pulse o Input A Encoder or Sensor Direction Control o Input B O Input Z Sensor or Switch compuse High Decrement Low Increment Count 1 2 3 2 1 0 1 2 Publication 1746 UM002B EN P August 2004 Module Operation 2 3 Pulse Internal Direction When the Pulse Internal Direction configuration is selected a bit written from the backplane determines the direction of the counter The counter increments on the rising edge of the input if the bit is low 0 and decrements on the rising edge of the input if the bit is high 1 Up and Down Pu
83. et copy Counter Configuration Block to the HSCE2 and set transmit bit 0 e 0 15 DATA_BLOCK_PTR HSCE2_XMIT HSCE2_ACK EQU O 1 I COP Equal J E 2t Copy File Source A N11 0 15 15 Source N10 10 140 lt 1746 HSCE2 1746 HSCE2 Dest 0 1 0 Source B 10 Length 8 10 lt HSCE2_XMIT O 1 15 When the previous block is completed transmit and acknowledge bit are reset copy Min Max Count 1746 HSCE2 Value Block for counter 1 to the HSCE2 and set transmit bit 0 e 0 15 DATA_BLOCK_PTR HSCE2_XMIT HSCE2_ACK EQU ENS O 1 I1 COP Equal JE JE Copy File Source A 15 15 Source N10 20 1746 HSCE2 1746 HSCE2 Dest 0 1 0 Source B Length 8 HSCE2_XMIT O 1 15 y f 1746 HSCE2 When the previous block is completed transmit and acknowledge bit are reset copy Min Max Count Value Block for counter 2 to the HSCE2 and set transmit bit 0 e 0 15 DATA_BLOCK_PTR HSCE2_XMIT HSCE2_ACK EQU O 1 I COP Equal Copy File Source A N11 0 15 15 Source N10 30 140 lt 1746 HSCE2 1746 HSCE2 Dest 0 1 0 Source B 30 Length 8 30 lt HSCE2_XMIT O 1 CL 15 1746 HSCE2 Publication 1746 UM002B EN P August 2004 6 4 Application Examples Ladder File 9 Continued When the previous block is completed transmit and acknowledge bit are reset copy Min Max Count Value Block for counter 3 to the HSCE2 and set transmit bit 0 e 0 15 DATA BLOCK PTR HSCE2_XMIT HSCE2_ACK EQU O 1 1 1 COP 0004 Equal lt t Copy File Source A N11 0 15 15
84. et while not in the internal direction mode e Acounter that is not valid in the selected mode has its enable counter bit set Application Errors The module can encounter the following application errors Linear Counter Overflow Underflow When the maximum count would be exceeded the counter overflow bit in the counter status byte is set When the count would become one lower than the minimum count the count underflow bit in the counter status byte is set When the module is in overflow condition the programmed maximum count value is reported and ranges that include the value will still be acted upon Likewise in underflow condition the minimum count value is reported and ranges including it are affected Rate Overflow Underflow The rate overflow bit is set when the rate is more than the maximum rate value Start Up Operation Troubleshooting and Debug Mode 5 5 The rate underflow bit is set when the rate value is less than the minimum rate value When the module is in overflow condition the programmed maximum rate value is reported and ranges that include the value will still be acted upon Likewise in underflow condition the minimum rate value is reported and ranges including it are affected Counter Value Does Not Change Check the LEDs associated with the Channel A and B inputs which have pulses coming in The A and B LEDs should flash whenever pulses are being received by the 1746 HSCE2 module If
85. ete the return process Outside United Please contact your local Rockwell Automation representative for States return procedure Power Control and Information Solutions Headquarters Americas Rockwell Automation 1201 South Second Street Milwaukee WI 53204 2496 USA Tel 1 414 382 2000 Fax 1 414 382 4444 Europe Middle East Africa Rockwell Automation Vorstlaan Boulevard du Souverain 36 1170 Brussels Belgium Tel 32 2 663 0600 Fax 32 2 663 0640 Asia Pacific Rockwell Automation Level 14 Core F Cyberport 3 100 Cyberport Road Hong Kong Tel 852 2887 4788 Fax 852 2508 1846 Publication 1746 UM002B EN P August 2004 Supersedes Publication 1746 UM002A US P April 2000 Copyright 2004 Rockwell Automation Inc All rights reserved Printed in the U S A
86. f the input is floating or has no voltage Q What does it mean when an output indicator is on Since the output indicator is tied to the logic side of the module it means that the module has commanded the output on It does not necessarily mean that the output is on The indicator illuminates even when no connection is made to the outputs or to the output supply For an output to actually turn on the output power supply must be connected Q What are the delay times for turning the outputs on and off The outputs turn on in lt 10 ys and turn off in lt 100 us However overall throughput is between 300 us and 1 5 ms Throughput is the delay time between the module receiving a pulse and the updating of its real outputs and the SLC backplane Publication 1746 UM002B EN P August 2004 D 2 Frequently Asked Questions Publication 1746 UM002B EN P August 2004 Can connect all of my outputs to the same output device Any or all of the 4 module outputs can go to the same output device as long as the output commons and Vcc are the same and the total output current is less than 1 5 A Can connect all of my inputs to the same input device You can if the device supplies enough current to drive multiple inputs How does the module make rate calculations See Rate Value on page 2 10 How do know what length to make my block transfer read write BTR BTW file The BTR BTW blocks should always consist of 8 input output
87. gram Program Ranges Ranges Ranges Ranges Ranges Ranges Ranges Ranges Ranges Ranges Ranges Ranges Counter Control Offset 10 0 10 10 10 20 10 30 10 40 10 50 10 60 10 70 10 80 10 90 120 130 140 150 160 170 Za E A A A EA A E A A ZA 2222235 2C i X Publication 1746 UM002B EN P August 2004 Data Table for N10 File hexidecimal 0 1 302 o O gt ER er er hh HH gt gt gt gt gt gt N gt gt gt gt gt OOO OOOOoOOoOoosoOo co o Data Table for N11 File decimal Offset N11 0 8001 0 170 PUGO GOGODOGO N MEC mo pT 170 N32 C20 C CO c ER CcOcccccccc 17 3 OOOOCO QU 3E7 3E7 3E7 3E7 3E7 3E7 3E7 3E7 31F 257 18F C7 FFOD oom o co A 00 A N FFF D DO ee ee OG ee eee E O O ee ee ee eee ee D a en ee Oe ee ee ee eee Application Examples 6 23 Example 6 Retentive The 1746 HSCE2 configuration and count values are not retentive If Counters power is cycled to the chassis the module must be re initialized and the count value re entered preset if desired To simulate a retentive counter the 1746 HSCE2 count values can be read by the processor and stored in the Min max Count Value Block preset value When the ladder logic re initialized the module after power up the last read count values can be loaded using the Min max Count Value Block preset value and auto preset bit The following
88. gramming error bit is set Program Ranges Block Figure 4 8 shows the format of the Program Ranges programming block This block programs the following parameters e Associated Counter e Range Type e Range Number e Range Start Point e Range End Point e Output State All counters can be running when this block is sent to the module Publication 1746 UM002B EN P August 2004 4 20 Configuration and Programming Publication 1746 UMO002B EN P August 2004 Figure 4 8 Program Ranges Block 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Word 0 c9 d A 12 ENS CORRERE E ES ec 0 Word 1 Range Number Word 2 Range Start Value Word 3 Word 4 Range Stop Value Word 5 Word 6 Output State 0 0 0 0 0 0 0 0 Virtual Real Word 7 RESERVED Must equal zero Programming Block Identification Bit Word 0 Bit 04 This bit identifies the type of block TRMT Transmit Bit Word 0 Bit 15 A 0 to 1 transition starts a programming cycle DEBUG Debug Mode Selection Bit Word 0 bit 12 When this bit is set the debug mode is activated Debug mode returns the input data file showing current settings in the Program Ranges block For details see Debug Mode Operation on page 5 7 Configuration and Programming 4 21 CNTR No Counter Number Bits Word 0 Bits 08 and 09 These two bits select the counter to which this progr
89. gure 3 6 shows the different encoder output waveforms If your encoder matches these waveforms the encoder signals can be directly connected to the associated screw terminals on the module For example the A lead from the encoder is connected to the module s A screw If your encoder does not match these waveforms some wiring modifications may be necessary See Appendix B for a description of these modifications Figure 3 6 Differential Encoder Output Waveforms i Lr e IE E EAS Lo gt dea ii AA PR A A 2 A z Z Installation and Wiring 3 9 Single Ended Encoder Wiring Open Collector Figure 3 7 Single Ended Encoder Wiring Cable vs oc 5 Power GND COM A Supply g A A19 Cj no va A y7 B B1 Allen Bradley A 845H Series z zi AAV single ended zo ANN A y encoder Shield 4 777 shield housing Earth Connect only if housing is electronically isolated from the motor and ground Module Inputs 1 Refer to your encoder manual for proper cable type The type of cable used should be twisted pair individually shielded cable with a maximum length of 300m 1000 ft 2 Calculate the value of the pull up resistor R as shown below For 5V dc jumper position A Wec Vmin Imin For 24V dc jumper position R Con 1 Ka Imin where R pull up resistor value Vcc power supply voltage Vmin 4 2 V de Imin 6 3 mA Power Supply Voltage
90. gust 2004 2 12 Module Operation Range Control Range 4 Stop Value on off The module can be programmed to use either counter or rate ranges to determine whether an output is active Up to 16 dynamically configurable ranges are available The ranges programmed using range start and range stop values can overlap When the count is within more than one range the output patterns of those ranges are combined logically ORed to determine the actual status of the output A mixture of count ranges and rate ranges may be used Count Range In a count range the outputs are active if the count value is within the user defined range The valid count range is dependent upon the operating class In Class 1 the valid range is 32 767 to 32 767 In Class 4 the valid range is 8 388 607 to 8 388 607 The examples in Figure 2 7 and Figure 2 8 use Class 1 operation Figure 2 7 Count Range with Linear Counter 32 767 E AEA gt Range 4 Start Value Range 1 Range 2 Range 3 Output 3 d Publication 1746 UM002B EN P August 2004 Range Start Stop Outputs Outputs Value Value Affected 116 5 4 3 2 1 0 1 7000 5000 0 0 0 0 0 0 0 1 0 2 1000 4500 0 0 0 0 0 0 11 0 1 3 4000 3000 0 0 0 0 0 11 01 0 2 4 9000 9000 0 0 0 0 1 0 0 1 0 and 3 1 Bits O through 3 are real outputs Bits 4 through 7 are virtual o
91. he previous block is completed transmit and acknowledge bit are reset copy Programming Ranges Block 4 for counter 1 to the HSCE2 and set transmit bit 0 e 0 15 DATA BLOCK PTR HSCE2_XMIT HSCE2_ACK EQU O 1 I COP 0008 Equal lt lt Copy File Source A 15 15 Source N10 80 Dest 0 1 0 1746 HSCE2 1746 HSCE2 Length 8 Source B HSCE2_XMIT O 1 L 15 When the previous block is completed transmit and acknowledge bit are reset copy Programming IAE Ranges Block 5 for counter 1 to the HSCE2 and set transmit bit 0 e 0 15 DATA BLOCK PTR HSCE2_XMIT HSCE2_ACK EQU O 1 I COP 0009 Equal lt lt Copy File Source A N11 0 15 15 Source N10 90 Dest 0 1 0 140 lt 1746 HSCE2 1746 HSCE2 Source B 90 90 lt Length 8 HSCE2_XMIT O 1 L 15 1746 HSCE2 When the previous block is completed transmit and acknowledge bit are reset copy Programming Ranges Block 6 for counter 1 to the HSCE2 and set transmit bit 0 e 0 15 DATA BLOCK PTR EQU 0010 Equal Source B Source A N11 0 140 100 100 HSCE2 XMIT O1 15 1746 HSCE2 HSCE2 ACK I1 15 1746 HSCE2 COP Copy File Source N10 100 Dest 0 1 0 Length 8 HSCE2_XMIT O 1 L 15 1746 HSCE2 When the previous block is completed transmit and acknowledge bit are reset copy Programming Ranges Block 7 for counter 1 to the HSCE2 and set transmit bit 0 e 0 15 DATA_BLOCK_PTR EQU 0011 Equal Source A N11 0 Source B 14
92. ion 1746 UM002B EN P August 2004 0000 0001 0002 0003 Application Examples 6 21 Ladder File 14 Preset Change Subroutine Copy the new preset value N7 0 and N7 1 into counter 1 s min max count block N10 25 and N10 26 Copy this block into the 1746 HSCE2 output image and set the 1746 HSCE2 transmit bit 0 1 0 15 HSCE2 XMIT HSCE2 ACK PRESET ENABLE 0 1 I1 B3 0 Tt Tt J E 15 15 5 OTHER OTHER N10 25 h 2 HSCE2_CFG_BLK Copy Fi Source Dest Length HSCE2_XMIT 0 1 15 OTHER PRESET ENABLE B3 0 When the 1746 HSCE2 sets its acknowledge bit l e 0 15 reset the transmit bit 5 0 e 0 15 and check for a programming error HSCE2 XMIT HSCE2 ACK HSCE2 XMIT 0 1 I1 0 1 HSCE2 ERROR MEQ B3 0 Masked Equal L Source I1 0 1 265 Mask 2000h 8192 Compare 0 0 When the Min max Count Block transfer is completed reload the Counter Control Block to the 1746 HSCE2 to permit soft presets disabling counters etc HSCE2_XMIT HSCE2_ACK PRESET_CHANGE_LATCH 0 1 I1 HSCE2_CFG_BLK OP Copy File Source ZN10 N11 0 Dest 0 1 0 Length 8 END gt Publication 1746 UM002B EN P August 2004 6 22 Application Examples Programming Blocks Module Setup Counter Configuration Min Max Count Value Counter 1 Min Max Count Value Counter 2 Min Max Rate Value Program Program Program Program Program Program Program Program Program Program Pro
93. is not used in Class 1 Setting this bit while using Class 1 causes a programming error In Class 4 the module transmits the rate value in a two word integer format when this bit is reset 0 The module transmits the rate value in single precision floating point format when this bit is set 1 PRA Program Range Allocation Word 1 Bit 08 When this bit is set 1 the module programs the range allocation to the values in words 2 3 and 4 Publication 1746 UM002B EN P August 2004 4 8 Configuration and Programming Publication 1746 UMO002B EN P August 2004 Op Mode Operating Mode Word 1 Bits 01 and 00 These two bits program the module s operating mode The combinations are shown below Table 4 2 Operating Mode Programming Bit Settings Bit01 Bit00 Operating Mode 0 0 Reserved 0 1 Mode 1 1 0 Mode 2 1 1 Mode 3 1 Using the reserved setting causes a programming error Range Allocation Values Words 2 3 and 4 Bits 00 to 04 Sixteen ranges are available for programming output on off positions and rates These ranges are assigned to the counters using these range allocation parameters Each value is the number of ranges assigned to each counter The operating mode parameter is read before the range allocation values The module s operating mode determines which counters allocation values are read e In Mode 1 two counters are used Only the Counter 1 allocation value is read All
94. is specified in the two word integer data format as described in Integer Format on page 4 3 This value may be changed with the counter running if minimum and maximum values are equal to their previously programmed values Minimum Maximum Count Value Words Words 1 to 4 The valid range of the parameter is dependent upon the operating class Table 4 7 Minimum Maximum Count Values by Class Class 1 Count Value Class 4 Count Value Minimum 32 767 to 32 766 Minimum 8 388 607 to 8 388 606 Maximum Min Value 1 to 32 767 Maximum Min Value 1 to 8 388 607 The minimum maximum count value can be changed after the output ranges have been programmed However they cannot be changed while the counter is enabled When the minimum maximum values are changed they are checked against the ranges If any of the new values are outside the range boundaries the new values are not accepted and the programming error bit is set The preset value is Publication 1746 UM002B EN P August 2004 4 16 Configuration and Programming Minimum Maximum Rate Value Block Publication 1746 UMO002B EN P August 2004 always included with this block and its value must fall between the minimum maximum count values The data is in the two word integer format as described in Integer Format on page 4 3 Counter Type The meanings of the minimum and maximum counter values are dependent on the counter type Ring Counter A
95. lane Outputs Eight outputs are available four real dc sourcing and four virtual bits The virtual outputs are available to the processor only The real outputs are protected from overloads by a self resetting fuse The outputs can be controlled by any or all of the counters and or directly controlled by the user s program Up to 16 dynamically configurable ranges are available using rates or counts to control outputs The ranges programmed with range start and range stop values can overlap If the count or rate is within more than one range the output patterns of those ranges are combined logically ORed to determine the actual status of the output When an output is enabled by more than one counter and or with the user program its output state is determined by logically ORing the programmed setpoints of all those counters and the user program Operation Module operation is controlled by user programmed settings in the following six module programming blocks Module Setup Block e Counter Configuration Block e Minimum Maximum Count Value Block e Minimum Maximum Rate Value Block Program Ranges Block e Counter Control Block Module Overview 1 3 Most programming parameters except those in the Module Setup and Counter Configuration blocks are dynamic and can be changed without halting counter operation The table below lists the static and dynamic parameters by programming block Programming Block Parameter Type
96. licable acts Publication 1746 UM002B EN P August 2004 A 2 Specifications Inputs A B and Z Outputs sourcing Publication 1746 UM002B EN P August 2004 Input Voltage 5V dc 24V dc Input Voltage Range 4JN dc to 12V dc 10V dc to 30V dc On State Voltage min 4 2N 10V Off State Voltage max 0 8V 3V Maximum Off state Leakage Current 100 pA 100 pA Input Current max 8 mA 20 mA Input Current min 6 3 mA 6 3 mA Nominal Input Impedance 500 Q 1500 Q Min Pulse Width 475 ns 475 ns Min Phase Separation 200 ns 200 ns Max Input Frequency 1 MHz 1MHz Isolation from backplane 1000V 1000V Isolation from outputs 500V 500V Output Voltage Range 5 30V dc Max On State Output Current per channel 1 0 A at 40 C 1 0 A at 60 C Max On State Current per module 2 0 A at 40 C See the derating graph below 1 5 A at 60 C Max On State Voltage Drop 0 5V Max Off State Leakage Current 100 pA Isolation from backplane 1000V Isolation from inputs 500V ATTENTION A transient pulse occurs in transistor output when the external dc supply voltage is applied to the output common terminals for example via the master control relay This can occur regardless of the processor having power or not For most applications the energy of this pulse is not sufficient to energize the load Refer to SLC 500 Modular Hardware Style User Manual publication 1747
97. llocation ololololo o o o ololo Counters words g p Range Allocation RESERVED Must equal 0 Word5 0 0 00 RESERVED Must equal 0 Word6 0 0 0 0 RESERVED Must equal 0 Word7 0 0 0 0 1 0 for normal operation 1 for debug mode Figure C 2 Counter Configuration Block see pages 4 10 to 4 13 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Hex Format Al S emm 1 Counters MM S S o gt II EE Wort 012 Input 8 0 0 0 0 0 0 0 0 0 G P Mode S Word1 0 0 Counter 1 Config 0 Word 2 Input S 0 010 0 0 0 0 0 0 G P Mode S Word3 0 0 Counter 2 Config 5 0 Word 4 o ololololole Solo 0 0 0l 0 8 Counter 3 O 5 Word5 0 0 or 4 as Counter 4 Counter 3 indicated Word 6 Word 7 1 0 for normal operation 1 for debug mode Publication 1746 UM002B EN P August 2004 C 2 Module Programming Quick Reference Figure C 3 Minimum Maximum Count Value Block see pages 4 13 to 4 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Hex Format tu N E c LL zjojo a o NB ofolo o o 1 o o Wondo o 4 a o s Ll Upper 4 digits Minimum Count Value Word 1 Lower 3 digits Minimum Count Value Word 2 Upper 4 digits Maximum Count Value Word 3 Lower 3 digits Maximum Count Value Word 4 Upper 4 digits Preset Value Word 5 Lower 3 digits Preset Value Word 6 RESERVED Must equal zero Word7 0 01010 1
98. loloj jololo o Word 4 0 0 0 0 E OCA a oe s Nh ico Otel oO i e ed Word 5 0 0 0 0 0olo olo olololo jojlololoj ololo o Word 6 0 0 0 0 000 O 358 39 We 0 8 Oe de Oe 3 90 ea oe n cO Word 7 0 0 0 0 Mode 2 Example In the Module Setup block below four ranges are assigned to Counter 1 Four ranges are assigned to Counter 2 with the remaining 8 assigned to Counter 3 Figure 4 3 Module Setup in Mode 2 Showing Hex Format 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Hex 0 0 1 Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7 oO oO GO CO OF CO CO O O O O oj OF CO CO O oO oO CO CO OF CO CO O O O O joj OF CO CO O oO oO CO CO OF CO CO O O O O oj OF CO CO O oO oO CO CO CO CO CO O oO oO GO CO OF CO CO O O O oOo oj OF CO CO O oO oO CO CO OF CO CO O oO oO CO OF OF CO O ojl oO ojl ojojoj ojl O O O Oo oj OF CO CO O IMPORTANT The number of ranges for the last configured counter used must equal zero otherwise the module fills in the value and errors even if the value is correct Publication 1746 UM002B EN P August 2004 4 10 Configuration and Programming Mode 3 Example In the Module Setup block below four ranges are assigned to Counter 1 Eight ranges are assigned to Counter 2 Two ranges are assigned to Counter 3 The last two ranges are assigned to Counter 4 but the counter is
99. lses In this configuration the counter increments on the rising edge of pulses applied to input A and decrements on the rising edge of pulses applied to input B TIP When both inputs transition simultaneously or near simultaneously the net result is no change to the count value Therefore simultaneous or near simultaneous pulses are ignored and no change in the count value is reported Figure 2 3 Up and Down Pulse Configuration 1 LI C3 O Input A Increment Pulse i p 1 L A count u i Incrementing Encoder p o Input B i or Sensor o Input Z i ci TER i Decrement Pulse Module Decrementing Encoder or count down Sensor Increment Pulse Input A i l Decrement Pulse l i Input B i i Count 1 2 3 2 1 0 1 2 Publication 1746 UM002B EN P August 2004 2 4 Module Operation Publication 1746 UMO002B EN P August 2004 X1 Quadrature Encoder When a quadrature encoder is attached to inputs A and B the count direction is determined by the phase angle between inputs A and B If A leads B the counter increments If B leads A the counter decrements The counter changes value only on one edge of input A as shown in Figure 2 4 on page 2 5 TIP If B is low the count increments on the rising edge of input A and decrements on the falling edge of input A If B is high all transi
100. med For example if you want all the default values of Class 4 operation then you only need to configure the module as Class 4 and send a Counter Control block to enable the counters The data tables follow the ladder logic The N10 data table is in hex format to improve readability Publication 1746 UM002B EN P August 2004 6 2 Application Examples Example 1 Addressin Direct This example sets up the module to count the number of pulses from a high speed device and apply that information to your ladder g program The module is in Class 1 mode 3 with 4 counters available Ladder File 8 HSCE2 Prior to use the programmer sets N11 2 to the total number of data blocks which will be entered into file N10 not including the Counter Control Block adds one rung for each configuration block including the Counter Control Block and initializes the data blocks in file N10 Ten integer data blocks are used instead of eight to simplify the display in data windows Note The Counter Control Block rung differs from the other rungs because the Counter Control Block does not require hand shaking The first pass of the program initializes the following values 1 The HSCE2 initialization done bit B3 0 is unlatched 2 The HSCE2 error bit B3 1 is cleared 3 The Counter Configuration Data Block is cleared Note The init HSCE2 routine ladder file 9 is bypassed during the first pass to ensure the Configuration Data Block is reset prior
101. minal Wire the remaining signal to the BC terminal Publication 1746 UM002B EN P August 2004 B 2 Connecting a Differential Encoder 4 Look at the A input signal and its complement A signal Whichever signal is low for at least part of the marker interval should be wired to the A terminal If both signals meet this condition then either signal may be wired to the A terminal Wire the remaining signal to the AC terminal 5 Since the encoder may be mounted on either end of a motor shaft the encoder may spin clockwise or counter clockwise for a given shaft direction As a result the direction phasing of the encoder may be backwards If this is the case exchange the A wire with the AC wire Publication 1746 UM002B EN P August 2004 Appendix C Module Programming Quick Reference The module programming blocks are duplicated below for your reference A column has been added to show corresponding hex values Figure C 1 Module Setup Block see pages 4 6 to 4 10 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Hex Format 1 Ct z 0 02 0 0 0 0 0 0 0 0 0 0 0 1 Wordo 0 0 1 irs a 0 0 0 0 0 2 5 2 0 0 0 0 0 0 S Words jo 0 S olololololo o o ololo Sue tora lolo Range Allocation olololololo o o ololo Counter f wora lolo Range A
102. n of the SLC processor The module is compatible with the SLC 500 family and can be used in a remote chassis with the SLC Remote I O Adapter Module 1747 ASB Counters The module is able to count in either direction A maximum of four pulse counters are available or 2 quadrature counters Each counter can count to 8 388 607 as a ring or linear counter In addition to providing a count value the module provides a rate value up to 1 MHz dependent on the type of input The rate value is the input frequency Cin Hertz to the counter When the count value is increasing the rate value is positive When the count value is decreasing the rate value is negative Counters can also be preset to any value between the minimum and maximum values The conditions that preset the count value and generate capture values are configured by the gate preset modes The four counters can have different gate preset modes Publication 1746 UM002B EN P August 2004 1 2 Module Overview Publication 1746 UMO002B EN P August 2004 Inputs The module features six high speed differential inputs labeled A1 B1 Z1 A2 B2 and Z2 It supports quadrature encoders with ABZ inputs and or up to six discrete switches In addition x1 x2 and x4 counting configurations are provided to fully use the capabilities of high resolution quadrature encoders The inputs can be wired for single ended or differential use Inputs are opto isolated from the backp
103. nated check your program operation If the LED is not illuminated check the wiring to your output device Check the leakage current of your connected device Soft Preset Does Not Work Soft preset does not work when the counter s P n bit is changed from 1 to 0 to 1 at the same time that the SP n bit is changed from 1 to 0 to 1 For example when word 1 goes from 8003H to 0000H and back to 8003H counter 1 is not preset Application Programming Errors Affecting Initialization Typically ladder logic manipulates 1746 HSCE2 parameters twice First the ladder logic initializes the module at power up using a handshaking procedure shown in Application Examples 1 2 and 3 in Chapter 6 After initialization ladder logic can be used to control the 1746 HSCE2 dynamically For example the program can manipulate the module s counter preset values see Example 5 on page 6 18 or the program can soft preset a module counter The programmer must be very careful to ensure that ladder logic programs intended to manipulate module parameters after initialization do not affect the initialization process A typical programming mistake is to use OTE instructions to set 1746 HSCE2 output image bits intended for post initialization operations for example soft presets OTE instructions set or reset the bit depending on whether the rung conditions are true or false For example the following ladder rung sets the bit if the condition is true meaning bits
104. ng cycles are controlled by the transmit and acknowledge bits A programming cycle consists of six steps 1 Write the new data into the correct output image table words The lower byte of each configuration block indicates which block is being transferred See the programming block descriptions on pages 4 6 to 4 28 Each block that can be altered has a Transmit bit O e 0 15 Set the Transmit bit in the output image table The 1746 HSCE2 will not act on the new programming block until the Transmit bit is set Once the Transmit bit is set an Acknowledge bit T e 0 15 is received When the ladder logic detects that the Acknowledge bit is set it should check for errors Error bits are only valid when the Acknowledge bit is set The error bits are the PERR bit e 0 13 and the MFLT bit 1 e 0 14 If either bit is set the programming block is rejected The block pointer is not incremented and initialization fails If neither error bit is set the block pointer is incremented and the Transmit bit is reset allowing the module to transfer the next block Once the desired configurable blocks have been transferred to the module and the Maximum Block Address is recognized the Counter Control Block is transferred to the output image table to enable the counters Configuration and Programming 4 3 Data Format In Class 4 the counter accepts rate data in either integer or floating point data formats dependi
105. ng upon the setting of the rate value bit Both formats are explained below TIP Count values are always in integer format The format of rate values is selected in the Module Setup Block as either integer or floating point formats All other data is in integer format Integer Format In integer format two words may be needed to hold each data value because the values can exceed 32768 decimal when the module is in Class 4 operation The combined decimal value of both words is calculated as follows actual value value of first word x 1000 value of second word Both word values must have the same sign or a programming error results If the value is positive both words must be positive If the value is negative both words must be negative TIP A value of zero in either word may be paired with either sign in the other word The following example illustrates how numbers are represented in integer format Table 4 1 Integer Format Example First Word Second Word Data 12 345 12 345 12 345 12 345 12 0 12 000 12 0 12 000 Floating Point Format Floating point notation EEE 754 single precision used is difficult to read and use but may be simplified by using programming software to view and use the data in a floating point file Publication 1746 UM002B EN P August 2004 4 4 Configuration and Programming Publication 1746 UM002B EN P August 2004 Reading the Data In the following example th
106. nment Low Voltage Directive This product is tested to meet Council Directive 73 23 EEC Low Voltage by applying the safety requirements of EN 61131 2 Programmable Controllers Part 2 Equipment Requirements and Tests Publication 1746 UM002B EN P August 2004 3 2 Installation and Wiring Prevent Electrostatic Discharge Setting the Jumpers Publication 1746 UM002B EN P August 2004 For specific information required by EN61131 2 see the appropriate sections in this publication as well as the following Allen Bradley publications e Industrial Automation Wiring and Grounding Guidelines for Noise Immunity publication 1770 4 1 e Automation Systems Catalog publication B111 ATTENTION Static discharges may cause permanent damage to the module Follow these guidelines when you handle the module e Touch a grounded object to discharge static potential e Wear an approved wrist strap grounding device e Handle module by plastic case only Avoid contact between module circuits and any surface which can hold an electrostatic charge e If available use a static safe work station Six jumpers are located in a column on the side of the module Use the jumpers to select the input voltage for each of the inputs A1 B1 71 A2 B2 and Z2 The settings are shown in the figure on the following page Installing the Module Installation and Wiring 3 3 Figure 3 1 Jumper Settings JP1 A1 JP2 B1 JP3 Z1 J
107. oduction of the contents of this copyrighted publication in whole or part without written permission of Rockwell Automation is prohibited Throughout this publication notes may be used to make you aware of safety considerations The following annotations and their accompanying statements help you to identify a potential hazard avoid a potential hazard and recognize the consequences of a potential hazard Identifies information about practices or circumstances that can cause an explosion in a hazardous environment which may lead to personal injury or death property damage or economic loss ATTENTION Identifies information about practices or circumstances that can lead to personal injury or death property damage or economic loss IMPORTANT Identifies information that is critical for successful application and understanding of the product Allen Bradley and SLC are trademarks of Rockwell Automation Module Overview Module Operation Table of Contents Preface Who Should Use This Manuals 6 5 454 0 oh gue O4 des P 1 Purpose of This Manual iu veoxs ra AAA xS P 1 Related Documentation marras e ers P 2 Conventions Used In This Manual P 3 Your Questions or Comments on the Manual P 3 Chapter 1 Multi Channel High Speed Counter Module Overview 1 1 COUDIGES ea a e et ds 1 1 Inputs 5 iu o dd RIDE 1 2 OUPS qu XO ERA e ROS ESQ ea SE REE HESS 1 2 OPCTAVON us cer es
108. ogrammed with this block CType Counter Type Bit Words 1 and 3 Bit 00 Word 5 Bits 00 and 08 For each counter this bit defines whether the counter is a ring or linear counter Table 4 3 Counter Type Programming Bit Settings Bit Counter Type 0 Ring Counter 1 Linear Counter Input Config Input Configuration Bits Words 1 and 3 Bits 01 to 03 These bits define the input configuration for Counters 1 and 2 Counters 3 and 4 are always Pulse Internal Direction counters and do not require programming bits The table below shows the input configuration programming bit values Table 4 4 Input Configuration Programming Bit Settings Bit03 Bit02 Bit01 Input Configuration 0 0 0 RESERVED 0 0 1 Up Down Pulses 0 1 0 Pulse External Direction 0 1 1 Pulse Internal Direction 1 0 0 Quadrature X1 1 0 1 Quadrature X2 1 1 0 Quadrature X4 1 1 1 RESERVED Minimum Maximum Count Value Block Configuration and Programming 4 13 G P Mode Gate Preset Mode Bits Words 1 and 3 Bits 04 to 06 Word 5 Bits 09 and 01 Counters 3 and 4 have only two gate preset modes available Therefore they have only one G P mode bit When this single bit is equal to zero the No Preset mode is selected When the bit is set the Soft Preset mode is selected Three bits determine the Gate Preset Mode for Counters 1 and 2 The table below shows the G P Mode settings for counters 1 and 2 Table 4 5 Gate Preset Mo
109. ount Value E o Word 9 Lower 3 digits Counter 2 Count Value Word 10 Counter 2 Rate Value z Word 11 E Word 12 Upper 4 digits Counter 2 Capture Value cc Word 13 Lower 3 digits Counter 2 Capture Value Ss Word 14 Counter 4 Status Counter 3 Status S Word 15 Upper 4 digits Counter 3 Count Value i Word 16 Lower 3 digits Counter 3 Count Value 5 Word 17 Counter 3 Rate Value E Word 18 c TO o 5 e us E Word 19 Upper 4 digits Counter 4 Count Value S Word 20 Lower 3 digits Counter 4 Count Value 3 Word 21 Counter 4 Rate Value E Word 22 8 5 2 e 1 The format of the Rate Values is programmed with the Rate Value Format bit in the Module Setup programming block This bit specifies the rate value to be in integer or floating point format The default is integer format Count values are always transferred in integer format See Data Format on page 4 3 2 Data values transferred Regardless of operating mode the module will transfer up to 23 words Words that do not contain relevant data are set to 0000H Publication 1746 UMO002B EN P August 2004 Module Operation 2 17 Input Word Bit Values ACK Acknowledge Bit This bit makes a O to 1 transition to signal the receipt of programming data MFLT Module Fault Bit This bit is set only if the module does not power up correctly After a proper power up the MFLT bit remains reset PERR Programming Error Bit The state of this bit is valid onl
110. overload conditions When an output channel overload occurs as described above all channels turn off within milliseconds after the thermal cut out temperature has been reached While the overcurrent condition is present the module tries resetting the outputs at intervals of 500 ms If the fuse cools below the thermal cut out temperature all outputs auto reset and resume control of their external loads as directed by the module until the thermal cut out temperature is again reached Removing power from an overloaded output channel would also allow the fuse to cool below the thermal cut out temperature allowing auto reset to occur when power is restored The output channels then operate as directed by the module until the thermal cut out temperature is again reached To avoid auto reset of output channels under overload conditions monitor the fuse blown status bit FB1 in the module s status file and latch the outputs off when an overcurrent condition occurs An external mechanical fuse can also be used to open output circuits when they are overloaded Installation and Wiring 3 7 Input and Output Input and output wiring terminals are shown in the figure below Connections Each terminal accepts 14 AWG wire Tighten screws only tight enough to immobilize the wire The torque applied to the screw should not exceed 0 9 Nm 8 in lb Figure 3 4 Terminal Wiring Al 1 Release Screw A1 B1 B1 Z1 Z1 A
111. r ranges not belonging to the indicated counter are set the block is rejected and a programming error results e If the range number equals zero and words two through 7 are equal to zero all ranges associated with the counter are reset e Setting more than one range bit when the values for range start and range stop are different causes a programming error TIP Each of the 16 ranges has a unique bit For example the ranges allocated for Counter 2 begin sequentially after the ranges for Counter 1 Range Start Value Range Stop Value Words 2 to 5 When specifying a count range the range start and range stop values must be within the range of the minimum and maximum count values programmed in the Minimum Maximum Count Value programming block The rate range must be programmed using the same data format as the rate value If the rate value is specified in floating point format the rate range is also If the rate value is specified in integer format the rate range is programmed in integer format Count values are always in two word integer format as described in Integer Format on page 4 3 If the range start and range stop numbers are equal the range specified by the range number is erased from memory Output State Output State Byte Word 6 Bits 00 to 07 This byte defines the state of the outputs while the programmed range is active It is combined with other output state bytes and output masks to define the actual output
112. requency is below 60 Hz Therefore we recommend that the 1746 HSCE2 module not be used for rate monitoring or rate range control for frequencies below 60 Hz The invalid measurements apply only to rate values and do not affect the count value reported to the controller which are always correct Accuracy The accuracy of the rate value can be 0 005 typical For this resolution the rate measurement value must be transferred in single precision floating point format This format is only available when the module operates as Class 4 Fractional rates those between 1 and 0 or 1 and 0 are not reported The rate measurement value can also be transferred as an integer value The integer format is available in both Class 1 and Class 4 All eight outputs can be controlled by any or all of the counters or they can be controlled by the user program When controlled by a counter an output can be programmed to turn on or off based on the count value and or rate value of the counter The eight outputs are divided into four real outputs and four virtual outputs The outputs can be activated from the user program or from the module in response to specified input events The status of the real outputs is available to the user program The virtual outputs are available only to the user program They have no real output associated with them The real outputs are protected from overloads by a self resetting fuse Publication 1746 UM002B EN P Au
113. s a ring counter the counter counts between the minimum and maximum values When counting up if the maximum value is reached the counter rolls over to the minimum value When counting down if the minimum value is reached the counter rolls over to the maximum value Linear Counter As a linear counter the counter counts between the minimum and the maximum value If the maximum value would be exceeded when the counter is counting up the counter stops counting and an overflow bit is set in the status field of the counter If while counting down the counter reaches a value that would be less than the minimum value an underflow bit is set in the status field of the counter The number of pulses accumulated in an overflow underflow state are ignored The counter begins counting again when pulses are applied in the proper direction For example if you exceed the maximum by 1 000 counts you do not need to apply 1 000 counts in the opposite direction before the counter begins counting down The first pulse in the opposite direction decrements the counter If the linear counter is in an overflow underflow state the rate value continues to update Figure 4 7 shows the format of the Minimum Maximum Rate Value programming block This block programs the minimum and maximum rate values of the selected counter All counters can be running when this block is sent to the module Configuration and Programming 4 17 Figure 4 7 Min Max Rate Valu
114. selection bit 4 6 error conditions 5 3 interrupt enable bit 4 7 operating mode programming bits 4 8 program range allocation bit 4 7 range allocation values 4 8 rate value format bit 4 7 transmit bit 4 6 no preset 2 6 0 on state current derating A 3 operating class 1 4 4 1 class 1 1 4 class 4 1 4 operating mode counter allocation values 4 8 programming bit settings 4 8 summary 2 8 operating modes 2 1 input assignments 2 1 OTE instructions initialization errors 5 6 output control 2 11 output state 4 20 bytes 4 22 determining 4 27 overflow 5 4 counter overflow bit 2 19 linear counter 2 9 4 16 rate overflow bit 2 19 rate value 4 18 P phasing B 2 power up 5 1 program preset block C 3 preset value words 4 15 program ranges block 4 19 C 2 counter number bits 4 21 debug mode selection bit 4 20 error conditions 5 4 output state byte 4 22 range number bits 4 21 range start stop words 4 22 range type bit 4 21 transmit bit 4 20 Index 3 programming 4 1 programming cycle 4 2 programming block default values 4 28 4 31 programming blocks 4 1 4 27 counter configuration block 4 10 counter control block 4 23 error conditions 5 3 minimum maximum count value block 4 13 minimum maximum rate value block 4 16 module setup block 4 6 program ranges block 4 19 programming cycle 4 2 programming error 5 2 5 3 programming error bit 5 3 pulse train 2 5 pulse external direction 2 2 pulse internal direction 2 3 bits 4 25
115. sist you in using its products At http support rockwellautomation com you can find technical manuals a knowledge base of FAQs technical and application notes sample code and links to software service packs and a MySupport feature that you can customize to make the best use of these tools For an additional level of technical phone support for installation configuration and troubleshooting we offer TechConnect Support programs For more information contact your local distributor or Rockwell Automation representative or visit http support rockwellautomation com Installation Assistance If you experience a problem with a hardware module within the first 24 hours of installation please review the information that s contained in this manual You can also contact a special Customer Support number for initial help in getting your module up and running United States 1 440 646 3223 Monday Friday 8am 5pm EST Outside United Please contact your local Rockwell Automation representative for any States technical support issues New Product Satisfaction Return Rockwell Automation tests all of its products to ensure that they are fully operational when shipped from the manufacturing facility However if your product is not functioning and needs to be returned United States Contact your distributor You must provide a Customer Support case number see phone number above to obtain one to your distributor in order to compl
116. states See Determining Actual Counter Control Block Output State on page 4 27 for a description of how the bytes are combined Configuration and Programming 4 23 If the start value is less than the stop value the output state is applied when the count or rate is within the range specified by the two values For example see ranges 1 through 3 on page 2 13 If the start value is greater than the stop value the output state is applied when the count or rate is outside the range For example see range 4 on page 2 13 At least one of these bits must be set when programming a range or a programming error is generated Figure 4 9 shows the format of the Counter Control programming block This block allows you to change the state of the following counter controls for all four counters in one cycle e Enable Disable Counter e Soft Preset if enabled e Internal Direction if enabled e Output ON Mask e Output Enable Mask e Count or Rate Value Class 1 only e Enable Disable Range All counters can be running when this block is sent to the module Figure 4 9 Counter Control Block Format Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Ma Ma P1 AOS LON OOO c AAA AO OA OS i S c3 jv 22 olololoalolo EBS ololola lo S S c3 jv o ololololo ES olola lalo PREJE
117. tatus of the physical outputs e The run LED is on to indicate the module s running status Publication 1746 UM002B EN P August 2004 5 2 Start Up Operation Troubleshooting and Debug Mode Troubleshooting Publication 1746 UM002B EN P August 2004 Figure 5 1 LED Locations COUNTER Output Status 3 Running Status Input Status Fault Status Three types of module generated errors can occur e module diagnostic errors e module programming errors e application errors The Fault LED indicates a module diagnostic error Fault LED Problem Solid Red Module diagnostic error Cycle power If condition persists replace the module Refer to Module Diagnostic Errors below Hashing Red Module output fuse has been tripped The counter status bytes indicate application errors encountered by the module Module Diagnostic Errors A module diagnostic error is produced if the power up self test or run time watchdog test fails This is an indication of a potential hardware failure When it detects a diagnostic error the module halts all operations Outputs are reset to zero and a fault indication is sent to the SLC processor The module fault LED turns solid red In response to a diagnostic error cycle power If the condition persists replace the module Start Up Operation Troubleshooting and Debug Mode 5 3 Module Programming Errors
118. ter individually Bits 10 11 13 and 14 must be zero The values of words 1 through 7 are ignored by the module while in debug mode Figure 5 6 Required Bits for Min Max Rate Value Block 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 E co Wordd z 0 o g 0 0 NP BLOCK TYPE E a TIP If the counter number entered is not valid the debug mode returns a programming error In the Program Ranges Block To activate the debug mode in the Program Ranges block the transmit bit the debug bit the block type byte and the range number word word 1 bits O 15 are required for each range individually The counter number word 0 bits 08 and 09 must be zero or a programming error results The values of any other bits or words 2 through 7 are ignored by the module while in debug mode Figure 5 7 Required Bits for Program Ranges Block 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 E Oo Word0 z 0 0 8 0 0 0 0 BLOCK TYPE ca Range Number Word 1 TIP If more than one bit in word 1 is set 1 the module returns a programming error Publication 1746 UM002B EN P August 2004 5 10 Start Up Operation Troubleshooting and Debug Mode Publication 1746 UM002B EN P August 2004 Activating Debug Mode 1 2 3 Clear the output image table Set the required bits in the block that will be echoed back Set the debug mo
119. the A and B LEDs do not flash check the power to the input sensor and the wiring from the sensor to the module If the A and B LEDs flash make sure that the configuration of the module is complete and counters are enabled Counter Value Rate Value Goes in the Wrong Direction If single ended encoder inputs are used swap channels A and B to change the direction If differential encoder inputs are used swap A and AC wires If pulse and direction inputs are used check the direction and input type If using up and down pulses mode make sure inputs A and B have not been switched Output Does Not Turn On Make sure the SLC processor is in run mode Check the output s LED If the LED is illuminated check the power supply and its connections to the module Also check the connections to the output device If the LED is not illuminated make sure the SLC processor is in the run mode and that a module fault has not occurred Check the output status field of the input image to see if the module is trying to energize the output If not make sure that the enable ranges byte and the output OFF mask are set Check the fuse status bit Publication 1746 UM002B EN P August 2004 5 6 X Start Up Operation Troubleshooting and Debug Mode HSCE2 INIT DONE B3 0 0001 0 Publication 1746 UMO002B EN P August 2004 Output Does Not Turn Off Check the associated module LED for the output If the LED is illumi
120. tions on input A are ignored X2 Quadrature Encoder Like the X1 Quadrature Encoder the count direction is determined by the phase angle between inputs A and B If A leads B the counter increments If B leads A the counter decrements However the counter changes value on the r sing and falling edges of input A as shown in Figure 2 4 on page 2 5 X4 Quadrature Encoder Operation is similar to the X2 Quadrature Encoder configuration except the counter changes value on the rising and falling edges of inputs A and B as shown in Figure 2 4 Input Frequency B i i D X1 Count 1 1 2 3 4 5 6 5 4 3 2 1 0 X2 Count mE rre ere E MET a a ee ee a a A 1 2 3 4 5 6 7 8 9 10 11 12 71 10 9 8 7 6 5 473 2 1 0 X4 Count Module Operation 2 5 Figure 2 4 Quadrature Encoder Configurations 5 o Input A i B i cj o Input B f Quadrature Z o Input Z Encoder i 1 Forward Rotation Reverse Rotation t Litt Jeti IMPORTANT The input configuration is limited by the operating mode In mode 1 Counters 1 and 2 can be assigned any input configuration In mode 2 Counter 1 can be assigned any configuration but Counters 2 and 3 are
121. to transfer of the first configuration block 4 The transfer data block offset N11 0 is cleared i e the first data block starts at offset 0 in N10 file 5 Max data block address N11 0 is calculated as Total Data Blocks N11 2 x 10 words data block FIRST PASS HSCE2 INIT DONE SH B3 0 0000 HH U 15 0 HSCE2_ERROR B3 0 U 1 FLL Fill File Source 0 0001 Dest MOV Move Source Dest MAX_BLOCK_ADDR MUL Multiply Source A 10 10 lt Source B N11 2 14 If the HSCE2 initialization is not done and the HSCE2 has not errored call the HSCE2 Dest N11 1 s initialization routine 140 lt FIRST_PASS HSCE2_INIT_DONE HSCE2_ERROR S 1 B3 0 B3 0 JSR if Vt Vt Jump To Subroutine 15 0 1 SBR File Number U 9 RET Return Publication 1746 UM002B EN P August 2004 Application Examples 6 3 0000 0001 0002 0003 Copy Module Setup Block to the Ladder File 9 HSCE2 Initialization Routine Programming ladder file 9 shows the direct addressing required to set up the programming blocks in this example HSCEZ and set transmit bit DATA_BLOCK_PTR HSCE2_XMIT HSCE2_ACK EQU O 1 I COP Equal lt lt Copy File Source A N11 0 15 15 Source N10 0 140 lt 1746 HSCE2 1746 HSCE2 Dest 0 1 0 Source B 0 Length 8 0 lt HSCE2_XMIT O 1 L 15 i 1746 HSCE2 When the previous block is completed transmit and acknowledge bit are res
122. tus when the rate value is less than the minimum value virtual output The status bits within the module that are set by module s program and can be examined by the user program A abbreviations G 1 acknowledge bits 4 2 application errors 5 4 counter overflow 5 4 counter underflow 5 4 initialization errors 5 6 OTE instructions 5 6 programming errors 5 6 rate overflow 5 4 soft preset 5 6 underflow 5 4 C cable length A 1 capture value 2 6 2 7 CE certified A 1 CE mark 3 1 certification A 1 class 1 1 4 ID code 4 1 valid count range 2 12 class 4 1 4 ID code 4 1 valid count range 2 12 control range rate range 2 14 count range 2 12 range type programming bit 4 21 with linear counter 2 12 with ring counter 2 13 count value 2 9 2 10 count rate bit 2 19 counter configuration block 4 10 C 1 counter type bit 4 12 debug mode selection bit 4 11 error conditions 5 3 filter value bits 4 13 gate preset mode bits 4 13 input configuration bits 4 12 program counter number bits 4 12 transmit bit 4 11 counter control block 4 23 C 3 control words 4 24 count or rate value bit 4 26 enable counter n bit 4 24 enable range bits 4 27 error conditions 5 4 internal direction n bit 4 25 output enable 4 26 output ON OR mask 4 26 Index program counter n bit 4 26 soft preset n bit 4 25 Counter Input Data Class 4 Operation 2 16 counter input data 2 14 2 19 acknowledge bit 2 17 class 1 2 15 counter status bytes 2 18
123. us of the module FLT Red Steady on Module fault Flashing Output overcurrent Al Yellow ON OFF status of input A1 A2 Yellow ON OFF status of input A2 B1 Yellow ON OFF status of input B1 B2 Yellow ON OFF status of input B2 Z1 Yellow ON OFF status of input Z1 Z2 Yellow ON OFF status of input Z2 Publication 1746 UM002B EN P August 2004 1 6 Module Overview Jumpers Six jumpers select the input voltages for the six inputs A1 B1 Z1 A2 B2 and Z2 The module accepts input voltages of 5V dc 12V dc or 24V dc See Chapter 3 for jumper locations and settings Publication 1746 UM002B EN P August 2004 Chapter 2 Operating Modes Module Operation The chapter contains information about e Operating modes e input configurations e gate preset modes e counter types e rate value e outputs e range types The module s operating mode determines the number of available counters and which inputs are attached to them The three operating modes and their input assignments are summarized in Figure 2 1 Figure 2 1 Operating Mode Input Assignments A1 gt gt Counter 1 Counter 3 Counter 1 Counter 3 E a Counter 2 Counter 4 2 gt Counter 2 Counter 4 E JLo 22 Operating Mode 1 Operating Mode 2 7 Counter 1 Counter 3 GD gt 7 Counter 2 Counter 4 E gt Operating Mode 3 Publication 1746 UM002B EN P August 2004 2 2 Module Op
124. utputs Module Operation 2 13 Figure 2 8 Count Range with Ring Counter 23 000 Range 4 8 099 20 000 10 000 12 500 Range 1 Start Stop Outputs Outputs Range Value Value Affected 7 6 5 4 3 2 1 0 1 10 000 12 500 0 0 0 0 0 0 0 1 0 2 200 8 000 0 0 0 0 0 01 0 1 3 32 000 500 0 0 0 0 0 1 0 0 2 4 20 000 23 000 0 0 0 0 1 0 0 1 0 and 3 1 Bits 0 through 3 are real outputs Bits 4 through 7 are virtual outputs Publication 1746 UM002B EN P August 2004 2 14 Module Operation 32 767 min rate value Rate Range In a rate range the outputs are active if the rate measurement is within the user defined range The valid input rate is dependent upon the operating class In Class 1 the input rate can be up to 32 767 Hz in either direction In Class 4 the input rate can be up to 1 MHz in either direction The linear counter example in Figure 2 9 uses Class 1 operation Figure 2 9 Rate Range 32 767 max rate value i apr 1 Range 1 Range 2 Range 4 i Ap Range 3 on Output 0 off i Output i l i Output i Output 3 n l anie Start Stop Outputs Outputs g Value Value 71 61 514 3 21110 Affected 1 7000 5000 0 0 0 0 0 0 0 1 0 2 1000 4500 0 0 0 0 0 0 1 0 1 3 4000 3000 0 0 0 0 0 1 0 0 2 4 20000 20000 0 0 0 0 1 0 0 1 0 and 3 Counter Input
125. ve transition on the Z input of the counter This stored value is made available to the backplane A stored status bit in the input image table is set to signal the processor that a new value is available This bit is active until the capture value is read by the processor Therefore it is on for a maximum of 10 ms in Class 1 and a maximum of one scan or 10 ms whichever is shorter in Class 4 If a second capture event occurs before the first is read the first value is lost The count and rate values are not affected by a store event counter has stopped counting mE BAN stop count Pu store count counter has start stopped counting counting stop count T7 from preset d Store count Store count preset start counting Module Operation 2 7 Store Hold Resume The count value captured when the module detects a positive transition on the Z input is made available to the backplane A stored status bit is set in the input image table to signal the processor that a new value is available This bit is active until the capture value is read by the processor Therefore it is on for a maximum of 10 ms in Class 1 and a maximum of one scan or 10 ms whichever is shorter in Class 4 The count value is held as long as the Z input is active Because the count value is not changing the rate value is equal to zero while the counter is held Store Preset Hold Resume The counter is set to its programmed preset value when the
126. ximum value Figure 2 6 Ring Counter Diagram Maximum Value Minimum Value Rollover Count Down Count Up The rate value reported to the processor is calculated in counts per second Hz and is available with all input configurations The input configuration determines how the rate value is calculated When the count value is increasing the rate value is positive When the count value is decreasing the rate value is negative The rate value is generally calculated as follows When the first input pulse is received the value of an independent free running timer Ta is recorded The module waits approximately 16 ms while counting more input pulses After 16 ms the module waits for the next input pulse and the value of the independent timer Tb is again recorded The module then calculates the rate value using the formula number of counts rate value Tb Ta Output Control Module Operation 2 11 Additional checks ensure that rates below 1 Hz which are not supported by the module and frequencies due to motor vibration are not counted in the rate value calculation Table 2 1 Typical Rate Update Times Rates Hz Time Between Pulses ms Time Between Updates ms 1 to 59 17 to 1000 17 to 1000 60 to 1000 0 to 16 0 to 33 Above 1000 0 to 1 16 Mihaela Because of the way the 1746 HSCE2 performs rate value calculations invalid rate measurements may occur if the input f
127. y when the acknowledge bit is set This bit is reset when the last programming block is accepted without error It is set when any one of the reserved bits are set or another programming error has occurred For a list of other programming error conditions see Module Programming Errors on page 5 3 DEBUG Debug Mode Bit This bit is set when the debug mode is active IMPORTANT When the debug mode is active the input data file shows the programming setup not rate and count values For details see Debug Mode Operation on page 5 7 FB1 Fuse Status Bit The FB1 fuse status bit is set 1 when the fuse is open In addition the module fault LED blinks to indicate an open fuse When FB1 is set 1 the real outputs do not function Virtual outputs are not affected The input word reflects this condition The module tries resetting the outputs at intervals of 500 ms During each retry the fuse status bit is reset 0 After the overload condition is corrected the fuse bit resets 0 automatically Publication 1746 UM002B EN P August 2004 2 18 Module Operation Publication 1746 UMO002B EN P August 2004 OP MODE Operating Mode Bits The module uses these two bits to tell the processor what mode it is in In class 1 the data value that an input word contains changes based on the operating mode Table 2 2 Mode Bit Settings Bit 09 Bit 08 Mode 0 0 Reserved 0 1 Mode 1 1 0 Mode 2 1 1 Mode 3 Output State

Multi-Channel High Speed Counter

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