TPMC117-DOC
Contents
1. PCI CFG Write 0 to all unused Reserved bits PCI Initial Values Register writeable Hex Values Address 31 24 23 16 15 8 7 0 0x00 Device ID Vendor ID N 0075 1498 0x04 Status Command Y 0280 0000 0x08 Class Code Revision ID N 118000 00 0x0C BIST Header Type PCI Latency Cache Line Y 7 0 00 00 00 00 Timer Size 0x10 PCI Base Address 0 for MEM Mapped Config Registers Y FFFFFF80 0x14 PCI Base Address 1 for I O Mapped Config Registers Y FFFFFF81 0x18 PCI Base Address 2 for Local Address Space 0 Y FFFFFFOO 0x1C PCI Base Address 3 for Local Address Space 1 Y 00000000 0x20 PCI Base Address 4 for Local Address Space 2 Y 00000000 0x24 PCI Base Address 5 for Local Address Space 3 Y 00000000 0x28 PCI Card bus Information Structure Pointer N 00000000 0x2C Subsystem ID Subsystem Vendor ID N 000A 1498 0x30 PCI Base Address for Local Expansion ROM Y 00000000 0x34 Reserved New Cap Ptr N 000000 40 0x38 Reserved N 00000000 0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line Y 7 0 00 00 01 00 0x40 PM Cap PM Nxt Cap PM Cap ID N 4801 48 01 0x44 PM Data PM CSR EXT PM CSR Y 00 00 0000 0x48 Reserved HS CSR HS Nxt Cap HS Cap ID Y 23 16 00 00 4C 06 0x4C VPD Address VPD Nxt Cap VPD Cap ID Y 31 16 0000 00 03 0x50 VPD Data Y 00000000 Table 4 1 PCI9030 Header TPMC117 User Manual Issue 1 0 2 Page 28 of 51 4 1 2 PCI Base Address Initialization PCI Base2. Table 7 2 DIP Switch Settings The Factory setting of the DIP switch is OFF hence the input configuration is single ended TTL 7 1 2 Single Ended TTL The following schematic shows the principle input wiring for one single ended TTL encoder signal For single ended TTL input leave the inverting input A open and connect the TTL signal to the noninverting input A The1200 termination resistor must be switched off when using single ended TTL input signals Figure 7 3 Single ended Input Wiring The switching point lies at approx 1 6V with a hysteresis of about 0 4 mV TPMC117 User Manual Issue 1 0 2 Page 47 of 51 7 1 3 Differential RS422 The following schematic shows the principle input wiring for one differential RS422 encoder signal RS422 input signals should be terminated The encoder input is fail safe based so that unused inputs can be left open Vcc Vcc A Figure 7 4 Differential Input Wiring It is recommended to terminate differential RS422 input signals 7 2 Clock Output Wiring The TPMC117 adheres to the original SSI specification that featured galvanic insulation with optocouplers Therefore the clock inputs in the sensor did not need a ground reference Nowadays the sensor s clock inputs are often build with conventional RS422 receivers which do need a ground reference The TPMC117 s clock drivers are referenced to circuit ground which is not available at the connector In this cas
3. Table 4 4 Configuration EEPROM TPMC117 Subsystem ID Value Offset Ox0C TPMC117 10 Ox000A TPMC117 User Manual Issue 1 0 2 Page 31 of 51 4 4 Local Software Reset The PCI9030 Local Reset Output LRESETo is used to reset the on board local logic The PCI9030 local reset is active during PCI reset or if the PCI Adapter Software Reset bit is set in the PCI9030 local configuration register CNTRL offset 0x50 CNTRL 30 PCI Adapter Software Reset Value of 1 resets the PCI9030 and issues a reset to the Local Bus LRESETo asserted The PCI9030 remains in this reset condition until the PCI Host clears this bit The contents of the PCI9030 PCI and Local Configuration Registers are not reset The PCI9030 PCI Interface is not reset TPMC117 User Manual Issue 1 0 2 Page 32 of 51 5 Configuration Hints 5 1 Big Little Endian e PCI Bus Little Endian Byte 0 ADI7 0 Byte 1 AD 15 8 Byte 2 AD 23 16 Byte 3 AD 31 24 e Every Local Address Space 0 3 and the Expansion ROM Space can be programmed to operate in Big or Little Endian Mode Big Endian Little Endian 32 Bit 32 Bit Byte 0 Sg Byte SE Bye2 0123 16 Byte 3 SE 16 Bit upper lane 16 Bit Byte 0 Sg Byte SE 16 Bit lower lane A 8 Bit upper lane 8 Bit Byte 0 Sg 8 Bit lower lane EA Byte 0 D 7 0 Table 5 1 Local Bus Little Big Endian TPMC117 User Manual Issue 1 0 2 Page 33 of 51 Standard use of the TPMC117 Local
4. SSI Data Valid Interrupt disabled An interrupt will be generated when a SSI transmission 2 SIEN2 completes and the Busy status bit is set to 0 1 SIEN1 0 SIENO Table 3 14 Interrupt Enable Register 3 15 Interrupt Status Register The interrupt status is updated only if the interrupt enable bit of the corresponding channel is set to 1 Otherwise the interrupt status is read as 0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved Digital Input IRQ Status Control 2 2 2 2 2 2 2 1 opo o o o o 0 0h bib blbblb lb ialalalalalalolo Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode IRQ Status Match IRQ Status SSI IRQ Status CH CN o 1O ks 9p N lt o 1O st CH N e o si ls ls Isi LL LL LI L LLL LILIA ETE E E EJ E vo o 0 9 90 90 0 0 0 b a b o O O JOJO Z2 gt 2 2 2 2 0 NDI ODI nl nin Bit Symbol Description Access Reset Value 31 25 Reserved always reads as 0 0 24 TISTA Pending Interval Timer Interrupts Read R C 0 Interrupt acknowledge Write On a read access this bit indicates a pending Interval Timer interrupt A 1 indicates a pending interrupt The interrupt is acknowledged by writing a 1 to this bit 23 DISTAS Pending Digital Input Interrupts Read R C 0 22 DISTA4 Interrupt acknowledge Write 21 DISTA3 On a read access these
5. 0 0 0 0 0 0 0 0 0 0 0 0 IDN WH Bit Symbol Description Access Reset Value 31 3 Reserved always reads as 0 0 2 1 ITDIV Interval Timer Clock Divider R W 0 Value Mode 0 0 8 MHz 0 1 4 MHz 1 0 2 MHz 1 1 1 MHz 0 ITEN Interval Timer Enable R W 0 0 disables the Interval Timer 1 enables the Interval Timer Table 3 10 Interval Timer Control Register 3 11 Interval Timer Preload Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interval Timer Preload Register ITPRE Bit Symbol Description Access Reset Value 31 16 Reserved always reads as 0 0 15 0 ITPRE Interval Timer Preload Register R W 0 Table 3 11 Interval Timer Preload Register TPMC117 User Manual Issue 1 0 2 Page 21 of 51 3 12 Interval Timer Data Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interval Timer Data Register ITDR Bit Symbol Description Access Reset Value 31 16 Reserved always reads as 0 0 15 0 ITDR Interval Timer Data Register R W 0 This register contains the actual Interval Tim
6. Address Space 0 32 bit bus in Little Endian Mode Local Address Space 1 not used Local Address Space 2 not used Local Address Space 3 not used Expansion ROM Space not used To change the Endian Mode use the Local Configuration Registers for the corresponding Space Bit 24 of the according register sets the mode A value of 1 indicates Big Endian and a value of 0 indicates Little Endian For further information please refer to the PCI9030 manual which is also part of the TPMC117 ED Engineering Documentation Use the PCI Base Address 0 Offset or PCI Base Address 1 Offset Short cut Offset Name LASOBRD 0x28 Local Address Space 0 Bus Region Description Register LAS1BRD 0x2C Local Address Space 1 Bus Region Description Register LAS2BRD 0x30 Local Address Space 2 Bus Region Description Register LAS3BRD 0x34 Local Address Space 3 Bus Region Description Register EROMBRD 0x38 Expansion ROM Bus Region Description Register You could also use the PCI Base Address 1 I O Mapped Configuration Registers TPMC117 User Manual Issue 1 0 2 Page 34 of 51 6 Functional Description Each channel can either work as a SSI interface or as an encoder general purpose counter The choice between both modes is made in the Global Control Register on a per channel base In addition to this main functionality the TPMC117 offers one isolated 24V digital input per channel plus an interval timer 6 1 SSI Short Description The Synchronous Serial Interface SSI
7. Control Mode determines how the counter interprets events on the l input Reference modes are only valid when Input Mode Quadrature Count ICM Mode None Reference Mode 000 Ignore l input 001 Load on 010 Latch on 011 Gate on 100 Reset on Reference Modes 101 Reference mode 110 Auto reference mode 111 Index mode See chapter 6 3 3 Index Control Modes for details 22 21 SCM Special Count Mode R W 00 1 0 SCM Mode 00 No special mode active cycling counter 01 Divide by N 10 Single Cycle See chapter 6 3 2 Special Count Modes for details 20 19 CLKDIV Internal Clock Prescaler R W 00 1 0 CLKDIV Prescaler Clock frequency 00 1x 32 MHz 01 2x 16 MHz 10 4x 8 MHz 11 8x 4 MHz TPMC117 User Manual Issue 1 0 2 Page 14 of 51 Bit Symbol Description Access Reset Value 18 16 INPUT Counter Input Mode R W 000 2 0 The Input Mode determines the input source and how the counter interprets these input signals The Quadrature mode can be used with a 1x 2x or 4x resolution multiplier INPUT Input Mode Input Source 000 Counter disabled 001 Timer Mode Up Internal Clock Prescaler 010 Timer Mode Down Internal Clock Prescaler 011 Direction Count Input A amp Input B 100 Up Down Count Input A amp Input B 101 Quadrature Count 1x Input A amp Input B 110 Quadrature Count 2x
8. data processes it parity check gray to binary code conversion and indicates the end of the data transfer with the deassertion of the Busy bit If enabled an interrupt is asserted and the positional data can be read in the Data Register In this mode the Read Error status bit is always read as 0 TPMC117 User Manual Issue 1 0 2 Page 36 of 51 6 2 2 SSI Listen only Mode In Listen only Mode a TPMC117 channel listens to an existing SSI interface to observe the data transfer Both the SSI clock and data signals are inputs to the TPMC117 Absolute Encoder TPMC117 Listen Only gt CLKINO e j P CLKINO 36 lt DATAO ER L l SSI Interface Controller DATAO 37 EE EE CLOCK CLOCK DATA DATA Figure 6 3 Wiring Example Channel 0 Listen only Mode This mode is enabled when the Interface Control in the Global Control Register is set to 01 and the MODE bit in the Control Register is set to 1 Register Bit Setting Global Control Register ICx 01 Control Register X MODE T Table 6 3 SSI Listen only Mode Selection In the Control Register the SSI interface must be set up conforming to the settings required of the observed SSI interface Register Symbol Setting Control Register X BC Number of data bits CODE B
9. external SSI clock to TPMC117 CLK IN inputs Data Transfer Start Data transfer is initiated by a write to the Data Register or a Multiple Channel Read Data transfer is initiated by external SSI interface controller Table 6 5 Mode behavior differences TPMC117 User Manual Issue 1 0 2 Page 38 of 51 6 3 Counter Mode The TPMC117 counter offers 4 input modes 2 special count modes and 8 index control modes 6 3 1 Input Modes The input mode determines how the counter interprets the A and B input lines Input Mode A Input B Input l Input Timer not used not used Direction Count Count Count direction up down Available for Input Up Down Count Count UP Count DOWN Control Modes Quadrature Count Quadrature A Quadrature B Table 6 6 Input Modes Changing the input mode does not affect the counter reading If no input mode is selected the counter is disabled 6 3 1 1 Timer Mode In Timer mode the counter uses an internal clock prescaler as input Bits Prescaler Clock frequency 00 1x 32 MHz 01 2x 16 MHz 10 4x 8 MHz 11 8x 4 MHz Table 6 7 Clock Prescaler 6 3 1 2 Direction Count The counter acts as up down counter Counting pulses are generated when a transition from low to high of the A input is detected The B input determines the count direction B input Count Direction 0 Down 1 Up Table 6 8
10. in the Divide by N mode every time the counter creates a borrow or a carry Reference modes Table 3 6 Counter Preload Register 3 7 Counter Compare Register Bit Symbol Description Access Reset Value 31 0 Counter Compare Register R W 1 Every time the counter matches the Counter Compare Register value bit 18 MAT of the Status Register is set to 1 and if enabled an interrupt is generated Table 3 7 Counter Compare Register 3 8 Counter Command Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 o Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reserved o o o o o o o o o o o o o o LCNT RCNT TPMC117 User Manual Issue 1 0 2 Page 19 of 51 Bit Symbol Description Access Reset Value 31 2 Reserved always reads as 0 0 1 LCNT Load Counter W 0 Write 1 to load the counter with the value of the Counter Preload Register 0 RCNT Reset Counter W 0 Write 1 to reset the counter Table 3 8 Counter Command Register Commands are performed by writing a 1 to the according
11. of 1 to 15 A value of 0 for the clock rate will stop the operation CR1 of the SSI interface CRO The Listen only Mode will ignore the Clock Rate setting in this mode the Clock Rate will be detected automatically O N O0 Table 3 3 Control Register Note that a value of 0x00 or a value from 0x21 to 0x3F for BC5 BCO0 is not valid and will stop the operation of the SSI Interface 3 4 Data Register Bit Symbol Description Access Reset Value 31 0 Data Register R W 0 Table 3 4 Data Register When the channel is disabled the Data Register returns 0x00000000 on read accesses 3 4 1 Data Register in SSI Mode The serial data of the absolute encoder is shifted into the Data Register In Standard SSI Interface mode a write access to the Data Register initiates a data transfer from the absolute encoder independently of the other channels In Listen only SSI Interface mode a read access to the Data Register sets the Busy bit to 1 and the channel is listening again The data register may not contain valid data if the serial data transfer is in progress the corresponding Busy bit is read as 1 3 4 2 Data Register in Counter Mode The Data Register contains the actual counter value While a Multiple Channel Read is in progress this register may contain latched data In Latch on P control mode this register contains latch
12. which allows timing intervals of up to 65ms It can be used as reference timer for closed loop applications or as trigger for the Multiple Channel Read function All data inputs are isolated The level of the input signals can be RS422 or TTL The input signals pass a digital filter for noise suppression before they are further used The level of the SSI clock output signals is RS422 TPMC117 User Manual Issue 1 0 2 Page 8 of 51 Each of the six motion control channels of the TPMC117 offers one isolated 24V digital input The input circuit ensures a defined switching point and polarization protection against confusing the pole The input has an electronic debounce circuit All six 24V digital inputs can generate an interrupt triggered on rising or falling edge Depending on the selected mode the input can be used as general purpose input or reference input All signals are accessible through a HD68 SCSI 3 type front I O connector The TPMC117 can operate with 3 3V and 5 0V PCI I O signaling voltage TPMC117 User Manual Issue 1 0 2 Page 9 of 51 2 Technical Specification PMC Interface Mechanical Interface PCI Mezzanine Card PMC Interface Single Size Electrical Interface PCI Rev 2 2 compliant 33 MHz 32 bit PCI 3 3V and 5V PCI Signaling Voltage On Board Devices PCI Target Chip PCI9030 PLX Technology UO Interface Number of Channels 6 isolated channels with 3 input lines and 1 output line
13. 030 for PCI I O and or PCI Memory Space access in the PCI9030 PCI Command Register Offset 0x04 To enable PCI I O Space access to the PCI9030 set bit 0 to 1 To enable PCI Memory Space access to the PCI9030 set bit 1 to 1 Offset in Config Description Usage 0x10 PCI9030 LCR s MEM Used 0x14 PCI9030 LCR s I O Used 0x18 PCI9030 Local Space 0 Used 0x1C PCI9030 Local Space 1 Not used 0x30 Expansion ROM Not used Table 4 2 PCI9030 PCI Base Address Usage TPMC117 User Manual Issue 1 0 2 Page 29 of 51 4 2 Local Configuration Register LCR After reset the PCI9030 Local Configuration Registers are loaded from the on board serial configuration EEPROM The PCI base address for the PCI9030 Local Configuration Registers is PCI9030 PCI Base Address 0 PCI Memory Space Offset 0x10 in the PCI9030 PCI Configuration Register Space or PCI9030 PCI Base Address 1 PCI I O Space Offset 0x14 in the PCI9030 PCI Configuration Register Space Do not change hardware dependent bit settings in the PCI9030 Local Configuration Registers Offset from Register Value Description PCI Base Address 0x00 Local Address Space 0 Range OxOFFF_FFOO 256 Bytes Memory Space 0x04 Local Address Space 1 Range 0x0000_0000 Not used 0x08 Local Address Space 2 Range 0x0000_0000 Not used 0x0C Local Address Space 3 Range 0x0000_0000 Not used 0x10 Loc
14. 11 INTERVAL TIMER PRELOAD REGISTER 0oooocccccoccnoccnononcnnnoncnnnancnnonnnnnnnnnnno nana nn nan nnnn nan ncnnnos 21 TABLE 3 12 INTERVAL TIMER DATA REGISTER ooocccocccononcnnnoncnonnnnnoncnn non nnnoncn nro cnn narco cnn 22 TABLE 3 13 GLOBAL CONTROL REGIST ER ose eee eee etre eres ete nc teeta ae eee nn rn 23 TABLE 3 14 INTERRUPT ENABLE REGISTER 00 0 0 ec cece cece ete eee ae nan nc nro rca ea cnn cnn rn 25 TABLE 3 15 INTERRUPT STATUS REGISTER 0 0 eee eee c eter eee sete ae teen eet ae eee ae sneee taser tage eneaeeeeaes 26 TABLE 3 16 TEST REGISTER eege see eebe ER iain TA bd a e aia 27 TABLE 4 4 PGI9030 HEADER iia Eesen ee geed 28 TABLE 4 2 PCI9030 PCI BASE ADDRESS USAGE 00 ooo eect eee e eee cnn cnn nan cnn nan nn nan nn canon nana nana 29 TABLE 4 3 PCI9030 LOCAL CONFIGURATION REGISTER o ooocccnccccconcnononcnanonononcnnnonnnnnononannn nan n nn nannncnnnos 30 TABLE 4 4 CONFIGURATION EEPROM TPDMCTITI occ ees cee eter eee ncnnnn cnn cnn nro rca anno cnn ran 31 TABLE 5 1 LOCAL BUS UTTLEIDIGENDIAN narco nan nc reer nana nana 33 TABLE 6 1 SSI STANDARD MODE GELECTION nan nnnnnn conan cnn non nan no nana n nro rn 36 TABLE D SSPSETUP iieii a a A ead A E A a ld aa Edi So 36 TABLE 6 3 SSI LISTEN ONLY MODE GEL CTION nono eter tener nro cnn nan nn nnnn cnn rca 37 TABLE 6 4 2 SSI LISTEN ONLY SETUP tiaia aati a a aai edel deed Eed TA e 37 TABLE 6 5 MODE BEHAVIOR DIFFERENCES esssssssressresrrnsrnstrnntrrntrnastnuct
15. 5 0x24 Not Used Table 3 1 PCI9030 Local Space Configuration TPMC117 User Manual Issue 1 0 2 Page 11 of 51 3 2 Local Register Address Space Offset to PCI Register Name Size Base Address 2 Bit 0x00 Control Register 0 32 0x04 Data Register 0 32 0x08 Status Register 0 32 0x0C Counter Preload Register 0 32 0x10 Counter Compare Register 0 32 0x14 Counter Command Register 0 32 0x18 Control Register 1 32 0x1C Data Register 1 32 0x20 Status Register 1 32 0x24 Counter Preload Register 1 32 0x28 Counter Compare Register 1 32 0x2C Counter Command Register 1 32 0x30 Control Register 2 32 0x34 Data Register 2 32 0x38 Status Register 2 32 0x3C Counter Preload Register 2 32 0x40 Counter Compare Register 2 32 0x44 Counter Command Register 2 32 0x48 Control Register 3 32 0x4C Data Register 3 32 0x50 Status Register 3 32 0x54 Counter Preload Register 3 32 0x58 Counter Compare Register 3 32 0x5C Counter Command Register 3 32 0x60 Control Register 4 32 0x64 Data Register 4 32 0x68 Status Register 4 32 0x6C Counter Preload Register 4 32 0x70 Counter Compare Register 4 32 0x74 Counter Command Register 4 32 TPMC117 User Manual Issue 1 0 2 Page 12 of 51 Offset to PCI Register Name Size Base Address 2 Bit 0x78 Control Register 5 32 0x7C Data Regi
16. 50 lt 400 lt 100 lt 300 lt 200 lt 200 lt 400 lt 100 TPMC117 User Manual Issue 1 0 2 Page 35 of 51 6 2 SSI Mode 6 2 1 Standard SSI Interface Controller Mode In this mode a TPMC117 channel operates as a standard SSI interface controller The SSI clock is an output and data signal is an input to the TPMC117 TPMC117 etarra contol Absolute Encoder gt CLKO 4 CLOCK gt j CLKO E CLOCK lt DATA0 3 DATA e DATAO 37 DATA AAA Figure 6 2 Wiring Example Channel 0 SSI Interface Controller Mode This mode is enabled when the Interface Control in the Global Control Register is set to 01 and the MODE bit in the Control Register is set to 0 Register Symbol Setting Global Control Register ICx 01 Control Register X MODE g Table 6 1 SSI Standard Mode Selection In the Control Register the SSI interface must be set up conforming to the settings required of the connected absolute encoder Register Symbol Setting Control Register X BC Number of data bits CODE Binary Gray Code ZB Additional Zero Bit EO Even Odd Parity PAR Parity detection CR Clock Rate Table 6 2 SSI Setup A data transfer is initiated by a write to the Data Register The SSI interface controller then generates a clock burst on which the absolute encoder returns its positional data The SSI Controller receives this
17. 7 User Manual Issue 1 0 2 Page 44 of 51 There is no designated interrupt to indicate the completion of a Multiple Channel Read Alternatively an interrupt can be set up for the SSI channel that takes the longest time to complete a conversion If only counter channels are read an interrupt is not necessary because the counter data is instantly available 6 5 Interval Timer The interval timer is a 16 bit preloadable counter with a programmable clock rate On activation the counter loads from the Interval Timer Preload Register und starts counting down When the counter reaches zero it generates an interrupt if enabled is automatically preloaded again and continues counting With the 16 bit preload register and the programmable clock interval interval times up to 65ms are possible Calculate the interval times using the following formula Interval Time Value of Interval Timer Preload Register Clock period ITDIV Clock Frequency Clock Period 00 8 MHz 125ns 01 4 MHz 250ns 10 2 MHz 500ns 11 1 MHz 1us Table 6 13 Interval Timer Clock Periods The interval timer can be used as a reference timer in closed loop applications or as a trigger for a multiple channel read 6 6 Isolated 24V Digital Inputs The TPMC117 offers one isolated digital 24V input per channel The inputs are electronically debounced Each digital 24V input can generate an interrupt triggered on rising or falling edge Depending on the
18. Address Initialization is scope of the PCI host software PCI9030 PCI Base Address Initialization 1 Write OxFFFF_FFFF to the PCI9030 PCI Base Address Register 2 Read back the PCI9030 PCI Base Address Register 3 For PCI Base Address Registers 0 5 check bit O for PCI Address Space Bit 0 0 requires PCI Memory Space mapping Bit 0 1 requires PCI I O Space mapping For the PCI Expansion ROM Base Address Register check bit 0 for usage Bit 0 0 Expansion ROM not used Bit O 1 Expansion ROM used 4 For PCI I O Space mapping starting at bit location 2 the first bit set determines the size of the required PCI I O Space size For PCI Memory Space mapping starting at bit location 4 the first bit set to 1 determines the size of the required PCI Memory Space size For PCI Expansion ROM mapping starting at bit location 11 the first bit set to 1 determines the required PCI Expansion ROM size For example if bit 5 of a PCI Base Address Register is detected as the first bit set to 1 the PCI9030 is requesting a 32 byte space address bits 4 0 are not part of base address decoding 5 Determine the base address and write the base address to the PCI9030 PCI Base Address Register For PCI Memory Space mapping the mapped address region must comply with the definition of bits 3 1 of the PCI9030 PCI Base Address Register After programming the PCI9030 PCI Base Address Registers the software must enable the PCI9
19. Count Directions 6 3 1 3 Up Down Count The counter acts as up down counter Counting pulses are generated when a transition from low to high of either the A or the B input is detected The A input counts up the B input counts down Simultaneous transitions on the A and B input do not generate a counting pulse TPMC117 User Manual Issue 1 0 2 Page 39 of 51 6 3 1 4 Quadrature Count The counter acts as quadrature counter A input is quadrature input A B input is quadrature input B The quadrature inputs can be interpreted as 1x 2x or 4x counting 1x lets the counter count once for each full cycle of the quadrature inputs 2x lets the counter count once for each half cycle of the quadrature inputs and 4x lets the counter count once for each quarter cycle of the quadrature inputs The count direction increase or decrease is determined by the relative phase of the A and B signals The maximum input frequency is 2 MHz In 4x mode the counter counts with max 8 MHz 1x single y 2x douple E 4x quad 4 LE LU Figure 6 4 Quadrature Signals 6 3 2 Special Count Modes In normal operation the counter is a cycling counter Two additional special count modes are available The Count Modes are available for every Input Mode 6 3 2 1 Divide by N The counter is enabled in the Control Register and will run until it is disabled The counter i
20. G WITH DIFFERENTIAL RECEIVER INPDUT ee 49 FIGURE 7 7 DIGITAL INPUT WIRING 00 eee ete terre ne errant aes eee nn ee nan n naar nan nn a 49 FIGURE 8 1 FRONT PANEL I O CONNECTOR o cccooccccocccononncononncnonnnnnnnnnononnnnnnnnnnnnnnnnnnnnnnn cnn n nn nan nnn nan nnnanninns 50 TPMC117 User Manual Issue 1 0 2 Page 6 of 51 List of Tables TABLE 2 1 TECHNICAL SGPECIFICATION ee eee ester etre ete cnn nan nn nn cnn nora nn rare 10 TABLE 3 1 PCI9030 LOCAL SPACE CONFIGURATION cococccccoccnnccccconcnnnnnnnnnnonononcn nao nnn nan nn nan nn nan nnnnnnn caninos 11 TABLE 3 2 LOCAL REGISTER ADDRESS SPACE cococccccccccconcnononcnnannnnoncnnnnnnnnnnn cnn rca nan nn anno cnn enn nan nn anar nc 13 TABEE 3 3 CONTROL REGISTER ooo dai tdi eege 16 TABLE 3 4 DATA RE GS TER eessen eege deer aAA aiaa TA Tao A Da EAEE a SANNA eege 16 TABLE 3 5 gt SSI STATUS REGISTER niian yeep aaa Sege eaaa a a aLi C A aa E aT aa danna 18 TABLE 3 6 COUNTER PRELOAD REGISTER irsin pi soatida e Eaa E tenet teaser EE A L l E aaia 19 TABLE 3 7 COUNTER COMPARE REGISTER 00ccconcccccocccononcnnnnnnancnononcnnnn nan nnncn cnn nan nr cnn nn nora rn 19 TABLE 3 8 COUNTER COMMAND REGISTER 00ccciccccocccononcnnnnnononcnononcnn no nn nano eset rca no cananea rn 20 TABLE 3 9 DIGITAL INPUT REGISTER 0 0 ec cece ete i i cnn cnn nro rn rancia 20 TABLE 3 10 INTERVAL TIMER CONTROL REGISTER oooocccococcncccccnoncnononnnnanonononcnnnonnn nan conan nnn nan nnnnnnncnnnos 21 TABLE 3
21. HD68 SCSI 3 type female connector e g AMP 787082 Pin 34 Pin 1 KZ Q S nn EDD E o GRARRRRARARARARERARABRERARAAARRARE Pin 68 Pin 35 Figure 8 1 Front Panel I O Connector Pin SSI Signal Counter Signal Pin SSI Signal Counter Signal OND ENC_A2 CLK IN2 ENC_B2 DATA2 EN D r wo al E D A Blo 00 A O J 36 37 38 D Z U ENC_A1 CLK IN1 ENC_B1 DATA1 ENG D CLK OUT1 ENC_A2 CLK IN2 ENC_B2 DATA2 ENC_12 CLK OUT2 S 1 2 43 45 6 47 S CLK OUT2 GND_ O Zz U ENC_A3 CLK IN3 ENC_B3 50 CLK IN3 ENC_B3 GND_l 25 CLK IN5 ENC_B5 59 CLK IN5 ENC_B5 51 2 DATA3 ENC_I3 CLK OUT3 ENC_A4 CLK IN4 ENC_B4 DATA4 ENG WM CLK OUT4 54 55 56 aja o Om 00 Wi I D Zz U TPMC117 User Manual Issue 1 0 2 Page 50 of 51 Pin SSI Signal Counter Signal 26 DATA5 ENC_I5 27 foxos gt gt gt T 2 a z S S 34 24V Digital Input 5 24V Digital Input 0 GND 24V Digital Input 1 GND 24V Digital Input 2 GND 24V Digital Input 3 GND 24V Digital Input 4 GND 24V Digital Input 5 GND Table 8 1 Pin Assignment Front I O Connector TPMC117 User Manual Issue 1 0 2 Page 51 of 51
22. IEN SZ The Embedded I O Company TECHNOLOGIES TPMC117 6 Channel SSI Incremental Encoder Counter Version 1 0 User Manual Issue 1 0 2 June 2010 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 40580 Fax 49 0 4101 4058 19 e mail info tews com www tews com TPMC117 6 Channel SSI Encoder Interface TPMC117 User Manual Issue 1 0 2 TEWS lt TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox i e O0x029E that means hexadecimal value 029E For signals on hardware products an Active Low is represented by the signal name with following i e IP_RESET Access terms are described as W Write Only R Read Only R W Read Write R C Read Clear R S Read Set 2005 2010 by TEWS TECHNOLOGIES GmbH All trademarks mentioned are property of their respective owners Page 2 of 51 TEWS lt lt TECHNOLOGIES Issue Descripti
23. Input A amp Input B 111 Quadrature Count 4x Input A amp Input B See chapter 6 3 1 Input Modes for details 15 BREAK Break on Read Error Listen only R W 0 1 The channel stops to listen on read errors 0 Read errors are ignored and the channel resumes to listen 14 MODE 1 SSI Listen only Mode R W 0 0 Standard SSI Interface Controller 13 BC5 Number of Data Bits R W 0 12 BC4 Bits are used to program the number of bits of the serial 1 BC3 absolute encoder It can be read and written by software The data bits must be programmed in the range from 1 to 32 10 BC2 BC5 BCO 0x01 to 0x20 means 1 to 32 bit 9 BC1 BC5 BCO 0x00 not valid 8 BCO BC5 BCO 0x21 to Ox3F not valid 7 CODE SSI Data word coding R W 0 1 Gray Code The data word is converted into binary code 0 Binary Code 6 ZB Parity Bit with Zero Bit controls the clock cycles R W 0 1 two additional clock cycles 0 one additional clock cycle are provided to get the parity bit 5 EO Controls the parity detection R W 0 1 odd parity 0 even parity This bit is ignored if bit 4 is set to 0 4 PAR Encoder with parity If encoder provides a parity bit R W 0 1 detect parity errors 0 do not detect parity errors no parity bit TPMC117 User Manual Issue 1 0 2 Page 15 of 51 Bit Symbol Description Access Reset Value CR3 Clock Rate for encoder serial clock speed R W 0 CR2 The clock can be programmed in steps of 1us in the range
24. R W 0 1 Enable Interval Timer as trigger for multiple channel read 0 Disable Interval Timer as trigger for multiple channel read 23 SL5 Enable Multiple Channel Read for the corresponding R W 0 Geer Iti ch read enables multi channel rea 2l ate 0 disables multi channel read 20 SL2 See chapter 6 4 Multiple Channel Read for details 19 SL1 18 SLO 17 PRL5 Manual Counter Preload W 0 16 PRL4 Writing a 1 issues a preload of the corresponding 1 PRL counter with the value of the Counter Preload Register 5 3 This preload method is only possible for channels in a 14 PRL2 None Reference Mode 13 PRL1 E ae F pr eas e E 12 PRLO re er Preload Registers must be loaded with vali 11 10 IC5 1 0 Interface Control R W 0 9 8 IC4 1 0 IC Mode 7 6 IC3 1 0 00 Channel disabled 5 4 IC2 1 0 01 SSI Mode 3 2 IC1 1 0 10 Counter Mode 1 0 ICO 1 0 11 Channel disabled the selection between normal SSI mode and SSI listen only mode is done the Channel Control Register Table 3 13 Global Control Register TPMC117 User Manual Issue 1 0 2 Page 23 of 51 3 14 Interrupt Enable Register For pending interrupts and interrupt acknowledge see the Interrupt Status Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved Enable Digita
25. a Register Lock Overflow OVFL will be set to indicate that data was lost This control mode can be used to capture a position in a mechanical system 6 3 3 4 Gate on The signal level on the l input enables or disables counting Remember that in this mode the l input is level sensitive l input Counter 0 Disabled 1 Enabled Table 6 11 Gate Mode In this mode an interrupt is generated if enabled when the gate is being closed I Input transition from 1 to 0 When a signal with constant frequency is connected to the A and B inputs this control mode can be used for impulse width measurements 6 3 3 5 Reset on An event on the l input resets clears the counter If the Single Cycle mode is active the event on the l input starts the counter The counter can also be reset by writing 1 to the Reset Counter RCNT bit in the Counter Command Register This control mode can be used to establish a known home or reference position in a mechanical system 6 3 3 6 Reference Mode This mode controls the counter with the isolated 24V digital reference input and the encoder index signal A specified reference input signal and a following index impulse produce a counter preload The host software must set the motion direction during such a reference access to backwards The following figure shows the two normal preload accesses An encoder motion area with eight index pulses and the corresp
26. al Exp ROM Range 0x0000_0000 Not used 0x14 Local Re map Register Space 0 0x0000_0001 Enabled Base Address 0x0000 0x18 Local Re map Register Space 1 0x0000_0000 Not used 0x1C Local Re map Register Space 2 0x0000_0000 Not used 0x20 Local Re map Register Space 3 0x0000_0000 Not used 0x24 Local Re map Register ROM 0x0000_0000 Not used 0x28 Local Address Space 0 Descriptor 0x4180_0020 Local Space 0 Configuration 0x2C Local Address Space 1 Descriptor 0x0000_0000 Not used 0x30 Local Address Space 2 Descriptor 0x0000_0000 Not used 0x34 Local Address Space 3 Descriptor 0x0000_0000 Not used 0x38 Local Exp ROM Descriptor 0x0000_0000 Not used 0x3C Chip Select O Base Address 0x0000_0081 Chip Select Local Space 0 0x40 Chip Select 1 Base Address 0x0000_0000 Not used 0x44 Chip Select 2 Base Address 0x0000_0000 Not used 0x48 Chip Select 3 Base Address 0x0000_0000 Not used 0x4C Interrupt Control Status 0x0041 Local IRQ1 amp PCI IRQ enabled 0x4E EEPROM Write Protect Boundary 0x0030 Standard write protection 0x50 Miscellaneous Control Register 0x0078_0000 Retry delay max 0x54 General Purpose UO Control 0x0000_0001 No GPIO 0x70 Hidden1 Power Management data 0x0000_0000 Not used select 0x74 Hidden 2 Power Management data 0x0000_0000 Not used scale Table 4 3 PCI9030 Local Configuration Register TPMC117 User Manual Issue 1 0 2 Page 30 of 51 4 3 Configuration EEPROM After power on or PCI reset the PCI9030 loads initial configuration regist
27. allows quick testing of the RS422 TTL in and outputs To check the digital input levels read the Digital Input Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SSI Clock Outputs Channel Gli SEE ee las ls A E E SS E E g PI O OJO O OJO Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 0 A5 14 13 12 10 olo M lt m lt 11 y ft Oo 49 ol A ol ol x TPMC117 User Manual Issue 1 0 2 Page 26 of 51 Bit Symbol Description Access Reset Value 31 25 Reserved always reads as 0 0 24 TSTEN Enable Test Output R W 0 1 Test Output enabled 0 Test Output disabled 23 CLK5 SSI Clock outputs R W 0 22 CLK4 When TSTEN is 1 these bits will control the SSI clock 21 CLK3 outputs 20 CLK2 19 CLK1 18 CLKO 17 I5 Channel 6 Inputs R 0 16 B5 15 A5 14 14 Channel 4 Inputs R 0 13 B4 12 A4 11 13 Channel 3 Inputs R 0 10 B3 9 A3 8 12 Channel 2 Inputs R 0 7 B2 6 A2 5 11 Channel 1 Inputs R 0 4 B1 3 A1 2 10 Channel O Inputs R 0 1 BO 0 AO Table 3 16 Test Register TPMC117 User Manual Issue 1 0 2 Page 27 of 51 4 PCI9030 Target Chip 4 1 PCI Configuration Registers PCR 4 1 1 PCI9030 Header
28. bit 3 9 Digital Input Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Digital Input Interrupt Control Digital Input Status lalala SiS ro SiS ms Sales Bit Symbol Description Access Reset Value 31 12 Reserved always reads as 0 0 11 DIIC5 Digital Input Interrupt Control R W 0 10 DIIC4 Selects interrupt on rising or falling edge for corresponding 9 DIIC3 24V digital input 8 1 selects interrupt for rising edge 8 DIIC2 0 selects interrupt for falling edge 7 DIIC1 6 DIICO 5 DI5 These bits reflect the actual state of the digital 24V inputs R 4 DI4 In Reference Mode and Auto Reference Mode the digital 3 DI3 24V inputs are used as reference inputs In all other modes the digital 24V inputs can be used as 2 DI2 general purpose inputs 1 DI1 0 DIO Table 3 9 Digital Input Register TPMC117 User Manual Issue 1 0 2 Page 20 of 51 3 10 Interval Timer Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 0 0 0O0 O0OJO OJOTIOJO OJO O OTOJ OL O Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Z 0
29. bits indicate the channels with pending digital input interrupts A 1 indicates a pending 20 DISTA2 interrupt 19 DISTA1 The interrupts are acknowledged by writing a 1 to the 18 DISTAO according bit TPMC117 User Manual Issue 1 0 2 Page 25 of 51 Bit Symbol Description Access Reset Value 17 CISTAS Pending Control Mode Interrupts Read R C 0 16 CISTA4 Interrupt acknowledge Write 15 CISTA3 On a read access these bits indicate the channels with pending control mode interrupts A 1 indicates a pending 14 CISTA2 interrupt 13 CISTA1 The interrupts are acknowledged by writing a 1 to the 12 CISTAO according bit 11 MISTAS Pending Match Interrupts Read R C 0 10 MISTA4 Interrupt acknowledge Write 9 MISTA3 On a read access these bits indicate the channels with pending match interrupts A 1 indicates a pending interrupt 8 MISTA2 The interrupts are acknowledged by writing a 1 to the 7 MISTA1 according bit 6 MISTAO 5 SISTA5 Pending SSI Interrupts Read R C 0 4 SISTA4 Interrupt acknowledge Write 3 SISTA3 On a read access these bits indicate the channels with pending SSI interrupts A 1 indicates a pending interrupt 2 SISTA2 The interrupts are acknowledged by writing a 1 to the 1 SISTA1 according bit 0 SISTAO Table 3 15 Interrupt Status Register 3 16 Test Register This register
30. ciu ta 39 6 3217 Jnpgt Modest ii 39 AA R NEI K 0e EEE E E E taeda cad ees EE EE E A dee dee dE 39 6 3 1 2 Direction ELE EEN 39 6 3 1 3 Up Down OoN ah AA EEEE TEA EEE E E AEAT 39 6 3 14 Quadrature Countian anien aa aa Di aa A lil Bt 40 6 3 2 Special CoUntModesS ocacion a a tenets a 40 03 21 Divide by N tii ta Dae eee de 40 6 3 2 2 Single Cycle TT 40 6 3 3 INdeX Control MOSS iria da la dla eh ed 41 63310 NO ECON Oli A bab aL 41 E e EN EX OY o ON Miu A a a E nO 41 0 3 3 37 LAtCh EE 42 E CN EE 42 E e Reset NEE 42 Gab Reference Modena Seet eh Eeselen eebe ef e 42 6 3 3 Auto Reference MOE tii dt at iaa E dba 43 6 3 3 9 Index Mode xiii id lada 43 6 34 Data Register LOCK ito da 44 6 4 Multiple Channel Read i cciscci cccdisvencesscncdesesseacnessenncnatcnsnscananctvescanacvasusnnuecastansuasasaseueastanseaatendecceie 44 6 5 MntervaleTime ties id A ida 45 6 6 Isolated 24V Digital Inputs oommccinncncnnnninncninnanncnnnncnnrnnacnn rra 45 6 7 SSl Counter Input Filtering cceeseecesseeeeeeeeeeeeeeeeeeeeeeeseeeseeeseeeseseeeeeseeeseaeseeseseaeseeeseaeseseseansensees 45 7 HARDWARE INTERFACE cccccsseccesseeeeeeeeceeeeeeeeseeeeeseeseseeeeneeseaseeseeseeseeeeesonees 46 7 1 Encoder Counter Input Wiring cccccessecceceseeeeeeeseeeeeeeeseeeseeeseesesesneeseseseaeeseseseaeseseseaeseseseanseeees 46 7 1 1 Termination Resistor DIP Gwitches a aaana a aa a aa ai 46 Tiz Singles Ended Teaia
31. e e eaa ee E ee lada 47 Z Differential Riets ee 48 7 2 Glock Outpt WINO E 48 7 3 Digital Input Characteristics lt 0 icc lt ccccseccccsecceeceesecdecdeanceeeesuaccee eaustie eensoeeeenacceaieanateseenaddetineractevensen 49 8 PIN ASSIGNMENT I O CONNECTOR ccsccceeseeeeeseeeeeeeeeeeneeeeeneeseeeeeseeeesseeees 50 8 1 Front Panel VO Connector iii ada 50 TPMC117 User Manual Issue 1 0 2 Page 5 of 51 List of Figures FIGURE T T i BLOCK DIAGRAM a conil a a a aiii 8 FIGURE 6 1 SSI TIMING EXAMPLE a 35 FIGURE 6 2 WIRING EXAMPLE CHANNEL 0 SSI INTERFACE CONTROLLER MODE 36 FIGURE 6 3 WIRING EXAMPLE CHANNEL 0 LISTEN ONLY MODE ccococccoccccnoncccnnnonononononcnnnnncannncn 37 FIGURE 6 4 QUADRATURE SIGNAL S oe teeter rete nnnnnn ee eee ae sete SAANA NAAA Mir Ania ERATO ENIKE ta 40 FIGURE 6 5 REFERENCE MODE PRELOAD ESAMPDLE eect t eee e tee ee teas sete nn nan ncnn ne ee tnaeeneees 43 FIGURE 41 INPUT WIRING sis igen ied tad ala adh Een ENEE eege See ativan 46 FIGURE 7 2 TERMINATION RESISTOR DIP SWITCHES ooo ee ee etter eer nn seta na nann cnn cnn ran cnn 46 FIGURE 7 3 SINGLE ENDED INPUT WIRING oo ee ee etre nono nc nono non n nn nn nan n cnn nn nan nn anna nnnnncnns 47 FIGURE 7 4 DIFFERENTIAL INPUT WIRING i eter ete corn cn cnn cnn nao nn nan nn tae nn tana anna nc nannins 48 FIGURE 7 5 CLOCK OUTPUT WIRING WITH OPTOCOUPLER INPUT ooocccccoccccnoncnononcnioncnononcnonananancnnn 48 FIGURE 7 6 CLOCK OUTPUT WIRIN
32. e only valid when the input mode is quadrature count They control the counter with the encoder index input in cooperation with a reference switch connected to the isolated 24V digital input An interrupt can be generated on a control mode event This is only available for the Load Latch Gate and Reset on modes Index Control Mode No Control Mode Interrupt generation No interrupt Load Mode Latch Mode Control mode event Reset Mode Gate Mode Gate closed Table 6 10 Index control mode interrupt generation 6 3 3 1 No I Control In this mode the l input is ignored 6 3 3 2 Load on I An event on the l input loads the counter with the content of the Counter Preload Register If the Single Cycle mode is active the event on the l input will start the counter The counter can also be preloaded by writing 1 to the Load Counter LCNT bit in the Counter Command Register This control mode can be used to establish a known reference position in a mechanical system Page 41 of 51 6 3 3 3 Latch on An event on the l input loads and locks the Data Register with the actual counter value see chapter Data Register Lock for details It will remain latched until the Data Register is read or the latch is released with the CDLT bit in the Status Register When a Latch on I event occurs while the Data Register Lock is still active the data in the Data Register will be retained and the Dat
33. e the clock s ground reference must be connected to the system ground which must be available somewhere in the chassis TPMC117 Absolute Encoder Figure 7 5 Clock Output Wiring with Optocoupler Input TPMC117 User Manual Issue 1 0 2 Page 48 of 51 TPMC117 Absolute Encoder System Ground Figure 7 6 Clock Output Wiring with Differential Receiver Input GND_l is an isolated input ground that can not be used as the clock output ground reference 7 3 Digital Input Characteristics The TPMC117 offers one digital 24V input per channel which is galvanically isolated by optocouplers A high performance input circuit ensures a defined switching point and polarization protection against confusing the pole The inputs are electronically debounced Each of the four digital 24V inputs can generate an interrupt triggered on rising or falling edge Depending on the selected reference mode the input can be used as general purpose input or as reference input Parameter Unit Typical Input isolation Optocoupler as galvanic isolation Input voltage V 24 Input current mA 4 2 at 24V input voltage Switching level V 12 min 7 5 max 14 Table 7 3 Digital Input Characteristics VCC DIN 24V O GDIN Figure 7 7 Digital Input Wiring TPMC117 User Manual Issue 1 0 2 Page 49 of 51 8 Pin Assignment I O Connector 8 1 Front Panel I O Connector The TPMC117 front panel I O connector is a
34. ed data after a control mode event See chapter Data Register Lock for details TPMC117 User Manual Issue 1 0 2 Page 16 of 51 3 5 Status Register The Status Register is divided into two parts bits 15 0 are dedicated for SSI status bits 31 16 are dedicated for Counter status Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Counter Status ololololololo 013158 Z 2 53 lt 2 5 o 5 QA F on 2 0 a Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSI Status x gt gt 00 0 0000 OJOJOJOJOJOJUJ EJB Bit Symbol Description Access Reset Value 31 24 Reserved always reads as 0 0 23 SGL Single Cycle active R 0 In Single Cycle counting mode this bit is set to 1 when the counter is active It is reset to 0 when the counter has counted down to zero 22 OVFL Data Register Latch Overflow R C 0 When a Latch Mode event occurs while the Data Register Lock is still active the data in the Data Register will be retained and this bit will be set to indicate that data was lost This bit must be reset by writing a 1 to this bit 21 DRL Data Register Latch R C 0 This bit is set to 1 when the Data Register is locked due to a Latch on l or a Multiple Channel Read This bit is cleared after a read access to the Data Register or by writing a 1 to this bit 20 DIR Count Direc
35. er Value Table 3 12 Interval Timer Data Register 3 13 Global Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved MCR Manual DIE o st oolololo Ele fr mee ale ee ee E E OLOJSESNI ONIN I NIN IN gq la 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Counter Preload Interface Control oa ess a Mar is XIXIX X ICS IC4 IC3 IC2 IC1 ICO gl ege geg Bit Symbol Description Access Reset Value 31 27 Reserved always reads as 0 0 26 MCRTR Multiple Channel Read Trigger W 0 By writing 1 to this bit a Multiple Channel Read is triggered the MCRTR bit on the same write access This is only valid for channels which are already enabled for a Multiple Channel Read Do not set the SLx bits and TPMC117 User Manual Issue 1 0 2 Page 22 of 51 25 MCRST Multiple Channel Read Status R C 0 This bit indicates pending Multiple Channel Read data When a SSI channel is enabled for Multiple Channel Read it takes time for the conversion to complete This bit indicates that the conversions of all enabled channels are complete 1 Multiple Channel Read Data is valid for all enabled channels 0 The Data Registers of all enabled channels have been read out To reset a multiple channel read sequence write 1 to this bit 24 ITRG Interval Timer as trigger for Multiple Channel Read
36. er data from the on board configuration EEPROM The configuration EEPROM contains the following configuration data e Address 0x00 to 0x27 PCI9030 PCI Configuration Register Values e Address 0x28 to 0x87 PCI9030 Local Configuration Register Values e Address 0x88 to OxFF Reserved See the PCI9030 Manual for more information Address Offset 0x00 0x02 0x04 0x06 0x08 Ox0A 0x0C Ox0E 0x00 0x0075 0x1498 0x0280 0x0000 0x1180 0x0000 s b 0x1498 0x10 0x0000 0x0040 0x0000 0x0100 0x4801 0x4801 0x0000 0x0000 0x20 0x0000 0x4C06 0x0000 0x0003 OxOFFF OxFFOO 0x0000 0x0000 0x30 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0001 0x40 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x50 0x4180 0x0020 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x60 0x0000 0x0000 0x0000 0x0081 0x0000 0x0000 0x0000 0x0000 0x70 0x0000 0x0000 0x0030 0x0041 0x0078 0x0000 0x0000 0x0240 0x80 0x0000 0x0000 0x0000 0x0000 OxFFFF OxFFFF OxFFFF OxFFFF 0x90 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxAO OxFFFF OxFFFF OxFFFF OXFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxBO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxXFFFF OxCO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxDO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxEO OxFFFF OxFFFF OxFFFF OXFFFF OxFFFF OxFFFF OxFFFF OxFFFF OXFO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OXFFFF
37. he Multiple Channel Read latches the enabled counter channels For SSI mode the Multiple Channel Read starts a conversion for the enabled SSI channels The data of counter channels is instantly available SSI channels need time for the conversion to complete To indicate that all data is available the MCRST bit in the Global Control Register will be set to 1 This bit will stay 1 until the Data Registers of all enabled channels were read Then it changes back to 0 To reset a Multiple Channel Read sequence beforehand write 1 to the MCRST bit SSI Counter SSI amp Counter Data availability When all channel Instantly SSI When all conversions are channel conversions complete are completed Counter Instantly Data availability MCRST 1 MCRST 1 MCRST 1 indication Counter data may already be read before MCRST 1 Table 6 12 Multiple Channel Read data availability Example Channels 1 3 are configured for SSI mode channels 4 6 are configured for counter mode Channels 1 4 and 6 are enabled for Multiple Channel Read A write to the MCRTR bit starts the Multiple Channel Read Channel 1 starts a conversion and the data of channels 4 and 6 are latched The data of the enabled counter channels is instantly available and can be read at once The SSI data is not available until MCRST is set to 1 When all enabled channels were read MCRST is reset to 0 TPMC11
38. inary Gray Code ZB Additional Zero Bit EO Even Odd Parity PAR Parity detection CR Table 6 4 SSI Listen only Setup TPMC117 User Manual Issue 1 0 2 Page 37 of 51 The clock rate setting in the Control Register is don t care the clock rate of the observed SSI interface will be detected automatically After the Control Register is set up the channel listens indicated by Busy 1 A data transfer is initiated by the observed SSI interface The positional data will be received and processed parity check gray to binary code conversion and the end of the data transfer is indicated with the deassertion of the Busy bit If enabled an interrupt is asserted and the positional data can be read in the Data Register Reading the Data Register will set the Busy bit to 1 and the channel is listening again Note that in this mode the clock rate setting in the Control Register is ignored the Clock Rate will be detected automatically Writes to the Data Register are also ignored for channels in this mode In case of a partial transmission a read error will be issued in the Status Register To detect read errors the width of the first SSI clock pulse is measured to detect the clock rate This clock rate is multiplied by 4 and used as the initial value for a watchdog timer Every new received bit resets the watchdog timer until either the programmed data word length is reached successful read or a
39. is based on two differential signal lines CLOCK and DATA The CLOCK line is an input the DATA line is an output of the absolute encoder su Ma eo SE CLOCK i tm DATA MSB Y msBa MSB 2 x LSB 1 LSB 7 E Parity Dn Dn 1 Dn 2 D1 DO Zero Bit Parity Bit opt opt T Clock Period n Number of Data Bits tm Recovery Time Figure 6 1 SSI Timing Example When not transmitting the clock and data lines are high To read out the positional data of an absolute encoder the controller transmits a pulse train on the CLOCK line The first falling edge of CLOCK O latches the positional data of the absolute encoder At the first rising edge of CLOCK the absolute encoder presents the most significant bit on the DATA line On each subsequent rising edge in the CLOCK pulse train the next bit in order is transmitted to the controller In addition to the data bits the absolute encoder can transmit a parity bit for error detection As an option a zero bit can be placed between the data and the parity bit After all bits are transmitted O the absolute encoder holds the data line low for 10 30us recovery time tm After that the absolute encoder is ready for a new transmission O A new transmission must not started before O The maximum achievable baud rate depends on the cable length Cables are assumed to be twisted pair and screened Cable length m Baud rate kHz lt
40. l Input IRQ Enable z e 3 3 Sl s e s s O0 O 0 0 0 0 0 H MW Ww Ww Ww ou uw i j jalalalalalalolo Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Control Mode IRQ Enable Match IRQ Enable SSI IRQ CO CN E o LO ks CH CN ke o wo ks CH CN o Z Z Z Z Z2Z2 2 2 1Z2 Z2 2 2 Z2 Z 2 Z 2 W j u pa pa oa fo a a 1 D OJOJO JO Z2 2 gt 2 2 gt 2 2 0 0 0 0 0 0 Bit Symbol Description Access Reset Value 31 25 Reserved always reads as 0 0 24 TIEN Interval Timer Interrupt R W 0 23 DIEN5 Enable 24V digital input Interrupt R W 0 22 DIEN4 1 Digital Input Interrupt enabled 91 DIEN3 0 Digital Input Interrupt disabled 7 An interrupt will be generated on an rising or falling edge 20 DIEN2 ofthe digital input 19 DIEN1 18 DIENO 17 CIEN5 Enable Control Mode Interrupt R W 0 16 CIEN4 1 Control Mode Interrupt enabled 15 CIEN3 ae ee gulls Scena cane l 14 CIENZ n interrupt will be generated on a control mode event 13 CIEN1 12 CIENO 11 MIEN5 Enable Match Interrupt R W 0 10 MIEN4 1 Counter Match Interrupt enabled 9 MIEN3 0 Counter Match Interrupt disabled An interrupt will be generated when the counter value 8 MIEN2 matches the Counter Compare Register 7 MIEN1 6 MIENO TPMC117 User Manual Issue 1 0 2 Page 24 of 51 Bit Symbol Description Access Reset Value 5 SIEN5 Enable SSI Interrupt R W 0 4 SIEN4 1 SSI Data Valid Interrupt enabled 3 SIEN3 0
41. omoococinicncccnnnoncccinnncnccnnnncnnrnnnc rra 21 3 11 interval Timer Preload Register ooommmnccionnnncnnnnnccccnnancccccnnannn cnn crac 21 3 12Interval Timer Data Register onnnccconnccccnnniccccnnancnccnnnnnnccnnncnn cnn recrean 22 3 13Global Control Register onmnccconnncccnnnanncccnnancnnnnanncrnnnc cnn 22 3 14Interrupt Enable Register ooononcccinnicnccnnnancccnnncnncnnancr cnc 24 3 15Interrupt Status Register o nocoonnncccnnnicccccnnanccnnnnncn crac cnn 25 310 rest IG 26 4 PCI9030 TARGET CHIP eeaeee A RR 28 4 1 PCI Configuration Registers PCR sssssusseenunsuunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn na 28 411 PCI9030 Header ccc nid a ie aden eae deen el ae aged 28 4 1 2 PCI Base Address Initialization 0 00 cceceee cence ee eneeeee erence eeeaeeeeeeneeesesiaeeeeseeneeeeneaes 29 4 2 Local Configuration Register LOR cccccccessenneeesenneeeeeeeeeeeeeneeeeeeeeeeeeseeeeeeaseeneeeaseeneeenseenenens 30 4 3 Configuration EEPROM coords di 31 4 4 Local Software Reset icono 32 5 CONFIGURATION HINTS tia 33 AA le E EE 33 6 FUNCTIONAL DESCRIPTION cooocccccccccoooocccccccccnnnnnnnnanannnnnnnnnnnnnnnannnnnnrnrnnnnnnnaanannnnnnns 35 6 1 SSI Short Description iii cd 35 6 2 SSI Mode a da 36 6 2 1 Standard SSI Interface Controller Mode 36 6 22 SSI Listen Only MOJE uc li ia 37 6 2 3 SSI Mode behavior differences AA 38 TPMC117 User Manual Issue 1 0 2 Page 4 of 51 6 3 Counter Mode
42. on Date Preliminary Issue December 2005 1 0 First Issue September 2006 1 0 1 New notation for HW Engineering Documentation Releases February 2009 1 0 2 Added 7 2 Clock Output Wiring June 2010 TPMC117 User Manual Issue 1 0 2 Page 3 of 51 Table of Contents 1 PRODUCT DESCRIP TION tis eessen iii cacas 8 2 TECHNICAL SPECIFICATION ere 10 3 LOCAL SPACE ADDRESSING cccccccccoooccccnccccnnnnnnnnnnnnnnnennnnnnnnnannnnnnrrrrrnnnnanananarenne 11 3 1 PCI9030 Local Space Configuration ccccssccceeseneeeeseeeeeeeeeenseeeeeeeseeeseeeseeeseaesesesenseeeseenseeenees 11 3 2 Local Register Address Space oocommncccconocicinnancncinnancnnncnnnnc nn renacer 12 3 3 Control REGIStCM 2 ices nica unea NA n N ENEE ENEE ENEE SEENEN EENS canas eo 13 KREE EE 16 34 1 Data Register in SSI Modes umd tidad 16 3 4 2 Data Register in Counter Mode oooonccccnocccccononcccccononcncnonononcnononcncnononnncnnnnnnnnn nana ncnnnanancccnnn 16 3 5 Status Register EE 17 3 6 Counter Preload Register aii cccsccccccccccetccesstteceeestteceeactteeceeeettnceeestinceeasteeeeeestineeeestinseeesttteceessteeseestee 19 3 7 Counter Compare Register cccessecceceeseeeeeeeseeeeeeeseeeseeeseeesesesnaeseeeseaesesesseaesesesaeseeeseanseseneaneeenaes 19 3 8 Counter Command Register cceecccesseneeeseeeeeesenenseeesseeeseeeseeeseeeseeeseseseaeseseneeeseseseeeseeeeseenseenees 19 3 9 Digital Input e LE EE 20 3 10Interval Timer Control Register oo
43. onding reference input is described as an example Two different start positions 1a and 1b are shown Position 1a Direction is forward and the reference input is active The host software must move into the area where the reference input is inactive Now the direction must be changed The next index pulse after entering the area with reference input active triggers the preload function for the counter TPMC117 User Manual Issue 1 0 2 Page 42 of 51 Position 1b Direction is backwards and the reference input is inactive The host software must move further backwards and after entering the area with reference input active the next index pulse triggers the preload function for the counter Encoder Motion Area Forward Reference Switching Point Backwards ee E Reference Switch Active l Inactive Index Signal Counter Preload so s2 s1 1b Figure 6 5 Reference mode preload example A correct execution of the reference function can be monitored in the Control Register After successful execution the mode is reset from Reference Mode to No l Control Mode 6 3 3 7 Auto Reference Mode This mode is the automation of the Reference Mode Every time the reference switching point and a following index pulse are crossed during backward direction a new preload is generated In Auto Reference Mode there is no change of the Index Control Mode in the Control Register 6 3 3 8 Index Mode In this mode the reference input is no
44. per channel Input Levels RS422 differential and TTL single ended ESD Protection 15kV Human Body Model 8kV IEC 1000 4 2 Contact Discharge 15kV IEC 1000 4 2 Air Gap Discharge Number of Isolated Digital Inputs 6 digital inputs reference input or general purpose input depending on mode Maximum Input Frequency 5 MHz Input Voltage 24V DC typical Input Current 4 2mA 24V input voltage Input Switching Level 12V typical 7 5V minimum 14V maximum Interval Timer Programmable with timing intervals up to 65ms UO Connector HD68 SCSI 3 type connector e g AMP 787082 Physical Data Power Requirements 160 mA typical 5V DC 10 mA typical 3 3V DC Temperature Range Operating 40 C to 85 C Storage 40 C to 85 C MTBF 330 000 h Humidity 5 95 non condensing Weight 779 TPMC117 User Manual Issue 1 0 2 Table 2 1 Technical Specification Page 10 of 51 3 Local Space Addressing 3 1 PCI9030 Local Space Configuration The local on board addressable regions are accessed from the PCI side by using the PCI9030 local spaces PCI9030 PCI9030 PCI Size Port Endian Description Local PCI Base Address Space Byte Width Mode Space OffsetinPci Mapping Bit Configuration Space 0 2 0x18 MEM 256 32 BIG Local Register Address Space 1 3 0x1C Not Used 2 4 0x20 Not Used 3
45. read error are The number of data bits set in the control register does not match the actual size of the received transmission Only a partial transmission was received this could happen when the mode is switched and a transmission is in progress on the observed SSl interface PRY Parity Error 1 Parity Error at the last data transmission 0 No Parity Error at the last data transmission During a transmission the parity error bit is not valid The parity error status is updated only if the parity enable bit of the corresponding channel is set to 1 Otherwise the parity status is read as 0 BSY Busy Bit 0 Data Ready set after every completed transmission even if a parity or a read error was issued In Standard SSI Interface Controller mode Busy Bit 1 indicates a transmission in progress In Listen only Mode the Busy Bit is set to 1 when a transmission is in progress It is set to 0 when transmission was received and stays 0 until the data word was read Table 3 5 SSI Status Register TPMC117 User Manual Issue 1 0 2 Page 18 of 51 3 6 Counter Preload Register Bit Symbol Description Access Reset Value 31 0 Counter Preload Register R W 0 The value of this register can be loaded into the counter by Setting bit 1 LCNT of the Counter Command Register An impulse on the l input when the Load on l mode is active Automatically
46. rogrammable data word length from 1 bit to 32 bit In Listen only Mode the channel listens to an existing SSI interface to observe its data transfer It takes both the SSI clock and data as inputs In Listen only Mode the channel also has a programmable data word length from 1 bit to 32 bit the SSI clock rate of the observed SSI interface can be in the range of 1us to 15us In both modes the data word can be encoded in Binary or in Gray code and with odd even or no parity The 32 bit incremental encoder counter is a preloadable up and down counter The counter is programmable for single double and quadruple analysis of the encoder signals In conjunction with the isolated 24V digital inputs it provides the possibility of automatic preload of the counter whenever the motion system passes a reference position The 32 bit general purpose preloadable up and down counter can be fed with an internal clock or with external signals Both counter modes offer a 32 bit preload register a 32 bit compare register and various count modes 6 Channels 3 isolated inputs SSI data amp counter modes 1 isolated 24V digital input 1 SSI clock output Local Control Logic Figure 1 1 Block Diagram A Multiple Channel Read function latches the actual values of all enabled channels whose values can then be read without interfering with normal function In addition the TPMC117 provides a 16 bit down counter with preload register
47. ructrnetrntrnstrnnetrnetrnetrnecrnsenenes 38 TABLE 6 67 INPUT MOES ee a dali EE e 39 TABLE 6 7 3 CLOCK PRESOA ER ui ad ariadna nlidiiae E 39 TABLE 6 8 COUNT DIRECTIONS esco cocinas cornonacadaranas daran edi a aa cd aii 39 TABLE 6 9 INDEX CONTROL MODE EVENT 41 TABLE 6 10 INDEX CONTROL MODE INTERRUPT GENERATION 41 TABLE 6 1 GATE MODES ciudad danesa 42 TABLE 6 12 MULTIPLE CHANNEL READ DATA AVAIL ABILTITY nn rnnnnn cnn 44 TABLE 6 13 INTERVAL TIMER CLOCK PERIODS 0 cette eee ete cnn cnn nan rca rancia nan nn nan nnannn nan 45 TABLE 7 1 DIP SWITCH SIGNAL ASSIGNMENT o oo eee eee ete etre nn terre teas anno carne 47 TABLE 7 2 DIP SWITCH SETTINGS orcii duina t eee era rere ee nner eta rca nan nn 47 TABLE 7 3 DIGITAL INPUT CHARACTERISTICS 0000 e terete eetene rete n narran rn rn 49 TABLE 8 1 PIN ASSIGNMENT FRONT I O CONNECTION oe eec ieee cee cece eter teeta nnnann nn nn nnn nan nnnnn cnn 51 TPMC117 Us er Manual Issue 1 0 2 Page 7 of 51 1 Product Description The TPMC117 is a standard single width 32 bit PMC module and offers six independent channels Each of these channels can operate as a standard SSI interface controller in a SSI Listen only Mode as an incremental encoder or general purpose counter The standard SSI interface controller outputs a clock burst to the absolute encoder and receives the returned positional data The SSI interface controller operates with a programmable clock rate from jus to 15us and p
48. s loaded with the content of the preload register every time the counter creates a borrow or a carry 6 3 2 2 Single Cycle The counter is enabled in the Control Register and will start on following events e A manual preload or reset in the Counter Command Register e A manual counter preload in the Global Control Register e A control mode event in Load on I or Reset on I mode The counter will stop when it creates a borrow or a carry TPMC117 User Manual Issue 1 0 2 Page 40 of 51 6 3 3 Index Control Modes The Index Control Mode determines how events on the l input are interpreted With the exception of the Gate on I mode all modes react on a level change on the l input Due to the digital input filtering a change in the input level is only detected when the input line is stable for at least 100ns The following table gives an overview of the index control mode events Index Control Mode Polarity high active low active POL 0 POL 1 No I Control S Load on Rising edge Falling edge Latch on Rising edge Falling edge Gate on High level Low Level Reset on Rising edge Falling edge Reference Mode Rising edge Falling edge Auto Reference Mode Rising edge Falling edge Index Mode Rising edge Falling edge TPMC117 User Manual Issue 1 0 2 Table 6 9 Index Control Mode events The control modes Reference Mode Auto Reference Mode and Index Mode ar
49. selected counter reference mode the input can be used as a general purpose input or as a reference input 6 7 SSI Counter Input Filtering To avoid false counts caused by noisy input signals the A B and l inputs are digitally filtered A change in the input level is only detected when the input line is stable for at least 100ns TPMC117 User Manual Issue 1 0 2 Page 45 of 51 7 Hardware Interface 7 1 Encoder Counter Input Wiring The following schematic shows the principle input wiring for one encoder signal Figure 7 1 Input Wiring The 1200 termination resistor is switchable via DIP switches For single ended TTL signals the switch must be left open default for differential RS422 signals the switch should be closed 7 1 1 Termination Resistor DIP Switches The termination DIP switches are located near the I O connector refer to the following figure PCI9030 Figure 7 2 Termination Resistor DIP Switches TPMC117 User Manual Issue 1 0 2 Page 46 of 51 Each channel has a dedicated DIP switch for its input signals Switch Signal 1 ENC_A 2 ENC_B 3 ENC_ 4 not used Table 7 1 DIP Switch Signal Assignment Switch Setting Termination ON Enabled OFF Disabled
50. ster 5 32 0x80 Status Register 5 32 0x84 Counter Preload Register 5 32 0x88 Counter Compare Register 5 32 0x8C Counter Command Register 5 32 0x90 Digital Input Register 32 0x94 Interval Timer Control Register 32 0x98 Interval Timer Preload Register 32 0x9C Interval Timer Data Register 32 OxA0 Global Control Register 32 OxA4 Interrupt Enable Register 32 OxA8 Interrupt Status Register 32 OxAC Test Register 32 Table 3 2 Local Register Address Space 3 3 Control Register The Control Register is divided into two parts bits 15 0 are dedicated for SSI control bits 31 16 are dedicated for Counter control Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Counter Setup 0 0 0 POL ICM SCM CLKDIV INPUT Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSI Setup tia a D dE Bc alajal o o O TPMC117 User Manual Issue 1 0 2 Page 13 of 51 Bit Symbol Description Access Reset Value 31 29 Reserved always reads as 0 0 28 26 POL A B I Polarity R W 000 2 0 The Input Polarity Control can be used to adapt the input to the input source polarity Bit Input Polarity 26 A 0 high active 1 low active 27 B 0 high active 1 low active 28 0 high active 1 low active 25 23 ICM Index Control Mode R W 000 2 0 The Index
51. t used Only the index impulse produces a counter preload After setting this mode the next occurrence of the index signal independent from direction will preload the counter A correct execution of this preload function can be monitored in the Control Register After successful execution the mode is reset from Index Mode to No l Control Mode TPMC117 User Manual Issue 1 0 2 Page 43 of 51 6 3 4 Data Register Lock The Data Register is loaded and locked with the actual counter value on following conditions e Latch in Mode e Multiple channel read The Data Register is locked until following conditions are met e Aread access to the Data Register e A write 1 to the RCNT bit in the Counter Command Register Until the lock is released the Data Register will not load again The status of the Data Register lock can be monitored in the Status Register DRL When the lock is released the Data Register retains its value until it is loaded again When a Multiple channel read is issued or a Latch Mode event occurs while a Data Register is locked the Data Register content will be retained and the Data Register Lock Overflow OVFL will be set to indicate that data was lost 6 4 Multiple Channel Read The Multiple Channel Read option is enabled in the Global Control Register A Multiple Channel Read is triggered by writing 1 to the MCRTR bit Alternatively the interval timer can be used to trigger a multiple channel read For Counter mode t
52. timeout occurs read error In case of a timeout the Read Error bit is set to 1 Depending on the BREAK setting in the Control Register the channel ignores a read error and continues listening or it stops to listen Reasons for a read error are e The number of data bits set in the control register does not match the actual size of the received transmission e Only a partial transmission was monitored this could happen when the mode is switched and a transmission is in progress on the observed SSI interface In the case that a SSI communication is in progress when the mode is switched to Listen only a read error will be issued for the first reading 6 2 3 SSI Mode behavior differences Standard SSI Interface Mode Listen only Mode Control Register Control Register SSI bits fully used Bit 14 MODE is set to 0 Clock rate setting in Control Register is don t care Bit 14 MODE is set to 1 Status Register Busy bit 1 during transmission Busy bit 1 during transmission or after the data word was read channel is listening again Read Error Bit Read Error bit is always 0 Read Error bit is set to 1 ona erroneous transmission Connections Connect external SSI data outputs to TPMC117 DATA inputs Connect external SSI Clock inputs to TPMC117 CLK OUT outputs Connect external SSI data to TPMC117 DATA inputs Connect
53. tion R 0 This bit indicates the counting direction of the counter 1 indicates up 0 indicates down In the Up Down Count mode this bit indicates the direction at the last count In the Direction Count mode this bit corresponds to the l input 19 SGN Sign R 0 The Sign bit is set to 1 when the counter overflows and is set to 0 when the counter underflows After reset or power up this bit should be considered as don t care until the first Carry or Borrow occurred TPMC117 User Manual Issue 1 0 2 Page 17 of 51 Bit Symbol Description Access Reset Value 18 MAT Match This bit is set to 1 when the counter value matches the value of the Counter Compare Register This bit must be reset by writing a 1 to this bit R C 17 CRY Carry This bit is set to 1 when the counter changes from OxFFFFFFFF to 0x00000000 This bit must be reset by writing a 1 to this bit R C 16 BOR Borrow This bit is set to 1 when the counter changes from 0x00000000 to OxFFFFFFFF This bit must be reset by writing a 1 to this bit R C 15 3 Reserved always reads as 0 RER Read Error 1 Data is invalid because of an error during the last transmission 0 Data OK This bit is only valid for channels in Listen only mode For channels in Standard SSI Interface Controller mode this bit will always read 0 Reasons for a
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