parallel interfacing to dsp processors
Contents
1. A v Figure 8 15 RFS DR tt RXn RECEIVE DATA REGISTER RECEIVE SHIFT REGISTER Polarity of TFS and RFS is software programmable ADSP 21xx FAMILY SERIAL PORT FEATURES Externally Generated Serial Data Words of 3 to 16 Bits Supported Automatically Generated Processor Interrupts Separate Transmit and Receive Sections for Each Port Double Buffered Transmit and Receive Registers Serial Clock Can be Internally or Externally Generated Transmit and Receive Frame Sync Signals Can be Internally or E Hardware Companding Requires no Software Overhead Figure 8 16 8 13 INTERFACING TO DSPS In the receiving portion of the serial port the receive frame sync RFS signal initiates reception The serial receive data DR from the external device ADC is transferred into the receive shift register one bit at a time The negative going edge of the serial clock SCLK is used to clock the serial data from the external device into the receive shift register When a complete word has been received it is written to the receive data register RX and the receive interrupt for that serial port is generated The receive data register is then read by the processor Writing to the transmit data register readies the serial port for transmission The transmit frame sync TFS signal initiates transmission The value in the transmit data register TX is then written to the internal transmit shift register The2. I O memory spaces You can specify 0 to 15 wait states for each parallel memory interface Each wait state added increases the allowable external data memory access time by an amount equal to the processor clock period 13 3ns for the ADSP 2189M operating at 75MHz In this example the data memory address DMS and RD lines are all held stable for an additional amount of time equal to the duration of the wait states AD7854 AD7854L is a 12 bit 200 100kSPS ADC which operates in the parallel mode It operates a single to 5 5V supply and dissipates only 5 5mW 3V supply AD7854L An automatic power down after conversion feature reduces this to 650uW 8 4 INTERFACING TO DSPS A functional block diagram of the AD7854 AD7854L is shown in Figure 8 5 The AD7854 AD7854L uses a successive approximation architecture which is based on a charge redistribution switched capacitor DAC A calibration mode removes offset and gain errors The key interface timing specifications for the AD7854 AD7854L and the ADSP 2189M are compared in Figure 8 6 Specifications for the ADSP 2189M are given for a clock frequency of 75MHz Examining the timing specifications shown in Figure 8 6 reveals that for the timing between the devices to be compatible 5 software wait states must be programmed into the ADSP 2189M This increases tgpp to 68 15ns which is greater than the data access time of the AD7854 AD7854L tg 50ns max The read pulse tpp
3. data in the transmit shift register is sent to the peripheral device DAC one bit at a time and the positive going edge of the serial clock SCLK is used to clock the serial transmit data DT into the external device When the first bit has been transferred the serial port generates the transmit interrupt The transmit data register can then be written with new data even though the transmission of the previous data is not complete In the normal framing mode the frame sync signal RFS or TFS is checked at the falling edge of SCLK If the framing signal is asserted data is available transmit mode or latched receive mode on the next falling edge of SCLK The framing signal is not checked again until the word has been transmitted or received In the alternate framing mode the framing signal is asserted in the same SCLK cycle as the first bit of a word The data bits are latched on the falling edge of SCLK but the framing signal is checked only on the first bit Internally generated framing signals remain asserted for the length of the serial word The alternate framing mode of the serial port in the ADSP 21xx is normally used to receive data from ADCs and transmit data to DACs The serial ports of the ADSP 21xx family are extremely versatile The TFS RFS or SCLK signals be generated from the ADSP 21xx clock master mode or generated externally slave mode The polarity of these signals can be reversed with software thereby allo
4. how the DSP processor reads data from a memory mapped peripheral the ADC and how the DSP processor writes data to a memory mapped peripheral the DAC We will first consider some general timing requirements for reading and writing data It should be noted that the same concepts presented here regarding ADCs and DACs apply equally when reading and writing from to external memory A block diagram of a typical parallel DSP interface to an external ADC is shown in Figure 8 1 This diagram has been greatly simplified to show only those signals associated with reading data from an external memory mapped peripheral device The timing diagram for the ADSP 21xx read cycle is shown in Figure 8 2 In this example it is assumed that the ADC is sampling at a continuous rate which is controlled by the external sampling clock not the internal DSP clock Using a separate clock for the ADC is the preferred method since the DSP clock may be noisy and introduce jitter in the ADC sampling process thereby increasing the noise level Assertion of the sampling clock at the ADC convert start input initiates the conversion process step 1 The leading or trailing edge of this pulse causes the internal ADC sample and hold to switch from the sampling mode to the hold mode so that the conversion process can take place When the conversion is complete the conversion complete output of the ADC is asserted step 2 The read process thus begins when this signal is applie
5. is shown in Figure 8 21 Power dissipation on a supply is 690uW A power down feature reduces this to 0 15uW Total harmonic distortion is greater than 70dB below full scale for a 10kHz output The references for the two DACs are derived from two reference pins one per DAC The reference inputs may be configured as buffered or unbuffered inputs The outputs of both DACs may be updated simultaneously using the asynchronous LDAC input The device contains a power on reset circuit that ensures that the DAC outputs power up to OV and remain there until a valid write takes place to the device 8 17 INTERFACING TO DSPS AD5322 12 100kSPS DUAL DAC VREFA ON AD5322 DAC STRING REGISTERA DACA POWER DOWN LOGIC VouTA INTERFACE LOGIC INPUT REGISTER B STRING DAC ne VouTB RESISTOR NETWORK LDAC GND VREFB Figure 8 21 Data is normally input to the AD5322 via the SCLK DIN and SYNC pins from the serial port of the DSP When the SYNC signal goes low the input shift register is enabled Data is transferred into the AD5322 on the falling edges of the following 16 clocks A typical interface between the ADSP 2189M and the 5322 is shown in Figure 8 22 Notice that the clocks to the AD5322 are generated from the ADSP 2189M clock It is also possible to generate the SCLK and SYNC signals externally to the AD5322 and use the
6. 4 15 Steven W Smith The Scientist Engineer s Guide to Digital Signal Processing Second Edition 1999 California Technical Publishing P O Box 502407 San Diego CA 92150 Also available for free download at lhttp www dspguide com or http www analog com C Britton Rorabaugh DSP Primer McGraw Hill 1999 Richard J Higgins Digital Signal Processing in VLSI Prentice Hall 1990 DSP Designer s Reference DSP Solutions CDROM Analog Devices 1999 DSP Navigators Interactive Tutorials about Analog Devices DSP Architectures Available for ADSP 218x family and SHARC family http www analog com industry dsp training index html Navigator General DSP Training and Workshops http www analog com industry dsp training The following DSP Reference Manuals and documentation are available for free download from http www analog com industry dsp tech_docs html ADSP 2100 Family Users Manual 3 4 Edition Sept 1995 ADSP 2100 Family EZ Tools Manual ADSP 2100 EZ KIT Lite Reference Manual Using the ADSP 2100 Family Vol 1 Vol 2 ADSP 2106x SHARC User s Manual 244 Edition July 1996 ADSP 2106x SHARC EZ KIT Lite Manual ADSP 21065L SHARC User s Manual Sept 1 1998 ADSP 21065L SHARC EZ LAB User s Manual ADSP 21160 SHARC DSP Hardware Reference 8 25 INTERFACING TO DSPS 8 26
7. EGISTER Y UY SM1 SM2 SYNC DIN DOUT SCLK POLARITY Figure 8 18 AD7853L SERIAL ADC OUTPUT TIMING 3V SUPPLY SCLK 1 8MHz SYNC O P 330 5 THREE STATE ned 5 55 11 55 DBO THREE STATE DOUT O P 556ns 226ns 1 Figure 8 19 8 16 INTERFACING TO DSPS Figure 8 20 shows the AD7853L interfaced to the ADSP 2189M connected in a mode to transmit data from the ADC to the DSP alternate master mode The AD7853 AD7853L contains internal registers which can be accessed by writing from the DSP to the ADC via the serial port These registers are used to set various modes in the AD7853 AD7853L as well as to initiate the calibration routines These connections are not shown in the diagram AD7853 AD7853L SERIAL ADC INTERFACE TO ADSP 2189M CLOCK CLKIN INPUT AD7853 4MHz 1 8MHz max AD7853L ADC ADSP 2189M 75MHz DSP SAMPLING CLOCK CONVST OPTIONAL SCLK SYNC DOUT SERIAL PORT Figure 8 20 SERIAL DAC TO DSP INTERFACE Interfacing serial input DACs to the serial ports of DSPs such as the ADSP 21xx family is also relatively straightforward and similar to the previous discussion regarding serial output ADCs The details will not be repeated here but a simple interface example will be shown The 5322 is a 12 bit 100kSPS dual DAC with a serial input interface It operates on a single 2 5V to 5 5V supply and a block diagram
8. INTERFACING TO DSPS SECTION 8 INTERFACING TO DSPs Parallel Interfacing to DSP Processors Reading Data From Memory Mapped Peripheral ADCs Parallel Interfacing to DSP Processors Writing Data to Memory Mapped DACs Serial Interfacing to DSP Processors Interfacing I O Ports Analog Front Ends and Codecs to DSPs DSP System Interface INTERFACING TO DSPS 8 b INTERFACING TO DSPS SECTION 8 INTERFACING TO DSPs Walt Kester Dan King INTRODUCTION As the technology in the rapidly growing field of mixed signal processing evolves more highly integrated DSP products are being introduced such as the ADSP 21ESP202 which contain on chip ADCs and DACs as well as the DSP thereby eliminating most component level interface problems Stand alone ADCs and DACs are now available with interfaces especially designed for DSP chips thereby minimizing or eliminating external interface support or glue logic High performance sigma delta ADCs and DACs are currently available in the same package called a CODEC or COder DECcoder such as the AD73311 and AD73322 These products are also designed to require minimum glue logic when interfacing to the most common DSP chips This section discusses the various data transfer and timing issues associated with the various interfaces PARALLEL INTERFACING TO DSP PROCESSORS READING DATA FROM MEMORY MAPPED PERIPHERAL ADCS Interfacing an ADC or a DAC to a fast DSP parallel requires an understanding of
9. able or read The rising edge of the RD signal is used to clock the data on the data bus into the DSP processor step 8 After the rising edge of the RD signal the data on the data bus must remain valid for tppy ns the data hold time In the case of most members of the ADSP 21xx family this specification value is Ons The key timing requirements for the peripheral device are shown in Figure 8 3 Values are given for the ADSP 2189M DSP operating at 75MHz ADC TO ADSP 21xx FAMILY PARALLEL INTERFACE ADSP 21xx 3 F O ADC MEMORY 0 13 CONVERT START ADDRESS BUS DATA MEMORY ___ SELECT DMS CHIP SELECT PROCESSOR INTERRUPT ipa CONVERSION REQUEST COMPLETE MEMORY READ RD OUTPUT ENABLE MEMORY DATA BUS OUTPUT DATA Figure 8 1 8 2 INTERFACING TO DSPS ADSP 21xx FAMILY MEMORY READ TIMING DMS PMS IOMS CMS Figure 8 2 PARALLEL PERIPHERAL DEVICE READ INTERFACE KEY REQUIREMENTS E Peripheral Device Data Outputs Must Be Three State Compatible Address Decode Delay Peripheral Chip Select Setup Time Must Less Than Address and Memory Select Setup Time tasr 0 325ns min for ADSP 2189M E For Zero Wait State Access the Time from Negative Going Edge of Read Signal RD to Output Data Valid Must be Less than tppp 1 65ns max for ADSP 2189M Operating at 75MHz or Software Wait States Must be Added or Processor Clock Frequency Reduced Output Data from Peripheral mus
10. as or where SPORT power down is not required it can be permanently strapped high using a suitable pull up resistor The RESET pin may be connected to the system hardware reset or it may be controlled with another flag bit In the program mode data is transferred from the DSP to the AD73322 control registers to set up the device for desired operation Once the device has been configured by programming the correct settings to the various control registers the device may exit the program mode and enter the data mode The dual ADC data is transmitted to the DSP in two blocks of 16 bit words Similarly the dual DAC data is transmitted from the DSP to the AD73322 in two blocks of 16 bit words Simplified interface timing is also shown in Figure 8 24 8 20 INTERFACING TO DSPS AD73322 INTERFACE TO ADSP 218x SERIES DATA TRANSFER MODE TFS SDIFS CLOCK 16 384MHz T DI 21 ADSP 218x CODEC DSP SCLK SDO SAMPLE WORD DEVICE SAMPLE WORD DEVICE SDIFS SDI DAC DATA WORD DEVICE 2 DAC DATA WORD DEVICE 1 XXX Figure 8 24 The AD73422 is the first product in the dspConverter family of products which integrate a dual analog front end AD73322 and a DSP 52MIPS ADSP 2185L 86L The entire functionality of the dual channel CODEC and the DSP fits into a small 119 ball 14mm by 22mm plastic ball grid array PBGA package The obvious advantage is the saving of circ
11. d to the processor interrupt request line IRQ of the DSP The processor then places the address of the peripheral initiating the 8 1 INTERFACING TO DSPS interrupt request the ADC on the memory address bus AO A18 step 3 At the same time the processor asserts a memory select line DMS is shown here step 4 The two internal address buses of the ADSP 21xx program memory address bus and data memory address bus share a single external address bus and the two internal data buses program memory data bus and data memory data bus share a single external data bus The boot memory select BMS data memory select DMS program memory select PMS and input output memory select IOMS signals indicate which memory space the external buses are being used for These signals are typically used to enable an external address decoder as shown in Figure 8 1 The output of the address decoder drives the chip select input of the peripheral device step 5 The memory read RD is asserted tasg ns after the DMS line is asserted step 6 The sum of the address decode delay plus the peripheral chip select setup time should be less than in order to take full advantage of the RD low time The RD line remains low for ns The memory read signal is used to enable the three state parallel data outputs of the peripheral device step 7 The RD line is connected to the appropriate pin on the peripheral device usually called output en
12. distribution switched capacitor DAC A calibration feature removes gain and offset errors A block diagram of the device is shown in Figure 8 18 The AD7853 operates on a 4MHz maximum external clock frequency The AD7853L operates on 1 8MHz maximum external clock frequency The timing diagram for AD78538L is shown in Figure 8 19 The AD7853 AD7853L has modes which configure the SYNC and SCLK as inputs or outputs In the example shown here they are generated by the AD78538L The AD7853L serial clock operates at a maximum frequency of 1 8 556ns period The data bits valid 330ns after the positive going edges of SCLK This allows a setup time of approximately 330ns minimum before the negative going edges of SCLK easily meeting the ADSP 2189 4ns requirement The hold time after the negative going edge of SCLK is approximately 226ns again easily meeting the ADSP 2189M ns tgcy timing requirement These simple calculations show that the data and RFS setup and hold requirements of the ADSP 2189M are met with considerable margin 8 15 INTERFACING TO DSPS AD7853 AD7853L 3V SINGLE SUPPLY 12 200 100kSPS SERIAL OUTPUT ADC AVpp AGND AGND AD7853L DVpp 2 5V REFERENCE REF jy REF CHARGE CLKIN Crary REDISTRIBUTION DAC O CONVST SAR ADC CONTROL gt BUSY CALIBRATION CAL MEMORY SLEEP AND CONTROLLER SERIAL INTERFACE CONTROL R
13. e AD5340 is also met by adding two wait states A simplified interface diagram for the two devices is shown in Figure 8 14 Parallel interfaces with other DSP processors can be designed in a similar manner by carefully examining the timing specifications for all appropriate signals for each device INTERFACING TO DSPS AD5340 DAC PARALLEL INTERFACE TO ADSP 2189M SAMPLING CLOCK ADSP 2189M AD5340 75MHz DAC LDAC Notes 2 Software Wait States Sampling clock may come from DSP Figure 8 14 SERIAL INTERFACING TO DSP PROCESSORS DSP processors which have serial ports such as the ADSP 21xx family provide a simple interface to peripheral ADCs and DACs Use of the serial port eliminates the need for using large parallel buses to connect the ADCs and DACs to the DSP In order to understand serial data transfer better we will first examine the serial port operation of the ADSP 21xx series A block diagram of one of the two serial ports of the ADSP 21xx is shown in Figure 8 15 The Transmit TX and Receive RX registers are identified by name in the ADSP 21xx assembly language and are not memory mapped 8 12 INTERFACING TO DSPS ADSP 21xx FAMILY SERIAL PORT BLOCK DIAGRAM 16 TXn TRANSMIT DATA REGISTER TRANSMIT SHIFT REGISTER DMD BUS J a COMPANDING HARDWARE H LAW A LAW SERIAL CONTROL 16 INTERNAL SERIAL CLOCK GEN TFS SCLK
14. e two devices are compared in Figure 8 13 Specifications for the ADSP 2189M are given for a clock frequency of 75MHz AD5340 12 BIT 100kSPS PARALLEL INPUT DAC BUF GAIN cs WR CLR 8 10 POWER ON RESET INTERFACE LOGIC INPUT REGISTER A VREF DAC REGISTER A A Figure 8 12 INTERFACING TO DSPS ADSP 2189M AND AD5340 PARALLEL WRITE INTERFACE TIMING SPECIFICATIONS ADSP 2189M PROCESSOR 75MHz AD5340 DAC tasw Address and Data Memory ty cS to WR Setup Time Select Setup Before WR Low Ons 0 325ns min twp WR Pulse Width WR Pulse Width 3 65ns Wait States 13 3ns min 20ns 30 25ns min tpw Data Setup Before WR High t4 Data Valid to WR Setup Time 2 65ns Wait States x 13 3ns min 5ns 29 25ns min Data Hold After WR High t Data Valid to WR Hold Time 2 325ns min 4 5ns NOTE Adding 2 wait states to the ADSP 2189M increases twp to 30 25ns and tpw to 29 25ns which is greater than 4 20ns and t 5ns respectively Figure 8 13 Examining the timing specifications shown in Figure 8 13 reveals that for the timing between the devices to be compatible two software wait states must be programmed into the ADSP 2189M This increases the width of WR to 30 25ns which is greater than the minimum required AD5340 write pulse width 20ns The data setup time of 5ns for th
15. eady to accept a new parallel data word step 1 The DSP then places the address of the peripheral device on the address bus step 2 and asserts a memory select line DMS 15 shown here step 3 This causes the output of the address decoder to assert the chip select input to the peripheral step 5 The write WR output of the DSP is asserted tasw ns after the negative going edge of the DMS signal step 4 The width of the WR pulse is twp ns Data is placed on the data bus D and is valid tpw ns before the WR line goes high step 6 The positive going transition of the WR line is used to clock the data on the data bus D into the external parallel memory step 7 The data on the data bus remains valid for tp ns after the positive going edge of the WR signal The key timing requirements for writing to the peripheral device are shown in Figure 8 10 The key specification is twp the write pulse width All but the fastest peripheral devices will require wait states to be added due to their longer data access times Figure 8 11 shows the key timing specifications for the ADSP 2189M Note that they are all related to the processor clock frequency PARALLEL PERIPHERAL DEVICES WRITE INTERFACE KEY REQUIREMENTS Address Decode Delay Peripheral Chip Select Setup Time Must Be Less Than Address and Memory Select Setup Time 0 325ns for ADSP 2189M Operating at 75MHz E For Zero Wait State Access Input Data Setup Time Must be Less T
16. han 2 65 5 for ADSP 2189M Operating at 75MHz or Software Wait States Must be Added or Processor Clock Frequency Reduced E Input Data Hold Time Must be Less Than t 2 325ns for ADSP 2189M Operating at 75MHz E Peripheral Device Must Accept Input Write Clock Pulse of Width twp 3 65ns for ADSP 2189M Operating at 75MHz or Software Wait States Must be Added or Processor Clock Frequency Reduced Figure 8 10 8 9 INTERFACING TO DSPS ADSP 2189M PARALLEL WRITE TIMING Processor Clock Period 13 3ns tasw Address and Memory Select Before WR Low 0 256 3ns Minimum tpw Data Setup Before WR High 0 5t 4ns Wait States tox Data Hold After WR High 0 25t 1ns twp WR Pulse Width 0 5 3 Wait States tox Minimum Figure 8 11 The AD5340 is a 12 bit 100kKSPS DAC which has a parallel data interface It operates on a single 2 5V to 5 5V supply and dissipates 345uW 8V supply A power down mode further reduces the power to 0 24uW The part incorporates an on chip output buffer which can drive the output to both supply rails The AD5340 allows the choice of a buffered or unbuffered reference input The device has a power on reset circuit that ensures that the DAC output powers on at OV and remains there until valid data is written to the part A block diagram is shown in Figure 8 12 The input is double buffered The key interface timing specifications for th
17. is likewise increased to 70 15ns which meets the ADC s read pulse width requirement t7 70ns min Unless the memory mapped peripheral has an extremely short access time wait states are generally required whether interfacing to ADCs DACs or external memory AD7854 AD7854L 3V SINGLE SUPPLY 12 200 100kSPS PARALLEL OUTPUT ADC AV AGND AIN 4 AD7854 AD7854L DVpp AIN O DGND REF REF oyz CHARGE CLKIN REDISTRIBUTION DAC SAR ADC O CONVST CONTROL BUSY CALIBRATION MEMORY REF2 AND CONTROLLER PARALLEL INTERFACE CONTROL REGISTER O O DB11 DBO CS RD WR HBEN Figure 8 5 8 5 INTERFACING TO DSPS ADSP 2189M AND AD7854 AD7854L PARALLEL READ INTERFACE TIMING SPECIFICATION COMPARISON ADSP 2189M Processor 75MHz AD7854 AD7854L ADC tasr Data Address Memory t CS to RD Setup Time Select Setup Time Before RD Low Ons min Must Add Address 0 325ns min Decode Time to this Value trp RD Pulse Width 5 RD Pulse Width 70ns min 3 65ns wait states x 13 3ns min 70 15ns min trop RD Low to Data Valid Data Access Time After RD 1 65ns wait states x 13 3ns min 50ns max 68 15ns min Data Hold from RD High tg Bus Relinquish Time After RD Ons min 5ns min 40ns max NOTES 1 Adding 5 wait states to the ADSP 2189M increases tpp to 70 15ns which is greater than t7 70
18. l DSP interface to a parallel peripheral device such as a DAC is shown in Figure 8 8 The memory write cycle timing diagram for the ADSP 21xx family is shown in Figure 8 9 In most real time applications the DAC is operated continuously from a stable sampling clock Most DACs for these applications have double buffering an input latch to handle the asynchronous DSP interface followed by a second latch called the DAC latch which drives the DAC current switches The DAC latch strobe is derived from an external stable sampling clock In addition to clocking the DAC latch the DAC latch strobe is also used to generate a processor interrupt to the DSP which indicates that the DAC is ready for a new input data word 8 7 INTERFACING TO DSPS DAC TO ADSP 21xx FAMILY PARALLEL INTERFACE ADSP 21xx 1 DAC DAC LATCH memory 0 13 STROBE ADDRESS BUS DATA MEMORY SELECT CHIP SELECT PROCESSOR INTERRUPT REQUEST INPUT LATCH STROBE MEMORY WRITE WR MEMORY DATA PARALLEL DATA BUS INPUT Figure 8 8 ADSP 21xx FAMILY MEMORY WRITE TIMING DSP CLKOUT 4 twwr 4 t i 1 1 1 ASW 1 1 1 T oE pi gt i i i twpe t 5 1 ty DW 1 Figure 8 9 8 8 INTERFACING TO DSPS The write process is thus initiated by the peripheral device asserting the DSP interrupt request line indicating that the peripheral is r
19. m to drive the ADSP 2189M The serial interface of the 05392 is not fast enough to handle the ADSP 2189M maximum master clock frequency However the serial interface clocks are programmable and can be set to generate the proper timing for fast or slow DACs The input shift register in the AD5322 is 16 bits wide The 16 bit word consists of four control bits followed by 12 bits of DAC data The first bit loaded determines whether the data is for DAC A or DAC B The second bit determines if the reference input will be buffered or unbuffered The next two bits control the operating modes of the DAC normal power down with 1kQ to ground power down with 100kQ to ground or power down with a high impedance output 8 18 INTERFACING TO DSPS AD5322 DAC SERIAL INTERFACE TO ADSP 2189M ADSP 2189M 75MHz AD5322 DAC SERIAL PORT Figure 8 22 INTERFACING I O PORTS ANALOG FRONT ENDS AND CODECS TO DSPS Since most DSP applications require both an ADC and a DAC I O Ports and CODECs have been developed which integrate the two functions on a single chip as well as provide easy to use interfaces to standard DSPs These devices also go by the name of analog front ends A functional block diagram of the AD73322 is shown in Figure 8 23 This device is a dual analog front end AFE with two 16 bit ADCs and two 16 bit DACs capable of sampling at 64KSPS It is designed for general purpose applications including speech and telepho
20. mode configuration with two serial devices a byte wide EPROM and optional external program and data overlay memories Programmable wait state generation allows the fast processor to connect easily to slower peripheral devices The ADSP 2189M also provides four external interrupts seven general purpose input output pins and two serial ports One of the serial ports can be configured as two additional interrupts a general purpose input and a general purpose output pin for a total of six external interrupts 9 IOs and one serial port The ADSP 2189M can also be operated in the host memory mode which allows access to the full external data bus but limits addressing to a single address bit Additional system peripherals can be added in the host memory mode through the use of external hardware to generate and latch address signals 8 23 INTERFACING TO DSPS ADSP 2189M SYSTEM INTERFACE FULL MEMORY MODE ADSP 2189M 1 2 X CLOCK CLKIN ADDR OR CRYSTAL XTAL INTERRUPTS TRax GENERAL 7 PURPOSE IO MODE x SERIAL DEVICE SERIAL DEVICE SPORT1 PMS DMS CMS SPORTO BR BG PWD PWDACK 8 24 BUS REQUEST GRANT HUNG POWER DOWN INPUT POWER DOWN OUTPUT Figure 8 27 DATA cs ADDR DATA SPACE PERIPHERALS 2048 LOCATIONS OVERLAY MEMORY TWO 8K PM SEGMENTS TWO 8K DM SEGMENTS INTERFACING TO DSPS REFERENCES 1 10 11 12 13 1
21. ns and meets the tg 50ns requirement 2 tg max 40ns may cause bus contention if a write cycle immediately follows the read cycle Figure 8 6 A simplified interface diagram for the two devices is shown in Figure 8 7 The conversion complete signal from the AD7854 AD7854L corresponds to the BUSY output pin Notice that the configuration allows the DSP to write data to the AD7854 AD7854L parallel interface control register This is needed in order to set various options in the AD7854 AD7854L and perform the calibration routines In normal operation however data is read from the AD7854 AD7854L as described above Writing to external parallel memory mapped peripherals is discussed later in this section Parallel interfaces between other DSP processors and external peripherals can be designed in a similar manner by carefully examining the timing specifications for all appropriate signals for each device The data sheets for most ADCs contain sufficient information in the application section to interface them to the DSPs 8 6 INTERFACING TO DSPS AD7854 AD7854L ADC PARALLEL INTERFACE TO ADSP 2189M SAMPLING CLOCK CONVST ADSP 2189M AD7854 AD7854L 75MHz ADC DMS LOW READ DB11 DBO Notes 5 Software Wait States HBEN and WR required for writing to ADC Sampling clock may come from DSP Figure 8 7 PARALLEL INTERFACING TO DSP PROCESSORS WRITING DATA TO MEMORY MAPPED DACS A simplified block diagram of a typica
22. ny using sigma delta ADCs and sigma delta DACs Each channel provides 77dB signal to noise ratio over a voiceband signal bandwidth The ADC and DAC channels feature programmable input output gains with ranges of 38dB and 21dB respectively An on chip voltage reference is included to allow single supply operation on 2 7V to 5 5V Power dissipation is 73mW with a 3V supply 8 19 INTERFACING TO DSPS AD73322 SINGLE SUPPLY 16 64kKSPS CODEC WITH SERIAL INTERFACE AVDD1 AVDD2 DVDD O O O 1 Q4 gt VINP1 ADC SDI VINN1 CHANNEL 1 VFBN1 5 gt gt SDIFS VOUTP1 O lt _ sa pac KJ SCLK CHANNEL 1 VOUTN1 gt SE REFOUT SERIAL REFERENCE REFCAP PORT VFBP2 O lt gt VINP2 ADC MCLK VINN2 CHANNEL 2 VFBN2 lt gt VOUTP2 DAC C SDOFS VOUTN2 CHANNEL 2 SDO O O O AGND1 AGND2 DGND Figure 8 23 The sampling rate of the CODECs is programmable with four separate settings of 64kHz 32kHz 16kHz and 8kHz when operating from a master clock of 16 384MHz The serial port allows easy interfacing of single or cascaded devices to industry standard DSP engines such as the ADSP 21xx family The SPORT transfer rate is programmable to allow interfacing to both fast and slow DSP engines The interface to the ADSP 218x family is shown in Figure 8 24 The SE pin SPORT enable may be controlled from a parallel output pin or a flag pin such
23. t Remain Valid for tap from the Rising Edge of Read Signal RD Ons for ADSP 2189M E Peripheral Device Must Accept Minimum Output Enable Pulse Width of trp 3 65ns for ADSP 2189M Operating at 75MHz or Software Wait States Must be Added or Processor Clock Frequency Reduced Figure 8 3 8 3 INTERFACING TO DSPS The DSP tppp specification determines the peripheral device data access time requirement In the case of the ADSP 2189M tgpp 1 65ns minimum 75MHz If the access time of the peripheral is greater than this wait states must be added or the processor speed reduced This is a relatively common situation when interfacing external memory or ADCs to fast DSPs The relationship between these timing parameters for the ADSP 2189M is given by the equations shown in Figure 8 4 Note that these specifications are dependent on the DSP clock frequency ADSP 2189M PARALLEL READ TIMING AT 75MHz E Processor Clock Period 13 3ns E tasr Address and Memory Select Setup Before Read Low 0 254 3ns Minimum E trop Read Low to Data Valid 0 5tc 5 wait states Maximum E Data Hold from Read High Ons Minimum E Read Pulse Width 0 5tc 3ns wait states Minimum Figure 8 4 The ADSP 2189M can easily be interfaced to slow peripheral devices using its programmable wait state generation capability Three registers control wait state generation for boot program data and
24. to the External Port of the DSP With the SHARC family of DSPs there are several ways of connecting the converters to this port The access to the converters can be done using the direct memory access DMA controller of the DSP or it can be done under program control using the core of the DSP Using the DMA places no load on the DSP core so it can continue processing executing program instructions while the data is transferred to from the on chip memory The AD9201 is a dual channel 10 bit 20MSPS ADC which operates a single 2 7V to 5 5V supply and dissipates only 215mW 8V supply The AD9201 offers closely matched ADCs needed for many applications such as I Q communications Input buffers an internal voltage reference and multiplexed digital outputs buffers make interfacing to the AD9201 very simple The companion part to the AD9201 ADC is the AD9761 DAC The AD9761 is a dual 10 bit 20 5 per channel DAC operating on a single 2 7V to 5 5V supply and dissipating only 200mW 8V supply A voltage reference digital latches and 2x interpolation make the AD9761 useful for I Q transmitter applications 8 22 INTERFACING TO DSPS AD9201 ADC AND AD9761 DAC INTERFACE TO ADSP 21065L ADSP 21065L DUAL 10 BIT 20MSPS ADCs AD9201 AD9761 ADC DAC 00 D9 DO D9 DUAL 10 CHIP SELECT Figure 8 26 DSP SYSTEM INTERFACE Figure 8 26 shows a simplified ADSP 2189M system using the full memory
25. uit board real estate ADC and DAC signal to noise ratios are approximately 77dB over voiceband frequencies The AD74222 80 integrates 80K bytes of on chip memory configured as 16K words 24 bit of program RAM and 16K words 16 bit of data RAM The AD73422 40 integrates 40K bytes of on chip memory configured as 8K words 24 bit of program RAM and 8K words 16 bit of data RAM Power down circuitry is also provided to meet the low power needs of battery operated portable equipment The AD73422 operates on a 3V supply and dissipates approximately 120mW with all functions operational 8 21 INTERFACING TO DSPS AD73422 dspConverter Complete Dual CODEC AD73322 and DSP ADSP 2185L 86L 14mm by 22mm BGA package 3V Single Supply Operation 73mW Power Dissipation Power Down Mode CODEC Dual 16 bit Sigma Delta ADCs and DACs Data Rates 8 16 32 and 64KSPS 77dB SNR DSP 52MIPS ADSP 218x Code Compatible 80K Byte and 40K Byte On Chip Memory Options Figure 8 25 HIGH SPEED INTERFACING With the advent of ever faster DSP clock rates and newer architectures it has become possible to acquire and process high speed signals The programmability of DSPs makes it possible to run different algorithms on the same hardware while providing different system functionality Figure 8 26 shows a simplified ADSP 21065L system connected to a high speed ADC and high speed DAC The ADC and DAC both have parallel interfaces connected
26. wing more interface flexibility The port also contains u law and A law companding hardware for voiceband telecommunications applications SERIAL ADC TO DSP INTERFACE A timing diagram of the ADSP 2189M serial port operating in the receive mode alternate framing is shown in Figure 8 17 The first negative going edge of the SCLEK to occur after the negative going edge of the RFS clocks the MSB data from the ADC into the serial input latch The process continues until all serial bits have been transferred into the serial input latch The key timing specifications of concern the serial data setup tgcg and hold times tsc with respect to the negative going edge of the SCLK In the case of the ADSP 2189M these values are 4ns and Tns respectively The latest generation ADCs with high speed serial clocks will have no trouble meeting these specifications even at the maximum serial data transfer rate 8 14 INTERFACING TO DSPS ADSP 2189M SERIAL PORT RECEIVE TIMING ADC i SCLK 15715550507 t SCS t gt 4 5 5 5 5 5 ALTERNATE FRAMING MODE ADC IS MASTER Figure 8 17 The AD7853 AD7853L is 12 bit 200 100kSPS ADC which operates a single 3 to 5 5V supply and dissipates only 4 5mW 3V supply AD78538L After each conversion the device automatically powers down to 25uW The AD7853 AD7853L is based on a successive approximation architecture and uses a charge re
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