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STM8S20xxx

1. Table 10 General hardware register map continued Address Block Register label Register name eae 0x00 5230 UART1_SR UART1 Status Register 0xCO 0x00 5231 UART1_DR UART1 Data Register XX 0x00 5232 UART1_BRR1 UART1 Baud Rate Register 1 0x00 0x00 5233 UART1_BRR2 UART1 Baud Rate Register 2 0x00 0x00 5234 UART1_CR1 UART1 Control Register 1 0x00 0x00 5235 UART1 UART1_CR2 UART1 Control Register 2 0x00 0x00 5236 UART1_CR3 UART1 Control Register 3 0x00 0x00 5237 UART1_CR4 UART1 Control Register 4 0x00 0x00 5238 UART1_CR5 UART1 Control Register 5 0x00 0x00 5239 UART1_GTR UART1 Guard time Register 0x00 0x00 523A UART1_PSCR UART1 Prescaler Register 0x00 se E Reserved area 5 bytes 0x00 5240 UART3 SR UARTS Status Register Coh 0x00 5241 UART3_DR UARTS Data Register XX 0x00 5242 UART3_BRR1 UART3 Baud Rate Register 1 0x00 0x00 5243 UART3_BRR2 UARTS Baud Rate Register 2 0x00 0x00 5244 UART3_CR1 UARTS Control Register 1 0x00 0x00 5245 ae UART3_CR2 UARTS Control Register 2 0x00 0x00 5246 UART3_CR3 UARTS Control Register 3 0x00 005247 UART3_CR4 UARTS Control Register 4 0x00 0x00 5248 Reserved 0x00 5249 UART3_CR6 UARTS Control Register 6 0x00 pers aie Reserved area 6 bytes Ky 41 96
2. Address Block Register Label Register Name er 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 cPu XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x17 0x00 7F09 SPL Stack pointer low OxFF 0x00 7FOA CCR Condition code register 0x28 ye du Reserved area 85 bytes 0x00 7F60 CPU CFG GCR Global configuration register 0x00 0x00 7F70 ITC SPR1 Interrupt Software priority register 1 OxFF 0x00 7F71 ITC SPR2 Interrupt Software priority register 2 OxFF 0x00 7F72 ITC_SPR3 Interrupt Software priority register 3 OxFF 0x00 7F73 ITC_SPR4 Interrupt Software priority register 4 OxFF 0x00 7F74 SR ITC_SPR5 Interrupt Software priority register 5 OxFF 0x00 7F75 ITC_SPR6 Interrupt Software priority register 6 OxFF 0x00 7F76 ITC SPR7 Interrupt Software priority register 7 OxFF 0x00 7F77 ITC_SPR8 Interrupt Software priority register 8 OxFF i Reserved area 2 bytes 0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00 posso Reserved area 15 bytes Ky 47 96 Memory map STM8S20xxx Table 11 CPU SWIM debug module interru
3. Figure 4 LOFP 64 pin pinout Q Q 9 x un o SV Z re g E oO ugz map t So or TD 5 V NP IX X adagio SOGZ EFPAYAVASEQMYVGHGE Sao odtZz2225 115 EEEEEEDEORS 3000000335 ESSTIIIIIICELE SALILASLLUNILIOOO LONLLALLlLANNNANLAANANA Huuuuumiuuiuiurm 64 63 62 61 60 59 58 57 56 55 5453 52 51 50495 NRST O 160 48 H PIO OSCIN PA1 D 2 47 PG4 OSCOUT PA2 O 3 46 H PG3 Vssio 1 O 4 45 H PG2 Vss 05 44 O PG1 CAN RX VCAP O 6 43 H PGO CAN TX Voo O7 42 O PC7 HS SPI_MISO Vppio 1 O 8 41 PC6 HS SPI_MOSI TIM3_CH1 TIM2_CH3 PA3 O 9 40 H Vppio 2 UART1_RX HS PA4 O 10 39 O Vssio 2 UART1_TX HS PA5 O 11 38 H PC5 HS SPI_SCK UART1_CK HS PA6 12 37 O PC4 HS TIM1_CH4 AIN15 PF7 D 13 36 H PC3 HS TIM1_CH3 AIN14 PF6 O 14 35 H PC2 HS TIM1 CH2 AIN13 PF5 O 15 34 H PC1 HS TIM1 CH1 AIN12 PF4 D 16 33 H PE5 SPI_LNSS 17 18 1920 21 22 23 24 25 26 27 28 29 3031 32 oOo t y O l XO lO st CO QN T Q r OO L i OG di glL m m m m mt m m a NU amp EVITL LD gt Ooronso ascooso5 z 52222222222 tTTTLTLATA AA A A THE ooOluIII IJ 1IOO0O OQor t aNSrrr S E TEBE 1 HS high sink capability 2 T True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of
4. Table 10 General hardware register map continued Address Block Register label Register name Reset status 0x00 50C3 CLK CMSR Clock master status register OxE1 0x00 50C4 CLK SWR Clock master switch register OxE1 0x00 50C5 CLK SWCR Clock switch control register perum 0x00 50C6 CLK CKDIVR Clock divider register 0x18 0x00 50C7 CLK_PCKENRI Peripheral clock gating register 1 OxFF 0x00 50C8 ork CLK_CSSR Clock security system register 0x00 0x00 50C9 CLK_CCOR Configurable clock control register 0x00 0x00 50CA CLK PCKENR2 Peripheral clock gating register 2 OxFF 0x00 50CB CLK CANCCR CAN clock control register 0x00 0x00 50CC CLK HSITRIMR HSI clock calibration trimming register XX 0x00 50CD CLK_SWIMCCR SWIM clock control register x0 0x00 50CE to 0x00 50D0 Reserved area 3 bytes 0x00 50D1 eee WWDG_CR WWDG Control Register Ox7F 0x00 50D2 WWDG WR WWDR Window Register Ox7F 0x00 50D3 to 0x00 50DF Reserved area 13 bytes 0x00 50E0 IWDG_KR IWDG Key Register 0x00 50E1 IWDG IWDG PR IWDG Prescaler Register 0x00 0x00 50E2 IWDG RLR IWDG Reload Register OxFF 0x00 50E3 to 0x00 50EF Reserved area 13 bytes 0x00 50F0 AWU CSR1 AWU Control Status Register 1 0x00 0x00 50F1 AWU AWU APR AWU Asynchronous prescaler buffer Ox3F register 0x00 50F2 AWU TBR AWU Timebase selection register 0x00 0x00 50F3 BEEP BEEP CSR BEEP Control Status Register Ox1F 0x00 50F4 to 0x00 50FF Reserved area 12 b
5. Memory map STM8S20xxx Table 10 General hardware register map continued Address Block Register label Register name an 0x00 5250 TIM1 CR1 TIM1 Control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 Control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 Slave Mode Control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1 IER TIM1 Interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 Status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 Status register 2 0x00 0x00 5257 TIM1_EGR TIM1 Event Generation register 0x00 0x00 5258 TIM1_CCMR1 TIM1 Capture Compare mode register 1 0x00 0x00 5259 TIM1_CCMR2 TIM1 Capture Compare mode register 2 0x00 0x00 525A TIM1_CCMR3 TIM1 Capture Compare mode register 3 0x00 0x00 525B TIM1_CCMR4 TIM1 Capture Compare mode register 4 0x00 0x00 525C TIM1_CCERI TIM1 Capture Compare enable register 1 0x00 0x00 525D TIM1 CCER2 TIM1 Capture Compare enable register 2 0x00 0x00 525E TIM1 CNTRH TIM1 Counter high 0x00 0x00 525F TIM1 CNTRL TIM1 Counter low 0x00 0x00 5260 D TIM1_PSCRH TIM1 Prescaler register high 0x00 0x00 5261 TIM1_PSCRL TIM1 Prescaler register low 0x00 0x00 5262 TIM1_ARRH TIM1 Auto reload register high OxFF 0x00 5263 TIM1 ARRL TIM1 Auto reload register low OxFF 0x00 5264 TIM1_RCR TIM1 Repetition counter register 0x00 0x00 5265 TIM1_CCR1H TIM1 Capture Compare register 1 high 0x00 0x00 5266 TIM1_CCRIL TIM1 Capture Compare register 1 low 0x00 0x00 5267
6. SU NSSy 1 c SCKj h NSS 1 CPHA 1 NE V V CPOL 0 E s Y tw SGKH Le pi CPHA 1 t i i i CPOL 1 E no mM MISO h OUTPUT dio vwsHour UT BITS OUT issour OUT SI lt gt gt MOSI MSB IN BIT IN LSB IN INPUT msn i 1 gt ai14135 SCK Input 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7Vpp K 75 96 Electrical characteristics STM8S20xxx Figure 39 SPI timing diagram master mode High NSS input le SCKj CPHA 0 N gf a CPOL 0 i z i T sl pesca i n i i i e Fe SCK Input o YT I i wise P SCK ae sem XC cie h MI i OUTUT 1 __mssour f U l A tov ty MO Jai te th MO ie ai14136 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7Vpp 76 96 2 STM8S20xxx Electrical characteristics 8 3 9 2 PPC interface characteristics Table 40 PC characteristics Standard mode PC Fast mode 1200 Symbol Parameter Unit MinO Max Min Max lwsciL SCL clock low time 4 7 1 3 us tw SCLH SCL clock high time 4 0 0 6 tsuspA SDA setup time 250 100 taspa SDA data hold time o 9 o 900 9 t SDA SDA and SCL rise time 1000 300 NS t scL t SDA SDA and SCL fall time 300 300 t scL ty stay START condition hold time 4 0 0 6 us lsusra R
7. 25 C m 25 C 1 75 85 C t75 85 C 1 5 125 C 1 5 1 125 C 1 25 1 25 2 j E E 0 75 0 75 0 5 0 5 0 25 0 25 OF OF 0 2 4 6 8 10 12 14 5 10 15 20 25 lo mA lo mA Figure 27 Typ Vor 9 Vpp 3 3 V high sink Figure 28 Typ Vor Vpp 5 0 V high sink ports ports 1 5 1 aoe 15 wg 25 C 25 C 125 85 C 1 25 85 C 125 C 125 C 1 1 4 0 75 7075 gt 05 05 0 25 0 25 A OF oF 0 2 4 6 8 10 12 14 0 5 10 15 20 25 lo mA lo mA 70 96 STM8S20xxx Electrical characteristics Figure 29 Typ Vpp z Vou Vpp 3 3 V standard ports Figure 30 Typ Vpp Vou Vpp 5 0 V standard ports A 40 C 25 C 1 75 85 C 1 5 125 C E 1 25 4 8 gt 0 75 0 5 0 25 oF 1 2 3 4 5 6 loy MA 40 C 25 C 1 75 85 C 15 125 C 1 25 1 0 75 0 5 p 0 25 OF o lon MA Figure 31 Typ Vpp Vou Vpp 3 3 V high Figure 32 Typ Vpp 3 Vou Vpp 5 0 V high sink ports sink ports 40 C 5 40 C As 25 C 25 C 1 75 85 C 179 85 C 1 5 125 C M5 125 C 1 25 1 25 5 5 gt 4 1 8 gt 0 75 gt 0 75 0 5 lt 0 5 0 25 0 25 0 OF 0 2 4 6 8
8. 4 14 5 SPI Maximum speed 10 Mbit s fyaster 2 both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on 2 lines with a possible bidirectional data line Master or slave operation selectable by hardware or software CRC calculation 1 byte Tx and Rx buffer Slave master selection input pin e C master features Clock generation Start and stop generation e IC slave features Programmable I C address detection Stop bit detection e Generation and detection of 7 bit 10 bit addressing and general call e Supports different communication speeds Standard speed up to 100 kHz A Fast speed up to 400 kHz CAN The beCAN controller basic enhanced CAN interfaces the CAN network and supports the CAN protocol version 2 0A and B It has been designed to manage a high number of incoming messages efficiently with a minimum CPU load For safety critical applications the CAN controller provides all hardware functions to support the CAN time triggered communication option TTCAN The maximum transmission speed is 1 Mbit Transmission e Three transmit mailboxes e Configurable transmit priority by identifier or order request e Time stamp on SOF transmission 19 96 Product overview STM8S20xxx 20 96 Reception 8 11 and 29 bit ID 1 receive FIFO 3 messages deep Software efficient mailbox mapping at a unique address space FMI filter match index stored wit
9. 18 96 e Transmission error detection with interrupt generation e Parity control Synchronous communication e Full duplex synchronous transfers e SPI master operation e 8 bit data communication e Max speed 1 Mbit s at 16 MHz fcpy 16 LIN master mode e Emission Generates 13 bit synch break frame e Reception Detects 11 bit break frame UART3 Main features e 1 Mbit s full duplex SCI LIN master capable e High precision baud rate generator Asynchronous communication UART mode e Full duplex communication NRZ standard format mark space e Programmable transmit and receive baud rates up to 1 Mbit s fcpy 16 and capable of following any standard baud rate regardless of the input frequency e Separate enable bits for transmitter and receiver e 2receiver wakeup modes A Address bit MSB Idle line interrupt e Transmission error detection with interrupt generation e Parity control LIN master capability e Emission Generates 13 bit synch break frame e Reception Detects 11 bit break frame LIN slave mode Autonomous header handling one single interrupt per valid message header Automatic baud rate synchronization maximum tolerated initial clock deviation 15 96 Synch delimiter checking 11 bit LIN synch break detection break detection always active Parity check on the LIN identifier field LIN error management Hot plugging support STM8S20xxx Product overview 4 14 3 4 14 4
10. Pinouts and pin description Figure 7 LQFP 32 pin pinout NRST OSCIN PA1 OSCOUT PA2 Vss VCAP Von Vppio AIN12 PF4 RX F PD6 UART3 F PD5 HS TIM2_CH1 BEEP HS TIM3_CH2 TIM1_BRK CLK_CCO HS TIM3_CH1 TIM2_CH3 HS TIM2_CH2 ADC_ETR HS SWIM UART3_TX ANOuRWND SO PD7 TLI TIM1_CH4 1 9 10111213141516 w 8 SO PD4 RO PD3 NO PD2 NH PDI NH PDO N NN NOR pp aoo VppA Vssa HTNN TQ manna canocanoca LILRVLE DFAA ZZZZZZ LLLI TIEZ ZZ QOrLTFowr Onw LIL oo 9 99 NAE SS EE EEE PC7 HS SPI_MISO PC6 HS SPI_MOSI PC5 HS SPI_SCK PC4 HS TIM1_CH4 PC3 HS TIM1_CH3 PC2 HS TIM1_CH2 PC1 HS TIM1_CH1 70 PES SPI NSS 1 2 K HS high sink capability alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function 25 96 Pinouts and pin description STM8S20xxx Table 4 Legend abbreviations Type l input O output S power supply Level Input CM CMOS Output HS High sink Output speed O1 Slow up to 2 MHz O2 Fast up to 10 MHz OS Fast slow programmability with slow as default state after reset OA Fast slow programmability
11. X Port C1 channel 1 Timer 1 44 35 27 25 19 PC2 TIM1_CH2 O X X X HS OS X X Port C2 channel 2 Timer 1 45 36 28 26 20 PC3 TIM1_CH3 1 O X X X HS OS X X Port C3 channel 3 Timer 1 46 37 29 21 PCA TIM CHA l O X X X HS OS X X Port C4 channel 4 47 38 30 27 22 PC5 SPI_SCK 1 O X X X HS OS X X Port C5 SPI clock 48 39 31 28 Vssio 2 S I O ground 49 40 32 29 Vppio 2 S I O power supply SPI master 50 41 33 30 23 PCO SPI MOSI 1 O X X X HS 03 X X Port C6 lout slave in 51 42 34 31 24 PC7 SPI_MISO_ 1 0 X X X HS 03 X X Port cz SP master in slave out 52 43 35 32 PGO CAN TX 1 O X X O1 X X Port GO CAN transmit 53 44 36 33 PG1 CAN RX 1 O X X O1 X X Port G1 CAN receive 54145 PG2 1 O X X O1 X X Port G2 55 46 PG3 1 O X X O1 X X Port G3 56 471 PG4 1 O X X O1 X X Port G4 28 96 ky STM8S20xxx Pinouts and pin description Table 5 Pin description continued Pin number Input Output or z Alt t olt ol qyin o S x o g Default funciones o oO ST I n Pin name Q D E E v 5 alternate EE e eee F al 2g 8 9 rs c9 function remap aki S 5 2 9 k option bit 3 34 34 202 Ss LU 57 48 PIO O
12. y STM8S20xxx Performance line 24 MHz STM8S 8 bit MCU up to 128 Kbytes Flash integrated EEPROM 10 bit ADC timers 2 UARTs SPI IPC CAN Features Core m Max fcpu up to 24 MHz 0 wait states fcp 16 MHz m Advanced STM8 core with Harvard architecture and 3 stage pipeline m Extended instruction set m Max 20 MIPS 24 MHz Memories m Program memory Up to 128 Kbytes Flash data retention 20 years at 55 C after 10 kcycles m Data memory Up to 2 Kbytes true data EEPROM endurance 300 kcycles m RAM Up to 6 Kbytes Clock reset and supply management m 2 95 to 5 5 V operating voltage m Flexible clock control 4 master clock sources Low power crystal resonator oscillator External clock input Internal user trimmable 16 MHz RC Internal low power 128 kHz RC m Clock security system with clock monitor m Power management Low power modes Wait Active halt Halt Switch off peripheral clocks individually m Permanently active low consumption power on and power down reset Interrupt management m Nested interrupt controller with 32 interrupts m Up to 37 external interrupts on 6 vectors Timers W 2x 16 bit general purpose timers with 2 3 CAPCOM channels IC OC or PWM m Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronization W 8 bit basic timer with 8 bit prescaler January 2009 LQFP44 10x10 LQFP64
13. 200 26063 ON Supply current in HSE crystal osc 16 980 R DD H active halt mode Powerdown mode MHz H LSI RC osc 128 kHz 140 Operating mode 68 OFF LSI RC osc 128 kHz Powerdown mode 11 45 3 1 Configured by the REGAH bit in the CLK_ICKR register 2 Configured by the AHALT bit in the FLASH CH1 register 3 Data based on characterization results not tested in production Table 22 Total current consumption in active halt mode at Vpp 3 3 V Conditions Symbol Parameter Main voltage Typ Unit regulator Flash mode 2 Clock source MVR HSE crystal osc 16 MHz 600 Operating mode a LSI RC osc 128 kHz 200 HSE crystal osc 16 MHz 540 Ipp AH upply CUREN IN Powerdown mode pA active halt mode LSI RC osc 128 kHz 140 Operating mode 66 OFF LSI RC osc 128 kHz Powerdown mode 9 1 Configured by the REGAH bit in the CLK ICKR register 2 Configured by the AHALT bit in the FLASH CH1 register 58 96 2 STM8S20xxx Electrical characteristics Total current consumption in halt mode Table 23 Total current consumption in halt mode at Vpp 5 0 V T4 40 to 85 C Symbol Parameter Conditions Typ Max Unit Flash in operating mode HSI 63 5 clock after wakeup Ipp H Supply current in halt mode uA Flash in powerdown mode HSI 6 5 30 clock after wakeup Table 24 Total current consumption in halt mode at Vpp 3 3 V Symbol Parameter Conditio
14. 5 5 V 40 252 40 C lt TA lt 125 C t HSI oscillator wakeup 4 1 SU HSI time including calibration H HSI oscillator power 2 IDD HS consumption TU 7250 pA 1 Guaranteeed by design not tested in production 2 Data based on characterization results not tested in production Figure 18 Typical HSI frequency vs Vpp 4 temperatures 40 C 3 m 25 C 85 C 2 125 C x 5 1 S 5 0 2 g kear g 1 I 2 3 r r r r r r 2 5 3 3 5 4 4 5 5 5 5 6 Voo V ky STM8S20xxx Electrical characteristics K Low speed internal RC oscillator LSI Subject to general operating conditions for Vpp and Ty Table 31 LSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit figi Frequency 110 128 146 kHz tsuLsi LSI oscillator wakeup time 70 us Ipp Lsi LSI oscillator power consumption 5 uA 1 Guaranteeed by design not tested in production Figure 19 Typical LSI frequency vs Vpp 150 145 140 Nw 135 I 130 g 5 125 g 120 5 115 l 110 105 100 r r 2 5 3 3 5 4 5 5 5 Vop V 65 96 Electrical characteristics STM8S20xxx 8 3 5 66 96 Memory characteristics RAM and hardware registers Table 32 RAM and hardware registers Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode Halt mode or reset Vit max V 1 Minimum supply voltage
15. 87 64 pin low profile quad flat package 10x 10 1 1 1 22s2sk saksar 88 48 pin low profile quad flat package 7 X7 LL 89 44 pin low profile quad flat package 10x10 212 2 2k skaka kaka ana 90 32 pin low profile quad flat package 7 X 7 LL 91 STM8S207 208xx performance line ordering information scheme 94 7 96 Introduction STM8S20xxx 8 96 Introduction This datasheet contains the description of the STM8S20xxx performance line features pinout electrical characteristics mechanical data and ordering information e For complete information on the STM8S microcontroller memory registers and peripherals please refer to the STM8S microcontroller family reference manual RM0016 e For information on programming erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual PM0051 e Forinformation on the debug and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 e Forinformation on the STM8 core please refer to the STM8 CPU programming manual PM0044 STM8S20xxx Description 2 Description The STM8S20xxx performance line 8 bit microcontrollers offer high density from 32 to 128 Kbytes Flash program memory All devices of the STM8S20xxx performance line provide the following benefits e Reduced system cost Integrated true data EEPROM for up to 3
16. Memory map STM8S20xxx Table 10 General hardware register map Address Block Register label Register name Naso status 0x00 5050 to Reserved area 10 bytes 0x00 5059 0x00 505A FLASH CR1 Flash control register 1 0x00 0x00 505B FLASH CR2 Flash control register 2 0x00 0x00 505C FLASH NCR2 fnshicompls nentahgonrel OxFF register 2 Flash 0x00 505D FLASH FPR Flash protection register 0x00 0x00 505E FLASH _NFPR Flash complementary protection register OxFF 0x00 505F FLASH IAPSR Flash in application programming status 0x00 register 0x00 5060 to 0x00 5061 Reserved area 2 bytes 0x00 5062 Flash FLASH PUKR Fash Progr m memory UMProtection 0x00 register 0x00 5063 Reserved area 1 byte 0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection register 0x00 0x00 5065 to 0x00 509F Reserved area 59 bytes 0x00 50A0 m EXTI_CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00 0x00 50A2 to 0x00 50B2 Reserved area 17 bytes 0x00 50B3 RST RST_SR Reset status register XX 0x00 50B4 to 0x00 50BF Reserved area 12 bytes 0x00 50C0 due CLK ICKR Internal clock control register 0x01 0x00 50C1 CLK_ECKR External clock control register 0x00 0x00 50C2 Reserved area 1 byte 38 96 ky STM8S20xxx Memory map
17. Option bytes STM8S20xxx 6 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated block of the memory Except for the ROP read out protection byte each option byte has to be stored twice in a regular form OPTx and a complemented one NOPTx for redundancy Option bytes can be modified in ICP mode via SWIM by accessing the EEPROM address shown in Table 6 Option bytes below Option bytes can also be modified on the fly by the application in IAP mode except the ROP and UBC options that can only be toggled in ICP mode via SWIM Refer to the STM8S Flash programming manual PM0051 and STM8 SWIM communication protocol and debug module user manual UM0470 for information on SWIM programming procedures Table 6 Option bytes Option bits Factory Option Option Addr us E E n default Lud MEE 6 5 4 3 2 1 0 setting Read out 4800h protection OPTO ROP 7 0 00h ROP 4801h User boot OPT1 UBC 7 0 00h 4802h 99de UBC NOPTI NUBCI7 0 FFh 4803h Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFRO 00h function 4804h AFR NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFRI NAFRO FFh LSI IWDG WWDG WWDG 4805h sta OPT3 Reserved _EN _HW _HW _HALT 00h option NLSI NIWDG_H NWWDG NWWDG 48
18. X X Port D5 es K 29 96 Pinouts and pin description STM8S20xxx Table 5 Pin description continued Pin number Input Output z z S x 92 Default Fs BS SIS Pin name g gt E 3 5 gt alternate LEGKELRLE xags 25882 28 function dpa G GG GG S ES l 79 st option bit 3 3 43 a a 3 z ss x LU 79 63 47 43 31 PD6 UART3_RX 1 O X X X O1 X X Port De VARTS data receive 80 64 48 44 32 PD7 TLI vo x x x O1 x X Port D7 TOP level TIM1_CH4 interrupt AFR4 1 In the open drain output column T defines a true open drain I O P buffer and protection diode to Vpp are not implemented 30 96 2 STM8S20xxx Pinouts and pin description 5 1 1 Alternate function remapping As shown in the rightmost column of the pin description table some alternate functions can be remapped at different I O ports by programming one of 8 AFR alternate function remap option bits Refer to Section 6 Option bytes on page 32 When the remapping option is active the default alternate function is no longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers Alternate function remapping does not effect GPIO capabilities of the I O ports see GPIO section of the family reference manual RM0016 ky 31 96
19. X X O1 X X Port IO 58 PM VO X X O1 X X Port 59 BID V OIX x O1 X X Port I2 60 PI3 VO x X O1 X X Port13 dia re oes I V OIX x O1 X X Port 14 62 pS V OIX x O1 X X Port I5 63 49 PG5 O X X O1 X X Port G5 64 50 PG6 O X X O1 X X Port G6 65 51 PG7 O X X O1 X X Port G7 66 52 PE4 VO X X X O1 X X Port E4 67 53 37 PES TIM1_BKIN 1 O X X X O1 X X Port E3 or a 68 54 38 34 PE2 C SDA V O X X 01 T Port E2 I2C data 69 55 39 35 PE1 PC SCL V O X X 01 T Port E1 I2C clock 70 56 40 36 PEo CLK cco vo X X X HS 08 X X Port Eo Configurable clock output 711 BIG O X X O1 X X Port 16 Pila PIZ VO X X O1 X X PortI7 TIM1_BKIN Timer 3 AFR3 73 57 41 37 25 PDO TIM3_CH2_ 1 O X X X HS O3 X X Port Do cik CCO AFR2 74 58 42 38 26 PD1 SWIM vol x x X IHSlo4 x x Port p1 SWIM data interface 75 59 43 39 27 PD2 TIM3 CH1 O x X X HS O3 x X Port D2 er 8 TIME Chis channel 1 AFR1 76 60 44 40 28 ppgtim2_cH2 vol x x x HS O3 x X Port D3 Ier 2 ADC ETA channel 2 AFRO PD4 TIM2_CH1 Timer 2 BEEP output 77 61 45 41 29 BEEP VO X X X HS O3 X X Port D4 AFR7 78 62 46 42 30 PD5 UART3_TX l O X X X O1
20. 1 60 LIPI3 OSCIN PA1LI 2 59 IPI2 OSCOUT PA2 3 58 CIPH Vssio 1l 4 57 PIO Vss 5 56 PG4 VCAPLI 6 55 DIPG3 Voo 7 54 LIPG2 Vppio 1l 8 53 IPG1 CAN RX TIM3_CH1 TIM2 CH3 PASLI 9 52 LIPGO CAN TX UART1_RX HS PA4D 10 51 D PC7 HS SPI MISO UART1 TX HS PASO 11 29 TEC HS SPI_MOSI UART1_CK HS PA6LI 12 49 LlVppio 2 HS PHOD 13 48 Vssio 2 HS PHIL 14 47 PC5 HS SPI_SCK PH20 15 46 1 PC4 HS TIM1_CH4 PH30 16 45 DPC3 HS TIMi CH3 AIN15 PF7 17 44 IPC2 HS TIM1_CH2 AIN14 PF6L 18 43 PC1 HS TIM1 CH1 AIN13 PF5C 19 42 PCO ADC ETR AIN12 PF40 20 41 C PE5 SPI_NSS T ON CO st 10 O cO Q ANDY r oo oc CN OU CJ CJ QJ OI QUI QU QI CO CO CO C CD CO Monet m OE OR LL O x OQ 10 t CO QI 1 O st 10 CO P l O w HY vLnnd a dangI TI IWUH Lio c010000000000056080 gt oOomRondoqd co g222095 E 5222222227 50522 VOIE ee Zsrrr AARS Q Q usa B FEF NN3rrr SS SSS CEEE 1 HS high sink capability T True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function K 21 96 Pinouts and pin description STM8S20xxx 22 96
21. 10x10 LQFP80 14x14 as LQFP48 7x7 LQFP32 7x7 m Auto wakeup timer m Window watchdog and independent watchdog Communications interfaces m High speed 1 Mbit s active CAN 2 0B interface m UART with clock output for synchronous operation LIN master mode m UART with LIN 2 1 compliant master slave modes and automatic resynchronization m SPlinterface up to 10 Mbit s m C interface up to 400 Kbit s Analog to digital converter ADC m 10 bit ADC with up to 16 channels I Os m Up to 68 I Os on an 80 pin package including 18 high sink outputs m Highly robust I O design immune against current injection m Development support Single Wire Interface Module SWIM and Debug Module DM for fast on chip programming and non intrusive debugging Table 1 Device summary Reference Part number STM8S207MB STM8S207RB STM8S207R8 STM8S207R6 STM8S207xx STM8S207CB STM8S207C6 STM8S207C8 STM8S207S6 STM8S207S8 STM8S207K6 STM8S208xx STM8S208MB STM8S208RB Rev 7 1 96 www st com Contents STM8S20xxx Contents 1 IRMOGUCTION MM 8 2 DeserpHOH 22229 xxm periti 9 3 Block diagram cs iasss 616 us 3r 2 RR rao oa 6 eb ee bebe ara dad 10 4 Product overview sic ain ie ce sien Oe p ga ae 11 4 1 Central processing unit STM8 2 2 222 2 sangarar karra 11 4 2 Single wire interface module SWIM and debug module DM 12 4 3 Interrupt controller 2222 certs ada eererseaee f
22. 128 125 kHz HSI RC osc 16 MHz 1 0 a fmasteR 128 15 625 RC ose 16 MHz 8 0 55 fopu faster 128 kHz LSI RC osc 128 kHz 0 5 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Table 20 Total current consumption in Wait mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit fopy faster 24 MHz HSE crystal osc 24 MHz 2 0 Ta lt 105 C HSE user ext clock 24 MHz 1 8 TBD HSE crystal osc 16 MHz 1 6 Supply fopy faster 16 MHz HSE user ext clock 16 MHz 1 4 TBD Inp wri current in HSI RC osc 16 MHz 12 160 wait mode fopu fmasteR 128 125 kHz HSI RC osc 16 MHz 1 0 fopu fmasteR 128 15 625 kHz HSI RC osc 16 MHz 8 0 55 fcpu fmasteR 128 15 625 kHz LSI RC osc 128 kHz 0 5 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off K 57 96 Electrical characteristics STM8S20xxx Total current consumption in active halt mode Table 21 Total current consumption in active halt mode at Vpp 5 0 V Ta 40 to 85 C Conditions Symbol Parameter Main voltage Typ Max Unit regulator Flash mode Clock source MVR ie crystal osc 16 1000 Operating mode z LSI RC osc 128 kHz
23. 67 Output driving current standard ports 69 Output driving current true open drain ports 69 Output driving current high sink ports 69 NRST pin characteristics sasaran 72 SPI characteristics 00 saw idea a te tea ral ee ker PUER adi e P ERE Re d 74 l C characteristics essi o REGE dnd eaixd tua RE EreC dace ud uu ates 77 ADC characteristics 222222 store cue ooa huc RU RO adea aa Y e abe ne 78 ADC accuracy with Rain lt 10 kQ RAIN VDDA HG DC DA PRI 79 ADC accuracy with Rain lt 10kO VDDA LARE NOE PIO ERA ORE 79 EMS data sse AS aed Lei ea a 82 EMI datas ined e ARR kk doe dpa e CUP Bere Saeed deb aee 82 ESD absolute maximum ratings 83 Electrical sensitivities eh 83 Thermal characteristics 0 0 nen 84 5 96 List of tables STM8S20xxx Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 6 96 Junction temperature range 1 6 m nh 85 80 pin low profile quad flat package mechanical data 87 64 pin low profile quad flat package mechanical data 10 x 10 88 48 pin low profile quad flat package mechanical data 89 44 pin low profile quad flat package mechanical data 90 32 pin low profile quad flat package mechanical data 91 Document revision history LL 95 STM8S20xxx List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure
24. TIM1_CCR2H TIM1 Capture Compare register 2 high 0x00 0x00 5268 TIM1_CCR2L TIM1 Capture Compare register 2 low 0x00 0x00 5269 TIM1_CCR3H TIM1 Capture Compare register 3 high 0x00 0x00 526A TIM1_CCR8L TIM1 Capture Compare register 3 low 0x00 0x00 526B TIM1_CCR4H TIM1 Capture Compare register 4 high 0x00 0x00 526C TIM1_CCR4L TIM1 Capture Compare register 4 low 0x00 0x00 526D TIM1_BKR TIM1 Break register 0x00 0x00 526E TIM1_DTR TIM1 Dead time register 0x00 0x00 526F TIM1_OISR TIM1 Output idle state register 0x00 peg Reserved area 147 bytes 42 96 IST STM8S20xxx Memory map Table 10 General hardware register map continued Address Block Register label Register name uad 0x00 5300 TIM2 CR1 TIM2 Control register 1 0x00 0x00 5301 TIM2 IER TIM2 Interrupt enable register 0x00 0x00 5302 TIM2_SR1 TIM2 Status register 1 0x00 0x00 5303 TIM2_SR2 TIM2 Status register 2 0x00 0x00 5304 TIM2_EGR TIM2 Event Generation register 0x00 0x00 5305 TIM2_CCMR1 TIM2 Capture Compare mode register 1 0x00 0x00 5306 TIM2_CCMR2 TIM2 Capture Compare mode register 2 0x00 0x00 5307 TIM2_CCMR3 TIM2 Capture Compare mode register 3 0x00 0x00 5308 TIM2_CCERI TIM2 Capture Compare enable register 1 0x00 0x00 5309 TIM2 CCER2 TIM2 Capture Compare enable register 2 0x00 0x00 530A TIM2 TIM2_CNTRH TIM2 Counter high 0x00 0x00 530B TIM2_CNTRL TI
25. VI Figure 35 T 5 o 5 z 60 40 C ao o 5 i M 25 C 85 C 20 125 C 0 T T T T T 0 1 2 3 4 5 6 Voo IVI The reset network shown in Figure 36 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below the Vj max level specified in Table 34 Otherwise the reset is not taken into account internally Figure 36 Recommended reset pin protection Vpp STM8 Rpu External NRST Internal reset reset e Filter circuit 0 01uF optional 73 96 Electrical characteristics STM8S20xxx 8 3 8 SPI serial peripheral interface Unless otherwise specified the parameters given in Table 39 are derived from tests performed under ambient temperature fysstErR frequency and Vpp supply voltage conditions tMASTER 1 MASTER Refer to I O port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 39 SPI characteristics Symbol Parameter Conditions Min Max Unit f Master mode 0 10 SCK SPI clock frequency MHz Ttcisck Slave mode 0 10 tick SPI clock rise and fall time Capacitive load C 30 pF 25 CK tsynss NSS setup time Slave mode A MASTER thuss NSS hold time Slave mode 70 1 W SCKH SCK high and low
26. X O1 X X Port B3 Analog input 3 orn TIM1_ 32 28 20 19 14 PB2 AIN2 O X X X O1 X X Port B2 Analog input CHS3N AFR5 TIM1_ 33 29 21 20 15 PB1 AIN1 VO X X X O1 X X Port B1 Analog input 1 CH2N AFR5 TIM1_ 34 30 22 21 16 PBO AINO O X X X O1 X X Port BO Analog input O CH1N AFR5 35 PH4 TIM1_ETR Vo X x O1 X x Port H4 Timer 1 trigger input IST 27 96 Pinouts and pin description STM8S20xxx Table 5 Pin description continued Pin number Input Output z ol t o tt ac o E x EE Default pes o ott Pin name SP E E v 5 alternate E E re e F ag gjaja 2 function remap colloca 5 E amp 2 9 S a option bit 43 34 34 4 4 s l 36 PHS vo Xx X O1 X X Port H5 or TIM1 CH3N SS channel 3 37 Cho 1 O X X O1 X X Port H6 E TIM1_CH2N Te channel 2 38 Rd 1 O X X O1 X X Port H7 B TIM1_CH1N n Vere channel 2 39 31 23 PE7 AIN8 I O O1 Port E7 Analog input 8 40 32 24 22 PEG AIN9 1 O X X O1 X X Port E6 Analog input 9 SPI 41 33 25 23 17 PE5 SPI_NSS O X X X O1 X X Port E5 imaster slave select 42 IPCUADC ETR IO X X X Ot X X PortCO eem Timer 1 43 34 26 24 18 PC1 TIM1_CH1 O X X X IHS OS X
27. device is described in Figure 11 Figure 11 Pin input voltage STM8 PIN STM8S20xxx Electrical characteristics 8 2 K Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 12 Voltage characteristics Symbol Ratings Min Max Unit Vppx Vss Supply voltage including Vopa and Vopio 0 3 6 5 Vin Input voltage on true open drain pins PE1 PE2 Vss 0 3 6 5 V Input voltage on any other pin Vss 0 3 Vpp 0 3 IVppx Vss Variations between different power pins 50 IVssx Vssl Variations between all the different ground pins 50 Te see Absolute maximum Vesp Electrostatic discharge voltage ratings electrical sensitivity on page 82 1 All power Vpp Vppio VppA and ground Vss Vssio Vssa pins must always be connected to the external power supply 2 liy piNy must never be exceeded This is implicitly insured if Vy maximum is respected If Vy maximum cannot be respected the injection current must be limited externally to the yi value A positive injection is induced by Viy gt Vpp while a negative injection is induced by Viy lt Vss there is no positive injection curren
28. ky 45 96 Memory map STM8S20xxx Table 10 General hardware register map continued Address Block Register label Register name mean 0x00 5420 CAN_MCR CAN Master Control Register 0x02 0x00 5421 CAN_MSR CAN Master Status Register 0x02 0x00 5422 CAN TSR CAN Transmit Status Register 0x00 0x00 5423 CAN TPR CAN Transmit Priority Register Ox0C 0x00 5424 CAN RFR CAN Receive FIFO Register 0x00 0x00 5425 CAN IER CAN Interrupt Enable Register 0x00 0x00 5426 CAN DGR CAN Diagnosis Register OxOC 0x00 5427 CAN FPSR CAN Page Selection Register 0x00 0x00 5428 CAN_PO CAN Paged Register 0 0x00 5429 CAN P1 CAN Paged Register 1 0x00 542A CAN P2 CAN Paged Register 2 0x00 542B CAN P3 CAN Paged Register 3 0x00 542C CAN_P4 CAN Paged Register 4 0x00 542D CAN_P5 CAN Paged Register 5 0x00 542E CAN_P6 CAN Paged Register 6 0x00 542F CAN_P7 CAN Paged Register 7 0x00 5430 CAN_P8 CAN Paged Register 8 0x00 5431 CAN_P9 CAN Paged Register 9 0x00 5432 CAN_PA CAN Paged Register A 0x00 5433 CAN_PB CAN Paged Register B 0x00 5434 CAN_PC CAN Paged Register C 0x00 5435 CAN_PD CAN Paged Register D 0x00 5436 CAN_PE CAN Paged Register E 0x00 5437 CAN_PF CAN Paged Register F a Reserved area 968 bytes 46 96 2 STM8S20xxx Memory map Table 11 CPU SWIM debug module interrupt controller registers
29. least with the temperature range suffix 6 Table 49 Junction temperature range Order codes Order codes with suffix 6 with suffix 3 Symbol Parameter Conditions for ios 9 ECT to Unit Min Max Min Max LQFP80 40 102 40 142 LQFP64 14 x14 40 105 40 145 LQFP64 10 x10 40 105 40 145 Ty Junction temperature range C LQFP48 40 110 40 150 LQFP44 40 108 40 149 LQFP32 40 106 40 146 85 96 Package characteristics STM8S20xxx 9 86 96 Package characteristics In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark STM8S20xxx Package characteristics 9 1 9 1 1 K Package mechanical data LQFP package mechanical data Figure 42 80 pin low profile quad flat package 14 x 14 D lt D1 61 80 Pin 1 Tai O ccc A A2 identification 4 A 20 c ahe aide Table 50 80 pin low profile quad flat package mechanical data mm inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 35
30. of the function 23 96 Pinouts and pin description STM8S20xxx Figure 6 LQFP 44 pin pinout NRST OSCIN PA1 OSCOUT PA2 Vssio 1 Vss VCAP Vpp Vppio 1 UART1 RX HS PA4 UART1 TX HS PAS TIM2 CH3 PD5 UART3_TX HS TIM2_CH1 BEEP HS TIM2_CH2 ADC_ETR TIM3_CH1 HS SWIM HSyTIM3 CH TIM1_BKIN CLK_CCO HS CLK_CCO T I2C_SCL T I2C_SDA PD6 UART3_RX HS PD4 PD3 PD2 PD1 PDO PEO PE1 PE2 R w R N R zu B o w 0 w o w N w o w u w 80 PD7 TLI TIM1_CH4 NOOOGOGOR ooh Ww OONDDNUROND o0 PG1 PGO PC7 HS SPI_MISO PC6 HS SPI_MOSI Vpbpio 2 Vssio 2 PC5 HS SPI SCK PC3 HS TIM1_CH3 PC2 HS TIM1_CH2 PC1 HS TIM1_CH1 UART1_CK HS PA6 PE5 SPI_NSS 12131415161718192021 22 Ire VAO mannaa ooaaoaga DFAA ZZZzzz lt Arzzz FOULIET ol 16060 N gt a z EZZZ EEE 1 HS high sink capability 2 T True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function 2 STM8S20xxx
31. the function 2 STM8S20xxx Pinouts and pin description K Figure 5 LQFP 48 pin pinout NRST OSCIN PA1 OSCOUT PA2 Vssio 1 Vss VCAP Vpp Vppio 1 TIM3_CH1 TIM2_CH3 PA3 UART1_RX HS PA4 UART1_TX HS PAS UART1_CK HS PA6 Q Q 9 x sand 9 co z I Y m o m n ugs E DEE E F rar No 5 6660 689 O LAXE 1998 lgJezzzzMOOxX EBRBEEEDEOQQ l LLION DSSS ESOLLIILIIIEEL hooxoa oor ao OP aoGoonouLl uim aacaaanaooaa L1 4847 4645 44 4342414039 38 37 Ole 360PGI 2 350 PGO 3 340 PC7 HS SPI_MISO 4 330 PC6 HS SPI_MOSI 5 320 Vppio_2 6 310 Vssio 2 7 301 PC5 HS SPI_SCK 8 29H PC4 HS TIM1_CH4 d9 28H PC3 HS TIM1_CH3 10 27H PC2 HS TIM1_CH2 7 261 PC1 HS TIM1_CH1 012 250 PE5 SPI_NSS 13 14 1516 17 1819 2021 222324 I 6 5 4 N5 PB N4 PB N3 PB3 N2 PB2 N1 PB1 NO PBO l2C_SDA A l2C_SCL A TIM1_ETR A TIM1_CHSN A TIM1_CH2N A TIM1_CH1N A 1 HS high sink capability 2 T True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication
32. time including t SONY sampling time 10 bit resolution fanc 6 MHz 2 33 hS 14 1 fapc 1 Data guaranteed by design not tested in production 2 During the sample time the input capacitance C ay 3 pF max can be charged discharged by the external Source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within ts After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result Values for the sample clock tg depend on programming 2 STM8S20xxx Electrical characteristics K Table 42 ADC accuracy with RAIN lt 10 kQ RAIN VppA 3 3 V Symbol Parameter Conditions Typ Max Unit fADC 2 MHz 1 1 2 lETI Total unadjusted error fADC 4 MHz 1 6 2 5 fADC 2 MHz 0 7 1 5 IEol Offset error fapc 4 MHz 1 3 2 fADC 2 MHz 0 2 1 5 lEc Gain error LSB fADC 4 MHz 0 5 2 fADC 2 MHz 0 7 1 IEpl Differential linearity error fADC 4 MHz 0 7 1 fADC 2 MHz 0 6 1 5 IELl Integral linearity error fADC 4 MHZ 0 6 1 5 Table 43 ADC accuracy with Rain lt 10 kQ VppA 5 V Symbol Parameter Conditions Typ Max Unit fADC 2 MHz 1 2 5 IET Total unadjusted error fApc 4 MHz 1 4 3 fapc 6 MHz 1 6 3 5 fapc 2 MHz 0 6 2 IEol Offset error 2 fApc 4 MHz 1 1 2 5 fADC 6 MHz 1
33. to bootloader vector RESETBL fetch 150 us 1 Data guaranteed by design not tested in production 60 96 2 STM8S20xxx Electrical characteristics Current consumption of on chip peripherals Subject to general operating conditions for Vpp and Ty HSI internal RC fcpu fmaster 16 MHz Table 27 Peripheral current consumption Symbol Parameter Typ Ippctim1 TIM1 supply current 220 Ippctimz TIM2 supply current 120 Ipp rim3 TIM3 timer supply current 7 100 Ippctima TIM4 timer supply current 25 IDD UART1 UART1 supply current 2 90 IDD UART3 UART3 supply current 2 110 IDD SPI SPI supply current 40 Ipp c I C supply current 2 50 Ibocan CAN supply current 2 210 Ipp apc2 ADC2 supply current when converting 1000 Unit pA 1 Data based on a differential Ipp measurement between reset configuration and timer counter running at 16 MHz No IC OC programmed no I O pads toggling Not tested in production 2 Data based on a differential Ipp measurement between the on chip peripheral when kept under reset and not clocked and the on chip peripheral when clocked and not kept under reset No I O pads toggling Not tested in production 3 Data based on a differential Ipp measurement between reset configuration and continuous A D conversions Not tested in production Current consumption curves Figure 14 and Figu
34. user ext clock 16 MHz 1 2 4 101 from RAM fcPU fvasteR 1 28 125 kHz HSI RC osc 16 MHz 10 130 fcPU fmaster 1 28 15 625 kHz HSI RC osc 16MHz 8 0 55 fopu fuasteR 128 kHz LSI RC osc 128 kHz 0 45 IDD RUN T mA fopu fmaster 24 MHz HSE crystal osc 24 MHz 11 0 TA x 105 C HSE user ext clock 24 MHz 10 8 TBD HSE crystal osc 16 MHz 8 4 Supply a current in fcPU fMASTER 16 MHz HSE user ext clock 16 MHz 8 2 15 2 run mode HSI RC osc 16 MHz 81 13 2 1 code executed fcPU fMASTER 2 MHz HSI RC osc 16 MHz 8 2 1 5 from Flash fopu fmasteR 128 125 kHz HSI RC osc 16 MHz 1 1 fopy fmaster 1 28 15 625 kHz HSI RC osc 16 MHz 8 0 6 fopu fuasteR 128 kHz LSI RC osc 128 kHz 0 55 1 Data basedon characterization results not tested in production 2 Default clock configuration 56 96 2 STM8S20xxx Electrical characteristics Total current consumption in wait mode Table 19 Total current consumption in Wait mode at Vpp 5 0 V Symbol Parameter Conditions Typ Max Unit fopu fmaster 24 MHz HSE crystal osc 24 MHz 2 4 Ta lt 105 C HSE user ext clock 24 MHz 1 8 TBD HSE crystal osc 16 MHz 2 0 Supply fopu fmaster 16 MHz HSE user ext clock 16 MHz 1 4 TBD Ipp wri current in HSI RC osc 16 MHz 12 1 6 mA vane fopu fuAsTER
35. without losing data stored in RAM in halt mode or under reset or in hardware registers only in halt mode Guaranteed by design not tested in production refer to Table 16 on page 54 for the value of Vir may Flash program memory data EEPROM memory General conditions T4 40 to 125 C Table 33 Flash program memory data EEPROM memory Symbol Parameter Conditions Min Typ Max Unit Operating voltage all modes execution write erase foru lt 24 MHz 299 3 9 y Standard programming time including erase for byte word block 6 6 6 ms t 1 byte 4 bytes 128 bytes Fast programming time for 1 block 128 bytes terase Erase time for 1 block 128 bytes 3 3 3 ms Erase write cycles Ta 85 C 10k program memory cycles Erase write cycles data memory 2 Ta 125 C 300k 1M Data retention program memory after 10k erase write cycles Tret 55 C 20 at TA 85 C Data retention data memory after tret 10k erase write cycles Tret 55 C 20 years at Ta 85 C Data retention data memory after 300k erase write cycles Tret 85 C 1 at Ty 4125 C Supply current Flash programming or lbp erasing for 1 to 128 bytes 1 Data based on characterization results not tested in production 2 The physical granularity of the memory is 4 bytes so cycling is performed on 4 bytes even when a write erase operation addresses a single byte
36. 0 1 400 1 450 0 0531 0 0551 0 0571 b 0 220 0 320 0 380 0 0087 0 0126 0 0150 C 0 090 0 200 0 0035 0 0079 D 15 800 16 000 16 200 0 6220 0 6299 0 6378 D1 13 800 14 000 14 200 0 5433 0 5512 0 5591 D3 12 350 0 4862 E 15 800 16 000 16 200 0 6220 0 6299 0 6378 E1 13 800 14 000 14 200 0 5433 0 5512 0 5591 E3 12 350 0 4862 e 0 650 0 0256 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 100 0 0039 1 Values in inches are converted from mm and rounded to 4 decimal digits 87 96 Package characteristics STM8S20xxx Figure 43 64 pin low profile quad flat package 10 x 10 lt D 49 D1 D3 gt O coc C 17 eJ 5W ME Table 51 64 pin low profile quad flat package mechanical data 10 x 10 mm inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 C 0 090 0 200 0 0035 0 0079 D 12 000 0 4724 D1 10 000 0 3937 E 12 000 0 4724 E1 10 000 0 3937 0 500 0 0197 K 0 000 3 500 7 000 0 0000 3 5000 7 0000 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 1 Values in inches are converted from mm and rounded to 4 decimal digits 2 STM8S20xxx Package characteristics Figure 44 48 pin low profile quad fla
37. 00 k write erase cycles A High system integration level with internal clock oscillators watchdog and brown out reset e Performance and robustness 20MIPS at 24 MHz CPU clock frequency Robust I O independent watchdogs with separate clock source Clock security system Short development cycles Applications scalability across a common family product architecture with compatible pinout memory map and and modular peripherals Full documentation and a wide choice of development tools e Product longevity Advanced core and peripherals made in a state of the art technology Afamily of products for applications with 2 95 to 5 5 V operating supply Table 2 STM8S20xxx performance line features 2 gt 0 gt Q e V 5 T amp 2 E E E 5 8 E 2 5 2 9 EE g S 3 28 z 2 2 2 CER S Device 3 E 21512 2 Sse 9 5 c 2 o 2 c os Q z a E lt 2 DET ul 4 lt oO o I a LU tr o o ul a S E z E S E 4 iL STM8S207MB 80 68 37 9 12 16 18 128K 2048 6K STM8S207RB 64 52 36 9 12 16 16 128K 2048 6K STM8S207R8 64 52 36 9 12 16 16 64K 1536 4K STM8S207R6 64 52 36 9 12 16 16 32K 1024 2K STM8S207CB 48 38 35 9 12 10 16 128K 2048 6K STM8S207C8 48 38 35 9 12 10 16 64K 1536 4K STM8S207S8 44 34 31 8 11 9 15 64K 1536 4K STM8S207C6 48 38 35 9 12 10 16 32K 1024 2K STM8S207S6 44 34 31 8 11 9 15 32K 1024 2K STM
38. 06h NOPT3 Reserved _EN w HW HALT FFh EXT CKAWU PRS PRS 4807h OPT4 Reserved CLK SEL C1 CO 00h Clock option NEXT NCKAWUS NPR NPR 4808h NOPT4 Reserved CLK EL SC1 SCO FFh 4809h HSE clock OPT5 HSECNT 7 0 00h 480Ah Startup NOPT5 NHSECNTI7 0 FFh 480Bh OPT6 Reserved 00h Reserved 480Ch NOPT6 Reserved FFh 480Dh Flash wait OPT7 Reserved Wait state 00h 480En _ States NOPT7 Reserved Nwait state FFh 487Eh OPTBL BL 7 0 00h Bootloader 487Fh NOPTBL NBL 7 0 FFh 32 96 ky STM8S20xxx Option bytes Table 7 Option byte description Option byte no OPTO Description ROP 7 0 Memory readout protection ROP OxAA Enable readout protection write access via SWIM protocol Note Refer to the family reference manual RM0016 section on Flash EEPROM memory readout protection for details OPT1 UBC 7 0 User boot code area 0x00 no UBC no write protection 0x01 Pages 0 to 1 defined as UBC memory write protected 0x02 Pages 0 to 3 defined as UBC memory write protected 0x03 Pages 0 to 4 defined as UBC memory write protected OxFE Pages O0 to 255 defined as UBC memory write protected OxFF Reserved Note Refer to the family reference manual RM0016 section on Flash EEPROM write protection for more details OPT2 AFR7Alternate function remapping option 7 0 Port D4 alternate function TIM2_CH1 1 Port D4 alternate function BEEP AFR6 Alternate function remapping option 6 0 Port B5 alternate function AIN
39. 0x00 4000 0x00 47FF Data EEPROM 1536 0x00 4000 0x00 45FF 1024 0x00 4000 0x00 43FF 7 1 Register map Table 9 I O port hardware register map Address Block Register label Register name Rese status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0x00 0x00 5002 Port A PA_DDR Port A data direction register 0x00 0x00 5003 PA CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0x00 0x00 5007 Port B PB_DDR Port B data direction register 0x00 0x00 5008 PB CHR1 Port B control register 1 0x00 0x00 5009 PB CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PB_IDR Port C input pin value register 0x00 0x00 500C Port C PC_DDR Port C data direction register 0x00 0x00 500D PC CR1 Port C control register 1 0x00 0x00 500E PC CR2 Port C control register 2 0x00 36 96 ky STM8S20xxx Memory map 2 Table 9 I O port hardware register map continued Address Block Register label Register name ci 0x00 500F PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0x00 0x00 5011 Port D PD_DDR Po
40. 10 12 14 0 5 10 15 20 25 lo mA lon MA ki 71 96 Electrical characteristics STM8S20xxx 8 3 7 Reset pin characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified Table 38 NRST pin characteristics Symbol Parameter Conditions Min Typ 1 Max Unit ViL NRST NRST Input low level voltage 1 0 3 V 0 3 x Vpp ViH NRST NRST Input high level voltage 0 7 x Vpp Vpp 0 3 V VotNRST NRST Output low level voltage 1 lo 2 mA 0 5 Reu NRST NRST Pull up resistor 30 60 kQ rP NRST NRST Input filtered pulse 9 75 ns tinFP NRST NRST Input not filtered pulse 9 500 ns toP NRST NRST output pulse 20 us 1 Data based on characterization results not tested in production 2 The Rpy pull up equivalent resistor is based on a resistive transistor 3 Data guaranteed by design not tested in production Figure 33 Typical NRST Vj and Vj vs Vpp 4 temperatures 40 C i a 25 C 8 85 C 125 C 72 96 Vi Vin V w 2 5 3 Voo V 2 STM8S20xxx Electrical characteristics Figure 34 Typical NRST pull up resistance Rp vs Vpp 4 temperatures 60 40 C m 25 C E 55 85 C B 125 C o 50 2 S _ _ _ a_er_ _ _ _ _ e 8 45 x 3 40 B Lr C 35 30 2 5 3 3 5 4 4 5 5 5 5 6 Voo
41. 11 800 12 000 12 200 0 4646 0 4724 0 4803 D1 9 800 10 000 10 200 0 3858 0 3937 0 4016 D3 8 000 0 3150 E 11 800 12 000 12 200 0 4646 0 4724 0 4803 E1 9 800 10 000 10 200 0 3858 0 3937 0 4016 E3 8 000 0 3150 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 100 0 0039 2 STM8S20xxx Package characteristics Figure 46 32 pin low profile quad flat package 7 x 7 5V ME Table 54 32 pin low profile quad flat package mechanical data mm inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 C 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 600 0 2205 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 600 0 2205 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 100 0 0039 1 Values in inches are converted from mm and rounded to 4 decimal digits Ky 91 96 STM8 development tools STM8S20xxx 10 10 1 92 96 STM8 development tools Development tools for the STM8 microcontrollers include the full featured STice emulation system supported by a complete software tool package including C compi
42. 2 STM8S20xxx Electrical characteristics 8 3 6 I O port pin characteristics General characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor Table 34 1 O static characteristics Symbol Parameter Conditions Min Typ Max Unit Input low level ViL voltage 0 3 0 3 x Vpp V Input high level Vpp 5 0 V Vin voltage 0 7 x Vpp Vpp 0 3 V V Viys Hysteresis 700 mV Rou _ Pull up resistor Vpp 5 V Vin Vss 30 45 60 kQ Fast I Os 20 ns te te Rise and fall time Load 50 pF R F 10 90 Standard and high sink I Os 125 ns Load 50 pF Input leakage likg current VssSViNSVpp 1 2 yA analog and digital Analog input lt V lt 2 Ikgana leakage current VssSVinSVop 250 nA Leakage current in Injection current 4 mA 1 uA kin adjacent I O 1 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested in production 2 Data based on characterization results not tested in production K 67 96 Electrical characteristics STM8S20xxx 68 96 Figure 20 Typical Vj and Vj vs Vpp 4 temperatures 6 E 40 C 5 m 25 C 85 C 4 125 C Vi Vin V 2 5 3 8 5
43. 2 2 5 fapc 2 MHz 0 2 2 IEgl Gain error 2 fADC 4 MHz 0 6 2 5 LSB fADC 6 MHz 0 8 2 5 fADC 2 MHz 0 7 1 5 IED Differential linearity error fApc 4 MHz 0 7 1 5 fADC 6 MHz 0 8 1 5 fADC 2 MHz 0 6 1 5 IE I Integral linearity error fApc 4 MHz 0 6 1 5 fapc 6 MHZ 0 6 1 5 1 Data based on characterisation results for LQFP80 device with Vpgre Vngr not tested in production 2 ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for Iny in and YliNj piN in Section 8 3 6 does not affect the ADC accuracy 79 96 Electrical characteristics STM8S20xxx Figure 40 ADC accuracy characteristics A i EG 1003 D ek eee c Re home pio bo 1022 4i gg VppA ssa IDEAL 1024 1021 F i aa 1 2 QU ow 2 ET R gt N i 74 1 E a 1 7a 1 SA ti i 5 4 L 4 D 4 Fo d 4 EL 3 3 1 el dc i Wr VPP E i 24 nel gt i vi 2 2 1 LSBiDEAL Kp ty 0 2 3 4 5 6 7 1021102210231024 Vssa DDA 1 Exampleofan actual transfer c
44. 4 4 5 5 5 5 6 Voo VI Figure 21 Typical pull up resistance Rpy vs Vpp 4 temperatures 60 u u u o Pull Up resistance k ohm A u 40 40 C 25 C 35 85 C 125 C 30 4 2 5 3 8 5 4 4 5 5 5 5 6 Von V Figure 22 Typical pull up current ly vs Vpp 4 temperatures 140 120 100 lt 5 80 E 40 3 60 40 C 2 E 25 C amp 40 85 C 20 125 C 0 1 2 3 4 5 6 Vop VI 1 The pull up is a pure resistor slope goes through 0 2 STM8S20xxx Electrical characteristics Table 35 Output driving current standard ports Symbol Parameter Conditions Min Max Unit Output low level with 4 pins sunk lio 4 mA Vpp 3 3 V 109 VoL Output low level with 8 pins sunk lo 10 mA Vpp 5 0 V 2 M Output high level with 4 pins sourced ljg 4 mA Vpp 3 3 V 2 400 You Output high level with 8 pins sourced lig 10 mA Vpp 5 0 V 2 8 d 1 Data based on characterization results not tested in production Table 36 Output driving current true open drain ports Symbol Parameter Conditions Min Max Unit lio 10 mA Vpp 3 3 V 1 50 VoL Output low level with 2 pins sunk lio 10 mA Vpp 5 0 V 1 V lio 20 MA Vpp 5 0 V 20 1 Data based on characterization results not tested in production Table 37 Output driving
45. 5 port B4 alternate function AIN4 1 Port B5 alternate function I2C_SDA port B4 alternate function FC SCL AFRB5 Alternate function remapping option 5 0 Port B3 alternate function AIN3 port B2 alternate function AIN2 port B1 alternate function AIN1 port BO alternate function AINO 1 Port B3 alternate function TIM1_ETR port B2 alternate function TIM1 CHSN port B1 alternate function TIM1 CH2N port BO alternate function TIM1_CH1N AFRA Alternate function remapping option 4 0 Port D7 alternate function TLI 1 Port D7 alternate function TIM1 CH4 AFRS3 Alternate function remapping option 3 0 Port DO alternate function TIM3_CH2 1 Port DO alternate function TIM1_BKIN AFR2 Alternate function remapping option 2 0 Port DO alternate function TIM3_CH2 1 Port DO alternate function CLK_CCO Note AFR2 option has priority over AFR3 if both are activated AFR1 Alternate function remapping option 1 0 Port A3 alternate function TIM2_CH3 port D2 alternate function TIM3_CH1 1 Port A3 alternate function TIM3_CH1 port D2 alternate function TIM2_CH3 AFRO Alternate function remapping option 0 0 Port D3 alternate function TIM2_CH2 1 Port D3 alternate function ADC_ETR K 33 96 Option bytes STM8S20xxx 34 96 Table 7 Option byte description continued Option byte no OPT3 Description LSI_EN Low speed internal clock enable 0 LSI clock is not available as CPU clock sourc
46. 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 ky STM8S20xxx performance line block diagram 10 Flash memory organization 0 ce rn 13 LOFP 80 pin pinolit iu cius ea ees E ee ee 21 LQFP 64 pin pinout LL 22 EQFP 48 pin pinout ree med hr Sl bed x E IX dE RYE RET E 23 LQFP 44 pin pinout i ssssssasasasakaaaaaakaa aaa rrr 24 LOFP 32 pin pinout mele cre Ras e yw hy Fat Rd x yes Pade eR EN ER RR be 25 Memory Wap usse eed aos cmm PORE ee be RUE pom RUE ba eee ee 35 Supply current measurement conditions 49 Pin loading conditions 2 nw nais n abs K R MSK RI n 50 Pin input voltage susci A Ier ede Ee Rd Re a 50 cPUmax Versus VDD ETT 53 External capacitor iii eee Due De p ee do i 54 Typ IDD RUN vs VDD usi Rc osc CPU 16 MHZ 61 Typ IDD WFI vs VDD usi RC ose CPU 16 MHZ 61 HSE external clock source 1 2 sa saka aaa akak aaa kakak kaka aaa 62 HSE oscillator circuit diagram 2 0 sasa sanak raak kaa aaa 63 Typical HSI frequency vs Vpp 4 tempe
47. 8S207K6 32 25 23 8 11 7 12 32K 1024 2K STM8S208MB 80 68 37 9 12 16 18 128K 2048 6K Yes STM8S208RB 64 52 37 9 12 16 16 128K 2048 6K 1 Including complementary outputs IST 9 96 Block diagram STM8S20xxx 3 10 96 Block diagram Figure 1 STM8S20xxx performance line block diagram Reset a Single wire debug interf e 92 400 Kbit s 4 10 Mbit s K LIN master LJ SPI emul L1 Master slave N autosynchro K gt 1 Mbit s lt 16 channels 1 2 4 kHz beep lt Reset block XTAL 1 24 MHz Clock controller Reset RC int 16 MHz Detector FOR BOR RC int 128 kHz Clock to peripherals and core lt gt Window WDG STM8 CORE lt gt E Independent WDG Debug SWIM lt gt Up to 128 Kbytes lt gt high density program Flash PC lt D lt gt Up to 2 Kbytes 2 data EEPROM a E Up to 6 Kbytes SPI lt gt 5 lt gt BAS Ko S 5 gt Boot ROM UART1 o o o o lt x EIS 16 bit advanced control UART3 lt gt timer TIM1 16 bit general purpose beCAN lt gt timers TIM2 TIM3 8 bit basic timer ADC2 gt TIMA Beeper gt lt gt AWU timer V Up to 9 CAPCOM gt channels 5 2 STM8S20xxx Product overview 4 4 1 Product overview The following
48. EEPROM e Read while write Writing in data memory possible while executing code in program memory e User option byte area Write protection WP Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction There are two levels of write protection The first level is known as MASS Memory Access Security System MASS is always enabled and protects the main Flash program memory data EEPROM and option bytes To perform In Application Programming IAP this write protection can be removed by writing a MASS key sequence in a control register This allows the application to write to data EEPROM modify the contents of main program memory or the device option bytes A second level of write protection can be enabled to further protect a specific area of memory known as UBC user boot code Refer to Figure 2 The size of the UBC is programmable through the UBC option byte Table 7 in increments of 1 page by programming the UBC option byte in ICP mode This divides the program memory into two areas e Main program memory Up to 128 Kbytes minus UBC e User specific boot code UBC Configurable up to 128 Kbytes The UBC area remains write protected during in application programming This means that the MASS keys do not unlock the UBC area It protects the memory used to store the boot program specific code libraries reset and inter
49. M2 Counter low 0x00 00 530C0x TIM2_PSCR TIM2 Prescaler register 0x00 0x00 530D TIM2_ARRH TIM2 Auto reload register high OxFF 0x00 530E TIM2 ARRL TIM2 Auto reload register low OxFF 0x00 530F TIM2 CCR1H TIM2 Capture Compare register 1 high 0x00 0x00 5310 TIM2 CCR1L TIM2 Capture Compare register 1 low 0x00 0x00 5311 TIM2 CCR2H TIM2 Capture Compare reg 2 high 0x00 0x00 5312 TIM2 CCR2L TIM2 Capture Compare register 2 low 0x00 0x00 5313 TIM2 CCR3H TIM2 Capture Compare register 3 high 0x00 0x00 5314 TIM2 CCR3L TIM2 Capture Compare register 3 low 0x00 LL Reserved area 11 bytes ky 43 96 Memory map STM8S20xxx Table 10 General hardware register map continued Address Block Register label Register name an 0x00 5320 TIM3_CR1 TIM3 Control register 1 0x00 0x00 5321 TIM3_IER TIMS Interrupt enable register 0x00 0x00 5322 TIM3_SR1 TIM3 Status register 1 0x00 0x00 5323 TIM3_SR2 TIM3 Status register 2 0x00 0x00 5324 TIM3_EGR TIM3 Event Generation register 0x00 0x00 5325 TIM3 CCMR 1 TIM3 Capture Compare mode register 1 0x00 0x00 5326 TIM3 CCMR2 TIM3 Capture Compare mode register 2 0x00 0x00 5327 TIM3_CCERI TIM3 Capture Compare enable register 1 0x00 0x00 5328 TIM3 TIM3_CNTRH TIM3 Counter high 0x00 0x00 5329 TIM3_CNTRL TIM3 Counter low 0x00 0x00 532A TIM3_PSCR TIM3 Prescaler register 0x00 0x00 532B TI
50. M3_ARRH TIMS Auto reload register high OxFF 0x00 532C TIM3 ARRL TIMS Auto reload register low OxFF 0x00 532D TIM3_CCR1H TIM3 Capture Compare register 1 high 0x00 0x00 532E TIM3 CCR1L TIM3 Capture Compare register 1 low 0x00 0x00 532F TIM3_CCR2H TIM3 Capture Compare register 2 high 0x00 0x00 5330 TIM3_CCR2L TIM3 Capture Compare register 2 low 0x00 puce Reserved area 15 bytes 0x00 5340 TIM4_CR1 TIM4 Control register 1 0x00 0x00 5341 TIM4 IER TIM4 Interrupt enable register 0x00 0x00 5342 TIM4 SR TIMA Status register 0x00 0x00 5343 TIM4 TIM4_EGR TIM4 Event Generation register 0x00 0x00 5344 TIM4_CNTR TIM4 Counter 0x00 0x00 5345 TIM4_PSCR TIM4 Prescaler register 0x00 0x00 5346 TIM4_ARR TIM4 Auto reload register OxFF 2 Reserved area 185 bytes 44 96 ky STM8S20xxx Memory map Table 10 General hardware register map continued Address Block Register label Register name Reset status 0x00 5400 ADC _CSR ADC Control Status Register 0x00 0x00 5401 ADC_CRI ADC Configuration Register 1 0x00 0x00 5402 ADC CR2 ADC Configuration Register 2 0x00 0x00 5403 ABS ADC_CR3 ADC Configuration Register 3 0x00 2 0x00 5404 ADC_DRH ADC Data Register High undefined 0x00 5405 ADC_DRL ADC Data Register Low undefined 0x00 5406 ADC_TDRH ADC Schmitt Trigger Disable Register High 0x00 0x00 5407 ADC_TDRL ADC Schmitt Trigger Disable Register Low 0x00 0x00 5408 to 0x00 541F Reserved area 24 bytes
51. P external capacitor Stabilization for the main regulator is achieved using an external capacitor via the VcAp pin The typical value is 470 nF with low equivalent series resistance ESR Care should be taken to limit the series inductance per pad to less than 15 nH Figure 13 External capacitor ESR Where ESR is the equivalent series resistance ESL is the equivalent inductance The typical value of C is 470 nF with an ESR between 0 05 0 2 Ohm ESL 2 STM8S20xxx Electrical characteristics 8 3 2 Supply current characteristics The current consumption is measured as described in Figure 9 on page 49 Total current consumption in run mode The MCU is placed under the following conditions e AIIl O pins in input mode with a static value at Vpp or Vas no load e Allperipherals are disabled clock stopped by Peripheral Clock Gating registers except if explicitly mentioned e When the MCU is clocked at 24 MHz T4 x 105 C and the WAITSTATE option bit is set Subject to general operating conditions for Vpp and Ta Table 17 Total current consumption with code execution in run mode at Vpp 5 0 V Symbol Parameter Conditions Typ Max Unit fopu fmaster 24 MHz HSE crystal osc 24 MHz 4 4 Ta lt 105 C HSE user ext clock 24 MHz 3 7 7 001 HSE crystal osc 16 MHz 3 3 Supply current in fcpu fuasrER 16 MHz HSE user ex
52. SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2009 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 2 96 96
53. X X O1 X X Port H2 16 PH3 1 O X X O1 X X Port H3 26 96 IST STM8S20xxx Pinouts and pin description Table 5 Pin description continued Pin number Input Output oe g 5 x 9 3 Default Paoli Gio S Pin name 2 Bg E v 3t alternate E E Des e C a 2 2 as 2 function remap lolol 53 EIS af option bit AJ Hd 44 d E Ss x ui 17 13 PF7 AIN15 vo x x 01 X X Port F7 iu input 18 14 PF6 AIN14 O X X O1 X X Port F6 ue input 19 15 PF5 AIN13 o X X O1 X X Port F5 N input 20 16 8 PFA AIN12 O X X O1 X X Port F4 Fi input 21 17 PF3 AIN11 O X X O1 X X Port F3 Pn input ADC positive reference di ia VREF 9 voltage 23 19 13 12 9 VppA Analog power supply 24 20 14 13 10 Vssa Analog ground 25 21 Vegg S ADC negative reference voltage 26 22 PFO AIN10 O X X O1 X X Port FO ee input 27 23 15 14 PB7 AIN7 1 O X X O1 X X Port B7 Analog input 7 28 24 16 15 PB6 AIN6 y o O1 Port B6 Analog input 6 IC SDA 29 25 17 16 11 PB5 AIN5 VO X X X O1 X X Port B5 Analog input 5 AFR6 lc SCL 30 26 18 17 12 PB4 AIN4 1 O X X X O1 X X Port B4 Analog input 4 AFR6 31 27 19 18 13 PB3 AIN3 VO X X
54. a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 1000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application 81 96 Electrical characteristics STM8S20xxx Software recommendations The software flowchart must include the management of runaway conditions such as e Corrupted program counter e Unexpected reset e Critical data corruption control registers Prequalification trials Most of the common failures unexpected reset and program counter corruption can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application not
55. aneously mW or Ta 125 C for suffix 3 32 pin package with output on 8 standard ports and 2 360 high sink ports simultaneously Ambient temperature for 6 Maximum power dissipation 40 85 C suffix version Low power dissipation 40 105 C TA Ambient temperature for 3 Maximum power dissipation 40 125 C suffix version Low power dissipation 40 140 C Ty Junction temperature range See Table 49 1 Refer to Section 8 4 Thermal characteristics on page 84 for the calculation method 2 In low power dissipation state TA can be extended to this range as long as Tj does not exceed Tmax see Section 8 4 Thermal characteristics on page 84 Figure 12 fcpumax Versus Vpp fopu MHz FUNCTIONALITY GUARANTEED Ty 40 to 105 C FUNCTIONALITY GUARANTEED T4 40 to 125 C FUNCTIONALITY NOT GUARANTEED IN THIS AREA 2 95 4 0 50 55 SUPPLY VOLTAGE V 53 96 Electrical characteristics STM8S20xxx 8 3 1 54 96 Table 16 Operating conditions at power up power down Symbol Parameter Conditions Min Typ Max Unit Vpp rise time rate 2 1 o0 lypp us V Vpp fall time rate 2 1 oo tTEMP LL REA Vpp rising 1 700 ms Power on reset Vit threshold 2 65 2 8 2 95 V Brown out reset Vit threshold 2 58 2 73 2 88 V Brown out reset VHYS BOR hysteresis H ii 1 Guaranteed by design not tested in production VCA
56. atic discharges 3 positive then 3 negative pulses separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin This test conforms to the JESD22 A114A A115A standard For more details refer to the application note AN1181 Table 46 ESD absolute maximum ratings Maxim Symbol Ratings Conditions Class value Unit Electrostatic discharge voltage TA 25 C conforming V ESD HBM Human body model to JESD22 A114 eee Electrostatic discharge voltage Ta 25 C conforming to V ESD CDM Charge device model JESD22 C101 d 1900 V 1 Data based on characterization results not tested in production Static latch up Two complementary static tests are required on 10 parts to assess the latch up performance e A supply overvoltage applied to each power supply pin and e A current injection applied to each input output and configurable I O pin are performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 47 Electrical sensitivities Symbol Parameter Conditions Class Ta 25 C A LU Static latch up class Ta 85 C A Ty 125 C A 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC spec
57. b ssssksskakasa russda asas 51 Current characteristics 2 2sasa sasaran akka aa akka aaa 52 Thermal characteristics LL 52 General operating conditions sss sasa saak akka kakak aa aaa 53 Operating conditions at power up power down sse 54 Total current consumption with code execution in run mode at Vpp 2 5 0V 55 Total current consumption with code execution in run mode at Vpp 2 3 3 V 56 Total current consumption in Wait mode at Vpp 5 0 V 00 02 57 Total current consumption in Wait mode at Vpp 3 3 V lala alana 57 Total current consumption in active halt mode at Vpp 5 0 V Ta 40 to 85 C 58 Total current consumption in active halt mode at Vpp 2 3 8 V 1 1 1 1222222 22 2 58 Total current consumption in halt mode at Vpp 5 0 V TA 40t0 85 C 59 Total current consumption in halt mode at Vpp 3 3 VV 59 WakeUp timeS s kan S s s k S ete eee 60 Total current consumption and timing in forced reset state 60 Peripheral current consumption 2 sss skaka n 61 HSE user external clock characteristics 62 HSE oscillator characteristics 0 00 00 ccc ren 63 HSI oscillator characteristics 0 0 0 0 lille ren 64 LSI oscillator characteristics LL 65 RAM and hardware registers 00 ec eee 66 Flash program memory data EEPROM Memory 66 I O static characteristics LL
58. ction environments programmers will include a complete range of gang and automated programming solutions from third party tool developers already supplying programmers for the STM8 family 93 96 Ordering information STM8S20xxx 11 94 96 Ordering information Figure 47 STM8S207 208xx performance line ordering information scheme Example Product class STM8 microcontroller Family type S Standard Sub family type 208 full peripheral set 207 intermediate peripheral set Pin count K 32 pins S 44 pins C 48 pins R 64 pins M 80 pins Program memory size 6 32K 8 64K B 128K Package type T LQFP Temperature range 3 40 C to 125 C 6 40 C to 85 C Package pitch no character 0 5 mm B 0 65 mm C 0 8 mm Packing no character tray or tube TR tape and reel S 208 M B 1 6 B For a list of available options e g memory size package and orderable part numbers or for further information on any aspect of this device please go to www st com or contact the ST Sales Office nearest to you ky STM8S20xxx Revision history 12 K Revision history Table 55 Document revision history Date 23 May 2008 Revision 1 Changes Initial release 05 Jun 2008 Added part numbers on page 1 and in Table 2 on page 9 Updated Section 4 Product overview Updated Secti
59. current high sink ports Symbol Parameter Conditions Min Max Unit Output low level with 4 pins sunk lio 10 mA Vpp 3 3 V 100 VoL Output low level with 8 pins sunk lio 10 mA Vpp 5 0 V 0 8 Output low level with 4 pins sunk lio 20 mA Vpp 5 0 V 1 50 y Output high level with 4 pins sourced lio 10 mA Vpp 3 3 V 2 10 Vou Output high level with 8 pins sourced lio 10 mA Vpp 5 0 V 4 0 Output high level with 4 pins sourced lio 20 mA Vpp 5 0 V 3 30 1 Data based on characterization results not tested in production K 69 96 Electrical characteristics STM8S20xxx Typical output level curves Figure 23to Figure 32 show typical output level curves measured with output on a single pin Figure 23 Typ Vor 9 Vpp 3 3 V standard Figure 24 Typ Vor Vpp 5 0 V standard ports ports 15 40 C 15 aG 25 C nm 25 C 1 25 85 C 1 25 85 C 125 C 125 C 1 0 75 0 5 2 0 25 0 7 0 2 4 6 8 10 12 lo mA lo mA Figure 25 Typ Vor 8 Vpp 3 3 V true open drain ports Figure 26 Typ VoL 8 Vpp 5 0 V true open drain ports 2 40 C 40 C m
60. e 1 LSI clock is available as CPU clock source IWDG_HW Independent watchdog 0 IWDG Independent watchdog activated by software 1 IWDG Independent watchdog activated by hardware WWDG HW Window watchdog activation 0 WWDG window watchdog activated by software 1 WWDG window watchdog activated by hardware WWDG HALT Window watchdog reset on halt 0 No reset generated on halt if WWDG active 1 Reset generated on halt if WWDG active OPT4 EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN CKAWUSEL Auto wakeup unit clock 0 LSI clock source selected for AWU 1 HSE clock with prescaler selected as clock source for for AWU PRSC 1 0 AWU clock prescaler 00 24 MHz to 128 kHz prescaler 01 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to 128 kHz prescaler OPT5 HSECNT 7 0 HSE crystal oscillator stabilization time This configures the stabilisation time 0x00 2048 HSE cycles OxB4 128 HSE cycles OxD2 8 HSE cycles OxE1 0 5 HSE cycles OPT6 Reserved OPT7 WAITSTATE Wait state configuration This option configures the number of wait states inserted when reading from the Flash data EEPROM memory 1 wait state is required if fopy gt 16 MHz 0 No wait state 1 1 wait state OPTBL BL 7 0 Bootloader option byte This option is checked by the boot ROM code after reset Depending also on the co
61. e AN1015 Table 44 EMS data Symbol Parameter Conditions Level class EC M Vpp 5 V Ta 25 C Voltage limits to be applied on any I O pin to V FESD induce a functional disturbance fmasteR 16 MHz 2B conforms to IEC 1000 4 2 Fast transient voltage burst limits to be Vpp 5 V Ta 25 C VEFTB applied through 100pF on Vpp and Vss pins fyasteR 16 MHz 4A to induce a functional disturbance conforms to IEC 1000 4 4 Electromagnetic interference EMI Emission tests conform to the SAE J 1752 3 standard for test software board layout and pin loading Table 45 EMI data Conditions 1 Symbol Parameter Max fuse fcpu Unit E Monitored General conditions frequency band 8MHz 8MHz 8MHz 8 MHz 16 MHz 24 MHz 0 1MHz to 30 MHz 15 20 24 Peak level YpD 5 V 30 MHz to 130 MHz 18 21 16 dBuV Se Ta 25 C LQFP80 package 130 MHz to 1 GHz 1 1 4 conforming to SAE J 1752 3 ci EMI 9 2 2 5 2 5 1 Data based on characterization results not tested in production 82 96 Absolute maximum ratings electrical sensitivity Based on two different tests ESD and LU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 ky STM8S20xxx Electrical characteristics Electrostatic discharge ESD Electrost
62. ed if Vjy maximum is respected If Viy maximum cannot be respected the injection current must be limited externally to the liy pin value A positive injection is induced by Viy Vpp while a negative injection is induced by Viy lt Vgs For true open drain pads there is no positive injection current and the corresponding Viy maximum must always be respected 5 Negative injection disturbs the analog performance of the device See note in Section 8 3 10 10 bit ADC characteristics on page 78 6 When several inputs are submitted to a current injection the maximum lin pin is the absolute sum of the positive and negative injected currents instantaneous values These results are based on characterization with lj py maximum current injection on four I O port pins of the device Table 14 Thermal characteristics Symbol Ratings Value Unit TsrG Storage temperature range 65 to 150 C Tj Maximum junction temperature 150 2 52 96 STM8S20xxx Electrical characteristics 8 3 K Operating conditions Table 15 General operating conditions Symbol Parameter Conditions Min Max Unit TA lt 105 C 0 24 MHz fopy Internal CPU clock frequency 0 16 MHz Vpp Vpp 1o Standard operating voltage 2 95 5 5 V 44 48 64 and 80 pin devices with output on 8 standard ports 2 high sink 443 Power dissipation at ports and 2 open n Pp Ta 85 C for suffix 6 ports simult
63. epeated START condition setup time 4 7 0 6 tsusto STOP condition setup time 4 0 0 6 us STOP to START condition time bus tw STO STA free 4 7 1 3 us Cy Capacitive load for each bus line 400 400 pF 1 faster Must be at least 8 MHz to achieve max fast I C speed 400kHz Data based on standard I C protocol requirement not tested in production The maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL 77 96 Electrical characteristics STM8S20xxx 8 3 10 78 96 10 bit ADC characteristics Subject to general operating conditions for Vppa faster and Ta unless otherwise specified Table 41 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VppA 3 to 5 5 V 1 4 fapc ADC clock frequency MHz VppA 4 5 to 5 5 V 1 6 VppA Analog supply 3 5 5 V Vngr Positive reference voltage 2 75 VDDA V Vngr Negative reference voltage Vesa 0 501 V Vssa Vppa V Va Conversion voltage range Devices with external y 3 V Vrer Vrer pins PER PEN Internal sample and hold C ADO capacitor pF f 4 MHz 0 75 tg Sampling time ane us fADC 6 MHz 0 5 tstag _ Wakeup time from standby 7 us fADC 4 MHz 3 5 us Total conversion
64. etale salata 12 4 4 Flash program and data EEPROM memory 13 4 5 Clock controller d P oct enbed bite Pale HER oe EE 14 4 6 Power management 2sssa skanna ee 14 4 7 Watchdog timers Lippi ERRE LERNER aa GG ended 15 4 8 Auto wakeup counter 11s sssak saak kaa ee 15 4 9 Beeper D m 16 4 10 TIM1 16 bit advanced control timer 16 4 11 TIM2 TIMG 16 bit general purpose timers 16 4 12 TIM4 8 bit basic timer 16 4 13 Analog digital converter ADC2 2s22ss sasaran ra arra 17 4 14 Communication interfaces illie 17 4141 UARTI Scc Rm la SW aa etos d ee ERR EAE PORE Rete 17 444 2 UART sa skak eren ke d ta eom n KR a Ro RR CR CE Lotus a 18 4 14 8 SP ested ees REN DERE EG YER rv o E Ea RR ACE 19 qii JU bes aa RUE SE DER a C DE 19 4 4 5 CAN iios oss nee Peek gc e quedas de Ra uu dad acr ds ond RU 19 5 Pinouts and pin description 000 21 5 1 Package pinouts isses kg RE REG REEAit OR REG 21 5 1 1 Alternate function remapping 11 1 22s sss kaa kaa aa 31 6 Option bytes tah cc sc rn n CR nt 32 2 96 ky STM8S20xxx Contents 10 Memory Map ux auc ck OR CR sia Qa C DuC e c aa 35 7 1 Register map oiran Re na 36 Electrical characteristics LL 49 8 1 Parameter conditions iii ee ea Rc RON OR 49 8 1 1 Minimum and maximum values 49 8 1 2 Typ
65. fer between stack and accumulator push pop with direct stack access Data transfer using the X and Y registers or direct memory to memory transfers 11 96 Product overview STM8S20xxx 4 2 4 3 12 96 Single wire interface module SWIM and debug module DM The single wire interface module and debug module permits non intrusive real time in circuit debugging and fast memory programming SWIM Single wire interface module for direct access to the debug module and memory programming The interface can be activated in all device operation modes The maximum data transmission speed is 145 bytes ms Debug module The non intrusive debugging module features a performance close to a full featured emulator Beside memory and peripherals also CPU operation can be monitored in real time by means of shadow registers e R Wto RAM and peripheral registers in real time e R W access to all resources by stalling the CPU e Breakpoints on all program memory instructions software breakpoints e 2advanced breakpoints 23 predefined configurations Interrupt controller Nested interrupts with 3 software priority levels 32 interrupt vectors with hardware priority Up to 37 external interrupts on 6 vectors including TLI Trap and reset interrupts STM8S20xxx Product overview 4 4 Flash program and data EEPROM memory e Upto 128 Kbytes of high density Flash program single voltage Flash memory e Up to 2 K bytes true data
66. h message Configurable FIFO overrun Time stamp on SOF reception 6 filter banks 2 x 32 bytes scalable to 4 x 16 bit each enabling various masking configurations such as 12 filters for 29 bit ID or 48 filters for 11 bit ID Filtering modes Mask mode permitting ID range filtering ID list mode Time triggered communication option Disable automatic retransmission mode 16 bit free running timer Configurable timer resolution Time stamp sent in last two data bytes STM8S20xxx Pinouts and pin description 5 Pinouts and pin description 5 1 Package pinouts Figure 3 LQFP 80 pin pinout Q o x m 9 mo z L x gui x 2M ugs DEE Y Sr Q 5 6000 _ 0 Qux lE Kad DDE ESS SES zi c m FEFEEE E Qoa _ LLHHD HH oS Ii gSSrrrrzri LFEE G d B8aBBn8re amp u unoooos D o nganoandand rinrin acria arrn ao ra i Q O0 0 r Q 10 st CO N 7 O O ORK OO 10 st 00 QN 77 oo P P PR oP PoP oP Po P P CO CQO CO CO QO CO OOO NRSTLI
67. haracteristics HSE crystal ceramic resonator oscillator The HSE clock can be supplied with a 1 to 24 MHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start up stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy Table 29 HSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fuse oa Speed oscillator 1 24 MHz RF Feedback resistor 220 kQ c Recommended load capacitance 20 pF C 20 pF 6 startup fosc 24 MHz 2 stabilized 9 lop Hse HSE oscillator power consumption C 10 pF 6 camp mA fosc 24 MHz stabilized Om Oscillator transconductance 5 mA V tsuHse Startup time Vpp is stabilized 1 ms C is approximately equivalent to 2 x crystal Cload 2 The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R value Refer to crystal manufacturer for more details Data based on characterization results not tested in production 4 tsu Hse is the start up time measured from the moment it is enabled by software to a stabilized 24 MHz oscillation is reached This value is
68. hermal test method environment conditions natural convection still air Available from www jedec org STM8S20xxx Electrical characteristics 8 4 2 Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the order code see Figure 47 STM8S207 208xx performance line ordering information scheme on page 94 The following example shows how to calculate the temperature range needed for a given application Assuming the following application conditions e Maximum ambient temperature Tamax 82 C measured according to JESD51 2 e lpomax 15 mA Vpp 5 5 V e Maximum 8 standard I Os used at the same time in output at low level with Io 10 mA Vo 2 V e Maximum 4 high sink I Os used at the same time in output at low level with lor 20 mA Vo 1 5 V e Maximum 2 true open drain I Os used at the same time in output at low level with lo 20 MA Vo 2 V Pintmax 15 MA x 5 5 V 82 5 mW Piomax 10 mA x 2 V x 8 20 MA x 2 V x 2 20 mA x 1 5 V x 4 360 mW This gives Pintmax 82 5 mW and Pjomax 360 mW Ppmax 82 5mW 360 mW Thus Ppmax 443 mW Using the values obtained in Table 48 Thermal characteristics on page 84 TJmax S calculated as follows For LQFP64 10x 10 mm 46 C W Tymax 82 C 46 C W x 443 mW 82 C 20 C 102 C This is within the range of the suffix 6 version parts 40 lt Tj lt 105 C In this case parts must be ordered at
69. ical values 1 21 221 su s ka kklssdas s eR eh 49 8 1 3 Typical CURVES xc rl eee i 49 8 1 4 Typical current consumption 49 8 1 5 Pin loading conditions LL 50 8 1 6 Loading capacitor 0 b k eren 50 8 1 7 Pin input voltage xaskuxssab la aad ki gn eee 50 8 2 Absolute maximum ratings 51 8 3 Operating conditions vsa saran ees 53 8 3 1 VCAP external capacitor 11 2s ssasa kakak akar 54 8 3 2 Supply current characteristics annan 55 8 3 3 External clock sources and timing characteristics 62 8 3 4 Internal clock sources and timing characteristics 64 8 3 5 Memory characteristics 66 8 3 6 I O port pin characteristics 67 8 3 7 Reset pin characteristics 2i2isssssskasaanaaaaraa 72 8 3 8 SPI serial peripheral interface 74 8 3 9 IC interface characteristics 2 ocersc dr eres a gaan TERT 77 8 3 10 10 bit ADC characteristics 78 8 84431 EMC characteristics llle ren 81 8 4 Thermal characteristics lle 84 8 4 1 Reference document LL 84 8 4 2 Selecting the product temperature range 85 Package characteristics ieri 86 9 1 Package mechanical data 87 9 1 1 LQFP package mechanical data na 87 STM8 development tools eee eee 92 10 1 Emulation and in circuit debugging tools s 92 10 2 SoftWare 100 53 sari usa ak
70. ifications that means when a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international standard 83 96 Electrical characteristics STM8S20xxx 8 4 8 4 1 84 96 Thermal characteristics The maximum chip junction temperature T ax must never exceed the values given in Table 15 General operating conditions on page 53 The maximum chip junction temperature T jm in degrees Celsius may be calculated using the following equation Tumax Tamax Ppmax X Oya Where Tamax is the maximum ambient temperature in C Oy is the package junction to ambient thermal resistance in C W Ppmax is the sum of Pintmax and P omax Ppmax Pintmax P Oomax e Pintmax IS the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power Pi omax represents the maximum power dissipation on output pins Where Promax VoL loL Vpp Vou on taking into account the actual Vo Igj and Voy loj of the I Os at low and high level in the application Table 48 Thermal characteristics Symbol Parameter Value Unit Oja e ee E 38 C W Oja oa e 45 C W Oja Eee EE 46 C W Oja ea il E 57 C W Oja e a 54 C W Oja i junction ambient 59 C W 1 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment Reference document JESD51 2 integrated circuits t
71. iguration register The clock signal is not switched until the new clock source is ready The design guarantees glitch free switching e Clock management To reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory e Master clock sources 4 different clock sources can be used to drive the master clock 1 24 MHz High Speed External crystal HSE Up to 24 MHz High Speed user external clock HSE user ext 16 MHz High Speed Internal RC oscillator HSI 128 kHz Low Speed Internal RC LSI e Startup clock After reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts e Clock security system CSS This feature can be enabled by software If an HSE clock failure occurs the internal RC 16 MHz 8 is automatically selected by the CSS and an interrupt can optionally be generated e Configurable main clock output CCO This outputs an external clock for use by the application Power management For efficent power management the application can be put in one of four different low power modes You can configure each mode to obtain the best compromise between lowest power consumption fastest start up time and available wakeup sources e Wait mode in this mode the CPU is stopped but peripherals are kept running The wakeup is perfor
72. ion features for STice such as code profiling and coverage ST visual programmer STVP Easy to use unlimited graphical interface allowing read write and verify of your STM8 microcontroller s Flash program memory data EEPROM and option bytes STVP also offers project mode for saving programming configurations and automating programming sequences C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of your application directly from an easy to use graphical interface Available toolchains include e Cosmic C compiler for STM8 Available in a free version that outputs up to 16 Kbytes of code For more information see www cosmic software com e Raisonance C compiler for STM8 Available in a free version that outputs up to 16 Kbytes of code For more information see www raisonance com e STM8 assembler linker Free assembly toolchain included in the STVD toolset which allows you to assemble and link your application source code Programming tools During the development cycle STice provides in circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol Additional tools are to include a low cost in circuit programmer as well as ST socket boards which provide dedicated programming platforms with sockets for programming your STM8 For produ
73. ithout notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR
74. ler assembler and integrated development environment with high level language debugger In addition the STM8 is to be supported by a complete range of tools including starter kits evaluation boards and a low cost in circuit debugger programmer Emulation and in circuit debugging tools The STice emulation system offers a complete range of emulation and in circuit debugging features on a platform that is designed for versatility and cost effectiveness In addition STM8 application development is supported by a low cost in circuit debugger programmer The STice is the fourth generation of full featured emulators from STMicroelectronics It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application In addition STice offers in circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module SWIM which allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers STice key features Occurrence and time profiling and code coverage new features Advanced breakpoints with up to 4 levels of conditions Data break
75. m the watchdog behavior to match the application perfectly The application software must refresh the counter before time out and during a limited time window A reset is generated in two situations 1 Timeout At 16 MHz CPU clock the time out period can be adjusted between 75 us up to 64 ms 2 Refresh out of window The downcounter is refreshed before its value is lower than the one stored in the window register Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the 128 kHZ LSI internal RC clock source and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 us to 1 s Auto wakeup counter Used for auto wakeup from active halt mode e Clock source internal 128 kHz internal low frequency RC oscillator or external clock 15 96 Product overview STM8S20xxx 4 9 Beeper The beeper function outputs a signal on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz 4 10 TIM1 16 bit advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver e 16 bit up down and up down autoreload counter with 16 bit pre
76. mance line products contain a 10 bit successive approximation A D converter ADC2 with up to 16 multiplexed input channels and the following main features _ Input voltage range 0 to Vppa Dedicated voltage reference VREF pins available on 80 and 64 pin devices Conversion time 14 clock cycles Single and continuous modes External trigger input Trigger from TIM1 TRGO End of conversion EOC interrupt Communication interfaces The following communication interfaces are implemented e UART1 Full feature UART SPI emulation LIN2 1 master capability Smartcard mode IrDA mode single wire mode e UART3 Full feature UART LIN2 1 master slave capability e SPI full and half duplex 10 Mbit s e C up to 400 Kbit s e CAN rev 2 0A B 3 Tx mailboxes up to 1 Mbit s UART1 Main features 1 Mbit s full duplex SCI SPI emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder LIN master mode Single wire half duplex mode Asynchronous communication UART mode Full duplex communication NRZ standard format mark space Programmable transmit and receive baud rates up to 1 Mbit s fcpy 16 and capable of following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver 2 receiver wakeup modes Address bit MSB Idle line interrupt 17 96 Product overview STM8S20xxx 4 14 2
77. measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 17 HSE oscillator circuit diagram K I R I i Gol i Lm Ci l Oy l Resonator gt STM8 Ci fuse to core Re OSCIN Consumption control Resonator IL 4 OSCOUT HSE oscillator critical gm formula Imorit 2 x TI x fyse x Rm 2Co 0 Rm Notional resistance see crystal specification Lm Notional inductance see crystal specification Cm Notional capacitance see crystal specification 63 96 Electrical characteristics STM8S20xxx 8 3 4 64 96 Co Shunt capacitance see crystal specification C 42C 52C Grounded external capacitance Im gt gt Omcrit Internal clock sources and timing characteristics Subject to general operating conditions for Vpp and Ta fuse High speed internal RC oscillator HSI Table 30 HSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fus Frequency 16 MHz Trimmed by the Accuracy of HSI oscillator CLK_HSITRIMR register A0 10 for given Vpp and TA conditions Vpp 5 0 V Ta 25 C 2 2 ACCHsi Vpp 5 0 V 3 2 25 C T lt 85 C li Accuracy of HSI oscillator factory calibrated 2 95 lt Vpp
78. med by an internal or external interrupt or reset Active halt mode with regulator on in this mode the CPU and peripheral clocks are stopped An internal wakeup is generated at programmable intervals by the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption ky STM8S20xxx Product overview 4 7 4 8 is higher than in active halt mode with regulator off but the wakeup time is faster Wakeup is triggered by the internal AWU interrupt external interrupt or reset Active halt mode with regulator off this mode is the same as active halt with regulator on except that the main voltage regulator is powered off so the wake up time is slower e Halt mode in this mode the microcontroller uses the least power CPU and peripheral clocks are stopped the main voltage regulator is powered off Wakeup is triggered by external event or reset Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications The WDG timer activity is controlled by option bytes or by software Once activated the watchdog can not be disabled by the user program without reset Window watchdog timer The window watchdog is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to tri
79. ns Typ Unit Flash in operating mode HSI clock after 61 5 wakeup K Ipp H Supply current in halt mode pA Flash in powerdown mode HSI clock after 45 wakeup ky 59 96 Electrical characteristics STM8S20xxx Low power mode wakeup times Table 25 Wakeup times Symbol Parameter Conditions Typ Max Unit See Wakeup time from wait 2 t note WU WF mode to run mode fcpu faster 16 MHz 0 56 Flash in operating 6 6 mode i 2 MVR Voltage regulator ON 4 Flash in powerdown 3 6 Wakeup time active halt mode HSI after us lWU AH 3 k mode to run mode Flash in operating Wakeup 5 486 mode MVR Voltage regulator OFF Flash in powerdown 50 TBp 9 mode Wakeup time from halt Flash in operating mode 52 twu H 3 mode to run mode Flash in powerdown mode 54 TBD 1 Data guaranteed by design not tested in production 2 twuwel 2 X 1 fmaster 7 1 fopu 3 Measured from interrupt event to interrupt vector fetch 4 Configured by the REGAH bit in the CLK_ICKR register 5 Configured by the AHALT bit in the FLASH_CRI register 6 Plus 1 LSI clock depending on synchronization Total current consumption and timing in forced reset state Table 26 Total current consumption and timing in forced reset state Symbol Parameter Conditions Typ Max Unit Vpp 5 0 V 1 6 Ipp R Supply current in reset state mA P Vpp 3 3 V 0 8 Reset release
80. ntent of the reset vector the CPU jumps to the bootloader or to the reset vector Refer to STM8S bootloader manual for more details 2 STM8S20xxx Memory map 7 2 Memory map Figure 8 Memory map 0x00 0000 0x00 17FF 0x00 1800 0x00 3FFF 0x00 4000 0x00 47FF 0x00 4800 0x00 487F 0x00 4900 0x00 4FFF 0x00 5000 0x00 57FF 0x00 5800 0x00 5FFF 0x00 6000 0x00 67FF 0x00 6800 0x00 7EFF 0x00 7F00 0x00 7FFF 0x00 8000 0x00 807F 0x00 8080 0x02 7FFF RAM up to 6 KBytes Reserved up to 2 KBytes Data EEPROM Option bytes Reserved GPIO and peripheral registers see Table 9 and Table 10 Reserved 2 KBytes Boot ROM Reserved CPU SWIM Debug ITC Registers see Table 11 Tes Interrupt Vectors Flash program memory 64 to 128 KBytes 35 96 Memory map STM8S20xxx Table 8 lists the boundary addresses for each memory size The top of the stack is at the RAM end address in each case Table 8 Flash Data EEPROM and RAM boundary addresses Memory area Size bytes Start Address End address 128K 0x00 8000 0x02 7FFF Flash Program Memory 64K 0x00 8000 0x01 7FFF 32K 0x00 8000 0x00 FFFF 6K 0x00 0000 0x00 17FF RAM 4K 0x00 0000 0x00 1000 2K 0x00 0000 0x00 07FF 2048
81. on 8 Electrical characteristics 22 Jun 2008 Added part numbers on page 1 and in Table 2 on page 9 12 Aug 2008 Added 32 pin device pinout and ordering information Updated UBC option description in Table 7 on page 33 USART renamed UART1 LINUART renamed UART3 Max ADC frequency increased to 6 MHz 20 Oct 2008 Removed STM8S207K4 part number Removed LQFP64 14 x 14 mm package Added medium and high density Flash memory categories Added Section 7 Memory map on page 35 Replaced beCAN3 by beCAN in Section 4 14 5 CAN Updated Section 8 Electrical characteristics on page 49 Updated LQFP44 Figure 45 and Table 53 and LQFP32 outline and mechanical data Figure 46 and Table 54 08 Dec 2008 Changed Vpp minimum value from 3 0 to 2 95 V Updated number of High Sink I Os in pinout Removed FLASH _NFPR and FLASH _FPR registers in Table 10 General hardware register map 30 Jan 2009 Removed preliminary status Removed VQFN32 package Added STM8S207C6 STM8S207S6 Updated external interrupts in Table 2 on page 9 Updated Section 8 Electrical characteristics 95 96 STM8S20xxx Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time w
82. points Program and data trace recording up to 128 KB records Read write on the fly of memory during emulation In circuit debugging programming via SWIM protocol 8 bit probe analyzer 1 input and 2 output triggers Power supply follower managing application voltages between 1 62 to 5 5 V Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements Supported by free software tools that include integrated development environment IDE programming software interface and assembler for STM8 STM8S20xxx STM8 development tools 10 2 10 2 1 10 2 2 10 3 Software tools STM8 development tools are supported by a complete free software package from STMi croelectronics that includes ST Visual Develop STVD IDE and the ST Visual Programmer STVP software interface STVD provides seamless integration of the Cosmic and Raiso nance C compilers for STM8 which are available in a free version that outputs up to 16 Kbytes of code STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www st com mcu This package includes ST visual develop Full featured integrated development environment from ST featuring Seamless integration of C and ASM toolsets Full featured debugger Project management Syntax highlighting editor Integrated programming interface Support of advanced emulat
83. pt controller registers continued Address Block Register Label Register Name si 0x00 7F90 DM BK1RE DM Breakpoint 1 register extended byte OxFF 0x00 7F91 DM BK1RH DM Breakpoint 1 register high byte OxFF 0x00 7F92 DM BK1RL DM Breakpoint 1 register low byte OxFF 0x00 7F93 DM BKA2RE DM Breakpoint 2 register extended byte OxFF 0x00 7F94 DM BK2RH DM Breakpoint 2 register high byte OxFF 0x00 7F95 DM DM BK2RL DM Breakpoint 2 register low byte OxFF 0x00 7F96 DM CR1 DM Debug module control register 1 0x00 0x00 7F97 DM CR2 DM Debug module control register 2 0x00 0x00 7F98 DM CSR1 DM Debug module control status register 1 0x10 0x00 7F99 DM CSR2 DM Debug module control status register 2 0x00 0x00 7F9A DM ENFCTR DM Enable function register OxFF nu a Reserved area 5 bytes 1 Accessible by debug module only 2 Product dependent value see Figure 8 Memory map 48 96 2 STM8S20xxx Electrical characteristics 8 8 1 Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referred to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at T4 25 C and T4 Tamax given by the selected temperature range Data based on characterization results design simulation and or technolog
84. ratures 1 ssas saka sana 64 Typical LSI frequency vs Vpp ii 65 Typical Vj and Vip vs Vpp 4 temperatures 68 Typical pull up resistance Rpy vs Vpp 4 temperatures 68 Typical pull up current lo vs Vpp 4 temperatures 1 1 s sanna 68 Typ VOL VDD 3 3 V standard ports 70 Typ VOL VDD 5 0 V standard ports 2 1 2 2s ssk sasa saa aaa na 70 Typ VOL VDD 3 3 V true open drain ports rasakan a 70 Typ VOL VDD 5 0 V true open drain ports sasa ka akan 70 Typ VOL VDD 3 8 V high sink ports LL 70 Typ VOL VDD 5 0 V high sink ports LL 70 Typ VDD VOH VDD 3 3 V standard ports 71 Typ VDD VOH VDD 5 0 V standard ports 71 Typ VDD VOH VDD 3 3 V high sink ports 71 Typ VDD VOH VDD 5 0 V high sink ports 71 Typical NRST Vj and Vip vs Vpp 4 temperatures 72 Typical NRST pull up resistance Rpy vs Vpp 4temperatures 73 Typical NRST pull up current lou VS Vpp 4temperatures 73 Recommended reset pin protection 0 0 ksa kakak askar 73 SPI timing diagram slave mode and CPHA 0 slakan aaa 75 SPI timing diagram slave mode and CPHA 100 MMC 75 SPI timing diagram master mode xxx 76 ADC accuracy characteristics 80 Typical application with ADC 1s sasa sasa RII Inh 80 80 pin low profile quad flat package 14 x 14 LL
85. re 15 show typical current consumption measured with code executing in RAM Figure 14 Typ Ipp RUN VS Vpp HSI RC OSC Figure 15 Typ Ipp wFi VS Vpp HSI RC osc fepy 16 MHz fepy 16 MHz 2 5 4 40 C m P ma 25C 85 C s Sus 125 C m I A E adan i 3 2 40 C 1 8 15 Rm 25 C E 1 85 C 0 5 125 C 0 5 0 0 25 3 3 5 4 4 5 5 55 6 2 5 3 3 5 4 4 5 5 5 5 6 Voo V Voo V 3 61 96 Electrical characteristi cs STM8S20xxx 8 3 3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for Vpp and Ta Table 28 HSE user external clock characteristics Symbol Parameter Conditions Min Typ Max Unit User external clock source f HSE ext frequency 0 24 MHz OSCIN input pin high level Vusenu P voltage put p g 0 7 x Vpp Vpp 0 3V V OSCIN input pin low level Visse voltage Vss 0 3 x Vpp OSCIN input leakage lLEAK HSE cerent B g Vss lt Vin lt Vpp 1 1 yA 1 Data based on characterization results not tested in production Figure 16 HSE external clock source VHsEH VHsEL EE MEM C D gt fuse External clock source OSCIN STM8 62 96 ky STM8S20xxx Electrical c
86. rt D data direction register 0x00 0x00 5012 PD CR1 Port D control register 1 0x02h 0x00 5013 PD_CR2 Port D control register 2 0x00 0x00 5014 PE_ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register 0x00 0x00 5016 Port E PE DDR Port E data direction register 0x00 0x00 5017 PE CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 0x00 5019 PF ODR Port F data output latch register 0x00 0x00 501A PF IDR Port F input pin value register 0x00 0x00 501B Port F PF_DDR Port F data direction register 0x00 0x00 501C PF CR1 Port F control register 1 0x00 0x00 501D PF CR2 Port F control register 2 0x00 0x00 501E PG ODR Port G data output latch register 0x00 0x00 501F PG IDR Port G input pin value register 0x00 0x00 5020 Port G PG DDR Port G data direction register 0x00 0x00 5021 PG CR1 Port G control register 1 0x00 0x00 5022 PG CR2 Port G control register 2 0x00 0x00 5023 PH ODR Port H data output latch register 0x00 0x00 5024 PH IDR Port H input pin value register 0x00 0x00 5025 Port H PH_DDR Port H data direction register 0x00 0x00 5026 PH CR1 Port H control register 1 0x00 0x00 5027 PH_CR2 Port H control register 2 0x00 0x00 5028 PI ODR Port data output latch register 0x00 0x00 5029 PI IDR Port input pin value register 0x00 0x00 502A Port PI DDR Port data direction register 0x00 0x00 502B PI_CR1 Port control register 1 0x00 0x00 502C PI_CR2 Port control register 2 0x00 37 96
87. rupt vectors the reset routine and usually the IAP and communication routines Figure 2 Flash memory organization r Data Data memory area 2 Kbytes EEPROM memory Option bytes Programmable area from Kbyte UBC area 2 first pages up to 128 Kbytes Remains write protected during IAP 1 page steps Up to 128 Kbytes Flash dq program memory Program memory area Write access possible for IAP 13 96 Product overview STM8S20xxx 4 5 4 6 14 96 Read out protection ROP The read out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode and debug mode Once the read out protection is activated any attempt to toggle its status triggers a global erase of the program and data memory Even if no protection can be considered as totally unbreakable the feature provides a very high level of protection for a general purpose microcontroller Clock controller The clock controller distributes the system clock fuAsrER coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features e Clock prescaler to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler e Safeclock switching Clock sources can be changed safely on the fly in run mode through a conf
88. s ta nah di a eee i 93 3 96 Contents STM8S20xxx 10 2 1 STM8toolset naana 93 10 2 2 Cand assembly toolchains lille eese 93 10 3 Programming tools iiie ERR RERO ra aaa aaa aaa 93 11 Ordering information eee 94 12 Revision ARISTON 95 4 96 Ti STM8S20xxx List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 ky Device summary sre kcu mpeg ure a ark a bi A ea oe Rana aoe ea 1 STM8S20xxx performance line features 1 2 ssss saak akka ess 9 TIM timer features 2 0 tee 16 Legend abbreviations LL 26 PIN description iii i RE a aa 26 Option bytes ies pte E RT RI ee Ron 32 Option byte description 33 Flash Data EEPROM and RAM boundary addresses 36 I O port hardware register Map 36 General hardware register Map 38 CPU SWIM debug module interrupt controller registers 2 2 2 47 Voltage characteristics 1 11 sbraunss anssss ka
89. scaler e 4 independent capture compare channels CAPCOM configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output e Synchronization module to control the timer with external signals e Breakinput to force the timer outputs into a defined state e 3complementary outputs with adjustable dead time e Encoder mode e Interrupt sources 3 x input capture output compare 1 x overflow update 1 x break 4 11 TIM2 TIM3 16 bit general purpose timers e 16 bit autoreload AR up counter e 15 bit prescaler adjustable to fixed power of 2 ratios 1 32768 e Timers with 3 or 2 individually configurable capture compare channels e PWM mode e Interrupt sources 2 or 3 x input capture output compare 1 x overflow update 4 12 TIM4 8 bit basic timer e 8 bitautoreload adjustable prescaler ratio to any power of 2 from 1 to 128 e Clock source CPU clock e Interrupt source 1 x overflow update Table 3 TIM timer features C ter Timer A Counting CAPCOM Complem Ext synchr Timer size Prescaler i as i mode channels outputs trigger onization bits ae chaining TIM1 16 Any integer from 1 to 65536 Up down 4 3 Yes TIM2 16 Any power of 2 from 1 to 32768 Up 3 0 No N o TIM3 16 Any power of 2 from 1 to 32768 Up 2 0 No TIM4 8 Any power of 2 from 1 to 128 Up 0 0 No 16 96 ky STM8S20xxx Product overview 4 13 4 14 4 14 1 Analog digital converter ADC2 STM8S20xxx perfor
90. section intends to give an overview of the basic features of the STM8S20xxx performance line functional modules and peripherals For more detailed information please refer to the corresponding family reference manual RM0016 Central processing unit STM8 The 8 bit STM8 core is designed for code efficiency and performance It contains 6 internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e Harvard architecture 3 stage pipeline 32 bit wide program memory bus single cycle fetching for most instructions X and Y 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations 8 bit accumulator 24 bit program counter 16 Mbyte linear memory space 16 bit stack pointer access to a 64 K level stack 8 bit condition code register 7 condition flags for the result of the last instruction Addressing e 20addressing modes e Indexed indirect addressing mode for look up tables located anywhere in the address space e Stack pointer relative addressing mode for local variables and parameter passing Instruction set 80 instructions with 2 byte average instruction size Standard data movement and logic arithmetic functions 8 bit by 8 bit multiplication 16 bit by 8 bit and 16 bit by 16 bit division Bit manipulation Data trans
91. t and the corresponding Viy maximum must always be respected or true open drain pads 51 96 Electrical characteristics STM8S20xxx Table 13 Current characteristics Symbol Ratings Max Unit lvpp Total current into Vpp power lines source 60 lyss Total current out of Vgg ground lines sink 60 Output current sunk by any I O and control pin 20 IO Output current source by any I Os and control pin 20 Total output current sourced sum of all I O and control pins i ce 3 200 for devices with two Vppio pins Total output current sourced sum of all I O and control pins 388 for devices with one Vppjo pin Zlio mA Total output current sunk sum of all I O and control pins for devices with two Vssio pins 160 Total output current sunk sum of all I O and control pins for B devices with one Vssio pin Injected current on NRST pin 4 lupin Injected current on OSCIN pin 4 Injected current on any other pin 4 Zlin Total injected current sum of all I O and control pins 20 1 Data based on characterization results not tested in production 2 All power Vpp Vppio VppA and ground Vss Vssjo Vssa pins must always be connected to the external supply 3 I O pins used simultaneously for high current source sink must be uniformly spaced around the package between the Vppio Vssio pins 4 lij piy Must never be exceeded This is implicitly insur
92. t clock 16 MHz 2 7 5 8 run mode HSI RC osc 16 MHz 25 3 4 code executed HSE user ext clock 16 MHz 1 2 44 HSI RC osc 16 MHz 10 1 3 fopy fmaster 1 28 15 625 kHz HSI RC osc 16 MHz 8 0 55 fopu fuasteR 128 kHz LSI RC osc 128 kHz 0 45 mA PERDI fopu fmaster 24 MHz HSE crystal osc 24 MHz 11 4 Ta x 105 C HSE user ext clock 24 MHz 10 8 TBD HSE crystal osc 16 MHz 9 0 Supply 1 current in fcPU fMASTER 16 MHz HSE user ext clock 16 MHz 8 2 15 2 run mode HSI RC osc 16 MHz 81 13 2 1 code executed fcPU fMASTER 2 MHz HSI RC osc 16 MHz 8 2 1 5 from Flash fopu fmasteR 128 125 kHz HSI RC osc 16 MHz 1 1 fopy fmaster 1 28 15 625 kHz HSI RC osc 16 MHz 8 0 6 fopu fmaster 128 kHz LSI RC osc 128 kHz 0 55 1 Data basedon characterization results not tested in production 2 Default clock configuration measured with all peripherals off IST 55 96 Electrical characteristics STM8S20xxx Table 18 Total current consumption with code execution in run mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit fopu fmaster 24 MHz HSE crystal osc 24 MHz 4 0 Ta lt 105 C HSE user ext clock 24 MHz 3 7 7 001 HSE crystal osc 16 MHz 2 9 Supply 4 current in fcPU fMASTER 16 MHz HSE user ext clock 16 MHz 2 7 5 8 run mode HSI RC osc 16 MHz 25 340 code executed HSE
93. t package 7 x 7 A ccc 4 A BUY 36 25 37 24 n IL P ES E1 E 48 13 Pin 1 identification 1 12 C am 5B_ME Table 52 48 pin low profile quad flat package mechanical data mm inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 C 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 500 0 2165 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 500 0 2165 e 0 500 0 0197 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits ky 89 96 Package characteristics STM8S20xxx 90 96 Figure 45 44 pin low profile quad flat package 10 x 10 4Y ME 1 Values in inches are converted from mm and rounded to 4 decimal digits Table 53 44 pin low profile quad flat package mechanical data mm inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 0 090 0 200 0 0035 0 0079 D
94. time Master mode 110 140 tw SCKL t 1 Master mode 5 Pa Data input setup time su Sl Slave mode 5 1 Master mode 7 Ihnen Data input hold time Bi insi Slave mode 10 Slave mode 400 taso Data output access time vaster 16 MHz fgcx 8 MHz Slave mode 4 fMASTER tasso 9 Data output disable time Slave mode 25 tso Data output valid time Slave mode after enable edge 100 tymoy Data output valid time Master mode after enable edge 30 inso Slave mode after enable edge 100 Data output hold time thao Master mode after enable edge 6 Values based on design simulation and or characterization results and not tested in production Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z 74 96 2 STM8S20xxx Electrical characteristics Figure 37 SPI timing diagram slave mode and CPHA 0 NSS input SU NSS lt gt lt tc SCK Ih NSS 24 CPHA 0 f Ah J UT CPOL 0 i i 3 h l Q i i i ra x CPHA 0 uei 1 MS se a Kis i i ce r SCK t dei WES Enne CE gt th SO mur RUM dis SO isu SI 9 4 INPUT Ll d ts gt ai14134 Figure 38 SPI timing diagram slave mode and CPHA 1 NSS input f
95. urve 2 The ideal transfer curve 3 End point correlation line Er Total unadjusted error maximum deviation between the actual and the ideal transfer curves Eo Offset error deviation between the first actual transition and the first ideal one Eg Gain error deviation between the last ideal transition and the last actual one Ep Differential linearity error maximum deviation between actual steps and the ideal one E Integral linearity error maximum deviation between any actual transition and the end point correlation line Figure 41 Typical application with ADC Vop STM8 V Nov AIN AINx i e ANN 10 bit A D Vang NNNNN t conversion _ LES Cain Vr L Lea A 0 6V w i UA CADC 80 96 2 STM8S20xxx Electrical characteristics 8 3 11 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility While executing a simple application toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 1000 4 2 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vgs through
96. with fast as default state after reset Port and control configuration Input float floating wpu weak pull up Output T true open drain OD open drain PP push pull Reset state is shown in bold Table 5 Pin description Pin number Input Output T E o amp x E 2 Detsuh Nase 213 FF Pin name 2 2 E Sis S alternate E EA E E F 22 52 a PE function Enap 6 G G a a 35 5 82 5 option bit SE JE gRr gt x ui 1 1 1 1 1 NNRST I O X Reset 2 2 2 2 2 PAYoscin volx x O1 x X Port a1 Resonator crystal in 3 3 3 3 3 PAZ SCOUT I O X X X O1 X X Port A2 Resonator crystal out 4141414 Vesp 1 S I O ground 5151 15151 4 Vss S Digital ground 6 6 1665 VCAP S 1 8 V regulator capacitor 7 17 1717 16 Vop S Digital power supply 8 8 8 8 7 Vppo 1 S I O power supply Timer 2 TIM3 CH1 951 9 1 9 PA3 TIM2_CH3 I O X X X O1 X X Port A3 channel3 AFR1 10 10 10 9 PA4 UART1 RX IO X X X HS OS X X Port A4 UART1 receive 11 11 11 10 PAS UART1 TX 1 O X X X HS OS X X Port A5 MATT transmit UART1 12 12 12 11 PA6 UART1_CK I O X X X IHS OS X X Port A6 synchronous clock 131 PHO 1 O X X HS O3 X X Port HO 141 PHI 1 O X X HS O3 X X Port H1 151 PH2 1 O
97. y characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 3 X Typical values Unless otherwise specified typical data are based on T4 25 C Vpp 5 0 V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean 2 X Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Typical current consumption For typical current consumption measurements Vpp Vppio and Vppa are connected together in the configuration shown in Figure 9 Figure 9 Supply current measurement conditions 5 0 V or 3 3 V A Voo PHP 49 96 Electrical characteristics STM8S20xxx 8 1 5 8 1 6 50 96 Pin loading conditions Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10 Figure 10 Pin loading conditions STM8 PIN S0pF WN Pin input voltage The input voltage measurement on a pin of the
98. ytes ky 39 96 Memory map STM8S20xxx Table 10 General hardware register map continued Address Block Register label Register name Uia 00 5200h SPI CR1 SPI Control Register 1 0x00 00 5201h SPI CR2 SPI Control Register 2 0x00 00 5202h SPI ICR SPI Interrupt Control Register 0x00 00 5203h SPI SR SPI Status Register 0x02 00 5204h d SPI DR SPI Data Register 0x00 00 5205h SPI CRCPR SPI CRC Polynomial Register 0x07 00 5206h SPI RXCRCR SPI Rx CRC Register OxFF 00 5207h SPI TXCRCR SPI Tx CRC Register OxFF priui Reserved area 8 bytes 00 5210h I2C_CR1 I2C control register 1 0x00 00 5211h 12C_CR2 I2C control register 2 0x00 00 5212h 12C_FREQR 12C frequency register 0x00 00 5213h I2C OARL I2C Own address register low 0x00 00 5214h 12C_OARH 12C Own address register high 0x00 00 5215h Reserved 00 5216h Il2C DR I2C data register 0x00 00 5217h 12C I2C_SR1 12C status register 1 0x00 00 5218h 12C_SR2 12C status register 2 0x00 00 5219h 12C_SR3 12C status register 3 0x00 00 521Ah I2C_ITR 12C interrupt control register 0x00 00 521Bh 12C_CCRL 12C Clock control register low 0x00 00 521Ch 12C_CCRH 12C Clock control register high 0x00 00 521Dh 12C_TRISER 12C TRISE register 0x02 00 521Eh I2C_PECR 12C packet error checking register 0x00 peel Reserved area 17 bytes 40 96 IST STM8S20xxx Memory map

STM8S20xxx

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