XStend Board V4.0 Manual
Contents
1. 11 XSA Board Mounting Sockets eee eee 13 ETI 13 DIP Switch and Pushbuttons 14 SECO AU AAA uwasta 14 WIGISO Ree SN EN 15 A ceeaaucunss J ebeatmeancastet 16 USB e En RR Hl ACC u uuu uy u uU u OD 16 10 100 Ethernet Interface 17 DEM Macu tia 18 Daughterboard Headers 19 ProtONpPING AO natal altas adi 19 A A A edele 20 XSTEND BOARD V4 0 USER MANUAL 2 Interactions Between the XSA 50 100 Boards and the XStend Board 20 XSA 50 100 Pushbutton Interactions 20 XSA 50 100 PS 2 Port Interactions ee 20 XSA 50 100 VGA Port Interactions 20 XSA 50 100 DIP Switch Interactions 21 XSA 50 100 Flash RAM Interactions 21 XSA 50 100 Parallel Port Interface Interactions 21 XSA 50 100 Seven Segment LEDs Interactions 22 XSA 50 100 SDRAM Interactions 22 XStend XSA Pin Connections ek 23 Aotend Schematics uuu iS 24 XSTEND BOARD V4 0 USER MANUAL2. S S 53 z l 52 LA 51 LJ 5a a sa 1 3 Daughterboard Connectors CA 35 A 34 y 31 A a Ce ej 23 a GC ze ap 4 a Go gt E a PS Oa C35 3 PER BEE CC D s f Video Inputs c64 Sm E JE es Vi AN ER HN wi 918 a Geck R40 Rokus T EB e SEJ arie TT ER bay lad kL x3 10 100 Ethernet XStend Board Components Interconnection Buses The connections between the various components on the XStend Board are shown below The socket for the XSA Board connects to the other components through a peripheral bus I2C bus and several point to point dedicated buses The peripheral bus consists of sixteen data lines five address lines and two read write strobes that form the main data conduit between the FPGA and the Ethernet interface XSTEND BOARD V4 0 USER MANUAL 11 IDE interface both daughterboard headers and most of the switches pushbuttons and LEDs The chip selects for components on the peripheral bus are controlled by the FPGA to prevent contention These devices also have sideband signals for interrupts and other status control functions that are specific to their operations The PC bus consisting of a clock line and a data line connects the FPGA to the USB interface video decoder and both daughterboard headers For the video decoder it serves only to send register setup data but it is also one of the conduits for packets going through the USB interface lts function for any daughterboards i
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4. MB ESS Corporation XStend Board V4 0 Manual How to install and use your new XStend Board RELEASE DATE 04 20 2009 Copyright 1998 2009 by X Engineering Software Systems Corporation All XS prefix product designations are trademarks of XESS Corp All XC prefix product designations are trademarks of Xilinx All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photocopying recording or otherwise without the prior written permission of the publisher Printed in the United States of America XSTEND BOARD V4 0 USER MANUAL 1 Table of Contents PrOlIMIN ANOS iii Eege 4 E t uy a ua a nD ak u ua t 4 Fake e ler 4 PACKING b B n Z n E u uma a Oa a m sa 4 JE dan EE 5 Inserting the XSA Board into an XStend Board 5 Applying Power to Your XStend Board 6 Making Connections to Your XSA and XStend Boards 7 Setting the Jumpers on Your XStend Board 8 XStend Board Interfaces 10 XStend Board Capahbilities 10 XStend Board Component5s 11 Interconnection BUSES
5. Preliminaries Getting Help If you can t get the XStend Board hardware to work submit a problem report at http www xess com help php Our web site also has m the XStend 4 0 Board product page m answers to frequently asked questions m example designs for the XS Boards m application notes m a place to sign up for our email forum where you can post questions to other XS Board users m The XStend Board V4 0 is not compatible with the XS95 XS40 or XSTE5 Boards Do not plug XS95 XS40 or XSTE5 Boards into the XStend Board V4 0 m If you are connecting a power adapter to jack J7 of your XStend Board please make sure the center terminal of the plug is positive and the outer sleeve is negative Packing List Here is what you should have received in your package m an XStend Board m an XSTOOLs CDROM with software utilities and documentation for using the XStend Board XSTEND BOARD V4 0 USER MANUAL 4 Installation Inserting the XSA Board into an XStend Board Orient the parallel port VGA port and PS 2 port connectors on the XSA Board as indicated on the XStend Board and insert it into the XStend Board as shown below The XSA Board is plugged into the inside columns of the socket strips Incorrect insertion of the XSA Board into the XStend Board will damage one or both boards when power is applied Let ge 0 00 D LE YA 4 dee 0 G G G Q 410 E ela ila 2 0 o 4 a e sl D c A 5
6. end H Gard Lia 3 ENT AT A3 LE PULL of LS A XSTEND BOARD V4 0 USER MANUAL Applying Power to Your XStend Board You can supply power to your XStend Board in four ways Do not apply power from more than one source at a time You can power both the XStend Board and your XSA Board by attaching a DC power supply to your XSA Board as shown below The XStend Board will draw its power through the XSA Board prototyping header The 5V output from the XSA Board can only supply a few mA to the XStend Board so you should use one of the other methods to power the board if you are attaching 5V logic to the XStend Board Or you can attach a 5V or 9V DC power supply directly to jack J7 on the XStend Board Now the XSA Board will draw its power from the XStend Board Place the shunt on jumper JP1 in the appropriate position for the voltage of your power supply Applying 9V will damage your XStend and XSA Boards if the shunt is in the 5V position XSTEND BOARD V4 0 USER MANUAL 6 Or you can attach a standard ATX PC power supply to the XStend Board through connector J6 Place the shunt on jumper JP1 in the 5V position If using the XStend Board with an XSA 3S1000 Board place the shunt in the PS 2 position of jumper J7 on the XSA 3S1000 Finally you can power the XStend Board from a dual 5V 3 3V power supply directly to binding posts on the XStend Board The binding posts are not provided Place the shunt on jumper JP1 in the
7. SD1 SD2 SD3 XSTEND BOARD V4 0 USER MANUAL XStend Connection ETHER CS PB OE PB WE ETHER AEN PSEN ETHER BHE PB A0 PB A1 PB A2 PB A3 PB A4 PB D0 PB D1 PB D2 PB D3 MAC PHY XStend Connection SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 IREQ PB D4 PB D5 PB D6 PB D7 PB D8 PB D9 PB D10 PB D11 PB D12 PB D13 PB D14 PB D15 ETHER IRQ RDY DTACK ETHER RDY DTACK CLK025 ETHER CLK 17 The Ethernet chip emits a 25 MHz clock signal on its CLKO25 output and this attaches to pin 64 of the XSA Board mounting socket Removing the shunt on the ETHCLK jumper disconnects CLK025 from the XSA Board IDE Interface The FPGA can access a hard disk through the 40 pin IDE interface connector The FPGA stores and retrieves data from the disk by reading and writing registers on the disk through the IDE interface These registers are accessed using the read and write strobes in combination with the register bank chip select lines the three bit register address bus and the sixteen bit data bus In addition to polled access the IDE interface also allows DMA access using the DMA request and acknowledge signals along with the I O ready signal The connections of the IDE interface signals to the XStend Board are as follows IDE Interface XStend Connection IDE Interface XStend Connection CS0 IDE CS0 DD7 PB D7 CS1 IDE CS1 DD8 PB D8 DA0 PB A0 DD9 PB D9 DA1 PB A1 DD10 PB D10 DA2 PB A2 DD11
8. The columns of the table are arranged as follows Column1 is the index of the prototyping header pin on the XSA Board and the mating socket on the XStend Board Pin 1 is in the middle of the left hand row of pins and the pin number increases as you proceed counter clockwise around the header or socket The header pin number should not be used when you create pin assignment constraints for your FPGA design Column 2 is the name of the signal net in the XStend Board schematics The prefix of each net name indicates the component to which it is connected except for the peripheral bus PB that connects to many of the components Column 3 lists the direction of flow on a signal net as seen from the perspective of the XSA Board Outputs are driven by the XSA Board into the XStend Board inputs are driven by the XStend Board into the XSA Board Columns 4 and 5 indicate the nets that connect to the LEDs DIP switches and pushbuttons on the XStend Board Columns 6 9 list the connections of the various components on the XSA 50 and XSA 100 Boards to the signal nets of the XStend Board Column 6 lists the pin numbers that should be used to create pin assignment constraints for the FPGA on the XSA 50 or XSA 100 Board Column 10 lists the pin names of the FPGA on the XSA 200 Board along with the XStend Board net they connect to The other components on the XSA 200 Board are not listed because they have no connection to the prototyping header Colum
9. D VIDIN Y3 BAR2 PB A1 LED1 E VIDIN Y4 BAR3 PB A2 LED1 F VIDIN Y5 BAR4 PB A3 LED1 G VIDIN Y6 BAR5 PB A4 LED1 DP VIDIN Y7 BAR6 ETHER IRQ LED2 A PB D8 BAR7 USB IRQ LED2 B PB D9 BAR8 IDE IRQ LED2 C PB D10 BAR9 SLOT1 IRQ LED2 D PB D11 BAR10 SLOT2 IRQ LED2 E PB D12 LED1 A VIDIN YO LED2 F PB D13 LED1 B VIDIN Y1 LED2 G PB D14 LED1 C VIDIN Y2 LED2 DP PB D15 The bargraph LED segments share their connections with the lines of the peripheral address bus and the interrupt outputs from other devices on the XStend Board The LEDs are not latched so they will respond to any signal driven on these lines The interrupt outputs from the other devices are protected by current limiting resistors so they will not be damaged if the FPGA actively drives the bargraph LEDs No current limiting resistors are needed on the address bus because the FPGA is the only device that can drive these lines The segments of the LED1 seven segment display share their connections with the pixel output bus of the video decoder The LEDs are not latched so they will respond to any signal driven on these lines There are no current limiting resistors on the pixel bus so the video decoder must be configured to place its outputs in a high impedance state whenever the FPGA drives the LED1 segments Upon power up or after a system reset XSTEND BOARD V4 0 USER MANUAL 13 the video decoder outputs are in a high impedance state by default The video decoder must receive an explicit com
10. Instead of simple output only drivers you will have to use bidirectional I O drivers for the peripheral address bus if you want the FPGA to read the state of these pushbuttons Current limiting resistors are placed between the switches pushbuttons and the peripheral bus lines to prevent damage if another device drives these lines at the same time that a switch or pushbutton is closed In such cases the level driven by the other device overrides the level from the pushbutton or switch Stereo Audio Codec The XStend Board has a stereo audio codec AKM AK4565 that accepts two analog input channels digitizes the analog values and sends the digital values to the FPGA as a serial bit stream on the AUDIO SDTO signal line The codec also accepts a serial bit stream from the FPGA on the AUDIO SDTI signal line and converts it into two analog output signals that exit the XStend Board The AUDIO MCLK AUDIO SCLK and AUDIO LRCK serve as clock signals that control the sequencing of the serial data streams The analog stereo input and output signals enter and exit the XStend Board through the 3 5mm jacks J1 and J2 respectively A soundcard CD player or passive microphone XSTEND BOARD V4 0 USER MANUAL 14 provides a source of audio through J1 and stereo headphones can be connected to J2 for listening to the processed output A shunt should be placed on jumper PIC2 if you are using a line level audio signal that doesn t require amplification eg a soun
11. PB D11 DIOR PB RD DD12 PB D12 DIOW PB WR DD13 PB D13 DD0 PB D0 DD14 PB D14 DD1 PB D1 DD15 PB D15 DD2 PB D2 INTRO IDE IRQ DD3 PB D3 DMARQ IDE DMARQ DD4 PB D4 DMACK IDE DMACK DD5 PB D5 IORDY IDE IORDY DD6 PB D6 XSTEND BOARD V4 0 USER MANUAL 18 Daughterboard Headers Daughterboards with specialized circuitry can be connected to the XStend board through the 20x2 headers SLOT1 and SLOT2 The official functions of the signals attached to the daughterboard headers are as follows MASTER RESET An active low signal that is used to reset the daughterboard to a known state CLK A clock signal sent by the FPGA for synchronizing the daughterboard operations PB D15 PB D0 The 16 bit bidirectional peripheral data bus PB A4 PB A0 The 5 bit peripheral address bus is used to address up to 32 locations on a daughterboard PB RD An active low read strobe that enables the daughterboard to send data over the peripheral bus This signal can be used in conjunction with the CLK signal to perform synchronous reads PB WR An active low write strobe that enables the daughterboard to receive data from the peripheral bus This signal can be used in conjunction with the CLK signal to perform synchronous writes SLOT1 CS SLOT2 CS An active low chip select that enables the daughterboard to access the peripheral bus for read and write operations Each daughterboard has a dedicated chip select SLOT1 IRQ SLOT2 IRQ An active high
12. TCP IP m anIDE hard disk interface that gives the FPGA access to long term nonvolatile data storage dual 20x2 daughterboard headers that allow the addition of external modules with new capabilities mg a2 5 x2 5 prototyping area where custom circuitry can be built XSTEND BOARD V4 0 USER MANUAL 10 E d The locations of the circuitry that provide these new capabilities are indicated on the following layout Each of these components and their interconnections will be described in the following sections APO I C31 43 ki Prototyping Area a A O O de S e LEDs Switches Buttons 00 Gi N LED1 LED BARL I L o DIPSH L ED oe ETTEN LI y 4l EDEN 2 ES a a E IG a o E cn E 3 H Buna Ep bei bna Ba3 Bra G HS RZ 7 ra O0 C4 HU q zm on o SL SE Hz se PROG Em yn O HE le cia LRRR8SS SEN dE 8 alle ORE 8 C3 28 5 SE ye gt Ta J2 TAL r Serial Port Audio I O 5U 3 2 64 109875654321 aii EW C2S IW c25 XSA Board Mountinq Socket PARALLEL PORT P DO NOT INSERT Jiz E 9 A rs R39 ta o PpsS 2 PORT R34 B VGA PORT USB 1 1 2 0 XS4 or XS95 BOARD IDE Hard Disk Connector 1 5 o
13. 5V position If using the XStend Board with an XSA 3S1000 Board place the shunt in the PS 2 position of jumper J7 on the XSA 3S1000 Making Connections to Your XSA and XStend Boards You can make the same connections to your XSA Board whether it is inserted into the XStend Board or used stand alone The download cable attaches from the parallel port on the PC to the female DB 25 connector J8 at the top of the XSA Board You can connect a VGA monitor to the 15 pin connector J3 at the bottom of your XSA Board And a keyboard or mouse connects through the PS 2 connector J4 XSTEND BOARD V4 0 USER MANUAL 7 The XStend Board offers some additional connection opportunities m You can capture audio output from a CD player or a microphone by attaching them to the 3 5mm stereo input jack J1 on the XStend Board while audio can be sent to a pair of headphones through the stereo output jack J2 m Youcan also grab frames of NTSC PAL or SECAM video by piping them into one of the RCA connectors AIP1A and AIP1B m You can perform serial communications by attaching a cable between the DB9 connector J9 on the XStend Board and a PC serial port m You can send and receive USB packets by connecting the peripheral end of a USB 1 1 2 0 cable to the USB port J5 on the XStend Board while the host end attaches to a PC USB port m You can send and receive Ethernet packets by inserting a Category 5 cable with a male RJ45 connector into
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16. 9 _ PP D6 FLASH WE L12 RA w OO mn em s Dram Sms CIS j EST DIE 3 mees e nem IPSZDATA e 15 GEK TB IGE 26 RS232RIS AA PS PA 6B NIT SBN Connections Between the XST 4 0 Board and the Various XSA Boards XSA 200 EOI JE AICM IMEI Pin SLOT1 CSH BA EID DB SLOT2 CS DUT A O A O AER DIB 16 TCK RAR 133 j j IG TK c14 TCK A15 TDI _ 3 TD AO 019 BIA TDO _T3 TDO D3 TMS 47 TEO INS SSCS E M A a wone No roan Nee mawar s naa vs ma wara u aa Ic e DNI IN LDB ar ee aeren Pe Ima o VIDINYS IN LDD e ao po maa M INS en nn DN Y IN 1 EO G ASAS Boo NS za s gt Se ep a AB o CC BIS XStend Schematics The following pages show the detailed schematics for the XStend Board XSTEND BOARD V4 0 USER MANUAL qQG be O 800Z 80 6 APT OT T n us SASQWNN USWNDOG dek TILIL yndin0 indu OTPNY 09 1931S ON9 ONO T m 5 ANT INTO 202 rI SS 6 y D U O a ae a HEE ge DIGONY Y NE E ANEE P54 ees B010S HOIN OLdS OIGNY Joey Bee 3 e ed a IL 0S O0IONY vz ids NIT IH 1 OIONY z 22981 Olai gt 1OW OIGNY zz ZEN 11X3 17 419S O1IGNY ez 1198 BulNI S 01039 0I0NY pz 0103 BNI OCH 1103 01019 cz 1409 TALNI NSJ OIONY EA HNSI TILNI 3493 0109 f zz 199 JH 13939 931SUN sz Ndd NO eh LO 808 W7 DIONY Y NE E NSN 5 u Z 9 den q D I EA N9 DIU M E ANGE inoy 7 co GD BZN JINGE Linon Sp 9
17. A 19S 010NY A 1IOW OIdNY IL S 0IG009 GI ISX A 19 03H13 OT E n us 9 8d Lo 8d H 00 4710 dd DU 0 L 2920 0 dd c0 8d 0 8d Gd dd 90 ed 0 dd dQGipe g GEE atra ES GT C Vez UEL mm El y DEE JT LO L G GEE HL LO g 5 OEE HEEN ES 6 8 DEE JEEN S gl DEE JEEN eme LL 9 OEE JEEN eer L G YES eed CL BES JEEN p F Dee JEEN or Dee YEEY oT D jee ZJ IND len Al jee Al lx LY IND CG LOA INS INS Ins Le jo INA je S SI Git SI SI SI S T G f r I ALO U I D gt o le P Pe Je Je TP j N j A Jo ALT N BQC 7 Dd JSQUNN u H b 1SxX suong pu ALF ALP ALt Lt AL EE un3or J 1111 e SUI l 917 p m Ae ON9 RR K GC ug Gro ww e I w ug w TK E lt amp Sug DTE w e DR b ug ONS w Dr i S ug ATG w e k ug w TK 7 lt Du OTE ww e w Se Ta Drai 5 lt 3 Eug OTE w e I w EE ata ZO 6 L C ab ps DL 99 q8 A SEL GT AR 3303 19387 MEA 6 IE ab p9 5 2 99 q8 a SEL L AE 3303 19387 GEE gay DEE 48d pS OEE GLA ST ee Oe sT Bee 10 KL DEE UZA e L DEE JLU CT G OEE 10 Ti BEE _ 34d BT GEE HZ 6 8 Bee J3d SL BES 99d BT l Vte HON SR DEE 1290 TT 5 BEE 393 le DEE Da TT Dee 9a SE Dee WO ST DEE Jg vb DEE goy BT HI HGN i 5 8
18. A Orri HAI9PUNO 301 32 1359 UOU Bee AUHOI ATI A UNC LOD TU Orri 0dd e8dd CL UN FMOIO OFF UM dd zz UN DAYNA OFF OJPNO 301 oz AJA UN OST SSO stad aaa OF 20 90 STO TOO Vad OST LO add CL TOO cad OFT 0 8d ZT ane Edd OTT d dd pTO raa 00 OF 0 8d sO grad 400 Be Gd dd O 600 saa OS 90 8d ZO 800 00 Oz 0 8d z UNC HIJS ID OT 1 4S 40 d4LSYUW 8d dd 6d 8d V4Ta ad Trd ad Ttda dd Ttd dd K 10 dd 4Tt0d dd Sot a Uta No e 0T 8 3989S dgs pe pa 800Z 80 6 eq JSQUNN 1USUNIOJ O keal SAIL 3944191U PSUUSYY UNS UNS UNS UNS UN ON9 ON9 ANT ANDO ANT ANDO EI ANT ANDO AND ANDO ANT O 113 0939 31149933 NE E daHia d nete Cl aH13 o nee 7 YaHLa u nere 13530d 431S4N ce ere 179 93H13 ONS PEA 3T19H13 ONS Bebe eefe 00 FLO NI OO INN al NOTE LO JON FOT O1 AS 00 ND je else sls Salsa ge ziee E DEI E Zi co LJ DAI EE EK 9p 1sIa SL LASA E KKO BZD ST bP OND LNOWLX 08 NITE LX A 191 87 Lid TNd9 Ore 6 FP ANIT I ANII I Banda ege DEE 033dS71 02205 I Z3SY8 OI Bit end 13971 194 I T3SYg OI BTT d OI g3SU8 OI ZTT 0033 Da l Ier nen OyI 93H13 1033 x9910 408 E SE A9910 40d 4 3H 13 33933 H9TSIOI ae 5933 gtas eer Bee HES GTO Ad Ez T0 8d PTOS Ee ONS ONS ONS 90d9 etas Gs me DEE Ven DIOU ZTOS c LU 0d 8 1 ez Ttd ad ee ora gt ae 60 ad anre antera met anteere antiaspres a EH See E 80 8d 849 DG 6 3 GU 449 94
19. E 9 ZE 8E BE Or Lk Cv Eb kk Gr 94 Lv 8 6 gs Lt CG EG kt GG IG 9 84 64 09 19 co Lkod 20 2HS X ef HT4399191 13938 nG Z L HN3Sd N3IY 93H13 709 971 S3 Z101S YdS IZI HSI T LOTS SLO ZEZSH SWL S1Y ZEZSY MIL 80 8d 101 60 8d bT LSX Td dd 13 OCL ZT 1SX GU ZEZSHY TT 1SX TT0 ad 0 8d ZT0 8d ESI 943H13 T0 8d HTS ATI 0 8d 0SI 301 T0 ad 9A NIGIN GTa ad GA NIGIN 0 8d A NIGIN Z0 8d 041 301 Td ad nG L Ol ZEZSY 1719 NIQIN 3H9 93H13 OYI TLOTWS HAIUWO ATI DAI ZLOTS AOHOI AI HOAI HSN OL0S OIONY 90 8d ON3dsns asn Gd dd M19 ASN D I d3H13 19410 409 93H13 bA NIGIN OUYWO JdI ZA NIGIN Y 8d 01 4 NIGIN Z4Y 8d INASN NIGIN CNS INASH NIGIN EG 1SX E2 1SX NE E GINY NIGIN 90Ud 0 8d TY 8d b dd Q Y dd 3398 1 OI0NY ZA NIGIN 1 719S 0I0NY TA NIQI ATIW 0IONY A NIGIN LLOS OIONY a 8d G9 1SX YUM dd 119 93H13 OYI NIGIN ZZ EZ pZ GZ EE ZZ BZ 57 QE TE ZE EE L GE DE ZE BE BE ay Tr Zy CL by CL oF Zy SL EL 29 TG ZG EG L GG G ZS 8G Ss 29 T9 Zo C9 80 20 3HSX GI L 3S9131 13SHa FN3Sd N3Y 0 3H 3 S3 10 IS SI T10 1S SWL AIL 101 vb LSX 2 19 L 1SX TI 1SX 0d dd SI 03H13 HTS IUI 05I IUI SA NICIN GA NIQIN QA NICIN Dull 201 AG A 19 NIGQI DYI TLO1S DAI ELO IS HOAI ASN 9d dd od 8d 0d1 43H13 vA NICIN ZA NIQCIN QI4 NICIN INASN NICIN INASH NICIN 2 1SX GING NICIN Qd dd vv ad AIA 1 010NY
20. MANUAL 8 Jumper PIC1 PIC2 PIC3 JP7 RTS CTS CPU1 CPUO Setting Off On default Off On default Off default On 1 2 3 4 556 7 8 1 3 2 4 5 7 6 8 Off On default Off On default Off Off Off On On Off On On Purpose Not currently used Not currently used Removing this shunt sets the gain of audio input channels to 38 dB Placing a shunt on this jumper sets the gain of the audio input channel to O dB Removing this shunt places the USB interface in user mode Placing a shunt on this jumper enables reprogramming of the USB interface firmware Placing the shunts on these pins makes the XStend Board appear as a DTE device that must be connected to the PC serial port using a null modem cable Placing the shunts on these pins makes the XStend Board appear as a DCE device that must be connected to the PC serial port using a straight through cable Removing this shunt disconnects the XSA Board from the RTS signal of the serial interface Placing a shunt on this jumper connects the XSA Board to the RTS signal of the serial interface Removing this shunt disconnects the XSA Board from the CTS signal of the serial interface Placing a shunt on this jumper connects the XSA Board to the CTS signal of the serial interface Places the Ethernet chip bus interface into 8051 mode Places the Ethernet chip bus interface into 68K mode Places the Ethernet chip bus inte
21. N ONASN NIGIN ONASH NIGIN GINY NIGIN NIOIA 9 M8 T1 OYI NIGIN ONO ONG IBEN Z60 d91T DEEL GTdI ANT UN ZEI INT ANT SES GE YJE Z60rd9T M LOI OL OL ASUS docter 800L 80 6 eq sA qUWNN vu uno 3or SE ON9 ON9 AZ TN AALINDAIJ Lesen WKT Z Bahai lt a E az Tn 3Z TN UN Z STO lt or UQK Ln 19 k AE E UZ Lr UN ANTS ble Ud Ln le lt 009 Ln le lt 14399141 13S53d L Ln le Z MC In 1353094 931SUN IR Ke kg e 3159 4399141 1353d le C UN 90dd
22. a line of the PS 2 port and the CTS line of the RS 232 port on the XStend Board Therefore these components cannot be used simultaneously XSA 50 100 PS 2 Port Interactions The clock and data line of the PS 2 port on the XSA 50 100 Board share FPGA pins with the RTS and CTS lines of the RS 232 port on the XStend Board The pushbutton on the XSA 50 100 Board also shares the PS 2 data line Therefore these components cannot be used simultaneously XSA 50 100 VGA Port Interactions The VGA port of the XSA 50 100 Board uses the same FPGA pins that connect to the upper byte of the peripheral data bus the LED2 seven segment display and the pushbutton PB1 on the XStend Board Therefore these components cannot be used simultaneously XSTEND BOARD V4 0 USER MANUAL 20 XSA 50 100 DIP Switch Interactions The DIP switch on the XSA 50 100 Board shares FPGA pins with the interrupt lines from the USB interface IDE interface and the two daughterboards These interrupt lines also connect to segments of the bargraph LED Therefore the XSA 50 100 Board DIP switches should be left in the OFF OPEN position if interrupts from these components or the bargraph LEDs are being used XSA 50 100 Flash RAMI Interactions The Flash RAM on the XSA 50 100 Board shares FPGA pins with the LED1 seven segment display bargraph LED video decoder stereo audio codec DIP switch pushbuttons PB2 PB3 and PB4 the lower byte of the peripheral data bus t
23. dcard or CD player The shunt should be removed when using a passive microphone to increase the gain of the audio codec Note that the state of the PIC2 jumper is checked and the gain of the audio codec is set only when power is applied to the XStend Board or when the RESET button is pushed When using a microphone remove the shunt from the PIC2 jumper to increase the audio codec gain Leave the shunt in place to lower the gain when using a line level audio source E a SE S Li LC LO amp y Video Decoder The XStend Board can digitize NTSC SECAM and PAL video signals using a video decoder chip Texas Instruments TVP5150A Eight bit pixels of digitized video arrive at the FPGA over the VIDIN Y bus on the rising edge of the VIDIN CLK which is generated by the video decoder chip The FPGA programs the video decoder options by reading and writing registers through the C bus at address 0x5C The connections of the video decoder signals to the XStend Board are as follows Video Decoder XStend Video Decoder XStend Connection Connection PCLK SCLK VIDIN CLK YOUT6 VIDIN Y6 YOUTO VIDIN YO YOUT7 VIDIN Y7 YOUT1 VIDIN Y1 INTERQ GPCL VIDIN IRQ YOUT2 VIDIN Y2 HSYNC VIDIN HSYNC YOUT3 VIDIN Y3 VSYNC PALI VIDIN VSYNC YOUT4 VIDIN Y4 FID GLCO VIDIN FID YOUT5 VIDIN Y5 AVID VIDIN AVID The VIDIN IRQ VIDIN HSYNC VIDIN VSYNC VIDIN FID and VIDIN AVID signals are not made available to the FRGA on some XSA Board models For these b
24. ddSZAD INY TIY Y0S 108 01714 01NI ZT7NY Bg8uY 3 u s 3ZI ddS30 2NY Z 38 caodd0ah gt DEE Ge eeh eet 8SSn b O1 GGb J9T7Ld d 8d 11 19 T9S0 Gr Ota gd SO 20 94 9U8 0113 Z3S0 81d SddS S 1t sq 8d INDETL OSOTL 94 bddS dde gt 0 8d ddNI1 LSHIL IN OUS L0 XD ZUS gnadsns asn 310N 2dI3 150711 TId YTd T1d4939 Z2304 S140dI1 IN SEI Dod QU d LdgdG LU d ddS Qu ddS E d Hn 0 K U dn 0 694 AJ XL1 9I0 ve GE DE ZE 8E 6 Or L Cv Cv kk ne 3SN3S 8S n pd399191 135308 NE E V0u ad 10 8d 0 8d e 0 ed 0 881 0 3981 A 19 85SN OT G n us ev ed v dd Me E 4710d dd 10 8d e T0d dd L 2320 110d dd V10d dd 60 8d 80 e8d U z J w o o OQ OOOGOOOOOOOOOOOOO NI sr NO CO GO NY SF NO CO GO N TTL eJ ll Cl C COL O Cl SIMON OL A OoGrtcztg UN CH CH IN Neer UN ME o gt UN UN UN HE et aTa KLU E LU cC LU Tra oTa 60 8d UN Gd 7 80 56 EE JSQUNN 1UeuP20On H b 15SX 3 1111 51015 Pp4eoq4s1ybneg vu HSJ Bu TU DI MUS WS 04 UM A 19 UN DU vd ca d a Gd 20 ZO HL IS AU N IW N vyd Hed GLOS HU 00 TO dd Dul 10 IS U0S 3 1 T1dS JEl 0d 8d daM 8d A 19 Vda ad L 2920 G Kg e ed 8d yd dd Gd ad 20 ad d ad 13S530d 431SUN e b ed vdd Me 6 4T10d dd 10 8d ETU dd V0 ad 110d dd VT10d ad 60 8d 8d dd U z E
25. ee 343 TI Dee JG zi g bee UG TT ee QG or GEE You ST BIG LOTS DAI TLO IS 041 301 0d1 8sn Dul d3H13 vu dd ev edd v edd TO ad HU 20 4T0 8d K 10 dd Hie va dd Tra dd VT0 8d 6d 8d 80 dd A NIQI S9A NIQI GA NIQI vA NIGIN A NIQI A NIQI TA NICIA QA NICIN doq L8 L0O QT b n us S _2DPJ4 lUI HSM PUE ee te sl CN SLO NO IN O 0 VUS Jc 19S IZI NY NY NY UND Ed Zld Told cat 99d aod ZIS0 asn ISNas asn BEE TISO 8SN GH DD 7 G JSQUNN 1Ueufn2Op D pals 24031 We OEE 974 143 1 8sS n ALD GV Wd NIEA LNOE NOTA NIEL NIT L LOT SG 6 79 79 en NG d IJN ALY 64 13534 4d31SUN NNgIgJOZEZNIH AL Ta NE E NSO OICNY A 199 OI0NY 8d d 60 ad YT0 8d NE Sch UN 13S0 8S n 3S0 8s n 13 km UN UN nl gel PEI NEEF GEI ME SF DEE AGEH gu Zezsy DEE Uar 7 Te Ea aA En SLY ZETSU T LU al zezs E ES E S S 39d y 7 09d C C T O HUT 29 hehehe ies SS 20009 ATINOOYdOWSTTLY HO HOO OTC 1 DD D 0 2 0 0 ULZZ DD DDDOWWWWUO ONPOF NOG Vs To D D D Al D D D D E EZ DDDDEAAADOO D I DD ei SE E A lt lt U gt gt N gt NNOO DD NxD DUDA DD gO EG 7 Eh U SL O NI 1n0T2 1300 1 eee 9 0dN Z2d99 6NV E8ul 5 EAU 1NOZI NIONTIH FSSAPNY GUA _ o Uun c LN SN ZU 13S38 331SUH ddSTAD GNY O34 57 198 AIS TINI OTNU TAU 198 921
26. he peripheral address bus and the interrupt lines for the Ethernet interface USB interface IDE interface and daughterboards on the XStend Board The Flash RAM can be deselected via its individual chip select signal so it can be used with the other components that share the peripheral bus such as the IDE interface Ethernet interface and daughterboards However the interrupt lines from these components cannot be used The video decoder audio codec and interrupt lines need continuous monitoring so they cannot be used in an application that employs the Flash RAM The DIP switches pushbuttons and LEDs can be used whenever the Flash RAM is not being accessed These restrictions do not apply if the Flash RAM is only used to load a configuration into the FPGA on the XSA 50 100 Board during system start up The other components should not be active until after the FPGA is configured after which the Flash RAM will be disabled so interference is not possible XSA 50 100 Parallel Port Interface Interactions The standard parallel port interface programmed into the CPLD on the XSA 50 100 Board dwnldpar svf will actively drive pins of the FPGA that also connect to the video decoder the read and write strobes of the peripheral bus and the interrupt line of the Ethernet interface The alternate parallel port interface dwnldpa2 svf can be downloaded into the CPLD so it will not interfere with these components but still allows bitstreams
27. interrupt generated by the daughterboard to signal the FPGA that some action needs to be taken Each daughterboard has a dedicated interrupt line I2C SCL I2C SDA The clock and data lines for the DC bus that can be used to access any devices on the daughterboard with C interfaces Except for the MASTER RESET signal all of the daughterboard signals connect directly to the FPGA Therefore you can use them to perform any function you want as long as you follow some simple rules m The daughterboard should never actively drive its CLK or SLOT CS signal m The daughterboard should never actively drive any of its signals except for the SLOT IRQ signal when its SLOT CS signal is high Prototyping Area The XStend Board has a prototyping area consisting of component through holes on an 0 1 x0 1 grid Components in this area can access the 5V 3 3V and signal ground by making connections to the appropriate pins on the JP9 header Connections from the XSA Board to the prototyping area are made through the J4 header Each pin on J4 is explicitly labeled with the corresponding number of the prototyping XSTEND BOARD V4 0 USER MANUAL 19 header pin it connects to on the XSA Board For example the pin at the bottom left of J4 on the XStend Board is connected to pin 21 of the XSA Board prototyping header Reset Circuitry Pressing the RESET button on the XStend Board will send a reset signal to the Ethernet interface IDE interface USB i
28. iting these registers the FPGA can act as a USB peripheral with the USB interface chip handling the low level data transactions for the USB bus The USB interface chip also provides an interrupt signal to alert the FPGA when USB transactions need to be processed In addition a suspend signal is output from the chip to alert the FPGA when the USB bus loses power or otherwise ceases operations A clock output from the chip is also made available to the FPGA The frequency of this clock is 48 MHz N 1 where N is a value loaded into a register on the chip through the C interface The suspend and clock signals are not available if you use an XSA 50 or XSA 100 Board with the XStend Board XSTEND BOARD V4 0 USER MANUAL 16 10 100 Ethernet Interface The XSB Board sends data over an Ethernet LAN at 10 or 100 Mbps through an Ethernet MAC PHY chip ASIX AX88796 The FPGA controls the Ethernet chip by reading and writing registers and FIFO buffers on the chip through a standard microprocessor bus interface The Ethernet chip supports several microprocessor bus interfaces The interface is chosen by setting the shunts on jumpers CPU0 and CPU1 as follows Microprocessor Interface MCS 51 805X MC68K 80186 ISA Bus Shunt Settings CPU1 OFF OFF ON ON CPU0 OFF ON OFF ON The connections of the Ethernet chip to the XStend Board are as follows MAC PHY CS IOR IOW AEN PSEN BHE SA0 SA1 SA2 SA3 SA4 SD0
29. mand over the C bus before it will activate these outputs The segments of the LED2 seven segment display share their connections with the upper byte of the peripheral data bus The LEDs are not latched so they will respond to any signal driven on these lines There are no current limiting resistors on the peripheral data bus so the chip selects for the other devices on the peripheral data bus must be deactivated whenever the FPGA drives the LED1 segments DIP Switch and Pushbuttons The XStend has a bank of eight DIP switches and four pushbuttons that are accessible by the XSA Board When a DIP switch is closed or a pushbutton is pressed the corresponding signal line is pulled to ground When a DIP switch is open or a pushbutton is released the signal line is pulled to a high level through a resistor The pushbuttons and switches are connected on the XStend Board as follows Pushbuttons Pushbuttons Seas XStend Connection switches XStend Connection PB1 PB D15 DIPSW 3 PB D2 PB2 PB A0 DIPSW 4 PB D3 PB3 PB A1 DIPSW 5 PB D4 PB4 PB A2 DIPSW 6 PB D5 DIPSW 1 PB D0 DIPSW 7 PB D6 DIPSW 2 PB D1 DIPSW 8 PB D7 When the FPGA reads the state of the switches or pushbutton PB1 it must deactivate the chip selects of the other devices on the peripheral data bus so they will not interfere This is not necessary when reading the state of pushbuttons PB2 PB3 and PB4 because they are attached to the address bus and only the FPGA can drive these lines
30. n 11 lists the pin names of the FPGA on the XSA 351000 Board along with the XStend Board net they connect to The other components on the XSA 351000 Board are not listed because they have no connection to the prototyping header XSTEND BOARD V4 0 USER MANUAL 23 Connections Between the XST 4 0 Board and the Various XSA Boards XSA 50 and XSA 100 XSA 200 XSA 351000 ALICE SS GND e DND ND DZ E E E E E E E E e E BN AO AA E ECO A ES AR IEN N FU 19 LIII GI _ AUDIO MCLK OUT BP HI PHH 31 088 GA i j O l Boons RESTE 38 DOUT BSY BM k o ak on NC 8 j j AS _42 ETHER BHE sas 9 GEK O R9 GC H EIER JOUT I 5146 PEDR FLASH A13 D9 UB O 28 _ ETHER RDY DTACK INN EI O E ESCH MEMES IN OUT O A O Td A CIS j EE EST CE BA IDE CS1 JOUT BESA CC 28 IDEDMARQ IN S S YO A ET EEN eo 2 IDEIRQ IN TBARS A 52 DIPSW1B FLASHA5 D mp a me mm De e Bp PBA1 OUTS DAn PB3 29 D PP S4 FAHA NM Nr 28 D PPSS FLASHA2 D M O men on o e e ene em ECN CS A NES O MT E PR a A n map en REES 49 D3 6 LE nap Aen bm BEE EN SE ES OK BEE 67 D7 10 LED SO FLASH D7 A5 PHB 27 peb won enen e varo e e 3 EE ROE 28 PB D10 IN OUT LED2C 119 NGAGPEEND NP 22 JVGAGREN RT P2 i O 290 PBD12 IN OUT IEDGE Di VGA BLUEO PI Gi E E E TI GS 28 PBD14 MOT LED2G mi VGA HSYNC ES GI DN EEN j DI PBRD OUT 48 12 PP D7 ____ FLASH OE P P 5 4
31. nterface video decoder audio codec daughterboards and the FPGA on the XSA Board The FPGA can also initiate a reset by driving the RESET TRIGGER signal to a low level A current limiting resistor is placed between the RESET button and the FPGA to prevent damage if they simultaneously try to drive the reset to opposite levels Pressing the PROG button will place a low level on the PROGRAM pin of the FPGA and erase its configuration Only the FPGA on the XSA Board will be affected the devices on the XStend board will retain their current settings Interactions Between the XSA 50 100 Boards and the XStend Board Many of the FPGA pins on the XSA 50 and XSA 100 Boards are connected to two or more components on the XSA and or XStend Board This causes interactions that may make it difficult or impossible to employ these components in the same application This section will provide an overview of some of the possible interactions between the components These discussions are overly pessimistic in terms of what components cannot be used together in a single application so advanced users are encouraged to check the list of pin assignments in Appendix A for more details Other models of the XSA Board have dedicated UC pins that connect the FPGA to the prototyping header so they do not have the interactions and restrictions listed below XSA 50 100 Pushbutton Interactions The pushbutton on the XSA 50 100 Board shares an FPGA pin with the dat
32. oards the equivalent functions are performed using the embedded sync flags inserted into the pixel stream according to the ITU R BT 656 standard XSTEND BOARD V4 0 USER MANUAL 15 RS 232 Serial Port The XStend Board has a 9 pin RS 232 port that provides the FPGA with transmit and receive serial data streams TD and RD as well as flow control signals RTS and CTS The shunts on jumper JP7 should be set as shown in the left hand picture if you are connecting the XStend Board to a PC with a straight through serial cable The shunts should be placed as shown in the right hand figure if you are using a null modem cable 4 OA O lt 9 3 jim 2 lo oh2 lo gt o x Ol 2 amp U3 RESET PROG OR RESET PROG 1 o When using the XStend Board with an XSA 50 or XSA 100 Board the RTS and CTS signals share the same wiring that is used by the PS 2 connector Therefore if you are using a mouse or keyboard with an XSA 50 or XSA 100 Board you must remove the shunts on the RTS and CTS jumpers to keep these signals from interfering with the PS 2 port The RTS and CTS signals do not share the PS 2 port wiring on other models of the XSA Board so the shunts can remain in place USB 1 1 2 0 Interface The XStend Board uses a USB enabled microcontroller Microchip PIC18F4455 to provide the XSA Board with a USB communication link The FPGA accesses registers on the chip via the ZC bus at the seven bit C addresses 0x1A and Ox1B By reading and wr
33. rface into x86 mode Places the Ethernet chip bus interface into ISA mode XSTEND BOARD V4 0 USER MANUAL XStend Board Interfaces This section describes the various sections of the XStend Board and shows how the FPGA on the XSA Board interfaces to the various components of the XStend Board Please refer to the complete schematics and pin list at the end of this document if you need more details XStend Board Capabilities The XSA Boards offer a flexible low cost method of prototyping FPGA designs However their small physical size limits the amount of support circuitry they can hold The XStend Board extends the range of applications of the XSA Boards by providing additional support circuitry such as m mounting sockets that provide the main interface between the FPGA on the XSA Board and the XStend Board components m additionalbargraph LED and LED digits for use as simple output devices m DIP switches and pushbuttons that serve as simple input devices m a stereo codec with left right input output channels for audio DSP applications m avideo decoder that digitizes NTSC PAL SECAM signals for input to image processing applications m an RS 232 serial port for sending information over a low speed communication link m a USB 1 1 2 0 interface that lets the FPGA appear as a low speed or full speed USB peripheral device m a 10 100 Base T Ethernet interface that supports various network communication protocols such as
34. s dependent on the characteristics of the external modules The components that process video audio streams and handle the serial port use dedicated point to point buses R5212 TD WSA RS2k2 CTS ALSK AUDIO SCLR GUDILPRCHR AUCIO SOTI AU0I0 S07TO VIN Y VEDIN PI E AA USB lt LK USa SUSPENO USBAR DE BEAL 20 504 RESETE E E PB D1S PB D0 SLOTTI SLOT2Z IRO ILOT ETHER SHE ETHER RDWIDTACK XSTEND BOARD V4 0 USER MANUAL 12 XSA Board Mounting Sockets LEDs The FPGA on the XSA Board accesses the functions of the XStend Board by mating its prototyping header with the XStend Board mounting socket The XSA Board is inserted into the inner rows of the double row sockets In addition the outer rows of each socket provide access points for probing the signals that go through the sockets Each hole in the outer rows is electrically connected to the horizontally adjacent hole on the inner rows Small wires 22 gauge or less can be Inserted in the holes on the outer rows and logic or oscilloscope probes can be attached to monitor the signals going through the mounting socket The XStend Board has a ten segment bargraph LED and two seven segment LED displays All of these LEDs are active high meaning that an LED segment will glow when a high logic level is applied to it These LEDs are connected on the XStend Board as follows LED Segment XStend Connection LED Segment XStend Connection BAR1 PB A0 LED1
35. the RJ45 female connector X3 m You can place data in long term storage by connecting a hard drive to the 40 pin IDE connector IDE 1 m YTOU can add functions by attaching external modules to the 40 pin daughterboard connectors SLOT1 and SLOT2 Setting the Jumpers on Your XStend Board The default jumper settings shown in Table 1 configure your XStend Board for use in a logic design environment You will need to change the jumper settings only if you are m powering the board from a regulated 5V supply applied through jack J7 m accepting audio signals from a low amplitude source e g a passive microphone m attaching a null modem cable from a PC to the serial port connector J9 m disconnecting the RTS and CTS serial port signals m changing the bus interface to the Ethernet MAC PHY chip m Table 1 Jumper settings for XStend Board Jumper Setting Purpose JP1 9V Place the shunt in this position if you are applying a voltage greater than 7V through power jack J7 default 5V Place the shunt in this position if you are applying a voltage of exactly 5V from a regulated power supply through power jack J7 ETHCLK Off Removing this shunt disconnects the 25 MHz clock signal output by the Ethernet interface from pin 64 of the XSA Board mounting socket On Placing a shunt on this jumper connects a 25 MHz clock signal from the Ethernet interface to pin 64 default of the XSA Board mounting socket XSTEND BOARD V4 0 USER
36. to be downloaded to the FPGA using GXSLOAD or XSLOAD Uploading and downloading the SDRAM however is not possible in this case The Parallel Cable lll interface for the CPLD p3jtag svf allows you to use the XILINX IMPACT programming utility to configure the FPGA on the XSA Boards This interface uses some of the same FPGA pins used by the audio codec interface on the XStend Board Therefore the audio codec can t be used if iMPACT is used to configure the FPGA XSTEND BOARD V4 0 USER MANUAL 21 XSA 50 100 Seven Segment LEDs Interactions The seven segment LED on the XSA Board shares FPGA pins with the XStend Board DIP switch and the lower byte of the peripheral data bus Therefore the LED can only be used when components on the peripheral data bus are not being accessed and the DIP switch is not being read The DIP switches do not have to be left in the OPEN position in order to use the LED because there are current limiting resistors that prevent any possible contention XSA 50 100 SDRAMI Interactions The synchronous DRAM chip on the XSA 50 100 Board does not share any FPGA pins with any other components Therefore any application can use the SDRAM regardless of the other components that are to be used that are already being driven on the SRAM XSTEND BOARD V4 0 USER MANUAL 22 XStend XSA Pin Connections The following table lists the connections between the XStend Board components and the various XSA Board models
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