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Data Sheet

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1. 13 15 17 19 21 23 25 27 29 31 33 1 to MHz VALID FOR ALL TEMPERATURE GRADES 1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS 2 IDLE REFERS TO ADSP 2171 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION DEASSERTED PINS ARE DRIVEN TO EITHER OR GND POWER REFLECTS DEVICE OPERATING WITH CLKOUT DISABLED TYPICAL POWER DISSIPATION 5 0V Vpp DURING EXECUTION OF IDLE N INSTRUCTION CLOCK FREQUENCY REDUCTION POWER REFLECTS DEVICE OPERATING WITH CLKOUT DISABLED Figure 18 Power vs Frequency ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2171 ADSP 2172 CAPACITIVE LOADING Figures 19 and 20 show the capacitive loading characteristics of the AD SP 2171 AD SP 2172 RISE TIME 0 4V 2 4V 5 25 50 75 100 125 150 C pF Figure 19 Typical Output Rise Time vs Load Capacitance C at Maximum Ambient Operating Temperature 414 12 10 8 4 2 VALID OUTPUT DELAY OR HOLD ns 2 25 50 75 100 125 150 C pF Figure 20 Typical Output Valid Delay or Hold vs Load Capacitance C at Maximum Ambient Operating Temperature TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured out put high or low voltage to a high impedance state T he output disable time
2. 9 od g a TIT m i D 48 023 022 021 020 019 GND D18 D17 D16 D15 D14 D13 D12 D11 Vpp GND D10 D8 07 05 04 03 GND D2 D1 BG NC BR NC REV A ADSP 2171 ADSP 2172 ADSP 2173 PQFP Pin Configurations PQFP Pin PQFP Pin PQFP Pin PQFP Pin Number Name Number Name Number Name Number Name 1 HA2 ALE 33 MMAP 65 NC 97 NC 2 1 34 66 BR 98 NC 3 HAO 35 PWD 67 NC 99 NC 4 HSEL 36 IRQ2 68 BG 100 NC 5 HD5 37 NC 69 DO 101 NC 6 HD4 38 BMODE 70 01 102 7 HD3 39 NC 71 D2 103 RD 8 HD2 40 NC 72 GND 104 WR 9 HD1 41 Vpp 73 D3 105 GND 10 HDO 42 GND 74 D4 106 GND 11 43 RESET 75 05 107 12 GND 44 NC 76 D6 108 PMS 13 45 77 07 109 DMS 14 AO 46 HMDO 78 D8 110 BMS 15 Al 47 HMD1 79 D9 111 PWDACK 16 A2 48 80 210 112 HD15 17 A3 49 TFSO 81 GND 113 HD14 18 A4 50 RFSO 82 114 HD13 19 A5 51 DRO 83 D11 115 HD12 20 A6 52 SCLKO 84 D12 116 HD11 21 A7 53 DT 1 FO 85 D13 117 22 XTAL 54 TFSI IROI 86 D14 118 HD10 23 CLKIN 55 RFSI IRQO 87 D15 119 HD9 24 CLKOUT 56 GND 88 D16 120 HD8 25 GND 57 DRI F1 89 D17 121 HD7 26 A8 58 SCLK1 90 D18 122 HD6 27 A9 59 FLO 91 GND 123 HSIZE 28 A10 60 FL1 92 D19 124 HRD H RW 29 A11 61 FL2 93 D20 125 HWR HDS 30 A12 62 NC 94 D21 126 GND 31 A13 63 BGH 95 D22 127 GND 32 NC 64 NC 96 D23 128 NC NC These pins M UST remain unconnected REV A 49 ADSP
3. Figure 32 Host Interface Port HMD1 1 HMDO 0 REV A 41 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2173 Parameter Min Max Unit Host Interface Port ultiplexed D ata and Address HM D1 1 Read Strobe and Write Strobe HM D 0 1 Timing Requirement ALE Pulse Width 15 ns HAD 15 0 Address Setup before ALE Low 5 ns HAD 15 0 Address old after ALE Low 2 ns 5 Start of Write or Read after ALE Low 15 ns tusu HRW Setup before Start of Write or Read 8 ns 15 0 Data Setup before End of Write 8 ns HAD 15 0 Data H old after End of Write 3 ns tun HRW H old after End of Write or Read 3 ns tuawe Read or Write Pulse Width 30 ns Switching Characteristic tusuk HACK Low after Start of Write or Read 0 20 ns HACK Hold after End of Write Read 0 20 ns tube HAD 15 0 Data Enabled after Start of R ead 0 ns tupp HAD 15 0 Data Valid after Start of Read 23 ns HAD 15 0 Data after End of Read 0 ns HAD 15 0 Data Disabled after End of Read 15 ns NOTES IStart of Write or Read HDS Low and HSEL Low End of Write or Read HDS High and HSEL H igh 3Read or Write Pulse Width HDS Low and HSEL Low ALE lup Host Write Cycle HRW Host Read Cycle HSEL HDS HACK tuasu than HD15 0 tusk I lupsu in HWDH ALE 4 4 lius
4. NEN wo wx i axo wc Avo avi 5 SE SB SYSTEM CONTROL SRAM DM WAIT CONTROL STACK STACK 4X14 12X25 but cannot execute it because the bus is granted to some other processor With the BGH signal the other processor s in the system can be alerted that the AD SP 217x is hung and release the bus by deasserting bus request Once the bus is released the AD SP 217x executes the external access and deasserts T his is a signal to the other processors that external memory is now available ADSP 217X REGISTERS Figure 7 summarizes all the registers in the ADSP 217x Some registers store values example stores an ALU oper and 14 stores a DAG2 pointer Other registers consist of control bits and fields or status flags For example ASTAT contains status flags from arithmetic operations and fields in DWAIT control the numbers of wait states for different zones of data memory A secondary set of registers in all computational units allows a single cycle context switch T he bit and field definitions for control and status registers are given in the rest of this section except for IM ASK and IFC which are defined earlier in this data sheet T he system control register D WAIT register timer registers HIP control registers H IP data registers and SPORT control registers are all mapped into
5. RISE TIME 0 4 V 2 4 V ns 25 50 75 100 125 150 C pF Figure 35 Typical Output Rise Time vs Load Capacitance at Maximum Ambient Operating Temperature 414 12 10 8 4 2 NOMINAL VALID OUTPUT DELAY OR HOLD ns 2 25 50 75 100 125 150 C pF Figure 36 Typical Output Valid Delay or Hold vs Load Capacitance C at Maximum Ambient Operating Temperature TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured out put high or low voltage to a high impedance state T he output disable time tpis is the difference of and tpecay as shown in the Output nable D isable diagram T he time is the interval from when a reference signal reaches a high or low volt age level to when the output voltages have changed by 0 5 V from the measured output high or low voltage T he decay time 44 is dependent on the capacitative load C and the cur rent load on the output pin It can be approximated by the following equation C 0 5V toecay from which tois ty EASURED toecay is calculated If multiple pins such as the data bus are dis abled the measurement value is that of the last pin to stop driving INPUT Z b V OUTPUT 4 E Figure 37 Voltage Reference
6. AD SP 217x supports an interrupt disable instruction T he instruction source code is specified as follows Syntax DIS INTS Description Reset enables interrupt servicing Executing the DIS INTS instruction causes all interrupts to be masked without changing the contents of the IMASK register Disabling interrupts does not affect the autobuffer circuitry which will operate normally whether or not interrupts are enabled T he disable interrupt instruction masks all user interrupts including the powerdown interrupt 16 REV A 05 2171 05 2172 05 2173 ADSP 2171 ADSP 2172 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter Unit Vpp Supply Voltage V TAMB Ambient Operating T emperature C ELECTRICAL CHARACTERISTICS K B Grades Parameter Test Conditions Min Max Unit i L Input Voltage 2 Vos max 2 0 V Vin Hi Level CLKIN Voltage 9 Vpp max 2 2 V Vin Hi Level RESET Voltage Vpp max 2 2 V Vu Lo L evel Input Voltage 3 Vpp min 0 8 V i L evel Output Voltage gt Vpp min 270 5 2 4 V min lon 100 pA Vpp 0 3 V VoL Lo Level Output Voltage 5 Vpp min 2 0 4 V liu Hi Level Input Current 9 Vpp max Vin Vpp max 10 lu Lo L evel Input Current 9 max Vin 0V 10 lozu T ristate L eakage urrent max Vin max 10 T ristate L eakage C urr
7. HACK H old after End of Write Read 4 0 15 ns D ata Enabled after Start of Read 0 ns D ata Valid after Start of Read 18 ns tunpH D ata H old after End of Read 0 ns turpp D ata Disabled after End of Read 7 ns NOTES IStart of Write HWR Low HSEL Low Start of Read lt HRD Low and HSEL Low 3End of Write HWR High or HSEL High 4End of Read HRD High or HSEL High Read Pulse Width HRD Low and HSEL Low Write Pulse Width HWR Low and HSEL Low 20 WA HSEL Host Write Cycle HWR HACK HD15 0 Host Read Cycle HD15 0 Figure 14 Host Interface Port HMD1 0 HMDO 0 REV A 25 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2171 ADSP 2172 Parameter Min Max Unit Host Interface Port Separate D ata and Address HM D1 0 Read Strobe and Write Strobe HM D 0 1 Timing Requirement tusu HA2 0 HRW Setup before Start of Write or Read 5 ns D ata Setup before End of Write 5 ns D ata H old after End of Write 3 ns HA2 0 HRW Hold after End of Write Read 3 ns tuawe Read or Write Pulse Width 20 ns Switching Characteristic tusuk HACK L ow after Start of Write or Read 0 15 ns HACK H old after End of Write or Read 0 15 ns tube D ata Enabled after Start of Read 0 ns D ata Valid after Start of Read 18 ns D ata H old after End of Read 0 ns turpp D ata Disabled after End of Re
8. HSEL HDS HACK tuasu than lt tunwp gt 4 tunpp Figure 33 Host Interface Port HMD1 1 HMD0 1 42 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2173 POWER INTERNAL ENVIRONMENTAL CONDITIONS Ambient T emperature Rating Tame case PD x Oca case Case T emperature PD Power Dissipation W Thermal Resistance C ase to Ambient 8 T hermal Resistance Junction to A mbient T hermal Resistance Junction to C ase POWER mW Package 8ca TQFP 50 C W 2 C W 48 C W 12 13 14 15 16 17 18 19 2 PQFP 41 C W 10 C W 31 C W 1 tek MHz POWER IDLE 1 2 POWER DISSIPATION T o determine total power dissipation in a specific application 20 OW the following equation should be applied for each output 19 C x Vpp xf 18 load capacitance f output switching frequency 116 415 In an application where external data memory is used and no other outputs are active power dissipation is calculated as 13 sw follows 12 Assumptions n 10 External data memory is accessed every cycle with 50 of the 85 mW address pins switching 12 13 14 15 16 17 18 19 20 External data memory writes
9. max 50 nsH 27 mA Ipp Supply Current Powerdown Lowest Power M ode 100 Ci Input Pin Capacitance 9 13 Vin 22 5 V fin 1 0 MH Z Tame 25 8 pF Co Output Pin Capacitance 13 14 2 5 V fin 1 0MHz Tams 25 C 8 pF NOTES Bidirectional pins D 0 D 23 RF S0 RFS1 SCLK 1 TFSO TFS1 0 15 0 15 Input only pins RESET IRQ2 BR MM AP DRO 1 HSEL HSIZE BM ODE HMDO HM D1 HRD HWR HWR HDS PWD HA2 ALE 1 0 3 nput only pins CLK IN RESET IRQ2 BR MM AP DR1 HSIZE ODE HM DO HM D1 HRD HWR HWR HDS PWD HA2 ALE HA1 0 Output pins BG PMS DMS BMS RD WR PWDACK 0 13 DT 1 CLKOUT HACK FL2 0 specified for TTL outputs all ADSP 2173 outputs are CM OS compatible and will drive to V pp and GND assuming no dc loads 5 uaranteed but not tested T hree statable pins 0 13 00 023 PMS DMS BMS RD WR DT1 SCLKO 5 1 TFSO TFS1 RFSO RSF1 HD0 HD15 H ADO HAD 15 80 V on BR CLKIN Active to force three state condition Idle refers to AD SP 2173 state of operation during execution of ID L E instruction D easserted pins are driven to either V pp or GND Current reflects device operation with CLK OUT disabled 10C urrent reflects device operating with no output loads ly iy 0 4 V and 2 4 V For typical figures for supply currents refer to Power Dissipation s
10. 7 ns 0 13 PMS DMS BMS Hold after RD Deasserted 0 25tcx 3 ns trRwR RD High to RD or WR Low 0 5tck 5 ns w wait states x CLKOUT Figure 27 Memory Read 36 REV A ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2173 Parameter Min Max Unit Memory Write Switching Characteristic tow D ata Setup before WR High 0 5 7 w ns toy Data Hold after WR High 0 25tc 2 ns twe WR Pulse Width 0 5 5 w ns twoe WR Low to Data Enabled 0 ns tasw A0 A13 DMS PMS Setup before WR Low 0 25tck 7 ns D ata Disable before WR or Low 0 25tc 7 ns tcwR CLKOUT High to WR Low 0 25 5 0 25 10 ns taw A0 A13 DMS PMS Setup before WR D easserted 0 75tck 11 5 w ns twra A0 A13 DMS PMS Hold after WR D easserted 0 25 ns twwr WR High to RD or WR Low Q 5tck 5 ns w wait states x REV A CLKOUT DEM m V E M 0 13 Figure 28 Memory Write 37 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2173 Parameter Min Max Unit Serial Ports Timing Requirement SCLK Period 76 9 ns tscs D R TFS RFS Setup before SCLK Low 8 ns tscu DR TFS RFS Hold after SCLK Low 10 ns tscp SC LK Width 28 ns Switching Characteristic tec CLKOUT High to SCLK gut 0 25 0 25 15 ns SCLK High to DT Enable 0 ns tscpv SCLK High to DT Valid 20 ns tnu TFS RF Sour Hold after SCLK High 0 ns tap TFS R
11. DATA MEMORY amp PERIPHERALS OPTIONAL HIP CONTROL HOST PROCESSOR HIP DATA ADDR OPTIONAL SCLK SERIAL DEVICE SERIAL PORTO DT OPTIONAL SCLK RFS or IRQO SERIAL DEVICE SERIAL TFS or IRQ1 PORT 1 OPTIONAL DT or FO DR or FI 14 2 158 e g EPROM 27C64 27C128 27C256 27C512 THE TWO MSBs OF THE DATA BUS ARE USED AS THE MSBs OF THE BOOT EPROM ADDRESS THIS IS ONLY REQUIRED FOR THE 27C256 AND 27C512 Figure 3 ADSP 217x Basic System Configuration Because the AD SP 217x includes an on chip oscillator circuit an external crystal may be used T he crystal should be con nected across the CLKIN and XTAL pins with two capacitors connected as shown in Figure 4 A parallel resonant fundamen tal frequency microprocessor grade crystal should be used CLKIN XTAL ADSP 217x CLKOUT Figure 4 External Crystal Connections A clock output CLK OUT signal is generated by the processor at the processor s cycle rate T his can be enabled and disabled by the CLKODIS bit in the SPORT 0 Autobuffer Control Reg ister DM Ox3F F 3 Reset The RESET signal initiates a master reset of the AD SP 217x The RESET signal must be asserted during the power up se quence to assure proper initialization RESET during initial power up must be held long enough to allow the internal clock REV A to stabilize f RESET is activated any time after power u
12. held low until serviced IRQO IRQ and IRQ2 Flag Output FLO FL1 FL2 and FO CLKOUT FLAG OUTPUTS IRQx Figure 9 Interrupts and Flags 20 REV A ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2171 ADSP 2172 Parameter Min Max Unit Bus Request Grant Timing Requirement teu BR Hold after CLK OUT High 0 25tck 2 ns tgs BR Setup before CLK OUT Low 0 25tck 17 ns Switching C haracteristic tsp CLKOUT High to DMS PMS BMS 0 25tcy 16 ns RD WR Disable DMS PMS BMS RD WR Disable to BG Low 0 ns tse BG High to DMS PMS BMS RD WR Enable 0 ns ieee DMS PMS BMS RD WR Enable to CLKOUT High 0 25 7 ns DMS PMS BMS RD WR Disable to BGH Low 0 ns BGH High to DMS PMS BMS RD WR Enable 0 ns NOTES TBR is an asynchronous signal If BR meets the setup hold requirements it will be recognized during the current clock cycle otherwise the signal will be recognized on the following cycle Refer to the ADSP 2100 Family U se s M anual for BR BG cycle relationships BGH is asserted when the bus is granted and the processor requires control of the bus to continue CLKOUT C BR N tes CLKOUT PMS DMS BMS RD WR gt BG tse 8 5 lt Figure 10 Bus Request Bus Grant REV A 21 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2171 ADSP 2172
13. 8 ns Timing Requirement CLKIN Period 60 150 ns CLKIN Width Low 20 ns CLKIN Width High 20 ns Switching Characteristic CLKOUT Width Low Q 5tck 7 ns CLKOUT Width igh 0 5tck 7 ns CLKIN High to CLKOUT High 0 20 ns Control Signals Timing Requirement tasp RESET Width Low 5tck1 ns NOTE 1Applies after power up sequence is complete Internal phase lock loop requires no more than 2000 cycles assuming stable not including crystal oscillator start up time CLKIN CLKOUT Figure 8 Clock Signals REV A 19 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2171 ADSP 2172 Parameter Min Max Unit Interrupts and Flags Timing Requirement ties IRQx FI Setup before CLK OUT Low 0 25tcx 15 ns IRQx or FI Hold after CLK OUT Hight 2 3 0 25tc ns Switching C haracteristic trou Flag Output H old after CLKOUT Low O 5tck 7 ns trop Flag Output D elay from CLK OUT Low 0 5tck 5 ns NOTES Nf IRQx and inputs meet tc and setup hold requirements they will be recognized during the current clock cycle otherwise the signals will be recognized on the following cycle Refer to Interrupt Controller Operation in the Program Control chapter of the U ser s M anual for further information on interrupt servicing Edge sensitive interrupts require pulse widths greater than 10 ns level sensitive interrupts must
14. is the difference of tu and tpecay as shown in the Output nable D isable diagram T he time is the interval from when a reference signal reaches a high or low volt age level to when the output voltages have changed by 0 5 V from the measured output high or low voltage T he decay time 30 tpecay 15 dependent on the capacitative load C and the cur rent load on the output pin It can be approximated by the following equation C 0 5V toecay i from which tois ty EASURED toecay is calculated If multiple pins such as the data bus are dis abled the measurement value is that of the last pin to stop driving 3 0V INPUT 1 5V 0 0V 2 0V OUTPUT 1 5V 0 3V Figure 21 Voltage Reference Levels for AC Measure ments Except Output Enable Disable Output Enable Time Output pins are considered to be enabled when that have made atransition from a high impedance state to when they start driv ing T he output enable time tena is the interval from when reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point as shown in the Output Enable D isable diagram If multiple pins such as the data bus are enabled the measurement value is that of the first pin to start driving REFERENCE SIGNAL Von MEASURED Von MEASURED MEASURED 0 5V OUTPUT MEASURED 0 5V 1 0V Vo
15. 2171 ADSP 2172 ADSP 2173 OUTLINE DIMENSIONS 128 Lead Metric Thin Plastic Quad Flatpack PQFP SEATING PLANE E q VIEW PINS DOWN 50 REV A ADSP 2171 ADSP 2172 ADSP 2173 ORDERING GUIDE Ambient Instruction Temperature Rate Package Part Number Range MHz Description ADSP 2171K ST 133 0 to 70 C 33 33 128 Lead ADSP 2171BST 133 40 C to 85 C 33 33 128 Lead ADSP 2171K S 133 0 to 70 C 33 33 128 Lead PQFP ADSP 2171BS 133 40 C to 85 33 33 128 Lead ADSP 2171K ST 104 0 to 70 C 26 128 Lead ADSP 2171BST 104 40 C to 85 C 26 128 L ead ADSP 2171K S 104 0 to 70 C 26 128 Lead PQFP ADSP 2171BS 104 40 C to 85 C 26 128 Lead PQFP ADSP 2173BST 80 40 C to 85 C 20 128 Lead ADSP 2173BS 80 40 C to 85 C 20 128 Lead PQFP Refer to section titled Ordering Procedure for ADSP 2172 ROM Processors for information about ordering ROM coded parts S Plastic Quad Flatpack ST Plastic T hin Quad F latpack REV A 51 lt 6 1 9 86 2 V S f NI 52
16. AD SP 217x s interrupt vector and reset vector map Sixteen condition codes are available F or conditional jump call return or arithmetic instructions the condition can be checked and the operation executed in the same instruction cycle M ultifunction instructions allow parallel execution of an arith metic instruction with up to two fetches or one write to pro cessor memory space during a single instruction cycle Consult the ADSP 2100 Family User s M anual for a complete description of the syntax and an instruction set reference 15 ADSP 2171 ADSP 2172 ADSP 2173 Example C ode T he following example is a code fragment that performs the filter tap update for an adaptive least mean squared algorithm filter N otice that the computations in the instructions are written like algebraic equations MF M X0 MY1 RND MXO DM I2 M 1 error beta MR M X0 M F RND AYO PM 16 5 DO adapt UNTIL CE 1 MXOZDM 12 1 AYO PM 16 7 adapt 16 6 ZAR MR M RND MODIFY 12 M3 Point to oldest data MODIFY 16 M7 Point to start of data Interrupt E nable AD SP 217x supports an interrupt enable instruction Inter rupts are enabled by default at reset T he instruction source code is specified as follows Syntax ENAINTS Description Executing the ENA INTS instruction allows all unmasked interrupts to be serviced again Interrupt Disable
17. ALU MAC SHIFTER TRANSMIT REG zi HIP DATA 154 PORT 0 PORT1 HIP R BUS 1 H F H Figure 1 ADSP 217x Block Diagram 2 REV A ADSP 2171 ADSP 2172 ADSP 2173 T wo data address generators D AG s provide addresses for simultaneous dual operand fetches from data memory and pro gram memory Each DAG maintains and updates four address pointers Whenever the pointer is used to access data indirect addressing it is post modified by the value of one of four pos sible modify registers A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers Efficient data transfer is achieved with the use of five internal buses Program M emory Address PM A Bus Program M emory D ata PM D Bus Data M emory Address DM A Bus Data M Data DM D Bus Result R Bus T hetwo address buses PM A and DM A share a single external address bus allowing memory to be expanded off chip and the two data buses PM D and DM D share a single external data bus Program memory can store both instructions and data permit ting the ADSP 217x to fetch two operands in a single cycle one from program memory and one from data memory T he AD SP 217x can fetch an operand from on chip program memory and the next instruction in the same cycle The memory interface supports slow memories and memory mapped peripherals with programmable wait state generation External devices
18. FL2 96 D19 128 HWR HDS NC These pins M UST remain unconnected 46 REV ADSP 2171 ADSP 2172 ADSP 2173 OUTLINE DIMENSIONS 128 Lead Metric Thin Plastic Quad Flatpack TQFP SEATING D gt PLANE A D te 7 U Ds i ni 103 102 TOP VIEW PINS DOWN SYMBOL MIN MAX A 8 A 005 045 002 0096 ee eae 1575 1600 1625 0 620 04630 0 640 13 1400 1410 0547 0551 0555 D 12501258 0492 045 2175 22 00 2225 0456 0866 0 876 19 90 2020 20 10 0 783 0 787 0792 1850 1858 ___ 0728 eas ums oom 0o30 lt eae as os ons oars B 017 022 027 0007 009 oon __ joom REV A 47 ADSP 2171 ADSP 2172 ADSP 2173 NC HA2 ALE HA1 HAO HSEL HD5 HD4 HD3 HD2 HD1 HDO Vpp GND Vpp A0 A1 A2 A3 4 5 6 CLKIN CLKOUT GND 8 A9 A10 A11 A12 A13 NC MMAP NC NO CONNECT 128 1 PQFP Package Pinout HWR HDS HRD HRW GND GND HSIZE HD6 HD7 HD8 amp HD9 HD10 Vpp HD11 HD12 HD13 HD14 HD15 PWDACK BMS DMS PMS Vpp GND GND WR RD NC NC NC NC NC NC 128L PQFP 28MM x 28MM TOP VIEW PINS DOWN vow gt 7
19. Internal Serial Clock Generation ISCLK DTYPE Data Format Receive Frame Sync Required RFSR 00 right justify zero fill unused MSBs 01 right justify sign extend into unused MSBs Receive Frame Sync Width RFSW 10 compand using 11 using A law Multichannel Frame Delay MFD Only If Multichannel Mode Enabled INVRFS Invert Receive Frame Sync Transmit Frame Sync Required TFSR INVTFS Invert Transmit Frame Sync or INVTDV Invert Transmit Data Valid Transmit Frame Sync Width TFSW Only If Multichannel Mode Enabled ITFS Internal Transmit Frame Sync Enable IRFS Internal Receive Frame Sync Enable or MCL Multichannel Length 1 32 words 0 24 words Only If Multichannel Mode Enabled Control Registers 12 REV A ADSP 2171 ADSP 2172 ADSP 2173 SPORTO SCLKDIV Serial Clock Divide Modulus Ox3FF5 15 14 13 12 11109 8 7 6 5 4 3 2 eee SPORTO RFSDIV Receive Frame Sync Divide Modulus Ox3FF4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SPORTO Autobuffer Control Register 15 14 13 12 1 109 8 7 CLKODIS RBUF CLKOUT Disable Control Bit Receive Autobuffering Enable BIASRND TBUF MAC Biased Rounding Control Bit Transmit Autobuffering Enable TIREG RMREG Transmit Autobuffer Register Receive Autobuffer M Register TMREG RIREG Transmit Autobuffer M Register Receive Autobuffer Register SPORT1 Control Register Ox3FF2 15 14 13 12 11 10
20. SPORT1 Receive or IRQO SPORT1 Transmit or IRQ1 Software 0 Software 1 SPORTO Receive SPORTO Transmit IRG2 Figure 2 Interrupt Registers REV A ADSP 2171 ADSP 2172 ADSP 2173 LOW POWER OPERATION The ADSP 217x has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions T hese modes are Powerdown Idle Slow Idle TheCLKOUT pin may also be disabled to reduce external power dissipation The CLK OUT pin is controlled by Bit 14 of SPORT 0 Autobuffer Control Register D M Ox3F F 3 Powerdown The AD SP 217x processor has low power feature that lets the processor enter a very low power dormant state through hard ware or software control H ere is a brief list of powerdown fea tures Refer to the ADSP 2100 F amily U ser s M anual Chapter 9 System Interface for detailed information about the powerdown feature Powerdown mode holds the processor in CM OS standby with a maximum current of less than 100 uA in some modes Quick recovery from powerdown T he processor begins ex ecuting instructions in as few as 100 CLKIN cycles Support for an externally generated TTL or CM OS processor clock T he external clock can continue running during powerdown without affecting the lowest power rating and 100 CLKIN cycle recovery Support for crystal operation includes disabling the oscillator to save power the processor automaticall
21. and HSEL Low Write Pulse Width HWR Low and HSEL Low 20 WA HSEL Host Write Cycle HWR HACK HD15 0 Host Read Cycle HD15 0 Figure 30 Host Interface Port HMD1 0 HMDO 0 REV A 39 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2173 Parameter Min Max Unit Host Interface Port Separate D ata and Address HM D 1 0 Read Strobe and Write Strobe HM D 0 1 Timing Requirement tusu HA2 0 HRW Setup before Start of Write or Read 8 ns tupsu D ata Setup before End of Write 8 ns D ata H old after End of Write 3 ns HA2 0 HRW Hold after End of Write Read 3 ns tuawe Read or Write Pulse Width 30 ns Switching Characteristic tusuk HACK ow after Start of Write or Read 0 20 ns HACK H old after End of Write Read 0 20 ns tube D ata Enabled after Start of Read 0 ns tupp D ata Valid after Start of Read 23 ns D ata H old after End of Read 0 ns D ata Disabled after End of Read 15 ns NOTES IStart of Write or Read HDS Low and HSEL Low End of Write or Read HDS High and HSEL High Read or Write Pulse Width HDS Low and HSEL Low WWW WWW HA2 0 EIS turwe PP HSEL lt Host Write Cycle HRW gt WAN N 9150 para t VVVVVVVVVVVVVVVVVV HA2 0 AMAA HSEL Host Read Cycle HRW HDS HACK HD1
22. can gain control of external buses with bus request grant signals BR and BG One execution mode Go M ode allows the ADSP 217x to continue running from inter nal memory N ormal execution mode requires the processor to halt while buses are granted In addition to the address and data bus for external memory connection the ADSP 217x has a configurable 8 or 16 bit Host Interface Port HIP for easy connection to a host proces sor The HIP is made up of 16 data address pins and 11 control pins T he HIP is extremely flexible and provides a simple inter face to a variety of host processors For example the M otorola 68000 series the Intel 80C 51 series and the Analog D evices AD 5 2101 can be easily connected to the HIP he host pro cessor can initialize the ASD P 217x s on chip memory through the HIP The ADSP 217x can respond to eleven interrupts T here can be up to three external interrupts configured as edge or level sensi tive and eight internal interrupts generated by the T imer the Serial Ports SPORT 5 the HIP the powerdown circuitry and software T here is also a master RESET signal T he two serial ports provide a complete synchronous serial in terface with optional companding in hardware and a wide vari ety of framed or frameless data transmit and receive modes of operation Each port can generate an internal programmable serial clock or accept an external serial clock Boot circuitry provides for loadin
23. data memory that is registers are accessed by reading and writing data memory locations rather than register names T he particular data memory address is shown with each memory mapped register Register bit values shown on the following pages are the default bit values after reset If no values are shown the bits are indeter minate at reset Reserved bits are shown in gray these bits should always be written with zeros PROGRAM ROM 8K X24 PROGRAM HOST INTERFACE PORT DATA STATUS mares FLAGS gt ALU MAC AR F mao wr SHIFTER CONTROL REGISTERS SPORT 0 CONTROL REGISTERS SPORT 1 0x3FF2 0x3FEF TPERIOD POWERDOWN TCOUNT CONTROL kt 0x3FFB TSCALE LOGIC Figure 7 ADSP 217x Registers Control Register 10 REV A ASTAT 765432 1 00090000 AZ ALU Result Zero AN ALU Result Negative AV ALU Overflow AC ALU Carry AS ALU X Input Sign AQ ALU Quotient MV MAC Overflow SS Shifter Input Sign MSTAT 6543210 ADSP 2171 ADSP 2172 ADSP 2173 SSTAT Read Only 76543210 PC Stack Empty PC Stack Overflow Count Stack Empty Count Stack Overflow Status Stack Empty Status Stack Overflow Loop Stack Empty Loop Stack Overflow L Data Register Bank Select 15 14 13 12 11 0 primary 1 secondary Bit Reverse Mode Enabl
24. ns HAD 15 0 Data Disabled after End of Read 7 ns NOTES IStart of Write or Read HDS Low and HSEL Low End of Write or Read HDS High and HSEL High 3Read or Write Pulse Width HDS Low and HSEL Low ALE thare Host Write Cycle HRW HSEL HACK luasu tuan HD15 0 gt QNA thwoH ALE 4 HRW Host Read Cycle luas lt turwe tusk Figure 17 Host Interface Port HMD1 1 HMDO 1 28 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2171 ADSP 2172 ENVIRONMENTAL CONDITIONS Ambient T emperature Rating Tams case PD x case Case T emperature in C PD Power Dissipation in W T hermal Resistance ase to Ambient T hermal Resistance J unction to A mbient Thermal Resistance Junction to C ase Package Oja Oca TQFP 50 C W 2 C W 48 C W PQFP 41 C 10 C W 31 C W POWER DISSIPATION determine total power dissipation in a specific application the following equation should be applied for each output C xVpp x f load capacitance f output switching frequency Example In an application where external data memory is used and no other outputs are active power dissipation is calculated as follows A ssumptions External data memory is accessed every cycle with 5096 of the address p
25. ns tgs BR Setup before CLK OUT Low 0 25 22 ns Switching Characteristic tsp CLKOUT High to DMS PMS BMS 0 25tc 16 ns RD WR Disable DMS PMS BMS RD WR Disable to BG Low 0 ns tse BG High to DMS PMS BMS RD WR Enable 0 ns DMS PMS BMS RD WR Enable to CLKOUT High 0 25 10 ns DMS PMS BMS RD WR Disable to BGH L ow 0 ns BGH High to DMS PMS BMS RD WR Enable 0 ns NOTES TBR is an asynchronous signal If BR meets the setup hold requirements it will be recognized during the current clock cycle otherwise the signal will be recognized on the following cycle Refer to the ADSP 2100 Family User s M anual for BR BG cycle relationships BGH is asserted when the bus is granted and the processor requires control of the bus to continue CLKOUT tes y CLKOUT PMS DMS BMS RD WR gt tsec BG 150 tse BGH 4 Figure 26 Bus Request Bus Grant REV A 35 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2173 Parameter Min Max Unit Memory Read Timing Requirement trop RD Low to Data Valid O 5tck 15 w ns taa A0 A13 PMS DMS BMS to Data Valid 0 75tc 20 5 w ns troy D ata H old from RD High 0 ns Switching Characteristic tap RD Pulse Width 0 5 5 ns CLKOUT High to RD Low o 0 25tck 5 0 25 10 ns tasr A0 A13 PMS DMS BMS Setup before RD Low 0 25tc
26. occur every other cycle with 1 tg MHz 5096 of the data pins switching Each address and data pin has a 10 pF total load at the pin POWER IDLE n MODES T he application operates at 3 3 and 50 ns 16 Total Power Dissipation xVpp x f 15 14 internal power dissipation from Power vs Frequency ee graph Figure 18 x Vpp x 1 is calculated for each output d a 10 9 xVop xf e IDLE 16 Address DMS x3 32V x20MHz 17 4 mW 2 IDLE 128 Data Output WR x3 3V 10 2 98mW B RD x3 3V 10 2 1 1 5 CLKOUT x3 3V x20MHz 22mW MES RUE TAM ME 12 13 14 15 16 17 18 19 20 30 5 mW 1 tek MHz T otal power dissipation for this example 30 5 mW VALID FOR ALL TEMPERATURE GRADES 1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS 2 IDLE REFERS TO ADSP 2173 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION DEASSERTED PINS ARE DRIVEN TO EITHER GND POWER REFLECTS DEVICE OPERATING WITH CLKOUT DISABLED 3 TYPICAL POWER DISSIPATION AT 3 3V DURING EXECUTION OF IDLE n INSTRUCTION CLOCK FREQUENCY REDUCTION POWER REFLECTS DEVICE OPERATING WITH CLKOUT DISABLED Figure 34 Power vs Frequency REV A 43 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2173 CAPACITIVE LOADING Figures 35 and 36 show the capacitive loading characteristics of the ADSP 2173
27. on the human body and equipment and can discharge without detection Permanent damage may occur to devices subjected to high energy electrostatic discharges ADSP 217x features proprietary ESD protection circuitry to dissipate high energy discharges Human Body M odel Per method 3015 of M IL ST D 883 the AD SP 217x has been classified as a Class 1 device Proper ESD precautions are recommended to avoid performance degradation or loss of function WARNING rar ESD SENSITIVE DEVICE ality Unused devices must be stored in conductive foam or shunts and the foam should be discharged to the destination before devices are removed ADSP 2171 ADSP 2172 TIMING PARAMETERS GENERAL NOTES U se the exact timing information given Do not attempt to de rive parameters from the addition or subtraction of others While addition or subtraction would yield meaningful results for an individual device the values given in this data sheet reflect statistical variations and worst cases Consequently you cannot meaningfully add up parameters to derive longer times TIMING NOTES Switching characteristics specify how the processor changes its signals Y ou have no control over this timing it is dependent on the internal design T iming requirements apply to signals that are controlled outside the processor such as the data input for a read operation Timing requirements guarantee that the processor operates cor rectly wi
28. 000 8000 00 0001 8000 00 0000 8001 00 0001 8001 00 0000 7FFF 00 0001 7FFF 00 0001 8000 00 0002 8000 00 0001 8001 00 0002 8001 00 0000 7FFF 00 0001 7FFF 00 0000 8000 00 0002 8000 00 0001 8001 00 0002 8001 00 0000 7FFF 00 0001 7FFF T his mode only has an effect when the M RO register contains 0x8000 all other rounding operation work normally T his mode was added to allow more efficient implementation of bit speci fied algorithms which specify biased rounding such as the GSM speech compression routines U nbiased rounding is preferred for most algorithms Note BIASRND bit is Bit 12 of the SPORT 0 Autobuffer Control register REV A INSTRUCTION SET DESCRIPTION The AD SP 217x assembly language instruction set has an alge braic syntax that was designed for ease of coding and read ability T he assembly language which takes full advantage of the processor s unique architecture offers the following benefits T he algebraic syntax eliminates the need to remember cryptic assembler mnemonics F or example a typical arithmetic add instruction such as AR 2 AYO resembles a simple equation Every instruction assembles into a single 24 bit word that can execute in a single instruction cycle T he syntax is a superset AD SP 2100 F amily assembly lan guage and is completely source and object code compatible with other family members Programs may need to be relo cated to utilize internal memory and conform to the
29. 2 64 or 128 T his instruction keeps the proces sor fully functional but operating at the slower clock rate While it is in this state the processor s other internal clock signals such as SCLK CLKOUT and timer clock are reduced by the same ratio T he default form of the instruction when no clock divisor is given is the standard IDLE instruction When the IDLE n instruction is used it effectively slows down the processor s internal clock and thus its response time to in coming interrupts the 1 cycle response time of the standard idle state is increased by n the clock divisor When an enabled interrupt is received the AD SP 217x will remain in the idle state for up to a maximum of n processor cycles n 16 32 64 or 128 before resuming normal operation When the IDLE n instruction is used in systems that have externally generated serial clock SC L the serial clock rate may be faster than the processor s reduced internal clock rate U nder these conditions interrupts must not be generated at a faster rate than can be serviced due to the additional time the processor takes to come out of the idle state a maximum of n processor cycles SYSTEM INTERFACE Figure 3 shows a basic system configuration with the AD SP 217x two serial devices a host processor aboot EPROM and optional external program and data memories Up to 14K words of data memory and 16K words of program memory can be sup ported Progr
30. 217x incorporates two complete synchronous serial ports SPORT 0 and SPORT 1 for serial communications and multiprocessor communication Here is a brief list of the capabilities of the ADSP 217x SPORT s Refer to the ADSP 2100 Family U se s M anual for further details SPORT sare bidirectional and have a separate double buffered transmit and receive section SPORT scan use an external serial clock or generate their own serial clock internally SPORT s have independent framing for the receive and trans mit sections Sections run in a frameless mode or with frame synchronization signals internally or externally generated Frame sync signals are active high or inverted with either of two pulse widths and timings SPORT s support serial data word lengths from 3 to 16 bits and provide optional A law and u law companding according to CCITT recommendation G 711 SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer SPORT 5 receive and transmit an entire circular buffer of data with only one overhead cycle per data word An interrupt is generated after a data buffer transfer SPORT 0 has a multichannel interface to selectively receive and transmit a 24 or 32 word time division multiplexed serial bitstream SPORT 1 can be configured to have two external interrupts IRQO and IRQ1 and the Flag and Flag Out signals T internally generated serial clock may
31. 4K by 8 bit space divided into eight separate 8K by 8 bit pages T hree bits in the system control register select which page is loaded by the boot memory interface Another bit in the system control regis ter allows the user to force a boot loading sequence under soft ware control Boot loading from page 0 after RESET is initiated automatically if M M AP 0 T he boot memory interface can generate 0 to 7 wait states it defaults to 7 wait states after RESET T his allows the ADSP 217x to boot from a single low cost EPROM such as a 27C256 Program memory is booted one byte at a time and converted to 24 bit program memory words T he BMS and RD signals are used to select and to strobe the boot memory interface Only 8 bit data is read over the data bus on pins D8 D 15 T o accommodate addressing up to eight pages of boot memory the two M SBs of the data bus are used in the boot memory interface as the two M SBs of the boot space address The ADSP 2100 F amily Assembler and Linker support the cre ation of programs and data structures requiring multiple boot pages during execution RD and WR must always be qualified by PMS DMS or BMS to ensure the correct program data or boot memory accessing HIP Booting The ADSP 217x can also boot programs through its H ost Inter face Port BMODE 1 and M M AP 0 the ADSP 217x boots from the HIP If BM ODE 0 the ADSP 217x boots through the data bus in the same way as the AD SP 2101
32. 5 0 Figure 31 Host Interface Port HMD1 0 HMDO 1 40 REV A ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2173 Parameter Min Max Unit Host Interface Port M ultiplexed D ata and Address HM D1 1 Read Strobe Write Strobe HM D 0 0 Timing Requirement ALE Pulse Width 15 ns tuasu HAD 15 0 Address Setup before ALE Low 5 ns 15 0 Address old after ALE Low 2 ns tuacs Start of Write or Read after ALE Low 2 15 ns HAD 15 0 Data Setup before End of Write 8 ns HAD 15 0 Data Hold after End of Write 3 ns turwe Read or Write Pulse Width 30 ns Switching Characteristic tusuk HACK Low after Start of Write Read 2 0 20 ns HACK H old after End of Write Read 4 0 20 ns tube HAD 15 0 Data Enabled after Start of Read 0 ns HAD 15 0 Data Valid after Start of Read 23 ns 15 0 Data H old after End of Read 0 ns HAD 15 0 Data Disabled after End of Read 15 ns NOTES IStart of Write HWR Low HSEL Low Start of Read lt HRD Low and HSEL Low 3End of Write HWR High or HSEL High 4End of Read HRD High or HSEL High gt Read Pulse Width HRD Low and HSEL Low Write Pulse Width HWR Low and HSEL Low ALE HSEL Host Write Cycle WWE HACK tuasu WV WWW WOW BOXXX lt ALE gt that lt t HRWP HSEL Host Read Cycle luus HRD lusuk gt
33. 71 ADSP 2172 Parameter Min Max Unit Serial Ports Timing Requirement tsck SCLK Period 50 ns tscs D R TFS RFS Setup before SCLK Low 4 ns tscu DR TFS RFS Hold after SCLK Low 7 ns tscp 5 Width 20 ns Switching Characteristic tec CLKOUT High to SCLK gut 0 25 0 25tc 10 ns SCLK High to DT Enable ns tscpv SCLK High to DT Valid 15 ns try TFS RF Soy Hold after SCLK High 0 ns trp TFS RFSoy7 Delay from SCLK High 15 ns DT Hold after SCLK High 0 ns to DT Enable 0 ns trpv TFS Alt to DT Valid 15 ns tscpp SCLK High to DT Disable 15 ns tapv RFS M ultichannel F rame D elay Zero to DT Valid 15 ns CLKOUT icc tcc SCLK DR RFS TFSin tro tru lt RFSout TFSour tscpp toe ttov TFS ALTERNATE FRAME MODE trov gt RFS MULTICHANNEL MODE FRAME DELAY 0 MFD 0 Figure 13 Serial Ports 24 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2171 ADSP 2172 Parameter Min Max Unit Host Interface Port Separate D ata and Address HM D1 0 Read Strobe and Write Strobe HM D 0 0 Timing Requirement tusu 2 0 Setup before Start of Write or Read 5 ns D ata Setup before End of Write 5 ns D ata H old after End of Write 3 ns tuu H A2 0 Hold after End of Write or Read 4 3 ns turwe Read or Write Pulse Width 20 ns Switching Characteristic tusuk HACK Low after Start of Write or Read 2 0 15 ns
34. 9 8 7 0 T Flag Out Read Only F 3 y SLEN Serial Word Length Internal Serial Clock Generation ISCLK DTYPE Data Format Receive Frame Sync Required RFSR 00 right justify zero fill unused MSBs 01 right justify sign extend into unused MSBs Receive Frame Sync Width RFSW 10 compand using 11 compand using A law Transmit Frame Sync Required TFSR INVRFS Invert Receive Frame Sync Transmit Frame Sync Width TFSW INVTFS Invert Transmit Frame Sync ITFS Internal Transmit Frame Sync Enable IRFS Internal Receive Frame Sync Enable Control Registers REV A 13 ADSP 2171 ADSP 2172 ADSP 2173 SPORT1 SCLKDIV SPORT1 RFSDIV Serial Clock Divide Modulus Receive Frame Sync Divide Modulus 0x3FF1 0x3FF0 15 14 13 12 11 10 9 8 7 15 14 13 12 1110 9 8 7 r 12 2 SPORT1 Autobuffer Control Register 0x3FEF 15 14 13 12 1 10 9 XTALDIS L RBUF XTAL Pin Drive Disable Receive Autobuffer Enable during Powerdown 1 disabled 0 enabled TBUF disable XTAL pin when no external Transmit Autobuffer Enable crystal connected RMREG XTALDELAY Receive M Register 4096 Cycle Delay Enable 1 delay 0 no delay RIREG Receive Register PDFORCE Powerdown Force TMREG Transmit M Register PUCR Powerup Context Reset Enable TIREG 1 soft reset context clear Transmit Register 0 resume execution HIP Data Registers HMASK Register H
35. ANALOG DEVICES DSP Microcomputer ADSP 2171 ADSP 2172 ADSP 2173 FEATURES 30 ns Instruction Cycle Time 33 MIPS from 16 67 MHz Crystal at 5 0 V 50 ns Instruction Cycle Time 20 MIPS from 10 MHz Crystal at 3 3 V ADSP 2100 Family Code amp Function Compatible with New Instruction Set Enhancements for Bit Manipula tion Instructions Multiplication Instructions Biased Rounding and Global Interrupt Masking Bus Grant Hang Logic 2K Words of On Chip Program Memory RAM 2K Words of On Chip Data Memory RAM 8K Words of On Chip Program Memory ROM ADSP 2172 8 or 16 Bit Parallel Host Interface Port 300 mW Typical Power Dissipation at 5 0 V at 30 ns 70 mW Typical Power Dissipation at 3 3 V at 50 ns Powerdown Mode Featuring Less than 0 55 mW ADSP 217Y ADSP 2172 or 0 36 mW ADSP 2173 CMOS Standby Power Dissipation with 100 Cycle Recovery from Powerdown Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU Multiplier Accumulator and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Two Double Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Programmable 16 Bit Interval Timer with Prescaler Programmable Wait State Generation Automatic Booting of Internal Program Memory from Byte Wide External Memory e g EPROM or Through Host Interface Port
36. D Low HSEL Low 3End of Write HWR High or HSEL High 4Read Pulse Width HRD Low and HSEL Low Write Pulse Width HWR Low and HSEL Low of Read HRD High or HSEL High KANN ALE HSEL Host Write Cycle HWR HACK tuasu than HD15 0 ALE lt lunwe Host Read Cycle HSEL 4 thas HRD tuasu Sm WV WV Figure 16 Host Interface Port HMD1 lt 1 HMDO 0 REV A 27 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2171 ADSP 2172 Parameter Min Max Unit Host Interface Port ultiplexed D ata and Address HM D1 1 Read Strobe and Write Strobe HM D 0 1 Timing Requirement ALE Pulse Width 10 ns tHASU HAD15 0 Address Setup before ALE L ow 5 ns tuAH HAD 15 0 Address H old after ALE Low 2 ns tuaLs Start of Write or Read after ALE Low 10 ns tusu HRW Setup before Start of Write or R ead 5 ns lupsu HAD 15 0 Data Setup before End of Write 5 ns HAD 15 0 D ata H old after End of Write 3 ns HRW Hold after End of Write or Read 3 ns Read or Write Pulse Width 20 ns Switching Characteristic tusuk HACK L ow after Start of Write or Read 0 15 ns HACK H old after End of Write or Read 0 15 ns tube HAD 15 0 Data Enabled after Start of Read 0 ns tupp HAD 15 0 Data Valid after Start of Read 18 ns H AD 15 0 D ata H old after End of Read 0
37. D8 A6 D7 A7 06 05 CLKIN CLKOUT D GND ND A8 D2 A9 Di A10 po A11 BG A12 NC A13 BR NC NC MMAP NC NC NC NC BGH PWD NC 89599 gt rrr an m B NC NO CONNECT REV A 45 ADSP 2171 ADSP 2172 ADSP 2173 TQFP Pin Configurations TQFP Pin TQFP Pin TQFP Pin TQFP Pin Number Name Number Name Number Name Number Name 1 GND 33 A13 65 NC 97 D 20 2 GND 34 NC 66 BGH 98 D21 3 HA2 ALE 35 MMAP 67 NC 99 D22 4 1 36 NC 68 NC 100 D23 5 HAO 37 NC 69 NC 101 NC 6 HSEL 38 PWD 70 BR 102 NC 7 HD5 39 IRQ2 71 NC 103 NC 8 HD4 40 NC 72 BG 104 NC 9 HD3 41 BMODE 73 DO 105 NC 10 HD2 42 NC 74 D1 106 RD 11 HD1 43 NC 75 D2 107 WR 12 HDO 44 76 GND 108 GND 13 45 GND 77 D3 109 GND 14 GND 46 RESET 78 D4 110 15 47 NC 79 D5 111 PMS 16 AO 48 HACK 80 D6 112 DMS 17 Al 49 HMDO 81 D7 113 BMS 18 A2 50 HMD1 82 D8 114 PWDACK 19 A3 51 DTO 83 D9 115 HD15 20 A4 52 TFSO 84 D10 116 HD14 21 5 53 RFSO 85 GND 117 HD 13 22 A6 54 DRO 86 118 HD12 23 7 55 SCLKO 87 D11 119 HD11 24 XTAL 56 DT 1 FO 88 D12 120 25 57 89 013 121 10 26 CLKOUT 58 RFS1 IRQO 90 D14 122 HD9 27 GND 59 GND 91 D15 123 HD8 28 A8 60 DRI F1 92 D16 124 HD7 29 A9 61 SCLK1 93 D17 125 HD6 30 10 62 FLO 94 D18 126 HSIZE 31 All 63 FL1 95 GND 127 HRD HRW 32 A12 64
38. DR5 poc Ox3FE8 1514131211109 8 76 54 3 2 1 B 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HDR4 Ox3FEA Host HDR5 Host HDRO HDR3 Host HDR4 Host HDR1 Read Write HDR2 Ox3FE2 Read Write Read Write HDR1 Ox3FE1 Host Host HDRO Host Host HDR5 Read Write 1 Enable 0 Disable Control Registers 14 REV A ADSP 2171 ADSP 2172 ADSP 2173 HSR6 ee 15 14 13 12 11 10 9 8 7 0 2171 HDR5 Write E a 2171 HDR4 Write 2171 HDR3 Write 2171 HDR2 Write 2171 HDR1 Write 2171 HDRO Write Host Write Host HDR1 Write Host HDR2 Write Host HDR3 Write Host HDR4 Write Host HDR5 Write HSR7 pagan 15 14 13 12 11 10 9 8 7 Overwrite Mode Software Reset 2171 HDRO Write 2171 HDR1 Write 2171 HDR2 Write 2171 HDR3 Write 2171 HDR4 Write 2171 HDR5 Write Control Registers Biased Rounding A new mode allows biased rounding in addition to the normal unbiased rounding When the BIASRND bit is set to 0 the nor mal unbiased rounding operations occur When the BIASRN D bit is set to 1 biased rounding occurs instead of the normal un biased rounding When operating in biased rounding mode all rounding operations with M RO set to 0x8000 will round up rather than only rounding odd M R1 values up For example MR value beforeRND biased result unbiased RN D result 00 0
39. FSour Delay from SCLK High 20 ns tscpH DT Hold after SCLK High 0 ns to DT Enable 0 ns TFS AIt to DT Valid 19 ns tscpp SCLK High to DT Disable 25 ns tkov RFS M ultichannel F rame D elay Zero to DT Valid 20 ns CLKOUT tec tec SCLK DR RFS TFSin tro gt TFSour tscpp tscpv DT tre ttov TFS ALTERNATE FRAME MODE trov gt RFS MULTICHANNEL MODE FRAME DELAY 0 MFD 0 Figure 29 Serial Ports 38 REV A ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2173 Parameter Min Max Unit Host Interface Port Separate D ata and Address HM D1 0 Read Strobe and Write Strobe HM D 0 0 Timing Requirement tusu HA2 0 Setup before Start of Write or Read 2 8 ns D ata Setup before End of Write 8 ns tuwpH D ata H old after End of Write 3 ns HA2 0 Hold after End of Write or Read 4 3 ns turwe Read or Write Pulse Width 30 ns Switching Characteristic tusuk HACK Low after Start of Write or Read 2 0 20 ns HACK H old after End of Write Read 4 0 20 ns D ata Enabled after Start of Read 0 ns D ata Valid after Start of Read 23 ns D ata H old after End of Read 0 ns D ata Disabled after End of Read 15 ns NOTES IStart of Write HWR Low HSEL Low Start of Read lt HRD Low and HSEL Low 3End of Write HWR High or HSEL High 4End of Read HRD High or HSEL High Read Pulse Width HRD Low
40. L VoL MEASURED 4 toecay MEASURED OUTPUT STOPS OUTPUT STARTS DRIVING DRIVING HIGH IMPEDANCE STATE TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1 5V Figure 22 Output Enable Disable oL TO OUTPUT 1 5V PIN 50pF lou Figure 23 Equivalent Device Loading for AC Measure ments Including Fixtures REV A ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2173 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade B Grade Parameter Min Max Min Max Unit Supply Voltage 3 0 3 6 3 0 3 6 V TAMB Ambient Operating T emperature 0 70 40 85 C ELECTRICAL CHARACTERISTICS K B Grades Parameter Test Conditions Min Max Unit i L evel Input Voltage 2 Vpp max 2 0 V Vin Hi Level CLKIN Voltage 9 Vpp max 2 0 V Vin Hi Level RESET Voltage Vpp Max 2 2 V Vu o L evel Input Voltage 3 min 0 4 V evel Output Voltage 5 8 Vpp min lou 0 5 mA 2 4 V min 100 mA Vpp 0 3 V Lo Level Output Voltage gt 9 Vpp 2 min 22 mA 0 4 V i L evel Input C urren max Vin Vpp max 10 lu Lo L evel Input Current 9 max Vin 0V 10 lozu T ristate C urrent max Vin Vpp max 10 T ristate eakage C urrent 9 Vpp 2 max Vin 0 y8 10 lop Supply Current Idle 10 max 7 mA Ipp Supply Current D 0 9
41. Levels for AC Measure ments Except Output Enable Disable Output Enable Time Output pins are considered to be enabled when that have made atransition from a high impedance state to when they start driv ing T he output enable time tena is the interval from when reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point as shown in the Output Enable D isable diagram If multiple pins such as the data bus are enabled the measurement value is that of the first pin to start driving REFERENCE SIGNAL Von MEASURED Von MEASURED MEASURED 0 5V OUTPUT MEASURED 0 5V 1 0V VoL VoL MEASURED toecay MEASURED OUTPUT STOPS OUTPUT STARTS DRIVING DRIVING HIGH IMPEDANCE STATE TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1 5V Figure 38 Output Enable Disable lo Figure 39 Equivalent Device Loading for AC Measure ments Including All Fixtures REV A ADSP 2171 ADSP 2172 ADSP 2173 128 1 TQFP Package Pinout HWR HDS HRD HRW HSIZE HD6 HD7 HD8 HD9 HD10 Vpp HD11 HD12 HD13 HD14 HD15 PWDACK BMS DMS PMS Vpp GND GND WR RD NC NC NC GND N HA2 ALE 023 022 HAO 021 HSEL D20 HD5 D19 HD4 GND HD3 D18 HD2 D17 HD1 D16 HDO 015 014 GND D13 012 0 Dii p Vpp TOP VIEW OND A2 PINS DOWN D10 A4 D9 A5
42. OMENABLE 1 8K INTERNAL ROM ROMENABLE DEFAULTS OR OR DURING RESET 8K EXTERNAL ROMENABLE 0 8K EXTERNAL ROMENABLE 0 27FF 2800 27FF 2800 27FF 2800 4K EXTERNAL 6K 37FF EXTERNAL 3800 6K EXTERNAL 2K INTERNAL RAM 3FFF 3FFF 3FFF 1 BMODE 1 0 BMODE 0 or 1 MMAP lt 1 BMODE 0 Figure 5 ADSP 217x Memory Maps When M MAP 1 words of external program memory begin at address 0x0000 and internal RAM is located in the upper 2K words beginning at address 0x3800 In this configuration pro gram memory is not loaded although it can be written to and read from under program control The optional ROM always resides at locations PM 0x0800 through PM 0x27F F regardless of the state of the M M AP pin TheROM is enabled by setting the ROM ENABLE bit in the D ata emory Wait State control register DM Ox3F F E When the ROM ENABLE bit is set to 1 addressing program memory in this range will access the on chip When set to zero addressing program memory in this range will access external program memory T he ROM ENABLE bit is set to 0 on chip re set unless and ODE 1 T he program memory interface can generate 0 to 7 wait states for external memory devices default is to 7 wait states after RESET Boot Memory Interface AD SP 217x can load on chip memory from external boot memory space T he boot memory space consists of 6
43. Parameter Min Max Unit Memory Read Timing Requirement trop RD Low to Data Valid O 5tck 9 w ns taa A0 A13 PMS DMS BMS to Data Valid 0 75tc 105 w ns troy D ata H old from RD High 0 ns Switching Characteristic tap RD Pulse Width Q 5tck 5 w ns CLKOUT High to RD Low o 0 25 5 0 25 7 ns tasr A0 A13 PMS DMS BMS Setup before RD Low 0 25tc 6 ns tn pA A0 A13 PMS DMS BMS Hold after RD Deasserted 0 25tcx 3 ns trRwR RD High to RD or WR Low 0 5tck 5 ns w wait states x CLKOUT Figure 11 Memory Read 22 REV A ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2171 ADSP 2172 Parameter Min Max Unit Memory Write Switching Characteristic tow D ata Setup before WR High O 5tc 7 W ns Data Hold after WR High 0 25tck 2 ns twe WR Pulse Width 0 5 5 w ns twoe WR Low to Data Enabled 0 ns tasw A0 A13 DMS PMS Setup before WR Low 0 25tc 6 ns D ata Disable before WR or Low 0 25tc 7 ns tcwR CLKOUT High to WR Low 0 25 5 0 25 7 ns taw A0 A13 DMS PMS Setup before WR D easserted 0 75tc 9 w ns twra A0 A13 DMS PMS Hold after WR D easserted 0 25 5 twwr WR High to RD or WR Low Q 5tck 5 ns w wait states x REV A CLKOUT DEM m V E M 0 13 Figure 12 Memory Write 23 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 21
44. Stand Alone ROM Execution Optional Single Cycle Instruction Execution Single Cycle Context Switch Multifunction Instructions Three Edge or Level Sensitive External Interrupts Low Power Dissipation in Standby Mode 128 Lead TQFP and 128 Lead PQFP GENERAL DESCRIPTION The ADSP 2171 AD 5 2172 ADSP 2173 are single chip microcomputers optimized for digital signal processing D SP and other high speed numeric processing applications T he ADSP 2171 and ADSP 2172 are designed for 5 0 V applica tions The ADSP 2173 is designed for 3 3 V applications T he AD SP 2172 also has words 24 bit of program REV Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM PROGRAM ROM 8 24 POWERDOWN CONTROL MEMORY DATA LOGIC 2 24 EN EXTERNAL 8 Hoe 3 TT J umma EXTERNAL DATA ARITHMETIC UNITS BUS ADSP 2100 BASE ARCHITECTURE The AD SP 217x combines the AD SP 2100 base architecture three computational units d
45. ad 7 ns NOTES IStart of Write or Read HDS Low HSEL Low End of Write or Read HDS High and HSEL High 3Read or Write Pulse Width HDS Low and HSEL Low HSEL 4 Host Write Cycle HRW HACK gt 1 HKH t 2 0 HSEL Host Read Cycle HRW HACK HD15 0 HWDH Figure 15 Host Interface Port HMD1 0 HMDO 1 26 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2171 ADSP 2172 Parameter Min Max Unit Host Interface Port M ultiplexed D ata and Address HM D1 1 Read Strobe and Write Strobe HM D 0 0 Timing Requirement ALE Pulse Width 10 ns tHASU HAD15 0 Address Setup before ALE Low 5 ns 15 0 Address old after ALE Low 2 ns tuaLS Start of Write or Read after ALE 2 10 ns HAD 15 0 Data Setup before End of Write 5 ns tuwpH HAD 15 0 Data H old after End of Write 3 ns Read Write Pulse Width 20 ns Switching Characteristic tusuk HACK Low after Start of Write or Read 2 0 15 ns HACK old after End of Write or Read 5 0 15 ns HAD 15 0 Data Enabled after Start of Read 0 ns HAD 15 0 Data Valid after Start of Read 18 ns 15 0 Data H old after End of Read 0 ns 15 0 Data Disabled after End of Read 7 ns NOTES IStart of Write HWR Low HSEL Low Start of Read HR
46. address buses and the PMS DMS BMS RD WR output drivers asserting the bus grant BG signal and halting program execution If the Go M ode is enabled the AD SP 217x will not halt pro gram execution until it encounters an instruction that requires an external memory access If the ADSP 217x is performing an external memory access when the external device asserts the BR signal then it will not three state the memory interfaces or assert the BG signal until the processor cycle after the access completes which can be up to eight cycles later depending on the number of wait states T he instruction does not need to be completed when the bus is granted If a single instruction requires two external memory ac cesses the bus will be granted between the two accesses When the BR signal is released the processor releases the BG signal reenables the output drivers and continues program ex ecution from the point where it stopped T he bus request feature operates at all times including when the processor is booting and when RESET is active The new Bus Grant H ang logic and associated BGH pin allow the ADSP 217x to operate in a multiprocessor environment with a minimal number of wasted processor cycles T he bus grant hang pin is asserted when the AD SP 217x desires a cycle PROGRAM SEQUENCER ICNTL SSTAT IMASK CNTR MSTAT OWRCNTR ASTAT COUNT STATUS
47. addresses up to 16K words 10K words of memory for ADSP 217x with optional 8K ROM and 2K words of memory for the non ROM version are on chip T he data bus is bidirec tional and 24 bits wide to external program memory Program memory may contain code and data T he program memory data lines are bidirectional T he program memory select PMS signal indicates access to the program memory and can be used as a chip select signal T he write WR signal indicates a write operation and is used as a write strobe T he read RD signal indicates a read operation and is used as a read strobe or output enable signal The AD SP 217x writes data from its 16 bit registers to the 24 bit program memory using the PX register to provide the lower eight bits When it reads data not instructions from 24 bit pro gram memory to a 16 bit data register the lower eight bits are placed in the PX register Program Memory Maps ADSP 217x Program memory can be mapped in two ways depending on the state of the M M AP pin Figure 5 shows the different configura tions When MM AP 0 internal RAM occupies 2K words be ginning at address 0x0000 In this configuration the boot loading sequence described in Boot M emory Interface is au tomatically initiated when RESET is released 0000 0000 0000 2K 2K INTERNAL RAM TERNAL INTERNAL RAM BOOTED _ o7FF BOOTED FF 0800 0800 0800 8K INTERNAL ROM ROMENABLE 1 8K INTERNAL ROM R
48. ammable wait state generation allows the processor to interface easily to slow memories he AD SP 217x also pro vides one external interrupt and two serial ports or three exter nal interrupts and one serial port Clock Signals The ADSP 217x can be clocked by either a crystal or bya TTL compatible clock signal TheCLKIN input cannot be halted changed during operation or operated below the specified frequency during normal opera tion T he only exception is while the processor is in the Power down State For additional information refer to C hapter 9 ADSP 2100 Family U se s M anual for detailed information on this powerdown feature If an external clock is used it should be a T T L compatible sig nal running at half the instruction rate T he signal is connected to the processor s CLKIN input When an external clock is used the XTAL input must be left unconnected TheADSP 217x uses an input clock with a frequency equal to half the instruction rate a 16 67 M Hz input clock yields a 30 ns processor cycle which is equivalent to 33 M H z N ormally in structions are executed in a single processor cycle All device timing is relative to the internal instruction clock rate which is indicated by the CLK OUT signal when enabled REV A ADSP 2171 ADSP 2172 ADSP 2173 CLOCK OR CRYSTAL CLKIN XTAL PWD PWDACK CLKOUT RESET IRQ2 ADSP 217x ADDRESS DATA L D PROGRAM MEMORY OPTIONAL NOTE
49. as described above in Boot M emory Interface For additional in formation about H IP booting refer to the ADSP 2100 Family User s M anual Chapter 7 Host Interface Port The AD SP 2100 Family D evelopment Software includes a util ity program called the HIP Splitter T his utility allows the cre ation of programs that can be booted via the AD SP 217X s HIP in a similar fashion as EPROM bootable programs generated by the PROM Splitter utility REV A ADSP 2171 ADSP 2172 ADSP 2173 Stand Alone ROM Execution When the and BM ODE pins both are set to 1 the ROM is automatically enabled and execution commences from program memory location 0x0800 at the start of T his feature lets an embedded design operate without external memory components T o operate in this mode the ROM coded program must copy an interrupt vector table to the appropriate locations in program memory In this mode the ROM enable bit defaults to 1 during reset Tablelll Boot Summary Table BMODE 0 BMODE 1 0 Boot from EPROM Boot from HIP then then execution starts execution starts at at internal RAM internal RAM location location 0x0000 0x0000 1 No booting execution Stand Alone M ode execution starts at internal ROM location 0x0800 starts at external memory location 0x0000 Ordering Procedure for ADSP 2172 Processors T o place an order for a custom ROM coded ADSP 2172 p
50. ata address generators and a pro gram sequencer with two serial ports a host interface port a programmable timer extensive interrupt capabilities and on chip program and data memory In addition the AD SP 217x supports new instructions which include bit manipulations bit set bit clear bit toggle bit test new ALU constants new multiplication instruction x squared biased rounding and global interrupt masking for increased flexibility T he AD SP 217x also has a Bus Grant H ang Logic feature TheADSP 217x provides 2K words 24 bit of program RAM and 2K words 16 bit of data memory T he ADSP 2172 pro vides an additional 8K words 24 bit of program ROM Power down circuitry is also provided to meet the low power needs of battery operated portable equipment T he AD SP 217x is avail able 128 pin T QFP and 128 pin PQFP packages Fabricated in a high speed double metal low power CM OS process the ADSP 217X operates with a 30 ns instruction cycle time Every instruction can execute in a single processor cycle The ADSP 217x s flexible architecture and comprehensive in struction set allow the processor to perform multiple operations in parallel In one processor cycle the AD SP 217x can e generate the next program address e fetch the next instruction perform one or two data moves update one or two data address pointers perform a computational operation T his takes place while the processo
51. d the shifter T he computational units process 16 bit data directly and have provi sions to support multiprecision computations The ALU per forms a standard set of arithmetic and logic operations division primitives are also supported T he M AC performs single cycle multiply multiply add and multiply subtract operations with 40 bits of accumulation T he shifter performs logical and arithmetic shifts normalization denormalization and derive exponent operations T he shifter can be used to efficiently implement numeric format control including multiword and block floating point representations T he internal result R bus directly connects the computational units so that the output of any unit may bethe input of any unit on the next cycle A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu tational units T he sequencer supports conditional jumps sub routine calls and returns in a single cycle With internal loop counters and loop stacks the AD SP 217x executes looped code with zero overhead no explicit jump instructions are required to maintain the loop POWER DOWN 42 K BOOT LOGIC ADDRESS GENERATOR 3 EZ EXTERNAL JE ADDRESS 14 BUS ee Ju pe _____ 7 Ll lalLcllIlloOo U PMD BUS DATA 24 BUS en DMD BUS CONTROL COMPANDING HIP REGS INPUTREGS TIMER coll L KZ
52. e DAG1 ALU Overflow Latch Mode Enable AR Saturation Mode Enable MAC Result Placement 0 fractional 1 integer Timer Enable Go Mode Enable System Control Register 10 9 SPORTO Enable 1 enabled 0 disabled PWAIT Program Memory SPORT Enable COUPES MES 1 enabled 0 disabled Boot Wait States BPAGE SPORT1 Configure Boot Page Select 1 serial port 0 FI IRQO IRQ1 SCLK 15 14 13 12 11 BFORCE Boot Force Bit Timer 10 9 TPERIOD Period Register Ox3FFD TCOUNT Counter Register Ox3FFC TSCALE Scaling Register Ox3FFB Control Registers REV A 11 ADSP 2171 ADSP 2172 ADSP 2173 ROM Enable Data Memory Wait State Control Register Ox3FFE 15 14 13 12 11 109 8 7 6 5 4 3 2 DWAITA DWAIT2 DWAIT1 DWAITO ROM enable 1 enable 0 disable SPORTO Multichannel Receive Word Enable Registers SPORTO Multichannel Transmit Word Enable Registers 1 Channel Enabled 1 Channel Enabled 0 Channel Ignored 0 Channel Ignored Ox3FFA Ox3FF8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Ox3FF9 Ox3FF7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 1110 9 8 7 6 5 4 2 02000 SPORTO Control Register Ox3FF6 15 14 13 12 1110 9 8 7 0 E Multichannel Enable MCE SLEN Serial Word Length
53. e external interrupt input pins IRQO IRQ1 and IRQ2 IRQ2 is always available as a dedi cated pin SPORT 1 may be reconfigured for IRQO IRQI and the flags The AD SP 217x also supports internal interrupts from the timer the host interface port the two serial ports software and the powerdown control circuit T he interrupt levels are in ternally prioritized and individually maskable except power down and reset T he input pins can be programmed to be either level or edge sensitive T he priorities and vector ad dresses of all interrupts are shown in T able II and the interrupt registers are shown in Figure 2 Interrupts be masked or unmasked with the IM ASK regis ter Individual interrupt requests are logically AN D ed with the bits in IM ASK the highest priority unmasked interrupt is then selected T he powerdown interrupt is nonmaskable The AD SP 217x masks all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register T his does not affect autobuffering he interrupt control register ICNTL allows the external in terrupts to be either edge or level sensitive Interrupt routines can either be nested with higher priority interrupts taking prece dence or processed sequentially ThelFC register is a write only register used to force and clear interrupts generated from software ICNTL 4 3 2 15 14 13 12 11 10 9 TT TT nnn n Tab
54. ection PSee Chapter 9 of the ADSP 2100 F amily U ser s M anual for details PApplies to T QFP and PQFP package types utput pin capacitance is the capacitve load for any three state output pin Specifications subject to change without notice REV A 31 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2173 TIMING PARAMETERS GENERAL NOTES U se the exact timing information given D o not attempt to de rive parameters from the addition or subtraction of others While addition or subtraction would yield meaningful results for an individual device the values given in this data sheet reflect statistical variations and worst cases Consequently you cannot meaningfully add up parameters to derive longer times TIMING NOTES Switching characteristics specify how the processor changes its signals Y ou have no control over this timing it is dependent on the internal design T iming requirements apply to signals that are controlled outside the processor such as the data input for a read operation Timing requirements guarantee that the processor operates rectly with another device Switching characteristics tell you what the device will do under a given circumstance Also use the switching characteristics to ensure any timing requirement of a device connected to the processor such as memory is satisfied MEMORY REQUIREMENTS T his chart links common memory device specification names and ADSP 2173 timing
55. egisters for the sys tem timer wait state configuration host interface port and se rial port operations are located in this region of memory 0000 0000 DWAIT 0 EXTERNAL DWAIT 1 0400 EXTERNAL o7FF 0800 12K EXTERNAL DWAIT 2 10K EXTERNAL 2FFF 3000 2FFF 3000 2K INTERNAL DATA RAM 37FF K 3800 RESERVED 3BFF 3C00 NO WAIT STATES MEMORY MAPPED REGISTERS RESERVED WAIT STATES Figure 6 ADSP 217x Data Memory Map T he remaining 12K of data memory is external External data memory is divided into three zones each associated with its own wait state generator By mapping peripherals into different zones you can accommodate peripherals with different wait state requirements All zones default to 7 wait states after RESET F or compatibility with other AD SP 2100 F amily pro cessors bit definitions for DWAIT 3 and DWAIT 4 are shown in the D ata M emory Wait State Control Register but they are not used by the ADSP 217x ADSP 2171 ADSP 2172 ADSP 2173 Bus Request amp Bus Grant TheADSP 217x can relinquish control of the data and address buses to an external device When the external device requires access to memory it asserts the bus request BR signal If the ADSP 217x is not performing an external memory access then it responds to the active BR input in the following processor cycle by three stating the data and
56. ent max Vin 0 y8 10 uA lop Supply Current Idle 10 max 18 mA Ipp Supply Current D ynamic 9 max 30 nsi 75 mA lop Supply Current Powerdown Lowest Power M ode 100 Ci Input Pin Capacitance 9 13 Vin 22 5 V fin 1 0MHz Tame 25 8 pF Co Output Pin Capacitance 7 13 14 22 5 V fin lt 1 0 M Hz Tame 25 8 pF NOTES Bidirectional pins D 0 0 23 RFSO RFS1 SCLK O 5 1 TFSO 51 0 15 15 2Input only pins RESET IRQ2 BR MM AP DRO DR1 HSEL HSIZE BM ODE HM DO HM D1 HRD HWR HWR HDS PWD HA2 ALE 1 0 3 nput only pins CLKIN RESET 1802 BR MM AP DRO DR1 HSIZE ODE HM DO HM D1 HRD HWR HWR HDS PWD HA2 ALE 1 0 Output pins BG PMS DMS BMS RD WR PWDACK 0 13 DT 1 CLKOUT HACK FL2 0 Although specified for TTL outputs all AD SP 2171 AD SP 2172 outputs are OS compatible and will drive to V pp and GND assuming no dc loads 66 uaranteed but not tested T hree statable pins 0 13 00 023 PMS DMS BMS RD WR DT1 SCLKO SCLK 1 TFSO TFS1 RFSO RSF1 HDO HD15 HADO HAD15 80 V on BR CLKIN Active to force three state condition Idle refers to AD SP 2171 AD SP 2172 state of operation during execution of ID LE instruction D easserted pins are driven to either V or GND Current reflects device operation with CLK OUT disabled 10C ur
57. g on chip program memory automatically from byte wide external memory After reset seven wait states are automatically generated T his allows for example a 30 ns AD SP 217x to use an external 200 ns EPROM as boot memory M ultiple programs can be selected REV A and loaded from the EPROM with no additional hardware T he on chip program memory can also be initialized through the HIP T he AD SP 217x features three general purpose flag outputs whose states can be simultaneously changed through software You can use these outputs to signal an event to an external device In addition the data input and output pins on SPORT 1 can be alternatively configured as an input flag and an output flag A programmable interval timer generates periodic interrupts A 16 bit count register T COUNT is decremented every pro cessor cycles where is a scaling value stored in 8 bit regis ter TSCALE When the value of the count register reaches zero an interrupt is generated and the count register is reloaded from a 16 bit period register T PERIOD The AD SP 217x instruction set provides flexible data moves and multifunction one or two data moves with a computation instructions Every instruction can be executed in a single pro cessor cycle T he ADSP 217x assembly language uses an alge braic syntax for ease of coding and readability A comprehensive set of development tools supports program development Serial Ports The ADSP
58. ins switching External data memory writes occur every other cycle with 5096 of the data pins switching Each address and data pin has a 10 pF total load at the pin T he application operates at 5 0 V and 30 ns Total Power Dissipation xVpp x f internal power dissipation from Power vs Frequency graph Figure 18 C x x f is calculated for each output Pins x C x Vpp xf Address DMS 8 x10pF x52V 333 2 66 6 mW Data Output WR 9 x10pF 52 x1667MHz 37 5 mW RD 1 x10pF x52V x1667MHz 4 2 mW CLKOUT 1 x10pF x52V x333MHz 83mW 116 6 mW T otal power dissipation for this example is 116 6 mW REV A 29 POWER INTERNAL 400 382mW 375 350 325 301mW 300 5 5 275 Il 250 5 0V pp 5 229mW 225 186mW 200 45 175 150 125 110mW 13 15 17 19 21 23 25 27 29 31 33 1 tox 7 MHz 1 2 POWER IDLE 85 82mW 80 75 70 tf 65 Vpp 55V 64mW 1 60 B gs 1 OW 5 0V 50 48mW 6 5 45V 40 3ymw 35 30 13 15 17 19 21 23 25 27 29 31 33 1 ty MHz POWER DLE n MODES 3 IDLE z E I a tc o IDLE 16 IDLE 128
59. its may be applied toward the minimum order quantity REV A U pon completion of the prototype manufacture Analog D evices will ship prototype units and a delivery schedule update for pro duction units An invoice against your purchase order for the NRE charges is issued at this time T here is a charge for each ROM mask generated and a mini mum order quantity Consult your sales representative for details A separate order must be placed for parts of a specific package type temperature range and speed grade Data Memory Interface T he data memory address DM A bus is 14 bits wide T he bidi rectional external data bus is 24 bits wide with the upper 16 bits D 8 D 23 used for data memory data D M D transfers T he data memory select DMS signal indicates access to the data memory and can be used as a chip select signal T he write WR signal indicates a write operation and can be used as a write strobe T he read RD signal indicates a read operation and can be used as a read strobe or output enable signal The AD SP 217x supports memory mapped 1 0 with the pe ripherals memory mapped into the data or program memory ad dress spaces and accessed by the processor in the same manner Data Memory Map The on chip data memory RAM resides in the 2K words of data memory beginning at address 0x3000 as shown in Figure 6 In addition data memory locations from 0x3800 to the end of data memory at Ox3FFF are reserved Control r
60. lell Interrupt Priority amp Interrupt Vector Addresses Interrupt Vector Source of Interrupt Address Hex Reset or Power U p with 1 0000 Highest Priority Powerdown N onmaskable 002C IRQ2 0004 HIP Write 0008 HIP Read 000C SPORT 0 ransmit 0010 SPORT 0 Receive 0014 Software Interrupt 1 0018 Software Interrupt 0 001C SPORT 1 T ransmit or IRQ1 0020 SPORT 1 Receive or IRQO 0024 Timer 0028 Lowest Priority On chip stacks preserve the processor status and are automati cally maintained during interrupt handling T he stacks are twelve levels deep to allow interrupt nesting T he following instructions allow global enable or disable servic ing of the interrupts including powerdown regardless of the state of IM ASK Disabling the interrupts does not affect autobuffering INTS DIS 5 When you reset the processor the interrupt servicing is enabled IMASK 8 7 6 5 4 3 2 IRQO Sensitivity IRQ2 Timer itivi 1 edge HIP Write IRQO or SPORT1 Receive IRQ1 Sensitivity 0 level 1802 Sensitivity z SPORNI Transmit ransmi oftware Interrupt Nesting 1 enable 0 disable 15 14 13 12 11 10 9 8 INTERRUPT FORCE IRQ2 SPORTO Transmit SPORTO Receive Software 1 Software 0 SPORT1 Transmit or IRQ1 SPORT1 Receive or IRQO Timer SPORTO Receive IFC 7 Software 1 6 5 4 3 2 INTERRUPT CLEAR Timer
61. p the clock continues to run and does not require stabilization time T he power up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid Vpp is ap plied to the processor and for the internal phase locked loop PLL to lock onto the specific crystal frequency A minimum of 2000 CLKIN cycles ensures that the PLL has locked but does not include the crystal oscillator start up time D uring this power up sequence the RESET signal should be held low On any subsequent resets the RESET signal must meet the mini mum pulse width specification ta sp The RESET input contains some hysteresis however if you use an RC circuit to generate your RESET signal the use of an ex ternal Schmidt trigger is recommended T he master reset sets all internal stack pointers to the empty stack condition masks all interrupts and clears the M STAT reg ister When RESET is released if there is no pending bus re quest and the chip is configured for booting M M AP 0 the boot loading sequence is performed T hen the first instruction is fetched from internal program memory location 0x0000 ADSP 2171 ADSP 2172 ADSP 2173 Program Memory Interface The on chip program memory address bus PM A and the on chip program memory data bus PM D are multiplexed with on chip DM A and DMD buses creating a single external data bus and a single external address bus T he 14 bit address bus directly
62. p sequence is complete Internal phase lock loop requires more than 2000 cycles assuming stable not including crystal oscillator start up time CLKIN CLKOUT Figure 24 Clock Signals REV A 33 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2173 Parameter Min Max Unit Interrupts and Flags T iming Requirement IRQx or FI Setup before CLKOUT Low 2 3 0 25tck 23 ns ru IRQx or FI Hold after CLKOUT High 2 3 0 25tc ns Switching Characteristic tron Flag Output Hold after CLK OUT 0 5 10 ns trop Flag Output D elay from CLK OUT 0 5 5 ns NOTES Nf IRQx and FI inputs meet tics and setup hold requirements they will be recognized during the current clock cycle otherwise the signals will be recognized on the following cycle Refer to Interrupt Controller Operation in the Program Control chapter of the U ser s M anual for further information on interrupt servicing dge sensitive interrupts require pulse widths greater than 10 ns level sensitive interrupts must be held low until serviced 3IRQx IRQO IRQI and IRQ2 Flag Output FLO FL1 FL2 and FO CLKOUT FLAG OUTPUTS IRQx FI Figure 25 Interrupts and Flags 34 REV A ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2173 Parameter Min Max Unit Bus Request Grant Timing Requirement ten BR Hold after CLK OUT High 0 25tck 2
63. parameters for your convenience Common Parameter Memory Device Name Function Specification Name tasw A0 A13 DMS PMS Address Setup to Setup before WR L ow Write Start taw A0 A13 DMS PMS Setup Address Setup before WR D easserted to Write End twra 0 13 DMS PMS Address H old T ime Hold after WR D easserted tow D ata Setup before WR High D ata Setup Time toy Data Hold after WR High DataHold Time trop RD Low to Data Valid OE to D ata Valid 0 13 DMS PMS Address Access T ime BMS to Data Valid 232 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2173 Parameter Min Unit Clock Signals is defined as 0 5 The ADSP 2173 uses an input clock with a frequency equal to half the instruction rate a 10 0 M Hz input clock which is equivalent to 100 ns yields a 50 ns processor cycle equivalent to 20 M Hz tex values within the range of 0 5 tex period should be substituted for all relevant timing parameters to obtain specification value Example 0 5tck 10 ns 0 5 50 ns 10 ns 15 ns Timing Requirement CLKIN Period CLKIN Width Low Switching Characteristic teki CLKOUT Width Low teru CLKOUT Width High CLKIN High to CLKOUT High Control Signals Timing Requirement tasp RESET Width Low 0 5 10 0 5 10 0 160 25 5 5 5 5 5 5 5 pplies after power u
64. r continues to receive and transmit data through the two serial ports receive and or transmit data through the host interface port decrement timer Analog Devices Inc 1995 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 Fax 617 326 8703 ADSP 2171 ADSP 2172 ADSP 2173 Development System The AD SP 2100 F amily D evelopment Software a complete set of tools for software and hardware system development supports the ADSP 217x T he System Builder provides a high level method for defining the architecture of systems under develop ment T he Assembler has an algebraic syntax that is easy to program and debug T he Linker combines object files into an executable file T he Simulator provides an interactive instruction level simulation with a reconfigurable user interface to display different portions of the hardware environment A PROM Splitter generates PROM programmer compatible files TheC Compiler based on the F ree Software F oundation s GNU C Compiler generates AD SP 217x assembly source code The Runtime Library includes over 100 AN SI standard mathematical and D SP specific functions EZ T ools low cost easy to use hardware tools also support the ADSP 217x TheADSP 217x EZ ICE Emulator aids in the hardware de bugging of AD SP 217x systems T he emulator consists of hard ware host computer resident software the emulator probe and the pin adaptor T he emulator perfo
65. rent reflects device operating with no output loads 1 0 4 V and 2 4 V For typical figures for supply currents refer to Power Dissipation section PSee Chapter 9 of the ADSP 2100 F amily U ser s M anual for details PApplies to T QFP and PQFP package types utput pin capacitance is the capacitive load for any three state output pin Specifications subject to change without notice REV A 17 ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2171 ADSP 2172 ABSOLUTE MAXIMUM RATINGS Supply 0 3 V to 7 V Input Voltage 0 3 V to Vpp 0 3 V Output Voltage Swing 0 3 V to Vpp 0 3 Operating T emperature Range Ambient 40 to 85 C Storage T emperatureRange 65 C to 150 C Lead Temperature 5 TQFP 280 C Lead Temperature 5 sec 280 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device T hese are stress ratings only and functional operation of the device these or any other conditions above thoseindicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD SENSITIVITY The ADSP 217x is an ESD electrostatic discharge sensitive device Electrostatic charges readily accumulate
66. rms a full range of emula tion functions including stand alone operation or operation in the target setting up to 20 breakpoints single step or full speed operation in the target examining and altering registers and memory values and PC upload download functions If you plan to use the emulator you should consider the emulator s restric tions differences between emulator and processor operation The EZ LAB Evaluation Board is a PC plug in card but it can operate in stand alone mode T he evaluation board system de velopment board executes EPROM based or downloaded pro grams M odular Analog F ront End daughter cards with different codecs will be made available EZ ICE and EZ LAB are registered trademarks of Analog D evices Inc DATA ADDRESS GENERATOR 1 DATA ADDRESS GENERATOR 2 PROGRAM SEQUENCER Additional Information T his data sheet provides a general overview of ADSP 217x functionality For additional information on the architecture and instruction set of the processor refer to the ADSP 2100 F amily U se s M anual For more information about the D evelopment System and AD SP 217x programmer s reference information refer to the ADSP 2100 Family A ssembler Tools amp Simulator M anual ARCHITECTURE OVERVIEW Figure 1 is an overall block diagram of the ADSP 217x T he processor contains three independent computational units the ALU the multiplier accumulator M AC an
67. ro cessor you must 1 Complete the following forms contained in theADSP ROM Ordering P ackage available from your Analog D evices sales representative ADSP 2172 ROM Specification Form ROM Release Agreement ROM NRE Agreement amp M inimum Quantity Order M QO Acceptance Agreement for Pre production ROM Products 2 Return the forms to Analog D evices along with two copies of the M emory I mage File EXE file of your ROM code T he files must be supplied on two 3 5 or 5 25 floppy disks for IBM PC DOS 2 01 or higher 3 Place a purchase order with Analog D evices for nonrecurring engineering charges N RE associated with ROM product development After this information is received it is entered into Analog Devices ROM M anager System which assigns a custom ROM model number to the product T his model number will be branded on all prototype and production units manufactured to these specifications To minimize the risk of code being altered during this process Analog D evices verifies that the EXE files on both floppy disks are identical and recalculates the checksums for the EXE file en tered into the ROM M anager System T he checksum data in the form of a ROM memory map a hard copy of the EXE file and a ROM Data Verification Form are returned to you for inspection A signed ROM Verification F orm and a purchase order for pro duction units are required prior to any product being manufac tured Prototype un
68. still be used in this configuration ADSP 2171 ADSP 2172 ADSP 2173 Pin Description The ADSP 217x is available in 128 lead T QF P and 128 lead PQFP packages T able contains the pin descriptions Tablel ADSP 217x Pin List Pin of Input Name Pins Output Function Address 14 0 Address output for program data and boot memory spaces Data 24 110 Datal O pins for program and data memories Input only for boot memory space with two M SBs used as boot space addresses RESET 1 Processor reset input IRQ2 1 External interrupt request 2 BR 1 External bus request input BG 1 0 External bus grant output BGH 1 0 External bus grant hang output PMS 1 0 External program memory select DMS 1 0 External data memory select BMS 1 0 Boot memory select RD 1 0 External memory read enable WR 1 0 External memory write enable MM AP 1 select CLKIN XTAL 2 External clock or quartz crystal input CLKOUT 1 0 Processor clock output HSEL 1 HIP select input HACK 1 0 HIP acknowledge output HSIZE 1 8 16 bit host select input 0 16 bit 1 8 bit BMODE 1 Boot mode select input 0 EPROM data bus 1 HIP HMDO 1 Bus strobe select input 0 RD WR 1 DS HMD1 1 HIP address data mode select input 0 separate 1 multiplexed HRD HRW 1 HIP read strobe read write select input HWR HDS 1 HIP write strobe host data strobe select input HD15 0 HAD 15 0 16 1 0 HIP data da
69. ta and address 2 1 ost address 2 Address latch enable input H A1 0 U nused 2 H ost addresses 1 and 0 inputs SPORT 0 5 1 0 Serial port 01 0 pins TFSO RFSO DRO 5 SPORT 1 5 10 or Serial port 11 0 pins IRQ TFS1 1 External interrupt request 1 IRQO RFS1 1 External interrupt request 0 SCLK1 1 0 Programmable clock output FO DT 1 1 0 Flag Output pin FI DR1 1 Flag Input pin FL2 0 3 0 General purpose output pins Vpp 6 Power supply pins GND 11 Ground pins PWD 1 Powerdown pin PWDACK 1 0 Powerdown acknowledge pin Host Interface Port The ADSP 217x host interface port is a parallel 1 0 port that al lows for an easy connection to a host processor T hrough the HIP the ADSP 217x can be used as a memory mapped periph eral to a host computer T he HIP can be thought of as an area of dual ported memory or mailbox registers that allow commu nication between the computational core of the AD SP 217x and the host computer The HIP is completely asynchronous T he host processor can write data into the HIP while the AD SP 217x is operating at full speed T heHIP can be configured with the following pins configures H IP for 8 bit or 16 bit communication with the host processor BM ODE when MM AP 0 determines whether the AD SP 217x boots from the host processor through the HIP or ex ternal EPROM through the data bus HM DO config
70. th another device Switching characteristics tell you what the device will do under a given circumstance Also use the switching characteristics to ensure any timing requirement of a device connected to the processor such as memory is satisfied 18 ADSP 2171 ADSP 2172 MEMORY REQUIREMENTS T his chart links common memory device specification names and ADSP 2171 AD SP 2172 timing parameters for your convenience Common Parameter Memory Device Name Function Specification Name tasw A0 A13 DMS PMS Address Setup to Setup before WR L ow Write Start taw A0 A13 DMS PMS Setup Address Setup before WR D easserted to Write End A0 A13 DMS PMS Address H old Time H old after WR D easserted tow D ata Setup before WR High Data Setup Time tou Data Hold after WR High Data Hold Time trop RD Low to Data Valid OE to D ata Valid 0 13 DMS PMS Address Access T ime BMS to Data Valid REV A ADSP 2171 ADSP 2172 ADSP 2173 ADSP 2171 ADSP 2172 Parameter Min Max Unit Clock Signals is defined as 0 5 The AD SP 2171 AD SP 2172 uses an input clock with a frequency equal to half the instruction rate a clock which is equivalent to 60 ns yields a 30 ns processor cycle 16 67 MHz input equivalent to 33 M Hz tex values within the range of 0 5 period should be substituted for all relevant timing parameters to obtain specification value Example 0 5 7 ns 0 5 30 ns 7 ns
71. ures the bus strobes as separate read and write strobes or a single read write select and a host data strobe e HM D1 selects separate address 3 bit and data 16 bit buses or a multiplexed 16 bit address data bus with address latch enable T ying these pins to appropriate values configures the AD SP 217x for straight wire interface to a variety of industry standard microprocessors and microcomputers In 8 bit reads the AD SP 217x three states the upper eight bits of the bus When the host processor writes an 8 bit value to the HIP the upper eight bits are all zeros F or additional informa tion refer to the ADSP 2100 Family U ser s M anual HIP Operation T heHIP contains six data registers H DR5 0 and two status registers SR 7 6 with an associated HM ASK register for masking interrupts from individual HIP data registers All HIP data registers are memory mapped into the internal data memory of the AD SP 217x HIP transfers can be managed us ing either interrupts or a polling scheme T hese registers are shown in the section 5 217 Registers TheHIP allows a software reset to be performed by the host processor T he internal software reset signal is asserted for five AD SP 217x processor cycles REV A ADSP 2171 ADSP 2172 ADSP 2173 Interrupts interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead The AD SP 217x provides up to thre
72. y waits 4096 CLKIN cycles for the crystal oscillator to start and stabilize and let ting the oscillator run to allow 100 CLKIN cycle startup Powerdown is initiated by either the powerdown pin PWD or the software powerdown force bit Interrupt support allows an unlimited number of instructions to be executed before optionally powering down T he powerdown interrupt also can be used as a non maskable edge sensitive interrupt Context clear save control allows the processor to continue where it left off or start with a clean context when leaving the powerdown state e The RESET pin also can be used to terminate powerdown and the host software reset feature can be used to terminate powerdown under certain conditions Powerdown acknowledge pin indicates when the processor has entered powerdown Idle When the AD 5 217 the Idle M ode the processor waits indefinitely in a low power state until an interrupt occurs When an unmasked interrupt occurs it is serviced execution then continues with the instruction following the IDLE instruction Slow Idle TheIDLE instruction is enhanced on the ADSP 217x to let the processor s internal clock signal be slowed during IDLE further reducing power consumption T he reduced clock frequency a programmable fraction of the normal clock rate is specified by a selectable divisor given in the IDLE instruction T he format of the instruction is IDLE n where n 16 3

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