User Manual - Sundance Multiprocessor Technology Ltd.
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1. 1 12 2 jz 3 z za 13 2 1 E uh a 1 mimm E 9 E zz o Version 2 2 Page 25 of 27 SMT363XC2 User Manual Operating Conditions Safety The module presents no hazard to the user EMC The module is designed to operate within an enclosed host system that provides adequate EMC shielding Operation within the EU EMC guidelines is only guaranteed when the module is installed within an appropriate host system The module is protected from damage by fast voltage transients introduced along output cables from outside the host system Short circuiting any output to ground does not cause the host PC system to lock up or reboot General Requirements The module must be fixed to a TIM40 compliant carrier board The SMT363XC2 TIM is in a range of modules that must be supplied with a 3 3V power source In addition to the 5V supply specified in the TIM specification these new generation modules require an additional 3 3V supply to be presented on the two diagonally opposite TIM mounting holes The lack of this 3 3V power supply should not damage the module although it will obviously be inoperable prolonged operation under these circumstances is not recommended The SMT363XC2 is compatible with2. interrupt The firmware can generate pulses on the external interrupt lines of the TIM Only the interrupt line IIOF1 and 2 are connected from to the DSP and the HOST e is connected from the DSP side to the HOST side so the DSP interrupts the HOST is connected from the HOST side to the DSP side so the HOST interrupts the DSP The IIOF interrupt lines are described in the SMT6400 help file Version 2 2 Page 18 of 27 SMT363XC2 User Manual Code Composer This module is fully compatible with the Code Composer Studio debug and development environment This extends to both the software and JTAG debugging hardware The driver to use is the tixds6x1x_11 dvr CCS version 3 0 or later is required as the reprogramming utility SMT6001 requires it a Troubleshooting Our Knowledge data base and FAQ sections may help you to resolve some known issues Application Development Depending on the complexity of your application you can develop code for SMT363XC2 modules in several ways SMT6400 For simple applications the Sundance SMT6400 software support package project examples and its associated header files SmtTim h and ModSup h can suffice The SMT6400 product is installed by the Sundance Wizard and it is free of charge SMT6060 SMT6060 FTP is a utility that allows and easy and cost effective integration of the Net 50 ARM chip and the DSP that can be found on SMT363 It is ready to use and prov
3. m oo 20 SHB e t 20 J rmper 2 JP1 NET 50 connections 21 JP2 Serial port header rice irren et cot inen een rt rone Es 21 Xilinx CPLD programming port 22 JPA 22 LED DescripliOPiS dt tend EA dut fune 23 Mechanical Configuration iae dad od dal cd ad od lod ad da otf 24 Operating GOnditions MT 25 jp 25 esc ER PEE 25 General Requirements 25 POWEr CONSUMPHOM 25 MD 26 Version 2 2 Page 5 of 27 SMT363XC2 User Manual Contacting Sundance You can contact Sundance for additional information by login onto the Sundance support forum Please note that first users have to register first Version 2 2 Page 6 of 27 SMT363XC2 User Manual Notational Conventions DSP The terms DSP C6713 and TMS320C6713 will be used interchangeably throughout this document SDB The term SDB will be used throughout this document to refer to the Sundance Digital Bus interface SHB The term SHB will be used throughout this document to refer to the Sundance High speed Bus interface Register Descriptions The format of
4. 0xB0080000 0xB0088000 0xB0090000 00 0000 0xB00C8000 0 00 0000 OxBOOE0000 OxBOOE4000 OxBOOE8000 OxBOOECO00 OxBOOFO000 OxBOOf4000 OxBOOF8000 OxBOOfc000 Version 2 2 Page 20 of 27 SMT363XC2 User Manual SHB pinout SHB generic pin out QSH Pin number QSH Pin number USERDEFO USERDEF1 USERDEF2 USERDEF3 USERDEFO USERDEF1 USERDEF2 USERDEF3 Note Hw is a short for Half word i e 16 bit Word Version 2 2 Page 21 of 27 SMT363XC2 User Manual Jumper Pin Outs JP1 50 connections 1 11 SPI CLK SPE EN 2 12 SPI RX SPI TX 3 13 RXD TXD 4 14 RTS CTS 5 15 DTR DCD 6 16 DSR RI 7 17 V33 GND 8 18 FA6 FA78 9 19 FA3 FA45 10 20 FA1 FA2 JP2 Serial port header 2 4 6 8 10 12 14 16 FSX1 FSR1 DX1 DR1 CLKX1 CLKR1 CLKS1 GND 5 2 FSR2 DX2 DR2 CLKX2 CLKR2 CLKS2 GND 1 3 5 7 9 11 13 15 Refer to the DSP s Peripheral Reference Guide for signal description and usage Version 2 2 22 of 27 JP3 Xilinx CPLD programming port 1 2 V33 TCK 3 4 GND TMS 5 6 TDO TDI JP4 port 1 2 TCLK TRST NC 3 4 TMS NC 5 6 TDI V33 7 8 TDO GND Typically TRST is not
5. controlled with the LED register Writing 1 will illuminate the LED writing O will turn it off LED Register 0 80000000 31 4 3 2 1 0 _ LED LED D3 D2 RW 0 RW 1 RW 0 RW 0 Despite LED register bit 2 is writable user should not change the value of this bit When SMT363XC2 embeds 16MB of SDRAM the DSP is configured to access SDRAM with 8 column address bits and 12 row address bits whereas when SMT363XC2 embeds 64MB SDRAM it s configured with 10 column address bits and 13 row address bits EMIF SDRAM Control register It results that FPGA s is moved in the DSP s memory space Writing a value to this bit changes the way the FPGA decodes the address and therefore it s location in the EMIF memory space This bit should be set to 1 when 64MB of SDRAM are fitted on board otherwise it should be set to 0 when 16MB of SDRAM are fitted on board Version 2 2 Page 15 of 27 SMT363XC2 User Manual CONFIG amp NMI The TIM specification describes the operation of an open collector type signal CONFIG that is driven low after reset This signal on a standard C4x based TIM is connected to the processor s IIOF3 pin On the SMT365 the CONFIG signal is asserted after power on and can be released by writing the value 1 6 to the config register Conversely CONFIG may be re asserted by writing O to this bit It is not possible for software to read the state of the CONFIG signal The NMI s
6. developed especially for high bandwidth applications in Intelligent Networked Devices Based on architecture it integrates 10 100Base T Ethernet MAC with an MII interface a distributed 10 channel linking DMA controller and a memory controller supporting all of the popular memory devices in use today This device is connected directly to an Intel LXT971 PHY device which provides an IEEE 802 3 compatible 10Base T and 100Base T physical layer interface Also directly connected to the 50 are 16Mbytes of SDRAM an RS232 level converter and a 128KB Dual Port RAM DPRAM LEDs 4 and 4 are controlled via PORTA bits 0 and 1 DSP The Texas Instruments DSP can run at up to 225MHz The DSP is doted of 16MB optional 64MB of SDRAM DSP is TMS320C6713 type An on board 37 5MHz crystal oscillator provides the clock used for the DSP which then multiplies this by for input to the DSP DSP internally multiplies this up to the required frequency using a PLL Boot Mode The DSP is connected to the on board flash ROM that contains the Sundance bootloader and the FPGA bitstream Following reset the DSP will automatically load the data from the flash ROM into its internal program memory at address 0 and then start executing from there All this code is the Sundance bootloader and it is made up of three parts FPGA configuration processor configuration and the Comport boot procedure FPGA configuration uses data in the ROM t
7. 5 1363 2 User Manual UKAS QUALITY MANAGEMENT Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 Version 2 2 Page 2 of 27 SMT363XC2 User Manual Revision History Date Comments Version 14 11 03 First release 1 0 0 02 12 03 Added addressing mode section LED Setting 1 0 1 Updated ComPort section 20 10 04 Updated block diagram 0 Removed endianess section Updated LED section Replaced Timer and interrupt section by Interrupt section Version 2 2 3 of 27 SMT363XC2 User Manual Table of Contents REVISION FAIGIONY cesna E E E 2 Table of 3 Contacting SUndan e 5 suce 6 82 ORE TEE AUTEUR 6 en 6 SHB 6 Register Biens rte 6 Outline Description E 7 Intended cll p Mp 7 5101A BITE Lo Ee a a 8 Architecture SSC MOM uiae nen 9 ee ete ne E E ene ee ee nee HO 9 DSP 9 Boot Mode tee eee eee ene ee ee error 9 DPRA M cei EE MS MI MP MEE ME 10 EMIF Control 10 CE1 I0 Control 11 SDR
8. AM 11 PPS 11 toe v 12 Senal DOS ana etes atado abe epit aia cobi aedes QE a E a 12 _____________6___ 12 VETSION COMO MER UM E 12 Firmware versions ios 12 Reprogramming the firmware and boot 6006 12 COMPOS a over rv vas vas Cees ep r PA Fr ERE EXE 13 SHB 13 Pear qp P ro 13 Global DUS EEE EE 13 Version 2 2 Page 4 of 27 SMT363XC2 User Manual T E 14 LED 14 CONFIG S utente enit 15 Register 15 16 Timer Control resection oe oi oet m LIU LA atc ea s 16 x ie mud mad Gut Exc Un Ro US DuC CE PUO DUI DU DUELO eee 17 Code Compose 18 18 SIN 18 SM TOO Oaea ra cd ade edu cete Ga 18 Sk Diamond 18 18 FPGA Memory 19 SHB
9. SPECIFICATION Including TMS320C44 Addendum 7 SDB Technical Specification 8 SHB Technical Specification 9 TMS320C4x User s Guide literature number SPRUOG3 It describes the 4 32 bit floating point processor developed for digital signal processing as well as parallel processing applications Covered are its architecture internal register structure instruction set pipeline specifications and operation of its six DMA channels and six communication ports Software and hardware applications are included 10 Xilinx Virtex Il datasheet 11 TMSC6713 datasheet UKAS QUALITY MANAGEMENT Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 Version 2 2 INDEX A Application Development 18 B Bibliography 26 C Code Composer 18 CONFIG amp NMI 15 Contacting Sundance 5 E email address 5 F Firmware versions 12 I IIOF lines 17 L LEDs 14 FPGA DONE 14 LED register 14 Page 27 of 27 SMT363XC2 User Manual M memory space to CE3 10 N Notational Conventions 6 0 Operating Conditions 25 P Power consumption 25 R Register Descriptions 6 S SDB 13 SHB pinout 20 SMT6400 18 SMT6500 18 T Timer 16 V Version Control 12
10. all Sundance TIM carrier boards It is 5V tolerant module and as such it may be used in mixed systems with older TIM modules carrier boards and I O modules Use of the TIM on SMT327 cPCI motherboards may require a firmware upgrade If LED D6 on the SMT363XC2 remains illuminated once the TIM is plugged in and powered up the SMT327 needs the upgrade The latest firmware is supplied with all new boards shipped Please contact Sundance directly if you have an older board and need the upgrade The external ambient temperature must remain between 0 C 40 C and the relative humidity must not exceed 95 non condensing Power Consumption The power consumption of this TIM is dependent on the operating conditions in terms of core activity and activity The SMT363XC2 module consumes about 3 18 Watts Bibliography 1 Sundance Help file 2 SMT6400 help file DSP support package and SMT6500 help FPGA support package 3 SMT6060 user manual Ethernet support package 4 50 Microprocessor 5 TMS320C6000 Peripherals Reference Guide literature number SPRU190 It describes common peripherals available on the TMS320C6000 digital signal processors This book includes information on the internal data and program memories the external memory interface EMIF the host port multichannel buffered serial ports direct memory access DMA clocking and phase locked loop PLL and the power down modes 6 TIM 40 MODULE
11. are version 1 0 and version 1 1 are described in the section Firmware versions Version 2 2 Page 8 of 27 SMT363XC2 User Manual Block Diagram The following drawing shows the block diagram of the SMT363XC2 module The main components of the SMT363XC2 are A Texas Instruments DSP One Xilinx Virtex Il FPGA One NetSilicon ARM Net 50 device with integrated MAC controller for connection to an Ethernet network 16 64MB of SDRAM DSP and J1 Top Primary TIM FPGA PSU Connector Comm Port 3 8M bytes Flash el a 0 5 lt 5 to 95 lt 16 64M bytes 5a 20 SDRAM o E 2 x 4 16M x 16 4 amp 32 bit EMIF C6211 6711 6713 McBSP GPIO LEDs Xilinx FPGA JTAG Header Virtex ll 1 5V Sundance High speed Dual Port RJ45 RS232 Bus RAM 1850 LEDs 60 way Samtec EN a 16M bytes SDRAM 50 2 x AM x 16 E o x 42 Bottom Primary Connector 1 2 4 J3 Global Expansion Connector Figure 1 SMT363XC2 block diagram Version 2 2 Page 9 of 27 SMT363XC2 User Manual Architecture Description 50 The 50 is a cost effective high performance 32 bit network attached microprocessor
12. connected to the 50 SMT363XC2 User Manual Version 2 2 Page 23 of 27 SMT363XC2 User Manual LED Descriptions LED Connection Function 1 FPGA DONE Shows the state of the FPGA s configuration If this LED is ON then the FPGA is NOT configured This LED should power up in the ON state and extinguish after a second 2 FPGA LEDO Controlled by the LED register DSP Heartbeat SMT6060 TCPIP rpcproxy tsk FPGA LED1 Controlled by the LED register 4 NET50 PORTAO Controlled by PORTA bit 0 of the NET 50 Net 50 Heartbeat SMT6060 TCPIP netsocksvr vOp5p7 dat NET50 PORTA1 Controlled by PORTA bit 1 of the 50 PHY LED3 Link receive status ON receiving OFF not receiving 7 PHY LED2 NET50 PORTCE6 Link up status ON connected OFF disconnected 8 PHY LED1 Link speed status ON 100Mbit OFF 10Mbit Version 2 2 Page 24 of 27 SMT363XC2 User Manual Mechanical Configuration Serial Ports 8Mbyte Flash DSP s 64Mbyte SDRAM SHB Connector gunt Xilinx JTAG NET 50 JTAG 71 DPRAM Ethernet PHY z JI PLI a ER X jm SMT363XC2VI 50 RS232 SPl Ethernet Ethernet Magnetic NET 50 16Mbyte SDRAM
13. d 0 to 5 The addresses of the Comport registers are shown in the Error Reference source not found and are described in the SMT6400 help file SHB The SMT363XC2 provides one SHB connector which is connected to the DSP to give two 16 bit SDB interfaces These interfaces operate with a fixed clock rate of 100MHz Architecture SDBO and SDB1 on the DSP are presented on the TIM s SHB connector SDBA and SDBB respectively SDBB SDBA The addresses of the SDB registers are shown in the Virtex Memory Map and are described in the SMT6400 help file Global bus The SMT363XC2 provides a single global bus interface This is only accessible from the DSP The addresses of the global bus registers are shown in the Virtex Memory Map and are described in the SMT6400 help file Version 2 2 Page 14 of 27 SMT363XC2 User Manual LED Setting The SMT363XC2 has 8 LEDs LED D1 always displays the state of the FPGA DONE pin This LED is off when the FPGA is configured DONE 1 and on when it is not configured DONE 0 This LED should go on when the board is first powered up and go off when the FPGA has been successfully programmed this is the standard operation of the boot code resident in the flash memory device If the LED does not light at power on check that you have the mounting pillars and screws fitted properly If it stays on the DSP is not booting correctly or is set to boot in a non standard way Two of the LEDs D2 3 can be
14. e Array is a Xilinx Virtex ll XC2V1000 device It implements the following communication resources e Six comport interfaces Two 16 bit Sundance Digital Bus interfaces e One global bus interface Version control Revision numbers for both the boot code and FPGA firmware are stored in the Flash ROM during programming as zero terminated ASCII strings The SMT6001 utility can be used to display the version numbers of the bootloader and the FPGA data Firmware versions The SMT6001 utility includes the latest version of the bootloader and the latest version of the FPGA data that implements the FPGA architecture described in the SMT6500 help file Note that the new firmware supports two more comports Customers who wish to use the old firmware that supported only 4 comports options can obtain it from our support web forum Reprogramming the firmware and boot code The contents of the flash ROM are managed using the 5 6001 utility This includes the latest firmware and bootloader along with complete documentation on how to reprogram the ROM The utility assumes that you have Code Composer Studio installed and that it has been configured correctly for the installed TIMs The Sundance Wizard can help you with this To confirm that the ROM has been programmed correctly you should run the confidence test in the Boardlnfo utility SMT6300 Version 2 2 Page 13 of 27 SMT363XC2 User Manual Comports The DSP has 6 comports numbere
15. enerates pulse on CCLK 1 1 0 N DPRAM semaphore enable when N 1 SDRAM Memory space CEO is used to access 16MB or optional 64MB of SDRAM over the EMIF The speed of the SDRAM is dependent on the processor variant Using the C6713 the SDRAM will operate at 100MHz Using the C6713 the SDRAM operates at a programmable rate up to the maximum allowed on the EMIF The EMIF CEO memory space control register should be programmed with the value 0x00000030 FLASH An 8MB Flash ROM is connected to the DSP in the EMIF CE1 memory space The ROM holds boot code for the DSP configuration data for the FPGA the boot code for the Net 50 chip and optional user defined code A software protection algorithm is in place to prevent programs accidentally altering the ROM s contents Please contact Sundance for further information about re programming this device The CE1 memory space control register should be programmed with the value OxFFFFFF23 Version 2 2 Page 12 of 27 SMT363XC2 User Manual RS232 A single RS 232 channel is provided at true RS232 levels The signals provided are TBD and are presented on wire wrap posts Serial ports The DSP provides two serial ports which are connected to a pin header on the SMT363XC2 module Additionally some of the serial port signals are connected to the Virtex2 FPGA in order to provide extra signals which can be used for external interrupts FPGA The FPGA Field Programmable Gat
16. ide a TCI IP interface to a host SMT6060 TCPIP is a software package that provides Ethernet connectivity via the industry standard Berkeley sockets interface to a 3L Diamond network of DSP processors The package is typically used when there is at least one SMT363 present in the system however using a feature of the SMT6025 software package it also provides seamless connectivity via the HOST PC s Winsock 2 2 Ethernet hardware The software is ready to use and provides sockets connectivity to any Sundance DSP processor 3L Diamond This module is fully supported by 3L Diamond which Sundance recommends for all but the simplest of applications An SMT363XC2 has to be declared as appropriate in configuration files as one processors of type e SMT363XC2 1 16MB SDRAM SMT363XC2 2 64MB SDRAM SMT6500 This is the support package for the FPGA It may be used to develop your application in the FPGA of the module Version 2 2 Page 19 of 27 FPGA Memory Map volatile unsigned SMT363CP0 volatile unsigned SMT363CP1 volatile unsigned SMT363CP2 volatile unsigned SMT363CP3 volatile unsigned SMT363CP4 volatile unsigned SMT363CP5 volatile unsigned SMT363CPO STAT volatile unsigned SMT363CP1 STAT volatile unsigned SMT363CP2 STAT volatile unsigned SMT363CP3 STAT volatile unsigned SMT363CP4 STAT volatile unsigned SMT363CP5 STAT volatile unsigned SMT363STAT volatile unsig
17. ignal from the TIM connector can be routed to the DSP NMI pin WARNING Several software components include code sequences that assume setting GIE 0 in the DSP CSR will inhibit all interrupts NMI violates that assumption If an NMI occurs during such code sequences it may not be safe to return from the interrupt This may be particularly significant if you are using the compiler s software pipelining facility Config Register 31 8 6 5 0 CONFIG Field Description 0 drive CONFIG low 1 tri state CONFIG 0 Disconnect NMI from the DSP 1 Connect NMI from TIM to the DSP CONFIG NMI Config and NMI DSP lines are described in the SMT6400 help file Version 2 2 Page 16 of 27 SMT363XC2 User Manual Timer The TCLKO TCLK1 signals can be routed to the DSP s TOUT TINP pins The signal direction must be specified together with the routing information in the timer control register Timer Control Register 31 6 5 4 3 0 Reserved TCLK1 TCLKO Reserved Field Description TCLKO TCLKO is an input 1 Enable TIM TCLKO as an output TCLK1 0 TIM TCLK1 is an input 1 Enable TIM TCLK1 as an output If the TIM TCLKx pin is selected as an output the DSP TOUTx signal will be used to drive it The TIM TCLKx pin will always drive the DSP TINPx input The Timer control register is described in the SMT6400 help file Version 2 2 Page 17 of 27 SMT363XC2 User Manual
18. ned SMT363SDBA volatile unsigned SMT363SDBB volatile unsigned SMT363SDBA STAT volatile unsigned SMT363SDBB STAT volatile unsigned SMT363SDBA FLAG volatile unsigned SMT363SDBB FLAG volatile unsigned GLOBAL BUS volatile unsigned GLOBAL BUS CTRL volatile unsigned GLOBAL BUS START volatile unsigned GLOBAL BUS LENGTH volatile unsigned SMT363TCLK volatile unsigned SMT363TIMCONFIG volatile unsigned SMT363LED volatile unsigned SMT363INTCTRL4 volatile unsigned SMT363INTCTRL4 EXT volatile unsigned SMT363INTCTRL5 volatile unsigned SMT363INTCTRL4 EXT volatile unsigned SMT363INTCTRL6 volatile unsigned SMT363INTCTRL4 EXT volatile unsigned SMT363INTCTRL7 volatile unsigned SMT363INTCTRL4 EXT nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned nsigned SMT363XC2 User Manual 0xB0000000 0xB0008000 0xB0010000 0xB0018000 0xB0020000 0xB0028000 0 0004 000 0 000 000 OxB0014 000 0OxB001C000 0 0024 000 0 002 000 0xB003C000 0xB0040000 0xB0050000 0xB0048000 0xB0058000 0 004 000 0 005 000 OxBOOA0000
19. o configure the FPGA A processor configuration sets the processor into a standard state copies its comport boot procedure into a dual port RAM DPRAM implemented in the FPGA and releases the 50 chip from reset The Net 50 chip is configured to boot from this DPRAM The bootloader is executed It will continually check the six comports until data appears on one of them This will next load a program in boot format from this comport Note that the bootloader will not read data arriving on other comports Finally the control is passed to the loaded DSP application It is safest to wait for the configuration to complete Note that comports will appear to be not ready until the FPGA has been configured The FPGA programming algorithm is not described here It can be found in the boot code Version 2 2 Page 10 of 27 SMT363XC2 User Manual DPRAM The DPRAM in the FPGA is only intended to be used during this boot process more general use is not recommended A 128KB memory is directly connected to both the DSP and the 50 devices Each can access the memory independently and at their respective maximum data rates The DPRAM is decoded as the boot ROM in the 50 5 memory space The DPRAM supports the generation of interrupts to either of its ports This functionality is achieved by the DSP writing to a specific DPRAM address which in turn generates an interrupt to the NET 50 PINT2 pin Similarly the NET 50 can write
20. registers is described using diagrams of the following form 31 24 23 16 15 8 7 0 OFLAGLEVEL R 00000000 RW 10000000 R 00000000 R 10000000 The digits at the top of the diagram indicate bit positions within the register and the central section names bits or bit fields The bottom row describes what may be done to the field and its value after reset Shaded fields are reserved and should only ever be written with zeroes R Readable by the CPU Writeable by the CPU RW Readable and writeable by the CPU Binary digits indicate the value of the field after reset Version 2 2 Page 7 of 27 SMT363XC2 User Manual Outline Description The SMT363XC2 is an Ethernet module size 1 TIM offering the following features NetSilicon ARM chip 50 TMS320C6713 processor running at 225MHz Six Comports 64MB of SDRAM 8MB Flash ROM Global Bus connector High bandwidth data I O via 2 Sundance Digital Buses SDB D D 0 D D UD Intended Audience There are two existing versions of the firmware for the SMT363XC2 These two versions differ by the number and the type of communication resources comport and SDB interfaces provided For each of the versions of the different firmware is loaded in the FPGA Firmware version 1 0 or Firmware version 1 1 This user manual covers the version 1 1 of the firmware for the SMT363XC2 implemented with the model described in the SMT6500 help file The changes between the firmw
21. to a specific address which generates an interrupt which can be routed to the DSP EMIF Control Registers The DSP has a single external memory interface EMIF which is 32 bits wide A full description of the registers used to control the EMIF can be found in the DSP C6000 Peripherals Reference GuideError Reference source not found Error Reference source not found The standard bootstrap will initialise these registers to use the following resources Memory space Resource Address range EMIF CEO SDRAM 0x80000000 Ox83FFFFFF CE1 Flash IO Control 0x90000000 0x903FFFFF CE2 DPRAM 0xA0000000 OxA7FFFFFF CE3 Virtex 0xB0000000 OXBOFFFFFF The power on and reset state for the semaphore enable DPRAM related is disabled This bit determines whether the flash or DPRAM semaphore registers are accessed Version 2 2 Page 11 of 27 SMT363XC2 User Manual CE1 IO Control Several I O connections are required to control the NET 50 reset signal upper flash address signals and the control signals for FPGA programming These are all accessed via the CE1 memory space and defined settings for some data lines D31 D30 D29 DO Function 0 0 0 X Flash write 0 0 1 N NET 50 reset control Reset active low N 0 1 0 N Flash address A20 control 20 0 1 1 N Flash address A21 control 21 1 0 0 N FPGA PROG pin control PROG active low N 1 0 1 X FPGA CCLK pin control G
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