AT91 ARM Thumb-based Microcontrollers Application Note
Contents
1. Application Note m 6275E ATARM 18 Dec 07 es caton Note Mw Signal Name Recommended Pin Connection Description ICE and JTAG TCK Pull up 100 kOhm This pin is a Schmitt trigger input No internal pull up resistor TMS Pull up 100 kOhm This pin is a Schmitt trigger input No internal pull up resistor TDI Pull up 100 kOhm This pin is a Schmitt trigger input No internal pull up resistor TDO Floating Output driven at up to Vyppiopo RTCK Floating Output driven at up to Vyppiopo Can be left unconnected NTRST It is strongly recommended to tie this Internal pull up resistor to Vyppiopo 100 kOhm pin to Vppiopo in harsh environments In harsh environments It is strongly JTAGSEL recommended to tie this pin to GNDBU Internal pull down resistor to GNDBU 15 kOhm if not used or to add an external low Must be tied to Vyppgu to enter JTAG Boundary Scan value resistor such as 1 kOhm Reset Test NRST is configured as an output at power up Application dependent NRST Can be connected to a push button for NRST is controlled by the Reset Controller RSTC hardware reset An internal pull up resistor to Vyppiopo 100 kOhm is available for User Reset and External Reset control In harsh environments It is strongly TST recommended to He this pin to GNDBU Internal pull down resistor to GNDBU 15 kOhm if not used or to add an external low value resistor such as 1 kOhm Must be2. 8 Rue Jean Pierre Timbaud BP 309 78054 Saint Quentin en Yvelines Cedex France Tel 33 1 30 60 70 00 Fax 33 1 30 60 71 11 Technical Support AT91SAM Support Atmel techincal support Atmel Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Sales Contacts www atmel com contacts Literature Requests www atmel com literature Disclaimer The information in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to any intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI TIONS OF SALE LOCATED ON ATMEL S WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the co
3. Main Oscillator XOUT can be left unconnected uty yc S i 9 i in Refer to the electrical specifications of the AT91SAM9260 datasheet Bypass Mode AMEL s 6275E ATARM 18 Dec 07 AMEL Signal Name Recommended Pin Connection Description Crystal Load Capacitance to check CoprystaL22 AT91SAM9260 XOUT32 GNDBU XINS2 32 768 kHz Crystal XOUT32 Corystatse Capacitors on XIN32 and XOUT32 Slow Clock f Oscillator crystal load capacitance dependent ae Clexts2 T kil Example for an 32 768 kHz crystal with a load capacitance of CorystaLa2 12 5 pF external capacitors are required C exr32 17pF Refer to the electrical specifications of the AT91SAM9260 datasheet See the Excel spreadsheet ATMEL_PLL_LFT_Filter_CALCULATOR_AT91_xxx zip available in the software files on the Atmel Web site allowing calculation of the best R C1 C2 component values for the PLL Loop Back Filter PLLRC Second order filter Pn g PLL PLLRCA Can be left unconnected if PLL not used R lt C2 Ci GNDPLL R C1 and C2 must be placed as close as possible to the pins Appolicati n debend ent Slow Clock Oscillator Selection Fe is i Must be tied to Vyppgu to select the external 32 768 Hz OSCSEL Please refer to the I O line considerations crystal and errata section of the AT91SAM9260 Must be tied to GNDBU t eee hib RC datasheet ust be tied to mined ect the on chip
4. m 6275E ATARM 18 Dec 07 es caton Note 4 External Bus Interface EBI Hardware Interface Table 4 1 and Table 4 2 detail the connections to be applied between the EBI pins and the external devices for each Memory Controller Table 4 1 EBI Pins and External Static Devices Connections Pins of the Interfaced Device Signa 8 bit Static re 16 bit Static 2 at 32 bit Static EBL Device Devices Device Devices Devices Device Controller MC DO D7 DO D7 DO D7 DO D7 DO D7 DO D7 DO D7 D8 D15 D8 D15 D8 D15 D8 D15 D8 15 D8 15 D16 D23 D16 D23 D16 D23 D16 D23 D24 D31 D24 D31 D24 D31 D24 D31 AO NBSO AO NLB NLB BE0 A1 NWR2 NBS2 A1 AO AO WE NLB BE2 A2 A22 A 2 22 A 1 21 A 1 21 A 0 20 A 0 20 A 0 20 A23 A25 A 23 25 A 22 24 A 22 24 A 21 23 A 21 23 A 21 23 NCSO CS CS CS CS CS CS NCS1 SDCS CS CS CS CS cs CS NCS2 CS CS CS CS CS cs NCS3 NANDCS CS CS CS CS cs CS NCS4 CFCSO CS CS CS CS cs CS NCS5 CFCS1 CS CS CS CS cs cs NRD CFOE OE OE OE OE OE OE NWRO NWE WE WE WE WE WE WE NWR1 NBS1 WE NUB WE NUB BE1 NWR3 NBS3 WE NUB BE3 Notes 1 NWR1 enables upper byte writes NWRO enables lower byte writes 2 NWRx enables corresponding byte x writes x 0 1 2 or 3 3 NBSO and NBS1 enable respectively lower and upper bytes of the lower 16 bit word 4 NBS2 and NBS
5. tied to Vyppiopo to boot on Embedded ROM BMS Application dependent Must be tied to GND to boot on external memory EBI Chip Select 0 Shutdown Wakeup Logic Application dependent A typical application connects the pin This pin is a push pull output SHDN SHDN to the shutdown input of the DC DC SHDN pin is driven low to GNDBU by the Shutdown Converter providing the main power Controller GHDWC supplies This pin is an input only WKUP OV to Vypppu WKUP behavior can be configured through the Shutdown Controller GHDWC 6275E ATARM 18 Dec 07 AMEL AMEL Signal Name Recommended Pin Connection Description PIO All PIOs are pulled up inputs at reset except those which are multiplexed with the Address Bus signals that require to be enabled as peripherals FAX PC4 A23 PC5 A24 and PC10 A25 PBx Application dependent PCx To reduce power consumption if not used the concerned PIO can be configured as an output driven at 0 with internal pull up disabled ADC 2 4V to Vvppana ADVREF is a pure analog input ADVREF Decoupling Filtering capacitors Application dependent To reduce power consumption if ADC is not used connect ADVREF to GNDANA EBI Data Bus DO to D31 Data Bus lines DO to D15 are pulled up inputs to Vyppiom DO D15 at reset D16 D31 Application dependent Note Data Bus lines D16 to D31 are multiplexed with the PIOC controller Their I O line r
6. 3 enable respectively lower and upper bytes of the upper 16 bit word 5 BEx Byte x Enable x 0 1 2 or 3 11 6275E ATARM 18 Dec 07 AMEL AMEL Table 4 2 EBI Pins and External Device Connections Pins of the Interfaced Device CompactFlash Signals SDRAM gti True ibe Mode NAND Flash EBI_ EBI only Controller SDRAMC SMC DO D7 DO D7 DO D7 DO D7 1 00 1 07 D8 D15 D8 D15 D8 15 D8 15 1 08 1 015 D16 D31 D16 D31 AO NBSO DQMO AO AO A1 NWR2 NBS2 DQM2 A1 A1 A2 A10 A 0 8 A 2 10 A 2 10 A11 A9 SDA10 A10 A12 A13 A14 A 11 12 A15 A16 BA0 BAO A17 BA1 BAI A18 A20 A21 7 ALE A22 REG REG CLE A23 A24 m A25 CFRNW CFRNW NCSO NCS1 SDCS cs NCS2 NCS3 NANDCS CE NCS4 CFCSO CFCso CFCso NCS5 CFCS1 cFcs1 CFcs1 NANDOE a RE NANDWE WE NRD CFOE OE NWRO NWE CFWE WE WE NWR1 NBS1 CFIOR DQM1 IOR IOR NWR3 NBS3 CFIOW DQM3 IOW IOW CFCE1 CE1 CS0 CFCE2 CE2 CS1 SDCK CLK 12 Application Note memm 6275E ATARM 18 Dec 07 es caton Note Table 4 2 EBI Pins and External Device Connections Continued Pins of the Interfaced Device mpactFlash Signals SDRAM al a be a NAND Flash EBI_ E
7. AT91SAM9260 Microcontroller Schematic Check List 1 Introduction This application note is a schematic review check list for systems embedding the Atmel ARM Thumb based AT91SAM9260 microcontroller It gives requirements concerning the different pin connections that must be consid ered before starting any new board design and describes the minimum hardware resources required to quickly develop an application with the AT91SAM9260 It does not consider PCB layout constraints It also gives advice regarding low power design constraints to minimize power consumption This application note is not intended to be exhaustive Its objective is to cover as many configurations of use as possible The Check List table has a column reserved for reviewing designers to verify the line item has been checked AIMEL T AT91 ARM Thumb based Microcontrollers Application Note 6275E ATARM 18 Dec 07 2 Associated Documentation Before going further into this application note it is strongly recommended to check the latest AMEL documents for the AT91SAM9260 microcontroller on Atmel s Web site Table 2 1 gives the associated documentation needed to support full understanding of this appli cation note Table 2 1 Associated Documentation Information Document Title User Manual Electrical Mechanical Characteristics Ordering Information Errata AT91SAM9260 Product Datasheet Internal architecture of pr
8. BI ony EBI only Controller SDRAMC SMC SDCKE CKE RAS RAS CAS CAS SDWE WE 7 NWAIT WAIT WAIT m Pxx CD1 or CD2 CD1 or CD2 Pxx CE Pxx RDY Notes 1 Not directly connected to the CompactFlash slot Permits the control of the bidirectional buffer between the EBI data bus and the CompactFlash slot Any PIO line For SDRAM connection examples See Using SDRAM on AT91SAM9 Microcontrollers application note For NAND Flash connection examples See NAND Flash Support in AT91SAM9 Microcontrollers application note 1 08 1 015 bits used only for 16 bit NAND Flash CE connection depends on the NAND Flash For standard NAND Flash devices it must be connected to any free PIO line oak w LP For CE don t care NAND Flash devices it can be connected either to NCS3 NANDCS or to any free PIO line 6275E ATARM 18 Dec 07 AMEL 13 AMEL 5 AT91SAM Boot Program Hardware Constraints See the AT91SAM Boot Program section of the AT91SAM9260 datasheet for more details on the boot program 5 1 AT91SAM Boot Program Supported Crystals and Input Frequencies 5 1 1 On chip RC Selected OSCSEL 0 If the Internal RC Oscillator is used OSCSEL 0 and the Main Oscillator is active Table 5 1 Supported Crystals MHz 3 0 6 0 18 432 Other Crystal Boot on DBGU Yes Yes Yes Yes Boot on USB Yes Yes Yes No Note Any other crystal can be used but i
9. OM VDDIOP VDDIOP1 pins GND Sauna OPO and OP1 pins l GND pins should be connected as shortly as possible to the system ground plane GNDBU pin is provided for VDDBU pin GNDBU Backup Ground GNDBU pin should be connected as shortly as possible to the system ground plane GNDPLL pin is provided for VDDPLL pin GNDPLL PLL and Main Oscillator Ground GNDPLL pin should be connected as shortly as possible to the system ground plane GNDANA pin is provided for VDDANA pin GNDANA Analog Ground GNDANA pin should be connected as shortly as possible to the system ground plane Application Note memm 6275E ATARM 18 Dec 07 es caton Note Mv Signal Name Recommended Pin Connection Description Clock Oscillator and PLL Crystal Load Capacitance to check Ccrystat AT91SAM9260 XOUT GNDPLL Crystals between 3 and 20 MHz XIN XOUT Capacitors on XIN and XOUT M crystal load capacitance dependent Covei f Main Oscillator ice in 1 kOhm resistor on XOUT only required Normal Mode for crystals with frequencies lower than 8 d Pale MHz Crex Crex T I Example for an 18 432 MHz crystal with a load capacitance of CepystaL 17 5 pF external capacitors are required C ey 12 pF Refer to the electrical specifications of the AT91SAM9260 datasheet XIN f XOUT 1 8V Square wave signal VDDPLL External Clock Source up to 50 MHz XIN external clock source Dik Cucle 4010 c0
10. any of these input frequencies SAM BA Boot The SAM BA Boot Assistant supports serial communication via the DBGU or the USB Device Port Table 5 5 Pins Driven during SAM BA Boot Program Execution Peripheral Pin PIO Line DBGU DRXD PB14 DBGU DTXD PB15 DataFlash Boot The DataFlash Boot program searches for a valid application in the SPI DataFlash memory The DataFlash must be connected to NPCSO or NPCS1 of the SPIO Table 5 6 Pins Driven during DataFlash Boot Program Execution Peripheral Pin PIO Line SPIO MOSI PA1 SPIO MISO PAO SPIO SPCK PA2 SPIO NPCSO PA3 SPIO NPCS1 PC11 NAND Flash Boot The NAND Flash Boot program searches for a valid application in the NAND Flash memory Table 5 7 Pins Driven during NAND Flash Boot Program Execution Peripheral Pin PIO Line PIOC PIOC14 for NAND Chip Select PC14 PIOC PIOC13 for NAND Ready Busy PC13 Address Bus NAND CLE A22 Address Bus NAND ALE A21 6275E ATARM 18 Dec 07 AIMEL Revision History Table 5 8 Revision History Change Request Doc Rev Comments Ref 6275A First issue Updated description and schematic for XIN and XOUT pin on page 5 Updated description and schematic for XIN32 and XOUT32 pin on page 6 Updated description of BMS pin on page 7 3929 Updated description of ADVREF pin on page 8 3822 Updated description of DDP and DDM pins on page 9 3824 6275B Added details t
11. eset state is input with pull up enabled too Address Bus AO to A25 All Address Lines are driven to 0 at reset A0 A22 PERE Application dependent A23 A25 Note A23 PC4 A24 PC5 and A25 PC10 are enabled by default at reset through the PIO controllers SMC SDRAM Controller CompactFlash Support NAND Flash Support See External Bus Interface EBI Hardware Interface on page 11 Application Note m 6275E ATARM 18 Dec 07 es caton Note i Signal Name Recommended Pin Connection Description USB Host UHP HDPA Internal pull down resistors Application dependent Refer to the electrical specifications of the HDPE AT91SAM9260 datasheet HDMA Internal pull down resistors Application dependent Refer to the electrical specifications of the FOME AT91SAM9260 datasheet USB Device UDP Integrated programmable pull up resistor UDP_TXVC Integrated pull down resistor to prevent over consumption when the host is disconnected DDP Application dependent To reduce power consumption if USB Device is not used DDP must be left unconnected Integrated pull down resistor to prevent over consumption when the host is disconnected DDM Application dependent To reduce power consumption if USB Device is not used DDM must be left unconnected Notes 1 These values are given only as a typical example 2 Decoupling capacitors must be con
12. nected as close as possible to the microcontroller and on each concerned pin 100nF H VDDCORE 100nF VDDCORE 100nF i VDDCORE GND 3 The power supplies VDDIOM and VDDIOPO and VDDIOP1 power the device differently when interfacing with memories or with peripherals 4 It is recommended to establish accessibility to a JTAG connector for debug in any case 5 Ina well shielded environment subject to low magnetic and electric field interference the pin may be left unconnected In noisy environments a connection to ground is recommended AMEL o 6275E ATARM 18 Dec 07 10 AIMEL 6 Example of USB Host connection A termination serial resistor Rey must be connected to HDPA HDPB and HDMA HDMB A recommended resistor value is defined in the electrical specifications of the AT91SAM9260 datasheet 5V 0 20A 10uF 100nF 10nF Rext Type A Connector HDMA or HDMB HDPA or HDPB Rext 7 Example of USB Device connection As there is an embedded pull up no external circuitry is necessary to enable and disable the 1 5 kOhm pull up Internal pull downs on DDP and DDM are embedded to prevent over consumption when the host is disconnected A termination serial resistor Rex must be connected to DDP and DDM A recommended resistor value is defined in the electrical specifications of the AT91SAM9260 datasheet 5V Bus Monitoring 27K PIO DDM DDP 3 TypeB 4 Rext Connector Application Note
13. ntents of this document and reserves the right to make changes to specifica tions and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically pro vided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products are not intended authorized or warranted for use as components in applications intended to support or sustain life POWERED ARMs 2007 Atmel Corporation All rights reserved Atmel logo and combinations thereof DataFlash and others are registered trademarks SAM BA and others are trademarks of Atmel Corporation or its subsidiaries ARM the ARM Powered logo Thumb and others are regis tered trademarks or trademarks of ARM Ltd Other terms and product names may be the trademarks of others 6275E ATARM 18 Dec 07
14. o schematic 1 8V and 3 3V Dual Power Supply with 3 3V Powered 3891 Memories Schematic Example3 Added details on harsh environment in Footnote on page 9 Added details on connection example for CE don t care NAND Flash in Footnote on page 13 Corrected PIO denomination in Section 5 2 SAM BA Boot on page 15 Section 5 3 DataFlash Boot on page 15 and Section 5 4 NAND Flash Boot on page 15 3916 Updated Main Oscillator description and figure on page 5 and Slow Clock Oscillator 4067 description and figure on page 6 OSCSEL JTAGSEL and BMS pin descriptions 6275C updated on page 6 and page 7 Updated HDPA HDPB HDMA HDMB pin descriptions on page 9 Removed 4202 resistors from schematic in Note on page 10 Changed information on internal pull down resistors for HDPA HDPB HDMA HDMB on page 9 Updated Recommended Pin Connection for DDANA OSCSEL JTAGSEL 6275E TT 5074 4732 Updated descriptiion for ADVREF 6275D 4207 16 Application Note mem 6275E ATARM 18 Dec 07 AIMEL T O Headquarters Atmel Corporation 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721 9778 Fax 852 2722 1369 Product Contact Web Site www atmel com www atmel com AT91SAM Atmel Europe Le Krebs
15. ocessor ARM Thumb instruction sets Embedded in circuit emulator ARM9EJ S Technical Reference Manual ARM926EJ S Technical Reference Manual Evaluation Kit User Guide AT91SAM9260 EK Evaluation Board User Guide Using SDRAM on AT91SAM9 Microcontrollers Using SDRAM on AT91SAM9 Microcontrollers NAND Flash Support in AT91SAM9 Microcontrollers NAND Flash Support in AT91SAM9 Microcontrollers 2 Application te i i i i EEE 6275E ATARM 18 Dec 07 3 Schematic Check List es caon Note 1 8V and 3 3V Dual Power Supply with 3 3V Powered Memories Schematic Example DC DC Converter GNDANA 100nF 100nF GND a apres GND DC DC Converter VDDIOM 10uF 100nF ad GND 100nF GNDPLL 100nF GNDBU T t 10uF 100nF a GND VDDANA VDDIOPO VDDPLL VDDBU VDDCORE VDDIOP1 deo 1 8V and 3 3V Dual Power Supply Schematic Example 3 3V external memories VDDIOM 3 3V Image Sensor VDDIOP1 ADC VDDANA is used T Signal Name VDDCORE Recommended Pin Connection 1 65V to 1 95V Decoupling Filtering capacitors 100 nF and 10pF Decoupling Filtering capacitors must be added to improve startup stability and reduce source voltage drop Description Powers the device VDDPLL 1 65V to 1 95V Decoupling capacitor 100 nF Powers the PLL cells and the Main Oscillator VDDBU 1 65V to 1 95V Deco
16. t prevents using the USB for SAM BA Boot If the Internal RC Oscillator is used OSCSEL 0 and the Main Oscillator is bypassed Table 5 2 Supported Input Frequencies MHz 1 0 2 0 6 0 12 0 25 0 50 0 Other Frequency Boot on DBGU Yes Yes Yes Yes Yes Yes Yes Boot on USB Yes Yes Yes Yes Yes Yes No Note Any other input frequency can be used but it prevents using the USB for SAM BA Boot 5 1 2 External 32 768 Hz Crystal Selected OSCSEL 1 If an external 32 768 Hz Oscillator is used OSCSEL 1 and the Main Oscillator is active Table 5 3 Supported Crystals MHz 3 0 3 2768 3 6864 3 84 4 0 4 433619 4 9152 5 0 5 24288 6 0 6 144 6 4 6 5536 7 159090 7 3728 7 864320 8 0 9 8304 10 0 11 05920 12 0 12 288 13 56 14 31818 14 7456 16 0 17 734470 18 432 20 0 Note Booting either on USB or on DBGU is possible with any of these crystals 14 Application Note memm 6275E ATARM 18 Dec 07 es caton Note 5 2 5 3 5 4 If an external 32 768 Hz Oscillator is used OSCSEL 1 and the Main Oscillator is bypassed Table 5 4 Supported Input Frequencies MHz 3 0 3 2768 3 6864 3 84 4 0 4 433619 4 9152 5 0 5 24288 6 0 6 144 6 4 6 5536 7 159090 7 3728 7 864320 8 0 9 8304 10 0 11 05920 12 0 12 288 13 56 14 31818 14 7456 16 0 17 734470 18 432 20 0 24 25 28 224 32 33 Note Booting either on USB or on DBGU is possible with
17. upling capacitor 100 nF Powers the Backup I O lines Slow Clock Oscillator and a part of the System Controller 6275E ATARM 18 Dec 07 AMEL Signal Name AMEL Recommended Pin Connection 1 65V to 1 95V Description Powers External Bus Interface 1 0 lines Dual voltage range supported The voltage ranges are selected by programming the or ia i VDDIOM 3 0V to 3 6V VDDIOMSEL bit in the EBI_CSA register Decouplino Filtering capacitors At power up the selected voltage is 3 3V nominal and ping g 3 power supply pins can accept either 1 8V or 3 3V 100 nF and 10yF Decoupling Filtering capacitors must be added to improve startup stability and reduce source voltage drop 3 0V to 3 6V Powers Peripheral I O lines and USB transceivers VDDIOPO Decoupling Filtering capacitors eet 1 2 Decoupling Filtering capacitors must be added to improve 100 nF and 10uF a startup stability and reduce source voltage drop Powers Peripheral I O lines involving the Image Sensor 1 65V to 3 6V Interface ISI VDDIOP1 Decoupling Filtering capacitors 100 nF and 10yF Decoupling Filtering capacitors must be added to improve startup stability and reduce source voltage drop conden P the Analog to Digital C ter ADC and A F 1 2 owers the Analog to Digital Converter and some VDDANA Decoupling capacitor 100 nF PIOC 1 0 lines Application dependent GND pins are common to VDDCORE VDDI
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