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TR5-F40W User Manual

1. 73 O LPCIEXPRESS SYSTEM INFRASTRUCTURE 73 6 2 FPGA PCI EXPRESS SYSTEM DESIGN 74 6 3 PC PCI EXPRESS SYSTEM DESIGN Eve bes vta dn URN EE 78 6 4 FUNDAMENTAL COMMUNICATION csccceccscceccecceccecccscceccsccsccsscscescesccsccsccsscsscescescescesscsscsscsceecescescesscsscescesceecencs 46 6 5 EXAMPLE 2 IMAGE PROCESS APPLICATION 93 ADDITIONAL INFORMATION Vg Ue OB E YrA Rl VO OA OPENS 98 TR5 F40W User Manual 3 www terasic com ter www terasic com August 29 2014 Chapter 1 Overview This chapter provides an overview of the TR5 F40W Development Board and installation guide 1 1 General Description The Terasic TR5 F40W Stratix V GX FPGA Development Kit provides the ideal hardware platform for developing high performance and high bandwidth application With standard height half length form factor package the TR5 F40W is designed for the most demanding high end applications empowered with the top of the l
2. 1 i SSS 8a 9 546570 112 siS70_controller u1 iFREG_MODE 6h lt gt 570 controleru iiRST n ej 8570 ej 5570 1 i Figure 5 4 Timing Waveform of Si570 Controller B Modify Clock Parameter For Your Own Frequency If all the six clock frequencies are not desired you can perform the following steps to modify 51570 controller 1 Open i2c reg controller v 2 Locate the Verilog code shown below always begin MODE 310 100 7 new hs div 4 b0101 new nl 8 b0000 1010 fdco 28004 E200 end 311 125Mhz begin new hs div 4 b0101 new nl 8 b0000 1000 TR5 F40W User Manual 63 iur Poss rA www terasic com August 29 2014 ANU S fdco 28 h004 E200 end 3h2 156 25Mhz begin new hs div 4 b0100 new nl 8 b0000 1000 fdco 281004 E200 end 3h3 250Mhz begin new hs div 4 b0101 new nl 8 b0000 0100 fdco 281004 E200 end 314 312 5Mhz begin new hs div 4 0100 new nl 8 b0000 0100 fdco 281004 E200 end 3h5 322 265625Mhz begin new hs div 4 b0100 new nl 8 b0000 0100 fdco 28 h005 0910 end 3h6 644 53125Mhz begin new hs div 4 b0100 new 8 60000 0010 fdco 28 h005 0910 end default 100Mhz begin new hs
3. 1 rHSMC Expansion pin 1004 DCC HighSpeedADC DAC C SFPIG REFCLK p n 15000 MHz Prefix Name Default Setting Load Setting Save Setting Figure 3 6 Project Settings B Project Generation When users press the Generate button the System Builder will generate the corresponding Quartus II files and documents as listed in the Table 3 1 in the directory specified by the user Table 3 1 Files generated by System Builder No Filename Description 00000000 0000 cones COCMEED consoler 4 Project name gt qpf Quartus II Project File 5 Project name gt qsf Quartus Setting File Project name gt sdc Synopsis Design Constraints file for Quartus Project name gt htm Pin Assignment Document The 51570 Controller includes seven files 51570 controller v initial config v clock divider v TR5 F40W User Manual 48 iur tease www terasic com August 29 2014 ANU RYAN edge detector v 12 reg controller v 12c_controller v and 12 controller v Users can use Quartus II software to add custom logic into the project and compile the project to generate the SRAM Object File sof For 51570 the Controller will be instantiated in the Quartus II top level file as listed below Configure 51570 644 5312 MHz
4. 61 4 2 51570 Input your chioce Figure 5 7 Menu of Demo Program In the temperature test the program will display local temperature and remote temperature The remote temperature is the FPGA temperature and the local temperature the board temperature where the temperature sensor located In the external PLL programming test the program will program the PLL first and subsequently will use TERASIC QSYS custom CLOCK COUNTER IP to count the clock count in a specified period to check whether the output frequency is changed as configured To avoid a Quartus II compilation error dummy transceiver controllers are created to receive the clock from the external PLL Users can ignore the functionality of the transceiver controller in the demonstration The example uses CDCMOIOO0x Config IP which is generated by system builder to programming CDCM61004 The Nios II uses PIO controllers to control the IP First Nios II specifies the desired output frequency through IP s desired freq pin then active the PPL recalibration by toggle IP s recal n pin For 51570 programming please note the device I2C address is 0x00 Also before configuring the output frequency users must freeze the DCO bit 4 of Register 137 first After configuring the output frequency users must un freeze the DCO and assert the NewFreq bit bit 7 of Register 135 B Design Tools e Quartus II 12 0 e Nios II Eclipse 12 0 B Demonstration Source
5. 1570 controller 81570 controller inst iCLK OSC 50 B3B system clock 50mhz iRST n BUTTON 0 system reset iFREQ MODE 3 b110 2 CLK CLOCK SCL I2C DATA CLOCK SDA oController Ready For CDM61004 configure the System Builder will generate the 100 Config and instantiates it in the Quartus II top level file as listed below TR5 F40W User Manual 49 www terasic com www terasic com August 29 2014 Configure CDCHM61004 150 desired freq 62 5 MHz 11 15 MHz 100 MHz ff 125 MHz 150 MHz ff 156 25 MHz ff 187 5 MHz 200 MHz 250 MHz ff 312 5 MHz 625 MHz assign desired freq assign desired freq assign desired freq assign desired freq assign desired freq assign desired freq assign desired freq assign desired freq e Dr assign desired freq assign desired freq assign desired freq LL 00 c in j CDCMe100x Config CDCM61004 Config inst Clk 50 5 50 recal n CPU RESET n desired freq desired freq CLE CE CLE de CLK OD CLE OD OS CLE 05 CLE PR CLE PR RST n CLK RST n If dynamic configuration for the oscillator 1s required users need to modify the code according to users desired behavior TR5 F40W User Manual 50 www terasic com August 29 2014
6. P 2 p v v v HSMC Expansion Programmable Oscillator SED REFCLK pin 6445312 MHz HSMC Transceiver x 8 SATA REFCLK pin CDCM61004 DCC High Speed ADCIDAC Default Setting Load Setting Save Setting Generate Figure 3 4 System Configuration Group B Programmable Oscillator There are two external oscillators on board that provide reference clocks for the following signals SFP_REFCLK SFPIG REFCLK SATA_HOST_REFCLK and SATA DEVICE REFCLK To use these oscillators users can select the desired frequency on the Programmable Oscillator group as shown in Figure 3 5 SPF or SATA should be checked before users can start to specify the desired frequency in the programmable oscillators As the Quartus project is created System Builder automatically generates the associated controller TR5 F40W User Manual 46 METRI www terasic com August 29 2014 ANU RYA according to users desired frequency in Verilog which facilitates users implementation as no additional control code is required to configure the programmable oscillator Note If users need to dynamically change the frequency they would need to modify the generated control code themselves r Terasic TRSFAOW V1 0 0 05 System Configuration
7. The vender ID is defined as 0x1172 and the device ID 15 defined as 0 001 The BUTTON LED register address is 0x04 based on PCIE BARI A C class PCIE is designed to encapsulate the DLL dynamic loading for TERASIC PCIE DLL loading TERAISC PCIEx64 DLL under 64 bits Windows A PCIE instance is created with the name m hPCIE To enumerate all PCIe cards in system call the function m hPCIE ScanCardiwVendorID wDewiceID amp dwDewiceNum m szPcielntfoj TR5 F40W User Manual 91 LA www terasic com August 29 2014 ANU where wVendorID and wDeviceID are zeros The return value dwDeviceNum represents the number of PCIe cards found in the system The m szPcieInfo array contains the detail information for each PCIe card To connect the selected PCIe card the functions are called int noel CaomhboBoxBoard Itemlndex WORD VID szPcieInfo n5el VendorID WORD DID m szPcieInfo nS5el DeviceID HSuccess m HPCIE Open VID DID O 0 first matched board where nSel is selected index in the Selected FPGA Board poll down menu Based on the return m szPcieInfo we can find the associated PID and DID which can use to specifiy the target PCIe card To read the BUTTON status the function 1s called m HPCIE Read32 DEMO PCIE USER BAR DEMO PCIE IO ADDR amp dwData To set LED status the function 1s called m hPCIE Write32 DEMO PCIE USER BAR DEMO PCIE IO ADDR dwData
8. Databus 25V _ PINAG2 Databus 1 25V PINAF22 Databus 2 Databus 25V Databus 257 PINAE0 Databus 0 25V PINAE2 FSM 017 Daabus 25V PINAD2 Databus 7 4 25V Databus __ 25 PINAE Databus 25V _ PINAE2 FSM D27 Databus 1 1 1 25V PINAE2 Databus 11 25V PIN_AF25 Databus __ 25V PINAF20 Tasic TR5 F40W User Manual 25 NP MIS RAD www terasic com August 29 2014 SSRAM DPAO Data bus 2 5 V PIN AK30 SSRAM DPA1 Data bus 2 5 V PIN AN25 SSRAM DPA2 Data bus 2 5 V PIN AL27 SSRAM DPA3 Data bus 2 5 V PIN AN27 SSRAM CLK Synchronous Clock 2 5 V PIN SSRAM BE 0 Synchronous Byte lane 0 Write Input 2 5 V PIN AJ29 SSRAM BE n1 Synchronous Byte lane 1 Write Input 2 5 V PIN AL28 SSRAM BE n2 Synchronous Byte lane 2 Write Input 2 5 V PIN AK27 SSRAM BE n3 Synchronous Byte lane 3 Write Input 2 5 V PIN AH25 SSRAM OE n Output Enable 2 5 V PIN AM28 SSRAM CE1 n Synchronous Chip enable 2 5 V PIN AL26 SSRAM WE n Write enable 2 5 V PIN AK29 SSRAM GW n Synchronous Burst Address Advance 2 5 V PIN AL30 SSRAM ADV n Address Status Controller 2 5 V PIN AN26 SSRAM ADSC n Address Status Controller 2 5 V PIN AM29 SSRAM ADSP n Address Status Processor 2 5 V PIN 28 SSRAM MODE Burst Sequence Selection 2 5 V PIN AJ27 SSRAM ZZ P
9. AND S RYAN nery Project 4 CLOCK V Switch x 4 v LEDx 10 Button x 4 4 Fan Control Temperature 7 Flash 256 155 RS 422 SFP SFP D 4 Sata Host Sata Device PCle HSMC Expansion REFCLK pi MHz HSMC Transceiver x 8 SATA REFCLK CDCM61004 DCC High Speed ADC DAC SFPIG REFCLK 150 00 MHz Name HSMC REFCLK p n Load Setting Save Setting Generate Default Setting Figure 3 5 External Programmable Oscillators B Project Setting Management The System Builder also provides functions to restore default setting loading a setting and saving users board configuration file shown in Figure 3 6 Users can save the current board configuration information into a cfg file and load it to the System Builder TR5 F40W User Manual 47 www terasic com August 29 2014 ANU S RYAN Terasic TRSFAOW V1 0 0 e 208 r System Configuration ATERA c 4 3 UNIVERSITY Project Name TROF40W PROGRAM www teresic com CLOCK 4 Switch x 4 v LEDx 10 Button x 4 Fan Control 4 Temperature Flash 256MB VI SSRAM RS 422 VISMA VI SFP SFP SFP C D Sata Host Sata Device 4 PCle Programmable Oscillator
10. Chapter 4 Flash Programming As you develop your own project using the Altera tools you can program the flash memory device so that your own design loads from flash memory into the FPGA on power up This chapter will describe how to use Altera Quartus II Programmer Tool to program the common flash interface CFI flash memory device on the FPGA board The Stratix V GX FPGA development board ships with the CFI flash device preprogrammed with a default factory FPGA configuration for running the Parallel Flash Loader design example 4 1 CFI Flash Memory Map Table 4 1 shows the default memory contents of two interlaced 1Gb 128MB CFI flash device Each flash device has a 16 bit data bus and the two combined flash devices allow for a 32 bit flash memory interface For the factory default code to run correctly and update designs in the user memory this memory map must not be altered Table 4 1 Flash Memory Map Byte Address Block Description Size KB Address Range PFL option bits 64 0x00030000 0x0003FFFF Factory hardware 33 280 0 00040000 0x020BFFFF User hardware 33 280 0 020 0000 0x0413FFFF Factory software 8 192 0x04140000 0x0493FFFF User software and data 187 136 0 04940000 OxOFFFFFFF For user application user hardware must be stored with start address 0x020C0000 and the user s software is suggested to be stored with start address 0x04940000 The NIOS II EDS tool nios 2 flash programmer is used for programmin
11. LVDS RX bit 3n or CMOS I O LVDS TX bit 4 or CMOS I O LVDS RX bit 4 or CMOS I O LVDS TX bit 4n or CMOS LVDS RX bit 4n or CMOS I O LVDS TX bit 5 or CMOS I O LVDS RX bit 5 or CMOS I O LVDS TX bit 5n or CMOS LVDS RX bit 5n or CMOS I O LVDS TX bit 6 or CMOS I O LVDS RX bit 6 or CMOS I O LVDS TX bit or CMOS LVDS RX bit 6n or CMOS I O LVDS TX bit 7 or CMOS I O LVDS RX bit 7 or CMOS I O LVDS TX bit 7n or CMOS I O LVDS RX bit 7n or CMOS I O LVDS TX or CMOS I O LVDS RX or CMOS differential clock input LVDS RX or CMOS LVDS RX or CMOS or differential clock input LVDS TX bit or CMOS I O LVDS RX bit 8 or CMOS I O LVDS TX bit 8n or CMOS I O LVDS RX bit or CMOS LVDS TX bit 9 or CMOS I O LVDS RX bit 9 or CMOS I O 2 40 TR5 F40W User Manual www terasic com LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO LVDS or VCCIO PIN K21 PIN 120 PIN J21 PIN H20
12. SOMHz Oscillator o Programmable oscillators 51570 and 61004 o SMA connector for external clock input output e Memory o SSRAM o FLASH e Communication Ports Four SFP connectors One SATA host port One SATA device port PCI Express PCIe x8 edge connector One RS422 transceiver with RJ45 connector One HSMC Connector Oo O O O0 O 5 e System Monitor and Control o Temperature sensor o Fan control e Power PCI Express 6 pin power connector 12V DC Input o PCI Express edge connector power e Mechanical Specification TR5 F40W User Manual 5 www terasic com ter www August 29 2014 ANU RYAN o PCI Express standard height and half length 1 3 Block Diagram Figure 1 1 shows the block diagram of the TR5 F40W board To provide maximum flexibility for the users all key components are connected with the Stratix V GX FPGA device Thus users can configure the FPGA to implement any system design Transceiver Link LED x4 LED Lamp x4 Switch x4 Button x4 SSRAM x36 Stratix V To FPGA For 10G Refclk To FPGA diia 4 SFP x4 2 Connector x8 10 0 SMA Clock Input SMA Clock Out Figure 1 1 Block diagram of the TR5 F40W board Stratix V GX FPGA 5SGXEA3K2FA0C3 e 340 000 logic elements LEs e 19 Mbits emb
13. TRS F40W FPGA Development Kit User Manual 2 9 ET 4 d 4 2 2972 47554 11021114 Memory i he a i 1370 ter WWW terasic com Copyright 2003 2014 Terasic Technologies Inc All Rights Reserved CONTENTS CHAPTER 1 OQ 4 1 1 GENERAL DESCRIPTION 4 RY AIRE 4 DP RAN 6 CHAPTER 2 BOARD COMPONENTS 9 ENNIO 8 1 9 2 2 CONFIGURATION STATUS AND SETUP eee iud Een EFE ERA TA ey v OX CUN FAVRE M E EE 10 2 S GENERAL USER INPUT OUTPUT 15 2 4 TEMPERATURE SENSOR AND FAN CONTROL scecccccecosscscceccececccccscsececcecsscecesceccesascsecescnscssasceecessesascsececceseesaecess 17 18 Es nae waco 20 MEMOR Y 21 20 31 es di 24 ZU mimi eres ra eo 26 LAO PETE ADI CREER 29 P LT 31 2 12 HSMC HIGH SPEED MEZZANI
14. To write and read memory mapped memory call the functions 7 write bouccess m hPCIE DmaWriteiLocal ddr pWrite nTestSizel it iba2uccezss i read bouccess m hPCIE DmaEead Local ddr pEead 5 To write and read FIFO memory call the functions 7 write bouccess m hPCIE DmaFiroWriteiFifoID pWrite nTestsoizel ift bSuccess 1 read bouccess m hPCIE DmaFirfoEeadiFifoID pRead nTest izej TR5 F40W User Manual J2 www terasic com ter WWW Lot www terasic com JA DTE RYAN 6 5 Example 2 Image Process Application This example shows how to utilize computing power of the FPGA for image processing The application demonstrates the invert image processing by utilizing the FPGA The PC and FPGA source code of the application layer are all available in the FPGA system CD allowing users to easily extent the image process function based on this fundamental reference design In the demonstration a memory mapped memory is designed in the FPGA to work as an image frame buffer The memory size is 320x240x3 bytes with start address 0x00 The raw image is downloaded to and uploaded from FPGA by DMA The image process command and status is controlled by a register which can be accessed from the PC by basic IO control The register address is 0x10 under PCIE BARI Writing any value into this register will start the image process The status of the image process is
15. reg controller which allows the 51570 controller to configure 51570 based on default settings iCLK Initial config Clock_divider iRST n iStart Initial Start Signal I2C_CLK iFREG_MODE Register Setting oController Ready 2 reg controller pm 2 bus controller 2 DATA I2C CLK Figure 5 3 Block Diagram of Si570 Controller IP TR5 F40W User Manual 61 iud Tees A www terasic com August 29 2014 ANU RYA B Using 51570 Controller IP Table 5 3 lists the instruction ports of 51570 Controller IP Table 5 3 S1570 Controller Instruction Ports Port Direction Description input System Clock 50Mhz iRST n input Synchronous Reset 0 Module Reset 1 Normal iStart input Start to Configure positive edge trigger iFREQ MODE input Setting 51570 Output Frequency Value 51570 Configuration status 0 Configuration in Progress 1 Configuration Complete l2C DATA inout I2C Serial Data to from Si570 2 CLK output I2C Serial Clock to Si570 oController_Ready output To use the 51570 Controller the first thing users need to determine is the desired output frequency in advance The 51570 controller provides six optional clock frequencies These options can be set through an input port named MODE in 51570 controller The specified settings with corresponding frequencies are listed in Table 5 4 For example setting MODE 375110 will configure 51570 to
16. PB2 7 BUTTON2 not pressed PIN B17 PIN A17 B User Defined Slide Switch There are four slide switches on the FPGA board to provide additional FPGA input control When a asic TR5 F40W User Manual 15 www www terasic com August 29 2014 ANU RYAN slide switch is in the DOWN position or the UPPER position it provides a low logic level or a high logic level to the Stratix V GX FPGA respectively as shown in Figure 2 8 Figure 2 8 4 Position Slide switches Table 2 6 lists the signal names and their corresponding Stratix V GX device pin numbers Table 2 6 Slide Switch Pin Assignments Schematic Signal Names and Functions Board Schematic Stratix V GX Description Reference Oe Name Standard Pin Number PIN_F17 High logic level when SW in the UPPER PIN G17 25 PNGIS 25V 616 B User Defined LEDs The FPGA board consists of 10 user controllable LEDs to allow status and debugging signals to be driven to the LEDs from the designs loaded into the Stratix V GX device Each LED is driven directly by the Stratix V GX FPGA The LED is turned on or off when the associated pins are TR5 F40W User Manual 16 www terasic com August 29 2014 driven to a low or high logic level respectively A list of the pin names on the FPGA that are connected to the LEDs is given in Table 2 7 Table 2 7 User LEDs Pin Assignments Schematic Sig
17. PIN G21 PIN G20 PIN F21 PIN M21 PIN F20 PIN L21 PIN E20 PIN B20 PIN E21 PIN A20 PIN D21 PIN C20 PIN F23 PIN C21 PIN E23 PIN P23 PIN B26 PIN N23 PIN A26 PIN T24 PIN B28 PIN R24 PIN A28 PIN B29 PIN B31 PIN A29 PIN A31 PIN L33 PIN M23 PIN L34 PIN L23 PIN A36 PIN B22 PIN A37 PIN A22 PIN A34 PIN M26 WWW terasic com August 29 2014 109 TX LVDS TX 9n or CMOS I O LVDS or VCCIO A35 110 HSMC RX LVDS RX bit 9n or LVDSorVCCIO 126 113 HSMC TX p10 LVDS TX bit 10 LVDSorVCCIO B32 114 HSMC p10 LVDS RX bit 10 or CMOSI O LVDSorVCCIO K27 115 8 TX 10 LVDS TX bit 10n or CMOS I O LVDSorVCCIO A32 116 HSMC RX n10 LVDS RX 10n or CMOS LVDS or VCCIO J27 119 TX LVDS TX bit iiorCMOS O LVDSorVCCIO 030 120 HSMC p11 LVDS RX bit 11 or CMOS I O LVDSor VCCIO H29 121 HSMC TX n11 LVDS TX bit 11n or CMOS LVDSorVCCIO C30 122 HSMC n11 LVDS RX bit 11n or CMOS 1 0 or VCCIO 629 125 HSMC TX p12 LVDS TX 12 LVDSorVCCIO 131 126 HSMC RX p12 LVDS biti2or CMOSI O LVDSorVCCIO K30 127 TX n12 LVDS TX bit 12n CMOS I O 1 08 PIN 130 128 HSMC n12 LVDS RX bit 12n or CMOS I O LVDSor VCCIO 430 131 HSMC TX 13 LVDS TX biti3or LVDSorVCCIO PIN G3
18. define DEMO IMAGE ADDR E The vender ID is defined as 0x1172 and the device ID is defined as 001 The image dimension is defined as 320x240 The register address 15 0x 10 and memory address 15 0x00 A C class PCIE is designed to encapsulate the DLL dynamic loading for TERASIC PCIE DLL loading TERAISC PCIEx64 DLL under 64 bits Windows A PCIE instance is created with the name m hPCIE To open a connection with FPGA the function is called hPCIE OpeniPCIE VID PCIE DID O first matched board To download the raw image from PC to FPGA memory the function 1s called m hPCIE DmaWriteiDEMO IMAGE DATA ADDE plmage nlmagesize j where pImage is a pointer of the image raw data and the nImageSize specifies the image size In this reference design nImageSize 320x240x3 byte To start the image process the function 1s called m hPCIE Write3z DEMO PCIE USER BAR DEMO IMAGE REG ADDR 1 The image process is started whenever the register is written with any value To check whether the image process is finished the control register is monitored by calling the function m hPCIE Read32 DEMO PCIE USER BAR DEMO IMAGE REG ADDR sdwStatus When the image process is finished the value of dwStatus becomes zero TR5 F40W User Manual 96 www terasic com ter www terasic com August 29 2014 ANU RYAN To update the processed image from FPGA memory to PC the function is
19. such as hard drives optical drives and solid state disks Supporting a storage interface 1s just one of many different applications an FPGA can be used in storage appliances The Stratix V GX device can bridge different protocols such as bridging simple bus I Os like PCI Express PCIe to SATA or network interfaces such as Gigabit Ethernet GbE to SATA The SATA interface supports SATA 3 0 standard with connection speed of 6 Gbps based on Stratix V GX device with integrated transceivers compliant to SATA electrical standards The two Serial ATA SATA ports include one port for device and one port for host capable of implementing SATA solution with a design that consists of both host and target device side functions Figure 2 15 depicts the host and device design examples asic TR5 F40W User Manual 31 www terasic com ter a www terasic com August 29 2014 Figure 2 15 PC and Storage Device Connection to the Stratix V GX FPGA The transmitter and receiver signals of the SATA ports are connected directly to the Stratix V GX transceiver channels to provide SATA IO connectivity to both host and target devices To verify the functionality of the SATA host device ports a connection can be established between the two ports by using a SATA cable as Figure 2 16 depicts the associated signals connected Table 2 19 lists the SATA pin assignments signal names and functions TR5 F40W User Manual 32 www terasic com ter WWW LET uU
20. ANU RYA FPGA User Application TERASIC PCle IP TERASIC_PCIE DLL Altera PCle t User Mode UL Figure 6 1 Express System Infrastructure 6 2 FPGA PCI Express System Design The PCI Express edge connector is able to allow interconnection to the PCIe motherboard slots For basic I O control a communication is established through the PCI Express bus where it is able to control the LEDs and monitor the button status of the FPGA board By implementing an internal RAM and FIFO the demonstration is capable of direct memory access DMA transfers B PCI Express Basic I O Transaction Under read operation the Terasic PCIe IP issues a read signal followed by the address of the data Once the address is received a 32 bit data will be sent along with a read valid signal Under write operation the PCIe IP issues a write signal accompany with the address to be written A 32 bit data is written to the corresponding address with a data enable signal of write operation All the write commands are issued on the same clock cycle Table 6 1 lists the associated port names along with the description Table 6 1 Single Cycle Transaction Signals of Terasic PCIe IP Polarity Clock The reference clock output of PCle local interface oCORE CLK oSC RD ADDR 11 0 Output 2 bus of read transaction It is 32 bit data per TR5 F40W User Manual 74 www terasic com te
21. Code Quartus II Project directory Nios BASIC DEMO e Nios II Eclipse Nios BASIC DEMONSoftware asic TR5 F40W User Manual 69 www terasic com ter a www terasic com August 29 2014 ANU RYAN B Nios IL IDE Project Compilation e Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned first by clicking on Clean in the Project menu of Nios II Eclipse B Demonstration Batch File Demo Batch File Folder Nios BASIC DEMONdemo batch The demo batch file includes following files e Batch File for USB Blaster II test ub2 bat test bashrc 062 FPGA Configure File TR5_f40w_golden_top sof e Nios II Program Nios DEMO elf B Demonstration Setup e sure Quartus II and Nios are installed on your e Power on the FPGA board Use the USB Cable to connect your PC and the FPGA board and install USB Blaster II driver if necessary e Execute demo batch ub2 bat under the batch file folder Nios _BASIC_DEMO demo_batch e After the Nios II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal For temperature test please input key 0 and press Enter the nios terminal as shown in Figure 5 8 For programming PLL CDCD61004 test please input key 1 and press Enter in nios terminal first then select the desired output frequency as shown in Figure
22. FIFO ID that is used to indicate that which FIFO buffer is selected by PC API Write data bus Write signal Indicates that DMA channel is memory mapping interface or FIFO link interface When this signal is asserted high DMA channel FIFO link interface When the signal is asserted low it is memory mapping interface 76 www terasic com August 29 2014 ANU RYA 1 2 3 d 5 6 7 8 9 oCORE Y oDMARD_ADDR iDMARD DATA KK Cu Cu oDMARD READ Oo 141 3 oDMARD_RDVALID l 2 clock oFIFO MEM SEL Low Level Figure 6 4 Read transaction waveform of the PCle DMA channel on memory mapping mode 1 1 2 3 4 5 6 7 8 9 oCORE oDMAWR_ADDR EXO XB XC oDMAWR_DATA lt gt lt bo 7X lt 4 gt oDMAWR WRITE N oFIFO SEL Figure 6 5 Write transaction waveform of the PCle DMA channel on memory mapping mode TR5 F40W User Manual 21 www terasic com August 29 2014 1 12 oCORE CLK 5 oDMARD ADDR K gt lt FIFO ID 1 1 lt DO X D X 02 X 03 X 2 pod 4 oDMARD READ l 1 o
23. FIFO Write and Read to test FIFO DMA A report dialog box will appear when the DMA process is completed e The Custom Registers Group is used to test custom design register on the FPGA side Users can use this function to verify custom register design B Demonstration Setup e Quartus II 12 0 Borland Builder 6 0 B Demonstration Source Code Location e Quartus Project PCIE Fundamental e Borland C Project PCle SW KIT PCIe Fundamental B FPGA Application Design The PCI Express demonstration uses the basic I O interface and DMA channel on the Terasic PCIe IP to control I O Button LED and access two internal memories RAM FIFO through the MUX block asic TR5 F40W User Manual 90 www terasic com ter www terasic com August 29 2014 ANU RYA FPGA NC v Address Decoder Interface m Basic PCle IP Internal RAM 3 MUX Channel rro Figure 6 13 Hardware block diagram of the PCle reference design B PC Application Design The application shows how to call the TERASIC PCIE DLL TERAISC PCIEx64 DLL under 64 bits Windows exported API To enumerate all PCIe cards in system call the software design defines some constant based on FPGA design shown below define PCIE VID 0x1172 define PCIE DID 1 define DEMO PCIE USER BAR PCIE define DEMO PCIE IO ADDR 0x04 define DEMO PCIE FIFO ID 0 00
24. FSM D5 Data bus 2 5 V PIN AG23 FSM D6 Data bus 2 5 V PIN AC27 FSM D7 Data bus 2 5 V PIN AC26 FSM D8 Data bus 2 5 V PIN AA26 FSM D9 Data bus 2 5 V PIN AF23 FSM D10 Data bus 2 5 V PIN AG22 FSM D11 Data bus 2 5 V PIN AF22 FSM D12 Data bus 2 5 V PIN AD21 FSM D13 Data bus 2 5 V PIN 21 FSM D14 Data bus 2 5 V PIN AE20 FSM D15 Data bus 2 5 V PIN AD20 FSM D16 Data bus 2 5 V PIN AE22 FSM D17 Data bus 2 5 V PIN AD22 FSM D18 Data bus 2 5 V PIN AB24 FSM D19 Data bus 2 5 V PIN AD24 FSM D20 Data bus 2 5 V PIN AC24 021 Data bus 2 5 V PIN AA25 FSM D22 Data bus 2 5 V PIN AB25 FSM D23 Data bus 2 5 V PIN AC25 FSM D24 Data bus 2 5 V PIN AE25 FSM D25 Data bus 2 5 V PIN AD26 FSM D26 Data bus 2 5 V PIN AE26 FSM 027 Data bus 2 5 V PIN AE24 FSM D28 Data bus 2 5 V PIN AF25 FSM D29 Data bus 2 5 V PIN AF26 WWw terasic com August 29 2014 TR5 F40W User Manual 23 www terasic com FSM D30 Data bus 2 5 V PIN AA27 FSM D31 Data bus 2 5 V PIN AB27 FLASH CLK Clock 2 5 V PIN AB30 FLASH RESET n Reset 2 5 V PIN AT27 FLASH CE n 0 Chip enable of of flash 0 2 5 V PIN AU25 FLASH CE n 1 Chip enable of of flash 1 2 5 V PIN AN24 FLASH OE n Output enable 2 5 V PIN 27 FLASH WE n Write enable 2 5 V PIN AP28 FLASH ADV n Address valid 2 5 V PIN AR27 FLASH RDY BSY n 0 Ready of flash 0 2 5 V PIN AU26 FLASH RDY BSY n 1 Ready of flash 1 2 5 V PIN AR28 2 8 SSRAM The IS61LPS51236A Synchronous Static Random Access Memory SSRAM device featured the TR
25. N1 1 0 RFREQ 31 24 RFREQ 23 16 RFREQ 15 8 RFREQ 7 0 RST REG Freeze M Bit 4 N1 6 2 RFREQ 37 32 Freeze VCADC Freeze DCO Table 5 2 lists the register settings for some common used frequency Output Frequency MHz 100 125 156 25 250 312 5 322 265625 644 53125 www terasic com Table 5 2 81570 Register Table HS_DIV HS_DIV NI Register Setting 9 101 6 11 111 4 9 101 4 11 111 2 9 101 2 4 000 4 4 000 2 TR5 F40W User Manual 58 NI Register Setting 0000101 0000011 0000011 0000001 0000001 0000011 0000001 Bit 3 Bit 2 Bit 1 Bit 0 RECALL REF_CLK Register Setting 02F40135A9 hex 0302013B65 hex 0313814290 hex 0302013B65 hex 0313814290 hex 02D1E127AF hex 02D1E127AF hex www terasic com August 29 2014 ANU RYA B CDCM61004 The FPGA board includes another programmable PLL CDCM61004 The CDCM61004 supports output frequency range from 43 75 MHz to 683 264 MHz It provides a parallel interface for selecting a desired output frequency The Stratix V GX FPGA s IOs connect to the interface directly The differential clock outputs of the CDCM61004 are designed for SFP and SATA applications on FPGA board When CDCM61004 is powered on the default output frequency is 100 MHZ Users can change output frequency by the following control pins RSTN CE PRO and PRI ODO ODI and OD2 OSO and OSI The following table li
26. TR5 F40W User Manual 33 www terasic com www August 29 2014 ANU S RYAN 2 12 HSMC High Speed Mezzanine Card The FPGA development board contains one HSMC connector The HSMC connector provides a mechanism to extend the peripheral set of an FPGA host board by means of add on cards which can address today s high speed signaling requirement as well as low speed device interface support The HSMC interfaces support JTAG clock outputs and inputs high speed serial I O transceivers and single ended or differential signaling The HSMC interface connected to the Stratix V GX device is a female HSMC connector having a total of 172pins including 121 signal pins 120 signal pins 1 PSNTn pin 39 power pins and 12 ground pins The HSMC connector is based on the SAMTEC 0 5 mm pitch surface mount QSH family of high speed board to board connectors The Stratix V GX device provides 12 V DC and 3 3 V DC power to the mezzanine card through the HSMC connector Table 2 20 indicates the maximum power consumption for the HSMC connector Table 2 20 Power Supply of the HSMC Supplied Voltage Max Current Limit 12V 2A 3 3V 3A There are three banks in this connector as Figure 2 17 shows the bank arrangement of signals with respect to the SAMTEC connector Table 2 21 lists the mapping of the FPGA pin assignments to the HSMC connectors TR5 F40W User Manual 34 www terasic com www terasic com Augu
27. Terasic TRSFAOW 1 0 0 UNIVERSITY PROG AM Programmable Oscillator SATA REFCLK p n 1004 HSMC REFCLK r System Configuration Project TRoF40W CLOCK V Switch x 4 iv LEDx 10 Button x 4 4 Fan Control 4 Temperature 4 Flash 256 SSRAM V RS 422 VISMA SFP B SFP C D Sata Host Sata Device PCIe 8550 rHSMC Expansion SFP_REFCLK_pin MHz HSMC Transceiver x 8 SFP1G_REFCLK_pjn MHz Prefix Name Default Setting Load Setting Save Setting Figure 3 2 The System Builder window B Select Board Type and Input Project Name Select the target board type and input project name as show in Figure 3 3 Project Name Specify the project name as it 1s automatically assigned to the name of the top level design entity E Terasic TRSFAOW V1 0 0 C NIVERSITY WWW terasic com r System Configuration VI CLOCK LEDx 10 PCIe VI SFP SFP B SFP C D Sata Host 4 Sata Device Project Name TRbF40W Switch x 4 7 Button x 4 lv Fan Control V Temperature 4 Flash 256MB SSRAM V RS 422 VISMA Programmable Oscillator SE HSMC Expansion REFCLK 644 5312 MHz HSMC Transceiver x 8 SATA R
28. div 490101 new 11 860000 1010 TR5 F40W User Manual 64 ter www terasic com www August 29 2014 fdco 28 h004 E200 end endcase end Users can get a desired frequency output from 51570 by modifying these three parameters new hs div new n1 and fdco Detailed calculation method is in following equation fdco output frequency new hs div new nl 64 There are three constraints for the equation 1 4850 lt output fequency new hs div new nl lt 5600 2 4 lt hs div lt 11 3 1 new nl lt 128 For example you want to get a 133 5 mhz clock then fdco 133 5 x 4x 10x64 3417604 0 53700 Find a mode in this RTL code section and modify these three parameters as shown below new hs div 3 b100 new nl 461010 fdco 23 h05 3700 In addition Silicon Lab also provide the corresponding calculation tool Users can refer to the Programmable Oscillator tool See Figure 5 5 mentioned in below link to calculate the values of new hs div and new nl then the fdco value can calcuted with above ftdo equation http www silabs com products clocksoscillators oscillators Pages oscillator software development tools aspx TR5 F40W User Manual 65 www terasic com ter www August 29 2014 ANU S RYAN Programmable Oscillator Calculator SiS x Options Power Supply Control He
29. includes a function to monitor system temperature with the on board temperature sensor B System Block Diagram Figure 5 6 shows the system block diagram of this demonstration The system requires a 50 MHz clock provided from the board The peripheral temperature sensor 51570 and CDCM61004 are all controlled by Nios II through the PIO controller The temperature sensor and external PLL 51570 are controlled through I2C interface The Nios II program toggles the PIO controller to implement the protocol CDCM 61004 is programmed through the CDCM6100x_Config and Nios II controls the IP through PIO controllers The Nios II program is running in the on chip memory FPGA 2 50 2 QSYS Nios Il lt gt Controller ew gt Controller 2 5 o Controller Controller c ede lt a gt Clock 2 Counter On Chip 45 gt Clock Memory Counter Figure 5 6 Block Diagram of the Nios II Basic Demonstration The program provides a menu in nios terminal as shown in Figure 5 7 to provide an interactive interface With the menu users can perform the test for the temperatures sensor and external PLL Note Inputting choice number should be followed by pressing Enter TR5 F40W User Manual 68 ETE www terasic com August 29 2014 Altera Nios II EDS 12 0 gcc4 Stratix U Demo Program 9 Temperature 1
30. n ANU S n VAN PCIE TX p 7 0 PCIE TX n 7 0 Stratix V Gx PCIE RX pI7 0 PCIE RX 7 0 Figure 2 14 Express pin connection Table 2 18 PCI Express Pin Assignments Schematic Signal Names and Functions Schematic Stratix V GX Pin Description Standard Signal Name Number PCIE TX pO Add in card transmit bus 1 4 V PCML PIN AU36 PCIE TX nO Add in card transmit bus 1 4 V PCML PIN AU37 PCIE TX p1 Add in card transmit bus 1 4 V PCML PIN AR36 PCIE TX n1 Add in card transmit bus 1 4 V PCML PIN AR37 PCIE TX p2 Add in card transmit bus 1 4 V PCML PIN AN36 PCIE TX n2 Add in card transmit bus 1 4 V PCML PIN AN37 PCIE TX p3 Add in card transmit bus 1 4 V PCML PIN AL36 PCIE TX n3 Add in card transmit bus 1 4 V PCML PIN AL37 PCIE TX p4 Add in card transmit bus 1 4 V PCML PIN AG36 PCIE TX n4 Add in card transmit bus 1 4 V PCML PIN AG37 PCIE TX p5 Add in card transmit bus 1 4 V PCML PIN AE36 PCIE TX n5 Add in card transmit bus 1 4 V PCML PIN AE37 PCIE TX p6 Add in card transmit bus 1 4 V PCML PIN AC36 PCIE TX n6 Add in card transmit bus 1 4 V PCML PIN AC37 PCIE TX p7 Add in card transmit bus 1 4 V PCML PIN AA36 PCIE TX n7 Add in card transmit bus 1 4 V PCML PIN AA37 PCIE RX pO Add in card receive bus 1 4 V PCML PIN 8 PCIE RX nO Add in card receive bus 1 4 V PCML PIN AV39 PCIE RX p1 Add in card receive bus 1 4 V PCML AT38 PCIE RX n1 Add in card receive bus 1 4 V PCML PIN AT39 PCIE RX p2 Add in card receive
31. output 655 53 MHz clock Table 5 4 51570 Controller Frequency Setting MODE Setting 51570 Clock Frequency MHz 3 b000 100 3 b001 125 3 b010 156 25 3 b011 250 3 b100 312 25 3 b101 322 26 3 b110 644 53125 3 b111 100 When the output clock frequency is decided the next thing users need to do is to enable the controller to configure 1570 Before sending the enable signal to the 51570 controller users need to monitor an output port named oController Ready This port indicates if 51570 controller is ready to be configured or not If it 1s ready logic high will be outputted and the user will need to send a high level logic to iStart port to enable the 51570 Controller as shown in Figure 5 4 During 1570 configuring the logic level of oController Ready is low when it rises to high again that Tasic TR5 F40W User Manual 62 NP MIS RAD www terasic com August 29 2014 JA DTE RYAN means the user can configure another frequency value 7 Signal lap ll Logic Analyzer File Edit View Project Processing Tools Window instance Manager PO m ttt Instance Status LEs 606 Memory 65536 Small NA Medium NA Large NA auto sig Not running 606 cells 65536 bits NA NA NA log 2012 03 22 17 24 29 0 si570 112 oh on
32. present PIN AD9 SFPA MOD1 SCL Serial 2 wire clock PIN AC9 SFPA MOD2 SDA Serial 2 wire data PIN AC12 SFPA RATESELO Rate select 0 2 5V SFPA RATESEL1 Rate select 1 25 9 SFPA TXDISABLE and disables the transmitter PIN AB9 SFPA TXFAULT Transmitter fault PIN AB12 Table 2 15 SFP B Pin Assignments Schematic Signal Names and Functions Schematic E Stratix V GX Description Standard _ Signal Name Pin Number TR5 F40W User Manual www terasic com 27 www terasic com August 29 2014 SFPB TX p Transmitter data 1 4 V PCML PIN AE4 SFPB_TX_n Transmitter data 1 4 V PCML PIN SFPB_RX_p Receiver data 1 4 V PCML PIN SFPB_RX_n Receiver data 1 4 V PCML PIN_AF1 SFPB_LOS Signal loss indicator 2 5V 9 SFPB MODO PRSNT Module present 2 5V PIN AM10 SFPB MOD1 SCL Serial 2 wire clock 2 5V PIN 11 SFPB MOD2 SDA Serial 2 wire data 2 5V PIN AL10 SFPB RATESELO Rate select 0 2 5V PIN AN11 SFPB RATESEL1 Rate select 1 2 5V PIN AP9 SFPB TXDISABLE Turns off and disables the transmitter 2 output SFPB TXFAULT Transmitter fault 2 5V PIN AK11 Table 2 16 SFP Pin Assignments Schematic Signal Names and Functions Schematic TN Stratix V GX 1 Description Standard Signal Name Pin Number SFPC TX p Transmitter data 1 4 V PCML ANA SFPC TX n Transmitter data 1 4 V PCML PIN AN3 SFPC RX p Receiver data 1 4 V PCML PIN AP2 SFPC RX n Receiver data 1 4 V P
33. reported by a read to this register The PCIe vender ID and device ID is 0x1172 and 001 respectively The block diagram of FPGA PCIe design is shown in Figure 6 14 FPGA Tersic PCle IP Basic Li Register Interface L PCI Express x Basic 4 Invert function Internal RAM Figure 6 14 Block Diagram of Image Process in FPGA B Demonstration Files Location The demo file is located in the folder PCIE ImageProcessxdemo batch The folder includes following files TR5 F40W User Manual 93 www terasic com ter Wwww terasic com asic August 29 2014 www terasic com ANU RYA e PC Application Software PCle Image Demo exe FPGA Configuration File PCle_ImageProcess sof e PCIe Library TERASIC PCIE DLL and wapi1921 dll TERASIC PCIEx64 DLL and wapil100 dll for 64 bits Windows Demo Batch File test bat B Demonstration Setup Installed the FPGA board on your e Locate demo folder PCIE batch e Download PCIe ImageProcess sof into the FPGA board using Quartus II Programmer e Restart Windows Installed driver if necessary The driver is located in the folder CDROMNdemonstrationNPCle SW KIINPCIe Driverlnstall e Launch demo program PCIe Image Demo exe Click Select Image to select a bitmap or jpeg file for image processing Terasic PCle Image Demo V1
34. terasic com ANU S RYAN memory SSRAM memory and MAX II CPLD EPM2210 System Controller Figure 2 12 shows the connections between the Flash SSRAM MAX II CPLD and Stratix V GX FPGA Flash x32 Chip Select Data x16 Wn Address amp Command an P Flash x16 Stratix V Data x16 Chip Select Flash x16 SSRAM x36 Chip Select Figure 2 12 Connection between the Flash Max and Stratix V GX FPGA Table 2 12 lists the flash pin assignments signal names and functions Table 2 12 Flash Memory Pin Assignments Schematic Signal Names and Functions Schematic Stratix V GX Pin 1 Description Standard Signal Name Number PIN AV23 PIN AV25 AT24 AP24 PIN AL24 TR5 F40W User Manual 22 www terasic com ter AWW LET uU August 29 2014 www terasic com FSM A14 Address bus 2 5 V PIN AH24 FSM A15 Address bus 2 5 V PIN AG25 FSM A16 Address bus 2 5 V PIN AK24 FSM A17 Address bus 2 5 V PIN AM22 FSM A18 Address bus 2 5 V PIN AL25 FSM A19 Address bus 2 5 V PIN AT23 FSM A20 Address bus 2 5 V PIN AJ26 FSM 21 Address bus 2 5 V PIN AT26 FSM A22 Address bus 2 5 V PIN AR22 FSM A23 Address bus 2 5 V PIN AU24 FSM A24 Address bus 2 5 V PIN AR24 FSM A25 Address bus 2 5 V PIN AN22 FSM A26 Address bus 2 5 V PIN AR25 FSM DO Data bus 2 5 V PIN AJ24 FSM D1 Data bus 2 5 V PIN 27 FSM D2 Data bus 2 5 V PIN 27 FSM D3 Data bus 2 5 V PIN AG26 FSM D4 Data bus 2 5 V PIN AG24
35. the SDK files in users C C project e Create a C C project Include TERASIC PCIE h in the 32 bits project Copy TERASIC PCIE DLL TERASIC PCIEx64 DLL for 64 bits Windows to the folder where the project exe 1s located e Dynamically load TERASIC PCIE DLL TERASIC PCIEx64 for 64 bits Windows in C C project To load the DLL please refer to two examples below Call the SDK API to implement the desired application B TERASIC PCIE DLL TERASIC PCIEx64 DLL Software API asic TR5 F40W User Manual 92 www terasic com ter a LRL sas www August 29 2014 Using the TERASIC PCIE DLL TERASIC PCIEx64 DLL software API users can easily communicate with the FPGA through the PCIe bus The API details are described below PCIE ScanCard Function Lists the PCIe cards which matches the given vendor ID and device ID Set Both ID to zero to lists the entire PCIe card Prototype BOOL PCIE ScanCard WORD wVendorID WORD DWORD pdwDeviceNum PCIE CONFIG szConfigList Parameters w VendorID Specify the desired vendor ID A zero value means to ignore the vendor ID wDevicelD Specify the desired device ID A zero value means to ignore the produce ID pdwDeviceNum A buffer to retrieve the number of PCIe card which is matched by the desired vendor ID and product ID szConfigList A buffer to retrieve the device information of PCIe Card found which is matched by the de
36. 0 www terasic com Exit FPGA baord is connected e Click Download Image to download image raw data into the local memory of FPGA Click Process Image to trigger invert image process e Click Upload Image to upload image to PC from local memory of FPGA to be displayed on the window demo application asic TR5 F40W User Manual 94 www terasic com L www terasic August 29 2014 Terasic PCle Image Demo 1 0 124 51 www terasic com Select Image Download Image Process Image Upload image successfully B Design Tools e Quartus II 12 0 Borland Builder 6 0 B Demonstration Source Code Location Quartus Project PCIE ImageProcess e Borland C Project PCle SW ImageProcess B FPGA Application Design This demonstration uses the DMA channel of PCIe IP to download upload the image into the internal RAM of FPGA and controls the user register that switches the function which inverts the image data from the internal RAM B PC Application Design The software design defines some constant based on FPGA design as shown below TR5 F40W User Manual 95 www terasic com ter AWW LET uU asic August 29 2014 www terasic com define PCIE VID 1174 detine PCIE DID 1 Sdefine IMAGE WIDTH 320 define IMAGE HEIGH 240 1 DEMO PCIE USER BAR PCIE BAEI Sdefine DEMO IMAGE REG ADDR Dx iu
37. 0 132 HSMC RX p13 LVDS RX 13 10 LVDSorVCCIO E24 133 HSMC TX n13 LVDS TX 13n or CMOS LVDS or VCCIO F30 134 HSMC n13 LVDS RX bit 13n or CMOS LVDS or VCCIO E25 137 HSMC TX p14 LVDS TX 14 CMOSI O LVDSorVCCIO K31 138 HSMC p14 LVDS RX biti4or CMOSI O LVDSorVCCIO N30 139 TX n14 LVDS TX bit 14n CMOS I O LVDSorVCCIO 31 140 n14 LVDS bit 14n or CMOS I O LVDS or VCCIO M30 143 HSMC TX 15 LVDS TX bit 15 or CMOSI O LVDSorVCCIO U31 144 HSMC p15 LVDS bit 15 or LVDSorVCCIO PIN G24 145 TX n15 LVDS TX 15n or CMOS I O LVDSorVCCIO 131 146 n15 LVDS RX bit 15n or CMOS LVDS or VCCIO F24 149 HSMC TX p16 LVDS TX 16 or CMOSI O LVDSor VCCIO 33 150 HSMC RX p16 LVDS bit 16 CMOSI O LVDSor VCCIO E30 151 TX n16 LVDS TX 16n or CMOS 1 0 or VCCIO PIN M33 152 HSMC n16 LVDS RX bit 16n or CMOS LVDS or VCCIO E31 155 CLKOUT p2 95 TX or CMOS or LVDS or VCCIO PIN P34 differential clock input output 156 HsMC CLKIN p2 DS RX or CMOS I O or LVDS or VCCIO PIN R32 differential clock input 157 HsMC CLKOUT 05 TX or CMOS V O or LVDS or VCCIO PIN N34 differential clock input output 158 CLKIN n2 LWPS RX or CMOS V O or LVDS or V
38. 0W User Manual 66 www terasic com www teraSic com August 29 2014 ANU RYAN B Demonstration Source Code Project directory 51570 Demonstration e Bit stream used 51570 Demonstration sof e Demonstration Batch File test ub2 bat e Demo Batch File Folder 51570 Demonstration Nemo batch The demo batch file folders include the following files e Batch File test ub2 bat e FPGA Configuration File 51570 Demonstration sof B Demonstration Setup Make sure Quartus II 1s installed on your PC e Connect the USB Blaster cable to the FGPA board and host PC Install the USB Blaster II driver if necessary According to Table 5 5 the output frequency is determined by setting the dip switch SWI2 0 Table 5 5 51570 Controller Frequency Setting SW 2 0 Setting 51570 Clock Frequency MHz 3 b000 100 3 b001 125 3 b010 156 25 3 b011 250 3 b100 312 25 3 b101 322 26 3 b110 644 53125 3 b111 100 e Power the FPGA board Execute the demo batch file 51570 Demonstration bat under the batch file folder 1570 DemonstrationNMemo batch Press BUTTONI can reconfigure the 51570 e Observe LED3 status TR5 F40W User Manual 67 www terasic com ter www terasic com August 29 2014 ANU RYA 5 3 Si570 and CDCM Programming Nios ll This demonstration shows how to use the Nios II processor to program both programmable oscillators 51570 and CDCM61004 on the FPGA board The demonstration also
39. 125 or 322 265625MHz from the 51570 Figure 5 1 shows the block diagram of 51570 device Users can modify the value of the three registers RFREQ HS DIV and NI to generate the desired output frequency TR5 F40W User Manual 56 www terasic com www terasic com August 29 2014 Voo GND fXTAL CLKOUT M HS DIV N1 b E RFREQ Frequency Control QE Control SDA Interface SCL Figure 5 1 Si570 Block diagram The output frequency is calculated using the following equation out Output Dividers HSDIVxN1 When 51570 is powered on the default output frequency is 100 MHz Users can program the output frequency through the I2C interface using the following procedure 6 Freeze the DCO bit 4 of Register 137 7 Write the new frequency configuration RFREQ HSDIV and 1 to Register 7 12 8 Unfreeze the DCO and assert the NewFreq bit bit 6 of Register 135 The I2C address of 51570 is zero and it supports fast mode operation whose transfer rate 1s up to 400 kbps Table 5 1 shows the register table for 1570 asic TR5 F40W User Manual 57 www terasic com www terasic com August 29 2014 Register Name 7 High Speed N1 Dividers 8 Reference Frequency 9 Reference Frequency 10 Reference Frequency 11 Reference Frequency 12 Reference Frequency 135 Reference Frequency 137 Reference Frequency Table 5 1 81570 Register Table Bit 7 HS DIV 2 0 Bit 6 Bit 5
40. 28 Programmable M Oscillator a SMA Clock I O PCI Express x8 Edge Connector FPGA Configure Mode Selection Switch 12V Fan Connector Figure 2 1 The FPGA Board Top ter Terasic TR5 F40W User Manual 9 www terasic com www terasic com Temperature Sensor Battery Holder Qee BS 124 m 5 88 age 1311 88 2 1211 E 6 11211 8 216 3 2 bu Im 3 5 E a 118 117 1 4812 1 30 oa 91 uz e 277 305 4 2 2 LI 2 EEE see gt TNR BS Scie R 1 Lp Factory User Load Selection Switch 537 2 RST Button PCI Express Lanes Switches Figure 2 2 The FPGA Board Bottom 2 2 Configuration Status and Setup B Configure The FPGA board supports two configuration methods for the Stratix V FPGA e Configure the FPGA using the on board USB Blaster II e Flash memory configuration of the FPGA using stored images from the flash memory on power up For programming via on board USB Blaster II the following procedures show how to download a configuration bit stream into the Stratix V GX FPGA sure that power is provided to the FPGA board e Connect your PC to th
41. 5 9 e For programming PLL 51570 test please input key 2 and press Enter in the nios terminal first then select the desired output frequency as shown in Figure 5 10 asic TR5 F40W User Manual 70 www terasic com ter www terasic com August 29 2014 Altera Nios II EDS 12 0 gcc4 Stratix U Demo Program Temperature Li 1 4 2 51570 nput your chioce 4 ocal Temperature 33 emote Temperature 45 emperature Test PASS Stratix U Demo Program 1 Temperature i 4 2 1578 Input your chioce Figure 5 8 Temperature Demo Em Altera Nios II EDS 12 0 gcc4 Stratix U Demo Program 1 Temperature 11 CDCH618H84 21 51570 Input your chioce 1 62 580 MHz 75 MHz 166 660 MHz 125 860 MHz 158 868 MHz 156 258 MHz 187 59 MHz 200 MHz 250 000 MHz 312 568 MHz 525 MHz Test Result SATA ref clock test PASS lt 1 1 998 clk2 12473 gt 5 DCMN61604 Test PASS Stratix U Demo Program 9 Temperature 11 1 21 51570 Input your chioce Figure 5 9 CDCM 61004 Demo TR5 F40W User Manual 71 www terasic com www terasic com August 29 2014 E Altera Nios I EDS 120 gcc4 Stratix U Demo Program A Temperature 1 CDCHM61HBB4 2 51570 Input your chioce 2 51578 Programming 166 666666 MHz 125 MHz 156 250000 MHz 258 6060 MHz 312 586666 MHz 322 265625 MHz 644 53125H MHz Othe
42. 5 F40W development board 18 part of the shared FMS Bus which connects to flash memory SSRAM and the MAX II CPLD EEPM2210 System Controller Table 2 13 lists the SSRAM pin assignments signal names relative to the Stratix V GX device in respectively Table 2 13 SSRAM Pin Assignments Schematic Signal Names and Functions Schematic EE Stratix V GX Pin Description Standard Signal Name Number FSM AO Address bus 2 5 V PIN AW22 FSM A1 Address bus 2 5 V PIN AV23 FSM A2 Address bus 2 5 V PIN AV25 FSM A3 Address bus 2 5 V PIN AT24 FSM A4 Address bus 2 5 V PIN 23 FSM A5 Address bus 2 5 V PIN AW23 FSM A6 Address bus 2 5 V PIN AU23 FSM A7 Address bus 2 5 V PIN AP24 FSM A8 Address bus 2 5 V PIN AM25 FSM A9 Address bus 2 5 V PIN AM26 FSM A10 Address bus 2 5 V PIN AP25 FSM A11 Address bus 2 5 V PIN AP22 FSM A12 Address bus 2 5 V PIN AL24 FSM A13 Address bus 2 5 V PIN 23 FSM A14 Address bus 2 5 V PIN AH24 FSM A15 Address bus 2 5 V PIN AG25 Tasic TR5 F40W User Manual 24 www terasic com www terasic com August 29 2014 Addressbus 254 PINAKM FSM A17 Addressbus 25V Addressbus 25V __ PINAR2 Addressbus 25V PINAUM Addressbus 25V PINAN2 Address bus 25V PINARS Databus 1 11 25V PINAG2 Databus 25V PINAG2 Databus 2257 FSM D7 Daabus 25 PINAF28
43. 8 15 HSMC GXB TX n4 Transceiver TX bit 1 4 V PCML PIN E37 16 HSMC GXB n4 Transceiver bit 1 4 V PCML PIN F39 17 HSMC GXB TX Transceiver TX bit 1 4 V PCML PIN G36 18 HSMC GXB Transceiver bit 3 1 4 V PCML PIN H38 19 HSMC GXB TX n3 TX bit 1 4 V PCML PIN G37 20 HSMC GXB RX n3 Transceiver RX bit 3n 1 4 V PCML PIN H39 21 HSMC GXB TX p2 Transceiver TX bit 2 1 4 V PCML PIN J36 22 HSMC GXB 2 Transceiver bit 2 1 4 V PCML PIN K38 23 HSMC GXB TX n2 Transceiver TX bit 2n 1 4 V PCML PIN J37 24 HSMC GXB RX n2 Transceiver RX bit 2n 1 4 V PCML PIN K39 25 HSMC GXB TX Transceiver TX bit 1 1 4 V PCML PIN L36 26 HSMC GXB Transceiver bit 1 1 4 V PCML PIN M38 27 HSMC GXB TX n1 Transceiver TX bit 1n 1 4 V PCML PIN L37 28 HSMC GXB n1 Transceiver RX bit 1n 1 4 V PCML PIN M39 29 HSMC GXB TX pO Transceiver TX bit 0 1 4 V PCML PIN N36 30 HSMC GXB pO Transceiver bit 0 1 4 V PCML PIN P38 31 HSMC GXB TX nO Transceiver TX bit On 1 4 V PCML PIN N37 32 HSMC GXB RX nO Transceiver RX bit On 1 4 V PCML PIN P39 33 E HSMC SDA Management serial data 3 3 V PIN G27 34 E HSMC SCL Management serial clock 3 3 V PIN F27 35 HSMC JTAG TCK JTAG clock signal 2 5 V 36 HSMC JTAG TMS JTAG mode select signal 2 5 V 37 HSMC JTAG TDO JTAG data output 2 5 V 38 HSMC JTAG TDI JTAG data input 2 5 V 39 HSMC CLKOUTO CMOS I O VCCIO PIN 025 40 HSMC_C
44. CCIO PIN P32 differential clock input Note for Table 2 22 signals HSMC SDA and E 5 SCL are level shifted from 3 3V HSMC to VCCIO HSMC FPGA www terasic com August 29 2014 TR5 F40W User Manual 41 www terasic com Chapter 3 System Builder This chapter describes how users can create a custom design project on the FPGA board by using the Software Tools System Builder 3 1 Introduction The System Builder is a Windows based software utility designed to assist users to create a Quartus II project for the FPGA board within minutes The generated Quartus II project files include Quartus II Project File qpf Quartus II Setting File qsf Top Level Design File v e External PLL Controller v Synopsis Design Constraints file sdc Pin Assignment Document htm The System Builder not only can generate the files above but can also provide error checking rules to handle situation that are prone to errors The common mistakes that users encounter are the following Board damaged for wrong pin bank voltage assignment Board malfunction caused by wrong device connections or missing pin counts for connected ends Performance dropped because of improper pin assignments asic TR5 F40W User Manual 42 www terasic com ter a www terasic com August 29 2014 ANU RYAN 3 2 General Design Flow This section will introduce the general design
45. CML PIN AP1 SFPC LOS Signal loss indicator 2 5V PIN AK12 SFPC MODO PRSNT Module present 2 5V PIN AH9 SFPC MOD1 SCL Serial 2 wire clock 2 5V PIN AH10 SFPC MOD2 SDA Serial 2 wire data 2 5V PIN AG9 SFPC RATESELO Rate select 0 2 5V PIN AJ10 SFPC RATESEL1 Rate select 1 2 5V PIN AL12 SFPC TXDISABLE Turns off and disables the transmitter 2 AG12 output SFPC TXFAULT Transmitter fault 2 5V PIN AF11 Table 2 17 SFP D Pin Assignments Schematic Signal Names and Functions Schematic M Stratix V GX 1 Description Standard _ Signal Name Pin Number SFPD TX p Transmitter data 1 4 V PCML PIN SFPD_TX_n Transmitter data 1 4 V PCML PIN SFPD_RX_p Receiver data 1 4 V PCML PIN_AV2 SFPD n Receiver data 1 4 V PCML AV1 SFPD LOS Signal loss indicator 2 5V PIN AV11 SFPD MODO PRSNT n Module present 2 5V PIN AU10 SFPD MOD1 SCL Serial 2 wire clock 2 5V PIN AU9 SFPD MOD2 SDA Serial 2 wire data 2 5V PIN AT9 Tasic TR5 F40W User Manual 28 www terasic com www terasic com August 29 2014 ANU RYAN SFPD RATESELO Rate select 0 2 5V AU11 SFPD RATESEL1 Rate select 1 2 5V PIN AW11 SFPD TXDISABLE Turns off and disables the transmitter 2 PIN AT11 output SFPD TXFAULT Transmitter fault 2 5V PIN AR9 2 10 PCI Express The FPGA development board is designed to fit entirely into a PC motherboard with x8 or x16 PCT Express slot Utilizing built in transceivers on a Stratix V GX device it 1s able to pr
46. D There folder contains five files as shown in Table 4 2 Table 4 2 Flash Memory Map Byte Address Files Name Description S5 PFL sof Parallel Flash Loader Design flash program ub2 bat Top batch file to download S5 PFL sof and launch batch flash program bashrc ub2 flash program bashrc ub2 Translate sof and into flash and programming flash with the generated flash file Golden top sof Hardware design file for Hello Demo HELLO NIOS elf Software design file for Hello Demo To apply the batch file to users sof and elf file users can change the sof and elf filename in the TRS F40W User Manual 92 NP MIS RAD www terasic com August 29 2014 ANU RYAN flash program bashrc ub2 file as shown in Figure 4 1 2 inprtGolden_top sof gt output f lash_hw flash offget O0x20C0000 pfl elf flash end UxQFFFFFFF reset x 4940000 input HELLO NOs el Figure 4 1 Change to users sof and elf filename If your design does not contain a NIOS II processor users can add to the beginning of the line to comment disable the elf2flash and nios flash programmer commands the flash program bashrc ub2 file in Figure 4 2 4 fconver to flazh KIT NIOS2 niogz2 command zhell sh gof2flagh input Golden top zof output flazh hw KIT NIOS2 nios2 command shell sh elf2flagh base x end x FFFFFFF reset 0x049 Frogramming w
47. D15 Loading D18 PAGE B Setup HSMC I O voltage The FPGA I O standards of the HSMC ports can be adjusted by configuring the header position J3 Each port can be individually adjusted to 1 5V 1 8V 2 5V via jumpers on the top right Figure 2 3 depicts the position of the jumpers and their associated I O standards Users can use 2 pin jumpers to configure the I O standard by choosing the associated positions on the header Please refer to Table 2 2 for more details Note removing or mounting all of the jumpers will force an output of 1 5V and will incur the risk of damaging your FPGA asic TR5 F40W User Manual 11 www terasic com ter a www terasic com August 29 2014 111114 ee gt gt o uonisog UOIISOd 1 5V 1 8V 2 5V 1 5V Figure 2 3 I O Configuration Header Table 2 2 HSMC IO Standard Select Board Signal Description Default Reference HSMC VCCIO 1 5V Short Select VCCIO 1 5V output Open 03 3 3 4 HSMC 1 8V Short Select VCCIO 1 8V output Open 8 5 36 HSMC VCCIO 25V Short Select VCCIO 2 5V output Short 937 438 HSMC 1 5V Short Select VCCIO 1 5V output Open B Setup PCI Express Control DIP switch The PCI Express Control DIP switch SW8 is provided to enable or disable different configurations of the PCIe Connector Table 2 3 lists the switch controls and description Table 2 3 SW8 PC
48. DMARD RDVALID I 2 clock cycles oFIFO MEM SEL 1 1 I 1 1 High Level Figure 6 6 Read transaction waveform of the PCle DMA channel on FIFO link mode 1 2 3 2 5 6 7 8 9 N V NY NV NV NY NY oDMAWR_ADDR gt lt FIFO ID l 1 oDMAWR DATA K X X Di X D2 X 03 X 04 2 oDMAWR WRITE E N oFIFO MEM SEL Figure 6 7 Write transaction waveform of the PCle DMA channel on FIFO link mode 6 3 PC PCI Express System Design The FPGA System CD contains a PC Windows based SDK to allow users to develop their 32 bits software application on Windows 7 Window XP 32 64 bits The SDK is located in the CDROM demonstrations PCle SW folder which includes PCI Express Driver e PCI Express Library PCI Express Examples TRS F40W User Manual 78 ETE www terasic com August 29 2014 ANU S RYAN The kernel mode driver requires users to modify the PCIe vender ID VID and device ID DID in the driver INF file to match the design in the FPGA where Windows searches for the associated driver The PCI Express Library is implemented as a single DLL called TERASIC PCIE DLL TERASIC PCIEx64 DLL for 64 bits Windows With the DLL exported to the software API users can easily communicate with the FPGA The library provides the following functions Device Scanning on Bus e Bas
49. E ADDRESS PcieAddress DWORD pdwData Parameters hPCIE A PCIe handle return by PCIE Open function PcieBar Specify the target BAR PcieAddress Specify the target address in FPGA pdwData A buffer to retrieve the 32 bits data Return Value Return TRUE if read data 1s successful otherwise FALSE 18 returned PCIE_Write32 Function Write a 32 bits data to the FPGA Board Prototype bool PCIE_Write32 PCIE HANDLE hPCIE PCIE BAR PcieBar PCIE ADDRESS PcieAddress DWORD dwData Parameters hPCIE A PCIe handle return by PCIE Open function PcieBar Specify the target BAR PcieAddress Specify the target address in FPGA dwData Specify a 32 bits data which will be written to FPGA board asic TR5 F40W User Manual 85 www terasic com www terasic com August 29 2014 Return TRUE if write data is successful otherwise FALSE 1s returned PCIE DmaRead Function Read data from the memory mapped memory of FPGA board in DMA function Prototype bool PCIE DmaRead PCIE HANDLE hPCIE PCIE LOCAL ADDRESS LocalAddress void pBuffer DWORD dwBufSize Parameters hPCIE A PCIe handle return by PCIE Open function LocalAddress Specify the target memory mapped address in FPGA pBuffer A pointer to a memory buffer to retrieved the data from FPGA The size of buffer should be equal or larger the dwBufSize dwButSize Specify the byte number of data retrieved from FPGA Return Value Ret
50. EFCLK p n 61004 SFP1G_REFCLK_pin 150 00 MHz Prefix Name HSMC_REFCLK_pin DCC High Speed ADC DAC M y www terasic com TR5 F40W User Manual 45 Default Setting Load Setting Save Setting Figure 3 3 Quartus Project Name www teraSic com August 29 2014 ANU RYA B System Configuration Under System Configuration users are given the flexibility of enabling their choice of components on the FPGA as shown in Figure 3 4 Each component of the FPGA board is listed where users can enable or disable a component according to their design by simply marking a check or removing the check in the field provided If the component is enabled the System Builder will automatically generate the associated pin assignments including the pin name pin location pin direction and I O standards Note The pin assignments for some components e g SFP require associated controller codes in the Quartus project otherwise Quartus will result in compilation errors Therefore do not select them if they are not necessary in your design Terasic TRSFAOW V1 0 0 me System Configuration Project Name TR5F40W CLOCK Switch x 4 LED x 10 Button x 4 Fan Control Temperature Flash 256MB SSRAM RS 422 VISMA SFP A SFP D Sata Host Sata Device PCIe lt S 11
51. Ie Control DIP Switch Board ee Signal Name Description Default Reference On Enable x1 presence detect PRSNT2n x1 PCIE PRSNTIN x1 Off Disable x1 presence detect on On Enable x4 presence detect PCIE PRSNT2n x4 Off Disable x4 presence detect on On Enable x8 presence detect PCIE_PRSNT2 Swe3 PCIE PRSNT2n x8 Off Disable x8 presence detect on asic TR5 F40W User Manual 12 www terasic com ter www terasic com August 29 2014 ANU RYA B Setup Configure Mode Control DIP switch The Configure Mode Control DIP switch SW7 is provided to specify the configuration mode of the FPGA Because currently only one mode is supported please set all positions as shown in Figure 2 4 MSEL 0 4 2 ON Figure 2 4 6 Position DIP switch for Configure Mode B Select Flash Image for Configuration The Image Select DIP switch SW5 is provided to specify the image for configuration of the FPGA Setting SW5 to the top specifies the default factory image to be loaded as shown in Figure 2 5 Setting SW5 to low specifies the TR5 F40W to load a user defined image as shown in Figure 2 6 lt sa 84 O O lt LL Figure 2 5 DIP switch for Image Select Factory Image Load TR5 F40W User Manual 13 www terasic com ter WWW LET uU asic August 29 2014 www terasic com ON FACTORY_LOAD AN Figure 2 6 DIP switch for Ima
52. LKINO Dedicated clock input VCCIO PIN N32 41 HSMC_DO LVDS TX or CMOS I O LVDS or VCCIO PIN N20 42 5 01 LVDS RX or CMOS I O LVDS or VCCIO PIN K22 43 HSMC 02 LVDS TX or CMOS I O LVDS or VCCIO N21 44 HSMC_D3 LVDS or CMOS I O LVDS or VCCIO PIN J22 47 HSMC TX pO LVDS TX bit 0 or CMOS I O LVDS or VCCIO PIN M20 WWW terasic com August 29 2014 TR5 F40W User Manual 39 www terasic com 48 49 50 53 54 55 56 59 60 61 62 65 66 67 68 71 72 73 74 77 78 79 80 83 84 85 86 89 90 91 92 95 96 97 98 101 102 103 104 107 108 HSMC RX HSMC TX nO HSMC RX nO HSMC TX p1 HSMC HSMC TX HSMC ni HSMC TX p2 HSMC RX p2 HSMC TX n2 HSMC RX n2 HSMC TX p3 HSMC RX p3 HSMC TX n3 HSMC RX n3 HSMC TX p4 HSMC RX p4 HSMC TX n4 HSMC RX n4 HSMC TX p5 HSMC RX p5 HSMC TX n5 HSMC RX n5 HSMC TX p6 HSMC RX p6 HSMC TX n6 HSMC RX n6 HSMC TX p7 HSMC RX p7 HSMC TX n7 HSMC RX n7 HSMC OUT 1 HSMC CLKIN p1 HSMC OUT n1 HSMC CLKIN n1 HSMC TX p8 HSMC RX p8 HSMC TX n8 HSMC RX n8 HSMC TX p9 HSMC RX p9 LVDS RX bit 0 or CMOS I O LVDS TX bit On or CMOS I O LVDS RX bit On or CMOS I O LVDS TX bit 1 or CMOS I O LVDS RX bit 1 or CMOS I O LVDS TX bit 1n or CMOS I O LVDS RX bit 1n or CMOS I O LVDS TX bit 2 or CMOS I O LVDS RX bit 2 or CMOS I O LVDS TX bit 2n or CMOS LVDS RX bit 2n or CMOS I O LVDS TX bit 3 or CMOS I O LVDS RX bit 3 or CMOS I O LVDS TX bit or CMOS
53. NE CARD scceccececcsscscccceccesseccscececcnsosccecescescesasceecescnscssaecescessesascsececcesessascess 34 CHAPTER 3 ip 46 01 5 7 4 42 CN M UN PROC 42 3 2 GENERAL DESIGN FLOW ENT 43 Jo USING SYSTEM BUILDER 44 4 FLASH PROGRAMMING cccccccccccccccccsccccsscccccsscccccsccccccscccccccccccccsccccccccccccscccccccccccccccccccccccccsccccsees 51 4 1 CFLFLASH MEMORY 51 4 2 PPGA CONFIGURE 52 4 3 FLASH PROGRAMMING WITH USERS DESIGN 52 RESTORE FACTORY SETTINGS EI ETE EE 54 5 PROGRAMMABLE OSCILLA T OR e Lecce Lecce eee eee eee e eese 56 m rT 56 SADOT EXAMPLE Mc T 60 TR5 F40W User Manual 2 www terasic com ter www terasic com August 29 2014 ANU RYAN 5 3 51570 AND CDCM PROGRAMMING 8 0 400 0000 000000010003 68 CHAPTER 6 PCI EXPRESS REFERENCE
54. ON Figure 2 20 JTAG Chain Enabled for HSMC Daughter Card Daughter Card TR5 F40W Board and signals Bypassed TDI 100 gt TDI TDO 4 ATERA HSMC SW6 OFF ON ON ON Figure 2 21 JTAG Chain Bypassed for HSMC Daughter Card Table 2 22 Pin Assignments Schematic Signal Names and Functions HSMC Schematic Signal Stratix V GX 1 Description Standard Pin Pin Number 1 Transceiver TX bit 7 1 4 V PCML PIN 836 2 HSMC GXB 7 Transceiver RX bit 7 1 4 V PCML PIN T38 TR5 F40W User Manual 38 www terasic com ter WWW LET uU asic August 29 2014 www terasic com 3 HSMC GXB TX n7 TX bit 7n 1 4 V PCML PIN R37 4 HSMC GXB n7 Transceiver RX bit 7n 1 4 V PCML PIN T39 5 HSMC GXB TX Transceiver TX bit 6 1 4 V PCML PIN W36 6 HSMC GXB RX p6 Transceiver RX bit 6 1 4 V PCML PIN Y38 7 HSMC GXB TX n6 Transceiver TX bit 6n 1 4 V PCML PIN W37 8 HSMC RX n6 Transceiver RX bit 6n 1 4 V PCML PIN Y39 9 HSMC GXB TX p5 Transceiver TX bit 5 1 4 V PCML PIN C36 10 HSMC GXB Transceiver RX bit 5 1 4 V PCML PIN D38 11 HSMC GXB TX n5 Transceiver RX bit 5n 1 4 V PCML PIN C37 12 HSMC GXB RX n5 Transceiver RX bit 5n 1 4 V PCML PIN D39 13 HSMC GXB TX p4 Transceiver TX bit 4 1 4 V PCML PIN E36 14 HSMC GXB Transceiver RX bit 4 1 4 V PCML PIN F3
55. asic August 29 2014 www terasic com _ SATA DEVICE RX n P 3 SATA HOST TX n SATA HOST RX SATA DEVICE TX SATA DEVICE TX n c x 9 2 lt lt Qo SATA HOST TX SATA DEVICE RX SATA HOST SATA DEVICE Figure 2 16 4 Pin connection between SATA connectors Table 2 19 Serial ATA Pin Assignments Schematic Signal Names and Functions Schematic m Stratix V GX Pin Description Standard Signal Name Number SATA REFCLK p Reference Clock HCSL PIN V6 SATA REFCLK n Reference Clock HCSL PIN V5 Device Differential receive data input ATA DEVICE RX 1 4 V PCML PIN P2 SAIA 0 after DC blocking capacitor M SATA DEVICE Differential receive data input bom PIN P1 after DC blocking capacitor SATA DEVICE no Differential transmit data output 1 v PIN 4 before DC blocking capacitor SATA DEVICE TX pO Differential data output 1 4 V PCML before DC blocking capacitor Host Diff ial SATA HOST TX GS OH 2271 PIN K2 before DC blocking capacitor SATA HOST TX n0 Differential transmi data output 14 V PCML PIN before DC blocking capacitor SATA HOST RX Differential data input 14 V PCML after DC blocking capacitor SATA HOST RX Differential data 14 V PCML J3 after DC blocking capacitor
56. bus 1 4 V PCML PIN AP38 PCIE RX n2 Add in card receive bus 1 4 V PCML PIN AP39 PCIE RX p3 Add in card receive bus 1 4 V PCML PIN 38 www terasic com August 29 2014 TR5 F40W User Manual 30 www terasic com PCIE RX n3 Add in card receive bus 1 4 V PCML PIN AM39 PCIE RX p4 Add in card receive bus 1 4 V PCML PIN 8 PCIE RX n4 Add in card receive bus 1 4 V PCML PIN 9 PCIE RX p5 Add in card receive bus 1 4 V PCML PIN AF38 PCIE RX n5 Add in card receive bus 1 4 V PCML PIN AF39 PCIE RX p6 Add in card receive bus 1 4 V PCML PIN AD38 PCIE RX n6 Add in card receive bus 1 4 V PCML PIN AD39 PCIE RX p7 Add in card receive bus 1 4 V PCML PIN AB38 PCIE RX n7 Add in card receive bus 1 4 V PCML PIN AB39 PCIE REFCLK p Motherboard reference clock HCSL PIN AF34 PCIE REFCLK n Motherboard reference clock HCSL PIN AF35 PCIE PERST n Reset 2 5 V PIN AC28 PCIE SMBCLK SMB clock 2 5 V PIN AF28 PCIE SMBDAT SMB data 2 5 V PIN AB28 PCIE WAKE n Wake signal 2 5 V PIN AE29 PRSNT1n Hot plug detect Hot plug detect x1 PCle slot enabled using SW8 dip switch Hot plug detect x4 PCle slot enabled using SW8 dip switch Hot plug detect x8 PCle slot enabled using SW8 dip switch PCIE PRSNT2n x1 PCIE PRSNT2n x4 PCIE PRSNT2n x8 2 11 SATA Two Serial ATA SATA ports are available on the FPGA development board which are computer bus standard with a primary function of transferring data between the motherboard and mass storage devices
57. called m hPCIE DmaRead DEMO IMAGE ADDR plImage nlImagesizel TRS F40W User Manual 97 ETE www terasic com August 29 2014 Additional Information Getting Help Here are the addresses where you can get help if you encounter problems e Terasic Technologies 9F No 176 Sec 2 Gongdao 5th Rd East Dist HsinChu City 30070 Taiwan 30070 Email support terasic com Web www terasic com TR5 F40W Web TR5 F40W terasic com Revision History Date Version Change 2012 7 First publication pe 201211 V1 01 Update 51570 Parameter 2014 08 V1 1 Update section 5 2 for modifying si570 function TR5 F40W User Manual 98 www terasic com ter WWW Lot asic August 29 2014 www terasic com
58. connector e Support for PCIe 1 2 3 e Edge connector for PC motherboard with x8 or x16 PCI Express slot Power Source e PCI Express 6 pin DC 12V power e PCI Express edge connector power TR5 F40W User Manual 8 ter www terasic com www terasic com August 29 2014 Chapter 2 Board Components This chapter introduces all the important components on the TR5 F40W 2 1 Board Overview Figure 2 1 is the top and bottom view of the TR5 F40W development board It depicts the layout of the board and indicates the location of the connectors and key components Users can refer to this figure for relative location of the connectors and key components SATA SATA HSMC 4 User HSMC JTAG HSMC Voltage Device Port Host Port CPU RST Button Connectors Push Buttons Switch Setting Jumper 4 User LEDs we m 4 User Switches e 12V Power Display LEDs e tt Supply Connector RS422 n Hi crc X feo RJ45 51570 y USB Blaster II Programmable EEES Fad To i Oscillator pmo 256MB Flash SOME gb 5 UI Altera Stratix V GX pu 5SGXEA3K2F40C3 4 SFP Ports 3 O cmon eee E EN T Zu Ies nudi JTAG Header ri ic 500 Ow Sete CDCM 61004 aoe
59. e FPGA board using a mini USB cable and make sure the USB Blaster II driver is installed on your PC e Launch Quartus II programmer and make sure the USB Blaster II 15 detected e In Quartus II Programmer add the configuration bit stream file sof check the associated TR5 F40W User Manual 10 www ter LL www terasic August 29 2014 ANU RYA Program Configure item and click Start to start FPGA programming B Status LED The FPGA Board development board includes board specific status LEDs to indicate board status Please refer to Table 2 1 for the description of the LED indicator Table 2 1 Status LED Board LED Name Description Reference D7 12 V Power illuminates when 12 V power is active D6 3 3 V Power Illuminates when 3 3 V power is active 1 5 V no Illuminates D25 HSMC Power 1 8 V Green 2 5 V Red Default Illuminates when the FPGA is successfully configured Driven by the MAX II CPLD EPM2210 System Controller Illuminates when the MAX II CPLD EPM2210 System Controller is actively configuring the FPGA Driven by the Il CPLD EPM2210 System Controller with the Embedded Blaster CPLD when the MAX II CPLD EPM2210 System D17 Error Controller fails to configure the FPGA Driven by the MAX CPLD EPM2210 System Controller Illuminates when FPGA is configured by the factory configuration bit stream D19 CONF DONE
60. econds to install the driver When installation is complete the following dialog window will popup shown in Figure 6 10 Click OK and then Exit to close the installation program Terasic PCle Driver Installer Information Congratulations The PCIe driver has installed successfully Figure 6 10 PCle driver installed successfully 5 Once the driver is successfully installed users can view the device under the device manager window shown in Figure 6 11 TR5 F40W User Manual 81 www terasic com ter WWW LET uU asic August 29 2014 www terasic com Device Manager File Acton View Help B Computer E a Disk drives E E Display adapters 9 8 9 Human Interface Devices IDE Mice and other pointing devices d Monitors m Bg Network adapters H i Ports amp LPT Processors m Sound video and game controllers H System devices Universal Serial Bus controllers Figure 6 11 Device Manager B Create a Software Application necessary files to create a PCIe software application are located the CDROM demonstration P Cle_SW_KII PCle_Library which includes the following files TERASIC PCIE h e TERASIC PCIE DLL for 32 bits Windows TERASIC PCIEx64 DLL for 64 bits Windows e wdapi921 dll for 32 bits Windows wdapil100 dll for 64 bits Windows Below lists the procedures to use
61. edded memory 36 transceivers 12 5Gbps asic TR5 F40W User Manual 6 www terasic com 14 www terasic com August 29 2014 JA DTE RYAN e 512 18 bit x 18 bit multipliers 256 27 bit x 27 bit DSP blocks 2 PCI Express hard IP blocks 696 user I Os e 174 full duplex LVDS channels 24 phase locked loops PLLs JTAG Header and FPGA Configuration e On board USB Blaster II or JTAG header for use with the Quartus II Programmer e MAXII CPLD EPM2210 System Controller and Fast Passive Parallel FPP configuration Memory devices 2MB SSRAM 256MB FLASH General user I O 10 user controllable LEDs e 4 user push buttons e 4 user slide switches On Board Clock 50MHz oscillator e Programmable oscillators providing clock for 10G SFP transceiver e Programmable oscillators providing clock for SATA HSMC and SFP transceiver connector for external clock output SMA connector for external clock input HSMC Connector TR5 F40W User Manual 7 www terasic com www terasic com August 29 2014 JA DTE RYAN e Total of 8 pairs transceivers at data rate up to 12 5Gbps e Total of 18 LVDS channels also can be configured as single end signals e Input and output clock JTAG Signals e Adjustable I O voltage 1 5V 1 8V 2 5V Two Serial ATA ports SATA 3 0 standard at 6Gbps signaling rate Four SFP ports Four SFP connector 10 Gbps PCI Express x8 edge
62. flash uas Reset vector offset 04540000 Reset vector 0 04940000 Figure 4 4 Reset Vector Settings for NIOS Il Processor For implementation detail users can refer the Hello example located in the CD folder Demonstrations Hello 4 4 Restore Factory Settings This section describes how to restore the original factory contents to the flash memory device on the FPGA development board Perform the following instructions 1 Make sure the Nios II EDS and USB Blaster II driver are installed 2 Make sure the FPGA board and PC are connected with an UBS Cable TR5 F40W User Manual 54 www terasic com www terasic com August 29 2014 ANU RYAN 3 Power on the FPGA board Copy the Demonstrations PFI flash programming batch folder under the CD to your PC s local drive Execute the batch file flash program ub2 bat to start flash programming Power off the FPGA Board Set FPGA configure mode as FPPx32 Mode by setting SW7 MSEL 0 4 to 00010 Specify configuration of the FPGA to Factory Hardware by setting the FACTORY LOAD dip in SWS to the upper position 9 Power on the FPGA Board and the Configure Done LED should light A Ke ub xe Except for programming the Flash with the default code PFL the batch file also writes PFL Parallel Flash Loader Option Bits data into the address 0x30000 The option bits data specifies 0 20 0000 as start address of your hardware design The NIOS II EDS tool nios 2 flash
63. flow to build a project for the FPGA board via the System Builder The general design flow is illustrated in the Figure 3 1 Users should launch System Builder and create a new project according to their design requirements When users complete the settings the System Builder will generate two major files which include top level design file v and the Quartus II setting file qsf The top level design file contains top level Verilog wrapper for users to add their own design logic The Quartus II setting file contains information such as FPGA device type top level pin assignment and I O standard for each user defined I O pin Finally Quartus II programmer must be used to download SOF file to the FPGA board using JTAG interface TR5 F40W User Manual 43 www terasic com www terasic com August 29 2014 Figure 3 1 The general design flow of building a design 3 3 Using System Builder This section provides the detail procedures on how the System Builder is used B Install and launch the System Builder The System Builder is located in the directory Tools SystemBuilder in the System CD Users can copy the whole folder to a host computer without installing the utility Before using the System Builder execute the SystemBuilder exe on the host computer as appears in Figure 3 2 TR5 F40W User Manual 44 www terasic com ter WWW LET uU asic August 29 2014 www terasic com ANU S RYAN
64. g the flash Before programming users need to translate their Quartus sof and NIOS II elf files into the flash which is used by the TR5 F40W User Manual 5 www terasic com ter a www terasic com August 29 2014 nios 2 flash programmer For sof to flash translation NIOS II EDS tool sof2flsh can be used For the elf to flash translation NIOS II EDS tool elf2flash can be used For convenience the System CD contains a batch file for file translation and flash programming with users given sof and elf file 4 2 FPGA Configure Operation Here is the procedure to enable FPGA configuration from Flash 1 Please make sure the FPGA configuration data has been stored in the CFI flash Set the FPGA configuration mode to FPPx32 mode by setting SW7 MSEL 0 4 000100 3 Specify the configuration of the FPGA using the default Factory Configuration or User Configuration by setting SW according to Figure 4 1 4 Power on the FPGA board or press MAX button if board is already powered on 5 When configuration 1s completed the green Configure Done LED will light If there 1s error the red Configure Error LED will light 4 3 Flash Programming with Users Design Users can program the flash memory device so that a custom design loads from flash memory into the FPGA on power up For convenience the translation and programming batch files are available on the Demonstrations Hello flash programming batch folder in the System C
65. ge Select User Image Load B Select JTAG Chain DIP Switch Table 2 4 explains the configuration for SW6 SWO 1 enables disables the USB Blaster SW6 3 selects the JTAG chain A more detailed explanation can be found in Chapter 2 12 JTAG Chain on HSMC Table 2 4 SW6 JTAG Chain DIP Switch Board 1 Signal Name Description Default Reference On Disable On Board USB Blaster swea RAA Off Enable On Board USB Blaster 5962 o O Disable JTAG chain sus Off Enable HSMC JTAG chain on SW6 4 0800 TR5 F40W User Manual 14 www terasic com ter WWW LET uU asic August 29 2014 www terasic com Figure 2 7 SW6 4 Position JTAG Chain DIP Switch Settings 2 3 General User Input Output This section describes the user I O interface to the FPGA B User Defined Push buttons The FPGA board includes four user defined push buttons that allow users to interact with the Stratix V GX device Each push button provides a high logic level or a low logic level when it is not pressed or pressed respectively Table 2 5 lists the board references signal names and their corresponding Stratix V GX device pin numbers Table 2 5 Push button Pin Assignments Schematic Signal Names and Functions Board Schematic e VO Stratix V GX Description Reference Signal Name Standard Pin Number BUTTONO PIN C18 1 High Logic Level when the button is PIN B19
66. ic Data Read and Write Data Read and Write by DMA For high performance data transmission DMA is required as the read and write operations are specified under the hardware design on the FPGA B PCI Express Software Stack Figure 6 8 shows the software stack for the PCI Express application software on 32 bits Windows The PCI Express driver is incorporated in the DLL library called TERASIC PCIE dll Users can develop their application based on this DLL In 64 bits Windows TERASIC PCIE dll is replaced by TERASIC PCIEx64 dll and wdapi921 dll is replaced wdapi1100 dll asic TR5 F40W User Manual 79 www terasic com ter a www terasic com August 29 2014 Terasic PCIE dll wdapi921 dll Users Mode Kemel Mode TERASIC PCIE inf Third Party Jungo Drivers Figure 6 8 PCI Express Software Stack B Install PCI Express Driver To install the PCI Express driver execute the steps below 1 From the FPGA system CD locate the PCIe driver folder in the directory CDROM demonstrations PCle_ SW DriverInstall asic TR5 F40W User Manual 80 WWw terasic com ter www terasic com August 29 2014 2 Double click the PCIe DriverInstall exe executable file to launch the installation program shown in Figure 6 9 Teranc PC Te Driver Install ES Figure 6 9 PCle Driver Installation Program 3 Click Install to begin installation process It takes several s
67. ine Altera Stratix delivering the best system level integration and flexibility in the industry Stratix amp V GX FPGA features 340K logic elements and integrated transceivers that transfer at a maximum of 12 5 Gbps allowing TR5 F40W to be fully compliant with version 3 0 of SATA version 3 0 of the PCI Express standard as well as allowing an ultra low latency straight connections to four external 10G SFP modules Not relying on an external PHY will accelerate mainstream development of network applications enabling customers to deploy designs for a broad range of high speed connectivity applications An HSMC expansion port also allows users to connect custom daughter cards such as those found on cards terasic com The feature set of the TR5 F40W fully supports all high intensity applications such as low latency trading cloud computing high performance computing data acquisition network processing and signal processing 1 2 Key Features The following hardware is implemented on the TR5 F40W board e FPGA o Altera Stratix GX FPGA 5SGXEA3K2F40C3 TR5 F40W User Manual 4 www terasic com www terasic com August 29 2014 ANU RYAN FPGA Configuration o On Board USB Blaster II or JTAG header for FPGA programming o Fast passive parallel FPPx32 configuration via MAX II CPLD and flash memory General user input output o 10 LEDs o 4 push buttons o 4 slide switches On Board Clock
68. ith flazh4 KIT NIOS2 nios2 command zhell zh nios flagsh programmer 0 0 flash KIT NIOS2 niogs2 command shell niogZ flazh programmer 0 0 flash zw flazh Figure 4 2 Add to these lines to disable elf conversion and programming If your design includes a NIOS II processor and the NIOS II program is stored on external memory users must to perform the following items so the NIOS II program can boot from flash successfully 1 QSYS should include a Flash controller for the CFI Flash on the development board Please ensure that the base address of the controller is 0x00 as shown in Figure 4 3 2 In NIOS II processor options select FLASH as reset vector memory and specify 0x04940000 as reset vector as shown in Figure 4 4 TRS F40W User Manual 22 www terasic com August 29 2014 Hame Description Export Clock Base cpu Nios Il Processor clk Clock Input Sys 2 reset n Reset Input clk data_master Avalon Memory Mapped Master clk 0 instruction_master Avalon Memory Mapped Master clk jflag_debug_module_reset Reset Output clk jtag_debug_module Avalon Memory Mapped Slave clk 011400800 custom instruction master Custom Instruction Master E cfi flash atb bridge 0 clk reset Clock Input SYS clk Figure 4 3 Flash Controller Settings in QSYS M Reset Vector Reset vector memory ext
69. ith a specific frequency via I2C interface For demonstration the output clock is used to implement a counter where the MSB is used to drive an LED so the user can get the result from the frequency of the LED blinking We will also introduce the port declarations and associated parameter settings of this IP Figure 5 2 shows the block diagram of this demonstration TRS F40W User Manual 60 Rau www 5 August 29 2014 FPGA CLOCK SDA Si570 CLOCK SCL Controller 91570 SFP_REF CLK pin Heart Beat _ Figure 5 2 Block Diagram of this Demonstration LED3 B Block Diagrams of 51570 Controller IP The block diagram of the 51570 controller is shown on Figure 5 3 Shown here are four blocks named 12 reg controller 12 bus controller clock divider and initial config in 51570 controller IP Firstly the i2c reg controller will generate an associated 51570 register value for the 12 bus controller based on user desired frequency Once 12 bus controller receives this data it will transfer these settings to 1570 via serial clock and data bus using I2C protocol The registers in 1570 will be configured and output the user desired frequency Secondly the clock divider block will divide system clock 50 MHz into 97 6 KHz which is used as interface clock of 12 bus controller Finally the initial config block will generate a control signal to drive 12
70. ll TERASIC PCIEx64 DLL and wapil100 dll for 64 bits Windows Demo Batch File test bat B Demonstration Setup Install the FPGA board on your e Download the PCIE Fundamental sof into the FPGA board using Quartus Programmer Restart Windows Install PCIe driver if necessary The driver is located in the folder CDROMNdemonstration NPCle SW KITNPCIe DriverlInstall Launch the demo program PCIe Fundamental Demo exe shown in Figure 6 12 Select FPGA Board vip 1172n PID E001h 2 Refresh Register Read Write Button Register 0x04 7 LED Register 0x04 Custom Registers BUTTON 0 Hu Register Address 00 Register Value BUTTON 2 LED2 00 BUTTON 3 LEDS Read Read Status Set LED Write DMA Memory Mapped Write and Read FIFO Write and Read PCIE Board Connected Figure 6 12 TRS F40W User Manual 89 August 29 2014 www terasic com ANU S RYAN Make sure the Selected FPGA Board appear as the target board VID 1172 DID E001 e Press Button0 3 on the FPGA board and click the Read Status in this application software e Check Uncheck the LEDO 3 in this application software then click Set LED The LED 1n the FPGA board will change Click Memory Mapped Write and Read to test memory DMA A report dialog will appear when the DMA process is completed Click
71. lp Definition r Large Frequency Change Small Frequency Change Current Anchor Frequency What is the device s start up frequency What is the device s new fre 340 000000000 MHz 100 000000000 MHz 340 000000000 Total PPM Change from Anchor Frequency Apply Definition Create Example What is the amount in ppm to change the current frequency m 0 0000 Procedure Divider Combinations Summary Add PPM Subtract PPM Here are the device programming details for the new output Result Lo frequency 3 fl x HS DIV x N1 See the Divider Combinations tab for more options HS DIV 0x0 4 1 0 3 4 fdco f1 x HS DIV x N1 340 000000000 Miz x 4x 4 5 440000000 GHz 5 Calculate the new crystal frequency multiplication ratio RFREQ as RFREQ fdco fxtal Figure 5 5 Programmable Oscillator Calculator tool In addition if the user doesn t want 51570 controller to configure 51570 as soon as the FPGA configuration finishes users can change settings in 51570 controller v shown below initial config initial config JCLK CLK system clock 50mhz 1 5 system reset INITIAL START initial start AINITIAL_ENABLE 1 b1 Changing the setting from ENABLE 1 b1 to aAINITIAL_ENABLE 1 b0 will disable the initialization function of 1570 Controller B Design Tools e Quartus II 14 0 TR5 F4
72. nal Names and Functions Board Schematic VO Stratix V GX 1 Description Reference Signal Name Standard Pin Number DO LEDO 2 5 V PIN C16 D1 LED1 2 5 V PIN D18 D2 LED2 2 5 V PIN B16 D3 LED3 Driving a logic low on the I O port turns the 2 5 V PIN A16 D5 1 LED BRACKETO LED ON 2 5 V PIN E18 D5 3 LED BRACKET1 Driving a logic high on the port turns 2 5 V PIN E17 D5 5 LED BRACKET2 the LED OFF 2 5 V PIN E19 D5 7 LED BRACKETS 2 5 V PIN D16 J6 10 LED RJ45 L 2 5 V PIN M15 J6 12 LED RJ45 R 2 5 V PIN N15 2 4 Temperature Sensor and Fan Control The FPGA board is equipped with a temperature sensor MAX1619 which provides temperature sensing and over temperature alert These functions are accomplished by connecting the temperature sensor to the internal temperature sensing diode of the Stratix V GX device The temperature status and alarm threshold registers of the temperature sensor can be programmed by a two wire SMBus which is connected to the Stratix V GX FPGA In addition the 7 bit POR slave address for this sensor is set to 0011000b An optional 3 pin 12 fan located on 715 of the FPGA board is intended to reduce the temperature of the FPGA Users can control the fan to turn on off depending on the measured system temperature The FAN is turned on when the CTRL pin is driven to high logic level or tri state The pin assignments for the associated interface are listed in Table 2 8 Table 2 8 Temperature Sensor Pin As
73. o programming oscillators are low jitter oscillators which are used to provide special and high quality clock signals for high speed transceivers Figure 2 10 shows the TR5 F40W User Manual 18 www terasic com August 29 2014 ANU RYAN control circuits of programmable oscillators The CDCM61004 oscillator can be programmed to generate a desired reference clock for the 1G Ethernet SFP transceiver SATA Host Device transceiver and eight transceivers in the HSMC connector The 51570 programmable oscillator 18 programmed via an I2C serial interface to generate the reference clock for 10G Ethernet SFP transceiver CLOCK SCL CLK CE M gt CLK OS 1 0 e SMA CLOCK Stratix 1 V ODI2 0 9 RST n SH P Figure 2 10 Control Circuits of Programmable Oscillators Table 2 9 lists the clock source signal names default frequency and their corresponding Stratix V GX device pin numbers Table 2 9 Clock Source Signal Name Default Frequency Pin Assignments and Functions Schematic Default Stratix V GX 21077 1 Standard Application Signal Name Frequency Pin Number 2 5 V 29 0 2 5 V 2 0 2 5 V PINAL 2 5 V 7 2 5 V 2 5 V PIN 16 1 5 V 1 8 V 2 5 V 4 1 5 V 1 8 V 2 5 V TR5 F40W User Manual 19 WWW te
74. oard The full duplex LTC2855 is used to translate the RS422 signal and the RJ45 is used as an external connector for the RS422 signal asic TR5 F40W User Manual 20 www terasic com ter www terasic com August 29 2014 LTC2855 Voc RS422 RE n RS422 DE RS422 TE RS422 DIN RJ45 Connector Stratix V Gx Figure 2 11 Block Diagram of RS422 Table 2 11 lists the RS422 pin assignments signal names and functions Table 2 11 RS422 Pin Assignments Schematic Signal Names and Functions 27 Stratix V GX Pin Description Standard Number Driver Enable A high on DE enables the driver A low input will force the driver outputs into a high impedance state PINHi9 Driver Input The data is sent from FPGA Receiver Enable A low enables the receiver A high input forces the receiver output into a high impedance state Internal Termination Resistance Enable A high The development board has two I Gb CFI compatible synchronous flash devices for non volatile input will connect a termination resistor 1200 RS422 TE typical between pins A and B 2 7 FLASH Memory storage of FPGA configuration data user application data and user code space Each interface has a 16 bit data bus and the two devices combined allow for FPP x32 configuration This device 1 part of the shared flash SSRAM and MAX FSM bus which connects to the flash TRS F40W User Manual 21 www
75. ovide a fully integrated PCI Express compliant solution for multi lane 1 x4 and x8 applications With the PCI Express hard IP block incorporated in the Stratix V GX device it will allow users to implement simple and fast protocol as well as saving logic resources for logic application Figure 2 14 presents the pin connection established between the Stratix V GX and PCI Express The PCI Express interface supports complete PCI Express Genl at 2 5Gbps lane Gen2 at 5 0Gbps lane and Gen3 at 8 0Gbps lane protocol stack solution compliant to PCI Express base specification 3 0 that includes PHY MAC Data Link and transaction layer circuitry embedded in PCI Express hard IP blocks The power of the board can be sourced entirely from the PCI Express edge connector when installed into a PC motherboard It is strongly recommended that users connect the PCIe external power connector to 6 pin 12V DC power connector in the FPGA to avoid FPGA damage due to insufficient power The PCIE REFCLK p signal is a differential input that is driven from the PC motherboard on this board through the PCIe edge connector A DIP switch SW8 is connected to the PCI Express to allow different configurations to enable a x1 x4 or x8 PCIe Table 2 18 summarizes the PCI Express pin assignments of the signal names relative to the Stratix V GX FPGA asic TR5 F40W User Manual 29 www terasic com ter a www terasic com August 29 2014 PCIE REFCLK p PCIE REFCLK
76. ower Sleep Mode 2 5 V PIN AL29 2 9 SPF Ports The development board has four independent 10G SFP connectors that use one transceiver channel each from the Stratix V GX FPGA device These modules take in serial data from the Stratix V FPGA device and transform them to optical signals The board includes cage assemblies for the SFP connectors Figure 2 13 shows the connections between the SFP and Stratix V GX FPGA TR5 F40W User Manual 26 www terasic com ter a www terasic com August 29 2014 Stratix V Gx SFPA_TX_p SFPA TX n or penned Control amp Status SFPA_RX_n SFPB 517 Fannod Control amp Status SFPB_RX_p SFPB n 9 SFPC TX m SR C Connector Control amp Status SFPC RX p SFPC SFPD TX p SFPD TX n Control amp Status SFPD RX n Figure 2 13 Connection between the SFP and Stratix V GX FPGA Table 2 14 to Table 2 17 list the SFP A B C and D pin assignments and signal names relative to the Stratix V GX device Table 2 14 SFP A Pin Assignments Schematic Signal Names and Functions Schematic Stratix V GX 1 Description Standard _ Signal Name Pin Number SFPA TX p Transmitter data 1 4 V PCML PIN AA4 SFPA TX n Transmitter data 1 4 V PCML SFPA RX p 14 V PCML PIN AB2 SFPA LOS Signal loss indicator SFPA RX n 1 4 V PCML SFPA MODO PRSNT Module
77. programmer programs the Flash based on the Parallel Flasher Loader design in the FPGA The Parallel Flash Loader design is included in the default code PFL and the source code 1s available in the folder Demonstrations PFL in System CD TR5 F40W User Manual 55 www terasic com www terasic com August 29 2014 Chapter 5 Programmable Oscillator This chapter describes how to program the two programmable oscillators 51570 and CDCM61004 on the FPGA board Also RTL based and Nios based reference designs are explained in the chapter The source codes of these examples are all available on the FPGA System CD 5 1 Overview This section describes how to program 51570 and CDCM61004 For detail programming information please refer to their datasheets which are available on the FPGA System CD B 51570 The 51570 utilizes Silicon Laboratories advanced DSPLL circuitry to provide a low jitter clock at any frequency The 51570 are user programmable to any output frequency from 10 to 945 MHz and select frequencies to 1400 MHz with lt Ippb resolution The device is programmed via an I2C serial interface The differential clock output of the 51570 directly connects to dedicated reference clock input of the Stratix V GX transceiver for SFP channels Many applications can be implemented using this function For example the 10G Ethernet application can be designed onto this board by feeding a necessary clock frequency of 644 53
78. r exit Please select 6 DIU 4h Hi 2h REFEQ 2 d01612 7afh 135 HReset Freezez4 Memory Control 46h 157867644 531250MH2 clock test PASS 1 1 998 clk2 12866 expected clk2 128645 51570 Test PASS Stratix U Demo Program Temperature 1 21 51570 Input your Figure 5 10 Si570 Demo TR5 F40W User Manual 12 www terasic com ter www terasic com August 29 2014 Chapter 6 PCI Express Reference Design PCI Express is commonly used in consumer server and industrial applications to link motherboard mounted peripherals From this demonstration it will show how the PC and FPGA communicate with each other through the PCI Express interface 6 1 PCI Express System Infrastructure The system consists of two primary components the FPGA hardware implementation and the PC based application The FPGA hardware component is developed based on Altera PCIe IP and the PC based application is developed under the Jungo driver Figure 6 1 shows the system infrastructure The Terasic PCIe IP license is located in the FPGA System CD under the directory CDROM License Terasic_PCle_TX_RX This license is required in order to compile the PCIe design projects provided below In case the license expires please visit the FPGA website DE5 Net terasic com to acquire and download a new license TR5 F40W User Manual 73 www terasic com www terasic com August 29 2014
79. r WWW LET uU August 29 2014 www terasic com ANU RYAN 5 RD DATA 31 0 Input Read data bus oSC RD READ Output High Read signal iSC RD DVAL Input High Read data valid oSC WR ADDR i1 0 Output Address bus of write transaction It is a 32 bit data per address oSC WR DATA 31 0 Output Write data bus oSC WR WRITE Output High Write signal 1 2 3 4 5 6 oCORE CLK I NV OSE EE ADDR iSC_RD_DATA DATA oSC RD READ l isC RD DVAL f N Figure 6 2 Read transaction waveform of the PCle basic I O interface l l l 4 ig amp 14 5 NV N A 05 WRITE 4 i Figure 6 3 Write transaction waveform of the PCle basic 1 interface B PCI Express DMA Transaction To support greater bandwidth and to improve latency Terasic PCIe IP provides a high speed DMA channel with two modes of interfaces including memory mapping and FIFO link The oFIFO MEM SEL signal determines the DMA channel used memory mapping or FIFO link which is enabled with the assertion of a low and high signal respectively The address bus of DMA TijasiC TR5 F40W User Manual 75 METRI www terasic com August 29 2014 indicates the FIFO ID which is defined by
80. r card system For example if the TR5 F40W User Manual 36 www terasic com ter WWW LET uU asic August 29 2014 www terasic com ANU RYA I O standard of HSMC pins on the board is set to 1 8V a daughter card with 3 3V or 2 5V I O standard may not work properly on the board due to I O standard mismatch When using custom or third party HSMC daughter cards make sure that all the pin locations are aligned correctly to prevent shorts B JTAG Chain HSMC The JTAG chain on the HSMC be activated through the DIP switch SW6 If there is no connection established on the HSMC connectors the position 4 of DIP switch SW6 is to set where the JTAG signals on the HSMC connectors are bypassed illustrated in Figure 2 19 TR5 F40W Board TDO lir lue OFF ON ON ON Figure 2 19 JTAG Chain Default for TR5 F40W board If a HSMC based daughter card connected to the HSMC connector uses the JTAG interface the position 3 of DIP switch SW6 should be set to In this case from Figure 2 20 HSMC is used where position 3 of the SW6 is set to Similarly if the JTAG interface isn t used on the HSMC based daughter card position 3 of SW6 is set to bypassing the JTAG signals as shown in Figure 2 21 TR5 F40W User Manual 37 www terasic com August 29 2014 TDI TDO 1 TR5 F40W Board LXE OFF ON OFF
81. rasic com terasic com August 29 2014 WWW U10 SFP REFCLK p 100 0 MHz HCSL PIN AF6 10G SFP U27 SFP1G REFCLK p 125 0 MHz HCSL PIN AB6 1G SFP U27 SATA REFCLK p 125 0 MHz HCSL PIN V6 SATA U27 HSMC REFCLK p 125 0 MHz HCSL PIN V34 HSMC XCVR J15 PCIE REFCLK p From Host HCSL PIN AF34 PCI Express J12 SMA CLKIN User input 2 5 V PIN U15 J14 SMA CLKOUT User output 2 5 V PIN AD30 Table 2 10 lists the programmable oscillator control pins signal names I O standard and their corresponding Stratix V GX device pin numbers Table 2 10 Programmable oscillator control pin Signal Name I O standard Pin Assignments and Descriptions Programmable Schematic Stratix V GX Pin 1 Standard Description Oscillator Signal Name Number 51570 CLOCK SCL 2 5 V PIN AD15 I2C bus direct connected U10 CLOCK SDA 2 5 V PIN AD16 with Si570 CLK RST n 2 5 V PIN AC15 Device reset active low CLK CE 2 5 V PIN AH15 Chip enable CLK PRO 2 5 V PIN AB16 Output divider control 1 2 5 V PIN AJ15 Output divider control CDCM61004 U27 CLK OSO 2 5 V PIN AG14 Output type select CLK OS1 2 5 V PIN AG15 Output type select CLK ODO 2 5 V PIN AB15 Output divider control CLK OD1 2 5 V PIN AA15 Output divider control CLK OD2 2 5 V PIN AA14 Output divider control 2 6 RS422 Serial Port The RS422 is designed to perform communication between boards allowing a transmission speed of up to 20 Mbps Figure 2 11 shows the RS422 block diagram of the development b
82. rwise FALSE 18 returned PCIE DmaFifoWrite Function Write data to the memory fifo of FPGA board in DMA function Prototype bool PCIE DmaFifoWrite PCIE HANDLE hPCIE PCIE LOCAL FIFO ID LocalFifold void pData DWORD dwDataSize Parameters hPCIE A PCIe handle return by PCIE Open function LocalFifold Specify the target memory fifo ID in FPGA pData A pointer to a memory buffer to store the data which will be written to FPGA dwDataSize Specify the byte number of data which will be written to FPGA Return Value Return TRUE if write data is successful otherwise FALSE 1s returned 6 4 Fundamental Communication The application reference design shows how to implement fundamental control and data transfer In the design basic I O is used to control the BUTTON and LED on the FPGA board High speed data transfer 1s performed by DMA Both Memory Mapped and FIFO memory types are demonstrated in the reference design The demonstration also lists the associated PCle cards asic TR5 F40W User Manual 88 www terasic com ter www terasic com August 29 2014 ANU RYA B Demonstration Files Location The demo file is located the folder CDRAOMNdemonstrationsVPCTE batch The folder includes following files e PC Application Software Fundamental Demo exe FPGA Configuration File PCIE Fundamental sof e PCIe Library TERASIC PCIE DLL and wapi921 d
83. signments Schematic Signal Names and Functions Schematic E Stratix V GX Pin Description Standard Signal Name Number TEMPDIODEp positive pin of temperature diode in 2 5 V R6 Stratix V asic TR5 F40W User Manual 17 www terasic com ter a www terasic com August 29 2014 TEMPDIODEn Negative pin of temperature diode in 2 5 V Stratix V TEMP CLK SMBus clock 25V AMI7 TEMP SMBus data PIN AN17 TEMP OVERT n SMBus alert interrupt PIN AR17 TEMP INT n SMBus alert interrupt PIN AT17 FAN CTRL Fancontrol 25 6 2 5 Clock Circuit The development board includes one 50 MHz and two programmable oscillators Figure 2 9 shows the default frequencies of on board all external clocks going to the Stratix V GX FPGA The figures also show an off board external clock from PCI Express Host to the FPGA Lastly there is an SMA connector for clock input and an SMA connector for clock output HSMC REFCLK 25 MHz CDCM61004 Buffer 50 MHz OSC 50 B8A OSC 50 B8D OSC 50 B7D OSC 50 B7A SMA CLKIN SATA REFCLK 125 MHz QR2 SFP1G REFCLK PCIE REFCLK SFP REFCLK QLO SMA CLKOUT OSC 50 B3B OSC 50 B3D OSC 50 B4D OSC 50 4 20 624 53 MHz Figure 2 9 Clock Circuit of the FPGA Board A clock buffer is used to duplicate the 50 MHz oscillator so each bank of FPGA I O bank 3 4 7 8 has two clock inputs The tw
84. sired vendor ID and device ID Return Value Return TRUE if PCIe cards are successfully enumeated otherwise FALSE is return PCIE Open Function Open a specified PCIe card with vendor ID device ID and matched card index asic TR5 F40W User Manual 93 www terasic com www terasic com August 29 2014 PCIE HANDLE PCIE Open WORD wVendorID WORD WORD wCardIndex Parameters w VendorID Specify the desired vendor ID A zero value means to ignore the vendor ID wDevicelD Specify the desired device ID A zero value means to ignore the device ID wCardIndex Specify the matched card index a zero based index based on the matched verder ID and device ID Return Value Return a handle to presents specified PCIe card A positive value is return if the PCIe card is opened successfully A value zero means failed to connect the target PCIe card This handle value is used as a parameter for other functions e g PCIE_Read32 Users need to call PCIE Close to release handle once the handle 1s no more used PCIE Close Function Close a handle associated to the PCIe card Prototype void PCIE Close PCIE HANDLE hPCIE Parameters hPCIE A PCIe handle return by PCIE Open function Read a 32 bits data from the FPGA board Prototype bool PCIE Read32 TR5 F40W User Manual 84 oer RAD www terasic com August 29 2014 PCIE HANDLE hPCIE PCIE BAR PcieBar PCI
85. st 29 2014 Bank 1 TX Channels CDR RX Channels CDR JTAG CLKIN 0 Bank 2 Power TX LVDS Channels RX LVDS Channels CLKIN 1 Bank 3 Power TX LVDS Channels RX LVDS Channels CLKIN 2 CLKOUT Figure 2 17 HSMC Signal and Bank Diagram B Distribution The HSMC connector consists of 8 pairs CDR based transceivers 18 pairs LVDS transmitter channels and 18 pairs LVDS receiver channels B Adjustable I O Standards The FPGA I O standards of the HSMC ports can be adjusted by configuring the header position Each port can be individually adjusted to 1 5V 1 8V 2 5V via jumpers on the top right Figure 2 18 depicts the position of the jumpers and their associated I O standards Users can use 2 pin jumpers to configure the I O standard by choosing the associated positions on the header The status of LED D25 will change to indicate the I O standard of the HSMC port as shown in Table 2 21 For example LED D25 will turn red when the I O Standard of HSMC 1s set to 2 5V TRS F40W User Manual 99 METRI August 29 2014 www terasic com uonisog uonisog uonisod 1 8V 2 5V Figure 2 18 HSMC I O Configuration Header Table 2 21 mm IO Standard Indicators Jum Standard Jump o Jump Postion i Position J3 LED Status D25 Position 1 Users who connect a daughter card onto the HSMC ports need to pay close attention to the I O standard between HSMC connector pins and daughte
86. sts the frequency which CDCM61004 can generate in the FPGA board PRESCALLR DIVIDER WW i FEEDBACK DIVIDER 20 24 24 20 24 25 15 24 20 20 25 OUTPUT DEVIDER N FP OUTPUT FREQUENCY MHz 62 5 75 100 125 150 156 25 187 5 200 250 312 5 625 APPLICATION GigE SATA PCI Express GigE SATA 10 GigE 12 GigE PCI Express GigE 10 GigE The both values of PRESCALER DIVIDER and FEEDBACK DIVIDER can be specified by the PRO and PRI control pins according to the following table www terasic com TR5 F40W User Manual 59 www terasic com August 29 2014 PRESCALER FEEDBACK DIVIDER DIVIDER The value of OUTPUT DIVIDER can be specified by the ODO and OD2 control pins according to the following table CONTROL INPUTS OUTPUT DIVIDER After specifying the desired output frequency in the parallel interface developers must assert the output enable pin CE and control the RSTN pin to generate a rising signal to start the PLL Recalibration process In the FPGA board the required output type 1s LVDS so always set OSO and SOI to 0 and 1 respectively 5 2 51570 Example RTL In this section we will demonstrate how to use the Terasic 1570 Controller implemented in Verilog to control the 51570 programmable oscillator on the FPGA board This controller IP can configure the 51570 to output a clock w
87. urn TRUE if read data 1s successful otherwise FALSE 18 returned PCIE DmaWrite Function Write data to the memory mapped memory of FPGA board in DMA function Prototype bool PCIE DmaWrite PCIE HANDLE hPCIE PCIE LOCAL ADDRESS LocalAddress void pData TR5 F40W User Manual 86 www terasic com ter www terasic com August 29 2014 DWORD dwDataSize js Parameters hPCIE A PCIe handle return by PCIE Open function LocalAddress Specify the target memory mapped address in FPGA pData A pointer to a memory buffer to store the data which will be written to FPGA dwDataSize Specify the byte number of data which will be written to FPGA Return Value Return TRUE if write data is successful otherwise FALSE 16 returned PCIE DmaFifoRead Function Read data from the memory fifo of FPGA board in DMA function Prototype bool PCIE DmaFifoRead PCIE HANDLE hPCIE PCIE LOCAL FIFO ID LocalFifold void pBuffer DWORD dwBufSize Parameters hPCIE A PCIe handle return by PCIE Open function LocalFifold Specify the target memory fifo ID in FPGA pBuffer A pointer to a memory buffer to retrieved the data from FPGA The size of buffer should be equal or larger the dwBufSize dwButSize asic TR5 F40W User Manual 87 www terasic com ter www terasic com August 29 2014 Specify the byte number of data retrieved from FPGA Return Value Return TRUE if read data 18 successful othe
88. user from the PC software API Most interfaces experience read latency during the event data 1s read and processed to the output To mitigate the overall effects of read latency minimum delay and timing efficiency is required to enhance the performance of the high speed DMA transfer As oDMARD READ signal is asserted the read data valid signal oDMARD RDVALID is inserted high to indicate the data on the iDMARD DATA data bus is valid to be read after two clock cycles Table 6 2 DMA Channel Signals of Terasic PCIe IP Name Type oCORE CLK Output oDMARD ADDR S31 0 Output iDMARD DATA 127 0 Input oDMARD READ Output oDMARD RDVALID Input oDMAWR ADDR 31 0 Output oDMAWR DATA 127 0 Output oDMAWR WRITE Output oFIFO MEM SEL Output www terasic com TR5 F40W User Manual High High High Polarity Description Clock The reference clock output of PCle local interface When oFIFO MEM SEL is set to low it is address bus of DMA transfer and the value of address bus is cumulative by PCle IP and it is 128 bit data per address When oFIFO MEM SEL is set to high oDMARD ADDR bus is a FIFO ID that is used to indicate that which FIFO buffer is selected by PC API Read data bus Read signal Read data valid When oFIFO MEM SEL is set to low it is address bus of DMA transfer and the value of address bus is cumulative by PCle IP and it is 128 bit data per address When oFIFO MEM SEL is set to high oDMARD ADDR bus is a

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