ECEN 449 - Dept. of Electrical and Computer Engineering
Contents
1. Skim through the user manual for the XUPVS board to determine the pin assignments for addi tional signals The user manual may be found on the course website After modifying the UCF to include the new ports and removing unused ports append the following text to the UCF Note The above UCF lines provide ISE with timing constraints necessary to ensure proper design operation and assume you signal for clock is labeled CLOCK The clock frequency is 100MHz Updates to the LEDs at this rate will not be visible and thus the incoming clock must be divided Think back to your introductory digital logic class to determine how to divide a clock 8 Design a Jackpot game which works as follows The LEDs glow in a one hot fashion which means that the LEDs are tumed on one a time in a sequential manner Get the transition to happen as fast as you can while you can still make out which LED is on at a given of time Assign a DIP switch to cach of the LEDs At any point in time if you tum on the switch corresponding to the glowing LED you win a Jackpot and all the LEDs start glowing s ECEN 449 Laboratory Exercise 1 Deliverables 1 6 points Demonstration of working portions ofthe lab Submit a ab report withthe following items 2 6 points Correct format including an Introduction Procedure Results and Conclusion 3 6 points Commented Verilog files 4 2 points Answers to the following questi2. Create New Source window to create Source file Likewise hit Next on the Add Existing Sources window as we have no additional source files to add at the moment Finally review the information in the Project Summary window and hit Next to create project ECEN 449 3 ae ee ee Figure 3 Create New Source 2 At this point ISE has crested a new project and source file for ws to modify We will now create code to provide the desired functionality e to tum on LEDIi when Switch is high a From the Sources window open the switeh v file It will contain a Verilog module with the Port declarations described in part 2 b Above endmodule add the following line of code assign LEDS 3 0 SWITCHES 3 0 The resulting verilog module should be as follows input 3 0 SWITCHES output 13 0 LEDS Click on File Save to save your changes 3 After making our simple modifications to switch v we want ISE to perform a syntax check 4 ECEN 449 Laboratory Exercise 1 a Figure 4 Select Source Type a Click on the switch v file in the Sources window The Process window lists a sequence of steps that need to be completed before the hardware described in the switch file can be ran on the target FPGA b Double lisk on Check Synta shoud appear next to Chest Syn onee the check is Cope TSE nay sys emsa piae Es he e
3. Pro gramming File This will run all the processes necessary to create a bitstream which can be downloaded into the FPGA Running these processes may take several minutes progress is in 6 ECEN 449 Laboratory Exercise 1 2 ical by he pioning ico and opto he console When a proces competes pepe ae hc pins proce ee Tic perth te ogres Fi iced are synthesis be Vlog mapping othe whe FPGA hardware pce ene e mapped rare andrei ced area b Wenow ed to download the isteam othe FPGA on the XUP board Turn on the power to XUP bon In reces window double click an Comge Tage Device Ts wl pe IMPACT het wich perfor te blnteam downlond aio reed was deve congas Son A mesg wing of the faet hat no IMPACT prot exis wil appear Ck TOR io comme On tie nat see ese Congre devs sing Boundary Sea TAGS see and it Bh E Aer scanning the board IMPACT shold ve devices Figure 6 E m so amu iem Zore Figure 6 FTAG Chain The firsttwo both labeled xcf32p are the board s non volatile PROMs The third rc95144x1 isa CPLD on the XUP board The fourth xccace is the System ACE controller for compact fash The fifth xeSxLOO is the actual FPGA We only need to program the FPGA You should now see the Assign New Configuration File dialog box Do not assign configuration files to the first four devices skip over them by clicking Bypass A The fifth device the FPGA is programmed with a
4. Type and click Nest Next the Device Properties window appears Figure 2 Set the device properties to the following Device Family VitexS Device XCSVLXIOT Package 11136 Speed Grade 1 Additionally set the following design fow properties Synthesis Tool XST VHDL Verilog Simulator ISE Simulator VHDL Verilog Preferred Language Verilog ECEN 449 Laboratory Exercise 1 a Figure 2 Device Properties A Next the Create New Source window appears Figure 3 Click on New Source to create a new source file In the Select Source Type window Figure 4 select Verilog Module as the source type For File Name enter switch Ensure the location points to your labl project directory and hit Next See figure below Next the Define Module window appears Figure 5 This allows us to define the ports for ur hardware module Xilinx will then auto generate part of our source file based on the infor mation provided Specify a port called SWITCHES Set its direction to input set the Mast Significant Bit MSB to 3 and se the Least Significant Bit LSB to 0 Specify another port called LEDS and set direction to output MSB to 3 and LSB to 0 This will create a 4 bit input port which will connect to the on board DIP switches and a 4 bit output port which will connect to the on board LEDs Click Finish on the Summary window and Neston the
5. ECEN 449 Microprocessor System Design Department of Electrical and Computer Engineering Texas A amp M University Prof Sunil Khatri TA Monther Abusultan Lab exercises created by A Targhetta P Gratz Laboratory Exercise 1 Using the Integrated Software Environment ISE Objective The aim of this week s lab exercise is to familarize you with the Xilinx FPGA design flow via ISE by step ping through a simple example We will use ISE to create hardware which lights up the LEDs on the XUP board depending on the status of the on board DIP switches The hardware will be entirely implemented in FPGA fabric and described in ISE using Verilog After completing the aforementioned example you will be expected to implement a simple counter and jackpot game on your own with the knowledge gained from the first part of this lab Procedure 1 Launch the ISE Project Navigator and create a new design project Open a terminal window in the CentOS workstation and run the following commands source softwares Linux xilin 10 I ISE settings64 esh The former sets up the environment in order to run ISE while the later actually starts the ISE toolset Laboratory Exercise 1 b Once in ISE select File New Project The New Project Wizard opens Figure 1 Figure 1 Create New Project Selecta Project Name ex labil and a Project Location ex Jecen449 abl in your home direc tory Then chose HDL as the Top Level Source
6. it file the bitstream to be downloaded ECEN 449 7 Laboratory Exercise 1 IMPACT should automatically show your project directory and a file switch bit which was produce after Generate Programming File Select this file and click Open then click OK on the next dialog box to assign the configuration file to the FPGA A Device Programming Properties window will appear Click Ok to continue with the default settings 6 In the IMPACT main window right click on the FPGA xcSvix1 109 and select Program The Executing Command box should appear followed by a blue Program Succeeded message 6 At this point the FPGA should be programmed to function as described in switch v Verify this fact by toggling the DIP switches 0 through 3 and observing LEDs 0 through 3 Demonstrate your progress to the TA 7 Implement a 4 bit counter using the LEDs You do not need the switches for this exercise The count value should update approximately every 1 second Use the up and down push buttons on the XUP board to control the direction of the count For example when the up button is pressed the counter should count up Likewise when the down button is pressed the counter should count down When neither button is pressed the count should remain the same Demonstrate this operation to the TA upon completion Hints Do not forget to add clock and reset as input pins to your verilog module
7. lects 4 We now need to create the User Constraint File uc containing the location of the DIP switches and LEDs on the XUP Board The uef file will be used to connect signals described inthe Verilog file LEDS 3 0 and SWITCHES 3 0 in our eae to pins on the FPGA which are hardwired to the LEDS and DIP switches on the XUP board a Use your favorite text editor to create a new file called switch uc in your labi project direc tory and copy the following text into the new file ECEN 449 5 Laboratory Exercise 1 Ser swrTeas 0 NET SWITCHES 1 NET SWITCHES 2 NET SWITCHES 3 Ser LENS o Loe NET LEDS 1 LoC NET LEDS 2 LoC NET LEDS 3 7 LOC Note that the above pin assignments were taken from the XUPVS user manual accessible from the course website Afer saving switch ue the Sources window return to ISE and right click on the Xilinx FPGA part number within Jeet Ada Source and navigate to switch uc in your labl directory Inthe ext window you should sea next to switsh uef Iso elik OK tna itto the woe 5 Atthis point both switch and switch uef should show up in the Sources window Itis now time to let the tols create the hardware configuration for our specific FPGA and download the generated configuration onto the XUP board a Select switch v in the Sources window In the Process window click on Generate
8. ons How are the user push buttons wired on the XUP board ie what pins on the FPGA do each of them correspond to and are the signals pulled up or down You will have to consult the board schematics for this information b What is the purpose of an edge detection circuit and how should it have been used in this lab ECEN 449 9
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