GR740 Comparison - ESA Microelectronics Section
Contents
1. serving cache hits during miss processing transactions L1 cache physical snoop Yes No No tag error counter Branch prediction Yes can be disabled via Yes Yes ASR17 Disable branch prediction Yes can be controlled via No No on i cache miss ASR17 LEON4 time stamp counter Yes No No ASR22 23 LEON4 support for SPARC Yes No No V8E nonprivileged ASI access LEON4 HW watchpoints Yes No No trigger on least significant word of LDD STD Memory Management Unit Yes Fault Status register and Yes Yes Fault Address Register update conditions have been changed compared to earlier versions See MMUTN Shared Level 2 cache Yes Yes Yes Level 2 cache size 4 x 512 KiB 4 x 64 KiB 4 x 128 KiB 2048 KiB total 256 KiB total 512 KiB total L2 cache EDAC Yes No sim timing Yes L2 cache scrubber Yes No Yes Pipeline stage between Yes increases latency of read No No LEON4 and L2 cache and write accesses on Processor AHB bus L2 cache support for Yes via the use of SPLIT No No Cobham Gaisler AB _ Doc No GR740 CMP COBHAM mm Date 2015 03 17 Page 6 of 11 Feature GR740 LEON4 N2X NGMP On chip buses 5xAHB 2xAPB 5xAHB 2xAPB 5xAHB 2xAPB On chip bus frequency Same as CPU Same as CPU Same as CPU CPU bus 128 bit AHB 128 bit AHB 128 bit AHB Memory bus 128 bit AHB 128 bit AHB 128 bit AHB Master bus 32 bit AHB 32 bit AHB 32 bit AHB Master a2. for AHB REQ GRANT Ethernet Debug 00 50 C2 75 A3 30 00 50 C2 75 A0 60 00 50 C2 75 A0 60 7F communication Link MAC 00 50 C2 75 A3 40 00 50 C2 75 A0 70 00 50 C2 75 A3 00 3F Addresses High Speed Serial Links No No Yes SPI Controller SPICTRL master slave SPICTRL master slave SPICTRL master slave UART s 2 x APBUART 2 x APBUART 2 x APBUART General purpose timer 1x5 4x4 1x5 4x4 1x5 4x4 Timer latch capability Yes No No Watchdog output Yes Yes Yes Watchdog clocked directly Yes No No by input clock to catch PLL related events GPIO 16 22 shared on pins 16 16 additional GPIO port peripheral included in design GPIO toggling controlled by Yes Timer ticks and latch No No internal hardware events events can toggle GPIO GPIO interrupt available and Yes No No interrupt flag registers GPIO logical or and xor Yes No No registers Interrupt controller IRQ A MP IRQ A MP IRQ A MP Interrupt re map support Yes No No Timer value synchronized Yes No No between DSU AHB trace buffer and interrupt controller timestamp Performance counters Yes Yes Yes LASTAT statistics unit CCSDS TDP controller Yes No No Number of performance 16 4 4 counters in LASTAT Performance counter events Yes No No from Master I O bus Performance counter events Yes No No Cobham Gaisler AB Doc No GR740 CMP Date 2015 03 17 Page 8 of 11 Feature GR740 LEON4 N2X NGMP Performance counter events per master from L
3. to be useful for users without prior knowledge of the NGMP project where the information in this document can be used to assess if the LEON4 N2X is a suitable prototype for specific GR740 applications M Master interface s S Slave interface s X Snoop interface Figure 1 GR740 block diagram Cobham Gaisler AB COBHAM 2015 03 17 2 2 Comparison Doc No GR740 CMP Issue 1 Rev 4 Date Page 5 of 11 The table below compares GR740 LEONA N2X and NGMP Rows with differences have bold text in the Feature column TBC estimated worst case at 125 C and 20 years lifetime Feature GR740 LEON4 N2X NGMP Technology STM C65SPACE eASIC Nextreme2 STM Space DSM target Device ID Build ID 0x740 4152 0x280 4114 0x280 0x281 Radiation tolerant Yes No Yes Package LGA625 CCGA w columns FC896 Ceramic flip chip target CPU 4 x LEONA 4x LEON4 4 x LEONA Protection of register files and No protection of L1 cache Protection of register files and L1 cache and register files L1 cache FPU 4 x GRFPU 2x GRFPU 4 x GRFPU one per CPU shared per CPU pair one per CPU CPU FPU clock 250 MHz 150 200 MHz 400 MHz target Level 1 L1 cache I 4x4KiB D 4x4KiB 4x4KiB D 4x4KiB I 4x4KiB D 4x4KiB L1 cache replacement policy Least Random Soft configurable Recently Used Direct mapped Least Recently Used Soft configurable
4. 2 cache Yes for hit miss access No combined for all masters No combined for all masters Performance counter events Yes No No for L2 cache EDAC Performance counter Yes No No latching and timestamp Master I O trace buffer Yes No No filters for RETRY response Spacewire debug link Yes separate GRSPW2 Yes separate GRSPW2 Yes separate GRSPW2 USB debug link No Yes Yes JTAG debug link Yes Yes Yes Ethernet debug link Yes 2x Yes 2x Yes 2x Ethernet debug link can be Yes No No disabled via separate bootstrap DSU AHB trace buffer size 4 KiB 4 KiB 4 KiB Instruction trace buffer size 8 KiB 4 KiB 4 KiB Instruction trace buffer can Yes No not all lines Yes be written via DSU register i f Instruction trace buffer can Yes No No be read while processor is executing Instruction trace buffer Yes No No overflow detection DSU trace buffers enabled Yes when DSUEN l and No No after reset BREAK 0 Debug units clock gated by Yes Yes Yes DSUEN Reset and clocking scheme Single reset input is connected to all internal interfaces and clock domains including PCI Ethernet MIL STD 1553B and SpaceWire reset lines Clocking scheme differs from NGMP specification See user manual and data sheet for details Multiple reset inputs for different interfaces Clocking scheme differs from NGMP specification See user manual an
5. Doc No GR740 CMP Date 2015 03 17 Page 1 of 11 COMPARISON BETWEEN GR740 LEON4 N2X AND NGMP Aeroflex Gaisler AB Doc No GR740 CMP Date 2015 03 17 Page 2 of 11 TABLE OF CONTENTS TANT RODUG TIO Nas A ox KR 3 Td Scope of ibe Document iai onsite iar itum aiaa du 3 1 2 Pelerence ae a co 3 2 COMPARISON BETWEEN GR740 LEON4 N2X AND 4 2 CONG RR RE 4 22 CU I CIR du 5 PARAT S se inna 10 Cobham Gaisler Doc No GR740 CMP Date 2015 03 17 Page 3 of 11 1 INTRODUCTION 1 1 Scope of the Document This document lists the differences between the Cobham Gaisler GR740 device and prototypes that have preceded this device The document also compares the GR740 with other radiation hard LEON devices This document supersedes the document Differences Between NGMP Functional Prototype and Baseline NGMP Design NGFP FPDIFF 0016 Note that this document describes an ongoing development Performance and timing parameters of the GR740 device may change once devices have passed manufacturing testing and characterisation 1 2 Refe
6. ccess control GRIOMMU GRIOMMU GRIOMMU I O master bus SPLIT support No Yes configurable by software Yes configurable by software IOMMU bus selection Via registers and IOPTE Not supported Via registers IOMMU number of groups 8 8 6 Slave bus 32 bit AHB 32 bit AHB 32 bit AHB APB bus connected to CPU Yes No connected to slave 1 No connected to slave I O bus bus bus Debug bus 32 bit AHB 32 bit AHB 32 bit AHB Debug bus clock gating Yes via DSUEN Yes via DSUEN Yes via DSUEN Main memory controller SDRAM Multiplexed DDR2 SDRAM Multiplexed DDR2 SDRAM W separate pins Memory width 64 32 32 16 64432 32 16 64 32 32 16 Memory speed Up to 100 MHz SDRAM PCB timing limited 300 MHz DDR2 100 MHz SDRAM 400 MHz DDR2 133 MHz SDRAM SDRAM 2T signalling Yes No No Memory EDAC 4x interleaved RS 4x interleaved RS 4x interleaved RS hardware Widest SEU tolerance 16 bit lane 16 bit lane 16 bit lane Memory failover Yes Yes Yes External memory scrubbing in Yes Yes Yes PROM controller FTMCTRL 8 16 bit FTMCTRL 8 16 bit FTMCTRL 8 16 bit interrupt support acknowledgements and 64 interrupts selected via bootstrap signals and software configurable PROM EDAC Yes in 8 bit mode Yes in 8 bit mode Yes in 8 bit mode PROM lead out cycles Configurable by SW 2 4 SpaceWire GRSPWROUTER GRSPWROUTER GRSPWROUTER 8 SpW
7. d data sheet for details Multiple reset inputs for different interfaces Clock gating unit Yes extended to allow manual Yes Yes gating of additional peripherals FPU clock gating controlled Yes Yes for shared FPU No separately from CPU clock Dynamic PLL control Yes Yes Not specified Dynamic Pad control Yes Yes Not specified Pin multiplexing Yes No Yes between DDR2 SDRAM and SDRAM Temperature sensor Yes No No General purpose register for Yes No No bootstrap signals Cobham Gaisler AB NEL MEN Doc No GR740 CMP COBHAM mm EO wooo Date 2015 03 17 Page 9 of 11 Feature GR740 LEON4 N2X NGMP JTAG boundary scan Yes using SoC TAP Yes separate TAP Yes Scan test Yes Not user accessible Yes OCC scan test Yes Not user accessible Not specified Memory BIST Yes accessed via JTAG Not user accessible Not specified Clock to out test modes SDRAM PCI ETH No Not specified LEON4 N2X section 44 Not affected Affected errata Cobham Gaisler AB Doc No GR740 CMP Date 2015 03 17 Page 10 of 11 2 3 Changes in memory map Some cores do not exist in all designs and are missing in the memory map Peripherals that have been moved are LASTAT Debug bus base address for the L4STAT unit has been changed in GR740 compared to LEON4 N2X NGMP e GR1553B Base address for the MIL STD 1553B controller has been changed in GR740 compared t
8. o LEON4 N2X e PCI arbiter is not included in the design CAN controller APB interface moved to PCI arbiters position on APB bus when compared to LEON4 N2X NGMP General purpose register bank Address map has been changed between LEON4 N2X and GR740 Peripheral is not included in NGMP specification The functionality driven by the registers are different between the devices Cobham Gaisler AB Doc No GR740 CMP Date 2015 03 17 Page 11 of 11 Copyright 2015 Cobham Gaisler Information furnished by Cobham Gaisler is believed to be accurate and reliable However no responsibility is assumed by Cobham Gaisler for its use or for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Cobham Gaisler All information is provided as is There is no warranty that it is correct or suitable for any purpose neither implicit nor explicit Cobham Gaisler AB
9. ports 8 SpW ports 8 SpW ports 4 AMBA ports 4 AMBA ports 4 AMBA ports SpaceWire D support Hardware support No hardware support No hardware support SpaceWire PnP support Yes subset No No SpaceWire distributed Yes 32 interrupts with No No SpaceWire Time Code filtering Connected to TDP controller and support for Time Code filtering in SpaceWire router AMBA ports Needs to be implemented in software Needs to be implemented in software SpaceWire clock 300 MHz 200 MHz 200 MHz SpaceWire sampling DDR DDR DDR SpaceWire buffers Protected RAM Unprotected RAM Protected RAM MIL STD 1553B GR1553B 1xdual red GR1553B 1xdual red GR1553B 1xdual red Cobham Gaisler AB NL MEE Doc No GR740 CMP Date 2015 03 17 Page 7 of 11 Feature GR740 LEON4 N2X NGMP CAN 2 0B controller Yes two No Yes one PCI interface GRPCI2 GRPCI2 GRPCI2 32 bit TBD MHz 32 bit 33 66 MHz 32 bit 33 66 MHz PCI Arbiter on chip No Yes Yes PCI buffers Implemented with rad hard Unprotected Protected flip flops Trace buffer with implemented with unprotected RAM Ethernet 2x GRETH GBIT 2x GRETH GBIT 2x GRETH GBIT Ethernet controller RAM debug access access to internal buffers via APB interface Disabled Yes Yes Ethernet buffers Protected RAM except EDCL data Unprotected RAM Protected RAM
10. rence Documents NGMP Quad Core LEON4 SPARC V8 Processor Data Sheet and User s Manual Aeroflex Gaisler LEON4 NGMP DRAFT 2 2 May 2013 LEON4 N2X Quad Core LEON4 SPARC V8 Processor LEON4 N2X Data Sheet and User s Manual Aeroflex Gaisler LEON4 N2X DS 2 9 October 2014 GR740 Quad Core LEON4 SPARC V8 Processor GR740 Data Sheet and User s Manual Cobham Gaisler LEON4 GR740 UM DS D1 March 2015 MMUTN Technical Note on LEON SRMMU Behaviour Cobham Gaisler TN LEON SRMMU January 2015 Cobham Gaisler AB Doc No GR740 CMP Date 2015 03 17 Page 4 of 11 2 COMPARISON BETWEEN GR740 LEON4 N2X AND NGMP 2 1 Overview The GR740 device is a result of the work performed within the Next Generation Microprocessor NGMP activity initiated by ESA ESTEC Within this activity there have been several NGMP FPGA prototypes developed and a functional prototype LEON4 N2X was also developed The block diagram below shows the architecture of the GR740 device The table in in section 2 2 lists differences between the GR740 GR740 LEON4 N2X LEON4 N2X and NGMP baseline design NGMP Please note that the design described by NGMP has undergone changes throughout the development This document describes the differences between designs for the latest data sheets at the time of writing FPGA prototypes of the NGMP design are reduced versions of the NGMP design and have additional differences The comparison is intended
Download Pdf Manuals
Related Search