ADC-AES User manual
Contents
1. E HU 10 A a EN INGENIEUR a a a RI a 11 6 3 Mounting of the connector 12 8 4 AnNaloglle SIGN alain arial are 12 6 5 Gil dqa Bere 13 FUNNIEST 14 TA LED S Light Emitting beee vannski 14 General environmental requirements for Nevion equlipment 15 PLOQUCEW TN ae 16 Appendix A Materials declaration and recycling information 17 nevion com 3 ADC AES Rev F 1 General description The ADC AES card is a reference quality audio A D converter lt is one of the Flashlink series of modules lt will convert four analogue audio channels with the highest possible quality and produce two AES3 stereo digital audio signals Each converter has dual AES outputs which are available on the C1 backplane connector Only one output per converter is available on the C2 backplane The card may be used with or without an external AES clock signal and may be run at nominal or double sampling rates The ADC AES has internal clocks for 48 kHz and 44 1 kHz based rates but can be used with any external sampling rate 29 kHz 100 kHz nevion com 4 ADC AES Rev F 2 Block diagram Inputs Outputs gt pie NI AJ N2. MDA MAD Clock lt E 7577 x Mu nevion com 5 ADC AES Rev F 3 Technical description The ADC AES card was designed as a reference audio converter with a highly audio optimised signal path Careful design of the input circuitry was needed to maintain a high dynamic range whilst minimising distortion Jitter of the sampling clock is kept to a minimum by the use of a two stage PLL clock recovery circuit as recommended in AES 2id The analogue audio input circuit is a DC coupled electronic differential amplifier with a gain of 6 dB The use of input coupling capacitors would degrade the common mode rejection ratio of the input amplifiers The signal is then AC coupled to an inverting variable gain stage with gains ranging from 8 dB to 17 dB The gain variation is performed by switching extra resistors in parallel with the input resistor The stage feeds the input of the A D converter directly and the choice of op amp is quite important in order to achieve a low output noise The stage also feeds an inverting amplifier which feeds the inverting A D converter input This last stage must have an output noise that is even lower than the previous one The AES transmitter chip is configured as the interface clock master This means that the AES output chip produces the bit clock and the word clock required for the serial interfaces between itself and the conve
3. NeVISN ADC AES ADC AES Audio Converter card User manual Rev F nevion com ADC AES Rev F Nevion Support Nevion Europe Nevion USA P O Box 1020 1600 Emerson Avenue 3204 Sandefjord Norway Oxnard CA 93033 USA Support phone 1 47 33 48 99 97 Toll free North America 866 515 0811 Support phone 2 47 90 60 99 99 Outside North America 1 805 247 8560 E mail support nevion com See http www nevion com support for service hours for customer support globally Revision history Current revision of this document is the uppermost in the table below Rev Repl Date Sign Change description A lt lt lt 0 O 557 MB li il changes to content 5 4 2010 06 10 AA Newtemplate Updated Appendix A 0060600 4 3 2007 10 23 New front page and removed old logo mo Declaration of Conformity 1 2004 02 10 C2 backplane description B 2002 11 02 Typos formatting A 2002 09 04 Figures corrected details for first production run 2001 01 25 Preliminary version 0006060600 4 3 2 2007 09 10 1 A A nevion com 2 ADC AES Rev F Contents f GENE FalhGSSCHDUOM rr AA 4 2 BIOCK GAG FAI ma 5 Mecanica ES NPS 6 FET NA 7 4 1 Analogue input levels ve 7 DPECiiCALORS ads 8 5 1 Measurement Condon See a La ASL 8 5 2 AAGE inhib ada 8 9 3 Digitaro LE ana adas 8 A ee 9 s e 16 9 PO A AAA A YA AYAN 10 BA ADC N
4. always be derived from the external sync signal if present Each converter has dual independent AES3 transformer isolated 1100 outputs which are available on the 15 pin D sub connector of the C1 backplane module The optional C2 backplane connector should be used if 75Q AES 3id outputs are required The C2 backplane connector has only one output per converter due to space restrictions The card has a microcontroller which controls the clock switching the AES drivers and controls the LEDs on the front of the card It also monitors the 5V and 15V power voltages and reports them to the Gyda system controller when present nevion com 6 ADC AES Rev F 4 Configuration The ADC AES has two eight way miniature DIP switches located near the front of the card Groups of 3 switches control the input gain of the analogue inputs Switches marked 1L and 1R control the levels for converter 1 while switches marked 2L and 2R control the levels for converter 2 The settings for the level switches are presented in the following table 4 1 Analogue input levels 0 corresponds to off 1 corresponds to on The three numbers in the top row should be read as 52 51 50 Switches 000 1001 1010 1011 1100 1101 1110 111 gt dBu 0 dBFS Switch 1 8 sets the default sample rate 0 48 kHz 1 44 1 kHz Switch 2 8 sets the sampling mode 0 is nominal rate 48 or 44 1 kHz 1 is double rate 96 or 88 2 kHz Note The external sync input always takes p
5. ance Connector 5 4 2 ADC AES C2 backplane Format Input impedance Connector D sub 15 pin female 2 unbalanced AES 3id 750 BNC 29 kHz 100 kHz AES3 1992 1100 D sub 15 pin female AES 3id 750 BNC Rev F nevion com 9 ADC AES Rev F 6 Connector modules 6 1 ADC AES C1 Analogue Audio Made in Nor way nevion com 10 ADC AES Rev F 6 2 ADC AES C2 Analogue Audio n T 3 Pr A Made n N nevion com 11 ADC AES Rev F 6 3 Mounting of the connector module Usually the backplane modules will be delivered mounted in a frame which is part of the order The details of how the connector module is mounted if delivered unmounted can be found in the user manual for the frame FR 2RU 10 2 This manual is also available from our web site http www nevion com 6 4 Analogue signals NO nevion com 12 ADC AES Rev F 6 5 C1 digital signals ST pg SIB i S7A m Cold LOZD gt sync input x b Tes Jutputs gt 0000 ie of nevion com 13 ADC AES Rev F 7 Module status The status of the module can be monitored in two ways Gyda SC system controller LED s at the front of the sub rack The LED s are mounted on the module itself whereas
6. information Nevion provides assistance to customers and recyclers through our web site http www nevion com Please contact Nevion s Customer Support for assistance with recycling if this site does not show the information you require Where it is not possible to return the product to Nevion or its agents for recycling the following general information may be of assistance Before attempting disassembly ensure the product is completely disconnected from power and signal connections All major parts are marked or labeled to show their material content Depending on the date of manufacture this product may contain lead in solder Some circuit boards may contain battery backed memory devices nevion com 17
7. itions Temperature range 10 C to 55 C Relative humidity range lt 95 non condensing nevion com 15 ADC AES Rev F Product Warranty The warranty terms and conditions for the product s covered by this manual follow the General Sales Conditions by Nevion which are available on the company web site www nevion com nevion com 16 ADC AES Rev F Appendix A Materials declaration and recycling information A 1 Materials declaration For product sold into China after 1st March 2007 we comply with the Administrative Measure on the Control of Pollution by Electronic Information Products n the first stage of this legislation content of six hazardous materials has to be declared The table below shows the required information Toxic or hazardous substances and elements Toxic or hazardous substances and elements hazardous substances and elements ERE FE R SRA 28 Part Name Cadmium HexavalentiPolybrominated Polybrominated Pb Hg Cd Chromium biphenyls diphenyl ethers Cr VD PBB PBDE O Indicates that this toxic or hazardous substance contained in all of the homogeneous materials for this part is below the limit requirement in SJ T11363 2006 X Indicates that this toxic or hazardous substance contained in at least one of the homogeneous materials used for this part is above the limit requirement in SJ T11363 2006 This Is indicated by the product marking A 2 Recycling
8. riority for the sampling rate The figure below shows the DIP switch SW1 set for 18 dBu dBFS and an internal sampling rate of 48 kHz nevion com 7 ADC AES Rev F 5 Specifications 5 1 Measurement conditions Sampling rate 48 kHz Ambient temperature 25 Measurement bandwidth 20 Hz 20 kHz Detector RMS Input overload level 0 dBFS 24 dBu 5 2 Analogue inputs Number of inputs 4 electronically balanced Common mode voltage tolerance 30 V Input impedance differential 25 kO Frequency response 10 Hz 21 5 kHz 0 dB 1 dB Passband ripple 0 001 dB Group delay 65 samples Stopband attenuation 110 dB Dynamic range Min 112 dB A 0 dBFS 15 dBu Typ 117 dB A THD N 1 dB FS Max 95 dB Typ 102 dB Intermodulation distortion 12 dB FS Max 85 dB Typ 104 dB Crosstalk Max 100 dB 110 dB CMRR 0 Hz 8 kHz Min 70 dB Typ 80 dB 5 3 Digital outputs Internal sampling rates 44 1 48 88 2 and 96 kHz Intrinsic jitter 200 ps peak peak JTF corner frequency 2 Hz JTF peaking 0 dB 5 3 1 ADC AES C1 backplane Number of outputs 2 2 transformer balanced Format AES3 1992 Output impedance 1100 1 THD N of 60 dB FS signal 60 2 SMTE 4 1 60 Hz 7 kHz nevion com 8 ADC AES Connector 5 3 2 ADC AES C2 backplane Number of outputs Format Output impedance Connector 5 4 Digital input External sampling rates 5 4 1 ADC AES C1 backplane Format Input imped
9. rters The A D converter chip uses the same master clock frequency for both nominal and double sample rates This means that we can use the same crystal oscillators for both sampling modes The external sync signal can be nominal or double the sample rate independent of the sampling mode on the card i e the card may sample at 96 kHz while the external sync signal is a 48 kHz signal The sampling mode is set with the DIP switch 2 8 for both converters Clock jitter in a reference A D converter must be kept very low By the time the external clock signals reach the card they often have more jitter than the internal clock oscillator The best solution is realized when using the external AES signal to lock the internal crystal oscillator The ADC AES has an advanced clock management system that locks quickly to an external clock The master clock is taken temporarily from the AES receiver but switches to the low jitter oscillator when it in turn has locked to the received signal The ADC AES has oscillators for 48 and 44 1 based sampling rates but only one will be powered up at any time When power is applied to the card the sample rate is decided by the DIP switch configuration If an external AES signal is detected the input AES circuit reports the received sample rate to the microcontroller which then switches to the appropriate oscillator if necessary or possible The external sync signal always has priority and the sampling rate of the card will
10. the Gyda SC is a separate module giving detailed information of the status of the card The functions of the LED s are described in sections 7 1 The Gyda SC is described in a separate user manual 7 1 LED s Light Emitting Diodes The status of the module can be easily monitored visually by the LED s at the front of the module The LED s are visible through the front panel as shown below Status External Sync status Output sample rate Sample mode Text not printed on the front panel Diode overview of ADC AES The ADC AES has 4 LED s each showing a status The position of the different LED s is shown above Diode state Red LED Green LED Status Module is faulty Module is OK Card has not been Replace Module power is OK programmed External Sync Loss of sync signal Input signal present Input signal present status No electrical input and identical to the 1 but different to the signal DIP setting DIP setting Output Sample rate Other sample rate 148 kHz 96 kHz 44 1 kHz 88 2 kHz Sample mode Double rate nevion com 14 ADC AES Rev F General environmental requirements for Nevion equipment 1 The equipment will meet the guaranteed performance specification under the following environmental conditions Operating room temperature range 0 C to 50 C Operating relative humidity range lt 90 non condensing 2 The equipment will operate without damage under the following environmental cond
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