Home

Atlas™-II AT460A-BI Application Processor

1. Figure 61 Contraction YUV YCrCb Mode YUVRGB 1 with 1 4 ratio in Row and Column 8 5 2 7 Active Region The Video Input Port always keeps track of the number of pixel clocks after each HSYNC X count and the number of lines after VSYNC Y count The current X count and Y count can be read from registers CAM COUNT The most important for the programmer to do is to define active region in which the image is valid and the pixel data is store to system memory via a FIFO The pixels outside of the active region are ignored The active region is defined by defining an X start and X end and a Y start and Y end In all the lines between Y start and Y end if the pixel is bet
2. cd 10 8 11 2 Pin 10 9 Physical 10 9 1 me 10 927 Package mannan a a E 10 9 3 DC Electrical Characteristics nennen nennt 10 9 3 1 Absolute Maximum Ratings rs i ecce renti Ced eI enne rne e ed srt 10 9 3 2 Recommended Operation 10 9 3 3 DC Electrical a a 10 9 3 4 Electrostatic Discharge ete 10 9 3 5 Power 10 9 3 6 Thermal CharacteristiCs 5 oerte trei e TEE HE LEE DRE d 10 94 AC Electrical Characteristics ssssssssssssssssssssee eene 10 9 4 7 Operation Frequency 2 4 11 eene nennen nennen nnn 10 9 4 8 Clock AC Specifications enne 10 9 4 9 BI cm ER 10 9 4 10 External Interr pts ient ere tee ERR 10 9 4 11 SDRAM SGIS2 10 9 4 12 DDR SDRAM 0000 10 9 4 13 Camera
3. 10 8bits pixel data a DWORD Big 22 10 12bits pixel data in a DWORD Little 10 2bits pixel data in a DWORD Big Endian in a byte Little Endian for byte in a DWORD 10 2bits pixel data in a DWORD Big Endian in a byte Little Endian for byte in a DWORD 10 Screen and OSD Active 0 a A nnne nennt 10 LCD Sync Signals Waveform nsns 10 LCD Alteration Signals Waveform sse 10 Screen OSD FIFOs Request 4 10 FIEO SUpptress uM 10 LCD Controller DMA Memory 10 LCD Controller DMA Memory 2 D 222 10 gie EE 10 Block Diagram of BitBLT 2044 0 0000 10 BitBLT 2D window 10 ROP2 3 Code Definitions 2 444 A 10 Block Diagram of PCI Bridge e er 10 32 bit Data Fix latency Read BURST_READ 0 DWORD_ACCESS 1 BUS_WIDTH 1 ecc 10 Figure 35 16 bit Data Fix latency Read BURST_READ 0 DWORD_ACCESS 0 BUS WIDTH 1 VAR ACO O wie deed ace oe E
4. CPU DSP SYS IO CPU DSP SYS IO 200 200 200 100 300 150 150 75 Typ Typ Unit Pcore VDDPRE a 7 mw PLL 4 mw IO MEM VDDIO MEM 90 Internal VDDPDN from 120 to 160 mw Sleep mode PIO Ppll Pcore Pin m Unit typ 35 3 0 2 0 mw total About 40 mw 9 3 6 Thermal Characteristics Table 100 Thermal Resistance Data Rating Value Unit Notes Junction to Ambient 19x19 Natural Convection Four layer board 2832 GW package Junction to Ambient Four layer board 2s2p Resa 38 5 14 14 Natural Convection Sep package Junction to Ambient 19 19 1 m s Four layer board 252 C W package Junction to Ambient 14 14 1 m s Four layer board 252 package Junction temperature is a function of die size on chip power dissipation package thermal resistance mounting site board temperature ambient temperature air flow power dissipation of other components on the board and board Centrality Communications Inc 361 AT460A BI Developer s Manual Centrality thermal resistance 9 4 AC Electrical Characteristics AC Test Timing Conditions Unless otherwise noted all test conditions are as follows TA 20 to 70 C VDD CORE 1 14 to 1 26 V VDD 31310 3 5 V Input conditions All Inputs tr tf lt TBD Output Loading All Outputs about 50 pF 9 4 7 Operation Frequency Data Table 101 provides the
5. 10 Timing Diagram power and reset 10 Timing Diagram Standard SDRAM Memory Read 10 Timing Diagram Standard SDRAM Memory Write Timing 10 Timing Diagram DDR SDRAM Memory Read 10 DDR SDRAM Memory Write Timing nemen nnns 10 data 10 Led Timing m 10 Nand rom read data 10 Nand rom write data TIMING sirais aa anaa a 10 GPIOdata liffirig 2 In 10 Serial Port AC Timing 10 Timing Diagram USB Output 10 Timing Diagram JTAG Input Output 10 Centrality Communications Inc 7 AT460A BI Developer s Manual LS Centrality COMMUNICATIONS Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40
6. Output high voltage VDD 10 3 0 DRV4 VOH 24 V is driver dependent Output high voltage VDD_10 3 0 DRV8 VOH 24 V IOH is driver dependent Output high voltage VDD MEM 2 3 DRV8 MEM VOHDDR 1 8 V IOL is driver dependent Output low voltage VDD 10 3 0 DRV4 VOL 04 V IOL is driver dependent Output low voltage VDD_10 3 0 DRV8V VOL 04 V 5 E T Output low voltage OLiS driver dependent VoippR y VDD MEM 2 3 DRV8 MEM Capacitance Cin 10 pF 1 See Table97 for the typical drive capability of a specific signal pin based on the type of output driver Table 97 Drive Capability of Atlasll Output Pins Driver Type Supply Voltage IOL Unit DRV4 VDD_IO 3 0V 4 4 mA DRV8_MEM VDD_IO 2 3V 8 8 mA DRV8 VDD_IO 3 0V 8 8 mA 9 3 4 Electrostatic Discharge CAUTION This device contains circuitry that protects against damage due to high static voltage or electrical fields However it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages Operational reliability is enhanced if unused inputs are tied to an appropriate logic voltage level i e either GND or VCC Table 98 gives package ESDI characteristics for this device Table 98 ESD Characteristics Sym Rating Unit Human Body Model HBM JEDEC JESD22 A114 B 2000 V VCD
7. RISC Control Controller bd registers Interface command 2 5 address generator data 1 0 device Interface 9 Interface NandF lash DMA DMA slave FIFO Controller Interface Interface Figure 55 NAND Flash Controller Block Diagram In normal read write mode RISC write command address to the NAND Flash interface to start read write cycle data can be exchanged between DMA controller and FIFO of NAND Flash interface or between RISC and FIFO of NAND Flash interface In directly read mode used when boot up from NAND Flash RISC sends address to I O address bus and NAND Flash interface will translate that address and generate the read command and address sequence to NAND Flash automatically When data is ready on the I O data bus NAND Flash interface will assert data ready signal to RISC and RISC can fetch that data from the I O data bus The NAND Flash controller supports 256 bytes or 512 bytes ECC Error Correction Code for 8 bit NAND flash 256 words ECC for 16 bit NAND flash The ECC is generated by hardware automatically when data are written into the NAND Flash If system boots up from NAND Flash the NAND Flash is mapped to the bottom of system address starts from 0 0000 0000 Usually boot loader code putted in the block 0 of the NAND flash RISC will execute the boot loader first in which it will configure the SDRAM and initialize the hardw
8. noe UR erbe D ae 10 5 1 2 Configuration Setup hate 10 527 Glockanmd PED 10 5 23 OVetVIOW seed er te es tea es as vtta a sedie oett dee e est ee 10 5 24 Osolllator reda dee idee e Ee BRI 10 5 255 hen eunte E 10 5 2 0 Multiplexer amp Divider 10 52 77 Clock Switching dada dated teet eden ed tee 10 5 2 8 Real Time Clock Registers Deel tie ee 10 5 9 ME io I II Te Tt 10 53 92 Over vIew e ae aa IIl 10 5 3 10 Power On Off Sequence 11 1 000000 000000 10 5 3 11 Sleep Wakeup 10 5 3 12 Power Manager 10 5A 10 5 4 1 oa 10 5 4 2 Interrupt Controller Registers 10 5 5 OS iin ei E EE 10 55 35 OVOEVIGW ciii sore OE De weit in 10 5 5 4 05 Timer Reg
9. 0 f 100000 159 408576 10198 1340 29184 105124 105000 COEF1 Offset 0 0 1000 223 223 10 hODF C4 C5 C6 COEF2 __ 0 1000 136 136 10088 C8 520 129 10208 0 0 1000 C __ O 1000 207 516 352 10 h204 COEF3 0 0 1090 27 27 10115 OFFSET To directly display the received picture in the LCD screen the RGB data will be combined to 5 6 5 5 5 6 6 5 5 8 8 8 formats as the LCD interface defined after the conversion Following formulas give the definition 5 6 5 output data 15 11 R 7 3 output data 10 5 G 7 2 output data 4 0 B 7 3 5 5 6 output data 15 11 R 7 3 output data 10 6 G 7 3 output data 5 0 B 7 2 6 5 5 output data 15 10 R 7 2 output data 9 5 G 7 3 output data 4 0 B 7 3 8 8 8 output data 24 16 R 7 0 output data 15 8 G 7 0 output data 7 0 B 7 0 In 5 6 5 5 5 6 6 5 5 format 2 combined 16 bit data will be recombined to a 32 bit data In 8 8 8 mode the combined 24 bit data will be zeroed in the upper 8 bit and recombined to a 32 bit data 8 5 2 6 Scaling The Video Input Port supports 1 2 1 4 and 1 8 scaling function in coloum and row direction For Bayer RGB data mode it scales the pixel data as following table 0 D 0 w o w 0 0 D O uo Q D 0 m o DW O o 0 3 0 D 0
10. Centrality USB OTG DMA Revision Register USBOTG REV 0 0800 Bit Name Default Description 7 0 REVCODE 3 8 te Reserved e USB OTG Interrupt Status Register USBOTG INT STATUS 0x0804 Bit Default Description 0 ETDERR 1 bO ETD Error Interrupt ETD DMA transfer aborted on error read 0x080c to find out which ETD client The Error status will be cleared by hardware 1 R 1 bO Endpoint Error Interrupt EP DMA transfer aborted on error read 0x0810 to find out which EP client The Error status will be cleared by hardware 312 __ Reserved 5 Interrupt Enable Register USBOTG DMA INT EN 0 0808 Bit Default Description 0 R W ETDERR ETD Error Interrupt Enable 1 R W EEERR 100 Endpoint Error Interrupt Enable Ls S Reseved e USB OTG ETD DMA Error Status Register USBOTG ERR 0x080C Bit Default Description 31 0 R ETDDMAERST 32 hO ETD DMA Error Status W e USB OTG Endpoint DMA Error Status Register USBOTG EP ERR 0 0810 Bit Name Default Description EPDMAERST 3280 Endpoint Error Status R W USB OTG ETD DMA Enable Register USBOTG DMA EN 0x0820 Bit Name Default Description 31 0 ETDDMAEN 320 ETD DMA Enable R W Setting the ETDDmaEnable bit will enable DMA transfer on the corresponding ETD Will be auto disable
11. rwwener uosome m xime rouwowooz xia m ome e m Centrality Communications Inc 347 AT460A BI Developer s Manual KE Centrality COMMUNICATIONS xePo Pouwospaz General Purpose IO LDD lt 8 gt xePo Pouwospez General Purpose LDD lt 9 gt 4 fes xeeoce Pouwopez General Purpose IO LDD lt 10 gt X lt 11 gt PDUWOADGZ General Purpose IO LDD lt 1 gt xePo Pouwopez General Purpose IO LDD lt 12 gt Pouwopez General Purpose IO LDD lt 13 gt x GPiocis gt PoUwoapez General Purpose IO LDD lt 15 gt rowener cesso m mo peee _ enor m foson rnor usse ea euse voon __ e seves wewus __________ USP1 Clock BIT_OLK USP1 Transmit Frame Sync FRAME_SYNC Centrality Communications Inc 348 AT460A BI Developer s Manual KS Centrality COMMUNICATIONS X_SCLK lt 2 gt PDUOASDGZ USP2 Clock le _ lt 2 gt PDUWOADGZ USP2 Transmit Data TRACESYNC fs X RXD 2 PDUWOADGZ
12. Default Description Centrality Communications Inc 279 AT460A BI Developer s Manual Centrality 15 0 R W HSYNC_ACT_NUM 1610000 HSYNC active width in the number of pixel 31 16 R W HSYNC BLANK NUM 16 h0000 HSYNC blank width in the number of pixel e Camera PIXCLK Control Register CAM PIXCLK CTRL 0x038 Bit Name Default Description 15 0 R W PIXCLK_NUM 16 h0000 PIXCLK number in the number of IOCLK Actual output PIXCLK period equals to 2 PIXCLK_NUM 1 IOCLK period 3116 RW Reserved Camera VSYNC width register CAM VSYNC HSYNC 0x03C Bit Name Default Description 15 0 R W HSYNC 1610000 Pixel number between the first HSYNC and VSYNC 31 16 VSYNC WIDTH 1680000 VSYNC width number in the number of R W PIXCLK period Actual VSYNC valid period equals to VSYNC_ACT_NUM HSYNC period VSYNC_HSYNC VSYNC_WIDTH PIXCLK period e Camera timing control register CAM TIMING 0x040 Bit Name Default Description 0 R W PCLK_POLAR 1 bO Invert pixel clock 1 Invert pixel clock i e pixel clock 72 phase off 0 Do not invert pixel clock the horizontal sync signal 1 horizontal sync signal is active low horizontal sync signal is active high roa Invert the vertical sync signal 1 vertical sync signal is active low 0 vertical sync signal is active high 3 R W HSYNC_MASK 1 bO Mask HSYNC control 1
13. _ data in the RXFIFO reaches the threshold Centrality Communications Inc 309 AT460A BI Developer s Manual oe 1 invalid 1 oe 1 It s time to write TXFIFO when the number of data in the TXFIFO reaches the threshold 0 invalid 1 valid Receive an error UART frame DEM DEM invalid 1 valid If this bit is become 1 it mean that the RXD line become low level for at least 10 bits time Then receiving action must be stopped Disable the RX EN bit in the USP TX EN register then delay some time to double check this bit again if no new break happens enable the RX EN wait some time and to reset and restart the RXFIFO to flush the invalid data and prepare to accept the new data 0 invalid 1 valid 9 NEN EMEN THD REACH nelli BREAK UART RX TIMEOUT If this bit is become 1 it means that since the last data had been received in the fifo there is no more new data received for the time specified by the timeout bit number defined in the TIMOUT NUM bits of the UART LINE CTRL register 0 invalid 1 valid If this bit is valid it means that one of delta status bit in the UART MODEM STATUS register has modified any read operation to the register of MODEM STATUS will clear this bit 0 invalid 1 valid 190 UART RISC DSP Mode Register UART_RISC_DSP_MODE RISC 0 5 DSP 0x2E MODEM_STATUS_CHG This register can only be written by RISC For it s r
14. number of byte specified by CANBUS_DMA_LEN has been all transferred 2 The number of message specified by CANBUS_DMA_MSGCNT has been all transferred 3 The internal unmasked canbus interrupt is generated Name Default Description Bit 2 0 R W INT MASK BitO canbus internal int Bit1 for message counter int and Bit2 for timeout int 0 masked 1 unmasked 5 3 R INT_STATUS for canbus internal int Bit4 for message counter int and Bit5 for timeout int can be masked by Interrupt Mask 0 no interrupt 1 interrupt generated transferred yet CANBUS DMA Timeout Register CANBUS_DMA_TIMEOUT 0xF2C Bit Name Default Description 31 0 R W TIMEOUT 32170 The number of clock cycle for timeout 0 means unlimited 8 10 PWM 8 10 1 Overview The PWM Pulse Wide Modulate generator can generate 4 independent outputs Each output duty cycle can be adjusted by setting the corresponding wait and hold registers All these 4 PWM outputs are multiplexed with GPIO Please refer to the section of Pin Sharing and GPIO for more details 8 10 2 PWM Registers Table 91 PWM Interface Register Mapping RISC Address Register Description lt 11 0 gt 00 PWMouputenable Others Reserved PWM PWM output 1 hold state for low pulse PWM_WAIT2 PWM output 2 wait state for high pulse Centrality Communications Inc 344 AT460A BI Developer s Man
15. CMDQUE ADDR 0x1C48 Bele Description co 4 a ADDR 23 h0 The command queue start address in memory when BLT R W works in command queue mode every command must be packed up as following Every command is composed of 16 double words and the start address must be 4Dword address based DWO Bit 26 0 Source base addr DW1 Bit 26 0 Destination base addr DW2 Bit 10 0 2D window height in pixel Bit 26 16 2D window width in pixel DW3 Bit 12 0 Destination stride Bit 28 16 Source stride DWA Bit 10 0 Source 2D window y coordination Bit 26 16 Source 2D window x coordination Bit 31 Source 2D window Y direction Centrality Communications Inc 147 460 Developer s Manual Centrality Bit 10 0 Destination 2D window y coordination Bit 26 16 Destination 2D window x coordination Bit 31 Destination 2D window Y direction Bit 10 0 Clip rectangle Top left y coordination Bit 26 16 Clip rectangle Top left x coordination Bit 10 0 Clip rectangle Bottom right y coordinate Bit 26 16 Clip rectangle Bottom right x coordinate Bit 31 0 Foreground color Bit 31 0 Background color Bit 31 0 Source color key Bit 31 0 Destination color key Bit 7 0 ROP Bit 9 8 Pixel format Bit 10 Clip enable Bit 11 Source color key enable Bit 12 Destination color key enable Bit 31 0 Pattern matrix low DW Bit 31 0 Pattern matrix high DW DW15 reserved The uppe
16. Default Description YUV_U ESTA 3 b000 Invert the MSB of the YUV components to convert IRR signed results to unsigned outputs Bit 2 invert Y Bit 1 invert U Bit 0 invert V ITU601 accepts positive YUV and is always positive while UV is signed after conversion so UV needs inversion So usually set the as 3 6011 RGB S CONV 3 b000 Invert the MSB of the RGB components to convert RAD signed to unsigned when the input RGB is signed Bit 5 invert R Bit 4 invert G Bit 3 invert B Remark the rgb2yuv conversion accept unsigned RGB and signed coefficients only so here keep this as Fee Hm For 8 bit 4 2 2 output even pixels are U ESSE 7 For 8 bit 4 2 2 output even pixels are V YUV output is 4 2 2 8 bit output double clock 0 YUV output is 4 4 4 16 bit output RGB_YUV Do RGB to YUV conversion p Bypass RGB to YUV conversion FAST CLK Use high speed SYSCLK When SYSCLK is higher than 108MHz 13 5MHz x 8 recommend setting this bit to make the internal multipliers work normally 0 When SYSCLK is lower than 108 2 this bit must be 0 2X HSCALE 2x scale horizontally R W 0 no scale This bit is mainly used when doing TV out cause the frame buffer will be 2 times scaled vertically the odd and even fields show the same frame buffer EVEN UV the even pixel UV U1V1 mode the even pixel odd pixel V U1V2 mode EVENFIELD This bit only used when in TV mode
17. PCI Bridge DSP Operation Register SYS2PCI DSP OPERATE 0x0000 Centrality Communications Inc 152 AT460A BI Developer s Manual Centrality Bit Name Default Description 0 R w 1 b1 1 DSP read PCI 0 DSP write PCI 1 Read 1 DSP operation finished 0 DSP operation not finished Write 1 reset to 0 0 reset to 0 3 2 ___ ______ _____ Reseved 7 4 AT lt 3 0 gt 4 hO Byte enable for PCI read write lt 0 gt SYS2PCI DSP DATALJ 7 0 lt 1 gt SYS2PCI DSP DATAL 15 8 lt 2 gt SYS2PCI DSP DATAH 7 0 lt 3 gt SYS2PCI DSP DATAH 15 8 1 enable byte 0 disable the byte 158 Reserved PCI Bridge DSP Address Low Register SYS2PCI DSP ADDL 0x0002 Default Description ADDL 16 0 PCI address low for DSP IO access on PCI bus Fw e PCI Bridge DSP Address Low Register SYS2PCI DSP ADDL 0x0002 Bit Name Default Description ADDL 16 h0 PCI address low for DSP IO access on PCI bus R w PCI Bridge DSP Address High Register SYS2PCI DSP ADDH 0x0004 Bit Name Default Description 16 h0 PCI address high for DSP IO access on PCI bus R w PCI Bridge DSP Data Low Register SYS2PCI DSP DATAL 0x0006 Bit Name Default Description 15 0 PCI data low for DSP IO access PCI bus R w When read this register contains data for read When write this register contains data for write
18. Please refer to figure of Screen and OSC Active Region for the effects of the OSD2 region settings They define the top left and the bottom right corner pixel position 6 2 4 2 Sync Signal Generation Registers In the slave mode the horizontal and vertical sync signals are given by the display In the master mode Atlas II Processor will generate the sync signals based on a set of parameters specifically the period and width of each sync pulse Centrality Communications Inc 107 460 Developer s Manual Centrality VSYNC_PERIOD 1 Lines ra gt VSYNC_WIDTH 1 Lines or Pixels VSYNC HSYNC ME HSYNC PERIOD 2 Pixels PIXEL DATA ii a 5 d 25 VCOUNT 0 VSTART y VEND al 0 e gt HSYNC PIXEL 5 7 DATA Valid Pixel a E E 2 S 24 HCOUNT 0 Es m l x 92 2 Figure 23 LCD Sync Signals Waveform VSYNC_PERIOD 1 Lines VSYNC_WIDTH 1 Lines or Pixels VSYNC ALT_VSYNC_START_ PIXEL asc LIL JL JL JE JE fL JL fL JL JE S 2 E 22 VCOUNT 0 oe 2 od 2 z E z1 2 d
19. e USB OTG Low Speed Threshold Register USBOTG HC LS THRESOLD 0x00E4 Name Default Description 10 2 LSTHRESH 11 h628 Low Speed Threshold R W This is the number in USB full speed bit times that are required to be remaining in a frame to allow a low speed packet to be transmitted All low speed packets have a MaxPacketSize maximum of 8 bytes so this should be set to the number of bit times needed to transmit an 8 byte packet The default value of 628h should not be changed for normal operation 3131 d f Reserved e USB OTG Root Hub Descriptor A Register USBOTG HC RH DESC A 0x00E8 Name Default Description Bit These bits specify the number of downstream ports supported by the Root Hub No Power Switching 8 R hall All ports are power switched This bit will PWRSWTMD always read as SET Power Switching Mode This bit is used to specify how the power switching of the Root Hub ports is controlled In this implementation each port is powered individually This allows for power to be controlled on a per port basis The port responds only to port power commands Set ClearPortPower Over Current Protection Mode This bit describes how the over current status for the Root Hub ports are reported This implementation uses gang power and gang over current reporting No Over Current Protection This bit describes how the over current status for the Root Hub is reported In this implementation the
20. has control over these pins either Video Input Port or NAND Flash can not control the pin e f GPIO does not have control over these pins the EN bit in RSC_PIN_MUX register determines whether Video Input Port or NAND Flash has control over these pins e _UARTO JTAG Pin Pin Name UARTO JTAG GPIO XGPIO 16 DSRO 1 __________ GPIO group0 offset 16 XGPO 19 GPIO groupO offset 19 XGPIO 20 20 XGPO 21 3 XRICK GPlOgroupOoffset21 XGPIO 22 crs0 XxpBGRO 9 GPlOgroupOoffset22 X_GPIO_23 50 XDBGACK GPlOgroupOoffset23 XTXDO __ GPlOgrouptoffset19 RXDO 20 Depending on the reset status of JTAG_MODE lt 1 0 gt please refer to the section of Mode Configuration Pins if the chip is configured into JTAG MODE the JTAG pins will be enabled GPIO UARTO functions except for the last two pins will be disabled However in this mode UARTO can still be used as asynchronous mode which only needs X TXD 0 X RXD 0 Otherwise after reset GPIO will have control over these pins User can write corresponding GPIO control registers to give the control of these pins to UARTO e USP1 CODEC Pin Pin Name USP1 CODEC GPIO IX RXD1 GPIO group offset 23 X TFS 1 FRAME SYNC GPIO group1 offset 24
21. n 0 Sn 4SSGSnS 10 8 2 NRI ERE 10 8 2 1 T 10 8 2 2 Bridge 0 2222 4 1 6 000000 0000 rennen rsen etre nnns 10 8 3 Controler si REN ERN ERR He E PIE 10 Centrality Communications Inc 3 AT460A BI Developer s Manual Centrality 8 3 1 RR 10 8 3 2 Functional D6escriptiOn ecco na ae aE 10 8 3 3 Basic DMA Operations esses eene tenter nnne rin EE SG 10 8 3 4 Controller Registers seessesseseeseseeeeen nennen enne enters nsi 10 84 INAND Fl sh Interface oerte 10 8 4 5 Overview E 10 8 4 6 Pin D scriptiON RE 10 8 4 7 NAND Flash Interface Registers 10 8 5 Video Input 10 8 5 1 iiri ERES NIU REGINE ER Uu ea intera 10 8 5 2 Functional Description 2 2 docete LER Ld de UD oae do E 10 8 5 3 Input Port Registers 10 8 6 UEBER BM ie da 10 Rr eus 10 8 6 5 Signal Description 10 8 6 6 Functional Descript
22. 29 24 CMD_INDEX 6 hO This bit shall be set to the command number CMDO R W 63 ACMDO 63 31 30 HO Reserved Table 40 Definition of Transfer T Multi Single Block Count Block Count Block Select Enable Function 810 Don t Care Infinite Transfer Transfer Stop Multiple Transfer Table 41 Defintion of Response Type Response type Index Check CRC Check Name of Response Type Transfer Type Enable Enable 001010 No Response 1 10 11124 40 1 0 0 4 SDIO Card Response Register 0 3 SD CARD RESP x 0x0010 0x001C Bit Name Default Description 127 0 RESP lt 127 0 gt 1280 The following table describes the mapping of command R responses from the SD Bus to this register for each response type In the table R lt gt refers to a bit range within the response data as transmitted on the SD Bus RESP lt gt refers to a bit range within the Response register Table 42 Response Bit Definition for Each Response Type Response Description Response Response Field Register R1 R1b normal response Card Status R lt 39 8 gt RESP lt 31 0 gt R1b Auto CMD12 response Card Status for Auto CMD12 R lt 39 8 gt RESP lt 127 96 gt R2 CID CSD Register CID or CSD reg incl R lt 127 8 gt RESP lt 119 0 gt Centrality Communications Inc 167 AT460A BI Developer s Manual Centrality R3 OCR Register OCR Register for memor R lt 39 8
23. Centrality Communications Inc 145 460 Developer s Manual Centrality ERES RC om omes DPSoon DSon SDPxon SDPnaon SDPSoox SDxPDxa SDPSxox DPSxa PSDPoax SDPxa SDPana DPSDxox PDSnaon DSPDxaxn PSDnox SPDSonox SSPxDSxoxn Pam Bits 7 4 ea re Rt ume ox om 7 v ten sme roem DPSxna DPSDPoaxx DPSnoa SSPxDSxox Figure 32 ROP2 3 Code Definitions DSna DPSona SDPxnon PSon SDPaon SPDnaon SDPona DPSxnon SPxDSxa DPSaon PDSPanaxn 3 PDSxnon PSDPSanaxx PDSaon SSPxDSxaxn SDPnaa SPxPDxa PDSxon SDPSanaxn PSDPSaoxxn SPDnox DPna PDSPaox DPSana SPDSxox PSDnaon SDPSxaxn SSPxPDxaxn SPDnoan 7 o x SPna PSDPaox SPDSoax SPDSnoaxn SPDaxn DPSDxoxn SDP xna PSDPSoaxx PDSPonoxn PSDnax DPSaxn DPSDoaxn 7 gt DSPnoaxn DSPDSoaxx DPSxx DSPnax DPSDPaoxx PSDPSonoxx PDSPoaxn SDPxan PDSaxn 5 SDPSonoxn DPSoa PSDPxax SDP Snaoxn DSxn DPSoxn DSPDaoxn DSPnoa DPSnax DPSnao DSPDxoxn SDPSoaxn DPSono DSno SDPnoa SPDnax SPDSxax SPDSanax SDPSxoxn DSPDoaxn DPSDaoxn SDxPDxan SSDxPDxax DSPDSaoxx DSPnao DPSxo DPSano
24. 0x005C USBOTG FC X STATUS X Buffer Filled Status Register 0x0060 USBOTG FC Y STATUS Y Buffer Filled Status Register 0x0050 USBOTG FC X INT STATUS X Buffer Interrupt Status Register 0x0054 USBOTG FC Y INT STATUS Y Buffer Interrupt Status Register 0x0058 USBOTG FC XY INT EN X Y Interrupt Enable Register USBOTG HC PORT1 STATUS Port 1 Status Register 0 00 8 pe Reserved 0 00 05 Immediate Interrupt Register Centrality Communications Inc 189 AT460A BI Developer s Manual KE Centrality COMMUNICATIONS ____ Reseved 0x0100 0x01FC Cd Reserved 0x0280 0x03FC_ 7 0x0480 Ox07FC_ 7 Reserved __ S 0x0814 0x081C_ 7 Reseved 2 0x0828 USBOTG TRIGX EN ETD DMA Enable X Trigger Request Register 0 082 USBOTG EP TRIGX EN EP DMA Enable X Trigger Request Register 0x0834 USBOTG DMA EP TRIGXY EN EP DMA Enable XY Trigger Request Register Misc Control Register _____ 0 0830 USBOTG TRIGXY ETD DMA Enable XY Trigger Request Register 0x084C USBOTG DMA EP CLR EP DMA Channel Clear Register 0 850 lt 8 __________ 0x0900 USBOTG ETDO START ADDR ETDO System Memory Start Address Register R
25. 0x0064 Bit Default Description Centrality Communications Inc 200 AT460A BI Developer s Manual Centrality Endpoint n IN Enabled When SET indicates that endpoint lt n gt is ready to respond to the host on the next IN token If there is not any data to be sent the Function Controller will respond with a NAK ODD R W When SET indicates that endpoint n is ready to respond to the host on the next OUT token If the Function Controller is unable to receive any data because the X and or Y Buffers are full it will respond with a NAK EVEN EPnOUT EN Endpoint n OUT Enabled USB OTG Endpoint Ready Set Register USBOTG FC EP READY 0x0068 t ODD EPnIN READY 1 bO Endpoint n IN Ready R W This register is directly written Writing a 1 to it will set it and a 0 will not affect it In order to clear this register a 1 must be written to the corresponding bit in the Frame Number Register Software must write to this bit to tell the Core whether or not the Endpoint is ready to be transferred If this bit is 0 and the EP is enabled then the function controller will return NAKs If this bit is 1 then the transfer will enabled EVEN EPnOUT READY 1 bO Endpoint n OUT Ready R W This register is directly written Writing a 1 to it will set it and a O will not affect it In order to clear this register a 1 must be written to the corresponding bit in the Frame Numb
26. 1 Memory 1 Enable 1 b0 Memory Window Mapping registers for Memory Window 1 disabled 1 b1 Memory Window Mapping registers for Memory Window 1 enabled When this bit is 1701 the Memory Window Mapping registers for the memory window 1 are enabled and the controller will be able to respond to memory accesses in the memory space defined by those registers 2 R W Memory 2 Enable 1 b0 Memory Window Mapping registers for Memory Window 2 disabled 1 b1 Memory Window Mapping registers for Memory Window 2 enabled When this bit is 1701 the Memory Window Mapping registers for the memory window 2 are enabled and the controller will be able to respond to memory accesses in the memory space defined by those registers 3 1 bO Memory Map3 Enable 1 b0 Memory Window Mapping registers for Memory Window 3 disabled 1 b1 Memory Window Mapping registers for Memory Window 3 enabled When this bit is 1701 the Memory Window Mapping registers for the memory window 3 are enabled and the controller will be able to respond to memory accesses in the memory space defined by those registers Memory Map4 Enable 1 b0 Memory Window Mapping registers for Memory Window 4 disabled 1 b1 Memory Window Mapping registers for Memory Window 4 enabled When this bit is 1701 the Memory Window Mapping registers for the memory window 4 are enabled and the controller will be able to respond to memory accesses in the memory s
27. 4 1280 Reserved e PWM Output Wait State Register PWM_WAIT lt 3 0 gt Name Default Description 31 WAIT 32780 Number of IO clock cycles that the PWM is R W high HI WAIT CNT 1 e PWM Hold State Register PWM_HOLD lt 3 0 gt Bit Name Default Description 31 0 LO HOLD CNT 3270 Number of IO clock cycles that the PWM R W is low LO WAIT CNT 1 Centrality Communications Inc 93 460 Developer s Manual LS Centrality COMMUNICATIONS 6 Graphic Display Subsystem 6 1 Overview Atlas II Graphic Display Subsystem is designed for applications like GPS Navigation Telematics systems PDAs and Smartphones It can support most of the popular LCD panels as well as the TV encoders And it has built in 2D Graphic Acceleration Hardware to improve the 2D Graphic performance 6 2 LCD Controller 6 2 1 Overview Atlas II LCD Controller supports the following features e Resolution up to 1024x1024 pixels e Support pixel depths of 8 16 bpp for main display layer and 8 16 bpp for the two overlay layers e Support following panels Maximum 18 bit output data can be used for non RGB muxed color TFT panel such 16 18 bit color TFT panel 8 bit RGB muxed TFT color panel e On chip RAMs for color palette or FRC sequence table the FRC supports up to 16 levels of grey scale for monochrome mode and 32 levels for every R G B of color mode e Integrated 3 channel
28. Centrality Vcount 0 Hcount 0 HSYNC PERIOD ra gt Horizontal Count HSYNC_WIDTH A coped _ m 5 SCN Layer 0502 Layer 5 z tH key 2 L IE 0 1 0 0 U H 0 1 H HPERIOD I H HPERIOD 1 V SES 2 V VPERIOD 1 V VPERIOD 1 H X HSTART H X_HSTART 1 H HPERIOD I H HPERIOD VSTART VSTART 227 UT V VPERIOD V VPERIOD H X HSTART H X_HSTART 1 V X_VSTART L V X_VSTART L H X_HEND 1 NEP UC V X VEND 2 V X VEND 2 X indicates SCN or H X HEND 1 H X HEND OSD or 0502 V X VEND 1 V X VEND 1 Figure 22 Screen and OSD Active Region One should understand as show in above figure only pixels inside the SCN 2D window will be visible that is OSD and 0502 layer will be clipped Horizontal start position for active screen LCD SCN HSTART 0x0 Description Horizontal Start Position in pixel number for the active LCD Name Default 10 7 SCN HSTART 11 hO R W display This value along with the horizontal end position and vertical start and end positions define the
29. Description AC97 playback channel enable decides right channel Bit1 decides left channel 1 channel is enabled 0 channel is disabled The playback channel enable register bits decide how the AC97 interface deals with 32 bit PCM data AC97 record channel enable Bit2 decides right channel Bit3 decides left channel 1 channel is enabled 0 channel is disabled The record channel enable register bits decide the source of record audio data AC97 warm wake control 1 warm wake AC97 CODEC 293 AT460A BI Developer s Manual Centrality 0 exit warm wake up mode WARM_WAKE should be set when BIT_CLK is absent The asserted WARM_WAKE signal set the SYNC to be HIGH to bring AC97 CODEC out of halted or low power mode 5 R W AC97 START 1 bO AC97 interface start control 1 97 interface is started to work 0 97 interface is stopped Before AC97 interface is started user needs to enables the channel once AC97_START is asserted AC97 interface begins to work Reseed _ _ 0 o AC97_WRITE_TAGH AC link output frame tag setting R W 3116 J 1600 AC97_WRITE_TAGH is used to control the AC link output frame The tag of output frame is decided by AC97_WRITE_TAGH user needs to program the register before play audio data stream or issue command to AC97 CODEC Table 77 97 WRITE TAGH Description Bit Default Description 15 R W Frame Valid 1 bO 1 7 Indicates that the o
30. Due to the pipeline nature of the RISC core after the Boot up register been set user CANNOT access the ROM address space at once It needs to insert at least one NOP between them Bit Name Default Description O R W COLD BOOT Set to 1 when system is cold boot up 1 R W WARM Set to 1 when system is warm boot up 312 7 3050 RISC Interface Wait States Register RISCINT WAIT1 0x0010 RISC read cycle can be inserted with up to 16 wait states There are 4 different wait values to be set at the same time Each value is for some group of internal devices Bit Name Default Description Interrupt Controller om interface Graphic controller and memory controller p states number used OS Timer RW ae Wait states number used by Power Manager and RW Resource Sharing Controller Reset Controller and Real time Clock RISC Interface Wait States Register RISCINT WAIT2 0x0014 RISC I O read cycle can be inserted with up to 16 wait states There are 4 different wait values to be set at the same time Each value is for some group of internal devices Bit Name Default Description Centrality Communications Inc 18 460 Developer s Manual Centrality R W Controller and USP5 R W and USPO USPA R W GPIO RISC Interface Width Control Register RISCINT WIDTH 0x0018 RISC I O Bus can access two different
31. RISC 0x0028 DSP 0x014 0x015 The DSP interrupt controller level register INT DSP LEVEL controls whether a pending interrupt generates an IRQL1 or an IRQLO DSP interrupt If a pending interrupt is unmasked the corresponding INT LEVEL bit field is decoded to select which interrupt should be asserted If the interrupt s mask bit is 0 then the corresponding bit in the INT LEVEL has no effect The following table shows the location of all interrupt level bits in the INT LEVEL question marks indicate that the values are unknown at reset Centrality Communications Inc 63 460 Developer s Manual e Centrality Name Default Description 31 2 DIL lt 31 0 gt 32 hO ae Interrupts level bits W R Interrupt routed to IRQLO interrupt input i Interrupt routed to DSP IRQL1 interrupt input e Interrupt Controller RISC Mask Extended Register INT RISC MASK EXT RISC 0x002C Bit Name Default Description 0 W R RME lt 0 gt 1 bO Interrupt extended mask register bit for PCMCIA in IP11 0 Pending interrupt is masked from becoming active 1 Pending interrupt is allowed to become active Same as following 1 W R lt 1 gt Interrupt extended mask register bit for EXTPORT 11 2 W R RME lt 2 gt Interrupt extended mask register bit for Camera in IP15 Reserved 4 W R RME lt 4 gt Interrupt extended mask register bit for LCD Controller in IP24 Interrupt extended mask
32. 1 bit mode 2 1 bO This bit is optional Before setting this bit the HD shall check the HIGH SPEED SUPPORT in the Capabilities register If this bit is set to 0 default the HC outputs CMD line and DAT lines at the falling edge of the SD clock up to 25 MHZ If this bit is set to 1 the HC outputs CMD line and DAT lines at the rising edge of the SD clock up to 50 MHz 1 High Speed Mode 0 Normal Speed Mode 1 o Reseved 8 R W SD BUS PWR 1 bO Before setting this bit the SD host diver shall set SD BUS VOL SEL If the HC detects the No Card State this bit shall be cleared 1 Power on 0 Power off 11 9 SD BUS VOL SEL 1 bO By setting these bits the HD selects the voltage R W level for the SD card Before setting this Centrality Communications Inc 171 AT460A BI Developer s Manual Centrality STOP_AT_BLK_GAP_ This bit is used to stop executing a transaction REQ at the next block gap for transfers Until the transfer complete is set to 1 indicating a transfer completion the HD shall leave this bit set to 1 Clearing both the STOP_AT_BLK_GAP_REQ and CONTINUE_REQ shall not cause the transaction to restart Read Wait is used to stop the read transaction at the block gap The HC shall honor STOP AT REQ for write transfers but for read transfers it requires that the SD card support Read Wait Therefore the HD shall not set this bit during read transfers unless
33. 2 0001001 eene 10 Centrality Communications Inc 4 AT460A BI Developer s Manual Centrality 9 4 14 Lcd 10 9 4 15 Specificatioris rire terrere esie sete eens 10 9 4 16 Nans cam Specifications eene nennen 10 9 4 17 Ide Specifications sec 10 9 4 18 GPIO Specifications 10 9 4 19 Serial Port Specifications sss eene 10 9 4 20 CANBUS AC Specifications 10 9 4 21 PCMCIA AC Specifications 10 9 4 22 USBOTG AC Specifications 1 0 01 nene 10 9 4 23 SDIO AC ener nennen a e 10 9 4 24 JTAG AC e at ete e ee TR 10 10 Revision 10 Centrality Communications Inc 5 AT460A BI Developer s Manual LS Centrality COMMUNICATIONS Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24
34. Bit Name Default Description SMDF timing 3 0 R W RD_PULSE 4 b0000 The pulse width of read signal of 30 ns NAND Flash 0 one IOCLK 1 two IOCLK 11 8 R W WAIT 4 b0010 The width between WE high to 100 ns Busy 0 one IOCLK 1 two IOCLK 12 R W RD WT HI The write or read signal high hold 7 4 R W WT PULSE 4 b0000 The pulse width of write signal of 25 ns NAND Flash 0 one 1 two IOCLK Centrality Communications Inc 264 AT460A BI Developer s Manual Centrality time 0 one IOCLK 1 two IOCLK O 31 13 19 hO Flash Bank Select Register SM BANK SEL 0x08 Bit Name Default Description 3 0 R W BANK_SEL lt 3 0 gt 201110 Select bank of NAND Flash 1110 first chip 1101 second chip 314 258 Reserved Flash Address Mode Register SM ADD NUM 0 0 Bit Default Description 2 0 R W ADD_MODE lt 2 0 gt 35100 Number of address bytes 00 0 bytes address 01 1 bytes address 11 3 bytes address 100 4 bytes address 313 _________ 2910 ___ Reserved Flash Command Register SM CMD 0x10 Write this register will start FSM If there is no second command bit 15 8 must be 8 or it will cause the FSM run into wrong state Bit Name Default Description CMD lt 7 0 gt Command to be written to NAND Flash 15 8 R W CMD2 lt 7 0 gt 870 Second command write to NAND Fla
35. CODEC auxiliary RXFIFO level check OxOBDO CODEC RX AUX FIFO OP CODEC auxiliary RXFIFO operation OxOBDA4 CODEC RX AUX FIFO STS CODEC auxiliary RXFIFO status register enable OxF7C 4 1 Resewed OxOF94 CODEC TX FIFO STS CODEC TXFIFO status register OxOF98 CODEC TX FIFO INT EN CODEC TXFIFO interrupt enable OxOF9C FB Reserved C Others e CODEC share register CODEC SHARE 0x0 CODEC interface supports AC97 audio formats CODEC SHARE is used to control whether record channel or playback channel in the Audio CODEC interface is enabled Default Description INTERLACE MODE CODEC interlace mode selection 0 The 32 bit audio data is in L R format that s the MSB 16 bit is from left channel and the LSB 16 bit is from right channel 1 The 32 bit audio data is in R L format the MSB 16 bit is right channel and the LSB 16 bit is left channel 5 a Saree AD_IDLE 1 b1 AC97 record channel status setting 1 AC97 record channel is shut down in CODEC interface no audio data stream can be recorded 0 AC97 record channel is enabled in AC97 interface input audio data stream is allowed to be recorded By default the AC97 record channel is shut down before recording audio data stream from AC97 CODEC user needs to clear this register bit Centrality Communications Inc 292 AT460A BI Developer s Manual Centrality 6 R W AC97_DA_IDLE The A
36. Color Key is a color or a range of colors defined as transparent Centrality Communications Inc 120 AT460A BI Developer s Manual Centrality The SCN color key register is for test purpose only software should not enable this Bit Default Description SCN_CKEYB 18 h0 Bigger value of color key for SCN channel display R W 19 18 250 20 SCN CKEY EN 1 bO 1 7 Color key function for SCN is valid R W 0 Color key function for SCN is invalid 21 SCN CKEY SEL 1 bO 1 8 bit index color mode In this mode only bit 7 0 of R W SCN CKEYB and SCN CKEYS are valid for the 8 bit index 0 18bit 6 6 6 color mode This can be used for 2 bit index 4 bit index 8 bit index 16 bit 5 6 5 5 5 6 6 5 5 and so on This mode is flexible but needs to calculate SCN CKEYB and SCN CKEYS values according to different data formats For 16 bit data format the 18bit CKEYB or CKEYS are calculated by expanding Red Green or Blue to 6bits and set the expanded LSB to 1 b0 31 22 108 e SCN color key small RGB value LCD SCNCKEYS 0x90 This register is for test purpose only Bit Name Default Description SCN_CKEYS 18 h0 Smaller value of color key for SCN channel display R W 3118 e OSD color key big RGB value LCD OSDCKEYB 0x94 Bit Default Description OSD_CKEYB 18 h0 Bigger value of color key for OSD channel display R W 1938 f 2 1480 20 OSD CKEY EN
37. UNE E LBA lt 7 0 gt LBA lt 7 0 gt __ UNION LBA lt 15 8 gt LBA lt 15 8 gt LBA lt 23 16 gt LBA lt 23 16 gt LBA lt 27 24 gt LBA lt 27 24 gt ___ __ 7 Status Command ____ Control Status Alternate __ Device Control The address space 0x3F0 3F7 is shared with the floppy disk controller Ox3FO 3F5 is used by the floppy disk controller Ox3F6 is used by the IDE Primary channel for alternate status device control and Ox3F7 is a shared register Data lt 7 gt is driven by the floppy disk controller and Data lt 6 0 gt is driven by the IDE device To resolve this conflict newer systems do not respond to address 0x03F7 the access being passed to the floppy disk controller For Atlas II IDE Controller it has been decided to respond only to address Ox3F6 7 7 PCMCIA CF Interface 7 7 4 Overview The PCMCIA CF interface integrated in Atlas II is the same as the one in Atlas I The PCMCIA master M6730 in Atlas II allows the processor to communicate with other peripherals via the PCMCIA CF interface The M6730 PCMCIA master is a PCI to PC Card host adapter solution from VirtuallP Group It is compatible with PC Card standard PCMCIA 2 1 and JEIDA 4 1 It provides suspend mode that stops transactions on the PC Card bus and turn off much of the internal circuitry It provides fully buffered interface which eliminates the need for external logic re
38. 0 Reserved e CODEC Operation Register CODEC AUX FIFO OP 0XBDO Bit Default Description 0 FIFO START Start the read write transfer when this bit is declared 1 R W FIFO RESET 1 bO Internally link to FIFO START INI Set to 1 to stop the FIFO and reset the FIFO internal status including the relevant interrupt status Set to 0 in normal operation 312 ____ S30no ___ 2 e AUX CODEC RXFIFO Status Register CODEC AUX FIFO STS 0xBD4 This register indicates the auxiliary RX FIFO status Bit Default Description 0 R W RX_AUX_FIFO_FULL 1 b0 Auxiliary RX FIFO full status 1 AUX RX FIFO is in full state Centrality Communications Inc 299 AT460A BI Developer s Manual Centrality 0 AUX RX FIFO is not in state It indicates the current auxiliary RX FIFO full status Once the FIFO status changes the status bit is cleared automatically 1 R W RX_AUX_FIFO_EMPTY 1 50 Auxiliary RX FIFO empty status 1 AUX RX FIFO is in empty states 0 AUX RX FIFO is not in empty states It indicates the current auxiliary RX FIFO empty 1b 1b status Once the FIFO status changes the status bit is cleared automatically RX AUX FIFO OFLOW Auxiliary RX FIFO overflow status 1 AUX RX FIFO overflow takes place 0 AUX RX FIFO is not overflow User can write 1 b1 to clear the register bit after the RX FIFO
39. 0001 TMCLK 2414 0000 TMCLK 2413 2322 _ ___________ __ ____ O 24 SOFT_RST_ALL 1 bO This reset affects the entire HC except for the R W card detection circuit Register bits of type ROC RW RW1C RWAC are cleared to 0 During its initialization the HD shall set this bit to 1 to reset the HC The HC shall reset this bit to O when capabilities registers are valid and the HD can read them Additional use of SOFT RST ALL may not affect the value of the Capabilities registers If this bit is set to 1 the SD card shall reset itself and must be reinitialized by the HD 1 Reset 0 Work 25 SOFT RST CMD Only part of command circuit is reset The R W following registers and bits are cleared by this bit SD CUR STATE register CMD CMD SD INT STATUS register Centrality Communications Inc 175 AT460A BI Developer s Manual Centrality END 1 Reset 0 Work SOFT_RST_DAT 1 bO Only part of data circuit is reset The following R W registers and bits are cleared by this bit SD BUF DATA register is cleared and Initialized SD CUR STATE register BUFF RD EN BUFF WT EN RD TRAN ACTIVE WT TRAN ACTIVE DAT LINE ACTIVE CMD INHIBIT DAT SD HOST Oregister CONTINUE REQ STOP AT BLK GAP REQ SD INT STATUS register BUFF RD READY BUFF WT READY BLK GAP EVT TRAN END 1 Reset 0 Work 3127 2 NOTE At the initialization of the HC the HD shall set th
40. 0x05 Index This register control which status change cause management interrupts as well as to which output signal the interrupt will go Default 1 bO BATT DEAD EN ST ST CHG EN BATT WARNING E N Centrality Communications Inc Description Battery dead or status change enable 1 b0 Battery Dead Or Status Change management interrupt disabled 1 b1 If Battery Dead Or Status Change bit is1b1 a management interrupt will occur When this bit is 1701 a management interrupt will occur when the Card Status Change register s bit O is set to 1 b1 This allows management interrupts to be generated on the changes the bvd nstschg nri input signal from the PC card Battery Warning Enable 1 b0 Battery Warning Change Management Interrupt disabled 1 b1 If Battery Warning Change bit is1 b1 a management interrupt will occur When this bit is 1 b1 a management interrupt will occur when the Card Status Change 232 AT460A BI Developer s Manual Centrality COMMUNICATIONS 2 R W RDY_EN 3 R W CARD_DET_EN register s bit 1 is set to 1 b1 This bit is not valid on I O PC card interface Ready Enable 1 b0 Ready Change Management Interrupt disabled 1 b1 If Ready Change bit is1 b1 a management interrupt will occur When this bit is 1 b1 a management interrupt will occur when the Card Status Change register bit 2 is set to 1 b1 This allows interrupts to be generated on the ch
41. 2 o Output Divider Value NO See Note NO OD 1 e PLL Output Frequency Setting Four NF NR X FiN Meanwhile the following constraints must be followed 1 Due to the speed limitation of our clock circuit the PG13A1G3 should not be programmed to be over 500MHz in worst case or 600MHz in best case FOUT is uncertain in Power Down mode Tready 0 5ms When OD 1 FOUT would have around 50 duty cycle So it s suggested to set OD 1 if it s possible Centrality Communications Inc 42 460 Developer s Manual LS Centrality COMMUNICATIONS 10 2 lt lt 50MHz where Frer Fin NR See Note 5OOMHz lt Fvco lt 1000 2 where Fvco Fin NF NO NR gt 63 NO For example if we want to get 252MHz output frequency clock when using 12MHz crystal oscillator as input NR 1 NF 21 NO 2 Fyco 504 2 Four 252MHz F lt 5 0 gt 19 0x13 R lt 3 0 gt 0 OD 1 PG13A1G3 requires 3 pairs of power supply in two different voltages 1 2V 3 3V as following AHVDD AHVSS Analog Power 3 3V amp Ground e AHVDDG AHVSSG Analog Power 3 3V amp Ground DVDD DVSS Digital Power 1 2V amp Ground In system design all power AHVDD AHVDDG and DVDD and ground AHVSS AHVSSG and DVSS should be considered as analog power DO NOT share these power ground with any other power ground planes in the system 5 2 5 2 PG13E3G 400MHz PLL PG13E3G is d
42. 256 DRAM Controller IO pins use the multi voltage multi functional programmable IO This kind of IO is special designed so that it can be configured to different modes as following e 1 8V LVCMOS mode e 2 5V SSTL mode e 2 5V LVCMOS mode e 3 3V LVCMOS mode For details about how to configure these modes please refer to the section of Mode Configuration Pins 4 3 2 DDR Connection Examples The following figures show the examples of configuration of 16 bit and 32 bit memory interface with16Mx16 DDR or SDRAM Centrality Communications Inc 31 AT460A BI Developer s Manual KE Centrality COMMUNICATIONS X MCS 1 0 X MCLK X MCLK B X X MCAS X MRAS X X MDQS 3 0 X MDQM 3 0 X lt 12 0 gt X lt 1 0 gt X lt 31 0 gt 16M 16 DDR x Mcs o CS CK ANE 5 RAS lt 1 0 gt lt 12 0 gt DQ lt 15 0 gt lt kuasa DQSH DQSL xwbaws DOMH Figure 5 DDR Connection in 16 bit Mode X 5 lt 1 0 gt X MCLK X MCLK B X MWE X MCAS X MRAS X 05 lt 3 0 gt a JC a X MDQM 3 0 2 42 lt 12 0 gt lt 1 0 gt S a Hi X 0 0 16M 16 16M 16 DDR DDR X_MCS lt 0 gt 5 lt 0 gt l NJ CK CK CKE CKE m cAS cAs nS IL lt 1 0 gt lt 12 0 gt x DQ
43. 7 0x0024 f Reserved 7 Ox0028 0x002C CANBUSn ALC CANBUS Arbitration Lost Capture Register 0x0030 CANBUSn ECC CANBUS Error Code Capture Register 0x0034 CANBUSn EWLR CANBUS Error Warning Limit Register Centrality Communications Inc 329 460 Developer s Manual Centrality Register 0x003C CANBUSn_TXERR CANBUS Transmit Error Counter Rege Note Read Back from 0x180 0x1B0 RegistersO Registers Registers2 Registers3 RegistersO Registers Registers2 Registers3 Registers Address Register 0 007 _______________ Reserved 2 0x0080 0x017C CANBUSn_RFIFO CANBUS Receive FIFO Other Reserved NOTE 1 0 1 2 The registers marked gray are only valid in Reset Mode e CANBUS Mode Register CANBUSn_MODE 0x0000 Bit Name Default Description 0 R W 1 b1 1 Reset Mode selected Any message currently being transmitted or received is aborted and Reset Mode is entered 0 Normal operation The CANBUS controller returns to Operating Mode on the 1 to 0 transition of this bit 1 R W LOM 1 bO 1 Listen Only enabled In this mode the CANBUS controller does not send an acknowledge to the CAN bus even when a message is received successfully 0 Normal operation The error counters are stopped at the current value 1 Self Test enabled In this mode a full node test is possible without any other active nod
44. 70 e OSD FIFO Control Register LCD OSDFIFO 0xC4 Bit Name Default Description 6 0 co LO 7 h60 Value for the low request watermark for the OSD FIFO If R W the FIFO is filled beyond this mark then the request stops If the FIFO is read below this point then the request becomes low level request Z J sve l 14 8 OSD_MI_CHK 7140 Value the middle request watermark for the OSD FIFO R W If the FIFO is filled beyond this mark then the request drops to low level request If the FIFO is read below this point then the request becomes high level request 16 SSO ACS HI_CHK 7120 Value the high request watermark for the OSD FIFO R W the FIFO is filled beyond this mark then the request an to high level request If the FIFO is read below this point then the request becomes critical LSU REG SEL REQ SEL 1 b0 Selection of request generation method for OSD FIFO R W 1 Only high request and low request watermark are useful request value can be as 2 b00 and 2b 11 If the FIFO is read below high request watermark then the request becomes critical and if the FIFO is filled beyond low request watermark then the request stops As in critical request status the DMA bandwidth is a little lower using this mode will save some bandwidth 0 Normal request generation Three watermarks are all useful request value be as 2100 2 b01 2b 10 2b 11 31 25 710
45. AT460A BI Developer s Manual KE Centrality COMMUNICATIONS 0x0018 DMA_CH1_YLEN 0x001C DMA 1 CTRL 0x0020 DMA CH2 ADDR 0x0024 DMA CH2 XLEN 0x0028 DMA CH2 YLEN 0x002C DMA CH2 CTRL 0x0030 CH3 ADDR 0x0034 DMA CH3 XLEN 0x0038 DMA CH3 YLEN 0x003C DMA CH3 CTRL 0x0040 DMA 4 ADDR 0x0044 DMA 4 XLEN 0x0048 DMA 4 YLEN 0 004 DMA_CH4_CTRL 0x0050 DMA 5 ADDR 0x0054 DMA 5 XLEN 0x0058 DMA CH5 YLEN 0x005C DMA 5 CTRL 0x0060 DMA CH6 ADDR 0x0064 DMA CH6 XLEN 0x0068 DMA CH6 YLEN 0x0070 CH7 ADDR 0 0074 DMA_CH7_XLEN 0 0078 DMA_CH7_YLEN 0 007 DMA_CH7_CTRL 0x0080 DMA_CH8_ADDR 0x0084 DMA_CH8_XLEN 0x0088 DMA CH8 YLEN DMA channel 8 Y length register 0x008C DMA CH8 CTRL DMA channel 8 control register 0x0090 0x48 0x49 DMA CH9 ADDR DMA channel 9 address register 0x0094 DMA CH9 XLEN DMA channel 9 X length register 0 006 DMA_CH6_CTRL 0x0098 DMA_CH9_YLEN 0x009C DMA CH9 CTRL Ox00A0 DMA_CH10_ADDR Ox00A4 DMA_CH10_XLEN 0x00A8 DMA CH10 YLEN 0 00 DMA_CH10_CTRL 0x00B0 DMA_CH11_ADDR 0 0084 DMA_CH11_XLEN 0 0088 DMA_CH11_YLEN 0 00 DMA_CH11_CTRL Others 0x0100 DMA WIDTHO 0x0104 DMA WIDTH1 0x0108 DMA WIDTH2 0 010 DMA_WIDTH3 0x0110 DMA CH VALID 0x0114 DMA CH INT Centrality Communications Inc 259 460 Developer s Manual Centrality 0 0118 DMA INT EN DMA interrupt enable register 0x011C CH channel DSP
46. Centrality Communications Inc 324 AT460A BI Developer s Manual Centrality e USP TX FIFO level check register USP TX FIFO LEVEL 9 0x10C DSP 0x46 0X47 B Name Default Description it lt 2 0 gt FIFO_SC lt 9 0 gt 3 hO Stop check in DWORD R W 12 10 FIFO LC 9 0 Low check in DWROD R W 38 22 20 FIFO_HC lt 9 0 gt 3 hO High check in DWORD R W lt 31 23 gt 9h0 Reserved e USP TX FIFO operation register USP TX FIFO OP ARM9 0x110 DSP 0x48 This register is different from FIFO of other peripheral operation register and reset bit is at bit 0 Bit Name Default Description 0 R W FIFO RESET 1 bO Set to 1 to stop the FIFO and reset the FIFO internal status including the relevant interrupt status Set to 0 in normal operation 1 R W FIFO START 1 bO Start the read write transfer when this bit is declared 33122 300 e USP TX FIFO status register USP_TX_FIFO_STATUS 9 0 114 DSP 0 4 Bit Name Default Description 4 0 R FIFO LEVEL 5710 The byte number of the valid data in the FIFO In case that FIFO is full the value of this register is 0 thus user must concatenate FIFO FULL bit with this value to determine the actual data count in the FIFO 5 FIFO_FULL 1 bO FIFO full status the FIFO is full when read out as 1 This bit is concatenated with FIFO_LEVEL to be the actual FIFO data cou
47. For 97 interface there are 12 slots for data transfer The PCM data for left channel and right channel is transferred through AC link slot3 and slot4 which takes Atlas PCM DMA channel DMA channel 6 and 7 Atlas provides a pair of auxiliary DMA channel channel 8 and channel 9 for other slots data transmission through AC link DMA channel 8 is for data in and DMA channel 9 is for data out User can configure AC97 interface to specify which slots is used for auxiliary data in and which for auxiliary data out 8 6 6 3 AC97 Controller The Atlas l AC97 Controller communicates with its companion AC97 audio codec via AC link digital serial interface and it supports the most common point to point AC link connection between controller and CODEC The AC97 CODEC derives its clock internally from an external attached 24 576MHz crystal and drives a buffered and divided down 1 2 clock to its digital controller over AC link under the signal name The beginning of all audio sample frames transferred over the AC link is synchronized to the rising edge of the SYNC signal SYNC is driven by Atlas II AC97 Controller it takes as input and generates the SYNC by dividing BIT CLK by 256 and applying some conditioning to tailor its duty cycle This yields a 48 KHz SYNC signal whose period defines an audio frame Data is transferred over AC link on every rising edge of and subsequently sampled on the
48. INT MASK 0x1C04 Default Description SINGLE BLT OVER INT MASK 1 hO Mask for interrupt when one single BitBLT a command completed QUEUED OVER INT MASK Mask for interrupt when the whole queued E BitBLT commands completed 312 e BitBLT interrupt and status INT STATUS 0x1C08 Description um der W R this bit by writing zero Pn E rr W R bit by writing zero 15 2 __ 140 16 BLT_BUSY 1 hO On when is assigned and cleared when BitBLT R finished 3117 _ 2415 Centrality Communications Inc 141 AT460A BI Developer s Manual Centrality SRC BASE x xy 0 0 x SRC XY TWOD HEIGHT TWOD WIDTH line pixel 4 gt SRC_STRIDE SRC buffer line width in pixel 4 gt SRC buffer DES_BASE x gt xy 0 0 JA DES XY gt TWOD HEIGHT TLXY line 8 7 TWOD_WIDTH pixel 8 CLIP_BRXY DES STRIDE DES buffer line width in pixel gt DES buffer Figure 31 BitBLT 2D window dimension Source Base Address in SDRAM BLT_SRC_BASE 0 1 0 Bit Name Default Description 26 0 SRC_BASE 2710 base memory address of source with byte address R W alignment the pixel whi
49. It indicates the current RX FIFO full status Once the FIFO status changes the status bit is cleared automatically 1 R W RX_FIFO_EMPTY 150 RX FIFO empty status 1 RX FIFO is in empty states 0 RX FIFO is not in empty states It indicates the current RX FIFO empty status Once the FIFO status changes the status bit is cleared automatically 2 R W RX FIFO OFLOW RX FIFO overflow status 1 RX FIFO overflow takes place 0 RX FIFO is not overflow User can write 1 b1 to clear the register bit after the RX FIFO overflow takes place 3 R W UFLOW 150 RX FIFO underflow status 1 RX FIFO underflow takes place 0 RX FIFO is not underflow 28 User needs to write 1 b1 to clear the register bit after the RX FIFO underflow takes place 314 280 __ Reserved e CODEC RXFIFO Interrupt Enable Register CODEC RX FIFO INT OxFD8 Bit Name Default Description 1 RX FIFO full interrupt is enabled 0 RX FIFO full interrupt is enabled 1 RX FIFO empty interrupt is enabled 0 RX FIFO empty interrupt is disabled 3 1 RX FIFO overflow interrupt is enabled 0 RX FIFO overflow interrupt is disabled 50 2 R W RX FIFO OFLOW EN 1 1 3 R W UFLOW 1 RX FIFO underflow interrupt is enabled 2 0 FIFO underflow interrupt is disabled 314 HO Reserved 8 7 UART Centrality Communications Inc 303 460 Developer s Manual Centr
50. No Error 1 Timeout 17 CMD CRC ERR CMD CRC ERR is generated in two cases R W 1 If a response is returned and the CMD TIMEOUT ERR is set to O this bit is set to 1 when detecting a CRC error in the command response 2 The HC detects a CMD line conflict by monitoring the CMD line when a command is issued If the HC drives the CMD line to 1 level but detects 0 level on the CMD line at the next SDCLK edge then the HC shall abort the command Stop driving CMD line and set this bit to 1 The Command Timeout Error shall also be set to 1 to distinguish CMD line conflict 0 No Error 1 CRC Error Generated CMD_ENDBIT_ERR Occurs when detecting that the end bit of a command response is 0 0 No Error 1 End Bit Error Generated 18 R W 19 CMD INDEX ERR Occurs if a Command Index error occurs in R W the Command Response 0 No Error 20 1 3 1 Error DAT TIMEOUT ERR Occurs when detecting one of following R W timeout conditions 1 Busy Timeout for R1b R5b type 2 Busy Timeout after Write CRC status 3 Write CRC status Timeout 4 Read Data Timeout 0 No Error 1 Timeout 2 DAT CRC ERR Occurs when detecting CRC error when R W transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 010 0 No Error 1 Error 22 DAT ENDBIT ERR Occurs when detecting 0 at the end bit RAW position of read data that use
51. PIN register determines whether USP2 or UART6 have control over the two last pins the other pins are controlled by USP2 e USP3 UART7 Pin Mux Pin Name USP3 UART7 GPIO XSCLK 3 J OPIO group2 offseto 2 X 3 GPIO group2 offset 2 3 X TXD 7 GPIO group2 offset 3 IXRFS3 XRXD7 GPIO group2 offset 4 After reset GPIO will have control over these pins User can write corresponding GPIO control registers to give the control of these pins to USP3 UART7 The priority of the above shared functions is as following e If GPIO has control over these pins both USP3 UART7 can not control the pin e Else if GPIO does not have control over these pins the USP_EN lt 1 gt bit in 5 PIN register determines whether USP3 or UART7 have control over the two last pins the other pins are controlled by USP3 e USP4 USP5 SD PCMCIA Part 1 Pin Mux Pin Name SDIO PCMCIA USP4 5 IX TXD4 2 group offset 6_ PoC PIO group offset 7_ X RXD 4 RFS 4 SD lt 3 gt PA 21 GP IO group2 offset9 XTXD5 GPIO group offset 11 Centrality Communications Inc 78 460 Developer s Manual Centrality XRXD5 GPIO group2 offset 12 X TFS 5 SD CMD lt 24 gt GPIO group2 offset 13 X RFS 5 SD lt 3 gt lt 20 gt GPIO group2 offset 14 After reset GPIO will h
52. USBOTG EP TRIGXY EN 0x0834 Bit Default Description 31 0 W EPDMAXYTEN 32 h0 Endpoint DMA X and Y Trigger Enable Writing a 1 sets the corresponding EndpointDMAEnable bit and causes both XTrigger and Y Trigger for the client e USB OTG ETD DMA Burst4 Enable Register USBOTG BURSTA EN 0x0838 This Register is set by default for all clients The DMA will transfer words on the AHB using the INCR4 transfer size burst of 4 DWORDS If for some reason a source destination of the DMA transfer cannot handle bursts of 4 DWORDS the corresponding bit should be cleared to transfer one word at a time Bit Default Description 31 0 ETDDMABST4EN 32 hFFF ETD DMA Burst 4 Enable R W FFFFFF Centrality Communications Inc 212 460 Developer s Manual Centrality e 5 Endpoint Burst4 Enable Register USBOTG_DMA_EP_BURST4_EN 0x083C This is set by default for all clients The DMA will transfer words on the AHB using the INCR4 transfer size burst of 4 DWORDS If for some reason a source destination of the DMA transfer cannot handle bursts of 4 DWORDS the corresponding bit should be cleared to transfer one word at a time Name Default Description 31 2 EPDMABST4EN 32 hFFF Endpoint DMA Burst 4 Enable R W FFFFF e USB OTG Miscellaneous Control Register USBOTG MISC 0x0840 Bit Name Default Description 0 R W FILTCC 1 bO Filter o
53. VS 2 1 PCMCIA VCC PCMCIA Power Controller VCC33 VCC5 VCC12 Figure 45 Connect to Compact Flash Card 7 7 7 PCMCIA Memory Mapping Centrality Communications Inc 224 AT460A BI Developer s Manual Centrality 0 5700 64K I O Space 0x57C0_0000 OxFFFF_FFFF Ox3FF FFFF P 0 3000_0000 ae Space X LA VM VM 0x000 0000 0x2000 0000 ae pace x include PC card address space Registers 0x0000_0000 Atlas II System Address M6730 PCI Address Space Figure 46 PCMCIA Memory Mapping The PCMCIA memory can be divided into three parts e Register Space e PC card I O Space e PC card Memory Space 7 7 7 1 Register Space The registers in M6730 module are used to configure the PCMCIA interface memory remapping and control the access timing of PCMCIA interface They are accessed through PCI I O mode M6730 requests a I O base address which is mapped to be 0 57 0 0000 Atlas II In order to save memory space all M6730 registers are operated by accessing the base address through index In write operation you should program the register index and data into PCMCIA Configuration Register first The lower 8 bits is the index number and the higher 8 bits is the data value After you programmed this register the M6730 will write the value into the register according to the index number internally I
54. break interrupt enable 0 disabled 1 enabled 2 R W RX_TIMEOUT_INT_EN receive timeout interrupt enable 1 enabled 13 R W MODEM_STATUS_INT_EN 1 bO Modem status interrupt enable 1 enabled 3144 __ LLL 18h0 UART Interrupt Status Register UART INT STATUS RISC 0x58 DSP 0x2C RISC DSP writes a 1 b1 to the bit will clear that interrupt except MODEM STATUS CHG bit any read operation to MODEM CTRL STATUS register will clear this bit Bit Default Description 0 R W E 50 A valid data has been received in the RXFIFO interrupt the valid data length is define by the RXFIFO_WIDTH 0 invalid 1 valid RW TX DONE A valid data has been transmitted from the TXFIFO interrupt the valid data length is define by the TXFIFO WIDTH 0 invalid 1 valid 2 R W RX OFLOW 1 bO RXFIFO overflow Interrupt 1 valid 3 R W TX ALL EMPTY 1 b0 all the data in both TXFIFO and tx shifter are sent out interrupt 0 invalid 1 valid 4 R W DMA IO RX DONE 1 50 RXFIFO has received all data of the data package whose SIZE is defined by UART_RX_DMA_IO_LEN register 0 invalid 1 valid 5 R W DMA IO TX DONE 1 bO TXFIFO has transmitted all the data of a data package whose SIZE is defined by UART TX DMA LEN register 0 invalid 1 valid 6 R W RXFIFO FULL 1 bO RXFIFO full interrupt 0 invalid 1 valid 7 TXFIFO EMPTY TXFIFO empty interrupt 0 invalid 1 valid pew mero 0
55. 00241 nnne nnns 10 I O Bridge Register Mapping nennen nnns 10 FIFO Requests Level 10 DMA Controller Register 10 Flash Interface Signal Descriptions 10 Flash Interface Register nemen 10 YUV YGrGCb 4 2 2 16 bit format one im cune ote ect tt 10 YUV YCrCb 4 2 2 8 bit format eene eene nennen 10 Shift example eee 10 YUV2RGB Conversion Coefficent sss enne nnns 10 Video Input Port Register 10 AC97 CODEC Interface Pin 10 A 10 651 RED eed dud tibi qe re 10 Input ette 10 Audio CODEC Register Mapping emen enne nnns 10 AC97 WRITE 0 011 nnnm 10 Descriptioris 22 3 excite eco e he ERES 10 UART Register Mapping 02020044204 010 eden 10 USP Pin edit tette date eei 10 SP Register Mappirig A eet ae at as 10 CAN Bus Pin Description siis
56. 0x0128 0x012C LCD OSD ADDR Current DMA Address for the OSD Display C 0x0144 LCD 0502 ADDR Current DMA Address for the OSD2 Displa 0x0180 LCD_INT CTRL Interrupt Status and Clear register 0x0184 LCD_INT_MASK Interrupt Mask 0x0188 LCD _ SCN INT LINE Interrupt Line Number 0x0120 LCD OSD YSIZE Y Size for OSD DMA 0x0124 LCD OSD SKIP Skip value for OSD DMA 0x1000 0x13FC LCD_ PALETTE Read Write 256 entry Palette 0x1400 0x143C LCD PALETTE16 Read Write 16 entry Palette 0x1800 0x18FC LCD COLORSEQ Read Write 32x64 Color Dithering Sequence Others Reserved 6 2 4 1 Screen and OSD Active Region Definition Registers The active region of the LCD display is specified by a rectangle defined by two coordinates the horizontal and vertical start position and the horizontal and vertical end position as shown in the diagram below The LCD display contains internal counters which will count pixels by pixel clock and lines by horizontal sync The pixel count is cleared by horizontal sync and line count is cleared by vertical sync Note For display a SCN OSD or OSD2 active region of M pixels x N lines following conditions must be satisfied 1 MzLCD SCN HEND LCD SCN HSTART 1 or LCD OSD HEND LCD OSD HSTART 1 or LCD OSD2 HEND LCD OSD2 5 1 2 NzLCD SCN VEND LCD SCN VSTART or LCD OSD VEND LCD OSD VSTART or LCD OSD2 VEND LCD OSD2 VSTART Centrality Communications Inc 103 AT460A BI Developer s Manual
57. 2 pur PIXEL DATA Figure 24 LCD Alteration Signals Waveform e Period for Master Mode Horizontal Sync LCD HSYNC PERIOD 0x30 Description HSYNC PERIOD 11 hO For master mode where Atlas II Processor generates the Centrality Communications Inc 108 AT460A BI Developer s Manual Centrality R W sync signals this value defines the period of the horizontal sync pulse in number of pixels If this register is set to 60 then the period of the sync is 62 pixel clocks For slave mode this register has no effect 1270 e Width for Master Mode Horizontal Sync LCD HSYNC WIDTH 0x34 Bit Default Description 10 0 HSYNC WIDTH 11 hO For master mode where Atlas Processor generates the R W sync signals this value defines the width minus 1 of the horizontal sync pulse in number of pixels If this register is set to 8 then the width of the sync pulse is 9 pixel clocks For slave mode this register has no effect 3111 __ Reserved e Period for Master Mode Vertical Sync LCD VSYNC PERIOD 0x38 Bit Name Default Description 10 0 VSYNC PERIOD 110 For master mode where Atlas I Processor generates the R W sync signals this value defines the period of the vertical sync pulse in number of lines For slave mode this register has no effect The actual vertical line number is VSYNC PERIOD 1 3111 120 e Width
58. 291 ATPGmode 224 2 b1X Normal mode 291 7 5 5 1 2 Configuration Setup 1 Please refer to ARM926 Reference Manual Centrality Communications Inc 37 460 Developer s Manual Centrality The mode configuration pins have on chip pull up down resistors So when Atlas II is powered up there is no default value User needs to use external pull up down resistors to set up the configurations Because these mode configuration pins are shared with normal functional pins the configuration process has to be completed before Atlas II enters the normal functional mode This is done by internal strobing logic which latches the configuration valued on the rising edge of the power on reset So the functional toggling after the reset is finished will not change the configuration mode anymore X RESET Figure 9 An Example of Mode Configuration Setup Centrality Communications Inc 38 AT460A BI Developer s Manual LS Centrality COMMUNICATIONS 5 2 Clock and PLL 5 2 3 Overview CLK_721 To CPU CLK_721 ES To System gt amp Memory NE 721 2905 PLL1 i 721 ms PLL2 CLK_DIVIDE CLK_521 id gt USB CLK_DIVIDE CLK_521 gt To CKO 0 CLK_DIVIDE CLK_521 t gt Figure 10 Atlas 2 Clock Circuit Block Diagram 12MHz Oscillator 1 2 32KHz Oscillator Pad fete The above
59. 9 R W SM RST Smartmedia NAND Flash software reset R W R W IDE F 8 USB RST USB OTG software reset Centrality Communications Inc 74 AT460A BI Developer s Manual Centrality 1 RST Bus 1 software reset 30 EIN HWACC RST 1 bO Hardware Accelerators YUV RGB YUV CHG and IPOLATE software reset 31 sl SYS RST System software reset including all blocks except the Power Manager Resource Sharing Controller Real Time Clock and GPIO e Reset Controller Status Register RESET STATUS 0x0004 User can use the reset controller reset status register RESET STATUS to determine the last cause or causes of the reset Each RESET STATUS status bit is set by a different source of reset and can be cleared by writing a zero back to that bit After hardware reset all the status bits are zero For reserved bits writes are ignored and reads return zero Bit Default Description 0 R W 1 bO Hardware reset 0 Hardware reset has not occurred since the last time the CPU cleared this bit 1 Hardware reset has occurred since the last time the CPU cleared this bit 1 R W 1 bO Software reset 0 Software reset has not occurred since the last time the CPU cleared this bit 1 Software reset has occurred since the last time the CPU cleared this bit 2 R W 1 bO Watchdog reset 0 Watchdog reset has not occurred since the last time the CPU cleared this bit 1 W
60. Figure 21 2bits pixel data in a DWORD Big Endian in a byte Little Endian for byte in a DWORD 6 2 3 3 Frame Rate Control The Frame Rate control FRC is actually a time based dithering which is to turn each pixel on or off in a certain period of time to create the perception of different intensities It is implemented by looking up the FRC sequence table periodically For an MxN FRC sequence table the FRC can support up to M levels and the sequence repeats itself every N frames for every pixel Higher 0 to 1 transition frequency within N frames will result in better picture quality Centrality Communications Inc 100 460 Developer s Manual Centrality For passive monochrome mode the FRC is implemented by looking up the 16 x 32 FRC sequence table the table is located part of the 256x18bit palette RAM The FRC can support up to 16 grey levels For passive color mode the FRC is implemented by looking up the 32x64 FRC sequence table this table is located in the 64x32 RAM The FRC can support up to 32 levels for every R G B color In order to decrease the flickering side effect of FRC the random control is added to avoid all the pixels in a large group on and off together in synchronization This random control is implemented by using two linear feedback shift registers LFSR The line LFSR which is shifted every HSYNC and the pixel LFSR which is shifted every pixel clock are reset every frame The
61. Mixing value for the OSD pixel type 2 RW 000 100 screen value 001 34 screen value OSD value 010 72 screen value OSD value 011 screen value OSD value 100 100 OSD value Note For 12 bit and 16 bit bypass mode only 100 screen and 100 OSD are allowed 31 27 50 Reserved e OSD Palette Entry 3 LCD OSDPAL3 0 0 Bit Name Default Description 7 0 BLUE Blue value for the OSD pixel type 3 15 8 R W GREEN 8 0 Green value for the OSD pixel type 3 23 16 8 Red value for the OSD pixel type R W 26 24 MIX RATIO 35000 Mixing value for the OSD pixel type Centrality Communications Inc 123 460 Developer s Manual Centrality R W 000 100 screen value 001 34 screen value 1 4 OSD value 010 screen value OSD value 011 screen value OSD value 100 100 OSD value Note For 12 bit and 16 bit bypass mode only 100 screen and 100 OSD are allowed 31 27 50 6 2 4 8 FIFO Control Registers The FIFO s in the LCD controller interface the screen FIFO and the two OSD FIFOs will all generate DMA requests to the bus master The requests generated are a 2 bit request level with 3 being critical request 2 being high level request and 1 being low level request The request level depends on the fullness of the FIFO The FIFO registers define three watermarks that help to determine
62. PCMCIA Register Enable EXT SEL B M17 USP4 Clock SD_DAT lt 3 gt PA lt 23 gt me 5 L18 USP5 Clock SD lt 25 gt Centrality Communications Inc 352 AT460A BI Developer s Manual KE Centrality COMMUNICATIONS 203 0 H13 General Purpose PWM lt 3 gt 24 18 General Purpose PWM lt 2 gt X_GPIO lt 5 gt PDUWOADGZ General Purpose IO PWM lt 1 gt 9600 417 General Purpose IO lt 0 gt es 15 General Purppose IO LDD lt 16 gt H16 General Purppose IO LDD lt 17 gt fais Pcome21x General Purppose IO DF_AD lt 15 gt ____ T s emae _ vorov ris pome __________ I me fome ________ Centrality Communications Inc 353 AT460A BI Developer s Manual KE Centrality COMMUNICATIONS 66 me __ PDIFF21X Memory Clock Output 2a as _ Memory clock output ________ 2d en d ER eu bis 22 ES ED pos r owes Bis i E __ gt __________ HE it BE a pr a n ES i
63. Pix_data output hold time 06 Centrality Communications Inc 368 AT460A BI Developer s Manual Centrality i i La bias a tavaild x_Idd F pix_data 2 gt tani Figure 83 Lcd data Timing 9 4 15 Nand rom Specifications Table 110 Nand rom read data Timing Description Min Units oe high to ce active switching time 87 a cs active to oe active delay2 60 Vaia data setup time 19 rs Tens Valid data noid up time rs toesu toehd copy from Atlas it can be adjust from internal reg gt Toesu2g gt 4 IN x foe b T Toehad gt lt x F gt Centrality Communications Inc 369 AT460A BI Developer s Manual Centrality Figure 84 Nand rom read data Timing Table 111 Nand rom write data Timing Description Min Units Sym oe high to ce active switching time es active to oe active delay 29 ns cs active to oe active delay 50 ns Tes peamodime 3 s lt lt V T gt 8 a 4 gt V Valid ADDRESS V X Fa X 1 9999 gt Tavalid pe es ee ee See Figure 85 Nand rom write data Timing 9 4 16 Na
64. R W DES buffer coordinate xy 0 0 0 2047 1511 150 Reserved 26 16 CLIP_BRX 11 rectangle bottom right Y coordination R W 0 2047 3127 50 Reserved e Foreground Color BLT_FCOLOR 0x1C2C Bit Name Default Description 31 0 FCOLOR 3270 Bit7 0 valid when pixel format is 00 R W Bit15 0 valid when pixel format is 01 Bit31 0 valid when pixel format is 1X e The Background Color BLT BCOLOR 0x1C30 Default Description BCOLOR 3270 Bit7 0 valid when pixel format is 00 Bit15 0 valid when pixel format is 01 Bit31 0 valid when pixel format is 1X The foreground color is used when doing ROP 0x00 BLACKNESS to fill the destination with this color The background color is used when doing ROP 0xFF WHITENESS to fill the destination with this color And these two registers defined the color when doing pattern concerned ROP please refer to the PATTERN_MATRIX_LOW and PATTERN_MATRIX_HIGH notes e The Source Color Key BLT_SRC_COLORKEY 0x1C34 Bit Name Default Description 31 0 SRC_COLORKEY 32 h0 Color key is a reserved color which will not interfere the R W ROP result result will not written back into the destination and here if source is needed pixels from the source bitmap with this value will not change the destination Centrality Communications Inc 144 AT460A BI Developer s Manual Centrality pixel value if source color key fun
65. R W is active R W access time can be smaller than the first access time R W R W E R W R W R W ae R W 29 WRITE_EN 1 b1 Enable write R W 1 write to ROM address will be written to ROM port Centrality Communications Inc 156 AT460A BI Developer s Manual h 1 b1 1 b1 Centrality 0 write to ROM address will be masked write will occur on ROM port 31 30 BUS WIDTH Defined Define the bus width of ROM port R W by reset 00 bus width is 8bit pin value 01 bus width is 16bit 10 bus width is 32bit 11 reserved NOTE pci period of one PCI clock e CS1 Configure Register ROM CFG1 0x0004 ROM CFGi controls the timing amp access mode for ROM port CS1 Default Description Bit 7 0 WGAP lt 7 0 gt 7 hO Write interval WGAP T clk_pci between each two R W write 13 8 TACC lt 5 0 gt 6 hO Access time TACC T clk_pci is the read write R W signal active time 15 14 TCES lt 1 0 gt 2 10 CS active time TCES T clk_pci before R W read write signal is active 21 16 TNACC lt 5 0 gt 6 hO Read burst access time For burst read the next R W access time can be smaller than the first access time 23 22 TDF lt 1 0 gt 2 0 Read data hold time R W 24 DWORD_ACC 1 0 Enable DWORD access R W BURST_READ Enable burst read BURST_WRITE Enable burst write Enable variable access mode Need to be writte
66. Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 List of Tables System Memory Mapping cccecceeeceeeeeeeeeeeeeeeeeeeeeseneeseeeeceeeeceeeeeeeeeseeeeseeeeseeeeseeeeseeeeseeeseeees 10 Internal Register 10 RISC Subsystem Register Mapping 10 DSP Memory Address 10 DSP ISA IDMA Control 10 DSP IO Device Address Mapping ecceceeeeeceeeneeeeeeeeeeeseaeceeseaaeceeceneeeseaeeeesecaeeeeseeeensnaes 10 DSP Subsystem Register Mapping essere nnne 10 System Bus Master Allocation sssssssssese eene nennen nennen 10 DDR SDRAM Configurations for a 16 bit Data 10 DDR SDRAM Configurations of 32 bit Data 0 0 10 RISC Interface Register Address 10 Mode Configuration sinn sene nsns 10 Decoding of JTAG lt 0 gt 244 0 00 0 00 10 Selection Guide of Crystal for 204 40 0 0 10 Supported Clock Ratios in Atlas 2 unit 2
67. The GPIO is output pin GPIO Data Output 0 mm DATA_IN GPIO Data Input PULL GPIO Pull up no pull see pin description SW 1 bO GPIO open drain mode open drain normal ae E INT 150 only for GPIO groupO GPIO will generate different interrupt to DSP and RISC There is different interrupt enable for DSP and RISC Enable the GPIO to generate interrupt to DSP when Interrupt Status is set 0 Interrupt is disabled 1 Interrupt is enabled _____ Reserved notes GPIO2 CTHRL 19 is reserved for DRAM clock control This register should never be used by GPIO purpose e GPIO DSP control enable Register GPIOx DSP This control register only exist for GPIO groupo Bit Default Description 31 0 DSP_EN lt 31 3210 GPIO DSP control enable R W 0 gt 1 the GPIO pin is controlled by DSP 0 the GPIO pin is controlled by RISC e PAD enable Register GPIOx_PAD_EN Each bit in GPlOx PAD EN control the pad mux of one GPIO pin in group x For example lt 0 gt control the pad mux of GPIO pin 0 in group 0 GPIO2_PAD_EN lt 21 gt control the pad mux of GPIO pin 85 32 2 21 in group 2 Each GPIO have different default value for PAD MUX enable as following GPIOO_PAD_EN 32 hF3FF FFFF GPIO1 PAD EN 32 hFFF8 0000 GPIO2 PAD EN 32 hFFFF FFFF Centrality Communications Inc 91 AT460A BI Developer s Manual Centrality GPIO3 PAD 32
68. WAIT lt 14 0 gt must be greater than 0 to enable the GPIO wakeup function Sleep wake up enable by RTC alarm 0 Wake up by RTC alarm disabled WE R W 1 Wake up by RTC alarm enabled NOTE Only GPIO in Group 0 and Group 5 can be configured as wakeup source Please refer to the GPIO section for more details Power Manager Sleep Status Register PWR SLEEP STATUS 0x000C Bit Name EUM 0 R W SW SLEEP BATT SLEEP VDD SLEEP DRAM HOLD FLASH HOLD Description Software sleep status 0 Chip has not been placed in sleep mode by setting the force sleep FS control bit since it was last cleared by reset or by the CPU 1 Chip was placed in sleep mode by setting the force sleep FS control bit Battery fault status 0 FAULT pin has not been asserted since it was last cleared by a hardware reset or by the CPU 1 FAULT pin has been asserted VDD fault status 0 FAULT pin has not been asserted since it was last cleared by a hardware reset or by the CPU 1 VDD FAULT pin has been asserted SDRAM hold control This bit is set upon exit from sleep mode and indicates that the MWE B MCKE lt 1 0 gt MRAS B MCAS B and MCS lt 1 0 gt continue to be held invalid so that the DRAM is still in self refresh mode The CPU can clear this bit after the DRAM interface has been configured but before any DRAM access is attempted The CPU can also enable this bit if nec
69. X PAD RQ X PAD GNT Pin Mux Pin Name 61 0 X PAD GNT GPIO group4 offset 16 X PAD RQ GPIO group4 offset 17 After reset GPIO will have control over these pins User can write corresponding GPIO control registers to give the control of these pins to X PAD GNT X PAD The priority of above functions is as following e If GPIO have control over these pins all others can not control the pin e Else X PAD GNT X PAD will take over the pin This function is for extension usage for future device NOTE As you may notice NAND Flash has two options for pin sharing it can be either shared with Video Input Port or it can be shared with ROM I F It s determined by some of the mode configuration pins when chip is powered on Please refer to the section of Mode Configuration Pins for more details Some of the pins are shared statically which means the pins will be dedicated to a certain function once the configuration bit is set But some other pins are shared dynamically which means the pins will be dynamically switched between different functions automatically The ROM I F pins shared with NAND Flash PCMCIA CF and IDE belong to the later dynamic sharing pins There is internal arbitration logic to determine which function can take the control of these pins But these pins can also be programmed to be statically sharing pins once the user set the corresponding PARK bit in RSC ROMPAD register 5 7 11 Resource Sh
70. an interrupt controller pending registers INT DSP1 PENDING amp INT DSPO PENDING The DSP can read the according interrupt pending register followed by the status register in the device It will use a different interrupt mask register from the RISC so that the DSP can by interrupted independently by different sources with the RISC 5 4 2 Interrupt Controller Registers The interrupt Controller registers are mapped as the following table Table 18 RISC DSP Address Address Register Description lt 11 0 gt lt 6 0 gt 0x0000 INT_PENDING Interrupt Pending Register 0 0004 INT IRQ PENDING IRQ Pending Register 0x0008 INT_FIQ_PENDING Read only FIQ Pending Register Default 0 00000000 0x000C 0 6 7 INT DSPO PENDING Read only DSP Pending Register for DSP s IRQLO interrupt Default 0x00000000 Default 0x00000000 Default 0x00000000 pt Controller Register Mapping 0x0018 INT RISC LEVEL RISC Level Register Default 0x00000000 0x001C INT DSP ACCEN DSP Access enable This register is read only register for DSP Only RISC can R amp W it Default 0 00000000 il ID This is a read only register It contains the CHIP ID P ewe Depend on chip version M 13 INT DSP LEVEL DSP Level Register Default 0 00000000 0x0028 0x14 15 INT_DSP1_PENDING Read only DSP Pending Register for DSP s IRQL1 interrupt Default 0 00000000 Centrality Communications Inc 59 AT460A BI
71. and Timer registers a Hongyu Zhang Corrected the data switch bits in COPY_CHX_STATUS register Modified register names in BitBLT engine Marked all features not fully verified to RED Added 4 12 14 2004 Hongyu Zhang Added notes for MEM_POWER COPY_CHx_X_NUM and YUV2RGB_BLOCK_NUM registers Strike through all contents not for release Fixed a typo in Figure 6 Update the Pin List according to the update from GUC on 9 17 Updated the IOBG_ARB_CLKRATIO 1 6 12 31 2004 Hongyu Zhang Fixed typo in PWR_WAKEUP_EN register Fixed typo in section 5 2 5 1 amp 5 2 5 2 Added definitions and notes for SM_CTRL register 1 7 2 2 2005 Hongyu Zhang Removed Gyro and MPEG2 decoder from Figure 2 to avoid confusion Added a note for PWR_WAKEUP_EN register in section 5 3 12 B 0 is not shared with GPIO section 5 7 10 Fixed the total number of GPIO in section 5 8 Moved PWM to section 5 9 Fixed the typo in Table 11 DDR SDRAM Configurations of 32 bit Data Bus Added a note for Table 13 Mode Configuration Pins Added notes for section 7 8 5 and 8 5 2 5 to avoid confusion between two YUV2RGB conversion logic Added Pin Type information in pinout list Centrality Communications Inc 973 AT460A BI Developer s Manual LS Centrality COMMUNICATIONS BE NEN Added 19x19mm package drawing in section 9 2 1 8 28 4 2005 Yong Peng Updated supported clock ratios in Atlas 2 Updated pad arbitration clock enable default setting Updated watchdog
72. tag bit of Slot 2 should be set the AC97 interface will Centrality Communications Inc 294 AT460A BI Developer s Manual Centrality audio data of right channel will be duplicated and played through left channel The tag bit of Slot 3 is controlled by software it decides whether output frame Slot 3 is enabled to transfer valid audio data to AC97 CODEC Tag bit of Indicates that output frame Slot 4 is enabled Slot 4 0 Indicates that output frame Slot 4 is disabled For stereo and mono right mode the output frame Slot 4 and AC97 playback right channel must be enabled for mono left mode if output frame slot 4 is enabled the audio data of left channel will be duplicated and played through left channel The tag bit of Slot 4 is controlled by software it decides whether the output frame Slot 4 is enabled to transfer audio data to AC97 CODEC e CODEC AC97 Command Register CODEC_AC97_CMD 0x20 Description Reserved AC97_CMD_ADDR 7 b0 AC97 CODEC control register address R W 1 Read AC97 CODEC status command 0 Write AC97 CODEC control register command R W CODEC AC97 Input Frame Tag Register CODEC AC97 RTAGH 0x24 It s a read only register The tag of AC link input frame is saved in this register It can be used to judge whether AC97 CODEC has been ready Bit Name Default Description 7 0 AC97 SLOT RQ AC97 input frame slot request for next output frame 1
73. the input data is always transferred to memory through DMA channel 8 The data transfer over AC link data is in serial mode First the Atlas I AC97 controller converts the serial input data into 16 bit data The 16 bit data may be PCM data or other ADC sample data The CLK counter will make the slot judgment AC link input slot 0 is the AC link tag the bits in the tag indicate whether the selected slot contains valid data 8 6 6 3 5 Auxiliary Data Output User can program AC97 Controller to select the right slot which is used for auxiliary data output No matter which slot is used to input the data the input data is always transferred to memory through DMA channel 9 And for the AC97 controller it fetches 32 bit PCM data from FIFO The AC97 CODEC will be responsible for the flow control of output data stream In AC link input frame data AC97 CODEC indicates its data request for next output frame in slot 1 The SLOTREQ bits occupy Slot 1 bit11 to bit 2 which indicate the request from Slot 3 to Slot 12 SLOTREQ bits are always valid and independent of tag bit 8 6 6 4 Interrupt Generation There are four DMA channels in the CODEC interface all the CODEC interrupt generation comes from the DMA interface There are eight FIFO statuses which can trigger the CODEC interrupt if it is not masked e TXFIFO Full e TXFIFO empty Centrality Communications Inc 290 AT460A BI Developer s Manual Centrality e TXFIFO
74. this bit is set Read Transaction This bit is set at the falling edge of the DAT LINE ACTIVE Status When the transaction is stopped at SD Bus timing The Read Wait must be supported in order to use this function Write Transaction This bit is set at the falling edge of WT TRAN ACTIVE Status After getting CRC status at SD Bus timing 0 No BLK GAP EVT 1 Transaction stopped at Block Gap This status is set if the BUFF_WT_EN changes from 0 to 1 0 Not Ready to Write Buffer 1 Ready to Write Buffer This status is set if the BUFF_RD_EN changes from 0 to 1 0 Not Ready to read Buffer 1 Ready to read Buffer This status is set if the the SD STATE registers EE from BLK GAP EVT EM M WT RDY a BUFF_RD_RDY 6 R W CARD_INSERT Centrality Communications Inc 177 AT460A BI Developer s Manual RD_TRAN_ACTIVE Status There are two cases in which the Interrupt is generated The first is when a data transfer is completed as specified by data length After the last data has been read to the Host System The second is when data has stopped at the block gap and completed the data transfer by setting the STOP_AT_BLK_GAP_REQ the SD HOST CTRL 0 Register After valid data has been read to the Host System Write Transaction This bit is set at the falling edge of the DAT LINE ACTIVE Status There are two cases in which the Interrupt is gen
75. to 1 full When set to 0 the interrupt is disabled When set to 1 an interrupt will be generated when a message has been successfully transmitted or the Md MN NE Centrality Communications Inc Transmit Buffer is accessible again When set to 0 the 332 AT460A BI Developer s Manual Centrality interrupt is disabled When set to 1 an interrupt will be generated when the bus status or error status bits change When set to 0 the interrupt is disabled 3 R W When set to 1 an interrupt will be generated when the Data Overrun Status bit is set When set to 0 the interrupt is disabled 4 R W 1 bO When set to 1 an interrupt will be generated when the sleeping CANBUS controller wakes up When set to 0 the interrupt is disabled 5 R W 1 bO When set to 1 an interrupt will be generated when the error status of the CANBUS controller changes from error active to error passive or vice versa When set to 0 the interrupt is disabled 6 R W ALIE 1 bO When set to 1 an interrupt will be generated when the CANBUS controller loses arbitration When set to 0 the interrupt is disabled 7 R W 1 bO When set to 1 an interrupt will be generated when a bus error has been detected When set to 0 the interrupt is disabled 31 8 1240 e CANBUS Timing
76. writing to this register has no effect when the CANBUS controller is in Bus Off state and that any change made within Reset Mode will in any case only come into effect on return to Operating Mode 3 8 120 e Transmit Error Counter Register CANBUSn_TXERR 0x003C Bit Name Default 7 0 TXERR R W Centrality Communications Inc Description The Transmit Error Counter Register records the current value of the Transmit Error Counter This counter is incremented when Transmission errors are experienced and decremented when messages are transmitted without error in line with the rules given in the CAN 2 0 specification Together with the associated Receive Error Counter it provides an indication of the quality of transmission being experienced on the CAN bus Three levels of the counter trigger specific events When the counter reaches the level set in the Error Warning Limit register an Error Warning Interrupt is generated if enabled unless this has previously been triggered by the Receive Error Counter When the counter goes over 127 the device is put into Error Passive state in accordance with the CAN 2 0 specification unless previously triggered by the Receive Error Counter an Active error is sent and an Error Passive Interrupt is generated if enabled When the counter goes over 255 the device is put into 336 AT460A BI Developer s Manual Centrality Bus
77. 0 TX FIFO is not overflow User can write 1701 to clear the register bit after the TX FIFO overflow takes place 3 R W TX_FIFO_UFLOW 1 bO TX FIFO underflow status 1 TX FIFO underflow takes place 0 TX FIFO is not underflow User needs to write 1 b1 to clear the register bit after the TX FIFO underflow takes place Centrality Communications Inc 301 AT460A BI Developer s Manual Centrality 314 28 Reserved e CODEC TXFIFO Interrupt Enable Register CODEC TX FIFO INT EN OxF98 Bit Name _ _ Description 0 R W TX FIFO FULL EN 1 bO 1 TX FIFO full interrupt is enabled 0 TX FIFO full interrupt is disabled 1 R W TX FIFO EMPTY EN 1 TX FIFO empty interrupt is enabled 0 TX FIFO empty interrupt is disabled 2 R W TX FIFO OFLOW EN 150 1 TX FIFO overflow interrupt is enabled 0 TX FIFO overflow interrupt is disabled 3 R W TX UFLOW EN 1 bO 1 TX FIFO underflow interrupt is enabled 0 TX FIFO underflow interrupt is disabled 314 28 0 Reserved e CODEC FIFO DMA I O Control Register CODEC IO CTRL 0 Bit Name Default Description IO DMA SEL 1 for I O mode 0 for DMA mode 1 IO DMA RW 1 b1 1 read from CODEC 0 write to CODEC 2 R W FLUSH 1 bO Flush the DMA receive FIFO in case the DATA LEN 1 bO set at the peripheral side doesn t match the DWORD size set in the DMA control 1 little end
78. 0 disabled 1 enabled 3 R W TX UFLOW INT EN 1 bO Transmit underflow interrupt enable 0 disabled 1 enabled A R W RX IO DMA INT EN 160 IO DMA receive interrupt enable 0 disabled 1 enabled 5 R W TX IO INT EN 160 IO DMA transmit interrupt enable 0 disabled 1 enabled 6 R W RXFIFO_FULL_INT_EN Receive FIFO full interrupt enable 0 disabled 1 enabled TXFIFO_EMPTY_INT_EN Transmit FIFO empty interrupt enable 0 disabled 1 enabled 8 R W RXFIFO_THD_INT_EN 1 bO Receive FIFO threshold interrupt enable 0 disabled Centrality Communications Inc 321 AT460A BI Developer s Manual Centrality ______ 1 enabled ____ TXFIFO_THD_INT_EN Transmit FIFO threshold interrupt enable 0 disabled 1 enabled 10 R W UART_ERR_INT_EN 1 bO UART error frame interrupt enable 0 disabled 1 enabled 11 R W USP RX TIMEOUT INT EN USP receive timeout interrupt enable 0 disabled 1 enabled 12 R W USP_TX_ALLOUT_INT_EN 4 USP all transmit out interrupt enable 0 disabled 1 enabled 3113 e USP Interrupt Status Register USP INT STATUS ARM9 0x18 DSP 0xC 0xD ARM9 DSP writes 1 b1 to the bit will clear that interrupt Bit Name Default Description 0 R W 1 bO A valid data has been received in the RXFIFO interrupt the valid data length is define by the RXFIFO WIDTH 0 invalid 1 valid 1 R W TX DONE 1 bO A valid data has been transmitted from the TXFIFO interrupt
79. 1 Main Display Layer 2 Overlay Display Layer 3 Overlay Display The following diagram shows the block diagram of the mixer that mixes those 3 display layers Centrality Communications Inc 98 AT460A BI Developer s Manual LS Centrality COMMUNICATIONS To Display Figure 17 Block Diagram of Layer Mixer Layer is the main layer SCN layer It supports 8 bit index index into RGB 6 6 6 lookup table 16 bpp RGB 6 5 5 5 6 5 5 5 6 data format And it also supports 8 bit with 8 bit index 18 bit with 18 bit RGB 6 6 6 color key range registers if a color matches between the range defined by two registers the color is transparent and the pixel from the layer2 OSD layer will be shown instead Layer2 amp 3 OSD amp OSD2 layer are all overlay layers Each of the overlay layers has the following alpha blend and or color key modes 8 bit index index into RGB 6 6 6 lookup table e RGB 6 5 e 8 bit with 8 bit index 18 bit with 18 bit RGB 6 6 6 color key range registers if a color matches between the range defined by two registers it will be transparent and the pixel from the main display layer will be shown instead 4 bit planar blending register to blend all pixels on the plane that are non transparent to one planar alpha value 6 2 3 2 DMA to Memory Interface Encoded pixel data of frame buffer are stored in off chip memory usually DRAM and are transferred to the LCD controller s 12
80. 11 0 Source window X coordination R W 0 2047 15 11 50 Reserved 2 26 16 SRC_X 11 0 Source window Y coordination R W 0 2047 9277 __ SRC_YDIR 1 bO Source window Y direction 0 top down 1 bottom up R W e Destination 2D Window XY Coordination DES XY 0x1C20 Bit Name Default Description 10 0 DES Y 11 0 Destination window X coordination R W 0 2047 15 11 f 50 Reserved 00 2 ee Destination window Y coordination R W 0 2047 307 Destination window Y direction 0 top down 1 bottom up Centrality Communications Inc 143 AT460A BI Developer s Manual Centrality e Clip 2D Rectangle Top Left XY Coordination BLT_CLIP_TLXY 0x1C24 The Clip Rectangle is used to determine whether the destination area is writable or not And here when clip is enabled only area in the clip rectangle will be writable includes the boundary Bit Name Default Description CLIP_TLY Clip rectangle top left X coordination relative to the DES buffer coordinate xy 0 0 15 11 f 1450 Reserved 26 16 CLIP_TLX 17 0 rectangle top left Y coordination R W 0 2047 3127 50 Reserved 2 e Clip 2D Rectangle Bottom Right XY Coordination BLT_CLIP_BRXY 0 1 28 Bit Name Default Description 10 0 CLIP_BRY 11 Clip rectangle bottom right X coordination relative to the
81. 13 h0 This value specifies the number of BYTE s for the DMA R W address generator to skip in between lines of the OSD DMA OSD 5 ByteWidthOfOsdFrameBuf OSD XSIZE 16 And the ByteWidthofOSDFrameBuf must be a multiple of 16 3113 1980 Reserved e Current DMA Address for the OSD Display LCD OSD ADDR 0x12C Writing to this register will activate the OSD DMA Make sure this register is written last after all the other DMA registers are setup correctly already Bit Default Description 0 W OSD START Write 1 to start the OSD DMA this bit is self cleared 31 1 __ Tho The read value is for test purpose only Bit Default Description 26 0 R OSD_DMA_ADDR 2710 Current DMA address for the OSD display 4727 0502 Memory Base Register LCD OSD2BASE 0x130 Name Default Description Bit 3 0 PIXEL_OFFSET 4 hO Pixel offset for OSD2 channel This pixel offset R W specifies which bits within the first DWORD specified by bits 30 4 is the first valid pixel for this channel When used as OSD2 the pixel data be 2 bit 4 bit 8bit 16 bit pixel When used as Dual Scan mode the pixel data can be 2 bit 4 bit 8 bit pixel Example 2bits pixel Big endian in word and in byte 0000 bits lt 31 30 gt 0001 bits lt 29 28 gt 1111 bits lt 1 0 gt BASE ADDR 27 h0 DMA address of the starting memory location for the Cent
82. 16 bit WORD PM is 5K 24 bit WORD and DMY is 5K 16 bit WORD The following table is the summary of the DSP memory spaces Table 4 DSP Memory Address Mapping Memory Starting Size WORD Word Accessed By Address Length DMX swap double 0x0400 DM 2048 DSP SDRAM 0x0000 PM 3 2 2 DSP Host Interface In Atlas II the DSP Host Interface is called ISA IDMA Port The ISA IDMA Port provides an efficient method of communication between a host system and the DSP core The port can be used to access the on chip program memory coefficient memory and data memory of the DSP with only on DSP cycle per word overhead The ISA IDMA port can not however be used to write to the DSP s memory mapped control registers A typical ISA IDMA transfer process is described as follows The start address and destination memory type should be set before data is transferred Destination address will be incremented automatically after each data transfer for DMX DMY data or every two data transfer for PM data Note that the DSP continues program execution during the transfer operation except during the stolen cycle used to access memory For PM data Set starting address Set memory type to PM While Data to be transferred is not empty Centrality Communications Inc 22 AT460A BI Developer s Manual Centrality transfer the low part transfer the high part fill the high byte to zero For DMX DMY data Set starting
83. 20 ai ER 2 Centrality Communications Inc 354 AT460A BI Developer s Manual Centrality a PCOMB21X Memory Data m poes p _________ m owe POE 2 Video Input Port Data DF_AD lt 12 gt x Pcome21x Video Input Port Data DF_AD lt 11 gt oem roven feae roven M7 8 9 M10 8 8 7 7 7 7 mu eem _ 90 ws NOTE Pin Type Pin Type Description 21 3 State Output 1 8 2 5 3 3V LVTTL and SSTL2 Buffer Pad PDIFF21X Differential Output 1 8 2 5 3 3V LVTTL SSTL2 Buffer input SV Centrality Communications Inc 355 AT460A BI Developer s Manual Centrality CMOS 3 State Output Pad with Input and Pulldown 5V Tolerant POD94ADGZ 4mA Driving Strength CMOS 3 State Output Pad with Schmitt Trigger Input and Pull up FREMDE 5V Tolerant 4mA Driving Strength 3 State Output Pad with Input and Enable Controlled Pull Up 5V Tolerant 4mA Driving Strength Centrality Communications Inc 356 AT460A BI Developer s Manual A Centrality 9 2 Pac
84. 21 57001000 Arbitration lost in 9th bit of identifier ID 20 57001001 Arbitration lost in 10th bit of identifier 10 19 5 b01010 Arbitration lost in 11th bit of identifier 10 18 5 b01011 Arbitration lost in SRTR bit 1 5 b01100 Arbitration lost in IDE bit 5 b01101 Arbitration lost in 12th bit of identifier ID 17 5 b01110 Arbitration lost in 13th bit of identifier ID 16 5 b01111 Arbitration lost in 14th bit of identifier ID 15 57010000 Arbitration lost in 15th bit of identifier ID 14 5 b10001 Arbitration lost in 16th bit of identifier ID 13 5 b10010 Arbitration lost in 17th bit of identifier ID 12 5 b10011 Arbitration lost in 18th bit of identifier ID 11 5 b10100 Arbitration lost in 19th bit of identifier ID 10 5 b10101 Arbitration lost in 20th bit of identifier ID 9 5 b10110 Arbitration lost in 21st bit of identifier ID 8 5 b10111 Arbitration lost in 22nd bit of identifier 10 7 334 AT460A BI Developer s Manual Centrality 57011000 Arbitration lost in 23rd bit of identifier 10 6 57111001 Arbitration lost in 24th bit of identifier 10 5 5 b11010 Arbitration lost in 25th bit of identifier 10 4 5 b11011 Arbitration lost in 26th bit of identifier 10 3 5 b11100 Arbitration lost in 27th bit of identifier 10 2 511101 Arbitration lost in 28th bit of identifier ID 1 5 b11110 Arbitration lost in 29th bit of identifier 10 0
85. 3 Memory Bus 0 nenne ener estne nenas 10 2 2 4 WOIBUS Interface neta he RIO epe IER chee ERR d 10 2 3 RISC Subsystem 10 3 10 3 1 HOVERVIOW nce eb enden I 10 3 2 FUNCHONAl DESCHPUON iion 10 3 2 1 DSP MOMO eine he t ht nd nere 10 3 2 2 DSP Host Interface acia d ERR E RC eine EI Ld HR 10 32 2 DSP IO Interface tente delenit tet bte pe dtes 10 3 3 DSP Subsystem Registers eese nennen 10 4 System Memory Interface 0 eee cceesseeseceeseceeeeseseeeeseeeeseeseaeeseaeeaeaeeseaeeseseeseaeeeeaeeseaeeseaeeeeaeeeaeeeeaeees 10 ZUM MH Lr TH 10 LM AMMESSI dL IPIE 10 4 2 1 OVEIVIEW 10 43 eise e PR 10 4 3 2 DDR Connection Examples 10 4 33 SDRAM Connection Examples tenen nen nnne nnns 10 4 34 DRAM Controller 4444 44440 4 0 nenne nennen senes nennen senes 10 5 System Control MOdUles xe nid EY A 10 5 1 Mode Configuration PINS eaaa aiaa 10 5 1 1
86. 4 m LALA NEN ULLUS NOTE Control Signals are composed of RAS CAS MEM WE CS 51 EN Figure 79 Timing Diagram Standard SDRAM Memory Write Timing 9 4 12 DDRSDRAM 1 Address and Control output are clocked by sys clk the same as SDRAM 2 Data DQS and DM output are clocked by mck2x_o which should match the delay between mck2x_o amp mck_clk 3 Data input is clocked by delayed DQS 9 4 12 1Memory Interface Timing DDR SDRAM Read Command Table 106 DDR SDRAM Memory Read Timing Sym Description Min a E MEM CLK period t Control Signals Address and MBA Valid valid after rising edge of MEM CLK T Control Signals Address and MBA Hold js after rising edge of MEM_CLK MDQ setup to rising edge of x mdqs M MDQ hold after rising edge of x mdqs 30 ns Centrality Communications Inc 365 AT460A BI Developer s Manual Centrality Control signal x mdqs Data 7 ldata setup i Strobe _ tdata_hold sta 7777 7 lt q i 1 gt 4 M LI mm ML Lg Lg NL LN thold x_ma Address Was Row Itvalid 1 gt 4 Bark 77777 77777 NOTE Control Signals are composed of RAS CAS MEM WE MEM CS MEM CS1 and CLK EN Figure 80 Timing Diagram DDR SDRAM Memory Read Timing 9 4 12 2Memory Interface Timing DDR SDRAM Write Command Table 107 DDR SDRAM Memory Write Tim
87. 4 3 Functional Desci ON 10 7 4 4 SDIO Host Controller Registers 10 7 5 USB OTG Interface rer ere ee IU RP EHE E ERE 10 7 5 1 LL Lm MUI LE M UEM Mm 10 7 5 2 Pin 10 7 5 3 Functional 10 7 5 4 USB OTG Interface 10 7 6 IDE 7 10 7 6 1 10 7 6 2 Pin PEE 10 7 6 3 IDE Interface Registers 10 77 A 10 77 4 Overview 2 022 20 44 0 000 000000010 8 10 7 7 5 PCMCIA Signal Descriptions 4 1 10 nennen nnn 10 7 7 6 Card Connection Example 04 4 4111 0000000000 00 10 7 7 7 PCMCIA Memory Mapping 2 220 212 2240 2 00000000000 00000 000000000000 0 10 7 7 8 PCMCIA Interface 10 8 Peripheral SEES SEES Eene nnn nnns 10 8 1
88. 7 0 P11 9 2 P12 9 2 P11 8 1 P12 8 1 11 7 0 12 7 0 P13 9 2 P14 9 2 P13 8 1 P14 8 1 1 P13 7 0 P14 7 0 P15 9 2 P16 9 2 P15 8 1 P16 8 1 P15 7 0 P16 7 0 P17 9 2 P18 9 2 17 8 1 18 8 1 P17 7 0 P18 7 0 P19 9 2 P20 9 2 P19 8 1 P20 8 1 P18 7 0 P20 7 0 8 5 2 5 YUV to RGB conversion The Video Input Port supports two types of format conversions from YUV to RGB and from YCrCb to RGB it works on following formulas YUV to RGB conversion formula Y C1 U C2 V C3 Y C4 U C5 V C6 Y C7 U C8 V CS9 YCrCb to RGB conversion formula Y C1 Cb C2 Cr C3 Offset Y C4 Cb C5 Cr C6 Offset2 B Y C7 Cb C8 Cr C9 Offset3 The output RGB data will be rounded and fixed as following formula R OUT R 8 h80 gt gt 8 amp 8 hff G OUT G 8 h80 gt gt 8 amp 86 B OUT B 8 h80 gt gt 8 amp 8 hff NOTE Unlike the YUV RGB engine on PCI bus the YUV to RGB conversion logic in Video Input Port is only applied to the Video input stream data it cannot be applied to other data transfers inside of the chip Following table gives the reference value Table 71 YUV2RGB Conversion Coefficent Centrality Communications Inc 271 AT460A BI Developer s Manual Centrality Color Coef 256 HEX Y Coef 256 0 Color C V Cb Color D R R Color E Color B B
89. 8 16 32 bit from RISC PCI IO access translate them onto 8bit 16bit 32bit ROM SRAM port Following table shows the detail access translation The first amp second columns list the access from RISC PCI IO The byte enable on RISC PCI is active 1 amp depends on the access mode for example an 8bit access will only have one byte enabled The third column defines the ROM SRAM interface bus width The fourth amp fifth columns list the translated access on ROM SRAM interface some translated access will require two data access to finish one RISC PCI IO access For example a 16bit access from RISC PCI IO will be translated into 2 accesses on ROM SRAM interface other accesses not listed in the table is not supported for example when RISC PCI access use 16 bit mode the on RISC PCI can not be 4 b0110 Table 36 RISC IO access PCI IO access width translation RISC PCI access Byte BUS WIDTH Actions taken on 0 Notes mode amp byte Enable on in ROM SRAM interface address RISC PCI ROM CFGx 8 bit Addr 31 0 4 b0001 8 bit Access Addr 25 0 4 b1110 1 4 b0010 4 b0100 4 b1000 16 bit Addr 31 0 4 bOOxy 8 bit Access Addr 25 0 4 b111y 4 bxy00 Access Addr 25 0 1 4 b111x 32 bit Addr 31 0 4 bxywz 8 bit Access Addr 25 0 4 b111z Access Addr 25 0 1 4 b111w Access Addr 25 0 2 4 b111y Access Addr 25 0 3 4 b111x 8 bit Addr 31 0 4 b0001 Access Addr 25 1 4 b1110 4 b0010 4 b1101 4 b0100 4 b1110 4
90. Address High registers each withidentical fields Bit Name Default Description 5 0 R W OA lt 25 20 gt 6 hO Offset Address lt 25 20 gt This register contains the most significant six bits of the address that is added to the system memory address to get where in the PC card memory address space the access will occur Centrality Communications Inc 239 AT460A BI Developer s Manual Centrality COMMUNICATIONS 6 R W REG_SETTING WT_PROTECT REG Setting 1 b0 nreg is not active for accesses made through this window 1 b1 nreg is active for accesses made through this window This bit determines whether the nreg signal is active for accesses through the window or not The CIS Card Information Structure memory or the attribute memory is alloted this window by setting this bit to 1 b1 Write Protect 1 b0 Writes to the Card through this window are allowed 1 b1 Writes to the Card through this window are inhibited This bit determines whether writes to the card through this window are allowed or not e M6730 Misc Control 1 Register M6730 MISC 1 Index 0x16 Name Default Bit 1 R W VCC 33 2 R W PM INT Description Multimedia Enable 1 b0 Socket address lines are normal 1 b1 Socket address lines a 25 4 are high impedance This bit tristates socket address lines a lt 25 4 gt All other aspects of the socket are not affected by this bit V
91. Address Low Register M6730 SIO MAPO 1 EAL Index OxOE There are two separate system I O Map End Address Low registers each with identical fields Bit Name Default Description 7 0 R W EA lt 7 0 gt 8 hO End Address lt 7 0 gt This register contains the least significant byte of the address that specifies where in the 1 space the corresponding I O map will end Centrality Communications Inc 236 460 Developer s Manual Centrality accesses that are equal or below this address and equal or above the corresponding system map start address will be mapped into the I O space of the corresponding PC card e M6730 System I O 0 1 End Address High Register 6730 510 1 Index 0x0B OxOF There are two separate system I O Map End Address High registers each with identical fields Bit Name Default Description 7 0 R W lt 15 8 gt 870 This register contains the most significant byte of the address that specifies where in the space the corresponding I O map will end accesses that are equal or below this address and equal or above the corresponding system map start address will be mapped into the space of the corresponding PC card e M6730 Card I O Map 0 1 Offset Address Low Register M6730 CIO MAPO 1 OAL Index 0x36 0x38 There are two separate system I O Map Offset Address Low registers each with identical fie
92. BLK CTRL 0x0004 Reserved ____ O Blocksize countregister Command argumentregister_ Transfer controlregister_ _______ SD card response registerO_ SD card response register 14 SD cardresponseregister2 SD card response register3 Transfer data bufferregister_ 0 host controller state register SD host controller control register O SD host controller control register 1 SD interrupt status SD interrupt status enable register SD interrupt signal enable register Automatical command 12 error status register__ SD host capabilities register Reserved 2 O 5 Maximum current capability 5 SD clock delay register Reserved Slot interrupt status and version register Reserved Bit Name Default Description Centrality Communications Inc 164 460 Developer s Manual Centrality 11 0 BLK_SIZE 1270 This register specifies the block size for block data transfers for R W CMD17 CMD18 CMD24 CMD25 and CMD53 It can be accessed only if no transaction is executing i e after a transaction has stopped Read operations during transfer return an invalid value and write operations shall be ignored 0000h No Data Transfer 0001h 1 Byte 0002h 2 Bytes 0003h 3 Bytes 01FFh 511 Bytes 0200h 512 Bytes 0800h 2048 Bytes E 12 ae Reserved _________________ Reserved d 16 BLK CNT 1680 This is e
93. CANBUSn BTIMO 0x0018 The CAN specification describes the bit period as being composed of a Synchronization segment a Propagation segment and two Phase Buffers For the purposes of CANBUSn the bit period is Seen as being composed of the Synchronization segment plus TSEG1 and TSEG2 where TSEG1 equals the Propagation segment plus the first Phase Buffer and TSEG2 is the second Phase Buffer as shown in the following diagram Sample Pontis Time Quanta TO v XTAL l Prescaler JM t upto 1670 hs Penod Figure 74 CAN Bus Timing Name Default Description 5 m m 6 hO The Baud Rate Prescaler defines the time quantum RW TQ of the CAN clock as a multiple of the input clock period The time quantum of the CAN clock is given by TQ 2 x tak x BRP 1 where time period of the XTAL1 frequency 1 fxtal1 7 6 The Synchronization Jump Width defines the maximum R W number of time quanta TQ by which a bit period may be shortened or lengthened in attempting to re synchronize on the relevant signal edge recessive to dominant of the current transmission Centrality Communications Inc 333 AT460A BI Developer s Manual Centrality 31 8 240 Bus Timing Registers1 CANBUSn 1 0x001C Bit Name Default 6 0 TSEG1 470 RW 3 0 TSEG2 3 hO 6 4 31 8 ____ 2470 ___ Description TSEG1 a
94. Clear Register USBOTG EP CLR 0x084C Centrality Communications Inc 213 AT460A BI Developer s Manual Centrality Bit Name Default Description 31 0 W EPDMACHNCLR 32 h0 Endpoint DMA Channel Clear Will clear the DMA channel corresponding to the bit that is set Will also clear the DMA enable bit for the EP This register is a Write Clear register Software will always read 0 on this register e USB OTG ETD n System Memory Start Address Register USBOTG ETDO START ADDR 0x0900 0x091C Before Enabling DMA for a client ETD the corresponding register must be loaded with the ETD System Memory Start Address where the data will be stored The ETD System Memory Start Address is byte address that must be DWORD aligned ETDO ETD7 Registers have same definition Name Default Description 31 2 ETDSMSA 320 lt gt System Memory Start Address R W Starting address in system memory where DMA will put fetch data to for ETD lt n gt USB OTG EP n System Memory Start Address Register USBOTG EPO OUT START ADDR 0x0980 0x99C Before enabling the DMA for a client EP the corresponding register must be loaded with the system memory address where the data will be stored The Endpoint System Memory Start Address is byte address that must be DWORD aligned EPO EP3 OUT IN Registers have same definition Default Description 32710 Endpoint n OUT IN System Memory Start Address
95. DWROD 19 14 feno High check DWORD 31224 80 Reserved UART TX FIFO Operation Register UART_TX_FIFO_OP RISC 0x110 DSP 0x48 This register is different from FIFO of other peripheral operation register and reset bit is at bit 0 Bit Name Default Description 0 R W FIFO RESET 1 bO Set to 1 to stop the FIFO and reset the FIFO internal status including the relevant interrupt status Setto 0 in normal operation 1 R W FIFO START 1 bO Start the read write transfer when this bit is declared 31 2 300 Reserved e UART TX FIFO Status Register UART TX FIFO STATUS RISC 0x114 DSP 0x4A Bit Default Description 5 0 R FIFO LEVEL 6 hO The byte number of the valid data in the FIFO In case that FIFO is full the value of this register is 0 thus user must concatenate FIFO FULL bit with this value to Centrality Communications Inc 311 460 Developer s Manual Centrality uu determine the actual data count in the FIFO 6 FIFO FULL FIFO full status the FIFO is full when read out as 1 This bit is concatenated with FIFO LEVEL to be the actual FIFO data count 7 R FIFO EMPTY FIFO empty status Equivalent to FIFO FULL FIFO LEVEL 318 2480 e UART TX FIFO Data Register UART TX FIFO DATA RISC 0x118 DSP 0x4C DSP can only access the low 16 bits of this register Bit Default Description 31 0
96. Description 10 6 2 3 Functional 4 10 6 2 4 LCD Controller 10 6 3 2D BIIBLT Engine rtr 10 6 3 5 Overview 24 4 4 1 000 5 0000 10 6 3 6 Functional Description 2 einn etude tte eee iL du dana de Een 10 6 3 7 2D BitBLT Engine Registers 10 ellc um 10 71 OV6TVIOW 5 dus MN HE 10 7 2 System to PCI Bridge eet testet e emt Ue Pudens 10 7 2 1 PCI Bridge RISC IO Registers 10 7 2 PCI Bridge DSP IO Registers 10 7 3 ROM SRAM Controller seson rei a a E O E r E E E E ESEE a 10 7 3 1 eui n 10 7 3 2 Pin Description RP P 10 7 3 3 Address Mapping 22 11 1111 100 0 sensn 10 7 34 ROM SRAM Controller 10 74 SDIO Host Controllers gt Ier eer cr e Ud SE UTR E TELE TY FCR ETE 10 7 4 1 000010030000 rt sss sren nsn nennen nennen 10 7 4 2 Pin Description wea ea 10 7
97. Description 31 0 R YBUFFERnINT 32 h0 Y Buffer n Interrupt When asserted indicates that the Y buffer of ETD lt gt requires servicing For the OUT case the buffer has been emptied by the host and requires more data to continue the transfer For the IN case the buffer has been filled by the host and requires emptying before it can continue Writing the asserted bit back to the register clears this bit e USB OTG XY Interrupt Enable Register USBOTG HC XY INT EN 0x00A0 Bit Default Description 31 0 XYnINT_EN 320 XY Buffer lt n gt Interrupt Enable R W e USB OTG X Buffer Filled Status Register USBOTG HC X STATUS 0x00A8 Bit Default Description 31 0 XFILLn 32 h0 X Filled lt n gt Status When SET this indicates that the Centrality Communications Inc 204 AT460A BI Developer s Manual Centrality Po corresponding X Buffer is Full e USB OTG Y Buffer Filled Status Register USBOTG HC Y STATUS 0x00AC Bit Default Description 31 0 R YFILLn 3210 Y Filled n Status When SET this indicates that the corresponding Y Buffer is Full USB OTG ETD Enable Set Register USBOTG HC ETD SET 0x00CO Name Default Description 31 ETDnSET_EN 32 hO ETD lt n gt Set R W When SET indicates that an ETD is enabled and ready to be processed by the host e USB OTG ETD Enable Clear Register USBOTG HC CLEAR 0x00C4 B
98. FC_ J Reserved 2 2 USP TX DMA IO LEN U U SP transmit data length register SP TXFIFO control register SP TXFIFO check level register 0x108 SP TXFIFO CTRL 0 10 0x46 0x47 SP TXFIFO LEVEL CHK 0 114 USP TXFIFO STATUS SP TXFIFO status register 0x118 USP_TXFIFO DATA SP TXFIFO bottom U U U USP TXFIFO operation register U U Others 8 8 5 1 USP Control Registers e USP Mode Register 1 USP_MODE1 ARM9 0x0 DSP 0x0 0x1 Bit Name Default Description 0 R W SYNC MODE 1 bO USP operation mode 0 asynchronous mode 1 synchronous mode 1 R W CLOCK MODE USP clock mode 0 master mode if USP is async mode it must be set to 1 1 slave mode clock is input from other device USP transmit data loop back mode 0 no loop back 1 loop back receive data comes from the transmit data IrDA function SYNC MODE must be set to 0 0 disabled 1 enabled 1 bO 1 bO 1 bO 1 bO Transmit receive data endian mode 0 big endian MSBF 1 small endian LSBF 1 bO USP operation enable signal when set to O it will reset the USP and it s transmit amp receive control register After it s set to 1 the reset of all these register is released and then you can operate the USP 1 bO 4 RW ENDIAN_CTRL Receive data is driven at 0 sclk rising edge 1 sclk falling edge Transmit data is driven at 0 sclk rising edge Centrality Communications Inc 317
99. Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 List of Figures Atlas I Block 1i edente deridet eee irte d itidir iaidd 10 Atlas as an Infotainment and Navigation 10 RISC Subsystem Block 10 DSP Subsystem Block eene 10 DDR Connection in 16 bit 0 10 DDR Connection in 32 bit 10 SDRAM Interface in 16 bit 10 SDRAM Interface in 32 bit 10 An Example of Mode Configuration 10 Atlas 2 Clock Circuit Block Diagram 220202 00 0 0 nennen nnns 10 Oscillator Tank CIECUIL EE wedi davon v s eu arta cha Se eh edad EA a Pes 10 1 10 PG 193ESG Block Diagram ertet e eae be trio Fete rac dta ee dete ea 10 Power on off Sequence sse enne ee nnt 10 Sleep Wakeup Sequence cccececceceeececesecaeeeeeseeeeeeaeeeeenaeeecaaeeeteaeeseecaeesetieeeseeaeeeesenaees 10 Interrupt Controller Block seen 10 Block Diagram of Layer
100. HW ECC RST Set 1 will reset hardware ECC register 3 R W HALF PAGE 1 b1 Only used in 8 bit NAND Flash Set 1 will enable 256byte ECC Set 0 will enable 512byte ECC 74 29h0 Reserved 2 Flash ECC Area1 Register SM ECC AREA 1 0x30 Bit Name Default Description 32 0 ECC 1 32 h0 Hard ware ECC result store register NAND Flash ECC Area2 Register SM ECC AREA2 0x34 Bit Name Default Description 32 0 R ECC AREA2 32 h0 Hard ware ECC result store register NAND Flash DMA IO Control Register SM DMA IO CTRL 0xF00 Bit Default Description 0 write to peripheral 2 R W Flush the DMA receive FIFO in case the data_length set at the peripheral side doesn t match the dword size set in the DMA control 0 little end write read 4 R W 1 write command and address to smartmedia and did not read write data 31 5 Reserved Flash Length Register SM IO LEN 0xF04 The smallest data size is DWORD i e bit1 and bit 0 of this register will be ignore Bit Default Description 15 0 R W DATA_LEN 1610 byte length of a DMA or I O transfer If rd set to zero the I O DMA transfer works continuously until it is stopped 31 16 160 Flash FIFO Control Register SM FIFO CTRL OxF08 In read mode when FIFO STATUS 5 2 FIFO REG 7 4 interrupt will
101. I O Bridge operation is over User set this register to 1 Then read this register until it is 0 311 __ 7 31 e Bridge interrupt status INT STATUS 0x0808 Centrality Communications Inc 250 460 Developer s Manual Centrality Bit Name Default Description O R W INT STATUS IO bridge status write 1 to clear e Arbiter Status Register 0x080C Bit Name Default Description 3 0 R lt 3 0 gt 410 lt 3 0 gt means which master is occupying the bus currently when IO Bridge generates an interrupt the RISC can read these bits For example bit lt 2 gt is 1 means Master2 is occupying the bus currently There might be following situation after arbiter assert interrupt the Master begins to transfer data and finished it before RISC respond to the interrupt So there might be wrong information However with time out value sufficient large things like this will not happen 314 280 __ Reserved Bridge clock ratio IOBG CLKRATIO 0x0810 Name Default Description CLK_RATIO 2 b01 IO bridge clock ratio 2 b00 SYS CLK IO CLK 1 1 2 b01 SYS CLK IO CLK 1 2 2 b11 SYS CLK IO CLK 1 4 Others are not supported and should not be written 31 2 3010 _ Reseved 2 8 3 DMA Controller 8 3 1 Overview DMA_CHx_D4WT lt 31 0 gt DMA_CHx_D4RD lt 31 0 gt Memory I F Dat
102. Oe RTR __ NOTE The received data length code the frame information byte represents the length of the data sent which may be greater than eight bytes However the maximum number of data bytes received will be eight Acceptance Code Registers CANBUSn ACRO CANBUSn ACR3 0x0040 0x004C Acceptance Mask Registers CANBUSn AMRO0 CANBUSn AMR3 0 0050 0 005 The CANBUS controller filters the incoming data stream discarding any message that does not have the required bit pattern in its identifier The bit pattern against which the message identifier is matched is recorded in the Acceptance Code Registers CANBUSn_ACR0 3 masked by the values recorded in the Acceptance Mask Registers CANBUSn_AMR0 3 0 s in CANBUSn_AMRO0 3 identify the bits at the corresponding positions in CANBUSn ACHRO0 3 which must be matched in the message identifier 175 identify the corresponding bits as don t care The bit patterns recorded as CANBUSn_ACRO 3 can either be used as a single 4 byte filter or two shorter filters The selection is made through the AFM bit of the Mode register bit 3 If AFM 1 a single filter will be applied if AFM 0 two filters will be applied Where two filters are used the incoming message will be accepted if its identifier matches either filter The way in which the bit patterns defined by CANBUSn ACRO0 3 are applied further depend on whether the incoming message is in Standard Frame
103. Overflow When the TX FIFO Full status is indicated if DMA interface continues to write audio data into TX FIFO the TX FIFO overflow will be triggered Generally the interrupt will not arise because when the TX FIFO is full the DMA request will not be generated and it can guarantee that no data will be written into TX FIFO e TX FIFO Underflow When the TX FIFO is in empty status while DMA controller can t serve CODEC transmission channel the further data request from audio CODEC will trigger the TX FIFO underflow interrupt RX FIFO Full RX FIFO empty RX FIFO Underflow RX FIFO Overflow When RX FIFO is in full state while DMA controller can t transfer the data into SDRAM more audio input data stream will trigger the RX FIFO overflow interrupt 8 6 7 Audio CODEC Registers Table 76 Audio CODEC Register Mapping RISC Register Description Address lt 11 0 gt 0 0004 0 0 Reserved 018 97 auxiliary RX slot selection 0 003 Reserved 7C 0 0 80 CODEC TX AUX IO CTRL CODEC auxiliary TX DMA transmit mode selection 0x0B84 ees 0 0 88 CODEC TX AUX CTRL CODEC auxiliary TX FIFO transfer threshold setting _ ___ ________ OxBBC Reseved Centrality Communications Inc 291 AT460A BI Developer s Manual Centrality OxOBC8 CODEC RX AUX FIFO CTRL CODEC auxiliary RXFIFO transfer threshold OxOBCC CODEC RX AUX FIFO LEVEL
104. RISC FIQ interrupt input e Interrupt DSP Access Enable Register INT_DSP_ACCEN RISC 0 001 DSP 0x00E At default all the register can only be written RISC only In order for DSP to write INT DSP MASK register user should set INT_DSP_ACCEN register by RISC Bit Name Default Description 0 05 EN 100 DSP Access enable 31 1 310 Reserved e Chip ID Register CHIP ID RISC 0x0020 DSP 0x010 This register is read only it contain the CHIP ID for different chip version Name Default Description 15 7 CHIP_ID lt 15 0 gt 1610 CHIP ID WR 3136 ____ e Interrupt Controller DSP Pending Register INT DSP1 PENDING RISC 0x0024 DSP 0x012 0x013 The INT_DSP1_PENDING contain one flag per interrupt 32 total that indicates an interrupt request to IRQL1 has been made by a unit Inside the interrupt service routine the INT_DSP1_PENDING are read by DSP to determine the interrupt source In general software then reads status registers within the interrupting device to determine how to service the interrupt The following table shows the bit locations corresponding to the 32 separate interrupt pending status flags in the INT_DSP1_PENDING This is a read only register Bit Name Default Description 31 0 DSP1 lt 31 0 gt 32 h0 DSP Interrupt pending bits 0 interrupt pending 1 Interrupt pending e Interrupt Controller DSP Level Register INT DSP LEVEL
105. SET Writing with this bit ______ has no effect 15 10 Reserved rved 16 R omes Connect Status Change When a connect or disconnect event occurs this bit will be SET A write with this bit SET will clear this bit Writing a 0 has no effect If CurrentConnectStatus is cleared when a SetPortReset SetPortEnable or SetPortSuspend write occurs this bit is SET to force the driver to re evaluate the connection status since these writes should not occur if the port is disconnected Only a write back with this bit SET will clear 17 R PRTENBLSC Port Enable Status Change This bit is set when hardware events cause the PortEnableStatus bit to be cleared Only a write back with this bit SET will clear this bit 18 R PRTSTSTSC Port Suspend Status Change This bit is set when the resume sequence has been fully completed A write back with this bit SET or when ResetStatusChange is SET when will clear this bit 19 R OVRCURIC Port Over Current Indicator Change This bit is SET when an PortOverCurrentIndicator has changed on this port and is only valid if over current conditions are reported on a per port basis Only a write back with this bit SET will clear this bit 20 R PRTRSTSC Port Reset Status Change This bit is SET at the end of the 50 ms port reset signal 2 write back with this bit SET will clear 312 Centrality Communications Inc 210 AT460A BI Developer s Manual
106. START Start the FIFO transfer when this bit is declared 1 R W FIFO RESET 100 Set to 1 to stop the FIFO and reset the FIFO internal status including the relevant interrupt status Set to 0 in normal operation 312 __ 2 Reserved O Reserved e FIFO Status Register CAM_FIFO_STATUS 0x058 Bit Name Default Description 7 0 R FIFO LEVEL 8 h00 The byte count of the valid data in the FIFO varies from 0 to 255 bytes In case FIFO is full the value of this register is 0 thus user must concatenate FIFO_FULL bit with this value to determine the actual data count in the FIFO Centrality Communications Inc 281 460 Developer s Manual Centrality 8 FIFO_FULL 1 bO FIFO full status the FIFO is full when read out as 1 This bit is concatenated with FIFO LEVEL to be the actual FIFO data count 9 R FIFO EMPTY 160 FIFO empty status equivalent to FIFO FULL FIFO LEVEL 0 3130 __ Reseved e Read FIFO Data Register RD FIFO DATA 0x05C Bit Name Default Description 31 0 FIFO DATA 31h00 FIFO data read by RISC or DSP 8 6 Audio CODEC 8 6 4 Overview The Atlas I Audio CODEC interface be used to connect to either AC97 125 type CODEC CODEC interface share pins with USP1 For 125 CODEC like UDA1343 there is a separate control interface L3BUS besides of the digital audio interface In this case the control inte
107. TRACEPKT lt 1 gt 141 14 ROM SRAM Data ED lt 18 gt TRACEPKT lt 2 gt 142 014 ROM SRAM Data ED lt 19 gt TRACEPKT lt 3 gt 2 5 ROM SRAM Data ED lt 20 gt TRACEPKT lt 4 gt Da es xmas romero Da ve arc romero Da me xmas romero Da arc romero merca Da er bs ve uma E X_FD lt 30 gt PDUWOBDGZ ROM SRAM Data ED lt 30 gt TRACEPKT lt 14 gt Ba wr rover ennemis Ts ro Ron ra xmes T ronez oua ae PcPro ach rac romero De m romero romero nsns sessi Centrality Communications Inc 351 AT460A BI Developer s Manual KE Centrality COMMUNICATIONS fe ens ROM SRAM Address PDUWOBDGZ lt 19 gt lt 19 gt _ lt 1 gt P14 PCMCIA Input Acknowledge EXT CLK me revsa rouwoencz ma rouwoencz povonsewo me rouwoencz L13 PCMCIA Reset EXT B __ REG B Pouwosoz
108. This value is in the number of full speed bit times The nominal value is set to be 11 999 J Je 150 ____ __ _ __ 15 W RSTFRM 1 bO Reset Frame When set the frame remaining register will be cleared and be set to the value in the FRMINTERVAL 29 16 14 h2A2 Frame Interval Periodic R W F The value written her sets the amount of time in a frame that periodic packets can be sent This value is in the number of full speed bit times 31 30 0 Reserved 5 Frame Remaining Register USBOTG TL FRM REMAINING 0x0018 Bit Name Default Description 15 0 J 160 29 16 R 1480 Frame Remaining This number represents the number of full speed bit times still remaining in the current frame This counter is decremented at each bit time When it reaches zero loading the FRMINTERVAL value specified in FRMREMN at the next bit time boundary resets it When entering the UsbOperational state the host controller re loads the content with the FRMINTERVAL and uses the updated value from the next SOF Centrality Communications Inc 193 AT460A BI Developer s Manual Centrality 31 30 20 Reserved USB OTG HNP Control Status Register USBOTG_HNP_CTRL L 0x001C Bit Name Description DENEN __ Reserved ___ R W ABBUSREQ 1 bO A B Bus Request 1 The software is requesting to be A MASTER or B MASTER 2 R W ADROPBUS A Drop VBus 1 The software
109. USP register it must access it two times to read or write a 32 bit register completely There are three methods for the Atlas 1 to access the TX_FIFO and RX_FIFO of USP e mode with Interrupt e mode without Interrupt e DMA mode The TX_FIFO and the RX_FIFO can be accessed in I O mode Both the TX_FIFO and the RX_FIFO have the interrupt state registers to reflect their state The operation in the I O mode usually use these interrupt to decide whether to write or read If the DMA access the TX_FIFO and the RX_FIFO they cannot be accessed by the RISC DSP NOTE In all three modes before transmitting operation the TX_FIFO must first be reset by set the FIFO_RESET bit of TX_FIFO_OP register to 1 and then it is started by clear FIFO_RESET and set the FIFO_START bit of TX_FIFO_OP register There is the same procedure for the RX_FIFO before operation it e mode with Interrupt The I O mode with interrupt is suitable for those small data cases which are time sensitive There are four interrupts for the transmit operation TX_DONE TXFIFO_SERVE TXFIFO_EMPTY TX_UFLOW After one data is put from the TX_FIFO to the tx_shifter and transmitting starts TX_DONE interrupt will happen If the data in the TX FIFO is less than parameter defined in the FIFO_THD bits of register USP TX FIFO CTRL the TXFIFO SERVE interrupt will happen If the TX FIFO is empty the TXFIFO EMTPY interrupt will happen TX UFLOW is used for the underflow case of
110. W CTS STATUS This bit is the complement of the pin of CTS Its value follows that of CTS pin If loop back mode is setting this bit is connected to the output of RTS 5 R W DSR STATUS This bit is the complement of the pin of DSR Its value follows that of DSR pin If loop back mode is setting this bit is connected to the output of DTR 6 R W RI STATUS 1 bO This bit is the complement of the pin of RI Its value follows that of RI pin If loop back mode is setting this bit is set to 0 7 R W STATUS 1 b0 This bit is the complement of the pin of DCD Its value follows that of DCD pin If loop back mode is setting this bit is set to O 3 188 240 Reserved UART Transmit Receive Enable Register UART TX RX EN RISC 0x4C DSP 0x26 Bit Name Default Description 0 R W 1 bO Receive enable bit 0 disabled 1 enabled 1 R W TX EN 1 bO Transmit enable bit 0 disabled 1 enabled Centrality Communications Inc 307 460 Developer s Manual KS Centrality 312 __ 300 Reserved e UART Clock Divisor Register UART DIV RISC 0x50 DSP 0x28 Default _ Description IOCLK DIV IOCLK fi clock baud SAMPLE DIV 1 1 21 16 SAMPLE DIV 6 hOf SAMPLE DIV should be larger than or equal to R W 15 3122 domo In normal mode SAMPLE DIV is always set to 15 and IOCLK is fio baud 16 1 In order to get the accurate hig
111. XRFSi1 GPIO group1 offset 25 After reset GPIO will have control over these pins User can write corresponding GPIO control registers to give the control of these pins to USP1 CODEC Centrality Communications Inc 77 AT460A BI Developer s Manual Centrality The priority of the above shared functions is as following e If GPIO has control over these pins both USP1 CODEC can not control the pin e If GPIO dos not have control over these pins the CODEC EN bit in PIN register determines whether USP1 or CODEC have control over these pins USP2 UARTG ETM Part 1 Pin Pin Name UART6 USP2 gt ___ GPIO group offset 26 _ X TXD 2 TRACESYNC__ GPIO group offset 27 X RXD2 lt 2 gt GPIO group1 offset 28 X TFS 2 X TXD 6 5 lt 1 gt GPIO 1 offset 29 IX RFS 2 6 5 lt 0 gt group1 offset 30 After reset GPIO will have control over these pins User can write corresponding GPIO control registers to give the control of these pins to USP2 UARTE6 The priority of the above shared functions is as following e is enabled during debug ETM9 will have control over these pins no matter which setting it is e Else if GPIO has control over these pins both USP2 UARTO can not control the pin e Else if GPIO does not have control over these pins the USP lt 0 gt bit in 5
112. ____ 0x480 0x4FF 50 54 _ 0 500 0 572 0x580 0x3FF_ Ox600 OxG7F Ox680 OxGFF 0x700 0x77F_ Ox780 OX7FF 0 500 0 57 lO 95 0x580 0x3FF P 0x600 0x67F ____________ Reserved 0 680 0 6 Od Reserved 0 700 0 77 Reserved 0 780 7 IO jReseved 0 Ox2000 0QFFF GPS Control Registers 0x2800 0x2FFF_ DSP interface ox3000 03BFF PM __ 6 2 3 3 DSP Subsystem Registers Table 7 DSP Subsystem Register Mapping RISC DSP DMX Register Description Address Address lt 12 0 gt lt 11 0 gt 0x0000 _________ DSP_REG_MODE ____ DSP register mode _____ 0x0028 0x40 f Reserved Centrality Communications Inc 24 AT460A BI Developer s Manual Centrality 0 0054 55 ____ _0 006 0 7 0x0084 Ox1C82 0x1C83_ DSP_GEN_REG1 lt generalregister1 0x0088 0 1 84 0 1 85 DSP GEN REG2 DSP generalregister2_ 0x008C 0 1 86 0 1 87 DSP GEN REG3 DSPgeneralregister3 Reserved e DSP Register Mode Register 06 REG MODE RISC 0 0 Bit Default Description 0 R W RISC_DSP 1 b0 0 DSP take the DMA control 1 RISC take the DMA control 151 15 Reserved 16 STANDBY 1 bO DSP core standby control R W 1 put DSP core standby 0 put DSP in normal mode 3117 150 Reserved _____________
113. _______ 188 ____ Reevd 0 18 GPIO1 INT STATUS GPIO group1 interrupt status for RISC 0x190 0x1FC Reserved 0x200 0 GPlOcontrlforGPIO64 o204 X j GPIO2CTRL GPIO control for GPIO65 o208 2 2 9 GPlOcontolforGPlO00 1 2 GPIO2 CTRL3 GPlOcontr forGPIO67 o210 GPIO control for GPIO68 0 214 2 5 GPlOcontolforGPlO69 218 GPIO2 CTRL6 GPlOcontrlforGPIO7O ____ o21c j GPIo2CTRL7 9 GPlOcontolforGPIO71 0x220 GPlOcontolforGPIO72 0x224 GPIO2 CTRL9 GPlOcontolforGPIO73 _ _ 0 228 X GPIO2CTRLIO GPlOcontolforGPIO74 0 2202 GPIO2CTRLM GPlOcontolforGPIO75 _____ 0 230 7 GPIO2 GPlOcontrlforGPIO76 _____ 0x234 GPIO2CTRLI3 GPIO control for GPIO77 0x238 GPIO2CTRLI4 GPIO control for GPIO78 ____ 0x23C_ _______ GPIO2_CTRL15 GPIO control for GPIO79 __ 0x240 GPIO2_CTRL16 GPIO control for GPIO80 0x244 2 CTRL17 GPIO control for GPIO81 0x248 GPIO2 CTRLI8 GPIOcontrolforGPIO82_ 0x24C GPIO2_CTRL19 GPIO control for GPIO83 0x250 GPIO2_CTRL20 GPIO control for GPIO84 0x254 ______ GPIO2_CTRL21 GPIO control for GPIO85 _____ 0x258 GPIO2_CT
114. address e Xlength e Y length The idea of a 2 D DMA is shown in the following diagram Centrality Communications Inc 256 AT460A BI Developer s Manual Centrality COMMUNICATIONS DMA Width Y Length lt XLenth gt 52 2 0 If the user specifies the Y length as 0 X length equals to the DMA Width then this 2 0 DMA will reduce to a 1 D DMA If the user configures the X length greater than DMA Width then the extra data will be wrapped around to the next data line It will corrupt DMA transfer for multiple line 2 0 DMA If it s only 1 D DMA then there is no problem The following diagram shows the wrap around of the extra data in case of X length greater than DMA Width DMA X Length DMA Width Figure 53 2 D DMA Wrap Around X length gt DMA Width 8 3 3 3 Loop DMA Centrality Communications Inc 257 AT460A BI Developer s Manual Centrality If X length is set to 0 it is special mode of the DMA loop mode In loop mode the DMA will never finish until user force to stop it by writing 1 50 to the CH VALID register The DMA will keep looping as described in the following figure DMA_WIDT p BUFA Y LENGTH BUFB Figure 54 DMA address change if X_LEN 0 As shown in the above figure the DMA address will keep increasing until reaching the end of a loop area whose size is defined by DMA_WIDTH Y_LE
115. almost the same and is not included Other Qualified RISC Interrupt Interrupt Bits Level Register RISC Interrupt Mask Register Interrupt Source Bit FIQ Interrupt Pending Register IRQ Interrupt Pending Register FIQ Interrupt Pending Register Figure 16 Interrupt Controller Block Diagram Centrality Communications Inc 58 460 Developer s Manual Centrality For the RISC the first level of structure is represented by the interrupt controller IRQ pending register INT_IRQ_PENDING and the interrupt controller FIQ pending register INT_FIQ_PENDING The INT_IRQ_PENDING register contains the interrupts that are programmed to generate an IRQ interrupt The INT_FIQ_PENDING register contains all valid interrupts that are programmed to generate a FIQ interrupt The routing is programmed via the RISC interrupt controller level register INT_RISC_LEVEL NOTE In most cases the root source of an interrupt can be determined by reading these two registers followed by the status register within the device to find the exact function needing service For the DSP we use low level sensitive interrupts of the DSP core IRQL1n IRQLOn The routing of interrupts to these two interrupts is programmed by the DSP interrupt controller level register INT_DSP_LEVEL This is a more simple process than with the RISC all the qualified interrupt bits will be stored
116. and DA DATA BIT_CLK and AD DATA are inputs from the AC97 CODEC and FRAME SYNC and DA DATA are generated by Atlas and output to the CODEC This interface also allows the host RISC DSP to read and write registers in the CODEC as part of the AC97 frame It has the ability to turn on off the left and right sound channels separately And the AC97 interface can support both normal mode 48 KHz and VRA mode 44 1 KHz 22 05 KHz 11 0125 KHz and 8 KHz In Atlas II the AC97 interface is sharing the pin with one of the Universal Serial Ports USP1 Table 73 AC97 CODEC Interface Pin Description Direction Description X_SCLK1 BIT_CLK Input 12 288 Clock signal input from external AC97 CODEC X TXD1 DA DATA Serial digital output data to AC97 CODEC X RXD1 AD DATA Serial digital input data from AC97 CODEC X TFS1 FRAME SYNC 48 KHz Frame signal for synchronization 8 6 6 Functional Description 8 6 6 1 RISC I O Interface User can program the audio codec interface registers to configure the codec controller mode or inquiry the controller status All the RISC I O access to audio codec interface registers is fixed latency In Atlas the registers of audio codec interface occupy 64KB space from 0x80060000 to 0x8006FFFF There three groups of registers which are located at the register space with the different offset address Centrality Communications Inc 283 AT460A BI Developer s Manual LS Centrality C
117. be generated In write mode when FIFO STATUS REG 5 2 FIFO REG 7 4 interrupt will be generated Centrality Communications Inc 267 460 Developer s Manual Centrality 1 0 R W FIFO WIDTH 2000 Bit Name Default Description 7 2 R W FIFO THRESHOLD 6710 A threshold in byte to trigger an interrupt An interrupt is triggered when the count of data in the FIFO reaches the threahold 318 24 Flash FIFO Level Check Register SM FIFO LEVEL OxFOC Bit Name Default Description 4 1 6 0 Reserved 2 4 Flash FIFO Operation Register SM FIFO OP OxF10 0 R W FIFO START 1 b1 Start the read write transfer when this bit is declared Bit Default Description 1 R W FIFO_RESET 1 bO Internally link to start ini Setto 1 to stop the fifo and reset the fifo internal status including the relevant interrupt status Set to 0 in normal operation 72 1300 Flash FIFO Status Register SM FIFO STATUS OxF14 Bit Default Description 5 0 R FIFO_LEVEL 6 hO The byte count of the valid data in the FIFO In case FIFO is full the value of this register is 0 thus user must concatenate FIFO_FULL bit with this value to determine the actual data count in the FIFO 6 R FIFO FULL 1 bO Fifo full status the fifo is full when read out as 1 This
118. bit a watchdog match event will be generated and it will cause the reset of most of the on chip modules 5 5 4 OS Timer Registers Table 19 OS Timer Register Mapping RISC Address Register Description lt 11 0 gt Others d Cd Reserved e OS Timer Counter Low Register TIMER COUNTER LO 0x0000 The OS timer count low register is the low 32 bit of the 64 bit counter that increments on rising edges of the timer clock This counter can be read or written at any time It is recommended that this register to be write protected through the MMU protection mechanisms BE Name Default Description CN lt 31 32 h0 OS Timer Counter low 32 bit value e OS Timer Counter High Register TIMER COUNTER 0x0004 The OS timer count high register is the high 32 bit of the 64 bit counter that increments on rising edges of the timer clock This counter can be read or written at any time It is recommended that this register to be write protected through the MMU protection mechanisms Bit Default Description CN lt 63 32 gt 32 hO OS Timer Counter high 32 bit value Centrality Communications Inc 68 AT460A BI Developer s Manual Centrality RW OS Timer Match Register 0 5 TIMER MATCH x 0x0008 0x001C These registers are 32 bits wide and are accessible by the RISC They are compared with the lower 32 bit of TIMER_COUNTER following every timer clock cycle If any of these
119. bit is concatenated with FIFO LEVEL to be the actual FIFO data count 7 R FIFO EMPTY 1 b1 Fifo empty status FIFO FULL or FIFO LEVEL 3018 1240 Flash FIFO Data Register SM FIFO DATA OxF18 Bit Default Description 31 0 R FIFO DATA 320 The fifo read write data register Centrality Communications Inc 268 AT460A BI Developer s Manual Centrality 8 5 Video Input Port 8 5 1 Overview This block interfaces with the DVD 2 decoder TV decoder CMOS imaging sensor processes the 16 bit input from these device through a series of hardwired logic The image is framed by HSYNC and VSYNC signals and is clocked by PIXCLK The sync signals and pixel clock can be inverted as needed Two counters will count the X and Y positions respectively of the current pixel The user can define an active region by specifying the beginning and ending X and Y coordinates In the active region each 16 bit sample will be combined to a 32 bit value This value then sent to the FIFO to be DMA ed to the system memory or read by RISC or DSP This video input port supports image scaling and translation for picture in picture or different video overlay display schemes Finally the Video Input Port can generate an interrupt to the controller at a specified line during each frame This may be useful for video application Signal VSYNC Interrupt Counter EX HSYNC PXCLK Active lt l
120. bits lt 30 4 gt is the first valid pixel for this channel When used as OSD the pixel data can be 2 bit 4 bit 8bit 16 bit pixel When used as Dual Scan mode the pixel data can be 2 bit 4 bit 8 bit pixel Example 2bits pixel Big endian in word and in byte 0000 bits lt 31 30 gt 0001 bits lt 29 28 gt 1111 bits lt 1 0 gt 30 4 DMA_BASE_ADDR 2710 DMA address of the starting memory location for the R W OSD data 31 DMA_MODE 1 bO Continuous mode DMA R W 1 when this DMA completes will automatically generate a DMA with exactly the same setting 0 each DMA must be explicitly started by software XSizefor OSD DMA LCD OSD XSIZE 0x11C Default Description 1380 This value specifies the number of consecutive 4 DWORD bursts per line for the OSD DMA This value should be inclusive of any partial DWORD s used per line OSD XSIZE OSD HEND Centrality Communications Inc 131 460 Developer s Manual KS Centrality OSD_HSTART 1 OSDBPP 8 16 1 3113 1910 Y Size for OSD LCD OSD YSIZE 0x120 Bit Name Default Description 12 0 OSD_YSIZE 1310 This value specifies the number of lines for the OSD R W Each line designates a segment of consecutive DWORD s with a skip in between OSD YSIZE OSD VEND OSD VSTART 1 3113 19 e Skip value for OSD LCD OSD SKIP 0x124 Bit __ Default Description 12 0
121. bus error This means Reset Mode is entered again the Transmit Error Counter is initialized to 127 the Receive counter is cleared and the relevant Status and Interrupt register bits are set Clearing Reset Mode now will perform the protocol defined Bus Off recovery sequence waiting for 128 occurrences of the Bus Free signal 318 240 e CANBUS Transmit Buffer Register Write CANBUSn 0x0040 0x0070 Read CANBUSn 0x00180 0x01B0 Transmit Buffer has length of 13 bytes It accommodates one Transmit message of up to eight data bytes Write only access to the Transmit Buffer is provided in Operating Mode using RISC address 0x40 70 The global layout of the Transmit Buffer is shown below It is important to distinguish between Standard Frame Format SFF messages and the Extended Frame Format EFF messages The Transmit Buffer is subdivided into descriptor and data fields The first byte of the descriptor field holds frame information It describes the frame format SFF or EFF remote or data frame and the data length This is then followed by either two identifier bytes for SFF or four bytes for EFF messages The data field contains up to eight data bytes Table 85 Transmit Buffer Layout Centrality Communications Inc 337 AT460A BI Developer s Manual Centrality Standard Frame Format SFF Extended Frame Format EFF CAN Address Field CAN Address Field The bit layout of
122. clock domains one is SYS_CLK and the other is IO CLK SYS can be 1X 2X or 4X of the IO_CLK So the write pulse width should be able to be programmable Bit Name Default Description 3 0 R W 0 lt 3 0 gt Write pulse width for System clock domain 7 4 R W PW1 lt 3 0 gt 41 Write pulse width for IO clock domain When SYS CLK IO 1 PW1 0 When SYS CLK IO CLK 2 PW1 1 When SYS CLK IO 4 PW1 3 31 8 2480 Reserved RISC Interface Timeout Register RISCINT_TIMEOUT 0x001C When RISC accesses I O device and the devices has no response in a certain period the RISC interface will be timeout and generate an interrupt Bit Default Description 15 0 R W TO lt 15 0 gt 16 hFFFF Timeout value 30 16 ismo 31 R W 1 bO Timeout enable 1 Enable timeout check 0 Disable timeout check default RISC Interface Timeout Interrupt Register RISCINT TIMEOUT INT 0x0020 When RISC accesses device and the devices has no response in a certain period the RISC interface will be timeout and generate an interrupt Bit Name Default Description 0 R W TO_INT 1 bO Timeout interrupt status 1 There is timeout interrupt 0 No timeout interrupt Write a 1 to this bit will clear the interrupt 311 __ RISC Interface Pre fetch Enable Register RISCINT PREFETCH 0x0024 There is a pre fetch FIFO inside of the R
123. completed this bit is cleared and PortResetStatusChange is SET This bit cannot be set if CurrentConnectStatus is cleared write SetPortReset The HCD sets the port reset signaling by writing a 1 to this bit Writing a 0 has no effect If CurrentConnectStatus is cleared this write does not set PortResetStatus but instead sets ConnectStatusChange This informs the driver that it attempted to reset a disconnected port Ze se Reserved Se 8 R W PRTPWRST 1 bO Port Power Status read PortPowerStatus This bit reflects the port s power status This bit is cleared if an over current condition is detected HCD sets this bit by writing SetPortPower HCD clears this bit by writing ClearPortPower When port power is disabled CurrentConnectStatus Centrality Communications Inc 209 AT460A BI Developer s Manual Centrality PortEnableStatus PortSuspendStatus and PortResetStatus should be reset write SetPortPower The HCD writes a 1 to set the PortPowerStatus bit Writing a 0 has no 9 R W LSDEVCON 1 bO Low Speed Device Attacjed read LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port When SET a low speed device is attached to this port When CLEARED a full speed device is attached to this port This field is valid only when the CurrentConnectStatus is set write ClearPortPower The HCD clears the PortPowerStatus bit by a write with this bit
124. current highest priority enabled pending interrupt Bit Name Default 7 0 R INT_ID lt 7 0 gt 8 hff 34 8 1 1 Interrupt ID Description Reserved Following table gives detail information about the priority and description of each ID the smaller the ID value the higher the interrupt priority ID value Description nterrupt from TIMERO nterrupt from RTC ALARM nterrupt from RTC TIC nterrupt from DMA nterrupt from UPS3 terrupt from USP2 nterrupt from USP1 nterrupt from USPO nterrupt from SYSTEM nterrupt from GPS nterrupt from USB nterrupt from CODEC 13 nterrupt from SMARTMEDIA nterrupt from YUVCHG nterrupt from IPOLATE nterrupt from DSP IF nterrupt from IDE terrupt from SDIO terrupt from YUV2RGB terrupt from PCICOPY terrupt from GPIO GROUP 5 terrupt from GPIO GROUP 4 terrupt from GPIO GROUP 3 terrupt from GPIO GROUP 2 terrupt from GPIO GROUP 1 nterrupt from GPIO GROUP 0 nterrupt from PCMCIA nterrupt from EXTPORT nterrupt from CAMERA gt 5 N 45 9 Centrality Communications Inc 66 13 InteruptromGPS 22 22 22 2224 9 0 7 2 __________ 22 interruptfromIDE 3 lnteruptromSDIO 25 InterruptfromPCICOPY 26 Interrupt from GPIO GROUP5 27 InterruptfromGPIOGROUP 4 28 Interrupt from GPIO 29 InterruptfromGPIOGROUP2 _ 30 ____ Interrupt from G
125. data memory interfaces that connect directly to the USB OTG core To connect the USB OTG core to internal PCI bus the PCI to AHB conversion is needed It converts the PCI target signal to the AHB slave interface connects the request of AHB master to the PCI arbiter and converts the AHB master signal to the PCI master 7 5 3 2 Internal SRAM The USB OTG interface has three different memories 32 DWORD EP memory 32 DWORD ETD memory and 128 DWORD DATA memory All the three memories are implemented by Single Port SRAM Only the Host Controller uses the ETD memory and only the Function Controller uses the EP memory Both Host Controller and Function Controller share the DATA memory The ETD memory can contain up to 8 ETDs each of them comprised by 4 DWORDs Software has full Read and Write access to the ETD memory All the unused fields in the ETD structure should be initialized to 0 The EP memory can contain up to 4 logical endpoints 8 physical endpoints each of them comprised by 4 DWORDs Each logical endpoint can be IN OUT or IN OUT each physical endpoint can be either IN or OUT Software has full Read and Write access to the EP memory All the unused fields in the EP structure should be initialized to 0 7 5 3 3 USB OTG Transceiver The transceiver TSMC TPD013G3 is separated as three major blocks voltage detector Centrality Communications Inc 187 AT460A BI Developer s Manual Centrality charge discharge U
126. depending on the external power control circuit 13 must be lona enouah until 12MHz Clock is stable t1 gt 10ms 12 gt 0 460 Developer s Manual 73 Centrality Communications Inc Centrality 5 6 8 Reset Controller Registers Table 21 Reset Controller Register Mapping RISC Address Register Description lt 11 0 gt 0x0000 RESET SR Reset Controller Software Reset Register 0x0004 RESET STATUS Reset Controller Status Register Others Reseved Reset Controller Software Reset Register RESET SWR 0x0000 Writing a one to each bit from bit30 to causes the corresponding block to be reset Writing a one to the most significant bit SYS RST causes all on chip resources to reset except the Power Manager RTC Memory controller Reset controller Resource Sharing Controller and GPIO controller Writing zero to the software reset bit will clear the corresponding reset Care should be taken to restrict access to this register by programming MMU permissions For reserved bits writes have no effect This register will be reset to default value by hardware reset only Bit Default Description 0 R W DSP_RST 190 DSP Core software reset 1 Reset The following are the same R 2 R W 3 R W 4 R 5 R W 6 R W R 10 R W E 12 R W 13 R W 14 R W 15 R W 20 10 Reserved W W 7 R W GPS RST GPS software reset
127. falling edge of CLK on the receiving side of AC link The AC link is bi directional fixed clock rate serial data stream AC link employs a TDM Time Division Multiplex scheme that divides each audio frame into 12 outgoing and 12 ingoing data streams each with 20 bit sample resolution The Atlas II AC97 Controller handles 16 bit PCM audio streams input and output as well as accessing control register Table 74 AC link Output Slots Centrality Communications Inc 284 AT460A BI Developer s Manual Centrality Slot Name Description Data out tag Indicates which slots contain valid data ADDR write port write port play back play back programmable and only one slot can be valid Table 75 AC link In ut Slots Slot Description O Datalntag Indicates which slots contain valid read port request data port record record programmable but only one slot is valid GPIO read port 8 6 6 3 1 Register Operations AC link slot 1 and slot 2 are used as AC97 command port to control AC97 CODEC features and monitor status The command port supports up to 64 16 bit read write registers addressable on even byte boundaries AC link output frame from Atlas II AC97 Controller interface to AC97 CODEC Slot 1 indicates the whether the current control transaction is a read or write operation and also specifies the target register address If it s a write operation
128. figure shows the clock circuit architecture in Atlas II The whole circuit can be divided into 3 parts e Oscillator e PLL e Multiplexers amp Dividers These stages will be explained in detail in the following sections 5 2 4 Oscillator Centrality Communications Inc 39 AT460A BI Developer s Manual Centrality There are two oscillator pads in 2 one is a high speed oscillator pad TSMC PDXOE3DG the other is a real time oscillator pad TSMC PDXOE4DG The PDXOE3DG is designed to oscillate for crystal samples from 2MHz to 30 2 For applications out of 2 30MHz range please contact with Centrality IC Design Group for further suggestions The PDXOE4DG is a low power 32 768 KHz crystal oscillator To ensure the oscillation start up the tank circuit must provide a negative resistance Re at least 5 times greater than the equivalent series resistance ESR of the crystal sample The greater the negative resistance provided the faster the crystal starts up To select the proper crystal is crucial to make the oscillator work stably The key parameters of the crystal lie in CL load capacitance and the maximum ESR at the target frequency Reducing the CL can help increase the negative resistance of the tank circuit but if CL is too small the deviation from the target frequency increases because of the growing percentage of the capacitance variation Therefore there is a trade off between the short sta
129. following figure shows the functional block diagram of the UARTO Centrality Communications Inc 304 AT460A BI Developer s Manual Centrality DMA amp FIFO INT CTRL TX RX logic Transmit RI t module Reg File Baud rate Control Control module RX FIFO Receive DMA interfade CTRL module DSP interface DMA amp FIFO INT CTRL data path gt control path Figure 72 UARTO Functional Block Diagram UART6 amp 7 do not have the TX FIFO and RX FIFO blocks 8 7 4 UART Registers Each UART in Atlas II has the same set of registers so there offset address is the same NOTE The Modem control and FIFO control registers of UART687 are not functional Accessing these registers will have no effect The actual address of the USP register is equal to the USP base address plus the offset address e UARTO base address 0x80000000 UART6 base address 0x80100000 UART7 base address 0x80110000 Table 79 UART Register Mappin RISC DSP I O Register Description Address Address lt 11 0 gt lt 7 0 gt UART_LINE_CTRL UART line control register UART MODEM CTRL UART modem control register 0x48 UART MODEM STATUS UART modem status register 08 Ox4c 0x26 UART_TX_RX_EN UART transmit amp receive enable register Centrality Communications Inc 305 AT460A BI Developer s Manual Centrality UART_DIVISOR UART baud rate divisor register UART INT EN UART interru
130. gt USP RX FIFO level check register USP FIFO LEVEL 9 0 12 DSP 0x56 0X57 Name Description FIFO_SC lt 9 0 gt Stop check in DWORD EN gt 2 740 M 0 gt ho Low check in EE gt R W 22 207 FIFO HC 9 0 3 0 High check in DWORD R W 3123 190 X Reserved e USP RX FIFO operation register USP RX FIFO OP 9 0x130 DSP 0x58 This register is different from FIFO of other peripheral operation register and reset bit is at bit O Name Default Description Centrality Communications Inc 326 AT460A BI Developer s Manual Centrality 0 R W FIFO RESET 1 0 Set to 1 to stop the FIFO and reset the FIFO internal status including the relevant interrupt status Setto 0 in normal operation FIFO START Start the read write transfer when this bit is declared lt 31 2 gt 30h0 e USP RX FIFO status register USP FIFO STATUS ARM9 0x134 DSP 0x5a Default Description e FIFO LEVEL 5 hO The byte number of the valid data in the FIFO In case FIFO is full the value of this register is 0 thus user must concatenate FIFO_FULL bit with this value to determine the actual data count in the FIFO 5 R FIFO_FULL FIFO full status the FIFO is full when read out as 1 te EN This bit is concatenated with FIFO_LEVEL to be the actual F
131. gt Centrality 460 Application Processor Developer s Manual Revision 2 4 Aug 2005 2004 2005 Centrality Commnications Inc 2520 Mission College Blvd Suite 103 Santa Clara CA 95054 Centrality Information in this document is provided in connection with Centrality products No license express or implied by estoppels or otherwise to intellectual property rights is granted by this document Except as provided in Centrality s Terms and Conditions of Sale for such products Centrality assumes no liability whatsoever and Centrality disclaims any express or implied warranty relating to sale and or use of Centrality products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Centrality products are not intended for use in medical life saving or life sustaining applications Centrality may make changes to specifications and product descriptions at any time without notice This document is an intermediate draft for comment only and is subject to change without notice Readers should not design products based on this document Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Centrality reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilitie
132. gt RESP lt 31 0 gt R4 OCR Register OCR Register for I O etc R lt 39 8 gt RESP lt 31 0 gt R5 R5b SDIO Response R lt 39 8 gt RESP lt 31 0 gt R6 Published RCA response New published RCA 31 16 etc R lt 39 8 gt RESP lt 31 0 gt SDIO Buffer Data Port Register SD BUF DATA 0x0020 Default Description 31 7 BUF_DATA_PORT 32 h0 The Host Controller Buffer can be accessed R W through this 32 bit Data Port Register SDIO Current State Register SD CUR STATE 0x0024 Bit Default Description 0 CMD_INHABIT CMD 1 b0 If this bit is 0 it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line This bit is set immediately after the SD TRAN CTRL 0x00C is written This bit is cleared when the command response is received Even if the CMD INHABIT DAT is set to 1 Commands using only the CMD line can be issued if this bit is 0 Changing from 1 to 0 generates a CMD END interrupt in the SD INT STATUS register If the HC cannot issue the command because of a command conflict error or because of AUTO CMD12 ERR this bit shall remain 1 and the CMD END is not set Status issuing Auto CMD12 is not read from this bit 1 INHABIT DAT 190 This status bit is generated if either the DAT_LINE_ACTIVE or the RD_TRAN_ACTIVE is set to 1 If this bit is 0 it indicates the HC can issue the next SD command Commands with busy signal belong to CMD_INHIBIT DAT ex R1b
133. it causes a status change and reported to USB system software so that it can take action Function Controller Features USB Specification Revision 2 0 compliant full speed function controller Software configurable as a standard bus powered self powered USB function 8 physical 4 logical user configurable endpoints each of which be programmed terms of endpoint type maximum packet size data buffer association Centrality Communications Inc 186 AT460A BI Developer s Manual Centrality USB On The Go Features Compliant with USB On The Go Supplement Specification Revision 1 0 be implemented in either built in hardware or user software 7 5 2 Pin Description The USB OTG interface is a 2 wire analog serial interface The signals required are described in the table below Table 49 USB OTG Interface Pin Description Pin Name Direction Description a Bi directional Negative X USB ID Bidirectona USB Pad OTG ID Selector X USB PDDM USB DM pull down X USB PDDP USB DP pull down X USB PUDP USB DP pull up 7 5 3 Functional Description 7 5 3 1 PCI to AHB The USB OTG core supports an AHB interface as well as a general bus interface This interface goes on top of the original bus interface and conforms to the AHB protocol as defined in the AMBA specification The USB OTG core contains both an AHB Master and Slave a DMA Controller and Core ETD EP and
134. it then will use the LongDebounceTimer to detect the connection 31 24 R LNGDBNC 8 h64 Long Debounce Timer W This timer is the de bounce time following the detection of a transition on the USB bus This timer is used only after the BConnectShortDebounceWindow has expired or following the transition from the A WAIT VRISE state Centrality Communications Inc 196 AT460A BI Developer s Manual signal is available The HNP protocol allows two methods to detect when Vbus is fully discharged below 0 8V One method is to use a comparator whose output is called B SESS END The other is to discharge the Vbus through a resistor to GND for a certain period of time 1 B SESS END signal is available and it will be used to control the HNP state machine to discharge Vbus 0 No B SESS END signal is available The Vbus Discharge Timer Value will be used to determine the discharge time for Vbus During discharge the Vbus Power Down signal will be asserted which should discharge the Vbus to GND through resistor 50 50 Centrality e USB OTG Interrupt Status Register USBOTG INT STATUS 0x002C Description IDCHANGE ID change Interrupt Indicates the state of the ID pin has changed Software should read the HnpControlStatus Register to determine the current status of the ID pin MASSLVCHG Master Slave Change Interrupt This interrupt is only valid in Hardware HNP Thi
135. lt 15 0 gt X DQ lt 15 0 gt BA lt 1 0 gt lt 12 0 gt DQSH DQSH DQSL DQSL DQMH DQMH Figure 6 DDR Connection in 32 bit Mode Centrality Communications Inc 32 AT460A BI Developer s Manual KE Centrality COMMUNICATIONS 4 3 3 SDRAM Connection Examples MCS lt 1 0 gt MCLK MWE MCAS MRAS MCKE MDQM lt 3 0 gt MA lt 12 0 gt MBA lt 1 0 gt MD lt 31 0 gt 16M 16 SDRAM ICS CLK CKE ICAS IRAS BA lt 1 0 gt A lt 12 0 gt DQ lt 15 0 gt DQMH lt lt gt Figure 7 SDRAM Interface in 16 bit Mode MCS lt 1 0 gt MCLK MWE MCAS MRAS MCKE MDQM lt 3 0 gt MA lt 12 0 gt MBA lt 1 0 gt MD lt 31 0 gt 16M 16 A lt 12 0 gt A lt 12 0 gt lt DQ lt 15 0 x moma DQ lt 15 0 Figure 8 SDRAM Interface in 32 bit Mode Centrality Communications Inc 33 AT460A BI Developer s Manual Centrality 4 3 4 DRAM Controller Regsiters There are 6 registers in System Memory Controller 4 of 6 registers are only used during the memory initialization NOTE After the memory is initialized the register content can not be changed The DRAM needs a series of initialization steps before the DRAM is ready to be accessed One must program the first 5 registers offset 0 0 0 10 in order Then 200 us after programming MEM EXTEND 0x10 register one can program MEM
136. of the A device wants to power down the VBUS 3 W CLRERROR HNP Clear Error State As an A DEVICE to clear the error when the A DEVICE HNP is in A VBUS ERROR state and does not want to release the bus As A B DEVICE to force the transition from B SLAVE to B IDLE HNPSTATE HNP State Represents the current state of the hardware HNP state machine Only valid in hardware HNP 9 R W SWPDDM 1 41 Software Pull Down _______ 0 Reserved 11 170 Software PullUpDP_ 14433 Reserved f Reseved 5 20 R W 170 Charge pump band Gap Enable _______ 23 ___ e Reserved 0 24 R W BHNPEN 70 BHNPEnabed 26 Reswved 71 ____ ______ Reserved USB OTG Register USBOTG TIMER 1 0 0020 Name Default Description 7 m AWAITVRISE 8 h64 A Wait VRise Timer R W This timer is used by an A DEVICE in the A WAIT VRISE state to wait for VBUS to rise Centrality Communications Inc 194 AT460A BI Developer s Manual Centrality to valid levellf VBUS does not reach valid level before a timeout then the A DEVICE knows that the B DEVICE is drawing too much current 15 8 AWAITCONN A Wait Connect Timer R W This timer is used by an A DEVICE in the A WAIT BCON state to wait for the B DEVICE to signal a connection If the B DEVICE does not connect before a timeout then the A DEVICE stops wa
137. of this bit from 1 to 0 occurs when all the block data is read from the buffer A change of this bit from 0 to 1 occurs when all the block data is ready in the buffer and generates the BUFF RD RDY Interrupt AT460A BI Developer s Manual Centrality 1 Read Enable n CARD_INSERTED This bit indicates whether a card has been inserted Changing from 0 to 1 generates a CARD_INSERT interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a CARD_REMOVE Interrupt in the Normal Interrupt Status register The SOFT_RST_ALL in the SD_HOST_CTRL_1 register shall not affect this bit If a Card is removed while its power is on and its clock is oscillating the HC shall clear SD BUS PWR SD EN in the SD HOST register In addition the HD should clear the HC by the SOFT RST ALL The card detect is active regardless of the SD Bus Power 0 Reset or Debouncing or No Card 1 Card Inserted CARD STATE STABL This bit is used for testing If itis O the E CARD DETECT PIN LEVEL is not stable If this bit is set to 1 it means the Card Detect Pin Level is stable The SOFT RST ALL in the SD HOST 1 Register shall not affect this bit 0 Reset of Debouncing 1 No Card or Inserted CARD DETECT PIN _ This bit reflects the inverse value of the SD Card LEVEL Detect pin SDCD 0 No Card present SDCD 1 1 Card present SDCD 0 SRR LINE LEVEL 4 bO Thi
138. of this space can be used For security reasons this memory must be mirrored Thus the maximum size that can be set for the ROM cannot exceed 256MB Also because the mirrored memory is laid out onto two sequential 256MB segments accessing 0x0000 0000 and 0x1000 0000 directly will yield the same result The memory space from 512MB to 1GB 0x2000 0000 0x3FFF FFFF is allocated to two PCMCIA Sockets Each socket takes 256MB of memory e DSP Shared Memory The DSP shared memory takes 128MB address space 0x4800 0000 0x4FFF FFFF Address Space The address between 0x5000 0000 and Ox5FFF FFFF 256MB is assigned to all the internal PCI devices And there is another 256MB space above it 0x6000 0000 0x6FFF FFFF assigned to the PCI ROM Flash e Reserved Space The 256MB address space between 0x7000 0000 0x7FFF FFFF is reserved If the CPU reads from the reserved address space a data abort operation will result Writes to the reserved address space have no effects e Internal Registers Every peripheral device occupies 64K byte space starting from 2GB to 3GB 0x8000 0000 0xBFFF FFFF e System Memory The system memory is between 3GB and 408 0xC000 0000 0xFFFF FFFF But the maximum memory size is 512MB The top 512MB 0 000 0000 is Zero Bank reading from this address range will return zero writing to this address range has no effect The actual memory size is also defined in the boot ROM or by the mem
139. read CurrentConnectStatus This bit reflects the current state of the downstream port A read with this bit SET indicates a device is connected write ClearPortEnable The HCD writes a 1 to this bit to clear the PortEnableStatus bit Writing a 0 has no effect The CurrentConnectStatus is not affected by any write 1 R W PRTENABST 1 bO Port Enable Status read PortEnableStatus When SET this bit indicates whether the port is enabled The Root Hub will clear this bit when an over current condition disconnect event the power is switched off or operational bus error has occurred A change in this bit causes PortEnabledStatusChange to be SET HCD sets this bit by writing SetPortEnable and clears it by writing ClearPortEnable This bit cannot be set when CurrentConnectStatus is cleared This bit is also set if not already at the completion of a port reset when ResetStatusChange is set or port suspend when SuspendStatusChange is set 0 port is disabled 1 port is enabled write SetPortEnable The HCD sets PortEnableStatus by writing 1 Writing a 0 has no effect If CurrentConnectStatus is cleared this write does not set PortEnableStatus but instead sets ConnectStatusChange This informs the driver that it attempted to enable a disconnected port 2 R W PRTSUSPST 1 bO Port Suspend Status read PortSuspendStatus When SET bit indicates the port is suspended or in the resume sequence It is SET by a Centrality
140. read having no effect on the register value Writing 0 to the bit has no effect writing 1 will clear the bit IDE Revision and Class Code Register IDE REV CLASS 0x0008 Bit Default Description 7 0 0 Revision identification number 15 3 R CCP Class Code Programming 31 16 Class Code Class Base Class 15 8 Sub Class 7 0 e IDE Master Latency and Header Type Register IDE MLT HTYPE 0x000C This register sets the minimum period for which the bus will be held assuming there is data to transmit in multiples of 16 PBI clocks zo _____ ____ Reserved 11 8 R Least significant bits of the count value fixed 15 12 4 hO Most significant bits of the count value R W 23 16 R HTYPE Defines format of configuration registers as Type 0 and single function 31 24 e IDE Bus Master Interface Base Address Register IDE BMI 0 0020 Bit Name Default Description 8 Bit Name Default Description 10 ADDR Always 1 Designates address as I O 91 130 Reserved 5 15 4 ADDR 1280 Bus Master Interface Base Address Must less R W than 0x2000 3116 1600 IDE Timing Register IDE TIMING 0x0040 Bit Default Description 0 R W DO FT BS 1 bO Drive 0 Fast Timing Bank Select When set to 0 disabled uses 16 bit compatible timings to the Data
141. read only Default Description AYSNC TIMEOUT 16 hff This parameter specifies the TIMEOUT bit number for NUM the receive operation Since the last bit received if there is no more data is receieved for TIMEOUT bit number time the rx timeout interrupt will be triggered 21 16 ASYNC DIV2 The parameter is used to cooperate with the USP DIVISOR in the USP MODE2 register to generate the right baud rate for async mode when ioclk is low frequency 31 1 31 h0 Reserved 8 8 5 2 USP TX FIFO register NOTE The data flow of TX FIFO is always from ARM9 DSP DMA to USP e USP TX DMA MODE register USP TX DMA IO CTRL 9 0x100 DSP 0x40 Bit Default Description 1130 reserved lt 31 6 gt 26 h0 Reserved e USP TX I O length register USP TX IO LEN 9 0x104 DSP 0x42 0x43 Bit Default Description lt 31 0 gt DATA_LEN 32 The byte number of a DMA or I O transfer If R W set to zero the I O or DMA transfer works continuously until it is stopped e USP TX FIFO control register USP TX FIFO CTRL ARM9 0x108 DSP 0x44 it Name Default Description B lt 1 0 gt FIFO_WIDTH lt 1 0 gt 290 Data width of FIFO 0 for byte 1 for word and R W 2 for DWORD R W data in the FIFO reaches the threshold lt 6 2 gt FIFO_THD lt 4 0 gt 5 hO A threshold in byte to trigger an interrupt An interrupt is triggered when the count of lt 317 gt _____ 2510
142. register bit 1 register bits 1 and 0 Inactive Inactive high high Yes Activated per Activated per MiscControl1 Power Control register bit1 register bits 1 and 0 Table 60 M6730 Power Control Register 2 Centrality Communications Inc 229 AT460A BI Developer s Manual Centrality nrst Level Both 1 Power Control Register M6730 Output Signals to Socket and ncd2 are active Vcc Power Card Enable low bit 4 bit 7 XK High Impedance O No High Impedance High 10 0 High Impedance High Impedance igh Yes High Impedance e M6730 Interrupt and General Control Register 6730 Index 0x03 Name Default Description 3 0 m IRQ LEVEL 4 These bits determine which IRQ will occur when the card causes an interrupt through the signal in the PC card socket 4 b0000 IRQ disabled 4 b0001 Reserved 4 b0010 Reserved 4 b0011 IRQ3 ninta 4 b0100 IRQA nintb 4 b0101 IRQ5 nintc 4720110 Reserved 4 b0111 IRQ7 nintd 4 b1000 Reserved 4 b1001 IRQ9 4 b1010 IRQ10 4 b1011 IRQ11 4 b1100 IRQ12 4 b1101 Reserved 4 b1110 IRO14 4 b1111 IRQ15 4 R W MGT INT EN Management Interrupt Enable 1 b0 Management IRQ specifies management interrupt bits 1 b1 Reserved This bit was created to determine how management interrupts occur on the ISA based systems It is included for the sof
143. register contains the most significant nibble of the address that specifies where in the memory space the corresponding memory map will begin Memory accesses that are equal or above this address and equal or below the corresponding System Memory Map End Address will be mapped into the memory space of the corresponding PC card 5 4 NW 20 Scratch pad bits 6 RW __ 150 Compatiiit bit 7 R W WIN DATA SIZE 1 bO Window Data Size This bit determines the data path size to the PC card M6730 System Memory Map 0 4 End Address Low Register M6730 SM 4 EAL Index 0x12 0x1A 0x22 0x2A 0x32 There are five separate System Memory Map End Address Low registers each with identical fields Bit Name Default Description 7 0 R W EA lt 19 12 gt 8 hO End Address lt 19 12 gt This register contains the least significant byte of the address that specifies where in the memory space the corresponding memory map Centrality Communications Inc 238 AT460A BI Developer s Manual Centrality will end Memory accesses that equal or below this address and equal or above the corresponding System Memory Map Start Address will be mapped into the memory space of the corresponding PC card M6730 System Memory Map 0 4 End Address High Register M6730 SM MAPO0 4 Index 0x13 0x1B 0x23 0x2B 0x33 There are five separate System Memory Map End Address High registers each w
144. second channel image data dual scan mode from SDRAM 1 Little Endian 0 Big Endian mode 1 OSD2_DW_BLE Big Little Endian selection of byte for OSD2 R W image data the second channel image data in dual scan mode from SDRAM 1 Little Endian 0 Big Endian 1 R W byte data only for 4 bit pixel 2 bit pixel 1 Little Endian 0 Big Endian 3116 1160 13 12 SCN_16BPP_FORMAT 2000 Data format for 16 bit per pixel mode R W 00 6 5 5 16 bit i e 6 bit R 5 bit G 5 bit B 01 5 6 5 16 bit 10 5 5 6 16 bit These two bits are only valid in 16 bit per pixel R 10 11 SCN_BYTE_BLE Big Little Endian selection in the screen image R W byte data only for 4 bit pixel 2 bit pixel 1 Little Endian 0 Big Endian 4 5 OSD2_BYTE_BLE Big Little Endian selection in the OSD2 image 6 2 4 4 FRC rate control Registers These registers are used to set the two LFSRs LINE_LFSR and PIX_LFSR The two LFSRs are used to reduce the flickering generated by FRC operation e Line Linear Feedback Shift register LCD LINE LFSR 0x68 t Name Default Description LFSR_SEED 910 Initial value of the line LFSR LFSR advanced by R W HSYNC 8 0 R Bi 17 9 LFSR VAL 9 hO Algorithm used for the LFSR If bit 1 then that bit of W the shift register is used in the sum For instance for the algorithm g x x x 1 program the algorithm value to 100001000 19 18 ARALLEL FORMAT 2 hO The foll
145. sum of the lower 5 or 6 bits of the two LFSRs plus the frame count gives the index to select one bit from the 32 bit or 64 bit sequence as one pixel ON OFF value in a frame The initial values and the algorithms of the two LFSR are changeable to obtain the best quality 6 2 3 4 Palette RAMs The palette RAMs are written or read directly by RISC Interface to access the specified address Three RAMs 256x18bit 16x18bit and 64x32bit are used for the palettes and the FRC sequence tables For the 256x1 8bit palette RAM when as color palette each address contains RGB value for a color that has an index corresponding to the address The color component is 6 bits each specifying the 6 MSB of an 8 bit value For the 2 bit pixel lookup the bottom 4 entries are used For the 4 bit pixel lookup the bottom 16 entries are used For the 8 bit pixel lookup all the 256 entries are used While for passive monochrome mode this palette is used for dithering of frame rate control As the dithering sequence for one gray color is 32 bit the bottom 32 entries are used for 16 grey levels For 4bit pixel mode bits lt 15 0 gt of entry 0 and entry 16 combine as 32 bits for one gray color and bits lt 15 0 gt of entry 1 and entry 17 as another gray color and so And for 2bit pixel mode only entry 0 3 and entry 16 19 are used The 16x18bit palette RAM is always a color palette and each address contains RGB value for a color that has an index corresponding
146. that changes made within Reset Mode are only put into effect on the return to Operating Mode 335 AT460A BI Developer s Manual Centrality 318 240 e Receive Error Counter Register CANBUSn_RXERR 0 0038 Bit Default 7 0 8 hO R W Description The Receive Error Counter Register records the current value of the Receive Error Counter This counter is incremented when errors are experienced in the Receive bit stream and decremented when messages are received without error in line with the rules given in the CAN 2 0 specification Together with the associated Transmit Error Counter it provides an indication of the quality of transmission being experienced on the CAN bus Two levels of the counter trigger specific events When the counter reaches the level set in the Error Warning Limit register an Error Warning Interrupt is generated if enabled unless this has previously been triggered by the Transmit Error Counter When the counter goes over 127 the device is put into Error Passive state in accordance with the CAN 2 0 specification unless previously triggered by the Transmit Error Counter and an Active error is sent An Error Passive Interrupt is also generated if enabled After a hardware reset or when a Bus Off event occurs the counter is automatically set to 0 The register is read only in Operating Mode but may be written in Reset Mode You should note however that
147. the previous command error 0 No Error 1 Error 0 0 Don t care 1 Response not received within 64 SDCLK cycles OO Response Received Table 45 Relation between Command CRC Error and Command Timeout Error Command CRC Error Command Timeout Error Kinds of Error Po NO Error 2 Response Timeout Error ______ Response 2 CMD Line Conflict e 5010 Interrupt Status Enable Register SD INT STATUS 0x0034 Bit Name Default Description 1 Enabled 1 Enabled 1 Enabled pu INT STA T bO bO bO bO 4 R W BUFF WT RDY INT STA pe 0 Masked 1 Enabled 5 R W BUFF RD RDY INT STA EN 0 Masked 1 Enabled Centrality Communications Inc 180 460 Developer s Manual Centrality 6 R W CARD INSERT INT STA 1 bO s 1 Enabled 1 Enabled Reserved R W 1 Enabled R W 1 Enabled 18 CMD ENDBIT ERR INT STA EN 0 Masked R W 1 Enabled R W 1 Enabled R W 1 Enabled 21 DAT CRC ERR INT STA EN 0 Masked R W 1 Enabled R W 1 Enabled 23 CURRENT LIM ERR INT STA EN 1 bO 0 Masked R W 1 Enabled 24 AUTO CMD12 ERR INT STA EN 1 bO 0 Masked R W 1 Enabled 31 28 VEND SPEC ERR INT STA 0 Masked R W 1 Enabled NOTE Setting to 1 enables Interrupt Status The HC may sample the card Interrupt signal during interrupt perio
148. the Descriptor Field of the Transmit Buffer is shown below first for SFF then for EFF Table 86 Descriptor Field of Transmit Buffer Transmit Frame SFF CAN Address BIT7 6 5 BIT4 BIT3 BIT2 BIT1 BITO 0x0040 0x0048 Transmit Frame EFF CAN Address BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO OxO04C 10 12 1011 0 10 10 9 108 10 7 06 105 0 0050 104 10 3 102 D1 Xo 1 Don t care but recommend 0 to be compatible with Receive Buffer in case the Self Reception or the Self Test option is used 2 Don t care but recommend matching the RTR bit used in the Receive Buffer in case the Self Reception or the Self Test option is used Frame Format FF The FF bit selects the type of frame format to be transmitted 1 selects Extended Frame Format EFF 0 selects Standard Frame Format SFF Remote Transmission Request RTR The RTR bit is used to identify the frame as either a remote frame or a data frame as defined in the CAN protocol 1 indicates a remote frame i e a request for data from another node 0 indicates a data frame Data Length Code DLC The DLC 3 0 bits are used to specify the number of data bytes included in message being sent Centrality Communications Inc 338 AT460A BI Developer s Manual Centrality maximum number of data bytes that can be included frame is eight so
149. the FIFO reach the threshold 314 7 12880 Flash Interrupt Status Register SM INT STATUS 0x24 When an interrupt occur the corresponding bit will be set to 1 even the interrupt bit is not enable automatically Write a 1 b1 will clear the interrupt bit Bit Name Default Description 0 Reserved 7 address to smartmedia is done is done RRS in the FIFO reach the threshold 314 ___ 80 Reserved Flash Control Register SM CTRL 0x28 This register is used for power on auto read in WINCE boot After reset this register is set to 1 b1 this enables RISC to directly read NAND Flash acting like ROM When using FIFO to read write datam this bit must be set 1 bO Bit Name Default Description 0 R W DIRECT_READ Set 1 will enable I O directly read Flash R W DATA_WIDTH Set 1 will enable 16 bit NAND Flash Set 0 will enable 8 bit NAND Flash Reserved 2 Lm IE Set 0 will disable large page support __ Set 0 will request rom pin Er NOTE default values of bit 1 3 and 4 are determined by the external pull up down resistor Please refer to the section of Mode Configuration Pins Centrality Communications Inc 266 AT460A BI Developer s Manual Centrality Flash ECC Setting Register SM ECC SET 0x2C Bit Name Default Description 1 R W HW ECC Set 1 will enable hardware ECC
150. the OSD alpha value will be zero For 2bpp data format keep this bit as zero but the MIX RATIO of OSD Palette registers will be used as the valid alpha value 157 90 Reserved 0 OSD2_ALPHA_VAL 19 16 4 hO 4 bit planar alpha value to blend all pixels on OSD2 R W layer to SCN layer or SCN OSD layer This value is used or not wil be selected by bit 6 of LCD_OSD2ALPHA register 21 20 OSD2_BPP OSD2_ALPHA_SEL 0 or 4 bit alpha 4 bit Red 4 bit Green 4 bit Blue when OSD2 ALPHA SEL 1 OSD2 ALPHA SEL 1 Select the valid alpha value as the 4 bit alpha data MT from the 8bpp or 16bpp image data only valid for 8bpp or 16bpp data format 0 Select the OSD2 ALPHA as the valid alpha value when the data format is 4bpp 8bpp or 16bpp Remark when OSD2 BPP is 4bpp this bit must be zero which is only the OSD2 ALPHA VAL will be used as the alpha value and if not the OSD2 alpha value will be zero For 2bpp data format keep this bit as zero but the MIX RATIO of OSD Palette registers will be used as the valid alpha value 31 23 __ HO Reserved 7 e color key big RGB value LCD SCNCKEYB 0 8 OSD2 data format for alpha blending 00 2bit pixel 2 bit index color 01 4bit pixel 4 bit index color 10 8bit pixel 8 bit index color when OSD2_ALPHA_SEL or 4 bit alpha 4 bit index color when OSD2_ALPHA_SEL 1 11 16bit pixel 16 bit RGB 5 6 5 color when 1
151. the corresponding bit in the GPIO Pin Data output bit OUT and cleared by writing a 0 to the same register The GPIO Pin Data output register can be written regardless of its input or output configuration If a pin is configured as an input the programmed output state occurs when the pin is reconfigured to be an output The user can validate each GPIO pin s state by reading the GPIO Pin data input bit DATA_IN This register can be read anytime to confirm the state of a pin The GPIO pull high low bit PULL is used to configure the GPIO input pin to pull it high or pull low Use the GPIO Open Drain bit OD to set the GPIO into Open Drain mode The GPIO supports two types of interrupts edge or level triggered The user should set the GPIO interrupt type bit INT_TYPE to choose Uses the GPIO interrupt enable bit INT_EN to enable the interrupt Use the GPIO high level trigger bit INT_HT to enable the high level or rising edge interrupt as defined in GPIO_INT_TYPE Uses the GPIO low level trigger bit INT_LT to enable the low level or falling edge interrupt as defined in GPIO_INT_TYPE Use the GPIO interrupt status bit INT_STATUS to read interrupt happened on the GPIO For each group GPIO there are 31 or 32 control registers for each GPIO pin 3 4 registers to control PAD MUX DSP enable read interrupt status and sleep mode The registers are mapped as the following table Table 25 GPIO Register Mapping RISC DSP Address Addr
152. the other DMA transfer is implemented via the data transfer between the external memory and FIFO s Centrality Communications Inc 253 AT460A BI Developer s Manual Centrality Each peripheral has its own FIFO size of FIFO is peripheral dependent Lower bandwidth peripherals do not need large FIFO size The FIFO must provide status flags and interrupts to the host RISC or DSP if there is an underflow or overflow The fullness of the FIFO is determined by the difference of the two pointers Since most of the FIFOs in this chip are bi directional one must be very careful with both FIFO overflow and underflow in both situations Make sure that the request levels to the SDRAM controller are set properly so that it can start stop in time The FIFO will interface with both a data producing consuming peripheral and the DMA controller A FIFO sends a 2 bit request level to the DMA controller If that FIFO is serviced the DMA controller will send it a data valid signal On the following cycle the FIFO will either write the 32 bit data onto the data bus if it s writing to SDRAM or it will read the 32 bit data from the data bus if it s reading from SDRAM The request level is determined by two sets of registers one for reading and one for writing setting three checkpoints stop low high that will trigger different request levels Table 64 FIFO Requests Level FIFO Requests FIFO write to external memory FIFO read fr
153. to 1 the HC shall issue CMD12 automatically when last block Centrality Communications Inc 165 460 Developer s Manual Centrality transfer is completed The HD shall not set this bit to issue commands that do not require CMD12 to stop data transfer 0 Disable 1 a oss Reseved 4 SRE EE TRAN_DIR_SEL This bit defines the direction of DAT line data transfers 0 Write Host to Card 1 Read Card to Host 5 R W MULT BLK SEL This bit enables multiple block DAT line data transfers 0 Single Block 1 Multiple Block 2 ae T RES_TYPE_SEL Response Type Select R W 00 No Response 01 Response length 136 10 Response length 48 11 Response length 48 check busy after response 15 E CRC CHK EN 1 bO If this bit is set to 1 the HC shall check the CRC field in the response If an error is detected it is reported as a Command CRC Error If this bit is set to 0 the field is not checked 0 Disable 1 Enable 20 CMD IND CHK EN If this bit is set to 1 the HC shall check the index field R W in the response to see if it has the same value as the command index If it is not itis reported as a Command Index Error If this bit is set to 0 the Index field is not checked 0 Disable 1 Enable This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line If is set to 0 for the follo
154. transmitting operation After enabling them RISC DSP can monitor these interrupts when transmitting If only one data is need to be transmitted at one time the TX DONE interrupt is enough for it and if several data are transmitted at one time the TXFIFO SERVE interrupt or TXFIFO EMPTY interrupt maybe useful to improve the Centrality Communications Inc 315 AT460A BI Developer s Manual Centrality efficiency If the TXFIFO_EMPTY interrupt happens software can write several new data into the TX_FIFO There are also four interrupt for the receive operation RX_DONE RXFIFO_SERVE RXFIFO_FULL RX_OFLOW The receiving operation is similar to the transmitting After the interrupt happens RISC DSP can read the data out from the RX_FIFO RXFIFO_SERVE interrupt and RXFIFO_FULL interrupt are useful for read several data from the RX_FIFO at one time e O mode without Interrupt This mode is suitable for the less data cases with time insensitive The RISC DSP can poll the USP_TXFIFO_STATUS and USP_RXFIFO_STATUS register before transmitting or receiving operation If the TX_FIFO is not full or RX_FIFO is not empty RISC DSP can write or read new data from the TX_FIFO or RX_FIFO e DMA mode This mode is suitable for many data cases If the transmitting receiving FIFO is set to DMA mode RISC DSP cannot access them in the DMA mode For transmitting first RISC DSP sets the number of the data to be transmitted in the USP_TX_DMA_I
155. 0 10 IDE Configuration Register Mapping sese 10 PIO Timing Programming eese nennen E eterne nnne ens 10 IDE Bus Master Control Register Mapping seen 10 Centrality Communications Inc 8 AT460A BI Developer s Manual LS Centrality COMMUNICATIONS Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Table 89 Table 90 Table 91 Table 92 Table 93 Table 95 Table 96 Table 97 Table 98 Table 99 Table 100 Table 101 Table 102 Table 103 Table 104 Table 105 Table 106 Table 107 Table 108 Table 109 Table 110 Table 111 IDE Device Port Map uide e eee cte ect te He dee edu aed 10 PCMCIA Interface Signal 10 PCMCIA Configuration Register POMCIA CONFIG 0x57C00000 10 M6730 Device Control Register 10 M6730 Power Control Register 0 eene nennen 10 M6730 Power Control Register 2 eene 10 Extended Indexed Registers 10 Memory Bus
156. 0 5 01 4 10 3 11 2 RW IDE Decode Enabled Command block at 01F0 7h R W and Control block at O3F6h 3116 2 2 2 Post write read prefetch allows buffering of to sixteen double words 16 x 32 bit Posted writes have priority over all reads All posted writes must have finished before any read may take place Posted writes and prefetched reads share the same buffers Primary and Secondary IDE channels have separate buffers Post write This only applies to transfers to the Data Port The Peripheral Bus cycle is terminated at the point that data is written to the post write buffer The data is then transferred to the IDE device using IDE timing If a subsequent write or read occurs at the Peripheral Bus Interface it will be forced to wait for the previously posted write to finish Read prefetch This only applies to transfers from the Data Port The first Data Port read starts the read prefetch sequence where subsequent bytes are read automatically and buffered at the Peripheral Bus Interface to minimize the read latency Any other read or write access to the IDE device automatically terminates the read prefetch and discards any data already fetched The following table shows the programming required for each of the PIO modes The cycle times given are based on a 33MHz PCI clock ISP and RCT values are given as a number of clock cycles Table 53 PIO Timing Programming 8 bit Compatible 0 Compatible
157. 0 R W UART_DTR 1 bO Write this bit will change the status of DTR pin of UART 1 b0 set to high level Centrality Communications Inc 306 AT460A BI Developer s Manual Centrality 161 set DTR to low level 1 ew UART RTS Write this bit will change the status of RTS pin of UART set RTS to high level 1 b1 set RTS to low level EO 1 bO 1 b0 no loop back 161 the is connected to not external pin but TXD internally and the transmit data is loop back to receive pin 315 ____ 1270 j Reseved e UART Modem Status Register UART MODEM STATUS RISC 0x48 DSP 0x24 vium Description 0 R W DELTA CTS 1 This bit monitors the status change of CTS Both the rising edge and falling edge of CTS will set this bit 1 Any read operation to UAHT MODEM STATUS will clear this bit 1 R W DELTA DSR This bit monitors the status change of DSR pin Both the rising edge and falling edge of DSR will set this bit 1 Any read operation to UAHT MODEM STATUS will clear this bit 2 R W DELTA RI 1 bO This bit monitors the status change of RI pin Only the rising edge of RI will set this bit 1 Any read operation to UART _ MODEM STATUS will clear this bit 3 R W DELTA BN bit monitors the status change of DCD pin Both the rising and falling edge of DCD will set this bit 1 Any read operation to UAHT MODEM STATUS will clear this bit 4 R
158. 0 Reset Scheme of Each Module Hardware System Block Module reset reset Sleep reset reset RISC Core Pes _ ves ____ RISC Interface ves No Interrupt Controller Mes Yes Power Manager Ves No 1 System reset has two sources first invoked by programming SYS_RST bit of RESET_SWR register second invoked by watchdog timer 2 Block reset is invoked by programming bit lt 23 0 gt of RESET SWR register Centrality Communications Inc 71 460 Developer s Manual Centrality ue e Nue ENG Jo pmo Resource Sharing Controller System Arbiter 5 6 7 Power On Reset The power on reset needs to hold long enough that the SoC can be initialized correctly And the power on reset should not be disserted until the 12 MHz oscillator is stable Centrality Communications Inc 72 AT460A BI Developer s Manual Centrality iS DM Iro Seat eO Ade ETC cruciat Sage SAS mmt RTL leet eh le 5 a E a 205 S 7 ue des dE 220 21 Zo x e e gt d lt amp i io I l 2 5 N a tc a 9 a LL a A a a ag a amp a a gt ag H oc gt x gt gt gt gt gt gt gt gt gt 5 4 8 t6 gt Os t7 gt 0s t3250ms 14 gt 3 t5 gt 2ms 2 is
159. 0x800 to offset 0x810 Table 63 Bridge Register Mappin RISC Address Register Description lt 11 0 gt 0x0800 IOBG INT CTRL O Bridge interrupt controller 0x0804 IOBG FLUSH O Bridge flush controller 1 0x080C IOBG ARB STATUS O Bridge arbiter status 0x0810 IOBG ARB CLKRATIO O Bridge clock ratio Others ____ ___________ Reserved 0 0808 OBG_INT STATUS I O Bridge interrupt status Bridge interrupt controller IOBG_INT_CTRL 0x0800 The Interrupt from I O Bridge is to monitor the abnormal transaction on I O Memory bus If one Master gets grant to access the memory bus after that it perform no operation on the bus The memory is blocked by this master The I O Bridge will issue an interrupt to inform this kind of situation Bit Default Description O R W INT EN IO bridge Interrupt enable 15 8 TIME OUT 8 hFF Timeout value TIME OUT 32 31 IO CLK cycles If the value is 0 then the actual time out value is 31 After 31 I O clock cycles the I O Bridge give grant signal if the master still has no operation the arbiter will assert an interrupt to the RISC 31 16 __ 16no Reserved Bridge flush register IOBG FLUSH 0x0804 Bit Default Description 0 R W FLUSH 1 bO IO bridge flush bit I O Bridge will clear this register when I O Bridge is in idle or a transaction in Bridge is over In order to determine the current
160. 1 lt 5 0 gt 8h0 The path delay of will be R W 1 DELAY 0 2ns 3130 Reserved Centrality Communications Inc 57 AT460A BI Developer s Manual LS Centrality COMMUNICATIONS 5 4 Interrupt Controller 5 4 1 Overview In the Atlas II processor both the RISC Core and the DSP Core can accept external interrupts In addition the RISC and DSP can interrupt them each other The RISC Core has two external interrupt inputs FIQ and IRQ FIQ allows for fast interrupt processing by providing five additional dedicated general purpose registers The DSP Core has up to six external interrupts pins IRQ2n IRQ1n IRQOn IRQL1n IRQLOn and IRQEn In Atlas II only IRQL1n and IRQLOn are used for all interrupt sources The interrupt hierarchy of the Atlas Il is a two level structure The first level is responsible for the masking unmasking of all enabled interrupts and sends the interrupt to the processor the second level is implemented in the source device the device generates the first level interrupt bit The second level interrupt status register gives additional information about the interrupt and is used inside the service routine In general multiple second level interrupts are OR ed to produce a first level interrupt bit The enabling of interrupts is performed inside the source device The following figure shows the interrupt controller block RISC part diagram For the DSP part it is
161. 1 alternate VYSNC signal alt vsync1 The alt vsync1 register must be set to a valid value Note VSYNC signals with different timing may be required for different display modes such as the STN modes This bit is not used when the ALT VSYNC VALID in LCD ALT VSYNC is set with 1 Please refer to Figure 10 for more details Centrality Remark This bit can control the latency of CS signal for look up table as the output delay of RAM for palette is rather large 1 When OSC lt 9 0 gt 1 assert this bit 0 Generally configuration 31 14 e First alternate HSYNC control register LCD ALT HSYNC 0x48 Description End value Define the pixel count after which the alternate RW signal will be de asserted Start value Define the pixel count after which the alternate signal will be asserted ROMA 1 7 Signal is valid Use start and end values to define phase 0 Signal is not valid 31 23 Reserved e First alternate VSYNC control register LCD ALT VSYNC 0x4C Default Description START_PIXEL 17 0 Start pixel value Define the location line pixel at which the alternate signal will be asserted The ALT VSYNC pulse width is also decided by LCD VSYNC WIDTH register 21 11 START LINE 110 Start line value R W Define the location line pixel at which the alternate signal will be asserted The ALT_VSYNC1 pulse width is also decided by LCD_VSYNC_WIDTH r
162. 10 RTC Register 10 PWR MGR Register Mapping 2 ccecesceceeeeeceeeeeceeeeeaeeeesenaeeeeseaeeeseaeeeeseaeeeeeseeeeeenneees 10 Interrupt Controller Register Mapping nennen 10 OS Timer Register 1 10 Reset Scheme of Each enne nnn 10 Reset Controller Register 10 DMA Channels 10 011 esee eene 10 RSC Register Mapping es 1 2 ier Lee tan inen dp th dpt eate en abe e edes 10 GPIO Pin MOK ice ott on t OUR ER ER EU RE tene editt ede 10 GPIO Register 10 PWM Interface Register 10 Atlas II LCD Controller Pin 00400 10 Atlas II LCD Controller Data Pins for passive displays 10 LCD Controller Regsiter Map 10 BitBLT Engine Regsiter Mapping emere 10 PCI Device Registers 10 PCI Bridge RISC IO Register 10 PCI Bridge DSP IO Register Mapping cccsecceeseeeeeeeceeeeceeeeeaeeeeaeeeeaeeeeaeeee
163. 15 Supported Clock Ratios in Atlas 2 unit MHz PLL CPU DSP System Memory IO PWR 11 1 Bus ONFIG TIO 0x9006 0028 0x9006 0040 32bit 1 2 32bit 16bit 0 The following constraints must be followed when programming the clock ratios e The frequency of DSPCLK can only be 1X or 2X of SYSCLK e The frequency of IOCLK can only be 1X 1 2X or 1 4X of SYSCLK e The maximum clock output of PLL1 should not exceed 600MHz in best case 500MHz in worst case e The maximum memory clock frequency should not exceed 138MHz in SDRAM mode worst case e The maximum memory clock frequency should not exceed 200MHz in DDR 32bit mode worst case e The maximum memory clock frequency should not exceed 138MHz in DDR 16bit mode worst case Centrality Communications Inc 46 460 Developer s Manual Centrality e After the PWR_CLK_RATIO register is changed software shall not access DSP or IO modules in Tready time 0 1ms NOTE As you may notice some configurations can be achieved by multiple approaches such as the two configurations highlighted in gray But to get better clock duty cycle we suggest using the configuration with higher PLL VCO frequency NOTE All the other clock configurations not shown in the above table are not guaranteed to be working 5 2 7 Clock Switching The clock configurations can be changed on the fly According to the clock c
164. 160 1 Color key function for OSD is valid R W 0 Color key function for OSD is invalid 21 different data formats For 16 bit data format the 18bit CKEYB or CKEYS are calculated by expanding Red Green or Blue to 6bits and set the expanded LSB to 1 bO 31 22 e OSD color key small RGB value LCD OSDCKEYS 0x98 OSD_CKEY_SEL 1 b0 1 8 bit index color mode In this mode only bit 7 0 of R W OSD_CKEYB and OSD_CKEYS are valid for the 8 bit index 0 18bit 6 6 6 color mode This be used for 2 bit index 4 bit index 8 bit index 16 bit 5 6 5 5 5 6 6 5 5 and so on This mode is flexible but needs to calculate OSD_CKEYB and OSD_CKEYS values according to Centrality Communications Inc 121 460 5 LZ Bit Name Default Description 5 1880 Smaller value of color key for OSD channel display 31 18 __ 0502 color key big RGB value LCD_OSD2CKEYB 0x9C zd Default Description CKEYB 18 h0 Bigger value of color key for OSD2 channel display 19 18 250 20 OSD2 CKEY 1 Color key function for OSD2 is valid R W 0 Color key function for OSD2 is invalid 21 OSD2 CKEY SEL 1 bO 1 8 bit index color mode In this mode only bit 7 0 of R W OSD2 CKEYB and OSD2 CKEYS are valid for the 8 bit index 0 18bit 6 6 6 color mode This can be used for 2 bit index 4 b
165. 176_ 0 544 CTRLi7 GPIO control for GPIO177 0x548 GPIO5 CTRL18 GPIO control for 1 8 0x54C GPIO5_CTRL19 GPIO control for GPIO179 0x550 GPIO5 CTRL20 GPIO control for GPIO180 0x554 GPIO5 CTRL21 GPIO control for GPIO181 0x558 GPIO5 CTRL22 GPIO control for 0 182 0x55C_ GPIO5_CTRL23 GPIO control for 018 0x560 GPIO5_CTRL24 GPIO control for GPIO184 0x564 ________ GPIO5_CTRL25 GPIO control for GPIO185 0x568 _______ GPIO5_CTRL26 GPIO control for GPIO186 _____ o6c ____ GPIO5 CTRL27 GPIO control for 0187 0x570 GPIO5_CTRL28 GPIO control for GPIO188 0x574 GPIO5_CTRL29 GPIO control for GPIO189 0x578 GPIO5 CTRL30 GPIO control for GPIO190 0x57C GPIO5_CTRL31 GPIO control for GPIO191 0x580 e f Reserved _______ ____ _______ rou pas enable ______ 0 588 5 SW GPIO group5 sleep wakeup enable 0x58C paso feos sa GPIO5 INT STATUS GPIO group5 interrupt status for RISC ones J Reserved GPIO control register GPIO_CTRLx The GPIO CTRLx is the register to control one GPIO pin There are a total of 192 GPIO control registers But there are only 188 GPIO pins available So there are 4 GPIO control registers reserved user should not acess them and they are GPIO1_CTRL31 GPIO2 CTRL1
166. 3 This register is used to control these different modes Name Default Description SSTL_S lt 1 0 gt 27911 2 b00 LVCMOS 1 8 2 b01 SSTL 2 5V 2 b10 LVCMOS 2 5V 2 b11 LVCMOS 3 3V default 2 R W SSTL PD This bit is only valid in SSTL 2 5V mode 1 b1 Memory pad is power down 1 60 Memory is power up default 313 290 Reserved Power Manager Delay Control Register PWR DELAY 0 0 004 Default Description Bit 5 0 HCLKEN_DELAY lt 5 0 gt 816 The path delay of HCLKEN will be R W HCLKEN_DELAY 0 2ns Only bit lt 4 0 gt is valid and it s the same for all the followings a i Reserved ft MCKO_DELAY lt 5 0 gt The path delay of MCK_O will be MCK_O_DELAY 0 2ns 15 1 Reserved MCK2X_O_DELAY lt 5 0 gt 8 h3 The path delay of MCK2X O will be O_DELAY 0 2ns rr 1 i is selected from internal 3125 e Power Manager Delay Control Register DELAY 1 0 0050 Name Default Description 5 m 0 DELAY 5 0 8 hf path delay of _0 will be CKO_0_DELAY 0 2ns 76 Reserved __ 2 13 8 CKO_1_DELAY lt 5 0 gt 8 hf The path delay of CKO 1 will be R W CKO 1 DELAY 0 2ns 1514 Reserved 21 16 EXTCLK_DELAY lt 5 0 gt 8 hf The path delay of EXTCLK will be R W EXTCLK DELAY 0 2ns 2322 Reserved 29 24
167. 414 ___ __ 7 5 GPlOcontolforGPIO133 0x418 ___ 7 ____ GPIO control 4______ 1 ____ 7 GPIO control for GPIO135 ______ 0x420 GPIO control for GPIO136 0x424 GPIO4_CTRL9 GPIOcontrolforGPIO137_ 0x428 GPIO4 CTRL10 GPIO control for GPIO138 _____ 0x42C_ GPIO4_CTRL11 GPIO control for GPIO139 __ 0x430 GPlIO4 GPIO control for GPIO140 0x434 GPIO4CTRLI3 ____ GPIO control for GPIO141 0x438 GPIO4_CTRL14 GPIO control for 142 _____ ______ GPIO4_CTRL15 GPIO control for GPIO143 0x440 GPIO4 CTRL16 GPIO control for GPIO144 0x444 GPIO4_CTRL17 GPIO control for GPIO145 0x448 ______ GPIO4_CTRL18 GPIO control for GPIO146 0x44C X 9 GPIO control for GPIO147 _____ 0x450 GPIO4_CTRL20 GPIO control for GPIO148 0x454 GPIO4_CTRL21 GPIO control for GPIO149 0x458 _______ G PIO4 CTRL22 GPIO control for GPIO150 0x45C _______ GPIO4_CTRL23 GPIO control for GPIO151 0x460 GPIO4_CTRL24 GPlOcontolforGPIO152 0x464 PIO4 CTRL25 GPIO control for GPIO153 0x468 GPIO4_CTRL26 GPIO control for GPIO154 0x46C GPIO4 CTRL27 GPIO control for GPIO155 0x470 GPIO4 CTRD26 GPIO control for GPIO156
168. 460A BI provides higher performance lower power consumption and lower cost The following diagram shows the block diagram of AT460A BI The different colors show the difference between Atlas I and Atlas I CPU ARM926EJ IO Bridge Internal PCI PCMCIA DMA Controller Minor Maior New EXT Port Figure 1 Atlas II Block Diagram Features of Atlas II Application Processor e 276MHz 32 bit RISC ARM926EJ 16KB o 16KB D Cache o Jazelle Java Acceleration 9 Embedded Trace Module e 200MHz 16 bit DSP enhanced with hardware acceleration Centrality Communications Inc 11 AT460A BI Developer s Manual Centrality COMMUNICATIONS 5Kx24bit Program Memory 10Kx16bit Data memory e 200 2 DDR or 138MHz SDRAM interface 3 3V SDRAM 2 5V DDR Enhanced 16 Channel GPS baseband e Color TFT LCD panel interface 8 16 bit NAND Flash interface e CMOS sensor interface e USB 2 0 full speed interface ATA interface e 5010 interface PCMCIA CF card interface 2CANBus ports e 5 Universal Serial Ports and 3 UARTs e PWM interface 605 timers e 190 programmable GPIO e Advanced power management o Normal mode o Idle mode o Sleep mode e Internal 1GHz and 400MHz PLL e Internal 12MHz and 32 768KHz oscillator e TSMC 0 13G process with Dual Vt e 324 ball 19x19mm lead free uBGA package 1 2 Example System Following figure shows how th
169. 47D01000 The following table shows the Configuration Register Mapping The address of the IDE device Data Command register is 0x47D001F0 47D001F7 The address of the IDE device Control Status register is Ox47D003F6 7 6 3 1 IDE Configuratoin Registers Table 52 IDE Configuration Register Mapping RISC Addr lt 7 0 gt Register Description 0x0010 0x001C Reserved 0 0020 DE 5 Bus Master Interface Base Address register 0x0024 0x003C Sti Reserved _0 0048 f Reserved f Reserved S Others Reserved S e IDE Vendor and Device ID Register IDE VEN DEV ID 0x0000 Bit Name Default Description 15 0 VEN ID Manufacturer s identification number 31 16 DEV ID Device identification number IDE Command and Status Register IDE CMD STATUS 0x0004 Bit Default Description O RW IO EN 0 VO Enable 0 Reserve 2 R W 10 Bus Master Function Enable __ _ _ 223 200 Reseved 2 DPD DEVSEL Timing Status Set to 1 b1 to indicate R medium speed timing for NAVAL assertion M82371IDE signals a transaction abort as a bus master receives a target abort a bus master generates a master abort Centrality Communications Inc 216 AT460A BI Developer s Manual Centrality 3130 12 NOTE Bits 27 28 and 29 are Read and Clear R C bit be read the
170. 5 8 AC97 READ TAGH 8 hO AC97 input frame tag Bit 7 1 CODEC is ready 0 CODEC is not ready Bit 6 1 Input frame Slot 1 contains valid echoed address 0 Input frame Slot 1 contains no valid data Bit 5 1 Input frame Slot 2 contains valid AC97 CODEC status data 0 Input frame Slot 2 contains no valid data Bit 4 1 Input frame Slot 3 contain valid PCM left channel data 0 Input frame Slot 3 contains NO valid data Bit 3 1 Input frame Slot 4 contains valid right channel data 0 Input frame Slot 4 contains no valid date Bit 2 0 meaningless for AC97 interface 31 9 CODEC 97 Status register CODEC_AC97_STATUS 0x28 Centrality Communications Inc 295 AT460A BI Developer s Manual Centrality When reading control register from 97 CODEC the result is saved this register It contains the 16 bit control register read data from AC97 CODEC and its corresponding register index Bit Name Default _ Description 45 0 R AC97 STATUS ADR 16 h0 AC97 CODEC register address 31 16 AC97 STATUS DATA 16 0 AC97 CODEC register read data R e CODEC 97 Status Read Control Register CODEC AC97REG OK 0x2C This register is used to monitor the AC97 CODEC command ports Slot 1 and Slot 2 and I O status port Slot 12 Bit Name Default Description 0 R W AC97 REG RD 1 bO AC97 register read status 1 AC97 CODEC has delivered the register read dat
171. 5 b11111 Arbitration lost in RTR bit 315 20 Reserved ___ e Error Code Capture Register CANBUSn ECC 0x0030 Bit Name Default 4 0 R SEG CODE 5 h0 ERR_CODE Description 5 b00011 Start of frame 5 b00010 ID 28 to ID 21 5 b00110 10 20 to ID 18 5 b00100 SRTR bit 5 b00101 IDE bit 5 b00111 ID 17 to ID 13 5 b01111 10 12 to ID 5 5 b01110 ID 4 to ID O 5 b01100 RTR bit 5 b01101 Reserved bit 1 5 b01001 Reserved bit 0 5 b01011 Data Length Code 5 b01010 Data Field 5 b01000 CRC sequence 5 b11000 CRC delimiter 5 b11001 Acknowledge 5 b11011 Acknowledge delimiter 5 b11010 End of frame 5 b10010 Intermission 5 b10001 Active error flag 5 b10110 Passive error flag 5 b10011 Tolerate dominant bits 5 b10111 Error delimiter 5 b11100 Overload flag If 1 the error occurred during reception If 0 the error occurs during transmission 2 0 2 b00 Bit error 2 b01 Form error 2 b10 Stuff error 2 b11 Some other type of error 318 e Error Warning Limit Register CANBUSn EWLR 0x0034 Bit Name Default 7 0 830 R W Centrality Communications Inc Description This register defines the number of errors after which an Error Warning Interrupt should be generated if enabled This register may only be written in Reset Mode In Operating Mode it is read only You should also note
172. 6 460 Developer s Manual Centrality 5 System Control Modules 5 1 Mode Configuration Pins 5 1 1 Overview There are several mode configuration pins that control the different modes of Atlas Il These pins are Table 12 piss Configuration Pins Pin Name Function Name Description X_FA lt 14 13 gt MODE lt 1 0 gt Configure the SSTL IO mode 2 b00 1 8V LVCMOS 2 b01 2 5V SSTL 2 b10 2 5V LVCMOS 2 b11 3 3V LVCMOS X lt 15 gt NAND MODE Configure the NAND Flash mode 1 b0 Disable the support of 2K page 1 b1 Enable the support of 2K page X_FA lt 16 gt Configure the Boot mode 1 b0 Boot from ROM NOR Flash 1 b1 Boot from NAND Flash FA lt 17 gt 1516 Configure Boot Flash bit width poor Ie 8 bit wide 1 b1 16 bit wide lt 19 18 gt TEST_MODE lt 1 0 gt Configure Test Mode 2 b00 Normal mode 2001 ATPG mode 2 b10 JTAG mode 2 b11 BIST mode for details X DF RY BY NAND SEL Configure NAND Flash pin sharing mode 1 b0 Pin share with Video Input Port 101 Pin share with ROM I F NOTE Please also refer to the section of Resource Sharing Controller for more details about the NAND Flash pin multiplex with Video Input Port and ROM I F The following table shows the decoding of JTAG lt 1 0 gt Table 13 Decoding of JTAG lt 1 0 gt _ lt 1 0 gt Description mode 290 ______ 926 9 INTEST moe Cid
173. 6 1 16 LEEREN a PIO modes 0 2 3 4 refer to Data Port accesses All other Ports use 8 bit compatible timing Centrality Communications Inc 218 AT460A BI Developer s Manual Centrality e IDE Slave Timing IDE_SLAVE_TIMING 0x0044 Name Default Description Bit 1 0 PD1_RCT 210 Primary Drive 1 Recovery Time RCT Defines the minimum R W number of clock periods NIRD NIWR are inactive between successive cycles 00 4 01 3 10 2 11 1 3 2 Primary Drive 1 IORDY Sample Point ISP Defines how R W many clock periods after NIRD NIWR is asserted on the IDE before IORDY is sampled 00 5 01 4 10 3 11 2 5 4 SD1 RCT Secondary Drive 1 Recovery Time RCT Defines the R W minimum number of clock periods NIRD NIWR are inactive between successive cycles 00 4 01 3 10 2 11 1 7 6 Secondary Drive 1 IORDY Sample Point ISP Defines how R W many clock periods after NIRD NIWR is asserted on the IDE before IORDY is sampled 00 5 01 4 10 3 11 2 318 __ Reserved e IDE Clock Divide Register IDE_CLK_DIV 0x0050 Name Default Description Bit CLK DIV 4 hO Clock Ratio between System Clock and IDE Clock R W 314 2880 Reserved 7 6 3 2 IDE Control Registers The IDE Control registers occupy 16 bytes of memory space starting at the address specified by the Bus Master Interface Base Address DE_BMI_BASE configuration register Primary channe
174. 6 2 3 Functional Description Centrality Communications Inc 96 AT460A BI Developer s Manual Centrality COMMUNICATIONS 2D BLT External or Display 2 BUS ARB Block Diagram of LCD Controller The LCD controller block provides a means for Atlas I Processor to interface with an external LCD driver LCD display Processor supports various LCD displays for applications ranging from PDA GPS to digital camera There are three major datapaths one for the main display data and one for the second overlay display data and another for the overlay2 display data to support dual panel LCDs or to mix two layer OSDs on top of the main display The LCD controller block connects to the system bus through a BUS HUB ARB module the BUS HUB ARB connects to the system bus as a Bus master and it does further arbitration for up to 8 masters The LCD controller takes 3 master interfaces on the BUS HUB ARB And the LCD controller has one Bus Slave interface for registers reading and writing by the RISC through memory mapped registers and buffers The 3 masters are grouped as a Bus Master DMA interface which will request display data from memory by the three DMA controllers independently On the other side the LCD controller is connected to the pins to interface with the external LCD driver or display The Bus Master Interface requests t
175. 6 6 3 3 PCM Playback The Atlas Il AC97 Controller supports both 48KHz sample rate VRA mode When the AC97 CODEC works at 48KHz stereo mode each audio output frame contain both the left channel and right channel valid data And for the AC97 Controller it fetches 32 bit PCM data from FIFO at the speed of 48KHz for each frame But for the lower sample frequency such as 44 1KHz 22 05KHz 11 025KHz and 8KHz the AC97 Controller can t send valid left and right channel data to AC97 CODEC in each output frame otherwise the FIFO in the AC97 CODEC will overflow When the AC97 CODEC is configured to be in VRA mode the AC97 CODEC will be responsible for the flow control of output data stream In AC link input frame data AC97 CODEC indicates its request of data for next output frame in slot 1 The SLOTREQ bits occupy Slot 1 bit11 to bit 2 which indicate the request from Slot 3 to Slot 12 The SLOTREQ bits are always valid and independent of tag bit Centrality Communications Inc 289 AT460A BI Developer s Manual Centrality 16 bit PCM Left m PCM DI Data DA_DATA PCM Data 16 bit PCM Right SYNC SYNC Generation Read BIT_CLK Control BIT CLK Slot Control unit Counter Judgment AD DATA Figure 71 AC97 PCM Playback Functional Diagram 8 6 6 3 4 Auxiliary Data Input User can program AC97 Controller to select the right slot which is used for auxiliary data input No matter which slot is used to input the data
176. 6 IDE Interface 7 6 1 Overview The IDE Interface is a licensed IP from Mentor Graphics M82371IDE The M82371IDE supports both primary and secondary IDE Integrated Drive Electronics channels with up to two devices per channel The timing of each device is individually configurable But Atlas II the IDE interface only supports primary IDE Integrated Drive Electronics channel with up to two devices So setting up the secondary channel won t take effect The M82371IDE also supports an intermediary synchronous bus interface Peripheral Bus Interface PBI allowing easy interfacing to proprietary bus types It is connected to the internal PCI Bus in Atlas I The IDE interface supports the following key features e Support primary IDE channel Support for two IDE devices Independent programmable timing for each device Programmable DMA Support PIO In Atlas II The IDE interface shares pins with ROM SRAM PCMCIA and NAND Flash 7 6 2 Pin Description IDE Pins are multiplexed with ROM I F Please refer to the section of Pin Sharing for more details Table 51 ROM SRAM Interface Pin Description Pin name Pin Direction Description IDE Select Data Command Active low DMA transfer Acknowldge Active low IDE Interrupt Cd Centrality Communications Inc 215 AT460A BI Developer s Manual Centrality 7 6 3 IDE Interface Registers The IDE Configuration Registers base address is 0x
177. 8x32bit FIFOs As the internal bus is 32bit while the pixel data can be 1 2 4 8 12 and 16 bit the user can select how the LCD views the ordering of frame buffer pixel by programming the big little endian selection bits and the pixel offset bits in SCNBASE OSDBASE or OSD2BASE registers There are two levels of endian selection for a DWORD data from the memory One is for bytes within a DWORD and the other is for 1 2 or 4 bit within a byte Following figures are some examples for these two levels of endian selections in different bit pixel formats The pixel offset values are 0 0 in these examples Two registers to specify a color key range Centrality Communications Inc 99 AT460A BI Developer s Manual Centrality Bit 7 0 Pixel data 7 0 Bit 31 24 23 Figure 18 8bits pixel data ina DWORD Big Endian Bit 11 Pixel data 11 0 Bit 31 Bit 1 0 Bit 7 N Bit 31 24 23 0 Pixel 12 15 Pixel 8 11 Pixel 4 7 Pixel 0 3 Figure 20 2bits pixel data DWORD Big Endian byte Little Endian for byte in a DWORD The following example is for non zero pixel offset value As pixel width is 2 bits the valid pixel offset value range is from 0x0 to OxF The following figure is the case in which pixel offset is 0 5 And the figure indicates the starting pixels of a frame Bit 1 0 Pixel data 1 0 Nn eee 9 Pixel 8 12 Pixel 3 7 Pixel 0 2 Invalid data
178. 9 GPIO4_CTRL18 and GPIO4_CTRL31 Bit Name Default Description O R W INT LT 1 bO GPIO Interrupt low falling edge trigger enable 0 Either the falling edge interrupt or low level interrupt is disabled 1 INT TYPE is set the falling edge interrupt is enabled if GPIO INT TYPE is de asserted the low level interrupt is enabled In Sleep mode this bit will define whether the low level from this GPIO pin will trigger wake up of the chip Only valid for GPIO 1 R W INT HT 1 bO GPIO Interrupt high rising edge trigger enable 0 either rising edge interrupt or high level interrupt is disabled 1 If GPIO INT TYPE is set the rising edge interrupt is enabled if GPIO INT TYPE is de asserted the high level interrupt is enabled In Sleep mode this bit will define whether the high level from this Centrality Communications Inc 90 AT460A BI Developer s Manual Centrality OL 9 5 INT TYPE GPIO ir Type Select bits 0 Interrupt is level triggered 1 Interrupt is edge triggered 3 R W RISC INT Enable the GPIO to generate interrupt to RISC when Interrupt EN Status is set 0 Interrupt is disabled 1 Interrupt is enabled 4 R W STAT 160 GPIO Interrupt Status US 0 No interrupt 1 There is interrupt request Write a one will clear the interrupt status bit 5 R W OUT EN 1 bO GPIO Data output enable 0 The GPIO is input pin 1
179. A mode 1 for I O mode 1 R W IO DMA RW 1 bO 0 write to peripheral 1 read from peripheral 2 R W DMA FLUSH Flush the DMA receive FIFO in case the data length set at the peripheral side doesn t match the dword size set in the DMA control Leave it as reserved if the flush isn t needed 43 Reserved NOTE Bit 0 of CANBUS_DMA_IO_CTRL CANBUSO controls both the receiving and sending channel So it must be set to DMA mode no matter which direction of the DMA transfer e CANBUS DMA IO Length Register CANBUS LEN 0 04 The smallest data size is DWORD i e bit1 and bit of this register will be ignored Name Default Description 31 0 my DATA LEN 32 hO The byte length of a DMA or I O transfer If set to zero the I O or DMA transfer works continuously until it is stopped CANBUS DMA FIFO Level Check Register CANBUS FIFO LEVEL 0xFOC Centrality Communications Inc 342 460 Developer s Manual Centrality Bit Name Default Description 3 0 R W FIFO_SC FIFO stop check in dword length Hua __ __ 4 hO FIFO low check in dword length 19 14 Reserved FIFO high check in dword length 3130 J i Reserved e CANBUS FIFO Operation Register CANBUS FIFO OP OxF10 Bit Default Description 0 R W FIFO_START 1 bO Start the fifo transfer when this bit is declared 1 R W FIFO RESET 1 bO Internally link to fifo start
180. AT460A BI Developer s Manual Z Centrality COMMUNICATIONS Pt solk falling edge 8 R W RFS_ACT_LEVEL 9 R W TFS_ACT_LEVEL lt 29 22 gt R W Centrality Communications Inc IRDA_WIDTH_DIV 21 R W TXD IO MODE ud 1 bO 1 bO ho IIDA IDLE LEVEL Receive sync signal RFS valid level 0 logic 0 1 logic 1 Transmit sync signal TFS valid level 0 logic 0 1 logic 1 In frame idle state sclk mode 0 stop and keep to sclk idle level 1 continue to toggle In frame idle state sclk will stop at level 0 logic 0 1 logic 1 SCLK pin operation mode 0 USP mode 1 mode RFS pin operation mode 0 USP mode RFS 1 mode TFS pin operation mode 0 USP mode TFS 1 mode RXD operation mode 0 USP mode rxd 1 mode TXD operation mode 0 USP mode txd 1 mode SCLK pin input output mode when SCLK PIN MODE 1 0 output mode 1 input mode RFS pin input output mode when RFS PIN MODE 1 0 output mode 1 input mode TFS pin input output mode when TFS PIN MODE 1 0 output mode 1 input mode pin input output mode when RXD PIN MODE 1 0 output mode 1 input mode TXD pin input output mode when TXD PIN MODE 1 0 output mode 1 input mode IrDA data pulse width register If user wants to transmit receive 1 6us width data by setting the IRDA DATA WIDTH in USP_MODE2 you must set this register accor
181. B B B B B B B B RG B B B B B B B B RG B B B B B B B B RG B B B B B B B RG B B B B B B B B RG B B B B B B B B RG B B B B B B B B Centrality Communications Inc Figure 60 Contraction in YUV YCrCb Mode YUVRGB 1 with 1 2 ratio in Row and Column 274 AT460A BI Developer s Manual Centrality v 0 DWV 0 V 0 DV 0 DV 0 D0 0 30 0 3 0 0 3 0 0 3 0 0 DV 0 3 0 0 D W 0 DV O DV O DV O D o C V DV C DIV DV 0 3 0 C 3 0 3 0 DV DV C DV O DV O D w DV V V I V 0 C V 0 00 D W 0 02 C 20 0 20 DODVDODDVDODVODVDODVDODVDODVODVDODVWODDVDODVWODVWODVDVWODVOD DWHDVDODDVDODVDODDVDODVDWODVDWODVWODVDODVWODNWODVWODVWODVWODWVWODWVOD
182. C97 record channel works only when AC97 mode is selected and AC97 AD DLE is de asserted AC97 playback channel status setting 1 97 playback channel is shut down in 97 interface the external AC97 CODEC receive NO valid audio data stream 0 AC97 playback channel is enabled in AC97 interface audio data stream is allowed to be feed to external AC97 CODEC By default the AC97 playback channel is shutdown before playing audio signal through AC97 CODEC user needs to clear this register bit The AC97 playback channel works only when AC97 mode is selected and AC97 DA IDLE is de asserted Z e __ _ _ _ _ _ c 5 8 R W DSP_CTRL 9 R W 10 ULAW_EN 750 RW CODEC interface register control mode 0 RISC control CODEC registers DSP access is disabled 1 DSP control CODEC registers RISC access is disabled For PCM DMA playback channel 0 ALAW expansion is enabled 1 ALAW expansion is disabled For PCM DMA playback channel 0 ULAW expansion is enabled 1 ULAW expansion is disabled 12190 e CODEC 97 Control Register CODEC AC97 0 1 This register is used to configure AC97 controller including e Leftand right channel control e AC97 CODEC warm wake control AC link output frame control Bit Name Default IW 1 0 DA CHANNEL 2 h0 R W 3 2 AD_CHANNEL 270 RW Centrality Communications Inc
183. CC 3 3V 1 bO The power control logic will apply 5 0V when card power is to be applied 1 b1 The power control logic will apply 3 3V when card power is to be applied This bit determines which output signal is used to enable Vcc power to the socket when the card power is applied this bit is used in conjuction with the bits 5 4 of the Power Control register bits Pulse Management Interrupt 1 b0 Interrupts are passed to the irq XX signal as level sensitive 1 b1 When an interrupt occurs the irq XX signal is driven with the pulse train shown in the figure 4 8 and allows for interrupt sharing This bit is valid only in External Hardware Interrupt Signalling mode This bit selects Level or Pulse mode operation of the signal Note that a clock must be present on pci clk for the pulsed interrupts to work Note that only the irq9 and irq10 can work in the pulse mode where as the other are just interrupt sensors 3 R W 1 bO Pulse System IRQ 1 b0 Interrupts are passed to the irq lt XX gt Centrality Communications Inc 240 AT460A BI Developer s Manual Centrality COMMUNICATIONS signal as level sensitive 1 b1 When an interrupt occurs the irq XX signal is driven with the pulse train shown in Fig 4 8 allows for interrupt sharing This bit is valid only in the External Hardware Interrupt Signalling mode This bit selects Level or Pulse mode operation of the irqx sig
184. CTRL registers one for RISC the other for DSP It depends on the current channel is controlled by RISC or DSP to decide which CH LOOP register is being used Name Default Description 11 BUFA VA 1210 E The first section of the loop area BUFA is valid R W LID lt 11 0 gt 0 The first section of the loop area BUFA is invalid 15 12 f 4 7 27 16 BUFB 12180 1 The second section of the loop area BUFB is valid R W LID lt 11 0 gt 0 The second section of the loop area BUFB is invalid 3128 40 O 8 4 NAND Flash Interface 8 4 5 Overview The NAND Flash can be used as a boot loader during boot up or be used as a simple storage device for both program and data When the NAND Flash is sued as a boot loader the boot code will be stored in the first physical block of the NAND Flash and the rest of NAND Flash also can be used as simple storage device The NAND Flash controller supports all types of NAND Flash SmartMedia card It has an independent FIFO and a DMA channel for data transfer to from system memory The NAND Flash controller supports five types of data transfer Centrality Communications Inc 262 460 Developer s Manual Centrality DMA read data from FIFO DMA write data to FIFO RISC read data from FIFO RISC write data to FIFO e RISC directly read data from Flash
185. Communications Inc 208 AT460A BI Developer s Manual LS Centrality COMMUNICATIONS SetSuspendState write and at the end of the resume interval This bit cannot be set if CurrentConnectStatus is cleared This bit is also cleared when PortResetStatusChange is set at the end of the port reset or when the Host Controller is placed in the USBRESUME state write SetPortSuspend The HCD sets the PortSuspendStatus bit by writing a 1 to this bit Writing a 0 has no effect If CurrentConnectStatus is cleared this write does not set PortSuspendStatus instead it sets ConnectStatusChange This informs the driver that it attempted to suspend a disconnected port 3 R W PRTOVRCURI 1 bO Port Over Current Indicator read PortOverCurrentIndicator This bit is only valid when the Root Hub is configured so that over current conditions are reported on a per port basis If per port over current reporting is not supported this bit is always read as 0 If cleared all power operations are normal for this port If SET an overcurrent condition exists on this port write ClearSuspendStatus The HCD writes a 1 to initiate a resume Writing a 0 has no effect A resume is initiated only if PortSuspendStatus is SET 4 PRTRSTST 1 bO Port Reset Status read PortResetStatus When this bit is SET by a write to SetPortReset and will remain asserted until the port reset signaling is completed When reset is
186. Controller This module conforms to SDIO Specification and SD memory card physical layer specifications Power consumption of the system can be kept to a minimum through gated clock control The SDIO SD Host Controller handles SDIO SD Protocol at transmission level by packing data adding cyclic redundancy check CRC start end bit and checking for transaction format correctness SD Mode wide bus width is also supported Here are the key features of SDIO Host Controller Meets SD Host Controller Standard Specification Draft Version 1 0 Card Detection Insertion Removal Password protection of Cards Host clock rate variable between 0 and 25 MHz Supports 1 and 4 bit SD modes Allows card to interrupt host in 1 and 4 bit SD modes Cyclic Redundancy Check CRC7 for command and 16 for data integrity Host Initiates Direct read write 1052 and Extended read write 1053 transactions Host can initiate CMD52 while data transfer for CMD53 is in progress Supports Read wait Control operation Supports Suspend Resume operation Supports Multi Block read and Write 7 4 2 Pin Description Table 38 SDIO Host Interface Pin Description Pin name Direction Description 7 4 3 Functional Description Centrality Communications Inc 162 AT460A BI Developer s Manual LS Centrality COMMUNICATIONS Internal PCI SDIO SD host controller txfifoO Data 3 0 amp Control txfifo1 Logic amp rxfifoO Interrupt Cmd Inte
187. D bus voltage 3 b111 3 3 V Typ 3 b110 3 0 V Typ 3 b101 1 8 V Typ Others Reserved Centrality WUEN ON CARD SERT WUEN ON CARD RE MOVE to enable use of the read wait protocol to stop read data using DAT lt 2 gt line Otherwise the HC has to stop the SD clock to hold read data which restricts commands generation When the HD detects an SD card insertion it shall set this bit according to the CCCR of the SDIO card If the card does not support read wait this bit shall never be set to 1 otherwise DAT line conflict may occur If this bit is set to O Suspend Resume cannot be supported 1 Enable Read Wait Control 0 Disable Read Wait Control This bit is valid only in 4 bit mode of the SDIO card and selects a sample point in the interrupt cycle Setting to 1 enables interrupt detection at the block gap for a multiple block transfer If the SD card cannot signal an interrupt during a multiple block transfer this bit should be set to 0 When the HD detects an SD card insertion it shall set this bit according to the CCCR of the SDIO card Reserved This bit enables wakeup event via CARD INT assertion in the SD NT STATUS register This bit can be set to 1 if FN WUS Wake Up Support in CIS is set to 1 1 Enable 0 Disable This bit enables wakeup event via CARD INTSERT assertion in the SD INT STATUS register FN WUS Wake up Support in CIS does not af
188. DMA three layers mixing support and dual panel display support e On chip RGB to YUV hardware conversion and interface 8 bit 4 2 2 format to TV encoder e Programmable frame and line clock polarity pulse width and starting locations and programmable polarity for output enable and programmable toggle frequency of L_BIAS output pin The LCD controller can be reset by four sources of resets please refer to section of Reset Controller for details After hardware reset the LCD controller is disabled and the output pins are configured as GPIO pins please refer to the section of GPIO for details And after any type of reset all LCD controller registers are reset to the default values shown in the LCD register definitions If the LCD controller is being enabled for the first time after hardware reset following registers must be programmed to enable the LCD controller e Configure power manager clock enable register EN to enable LCD controller system clock See section of Power Manager for details e Configure Timing Control Register LCD TIMCTRL to set the LCD controller as master mode or slave mode that is set L_PCLK L LCLK or as outputs or inputs e Configure GPIO mux register GPlOx PAD EN to release pins to LCD e Write color palette or grey palette FRC sequence table if needed e Program all of the LCD registers required except the DMA start registers SCN CUR Y OSD CUR Y and SCN AD
189. DR OSD and the Frame Valid bit bit of DISPLAYMODE register e Write 1 to DMA start registers SCN CUR OSD CUR Y and SCN ADDR OSD ADDR to start the DMA e Write 1 to the Frame Valid bit to output the valid image frame to data pins 6 2 2 Pin Description 1 The actual resolution is limited by the memory bandwidth Centrality Communications Inc 94 460 5 Centrality When the LCD controller is enabled LDD lt 17 0 gt and L_BIAS outputs only and L_PCLK and L_FCLK can be programmable inputs or outputs slave or master mode When the LCD Controller is disabled LDD lt 17 8 gt can be used as general purpose IO please refer to section of GPIO for details Table 27 JAtlas Il LCD Controller Pin Descriptions Function Type Definition Name LCD Data Bus Provide four eight or sixteen bit data at a time to the X GPIO 25 24 LDD lt 17 16 gt LCD panel Either the bottom four pins LDD lt 3 0 gt the T bottom 8 pins LDD lt 7 0 gt or all 16 pins LDD lt 15 0 gt will be used For passive monochrome displays each pin value represents a single pixel For passive color displays every three pins represent a single pixel For active displays all the used data pins represent a single pixel LDD lt 17 gt is the R channel s lowest bit and LCD lt 16 gt is the channel s lowest bit when rgb666 output mode is needed If not used t
190. DRAM Supply voltage PLL VDD_PHA 0 3 4 V Supply voltage PLL VDD PLA 0 3 1 44 V Supply voltage PLL VDD PLD 0 3 1 44 V Supply voltage core VTT 0 3 1 44 V Supply voltage core VREF 0 3 1 44 V Supply voltage core VDDPRE 0 3 1 44 V Supply voltage inter model VDDPDN 0 3 1 44 V Input voltage overshoot Vinos 0 5 V Input voltage undershoot Vinus 0 5 V Storage temperature range Tstg 40 150 1 Absolute maximum ratings stress ratings only and functional operation at the maximums is not guaranteed Stresses beyond those listed may affect device reliability or cause permanent damage 9 3 2 Recommended Operation Conditions Table 95 gives the recommended operating conditions Table 95 Recommended Operating Conditions1 Characteristic Supply voltage I O buffers VDDIO 3 13 3 3 3 5 V Supply voltage I O buffers XVDDIO 3 13 3 3 3 5 V Supply voltage mem bus VDD MEM DDR SDRAM vss 237 25 SP qox Centrality Communications Inc 358 460 Developer s Manual Centrality Supply voltage mem bus VDD_MEM SDRAM SDRAM 3 13 3 3 3 5 V Supply voltage PLL VDD PHA 3 13 3 3 3 5 V Supply voltage PLL VDD PLA 1 14 1 2 1 26 V Supply voltage PLL VDD PLD 1 14 1 2 1 26 V Supply voltage core VTT 1 14 1 2 1 26 V Supply voltage core VREF 1 14 1 2 1 26 V Supply voltage core VDDPRE 1 2 1 28 1 36 V Supply
191. Developer s Manual Centrality Default 0x0000001F Default 0 00000000 0x0034 Ox1A 1B PENDING EXT Extended Interrupt Pending Register 0 0038 7 J INT IRQ PENDING EXT Extended IRQ Pending Register 0x003C 7 INT FIQ PENDING EXT Extended FIQ Pending Register IRQLO interrupt r IRQL1 interrupt 0 0048 ____ INT ID Interrupt ID Others Others e Interrupt Controller Pending Register INT_PENDING RISC 0 0000 DSP 0x000 0x001 The INT_PENDING is a 32 bit read only register that shows all active interrupts in the system These bits are not affected by the state of the mask register The following table shows the pending interrupt source assigned to each bit position in the INT PENDING For more details on the second level interrupts see the section describing that unit Bits within the INT_PENDING are read only and represent the logical OR of status bits for a given interrupt within the source unit Once an interrupt has been serviced the handler clears the pending interrupt at the source by writing a one to the necessary status bit Clearing the interrupt status bit at the source automatically clears the corresponding INT_IRQ_PENDING INT FIQ PENDING flag provided there are no other interrupt status bits set within the source unit All interrupt source status bits are cleared by writing a one to them Writing a zero to an interrupt status bit
192. Developer s Manual Centrality e Screen Memory Base Register LCD SCNBASE 0x100 First MA in Second DMA a line Y Y Unused bytes i first DWORD o first DMA Figure 29 Pixel Offset Name Default Description 3 PIXEL_OFFSET 4 hO Pixel offset for screen channel Since the pixel R W data can be as little as 2 bits pixel this pixel offset specifies which bits within the first DWORD specified by bits 30 4 is the first valid pixel The pixel data can be 2 bit 4 bit 8 bit 12 bit 16 bit pixel Example 16 bit pixel Big endian in word 0000 bits 31 16 0001 bits 15 07 Example 16 bit pixel Little endian in word 0000 bits 15 07 0001 bits 31 16 30 4 BASE 2710 DMA address of the starting memory location R W for the screen data this is a byte address but the lower 4 address bits must be zeroes which means the DMA start address must lie on a 4 dwords burst boundary 31 DMA MODE 1 bO Continuous mode DMA R W 1 when this completes will automatically generate a DMA with exactly the same setting 0 each must be explicitly started by software e X Size for screen LCD 5 XSIZE 0x104 Bit Name Default Description 12 0 SCN XSIZE 1310 This value specifies the number of consecutive 4 DWORD R W bursts per line for the screen DMA This value should be inclusive of any partial DWO
193. Disable the HSYNC during vertical blank time 0 Enable the HSYNC during vertical blank time 31 4 RW Reserved DMA Control Register CAM 0x044 Bit Default Description O R W 1 bO 0 DMA operation 1 IO operation E Cd Reserved n DMA_FLUSH Flush the DMA receive FIFO in case the data Centrality Communications Inc 280 AT460A BI Developer s Manual Centrality length set at the peripheral side doesn t match the DWORD size set in the DMA control _____________ 5 RW ENDIAN MODE 210 00 not changed 01 byte exchange in dword 10 word exchange in dword 11 byte exchange in word 316 Reserved DMA Operation Length Register CAM DMA LEN 0x048 Bit Default Description 31 0 DATA_LEN 32710 The byte length of a DMA transfer If set to zero R W the DMA transfer works continuously until it is stopped FIFO Control Register CAM FIFO CTRL 0x04C Description FIFO_WIDTH byte mode FIFO 01 word mode FIFO 10 dword mode FIFO 11 dword mode FIFO 312 aoho Resevd 2 FIFO Level Check Register CAM FIFO LEVEL CHK 0x050 Bit Name Default Description 96 _____ 4hnO jReseved 196 40 Reseved 31 20 6 jReseved FIFO Operation Register CAM FIFO OP 0x054 Bit Default Description 0 FIFO
194. Dual 8bit Upper Lower LDD lt 7 0 gt LDD lt 7 gt Monochrome Lower Upper LDD lt 15 8 gt LDD lt 15 gt 16bit LDD lt 15 0 gt LDD lt 15 gt NOTE For passive color mode one pixel is made of three bits of LDD pins therefore the last column of the above table is actually the Red bit of top left pixel in a frame Following is an example of pixel ordering for passive color 8bit parallel dual panel display where n is the number of rows of the panel Top Left Corner of Screen of the upper half pannel Column 0 Column 0 Column 0 Column 1 Column 1 Column 1 Column 2 Column 2 Column 2 Red Green Blue Red Green Blue Red Green Blue Row 0 LDD lt 7 gt LDD 6 LDD lt 5 gt LDD lt 4 gt LDD lt 3 gt LDD lt 2 gt LDD lt 1 gt LDD lt 0 gt LDD lt 7 gt Row 1 LDD lt 7 gt LDD lt 6 gt LDD lt 5 gt LDD lt 4 gt LDD lt 3 gt LDD lt 2 gt LDD lt 1 gt LDD lt 0 gt LDD lt 7 gt 47 Row 2 LDD lt 7 gt LDD lt 6 gt LDD lt 5 gt LDD lt 4 gt LDD lt 3 gt LDD lt 2 gt LDD lt 1 gt LDD lt 0 gt LDD lt 7 gt Top Left Corner of Screen of the second half pannel Row 2 1 LDD 15 LDD 14 LDD 13 LDD 12 LDD 11 LDD 10 LDD lt 9 gt LDD lt 8 gt LDD 15 Pixel Ordering of Passive Color 8 bit Parallel Dual Panel Display For color TFT panels LDD lt 17 0 gt can be used for 12 16 or 18 bit panels LDD lt 7 0 gt are used for 8 bit RGB muxed TFT color panel
195. ENDING will also change This needs special care in interrupt routine If in interrupt routine user writes the INT RISC MASK register to mask the interrupt from certain block the INT IRQ PENDING will change to 0 accordingly User can not read this register to determine the interrupt status Instead user should read INT PENDING register 4 The INT PENDING register contain different information for DSP and RISC The bit that are different are listed below INT PENDING bit RISC read DSP read IPO PIO 0 for RISC __ GPIO interrupt0 for 5 ___ IP10 DSP interrupt RISC RISC interrupt DSP OS TIMER1 5 interrupt amp OS TIMER1 5 interrupt amp TIMERMUX RISC MASK TIMERMUX DSP MASK 5 5 OS Timer Centrality Communications Inc 67 AT460A BI Developer s Manual Centrality 5 5 3 Overview There 6 programmable OS timers in the Atlas II User can program them independently All 6 OS timers are actually generated from a single 64 bit counter TIMER_COUNTER The counter is clocked by a divided clock from system clock User can configure the frequency of this divided clock by programming TIMER_DIV register If the value of the TIMER COUNTER matches either one of the 6 timers there will be an interrupt generated to the RISC if the corresponding enable bit is set The 6 timer can also act as a Watchdog timer when the Watchdog mode is enabled In this mode if this timer matches the TIMER COUNTER lower 32
196. EPKT lt 0 gt 19 18 17 16 15 14 13 12 11 10 lt 19 gt lt 18 gt lt 16 gt lt 15 gt lt 14 gt lt 13 gt gt lt mimjmim i gt gt m mim m lt 11 gt lt 10 gt lt 9 gt lt 8 gt gt X 7 lt 6 gt lt 5 gt lt 4 gt lt 3 gt DE_A lt 2 gt DE A 1 DE lt 0 gt U Ul Ul Uf Ul Ul m Ul Ul Ul Ul Ul R RY Ul Ul UL U gt gt gt gt A A A A N 2 lt 1 gt lt 0 gt CLE DE ALE ______ _____ ______ ______ _____ XFA9 6 XFA5 __ ______ j XFA2 jj _15 DF_AD lt 15 gt IDE_D lt 15 gt IDE D 0 PD lt 15 gt PD lt 0 gt GPIO group5 offset 15 GPIO group5 offset 0 mE DF AD 0 XFOEB DF RDB J Y GPIO group3 offset 31 xX FWE B 9 4 3 After reset GPIO will have no control over these pins User can write corresponding GPIO control registers to give the control of these pins to GPIO The priority of the above functions is as following e is enabled during debug ETM9 will have control over X FD 31 X FD 16 no matter which setting it is Centrality Communications Inc 79 AT460A BI Developer s Manual Centrality e Else
197. EQ SEL according to the Capabilities register Bit Name Default Description R W INT_CLK_EN 1 bO This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event The HC should stop its internal clock to go very low power state Still registers shall be able to be read and written Clock starts to oscillate when this bit is set to 1 When clock oscillation is stable the HC shall set INT CLK STABLE in this register to 1 This bit shall not affect card detection 1 Oscillate 0 Stop This bit is set to 1 when SD clock is stable after writing to INT EN in this register to 1 The SD Host Driver shall wait to set SDCLK EN until this bit is set to 1 Note This is useful when using PLL for a clock oscillator that requires setup time 1 Ready 0 Not Ready X SDCLK FREQ SEL Reserved This register is used to select the frequency of the SDCLK pin The frequency is not programmed directly rather this register holds the divisor of the BASE CLK FREQ for SD clock in the Capabilities register Only the following settings are allowed 0x80 base clock divided by 256 0x40 base clock divided by 128 0x20 base clock divided by 64 0x10 base clock divided by 32 0x08 base clock divided by 16 0x04 base clock divided by 8 2 R W SDCLK EN The HC shall stop SDCLK when writing this bit to 0 SDCLK FREQ SEL can be changed when this bit is 0 Then the HC shall maintai
198. Each pin has two methods interrupt edge level Due to synchronization prioritization and mapping of external interrupt sources the propagation of external interrupts to the core processor is delayed by several IO clk clock cycles The following table specifies the interrupt latencies in IO cycles The IO frequency is programmable in the Clock Distribution Module Table 103 Minimum pulse width for external interrupts to be recognized Name Min Pulse Width Max Pulse Width Reference Clock Centrality Communications Inc 363 AT460A BI Developer s Manual Centrality All external interrupts gt 3 clock cycle IO 9 4 11 SDRAM sdr32 1 x Address Control and Data output clocked by sys The path delay of x_mem_clk can be adjust by Manager Delay Control Register PWR_DELAY_CTRL_0O only x mem the others can t be changed 2 Data input is clocked by mck_i Mck_i can be driven by internal mem_clk or pad loop back x_mem_clk from PWR DELAY CTRL 0 the path delay of i can be configured by PWR DELAY CTRL 1 Because the internal delay of x mem amp mck i are configurable it should be relatively loose for the timing table 116 9 4 11 1Memory Interface Timing Standard SDRAM Read Command Table 104 Standard SDRAM Memory Read Timing Sym Description Min Units tvali Control Signals Address and MBA Valid ris valg after rising
199. FO request control register to control when the FIFO generates requests to the DMA Controller For example the value in the request control register can be half of the FIFO size Then once the FIFO is half full empty it will generate a request signal to the DMA controller to start or stop the DMA If the peripheral needs service sooner the user can program the register to a higher lower value depending on the direction of the DMA If the peripheral is a full duplex device then it needs to have 2 FIFOs one for each direction If the peripheral is half duplex then one FIFO is enough But the peripheral designer needs to be careful in deciding the size of the FIFO to prevent the FIFO overflow or underflow If an overflow or underflow occurs it will generate an interrupt The DMA controller is intended to relieve the processor of the interrupt overhead in servicing these peripherals via a programmed I O But if desired any or all peripherals can be serviced by the programmed instead of the DMA Each peripheral is capable of requesting processor service through its own interrupt line 1 The x means the DMA channel number from 0 to 11 Centrality Communications Inc 252 460 Developer s Manual Centrality 8 3 2 Functional Description 8 3 2 1 DMA Channel Arbitration DMA Requests Arbiter DMA Controller FSM DMA DMA Configuration Address Register file Generator 1950 I O Memory Bus Interf
200. Format SFF or Extended Frame Format EFF as follows Table 89 Filter Bit Patterns Standard Frame Format Single Filter 0x0044 0x0048 0 004 0 0050 10 28 10 21 10 20 RTR XXXX not Data Byte 1 Data Byte 2 ID 18 matched ooo lt eee unused unused NOTE If matching of the data bytes is not required AMR2 and AMR3 should be set to FFh Centrality Communications Inc 340 AT460A BI Developer s Manual Centrality Standard Frame Format Dual Filter 0x0044 0x0048 0x004C 0x0050 ID 28 10 21 10 20 XXXX not Byte Data Byte Data Byte 2 10 18 matched 1 7 4 1 3 0 not matched iter ACRO 7 0 __ ACR3 3 0 7 0 1 7 4 1 3 0 3 0 2 7 0 __ ACR3 74 po AMR2 7 0 1 Extended Frame Single Filter 0x0044 0x0048 0x004C 0x0050 ID 28 10 21 20 0 13 10 12 0 5 10 4 0 0 RTR XX not matched unused unused Extended Frame Format Dual Filter 0x0044 0x0048 0x004C 0x0050 ID 28 10 21 10 20 10 13 10 12 ID 5 not 10 4 RTR not XX not matched ID O not matched matched matched iter 0 2 ACRO 0 ACR1 7 0 E AMRO 7 0 2 7 0 7 0 _______ 7 0 1 e CANBUS Receive Message Counter CANBUSn_RMC 0x0074 Bit Name Default Description 4 0 R 5 hO The Receive Message Counter register rec
201. IFO data count 6 R FIFO empty status GE Equivalent to FIFO FULL FIFO LEVEL 33175 12580 e USP RX FIFO Data Register USP FIFO DATA 9 0x138 DSP 0x5c 0x5d Name Default Description FIFO_DATA 320 The FIFO data register which is the bottom of the RX_FIFO Centrality Communications Inc 327 AT460A BI Developer s Manual Centrality 8 9 CAN Bus Controller 8 9 1 Overview The CANBUS controller in Atlas II is a stand alone controller for the CAN Controller Area Network used in the automotive industry and in a number of other industrial environments It provides an interface between a microprocessor and a CAN Bus which carries out all the actions of data encoding decoding including serialisation deserialisation of data bit stuffing unstuffing message management acceptance filtering acknowledgement error detection and signaling and re transmission bit timing and synchronization involved in transmitting and receiving information over a CAN network Supports full CAN 2 0 both 2 0A equivalent to CAN 1 2 and 2 0B Supports both 11 bit and 29 bit identifiers Supports bit rates from less than 125Kbaud to more than 1Mbaud 64 byte Receive FIFO Software driven bit rate detection offering hot plug in support Acceptance filtering Single shot transmission option Listen only mode Reception of own messages Error interrupt generated for each CAN bu
202. ISC interface When Atlas II uses DDR or 32 bit SDRAM as system memory this FIFO can be enabled to speed up the CPU read Bit Name Default Description Centrality Communications Inc 19 AT460A BI Developer s Manual Centrality 0 R W 151 Pre fetch enable bit 1 Enabled 0 Disabled 31 1 2 1370 NOTE This register bit has to be diabled 16 bit SDRAM mode Centrality Communications Inc 20 AT460A BI Developer s Manual LS Centrality COMMUNICATIONS 3 DSP Subsystem 3 1 Overview The DSP Subsystem in Atlas II is similar to the Atlas I it includes a 16 bit general purpose DSP core Program amp Data memory System bus interface and Host Interface RISC I O Bus DSP Subsystem DSP Core Host Interface DSP Interface Bus GPS Memory Interface System Memory Bus Figure 4 DSP Subsystem Block Diagram But the DSP Subsystem in Atlas Il provides higher performance and more features as following e Faster speed 200MHz 4x larger Memory than Atlas 1 e Support 1X and 2X1 Clock modes e Idle Power down mode The flexible architecture and comprehensive instruction set allow the DSP to perform multiple operations simultaneously In one processor cycle the processor can Generate the next program address Fetch the next instruction Perform one or two data moves Update one or two data address pointers Perform a co
203. Inc 28 460 Developer s Manual Centrality R W information between RISC and DSP RISC had the priority to write this register 31 16 DATA_H 16h0 Same as above R W Centrality Communications Inc 29 AT460A BI Developer s Manual Centrality 4 System Memory Interface 4 1 Overview The Atlas II implements a high speed internal system memory bus that can run up to 200MHz There are 5 bus masters on this bus RISC Subsystem DSP Subsystem Graphic Display PCI Bridge and the IO Bridge And there are 2 bus slaves target the DRAM Controller and or SRAM Controller Each bus master can choose its bus slave target between the DRAM Controller and SRAM Controller separately There is a System Arbiter to arbitrate the memory access of all 5 bus masters In most cases when users want to achieve high performance and high bandwidth then the DRAM Controller should be used as the bus slave In some other cases when users want to achieve low power and reasonable bandwidth then the SRAM Controller may be used as the bus slave 4 2 System Arbiter 4 2 1 Overview As specified above there are a total of 5 bus masters on the system memory bus The System Arbiter arbitrates the requests from the 5 bus masters and passes the appropriate accesses to the active bus slave either DRAM Controller or SRAM Controller Table 8 System Bus Master Allocation Bus Masters Block System Bus Mast
204. Jm o o O ou o Centrality Communications Inc 272 460 Developer s Manual Centrality Figure 58 Contraction in Bayer RGB Mode with 1 2 Ratio in Row and Column Centrality Communications Inc 273 AT460A BI Developer s Manual Centrality RI G R 8 B G B G B B 6 G B G B G B G B G B G B G B G B R G R G R G R G 8 8 8 G B G R G R G R G R G G B G B G B G B G R B G R GR G Figure 59 Contraction in Bayer RGB Mode with 1 4 Ratio Row and Column For YUV YCrCb mode it first converts the YUV YCrCb data to RGB data then scales the RGB data as following table RG B B B B B B B RG
205. M Charge Device Model CDM JEDEC JESD22 C101 500 V ILAT Latch up Current at TA 70 positive negative 100 mA 9 3 5 Power Dissipation Power dissipation of the Atlasll is caused by 4 different components 1 the dissipation of the core digital logic supplied by VDDPRE 2 the dissipation of the PLL circuitry supplied by VDD PHA and VDD PLA Centrality Communications Inc 360 460 Developer s Manual Centrality 3 the dissipation of the IO logic supplied by VDD IO MEM VDD_1O 4 the dissipation of the some internal model supplied by VDDPDN this can be shutdown by external power management see every model Table 99 details typical measured core and PLL power dissipation figures for a range of operating modes However the dissipation due to the Switching of the IO pins can not be given in general but must be calculated by the user for each application case using the following formula Pio Pian VDD IO f where N is the number of output pins switching in a group M C is the capacitance per pin VDD_IO is the IO voltage swing f is the switching frequency and PlOint is the power consumed by the unloaded IO stage The total power consumption of the Atlasll must not exceed the value which would cause the maximum junction temperature to be exceeded and damaged Protal Pio Pinm Table 99 Power Dissipation normal mode
206. NG EXT RISC 0x0038 0x003C The INT IRQ PENDING EXT and the INT FIQ PENDING EXT contain one flag per interrupt for MUXED interrupts Please refer to INT PENDING EXT register for the exact bit definition Bit Default Description IRQ extended pending bits 0 No interrupt pending 1 Interrupt pending 777 150 dT Reserved Bit Name Default Description FIQ extended pending bits 0 No interrupt pending 1 Interrupt pending 31 17 __ 1 150 dT Reserved e Interrupt Controller DSP DSP1 Extended Pending Register INT DSPO PENDING EXT INT DSP1 PENDING EXT RISC 0x0040 0x0044 DSP 0x20 0x22 The INT DSPO PENDING EXT and the INT DSP1 PENDING EXT contain one flag per interrupt for MUXED interrupts Please refer to INT PENDING EXT register for the exact bit definition Bit Name Default Description 16 0 DSPOE 17 hO DSPO extended pending bits 16 0 gt 0 No interrupt pending 1 Interrupt pending 31 17 __ 150 Reserved Bit Name Default Description 16 0 DSP1E lt 1 17 hO DSP1 extended pending bits 6 0 gt 0 No interrupt pending 1 Interrupt pending Centrality Communications Inc 65 AT460A BI Developer s Manual Centrality 31 17 __ 1550 e Interrupt Controller ID Register INT_ID RISC 0x0048 The Interrupt Controller ID register returns the interrupt ID from pending interrupts Each time RISC read this register it will return
207. NGTH Then the DMA address will go back to the beginning of this area If Y LENGTH or DMA WIDTH is equal to 0 then the DMA address will not change at all And the DMA will keep transferring the data to the same DMA address until user force to stop it In loop mode the DMA data region is actually divided into two halves BUFA and BUFB i e Buffer A and Buffer B The DMA controller will generate interrupt twice during each loop one time is when the DMA address reaches the end of BUFA the other time is when the DMA address reaches the end of the BUFB And of course the interrupt can only be generated when the corresponding interrupt enable DMA_INT_EN bit is set Each half BUFA amp BUFB has its own buffer valid register bit which can be programmed by user The loop DMA will not be really started until the current buffer valid register bit is asserted For example if when the DMA goes to the end of BUFA and the valid bit of BUFB is not set then the DMA will stop at the end of BUFA until the valid bit of BUFB is set 8 3 4 DMA Controller Registers Table 65 Controller Register RISC DSP I O Register Description Address Address lt 7 0 gt lt 11 0 gt 0 000 CHO CTRL DMA channel 0 control register 0x0010 0x08 0x09 DMA CH1 ADDR DMA channel 1 address register 0 0014 DMA CH1 XLEN DMA channel 1 X length register 0x0008 DMA CHO YLEN DMA channel 0 Y length register Centrality Communications Inc 258
208. NP This interrupt is asserted when the AWaitDisconnectTimer expires This timer is started in the A SUSPEND state and when it expires it will cause the transition to A WAIT VFALL AWAITBTO 1700 A Wait Connect Time Out Interrupt Centrality Communications Inc 197 AT460A BI Developer s Manual Centrality This timer is only used in Hardware HNP When the AWaitConnectTimer expires this interrupt is asserted The timer is started when in the A_WAIT_BCONN state and when it times out the state transitions to the A_WAIT_VFALL state This interrupt is only asserted if the InsertionModeSet is cleared 31 9 __ Reserved e USB OTG HNP Interrupt Enable Register USBOTG INT EN 0x0030 Bit Default Description 79 10 Reseved e USB OTG Function Command Status Register USBOTG FC CMD STATUS 0x0040 Bit Default Description RESETDET USB Bus Reset Detected 1 R W RSMINPROG 1 bO Resume In Progress When Software reads this bit to be 1 it indicates that the USB bus and the Function controller are in the RESUME state 0 indicates that the USB bus and the Function controller are not in the RESUME state Writing a 0 leaves the hardware unchanged Writing a 1 generates a RESUME signal to the upstream port and lets the xcvr exit the power saving mode Writing a 1 is a RESUME command It will not affect the value of the physical register bit which merely d
209. N_0 Magnitude bit of GPS baseband signals from GPS RF X SAMPLE CLK Sample clock to GPS RF X RF CLK Clock from GPS RF NOTE Normally there needs to have a GPIO to handle the sleep mode control of the GPS RF module Centrality Communications Inc 346 AT460A BI Developer s Manual Centrality 9 Physical Information This chapter describes the mechanical data and package information of AT460A BI It is a 19x19mm 324 ball TFBGA package with 1mm pitch 9 1 Pinout Table 93 AT460A BI Pinout i ad Pin Description ___ 05 x Pxpea gt Video Input Port Data Input DF_AD lt 4 gt Video Input Port Data Input DF_AD lt 3 gt Be Video Input Port Data Input DF_AD lt 2 gt lt Video Input Port Data Input DF_AD lt 1 gt Video Input Port Data Input DF_AD lt 0 gt e osme Por Pua Goer OF mem vars Por Hoon Se e rouwosbez ROMSRAM chip Select 827 as roe sats cnn sacs buwosoez ROMSRAM Chis Select OF 05 8 02 powon xs cous __ ora fo ome E
210. O pin can be configured as input output open drain pin independently When a GPIO is configured as input it can be also enabled as an interrupt source edge or level triggered Most of the GPIO pins have optional internal pull up resistor 75K ohm only a few have optional pull down resistor And most of the GPIO pins are multiplexed with other functional pins All GPIO pins are grouped into 6 groups Each group has 32 GPIO s And there are 32 control registers for each GPIO functional control 1 register for pad multiplex control 1 for DSP access control only valid for group 0 1 for interrupt status and 1 for sleep mode status The following table shows the Pin Mux of each GPIO Table 24 Pin Mux Group GPIO Pin Name X SCL 1 X_PXD lt 15 0 gt Centrality Communications Inc 83 AT460A BI Developer s Manual COMMUNICATIONS Centrality 7 E 2 lt LL c o 2 lt lt x LL c gt lt X SAMPLE CLK X CLK X L X L LCLK FCK L BIAS X LDD 7 0 lt 25 16 gt INPACK PC WAIT 101516 AT460A BI Developer s Manual 84 Centrality Communications Inc Centrality RXD 1 X_FD lt 31 0 gt 5 8 13 GPIO Registers Use the GPIO Pin Output Enable bit OUT EN to set whether the GPIO pins are outputs or inputs When programmed as an output the pin can be set high by writing a 1 to
211. OMMUNICATIONS Audio CODEC controller registers address offset 0x0 TX FIFO control registers address offset Oxf80 RX FIFO control registers address offset OxfcO AUX TX FIFO control registers address offset 0 80 AUX RX FIFO control registers address offset OxB80 8 6 6 2 DMA Interface e PCM DMA Channel The CODEC interface will have FIFOs for PCM audio data transfer for AC97 interface The FIFOs are organized as two separate physical SRAM blocks each one is sixteen 32 bit entries one for audio in channel 6 and another for audio out channel 7 AC97 interface expect to receive a 32 bit value from the FIFO that contains two samples In stereo normal mode the data will be interlaced as LR LR LR samples In stereo interlace mode the data will be in RL RL RL format In mono mode the 16 bit input data is saved in low WORD and then high WORD The audio CODEC interface shares the DMA controller with other peripherals There are programmable FIFO level check registers to decide the CODEC FIFO request priority And also the DMA block will update the FIFO status during the data transaction When FIFO is full or empty the FIFO full or empty interrupt will be generated more read or write operation to the empty or full FIFO will trigger the FIFO underflow or overflow interrupt if the interrupt is enabled Please refer to the DMA Controller and peripheral FIFO for more information about the DMA interface e Auxiliary DMA Channel
212. ORD data transfer to from the peripheral For 1 D DMA it is not so important because the last data transfer in the whole DMA will not affect the peripheral FIFO But in 2 D DMA when X length is not in the 16 byte boundary then the last burst of every line will only do a 1 DWORD data transfer Thus the DMA controller will not do extra data transfer and will not affect the data sequence in the peripheral FIFO Note From the system memory s point of view it will still see 2 bursts on each line i e the 5 DWORD data transfer of each line will take 8 DWORD s memory space Bit Name Default Description XL lt 11 0 gt 12 h0 DMA X length in 32 bit DWORD boundary R W 31 12 200 DMA Channel lt 11 0 gt Y Length Register DMA_CH lt 11 0 gt _YLEN The DMA Y length specifies the number of lines in DMA transfer The number of the lines in DMA transfer is Y Length 1 The maximum number of line can be 2048 To set Y length to 0 has the effect that doing 1 D DMA Bit Name Default Description 1 It should be less than the value of DMA width register Centrality Communications Inc 260 AT460A BI Developer s Manual Centrality 11 0 YL lt 11 0 gt 1280 DMA Y length R W 31 12 __ 7 2080 e DMA Channel 11 0 Control Register DMA_CH lt 11 0 gt _CTRL Default Description WS lt 1 0 gt 270 DMA width register select signal 00 select DMA WIDTHO 01 select WIDTH1 10 sele
213. O_LEN then resets and starts the TX FIFO DMA can be started The DMA controller will transfer the data from the memory to TX_FIFO till all the data is transmitted out The DMA receiving operation is similar to the transmitting The number of the data to be received is stored the USP_RX_DMA_IO_LEN DMA controller will read data from the RX_FIFO to memory till all the data is finished receiving 8 8 5 USP Registers Each USP in Atlas II has the same set of registers so there offset address is the same The actual address of the USP register is equal to the USP base address plus the offset address USP1 base address Oxab010000 USP2 base address O0xab020000 USP3 base address 0000 USP4 base address Oxab040000 USP5 base address Oxab050000 The following table shows the all the registers of USPand their offset address Table 81 USP Register Mapping ARM9 DSP I O Register Description Address Address 5 lt 7 0 gt 0 00 0 01 SP mode setting register 1 0 02 0 03 SP mode setting register 2 8 0 04 0 05 SP TX FRAME CTRL SP transmit frame control register 0 06 0 07 SP RX FRAME CTRL SP receive frame control register 0x08 USP TX RX ENABLE USP transmit amp receive enable register USP INT ENABLE USP interrupt enable register Centrality Communications Inc 316 460 Developer s Manual Centrality 0 20 USP_RISC_DSP_MODE USP accessing select register Ox28
214. Off state accordance with the CAN 2 0 specification and is automatically put into Reset mode except during start up when there is only one node on the CAN bus An Error Warning Interrupt is also generated if enabled After a hardware reset the Transmit Error Counter is automatically set to 0 After a Bus Off event the register is initialized to 127 in order to count the minimum protocol defined time before the CANBUS controller can take part in further transmission on the CAN bus 128 occurrences of the Bus Free sequence of 11 consecutive recessive bits Reading the Transmit Error Counter during this time will give the status of the Bus Off recovery Note If the Reset Mode is re entered before the Bus Off recovery has been completed TXERR gt 0 Bus Off will stay active with TXERR frozen until the CANBUS controller is taken back into Operating Mode The register is read only in Operating Mode but may be written in Reset Mode While in Bus Off state writing a value in the range from 0 to 254 to TXERR clears the Bus Off flag The CANBUS controller will then wait for just one Bus Free sequence after the Reset Mode has been cleared Writing 255 to TXERR in Reset Mode initiates a CPU driven Bus Off event No error or bus status change happens in response to the new TXERR value until the CANBUS controller is taken back into Operating Mode when a Bus Off event will be performed exactly as if it had been forced by a
215. PCI Bridge DSP Data High Register SYS2PCI DSP DATAH 0x0008 Bit Default Description DATAH 16180 PCI data high for DSP IO access on PCI bus Centrality Communications Inc 153 AT460A BI Developer s Manual Centrality PCI Bridge DSP Status Register SYS2PCI DSP STATUS 0x000A Bit Name Default Description oR 90 Reserved 1 1 bO System to PCI Bridge Master abort interrupt Read 1 interrupt pending 0 no interrupt pending Write no effect 2 R TIMEOUT 1 bO System to PCI Bridge Time out interrupt Read 1 interrupt pending 0 no interrupt pending Write no effect 3153 __ 0 This register is read only about interrupt status information for DSP access It requires RISC access to clear the interrupt status 7 3 ROM SRAM Controller 7 3 1 Overview The Atlas II ROM SRAM interface supports both fixed latency and variable latency devices such as ROM NOR Flash SRAM or SRAM like devices The ROM SRAM Controller is one of the PCI devices on the internal PCI Bus It can be programmed as a normal peripheral interface or it can be programmed as the system memory controller 7 3 2 Pin Description The following table shows the ROM SRAM interface pins and their functional description The ROM SRAM interface pins are multiplexed with others interfaces PCMCIA IDE and NAND Flash Please refer to Developer s Manual for more information Ta
216. PDSanan PDSxan DPno Each raster operation code represents a Boolean operation in which the values of the pixels in the Source the selected brush pattern and the destination are combined The operands and operands are D Destination bitmap P Selected brush pattern S Source bitmap a bitwise AND n bitwise NOT inverse o bitwise OR x bitwise XOR exclusive OR Centrality Communications Inc 146 AT460A BI Developer s Manual Centrality All Boolean operations are presented in reverse Polish notation For example SDPnoa represents D P amp S DPSDaoxn represents S amp D P D This engine supports all 256 rop operations and while doing ROP3 operations only mono pattern as the following two registers defined is supported BitBLT pattern matrix low bytes PM LOW 0x1C40 Bit Default Description LOW 32 h0 Bit31 bitO of the 8 8 mono pattern R W e BitBLT pattern matrix high bytes BLT_PM_HIGH 0x1C44 Name Default Description me mme 32 h0 Bit63 bit32 of the 8 8 mono pattern The mono pattern is organized as following bit7 represents the top left first pixel of the pattern 7 6 5 4 13 2 1 10 15 8 23 16 31 24 39 32 47 40 55 48 63 56 Where bit is 1 the color represents the foreground color and if 0 means the background color with suitable pixel format BitBLT command queue start address
217. PIO GROUP1 322 InterruptfromPCMCIA 3 InterruptfromEXTPORT 34 InterruptfromCAMERA E SCs AT460A BI Developer s Manual Centrality 1 The INT_PENDING INT_IRQ_PENDING PENDING DSPO PENDING INT_DSP1_PENDING register all read only They only perform some combinational logic of interrupt inputs from each internal block To clear the interrupt user need to clear the interrupt in the block this generates the interrupt These registers will change as soon as the interrupt signal from the internal block changes 2 The INT_ FIQ_PENDING register are the result from INT PENDING amp INT RISC MASK 4 INT RISC LEVEL The INT DSP1 PENDING register are the result from INT PENDING amp INT DSP MASK amp INT DSP LEVEL So if user changes the value in other register the INT FIQ PENDING will also change This needs special care in interrupt routine If in interrupt routine user write the INT RISC MASK register to mask the interrupt from certain block the INT PENDING will change to 0 accordingly User can not read this register to determine the interrupt status Instead user should read INT PENDING register 3 The INT IRQ PENDING register are the result from INT PENDING amp INT RISC MASK amp INT RISC LEVEL The INT DSPO PENDING register are the result from INT PENDING amp INT DSP MASK amp INT DSP LEVEL So if user changes the value in other register the INT IRQ P
218. PIO105 0x328 A GPIO3 CTRL10 GPIO control for GPIO106 0 32 9 CTRL11 GPIO control for GPIO107 0 330 GPIO3_CTRL12_ GPIO controlforGPIO108_ 0x334 _______ GPIO3 CTRL13 ____ GPIO control for GPIO109 0x338 GPIO3 CTRLi4 GPIO control for GPIO110 0x33C ________ GPIO3_CTRL15_ GPlOcontroforGPIO111 1 0x340 ________ GPIO3 CTRL16 GPIOcontrolforGPIO112_ 0x344 _______ GPIO3 CTRLi7 GPIO control for GPIO113_ 0x348 ________ GPIO3_CTRL18 GPIO control for GPIO114 1 0x34C GPIO3 CTRLi9 ____ GPIO control for 0115 Oooo O C _____ 1 e e eo E _____ E OL 0x350 0x354 0x358 0 35 0 360 0 364 0x368 0x36C 0x370 0x374 0x378 0 37 0 380 0 384 GPIO group3pad enable 0 388 0 38 STATUS GPIO group3 Interrupt status for Centrality Communications Inc 88 AT460A BI Developer s Manual KE Centrality COMMUNICATIONS RIS 0x390 0x3FC 00 20 0x400 GPlOcontolforGPIO128 ______ 44 7 GPIO4 CTRL GPIO control for GPIO129 2 7 2 GPlOcontolforGPIO130 ____ ____ 7 GPIO control for GPIO131 2 0x410 ____ 7 GPIO4 CTRL4 GPIO control for 132 _____ 0
219. Port When set to 1 enabled uses timing defined by Bit 3 1 DO IS EN 190 Drive 0 Enable IORDY Sampling DO PFPW EN Drive 0 Enable Pre fetch and Post write 3 R W 00 EN 1 bO Drive 0 DMA Timing Enable Only When set to 1 enabled allows fast transfer timing only for DMA transfers PIO transfers use compatible timing When set to 0 disabled both DMA and PIO transfers use fast timing 4 R W D1 FT BS 1 bO Drive 1 Fast Timing Bank Select When set to 0 disabled uses 16 bit compatible timings to the Data Centrality Communications Inc 217 460 Developer s Manual Centrality Port When set to 1 enabled uses timing defined by Bit 7 5 01 15 ____ 150 ____ Drive 1 Enable IORDY Sampling 6 R W 01 Drive 1 Enable Prefetch and Posting 7 R W D1 DMAT EN 1 bO Drive 1 DMA Timing Enable Only When set to 1 enabled allows fast transfer timing only for DMA transfers PIO transfers use compatible timing When set to 0 disabled both DMA and PIO transfers use fast timing 9 8 RCT 290 Recovery Time RCT Defines the minimum number R W of clock periods NIRD NIWR are inaction between successive cycles 00 4 01 3 10 2 11 1 11 10 Reserved 13 12 290 IORDY Sample Point ISP Defines how many clock R W periods after NIRD NIWR is asserted on the IDE before IORDY is sampled 0
220. R5b type Changing from 1 to 0 generates a TRAN_END interrupt in the SD_INT_STATUS register Note The SD Host Driver can save registers in the range of 000 00Dh for a suspend transaction after this bit has changed from 1 to 0 1 Cannot issue command which uses the DAT line 0 Can issue command which uses the DAT line 2 R DAT_LINE_ACTIVE This bit indicates whether one of the DAT line on SD bus is in use 1 DAT line active 0 DAT line inactive Reserved 2 8 WT_TRAN_ACTIVE 1 bO This status indicates a write transfer is active If this bit is O it means no valid write data exists in the HC This bit is set in either of the following cases 1 After the end bit of the write command Centrality Communications Inc 168 AT460A BI Developer s Manual Centrality COMMUNICATIONS 9 RD_TRAN_ACTIVE 1 bO 10 R BUFF WT EN 11 R BUFF RD EN Centrality Communications Inc 169 2 When writing a 1 to CONTINUE REQ the SD HOST 0 register to restart a write transfer This bit is cleared in either of the following cases 1 After getting the CRC status of the last data block as specified by the transfer count Single or Multiple 2 After getting a CRC status of any block where data transmission is about to be stopped by a STOP AT BLK GAP REO During a write transaction a GAP EVT interrupt is generated when this bit is changed to 0 as a result of the STOP AT BLK GAP REQ bei
221. RD s used per line SCN_XSIZE SCN_HEND SCN_HSTART 1 31 13 1980 Reserved e Y Size for screen DMA LCD SCN YSIZE 0x108 Bit Name Default Description 12 0 SCN YSIZE 130 This value specifies the number of lines for the screen R W DMA Each line designates a segment of consecutive Centrality Communications Inc 130 460 Developer s Manual Centrality DWORD s with a skip in between SCN YSIZE SCN VEND SCN VSTART 1 3113 19850 e Skip value for screen DMA LCD 5 SKIP 0x10C Bit Name Default Description 12 0 SCN SKIP 13 hO This value specifies the number of BYTE s for the DMA R W address generator to skip in between lines of the screen DMA SCN SKIP ByteWidthOfScnFrameBuf SCN XSIZE 16 And the ByteWidthofScnFrameBuf must be a multiple of 16 31 13 1980 Reserved e Current DMA Address for the Screen Display LCD_SCN_DMA_ADDR 0x114 Writing any value to this register will activate the screen DMA Make sure this register is written last after all the other DMA registers are setup correctly already m Description SCN_DMA_START Write 1 to start the SCN layer DMA this bit is self cleared 313 __ e OSD Memory Base Register LCD OSDBASE 0x118 Name Default Description 3 m PIXEL OFFSET H 0 Pixel offset for OSD channel This pixel offset specifies R W which bits within the first DWORD specified by
222. RL 1 GPIO control for GPIO43 0x118 0x11C 0x120 0x124 0x128 0x12C Centrality Communications Inc 86 460 Developer s Manual KE Centrality COMMUNICATIONS GPIO1_CTRL12 control for GPIO44 GPIOi CTRLi3 control for GPIO45 GPIOi CTRLi4 GPIO control for GPIO46 _______ GPIOi CTRL 5 ____ GPIO control for GPIO47 _______ GPIOi CTRLi6 GPIO control for GPIO48 id _______ 7 GPIO control for GPIO49 ______ _______ GPIO1_CTRL18 ____ GPIO control for GPIO50 _______ _______ GPIO1_CTRL19 ____ GPIO control for GPIO51 0x150 ____ ________ GPIO1_CTRL20 for GPIO52 0x154 ____ GPIO1_CTRL21 ____ GPIO control for GPIO53 0x158 _______ GPIO1_CTRL22 ____ GPIO control for GPIO54 0x15C ____ _______ GPIO1_CTRL23 GPlOcontrolforGPlO55 0x160 7 GPIOt CTRL24 GPIO control for GPIO56 _______ 0x164 _______ CTRL25 for GPIO57 GPIOi CTRL26 GPlOcontrofor GPIO58 _______ GPIO1 CTRL27 GPIO control for 59 ___ GPIOi CTRE28 GPlOcontrolfor 6 GPIOi CTRL29 ____ GPIO control for GPIO61 GPIO1 CTRL30 j GPlOcontrofor GPIOG2 17 0 180 1 2 Reserved 0x184 _______ GPlOgrouptpadenabe
223. RL22 GPIO control for GPIO86 o25c GPIO2_CTRL23 j GPlOcontolforGPIO87 Centrality Communications Inc 87 AT460A BI Developer s Manual KE Centrality COMMUNICATIONS 0x260 GPIO2_ 24 GPIO control for GPIO88 0 264 9 2 CTRL25 ____ GPIO control for GPIO89 _______ 0 268 _______ GPIO2 26_ GPIOcontrolforGPIO90_ 0 26 GPIO2_CTRL27 GPIO control for GPIO91 0x270 _______ GPIO2 CTRL28 GPIO control for GPIO92 0x274 _______ GPIO2 CTRL29 ____ GPIO control for GPIO93 0x278 ________ GPIO2_CTRL30 GPlOcontroforGPIO94 _____ 0x27C _______ GPIO2 CTRL31 GPIO controlforGPIO95_ 0x280 aE f Reserved eee 0x284 GPIO2 PAD EN GPIO group2 enable ______ 0x288 x Reserved 0 28 GPIO2 INT_STATUS 0x290 0x2FC Reserved 0 300 6 GPIO control for GPIO96_ 0 304 GPIO control for GPIOO7 0 308 CTRL2 GPIO control for GPIO98 0x30C GPIO3 CTRL3 GPIO control for GPIO99 0x310 GPIO3 CTRL4 GPIO control for GPIO100 0 314 9 CTRL5 GPIO control for GPIO101 0x318 GPIO3 CTRL6 GPIO control for GPIO102 1 0 31 9 GPIO control for 010 0 320 CTRL8 GPIO control for 014 0 324 6 GPIO control for G
224. Remote Wake Up Enable 155 CREE es 16 SCHEDOVR Schedule Overrun Count R This count is incremented each time a Scheduler Overrun event is detected in the Host Controller 348 J Reseved 002 31 W HCRRESET Host Controller Reset e USB OTG System Interrupt Status Register USBOTG SYS INT STATUS 0x0088 Bit Name Default Description SORINT Schedule Overrun Interrupt 1 DONEINT 1 bO Done Register Interrupt When asserted this indicates that there are completed ETDs on the ETDDoneStatus Register Centrality Communications Inc 203 AT460A BI Developer s Manual Centrality e USB OTG System Interrupt Enable Register USBOTG SYS INT EN 0x008C Default Description Schedule Overrun Interrupt Enable 31 77 __ _____ ______ Reseved e USB OTG X Buffer Interrupt Status Register USBOTG HC X INT STATUS 0x0098 Bit Default Description 31 0 R XBUFFERnINT 32710 X Buffer lt n gt Interrupt When asserted indicates that the X buffer of ETD lt n gt requires servicing For the OUT case the buffer has been emptied by the host and requires more data to continue the transfer For the IN case the buffer has been filled by the host and requires emptying before it can continue Writing the asserted bit back to the register clears this bit e USB OTG Y Buffer Interrupt Status Register USBOTG HC Y INT STATUS 0x009C Bit Default
225. Reserved e 0502 FIFO Control Register LCD OSD2FIFO 0xC8 Bit Default Description 6 0 02 LO CHK 7160 Value for the low request watermark for 0502 FIFO If Centrality Communications Inc 125 AT460A BI Developer s Manual Centrality R W the FIFO is filled beyond this mark then the request stops If the FIFO is read below this point then the request becomes low level request 7 ___ HO Reserved 14 8 OSD2_MI_CHK 7140 Value the middle request watermark 0502 FIFO R W If the FIFO is filled beyond this mark then the request drops to low level request If the FIFO is read below this point then the request becomes high level request 16 SS 7120 Value for the high request watermark for the 0502 FIFO R W the FIFO is filled beyond this mark then the request 1 to high level request If the FIFO is read below this point then the request becomes critical 0502 REQ SEL 150 Selection of request generation method for OSD2 FIFO IR 1 Only high request and low request watermark are useful request value can be as 2 b00 and 2b 11 If the FIFO is read below high request watermark then the request becomes critical and if the FIFO is filled beyond low request watermark then the request stops As in critical request status the DMA bandwidth is a little lower using this mode will save some bandwidth 0 Normal request gene
226. SB1 1 core Voltage detector checks the voltage status of VBUS and represents result to output signals VBUSVALID SESSEND AVALID BVALID Charge discharge block provide pulse for SRP Three switch signals DP_PULL_UP DP PULL DOWN DM_PULL_DOWN control DP DM and external resistor connection Major transmission functions are determined by RX TX and suspend signals IDDIG and IDPULLUP decide the status of ID DRVVBUSC controls off chip charge pump device For the detail of the USB OTG transceiver please refer to the related TSMC document VDDA VSSA VBUSVALID AVALID detector VBus BVALID CHRGVBUS charge DISCHRGVBUS discharge DP_PULL_UP ae DP PULL DOWN PUDP DM PULL DOWN DP RX DP RX DM xs RX PDDM TX DAT TX SEO 15Kohm SUSPENDM Y TX_ENABLE_N IDDIG ID IDPULLUP DRVVBUS DRVVBUSC Figure 43 Block Diagram of USB OTG tranceiver 7 5 4 USB OTG Interface Registers Table 50 USB OTG Interface Register Mapping RISC Address Register Description lt 15 0 gt 0 0000 USBOTG TL HW MODE Hardware Mode Register 0x0004 USBOTG TL INT STATUS Core Interrupt Status Register 0x0008 USBOTG TL INT EN Core Interrupt Enable Register Centrality Communications Inc 188 460 Developer s Manual KE Centrality COMMUNICATIONS 0x0020 0x0034 0x003C 7 0x0080 USBOTG_HC_CONFIG Host Controller Configuration Register 0x0084 Reserved 0x0090 0x0094
227. SC 0x114 DSP 0x85 After each DMA is finished it will generate an interrupt bit in the corresponding bit in this register The RISC or DSP can read this register to check which DMA is finished If the RISC or DSP writes a 1 to that bit the interrupt bit will be cleared Bit Default Description Centrality Communications Inc 261 AT460A BI Developer s Manual Centrality 11 0 INT lt 11 0 gt 12 hO DMA interrupt bits R W 31 12 __ 7 2080 e DMA Interrupt Enable Register DMA_INT_EN RISC 0x118 DSP 0x86 There are two separate interrupt enable registers one for RISC and the other for DSP The DMA channel can only generate interrupts when the corresponding bits in this register and DMA_CH_DSP_EN are set correctly Name Default Description 11 2 lt 11 0 gt 1270 A interrupt enable bits R W 1 The DMA interrupt is enabled 0 The DMA interrupt is disabled 31 12 __ 2080 e Channel DSP Control Register DMA CH DSP CTRL RISC 0x11C This register is accessible to the RISC only Name Description A channel DSP control enable bits RAV 1 0 gt 1 The DMA channel is controlled by DSP 0 The DMA channel is controlled by RISC 31 12 209 e Channel Loop Control Register LOOP CTRL RISC 0 120 DSP 0 87 88 Just as the DMA WIDTH registers DMA INT EN register there are actually two separate DMA CH LOOP
228. SD_FIFO 0xA00 0xBFC Bit Name Default Description 31 0 FIFO_DATA Values in the OSD FIFO Can directly read or write values R W anywhere in the FIFO by specifying the corresponding Centrality Communications Inc 135 AT460A BI Developer s Manual Centrality Lo Ledes O 2 Push Pop OSD2 FIFO LCD OSD2 FIFO PUSH POP 0 00 Bit Default Description 31 0 PUSH POP If this register is read the first value in the OSD2 FIFO will be R W popped out i e the value read and the read index increased If this register is written then the value is pushed into the OSD2 FIFO i e the value is written to the end of the FIFO and the write index is increased Read Write 0502 FIFO LCD 0502 FIFO 0xE00 0xFFC Name Default Description um Values OSD2 FIFO Can directly read or write values anywhere in the FIFO by specifying the corresponding address 6 2 4 12 Palette amp Sequence RAM The 256 x 18 palette RAM is written or read directly by RISC Interface to access the specified address When as color palette each address contains RGB value for a color that has an index corresponding to the address The color component is 6 bits each specifying the 6 MSB of an 8 bit value For passive monochrome mode the palette is used for dithering sequence of frame rate control As the dithering sequence for one gray color is 32 bit the bottom 32 entries are used fo
229. Select Definition is the same as above R W 5 4 0 CS 2 b00 0 Clock Source Select Definition is the same as R W above CKO_1_CS 2 b00 CKO_1 Source Select Definition is the same as above R W 318 40 e Power Manager PLL1 Configuration Register PWR PLL1 CONFIG 0x28 Both PLL1 and PLL2 can be programmed to different frequencies User needs to make sure that when programming one PLL the Atlas 2 clock source has been switched to another PLL And only after the PLL is stable the clock source can be switched back NF 5 0 and NR 3 0 determine the clock frequency by the following equation Four NF NR X FiN NOTE NF 3 NO F lt 5 0 gt 2 NR R lt 3 0 gt 1 OD 1 Meanwhile the following constraints must be followed e 10MHz lt Frer lt 50MHz where Frer Fin NR when Fin is 12MHz NR has to be 1 500MHz lt lt 1000MHz where Fvco Fin NF NO NR e NF gt 6 3 NO For example if Fiy 12MHz and by default NR 1 NO 2 NF 21 so the PLL output will be 252MHz Bit Name Default Description 5 0 R W 6 h13 Feedback divider 0 63 9 6 R W R 3 0 4 hO Input divider 0 15 Note R has to be 0 when input frequency is 12MHz 10 R W 1b1 Output divider 1 b0 1 151 2 Note When OD is 1 b1 FOUT would have around Centrality Communications Inc 53 AT460A BI Developer s Manual Cen
230. Starting address in system memory where DMA will put fetch data to for e USB OTG ETD n DMA Buffer Transfer Pointer Register USBOTG ETD n BUF PTR 0x0A00 0xA1C If the DMA is paused due to the encounter of an AHB RETRY response and the SKIPONRETRY feature is enabled the current index into the buffer is stored in these registers so that the DMA knows where to re start the transfer The buffer transfer pointers are accessible only for debug purposes ETDO ETD7 Registers have same definition Name Default Description 31 si ETDDMABUFPTR 32 h0 ETD n DMA Buffer Transfer Pointer R W Stores the current index of the buffer when AHB RETRY response is asserted e USB OTG Endpoint n DMA Buffer Transfer Pointer Register USBOTG lt gt BUF PTR 0x0A80 0x A9C Centrality Communications Inc 214 460 5 Centrality If the DMA is paused due to the encounter of AHB RETRY response the SKIPONRETRY feature is enabled the current index into the buffer is stored in these registers so that the DMA knows where to re start the transfer The buffer transfer pointers are accessible only for debug purposes EPO EP3 OUT IN Registers have same definition Bit Name Default Description 31 0 R EPDMABUFPTR 3210 Endpoint n OUT IN DMA Buffer Transfer W Pointer Stores the current index of the buffer when AHB RETRY response is asserted 7
231. Transparency a pixel value is designated as transparent any pixel output from the BLT engine with this value is not written to the destination memory when enabled 4 Support Source Color Transparency a pixel value is designated as transparent any pixel from the source with this value will not affect the destination memory at the corresponding XY coordination 5 Support all the 256 raster operations 6 Support both Y direction of the 2D window while the given coordination is always at the window s top left corner 7 Support Command Queue in SDRAM and single command mode The BitBLT engine also has certain limitations as following 1 BitBLT Engine supports 8bpp 16bpp 32bpp pixel format and when 16bpp one pixel must be WORD 2bytes aligned and when 32bpp one pixel must be DWORD 4bytes aligned in SDRAM And when 8bpp it is not index mode as there is no color look up table palette in this design 2 The source and destination must share the same pixel format 3 The doesn t support right to left BLT which is the BitBLT engine always does BLT from the left border of the window to the right border This will be a problem only when the destination window is on the absolutely right side of the source window same y coordinate with overlap between them and in such situation SW must configure this BLT as two first Centrality Communications Inc 137 AT460A BI Developer s Manual Centrality SRCCOPY th
232. USP2 Receive Data PIPESTAT lt 2 gt USP2 Transmit Frame Sync X TFS 2 PDUWO4DGZ PIPESTAT lt 1 gt TXD lt 6 gt m e ume m m qw e 7778 e peres Set m qw arses verona General Purpose nTRST General Purpose IO TMS DCDO __ Pouwopcz General Purpose IO TDO DTRO __ 00 04062 General Purpose IO TDI DSRO m m omron m we m e eono caves Pon Tenemos m caves Pon n em memeem m m am f ne revere m m ames ia eren n eme eem S m m ww ___ newer e ww __ memes s em S E e m n em CS m qw em dzone qu em ___ o fe em SS qw wee ___ eso S qe pow fe wee zona E Centrality Communications Inc 349 460 Developer s Manual KE Centrality COMMUNICATIONS ww poemo worn _ Dm 6 X RESET PDUSDGZ Reset Input qw __ ____ wasser qw Pox08 06 fos uw __ gt __ casee pw qw re
233. UTO_PWR_CLR 1 bO Auto Power Clear 1 b0 The Vcc Power bit bit 4 of Power Control register is reset to1 bO when the card is removed 1 b1 The Vcc Power bit bit 4 of Power Control Centrality Communications Inc 244 460 Developer s Manual Centrality register Note that the same function happens when the auto power bit of the Power control register is set together with the Vcc power bit In this case the auto power clear bit need not be set When the card is removed the power to the socket is disabled even though the Vcc power bit is not reset to 1 b0 LED Activity Enable 1 b0 LED Activity disabled 1 b1 LED Activity enabled This bit allows the nled out signal to reflect any activity in the card Whenever PC card cycles are in the process to or from a card in either socket nled out will be active low The nled input from the IO PC card gives the activity level Invert Card IRQ Output 1 50 The card irq is active high 1 b1 The card irq is active low This bit changes the active high ISA type card IRQ level to an active low output that complies with the PCI bus requirements LED EN CARD IRQ PULL UP CTRL Pull up Control 1 b0 Pull ups on vs2 vsf cd2 and cd1 in use 1 b1 Pull ups on vs2 vsf cd2 and cd1 are turned off This bit turns off the pull up on the signals vs2 vs1 ncd2 and 1 Turning off these pull ups can be used in addition to suspend mod
234. W FIFO_DATA 3210 The FIFO data register which is the bottom of the TX_FIFO 8 7 4 3 UARTO RX_FIFO Registers NOTE The data flow of RX_FIFO is always from UART to RISC DSP DMA UART RX DMA I O MODE Register UART RX DMA IO CTRL RISC 0x120 DSP 0x50 m Default Description HO SEL DMA SEL 1 for mode 0 for DMA mode FLUSH 1 bO Flush the DMA receive FIFO in case the DATA LEN set at the peripheral side doesn t match the DWORD size set in the DMA control B pw qe o 5 4 RX ENDIAN M 2 b0 reserved ODE 316 UART RX DMA Length Register UART DMA IO LEN RISC 0x124 DSP 0x52 0x53 Bit Default Description 31 0 DATA_LEN 32 h0 The byte number of a DMA or I O transfer If set to R W zero the I O or DMA transfer works continuously until itis stopped UART RX FIFO Control Register UART_RX_FIFO_CTRL RISC 0x128 DSP 0x54 Name Default Description 1 m FIFO_WIDTH lt 1 0 gt 2 h0 Data width of FIFO 0 for byte 1 for word and 2 for R W DWORD 7 2 FIFO_THD lt 5 0 gt A threshold in byte to trigger an interrupt R W An interrupt is triggered when the count of data in the FIFO reaches the threshold 31 8 2 2 UART RX FIFO Level Check Register UART FIFO LEVEL RISC 0 12 DSP Centrality Communications Inc 312 AT460A BI Developer s Manual Centralit
235. WARNING C 160 Battery Warning Change HG 1 b0 A transition from high to low on bvd2 nspkr nled signal has not occurred since Centrality Communications Inc 231 AT460A BI Developer s Manual Centrality COMMUNICATIONS 2 R W RDY I this register was last read 1 b1 A transition on the bvd2 nspkr nled signal has occurred In memory PC card interface this bit is set to 1 b1 when the bvd2 nspkr nled signal changes from high to low indicating a battery warning condition This bit is reset to 1 bO whenever this register is read Ready Change 1 b0 A transition on the rdy nireq signal has not occurred since this register was last read 1 b1 A transition on the rdy nireq signal has occurred In memory PC card interface mode this bit is set to 1 b1 when a change has occurred in the signal input from the PC card In an I O interface this bit is always read as 1 bO This bit is reset to 1700 whenever this register is read Card Detect Change 1 b0 A transition on neither the ncd1 not the ned2 signal has occurred since this register was last read 1 b1 A transition on either the not the ncd2 signal has occurred This bit is set to 1 b1 when a change has occurred on the signals This bit is reset to 1 bO when this register is read 74 ano Reseved e M6730 Management Interrupt Configuration Register 6730 INT CONFIG
236. X FCE B X FOE B Figure 36 32 bit Data Fix latency Read BURST_READ 1 DWORD 55 1 BUS WIDTHz0 1 2 VARI 0 NOTE BUS_WIDTH 0 n 4 BUS_WIDTH 1 n 2 BUS WIDTH 2 n 1 T1 T2 L3 6 H 7 T8 X FCE B X FWE B X FA ITem EN ROME M Figure 37 32 bit Data Fix latency Write BURST_WRITE 1 DWORD_ACCESS 1 BUS WIDTHz0 1 2 VARI_ACC 0 NOTE BUS _WIDTH 0 n 4 BUS_WIDTH 1 2 Centrality Communications Inc 159 AT460A BI Developer s Manual 2 valiq ye 1 Valid address 2 721 T8 17 72 TI gt Figure 38 32 bit Data Fix latency Write BURST_WRITE 0 DWORD_ACCESS 1 BUS WIDTH 1 VARI_ACC 0 NOTE Centrality Communications Inc 160 AT460A BI Developer s Manual Figure 39 16 bit Data Variable latency Read BURST_READ 0 DWORD_ACCESS 0 BUS_WIDTH 1 VARI_ACC 1 NOTE X FD from ROM SRAM device will be latched 1 T clk pci ahead of X FOE B rising edge Centrality Communications Inc 161 460 Developer s Manual Centrality Figure 40 16 bit Data Variable latency Write BURST_WRITE 0 DWORD_ACCESS 0 BUS_WIDTH 1 VARI_ACC 1 NOTE After T10 ROM SRAM interface will detect the X FRDY B pin When it is low the write can be finished T7 T10 1 2 4 7 4 SDIO Host Controller 7 4 1 Overview SDIO SD Host Controller is a Host
237. YNC is low 0 Initial value of the 1 2 clock at the beginning of VSYNC is high 27 SYN RESET 1 When input PIXCLK is divide by 2 the initial value of R W the 1 2 clock is reset at the beginning of VSYNC This is mainly used for external TV encoder 27MHz clock input 0 When input PIXCLK is divide by 2 the initial value of the 1 2 clock is not reset at the beginning of VSYNC 3128 0 Reseved 6 2 4 6 Alpha Blending amp Color Key Control Registers These registers are used for OSD and OSD2 alpha blending and color key functions Alpha blending is a means to blend two layers together The ratios between two layers are defined as below And for the color key function two registers CKEYB and CKEYS are used to specify a color key range For OSD and 0502 color key registers if a color of OSD or OSD2 is between the and the CKEYS it will be transparent and the pixel from the main display layers will be shown instead While for SCN color key registers if the color of SCN is in the range defined by CKEYB and CKEYS the color is transparent and the pixel from the OSD layer will be shown instead The ratios between main display layer and the alpha blending layer are as follows Alpha value 0000 10096 main display layer value Alpha value 0001 15 16 main display layer value 1 16 alpha blending layer value Alpha value 0010 14 16 main display layer value 2 16 alpha blending layer value Alph
238. _START 0x14 to start the DRAM initialization bus sequence Another 200 us settling time is required by DRAM to stabilize its internal clocks When DRAM is ready the bit 0 of MEM_START will be set to 1 One can read this bit to check whether DRAM is ready Table 11 RISC Interface Register Address Mapping RISC Register Description Address lt 11 0 gt 0x0000 MEM_TYPE Memory type and configuration register 0x0004 MEM_TIMING Memory timing register 0 0008 _____ MEM_POWER Memorypowermanagement 0x000C_ DRAMmoderegister Others Reserved e Memory Type and Configuration Register MEM TYPE RISC 0 0 Default Description 7 7 DRAM_TYPE 8801 00000001 gt 1 16 R W 00000010 gt 8Mx8 00000100 gt 16Mx8 00001000 gt 32Mx8 00010000 gt 64Mx8 00100000 gt 8Mx16 01000000 gt 16Mx16 10000000 gt 32Mx16 others reserved 8 R W DRAM MODULE 0 gt 1 module 1 gt 2 module 1 gt 32 bit data wide 10 EN LARGE PAGE 0 Disable large page BA map to highest R W address bits 1 gt Enable large page BA map to the middle of Row and Column address bits 1 gt DDR qe me 00 1 gt mobile DRAM e Memory Timing Register MEM TIMING RISC 0x4 Centrality Communications Inc 34 460 Developer s Manual Centrality Default Description REFRESH_MODE 2 b01 00 gt one r
239. ___ DSP DMA Mode Register DSP DMA MODE RISC 0x4 DSP 0x1C01 Bit Default Description STATUS 1 bO 0 DMA done 1 DMA busy Write 1 to this register will start the DMA automaticall 2 1 TYPE 210 00 R W 01 DMA for PM 10 DMA for DMX 11 DMA for DMY 3 R W 1 bO 0 DMA from SDRAM to SRAM 1 DMA from SRAM to SDRAM 154 __ 1280 Kw Pe R W em LLL R W 3118 145 e DSP DMX Start Address Register DSP DMX START ADD RISC 0 8 DSP 0x1C02 0x1C03 Name Default Description START_ADD 32 h0 DSP DMA start address DSP PM Start Address Register 05 PM START ADD RISC 0 DSP 0x1C04 0x1C05 Bit Name Default Description Centrality Communications Inc 25 AT460A BI Developer s Manual Centrality START ADD 3210 DSP DMA PM start address R W DSP DMA Length Register 05 LENGTH RISC 0x10 DSP 0x1C06 0x1C07 Bit Default Description 15 0 X_LEN 1610 DSP X Length R W 31 16 16 h0 DSP DMA Y Length R W e DSP Memory Start Address Register DSP_MEM_START_ADD RISC 0x14 DSP 0x1C08 0x1C09 Name Default Description START_ADD 32 h0 DSP DMA SDRAM start address DSP DMA Pitch Register DSP_DMA_PITCH RISC 0x18 DSP 0x1C0A 0x1COB Bit Name Default Description 31 0 PITCH 32 h0 2 D DMA Pitch i e the leng
240. _____ 0x474 GPIO4_CTRL29 GPIOcontrolforGPIO157_ 0x478 GPIO4_CTRL30 GPIO control for GPIO158 1 0x47C Ox480_ PAD EN G10 grouptpad enable _______ 0x488 1 2 SES 0x48C ro GPIO4_INT_STATUS group4 interrupt status for RISC 0x490 Ox4FC 0x500 GPlOcontolforGPIO160 0x504 7 GPIOS CTRL GPIO control for GPIO161 0x508 2 GPlOcontolforGPIO162 X GPIO5 CTRL3 GPlOcontolforGPIO163 0x510 GPIOS CTRL4 GPIO control for GPIO164 0x514 GPIO5_CTRL5 GPIO control for GPIO165 0x518 GPIO5_CTRL6 GPIO control for GPIO166 GPIO5 CTRL7 GPlOcontrlforGPIO167 520 GPIO5 CTRL8 GPlOcontolforGPlO168 0x524 7 GPIO5 CTRL9 GPlOcontrlforGPIO169 _____ Centrality Communications Inc 89 AT460A BI Developer s Manual Centrality 0x528 7 GPIO5 CTRLIO GPlOcontrlforGPIO170 0x52C_ X j GPIO5 CTRLM GPIO control for GPIO171 2 0x530 GPIOS CTRLi2 ___ GPIO control for 1 172 0x534 GPIO5 CTRLi3 GPIO control for GPIO173 0x538 GPIO5 CTRLi4 GPIO control for GPIO174 0x53C GPIOS CTRLi5 GPIO control for GPIO175 0 540 CTRL 6 GPIO controlforGPIO
241. a the data and echoed address is saved in CODEC AC97 STATUS 0 AC97 CODEC delivers no status data Before issuing read command to AC97 CODEC User needs to write 1 b1 to clear the status AC97 SLOT12 VLD Slot 12 contains valid data 1 AC link slot12 contains valid data in current input frame the data will be saved in register CODEC SLOT12 DAT 0 Slot 12 contains no valid data in current input frame User needs to write 1 b1 to this register bit to clear this status 312 sobo e CODEC 97 510112 Data Register CODEC SLOT12 DAT 0x30 Bit Default Description 15 0 CODEC_SLOT12 1670 97 slot12 read back data 6 dieho e CODEC 97 Auxiliary Output Slot Selection Register CODEC_TXSLOT_EN 0x34 Default Description Bit 6 0 CODEC TXSLOT EN 7 hO AC97 auxiliary output slot selection only one slot R W allowed to be valid 0 Slot output is disabled 1 Slot output is enabled Bit 0 output frame Slot5 selection Bit 1 output frame Slot6 selection Bit 2 output frame 51017 selection Bit 3 output frame Slot8 selection Bit 4 output frame Slot9 selection Bit 5 output frame Slot10 selection Bit 6 output frame Slot11 selection 317 25 Centrality Communications Inc 296 460 Developer s Manual Centrality e CODEC 97 Auxiliary Input Slot Selection Register CODEC RXSLOT 0x38 Default Description CODEC RXSLOT EN 7 hO AC97 aux
242. a Interface DMA_CHx_BE lt 3 0 gt DMA DMA_CHx_RQ lt 1 0 gt DMA Controller Interface RISC I F Control DMA CS B 15 0 Interface DSP I F DMA RD_B DMA_WT_B o Centrality Communications Inc 251 AT460A BI Developer s Manual Centrality Figure 48 DMA Controller Diagram1 The DMA controller consists of 12 independent DMA channels Each channel is allocated to a different function described in the figure below Priorit CAN Bus input High CAN Bus output Video Camera input Reserved NAND Flash input output Reserved CODEC input CODEC output UART USP CODEC input UART USP CODEC output 10 UART USP CODEC input 11 UART USP CODEC output Low Channels 0 1 are shared between CANBUSO CANBUS1 Channels 8 11 are shared between following devices ports UARTO USPO input output USP1 input output USP2 input output USP3 input output SIB input output USP4 input output USP5 input output AUX input output Channel 8 10 can be configured as the input DMA channels for any of the above devices ports Channel 9 11 can be configured as the output DMA channels for any of the above devices ports NOTE Some PCI devices in Atlas Il also have their own DMA channels which are controlled by the DMA Controller Please refer to the PCI Subsystem section for more details Each peripheral has its own FIFO for DMA The user can setup the FI
243. a memory read from the PC Card socket to the Atlas II This output goes active low to indicate a memory write from the Atlas II to the PC Card socket In Memory Card Interface mode this input indicates to the Atlas II that the card is either ready or busy In I O card Interface mode this input indicates a card interrupt request This output is low for normal operation and goes high to reset the card To prevent reset glitches to a card this signal is given tristate enable unless a card is seated in the socket card power is applied and the card s interface signals are enabled 7 7 6 CF Card Connection Example The Atlas II PCMCIA interface is designed to provide a glueless interface between CompactFlash CF or PC card and Atlas II It can support a 68 pin type II PCMCIA card and 50 pin CompactFlash card When connecting to CompactFlash card a PCMCIA type passive adapter should be used to realize the conversion Centrality Communications Inc 223 AT460A BI Developer s Manual LS Centrality 2 COMMUNICATIONS X PC D X PC ADD 10 0 X PC REG B X PC CE B 2 1 X PC OE B X PC WE B X PC IORD B X PC IOWE B X PC B X PC WAIT B X PC 101516 B X PC RESET z X SPKR B gt X_PC_STSCHG_B 5 3 X FC CD B 9 X PC VS 2 1 PCMCIA VCC BE NEN D 15 0 A 10 0 nREG nCE 2 1 nOE nWE nlOR nlOW RDY nWAIT 101516 BVD 2 BVD 1 nCD 2 1
244. a value 0011 13 16 main display layer value 3 16 alpha blending layer value Alpha value 1101 3 16 main display layer value 13 16 alpha blending layer value Alpha value 1110 2 16 main display layer value 14 16 alpha blending layer value Alpha value 1111 10096 alpha blending layer value e OSD and OSD2 Alpha blending control register LCD OSDALPHA 0x88 Bit Name Default Description 3 0 ALPHA VAL 4 h0 4 bit planar alpha value to blend all pixels on OSD layer R W to SCN layer This value is used or not will be selected Centrality Communications Inc 119 AT460A BI Developer s Manual Centrality SSS BB register OSD_BPP OSD data format for alpha blending 00 2bit pixel 2 bit index color 01 4bit pixel 4 bit index color 10 8bit pixel 8 bit index color when OSD_ALPHA_SEL 0 or 4 bit alpha 4 bit index color when OSD_ALPHA_SEL 1 11 16bit pixel 16 bit RGB 5 6 5 color when OSD_ALPHA_SEL 0 or 4 bit alpha 4 bit Red 4 bit Green 4 bit Blue when OSD ALPHA SEL 1 OSD ALPHA SEL 1 Select the valid alpha value as the 4 bit alpha data on from the 8bpp or 16bpp image data only valid for 8bpp or 16bpp data format 0 Select OSD_ALPHA_VAL the valid alpha value when the data format is 4bpp 8bpp or 16bpp Remark when OSD BPP is 4bpp this bit must be zero which is only the OSD ALPHA VAL will be used as the alpha value and if not
245. able register 3 To specify where in the PCI space a memory window is mapped start and end addresses are specified A memory window is selected whenever the appropriate bit is set and the following conditions are true The PCI address is greater than or equal to the appropriate System Memory Map Start Address register The PCI address is less than or equal to the appropriate System Memory Map End Address register The System Memory Map Upper Address register is equal to the upper PCI address 4 Start and End addresses are specified within PCI address bits 23 12 This sets the minimum memory window size to 4 KBytes Memory windows are specified within the PCI memory address space Bit Name Default Description 7 0 R W SA lt 19 12 gt 870 Start Address lt 19 12 gt This register contains the least significant byte of the address that specifies where in the memory space the corresponding memory map will begin Memory accesses that are equal or above this address and equal or below the corresponding System Memory Map End Address will be mapped into the memory space of the corresponding PC card M6730 System Memory 0 4 Start Address High Register 6730 SM 0 4 SAH Index 0x11 0x19 0x21 0x29 0x31 There are five separate System Memory Map Start Address High registers each with identical fields Name Default Description 3 0 RET SA lt 23 20 gt 4 hO Start Address 23 20 This
246. ace Memory Bus Figure 49 DMA Controller Block Diagram The DMA controller serves multiple blocks and arbitrates between the different blocks that need to access external memory Each DMA channel has a two bit request level In addition they all have an inherent priority as shown above so that when two channels have the same request level the channel with the higher priority will win The priority level can be programmed by the RISC or determined by FIFO fullness depending on the channel Arbitration is a 3 step process 1 First requests for each level are determined by the request signals and whether a DMA is set up for that channel 2 Second each level goes to a priority encode to come out with whether there is a request for that channel and a channel to service 3 Third the channel for the highest valid request will be serviced When the DMA controller detects a request with a higher arbitration priority based on the above protocol than the current one it will interrupt the current DMA store the location of the last access i e where the stop occurs and then proceed to service the new request The interrupted request can resume at where it stopped after its arbitration priority once again becomes the highest This scheme can be repeated for all the channels active at the same time 8 3 2 2 DMA FIFO Interface The FIFOs are a block of SRAM on chip with a read pointer chasing a write pointer one may never pass
247. ad write transfer when this bit is declared 1 R W FIFO RESET 1 bO Internally link to FIFO START INI Set to 1 to stop the FIFO and reset the FIFO internal status including the relevant interrupt status Set to 0 in normal operation 312 ____ ______ Reseved Auxiliary CODEC TXFIFO Status Register CODEC TX AUX FIFO STS 0xB94 This register indicates the auxiliary TX FIFO status Description TX_AUX_FIFO_FULL Auxiliary TX FIFO full status 1 TX FIFO is in full state 0 TX FIFO is not in full state It indicates the current TX FIFO full status Once the FIFO status changes the status bit is cleared automatically TX_AUX_FIFO_EMPTY Auxiliary TX FIFO empty status 1 TX FIFO is in empty states 0 TX FIFO is not in empty states It indicates the current TX FIFO empty status Once the FIFO status changes the status bit is cleared automatically TX_AUX_FIFO_OFLOW TX FIFO overflow status 1 TX FIFO overflow takes place 0 TX FIFO is not overflow User can write 1 b1 to clear the register bit after the TX FIFO overflow takes place TX_AUX_FIFO_UFLOW TX FIFO underflow status 1 TX FIFO underflow takes place 0 TX FIFO is not underflow User needs to write 1 b1 to clear the register bit after the TX FIFO underflow takes place 1280 e AUX CODEC TXFIFO Interrupt Enable Register CODEC TX FIFO INT 0xB98 Name Default Description 1 Aux TX FIFO full interrupt is enable
248. address Set memory type to DMX DMY While Data to be transfer is not empty rebooting Write 1 to REBOOT adaress transfer the data The ISA IDMA control registers are located in the DSP Shared Memory started from 0 4800 0000 in RISC address space Table 5 DSP ISA IDMA Control Registers RISC Address Width Description 16 DSP_SHARED_MEMORY 8 Destination memory 0x0 PM 0x1 DMX 0 2 0x3 reserved MADDR MTYPE MDATA DSP_SHARED_MEMORY 16 For PM One 24 bits instruction takes two cycles to transfer At the first cycle transfer the lower bytes of code 15 0 at the second cycle transfer the high byte of code 8 h0 23 16 For DMX and DMY transfer 16 bit data in REBOOT DSP_SHARED_MEMORY 24 A write will reboot the processor core and force DSP starting execution at PM 0x0 Note BDMA and ISA part won t be 3 2 3 DSP IO Interface It s different with Atlas I that the space no longer occupies the overlaid DMX space Instead it uses the independent IO BDMA port The DSP core supports an additional external memory space called I O space This space is designed to support simple connections to peripherals such as data converters and external registers or to bus interface ASIC data registers I O space supports 2048 locations of 16 bit wide data The lower eleven bits of the external address bus are used the upper three bits are undefined The I O space also has four dedica
249. ade off between high performance and high code density The ARM926EJ S processor includes features of efficient cod execution of Java byte codes providing Java performance close to JIT but without the associated code overhead The ARM926EJ S processor has a Harvard cached architecture version 5TEJ and provides a complete high performance processor subsystem including the MMU and AHB bus unit The ARM926EJ S is a synthesizable core that allows user to configure the cache size between 4KB and 128KB But ARM926EJ_1616 is the hardened version with fixed 16KB l Cache and 16KB D Cache 2 2 2 Address Mapping The ARM926EJ has a 32 bit address bus which will be translated by the RISC interface into either access to cacheable data memory non cacheable data memory or memory mapped registers Bits lt 26 0 gt of the address are used as the physical address bus Centrality Communications Inc 14 AT460A BI Developer s Manual Centrality address mapping registers must be inside the RISC interface The RISC interface will responsible for all address decoding before it issues the command cycles to the system The boot ROM should have instructions about how to initialize these address mapped registers The programmer needs to provide the system with the initialization routine e ROM amp PCMCIA The address mapping is defined starting from CPU reset vector 0x0000 0000 There is 512MB set aside for ROM However not all
250. aeeeaaeeeaeeneas 10 ROM SRAM Interface Pin Description eene 10 RISC IO access PCI IO access address 10 RISC IO access PCI IO access width translation 2 10 ROM RISC IO Register Mapping 10 SDIO Host Interface Pin 10 SDIO Host Controller Register Mapping ccsecceseeeeeseceeeeceeneeceneeceneeeseeeteeesneeeseeeeeene 10 Definition of Transfer 10 Defintion of Response 10 Response Bit Definition for Each Response 10 Relation between Transfer Complete and Data Timeout 10 Relation between Command Complete and Command Timeout Error 10 Relation between Command CRC Error and Command Timeout 10 Relation between Auto CMD12 CRC Error and Auto CMD12 Timeout Error 10 Relation between Auto CMD12 CRC Error and Auto CMD12 Timeout Error 10 Maximum Current Value Definition 10 USB Interface Pin enne 10 USB OTG Interface Register 10 ROM SRAM Interface Pin Description 0 41
251. ags the INT DSPO PENDING This is a read only register Bit Name Default Description 31 0 DSP0 lt 31 0 gt 3270 DSP Interrupt pending bits 0 No interrupt pending 1 Interrupt pending e Interrupt Controller RISC Mask Register INT_RISC_MASK RISC 0x0010 There are two interrupt mask registers one for RISC INT_RISC_MASK and the other for DSP INT DSP MASK Each mask register contains one mask bit per pending interrupt bit totally 32 Mask bits serve two purposes First they allow periodic software polling of interruptible sources while preventing them from actually causing an interrupt Second they allow the interrupt handler routine to prevent interrupts of lower priority from occurring while still maintaining a list of pending interrupts that may have occurred previously or during the servicing of another interrupt The INT RISC MASK INT DSP MASK is not initialized at reset a question mark indicates that the values are unknown at reset The following table shows the bit locations corresponding to the 32 separate interrupt mask bits Bit Default Description 31 0 lt 31 0 gt 32 h0 RISC interrupts mask bits W R 0 Pending interrupt is masked from becoming active 1 Pending interrupt is allowed to become active The IP 11 IP 15 IP 24 IP 26 IP 27 IP 29 for RISC DSP is MUXED with several interrupt IP11 PCMCIA EXT IP15 Camera 24 LCD Controller LCD 2D 26 Se
252. akes both DMY and GPS SRAM 317 d 250 e DSP Start Address Register 05 DMY START ADD RISC 0x24 DSP Ox1COE 0x1COF Bi Default Description START ADD 32 0 DSP DMA DMY start address R W e DSP FSM Reset Register DSP_FSM_RST RISC 0x44 DSP 0x1C41 T Name Description __ 314 __ Ci 2870 Reserved e DSP System Clock Ratio Register DSP DIV RISC 0x48 DSP 0x1C42 Name Default Description CLK_RATIO 260 0 DSP System clock ratio is 1 1 DSP System clock ratio is 2 2 DSP System clock ratio is 4 3 DSP System clock ratio is 8 31 2 __ 300 Reserved 2 2 DSP IO Mode Register DSP IO MODE RISC 0x4C DSP 0x1C43 Bit Name Default Description O R W IO BDMA 1 bO 0 Normal IO Mode or BDMA Mode 1 Fixed Address BDMA Mode 31 1 __ 1310 DSP BDMA Start Address DSP BDMA S4A RISC 0x50 DSP 0 1 44 Default Description BDMA_SA 12 b0 Start Address of Fixed Address BDMA Mode RW 31 12 __ 200 Centrality Communications Inc 27 460 Developer s Manual Centrality e DSP Interrupt from RISC Register DSP_INT_FROM_RISC RISC 0x60 DSP 0x1C60 Description 14 0 MSG TO DSP Message bit to DSP with the interrupt operation RISC writes to this register will interrupt the DSP R W 15 INT_DSP 1 hO The interrupt status bit DSP writes 1 to this bit will clear the int
253. ality 8 7 1 Overview There are 3 dedicated UARTs Universal Asynchronous Receiver Transmitter and 5 USPs Universal Serial Port in Atlas II UARTO full UART with DMA and Hardware flow control USP1 5 Universal Serial Port UART6 amp 7 UART without or Hardware flow control UARTO supports the following features 5 6 7 or 8 bits per character 1 or 2 stop bit detection and generation Internal baud rate generator and separate receiver clock input two clock divisor for more flexible clock division Modem control functions Transmit receive line status and modem control interrupts Line break detection and generation Internal loop back diagnostic functionality ndependent 64 BYTE transmit and receive FIFOs for DMA UART6 amp 7 are the same as UARTO except that they do not support Modem control and DMA functionality 8 7 2 Pin Description The following table shows the UARTO input output pins Table 78 UARTO Pin Descriptions Direction Description RTS Input Receive Data input Indicator DCD DSR input Data Set Ready CTS Each pin of UARTO is muxed with other functions Please refer to the section of Pin Sharing for detail information About The PIN connection of UARTO to external device please refer to the RS232 specification NOTE UART687 only have 2 pins TXD and RXD 8 7 3 Functional Description The
254. am eene nennen enne 10 Figure 48 DMA Controller Diagram 1 nennen mener nre n nennen nnns 10 Centrality Communications Inc 6 AT460A BI Developer s Manual Centrality COMMUNICATIONS Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 Figure 80 Figure 81 Figure 82 Figure 83 Figure 84 Figure 85 Figure 86 Figure 87 Figure 88 Figure 89 DMA Controller Block Diagram nennen nnns 10 FIFO Request Level Checkpoints 10 DMA Configuration 10 22D ee eb ted 10 2 D DMA Wrap Around X length gt DMA 10 DMA address change if X 0 10 Flash Controller Block 10 Block Diagram of Video Input 10 16 bit RGB Data Forral uic deret Pee ue 10 Contraction in Bayer RGB Mode with 1 2 Ratio in Row and 10 Contraction
255. and the outside TV encoder chip drives HSYNC and VYSNC 1 Current field is the even field of a frame 0 Current field is the odd field of a frame 3113 21h0 Reserved 0 e Screen control for external TV encoder register LCD SCN TVFIELD 0x84 Bit Name Default Description 10 0 SCN_VEND1 17 0 SCN_VEND1 Vertical End Position line number for R W the active TV display 170 Reserved 5 22 12 SCN_VSTART1 17 0 SCN_VSTART1 Vertical Start Position in line number R W for the active TV display Centrality Communications Inc 118 AT460A BI Developer s Manual Centrality 23 __ _____ 24 1 Also use SCN_VSTART1 and SCN_VEND1 values R W to control the active Screen 0 SCN_VSTART1 and SCN_VEND1 are not active This is used when doing TV 2 fields mode define the EVEN field position refer to the figure above 25 HALF_PIXCLK 1 The input PIXCLK when external TV encoder R W drives the PIXCLK or the clock after the divider when Atlas drives the PIXCLK is divided by 2 after which it is used as the internal PIXCLK This is mainly used for external TV encoder 27 2 clock 0 The frequency of internal PIXCLK remain unchanged 26 INI HALF PXCLK The bit sets the reset value of initial value of the 1 2 R W clock This is mainly used for external TV encoder 27MHz clock input 1 Initial value of the 1 2 clock at the beginning of VS
256. anges in the rdy nireq signal input from the PC card Card Detect Enable 1 b0 Card Detect Change Management Interrupt disabled 161 If Card Detect Change bit is1 b1 management interrupt will occur When this bit is set to 1561 a management interrupt will occur when the Card Status Change register bit 3 is set to 1 b1 This allows interrupts to be generated on the level changes on the ncd1 or ncd2 inputs from the PC card Management IRQ 4 b0000 IRQ disabled 4 b0001 Reserved 4 b0010 Reserved 4 b0011 IRQ3 ninta 4 b0100 4 nintb 4 b0101 IRQ5 nintc 4 b0110 Reserved 4 b0111 IRQ7 nintd 4 b1000 Reserved 4 b1001 IRQ9 4 b1010 IRQ10 4 b1011 IRQ11 4 b1100 IRQ12 4 b1101 Reserved 4 b1110 IRQ14 4 b1111 IRQ15 These bits determine which interrupt will be used for a card status change management interrupt M6730 Mapping Enable Register M6730 MAP EN Index 0x06 Default Description Memory Map0 Enable 1 b0 Memory Window Mapping registers for Memory Window 0 disabled 1 b1 Memory Window Mapping registers for Memory Window 0 enabled When this bit is 1701 the Memory Window Mapping registers for the memory window 0 are enabled and the controller will be able to Centrality Communications Inc respond to memory accesses in the memory 233 AT460A BI Developer s Manual Centrality space defined by those registers
257. ardware reset RESET_B The counter may be written by the RISC at any time It is recommended that the RTC_COUNTER to be protected by the MMU protection mechanisms Bit Name Default Description 31 0 lt 31 32 h0 Real time Counter value R W RTC Alarm Register RTC ALARM 0x0004 Centrality Communications Inc 47 AT460A BI Developer s Manual Centrality real time clock alarm register is 32 bit register that is accessible by the RISC In each cycle of the divided real time clock this register is compared to the RTC_COUNTER If the two matches and the enable bit ALE is set then the alarm bit in the RTC status register is set Bit Name Default Description 31 0 AL lt 31 0 gt 32 h0 Alarm value R W RTC Status Register RTC_STATUS 0 0008 Writing ones to AL and HZ will clear them Bit Name Default Description 0 R W AL 1 bO RTC alarm detected 0 No alarm has been detected 1 An alarm has been detected RTNR matches RTC ALARM 1 R W 1 bO 1 Hz rising edge detected 0 No rising edge has been detected 1 A rising edge has been detected 2 R W ALE 1 bO RTC alarm interrupt enable 0 RTC alarm interrupt is not enabled 1 RTC alarm interrupt is enabled 3 R W 1 bO 1 Hz interrupt enable 0 The 1 Hz interrupt is not enabled 1 The 1 Hz interrupt is enabled 314 ____ 2870 Reserved e RTC Division Register RTC DIV 0
258. are properly Then it will go to a loop to copy the system code page by page 8 4 6 Pin Description The NAND Flash interface shares pins with Video Input Port or ROM interface User can use Mode Configuration Pins to choose pin sharing method in system PCB design Table 66 NAND Flash Interface Signal Descriptions Pin Name Direction Description Centrality Communications Inc 263 AT460A BI Developer s Manual Centrality DF WE B ___ Output Write Enable O DF RD B Read Enable DF RY BY Ready Busy output Schmitt Triggered DF CS lt 3 0 gt Chip Enable 8 4 7 NAND Flash Interface Registers Table 67 Flash Interface Register Mapping RISC Address Register Description lt 11 0 gt 0x00 Reserved SOS OXOC ______ ADD NUM ___________ byte number for NAND Flash address SM LOW ADDR Low 4 bytes of address to NAND Flash 0x18 SM HIGH ADDR High bytes of address to NAND Flash needed only by NAND Flash more than 256MB OxXiC SIZE ________ size of NAND Flash SM INT EN Interrupt mast register SM CTRL Control Register of NAND Flash SM ECC SET Hard ware ECC set register SM ECC 1 Hard ware ECC result store register 1 SMFIFOOP ResetandstartbitfoFlFO OxF18 SM FIFO DATA RISC read FIFO from this register Flash Wait State Register SM WAIT 0x04 SM ECC AREA2 Hard ware ECC result store register
259. aring Controller Registers Table 23 RSC Register Mappin RISC Address Register Description lt 11 0 gt 0x0000 ________________ 0 0004 RSC MUX RSC Pin Multiplex Register 0x0008 RSC DMA MUX RSC DMA Multiplex Register 0 000 RSC_ROMPAD MUX RSC ROM Pad Multiplex Register Others ____ Cid Reserved Pin Multiplex Register PIN 0x4 Centrality Communications Inc 81 460 Developer s Manual Centrality Bit Name Default Description 0 R W CAM_EN 1 bO Video Input Port enable 1 Enabled Video Input Port takes the pins 0 Disabled NAND Flash takes the pins 1 R W CODEC EN 1 bO CODEC interface enable 1 Enabled CODEC takes the pins 0 Disabled USP takes the pins 3 2 R W SD lt 1 0 gt 1 bO SD interface enable 2 b00 USP takes the pins 2 b01 SDIO takes the pins 2 b1X PCMCIA lt 25 20 gt takes the pins 54 L Zboo 6 R W USP lt 0 gt 160 USP6 enable 1 Enabled USP6 takes the pins 0 Disabled USP2 takes the pins 7 R W USP lt 1 gt 750 USP7 enable 1 Enabled USP7 takes the pins 0 Disabled USP3 takes the pins 11 8 NAND_CS lt 3 0 gt 45000 NAND Flash Chip Select enable R W 1 Enabled NAND Flash takes the CS pin 0 Disabled ROM takes the CS Pin 31 12 __ 2090 e DMA Multiplex Register RSC_DMA_MUX 0x8 DMA Channel 8 amp 10 are only for DMA read pe
260. arity is not reset at the beginning of frame 1 Invert FMOD SCN ACTIVE signal before output R W 0 Do not invert FMOD SCN ACTIVE signal 1 Output FMOD signal to the L_BIAS Pin R W 0 Output SCN_ACTIVE signal to the L_BIAS Pin 31 11 6 2 4 5 YUV Output Registers These registers allow the support of YUV output instead of RGB output mainly targeted towards video encoders The first set of registers contains the coefficients to use to convert the RGB outputs to YUV outputs The conversion is a 3x3 matrix multiplication as follows Y C11 C12 C13 R U C21 C22 C23 V C31 C32 C33 B Note that this multiplication is a signed multiplication Thus the coefficients must be 8 bit signed values In addition the RGB values may have to be turned to signed values by inverting the MSB of the each Centrality Communications Inc 116 AT460A BI Developer s Manual Centrality component Also the YUV output is initially signed value so it may be necessary to invert the MSB again to output unsigned values These invert options and other control signals for the YUV output are in the YUV_CTRL register The coefficients format is as following Bit7 the sign bit Bit6 0 the fraction bits e RGB to Coefficient 1 LCD_RGB_YUV_COEF1 0x74 Bit Name Default Description 23 16 COEF1 8 hO Coefficient 11 for the RGB to YUV conversion matrix This value should be an 8 bit signed value Co
261. ash IDE E E E ID ID 10 The priority of the above functions is as following e f GPIO have control over these pins all others can not control the pin e Else ForX 3 0 NAND_CS lt 3 0 gt RSC_PIN_MUX register determines either ROM or NAND Flash control these pins For X_FRDY_B since this pin is open drain in the corresponding device it be used with ROM and IDE co existing o For other pins they will be used by the corresponding device e EXT Part 2 Part 3 Pin Mux Pin Name EXT Port PCMCIA XPCCDB1 DJGPlOgroup3offset22 XPCCDBO GPlOgroup3offset21 P P P GPIO group3 offset 19 X X PC WAIT B EXT RDY B GPIO group3 offset 17 X PC INPACK B EXT CLK GPIO group3 offset 16 EXT SEL B GPIO group3 offset 15 PC 101516 EXT REQ GPIO group3 offset 18 EXT SEL B GPIO group3 offset 15 Centrality Communications Inc 80 AT460A BI Developer s Manual Centrality 5 EXT GPIO group3 offset 11 After reset GPIO will have control over these pins User can write corresponding GPIO control registers to give the control of these pins to EXT PCMCIA The priority of the above functions is as following e has control over these pins all others can not control the pin e Else if PCMCIA_EN is 1 in 5 ROMPAD register PCMCIA has control over these pins e Else EXT port has control over these pins
262. atchdog reset has occurred since the last time the CPU cleared this bit 33 12090 Reserved 5 7 Resource Sharing Controller 5 7 9 DMA Sharing The Resource Sharing Controller RSC manages the two major resources of Atlas II one is the pins the other is the DMA channels The following table shows the DMA channel sharing Table 22 Channels Allocation DMA Channel Shared Functions 0 Controller 081 2 2 24 3 Reseved 7 4 Flash Controller 5 ______ __ _______________________ 6 7 Audio CODEC Interface 8 11 Audio CODEC Interface UARTO USP1 5 Centrality Communications Inc 75 AT460A BI Developer s Manual Centrality NOTE Please refer to the section of DMA Controller for more details about the DMA channel sharing 5 7 10 Pin Sharing There are following groups of pin sharing e X FAULT X VDD FAULT Pin Pin Name HW GPIO Sleep Control X BATT FAULT GPIO groupO offset 28 X VDD FAULT GPIO group0 offset 29 These two pins will affect the hardware sleep function After reset these two pins are not controlled by GPIO and used as input GPIO can take over the control of these two pins by writing GPIOO_CTRL28 GPIOO CTRL29 Even in sleep mode GPIO still have the control over these two pins NOTE To use these two pins as GPIO the connected device can not pull the pin to high after reset otherwise the c
263. atermark for the screen FIFO If R W the FIFO FIFO count is filled beyond this mark then the request stops If the FIFO is read below this point then the request becomes low level request 8 MI CHK T h40 Value for the middle request watermark for the screen FIFO R W If the FIFO is filled beyond this mark then the request drops to low level request If the FIFO is read below this point Centrality Communications Inc 124 AT460A BI Developer s Manual Centrality _ then the request becomes high level request 15 70 Reseved 0 2 22 16 SCN 77 20 Value for the high request watermark for the screen FIFO If R W the FIFO is filled beyond this mark then the request drops to high level request If the FIFO is read below this point then the request becomes critical 23 _ 0 2 24 SCN REQ SEL 1 bO Selection of request generation method for SCN FIFO R W 1 Only high request and low request watermark are useful request value can be as 2 b00 and 2b 11 If the FIFO is read below high request watermark then the request becomes critical and if the FIFO is filled beyond low request watermark then the request stops As in critical request status the DMA bandwidth is a little lower using this mode will save some bandwidth 0 Normal request generation Three watermarks are all useful request value can be 2 b00 2 b01 2b 10 2b 11 3125
264. ations Centrality Communications Inc 371 AT460A BI Developer s Manual Centrality 9 4 24 JTAG AC Specifications Table 115 JTAG Timing Specification Spec ID Description 1 JTAG clock frequency 5 MHz 2 TRST TMS TDI data setup time 4 ns 3 TRST TMS TDI data holdup time 4 ns 4 TDO data output delay 15 ns 1 12 35 lt gt TRST TMS TDI 4 Data output gt Figure 89 Timing Diagram JTAG Input Output Line Centrality Communications Inc 372 460 Developer s Manual Centrality 10 Revision History Revision Date Author Comments 10 12 2004 Hongyu Zhang Created Completed Section 1 1 to Section 7 5 0 11 10 12 2004 Hongyu Zhang Added Section 5 4 Interrupt Controller 5 7 2 Pin Sharing 7 2 System to PCI Bridge 7 7 PCMCIA CF Interface and 7 8 Data Transfer Engines 10 14 2004 Hongyu Zhang Added Section 8 1 to 8 6 10 15 2004 Added Section 7 6 2 and 8 7 8 13 0 40 10 22 2004 Hongyu Zhang Added detail register definitions in Section 7 5 4 and added Section 9 Package and Pinout 10 23 2004 Hongyu Zhang Added detail register definitions in Section 8 9 3 1 Added an extra register section 7 4 4 5010 Host Controller Revision History format 0 90 11 2 2004 Hongyu Zhang Added M6730 Device control registers CAM_PIXEL_SEL register PWR CLK_EN registers
265. ave control over these pins User can write corresponding GPIO control registers to give the control of these pins to USP4 USP5 SD PCMCIA The priority of above shared function is as following e f GPIO has control over these pins both USP4 USP5 SD PCMCIA can not control the pin e Else if GPIO does not have control over these pins the SD EN 1 0 bit in RSC_PIN_MUX register determines whether USP4 USP5 or SD or PCMCIA has control over the shared pins X TXD 4 X RXD 4 X TXD 5 X RXD 5are controlled by USP4 5 ROM Part 1 NAND Flash Part 1 IDE Part 1 PCMCIA Part 2 ETM Part 2 Pin NAND Flash IDE PCMCIA 25 GPIO group3 offset9 WE GPIO group3 offset 8 1I DEIOW B PCIOWE B f GPlOgroup3offset7 X FA 22 PCIORDB f GPlOgroup3offseto X FA 21 DF CLE PY GPIO group offset 5 FALE GPIO group3 offset 4 GPIO group3 offset 3 GPIO group3 offset 2 GPIO group3 offset 1 GPIO group3 offset 0 GPIO group4 offset 15 GPIO group4 offset 14 GPIO group4 offset 13 GPIO group4 offset 12 GPIO group4 offset 11 GPIO group4 offset 10 GPIO group4 offset 9 GPIO group4 offset 8 GPIO group4 offset 7 GPIO group4 offset 6 GPIO group4 offset 5 GPIO group4 offset 4 GPIO group4 offset 3 GPIO group4 offset 2 GPIO group4 offset 1 GPIO group4 offset 0 TRACEPKT GPIO group5 offset 31 lt 15 gt GPIO group5 offset 16 TRAC
266. b1000 4 b1101 16 bit Addr 31 0 4 bOOxy 16 bit Access Addr 25 1 4 b11 x y 1 2 3 4 bxy00 32 bit Addr 31 0 Access Addr 25 1 4 b11 w z Centrality Communications Inc 155 AT460A BI Developer s Manual Centrality __________ Add 25 1 f 4 b11 x y 8 bit Addr 31 0 4600017 Access Addr 25 2 1 4 b0010 4 b0100 4 b1000 16 bit Addr 31 0 4 b0Oxy 32 bit Access Addr 25 2 4 b11 x y 4 bxy00 32 bit Addr 31 0 Access Addr 25 2 4 b x y w 732 1 slash RISC PCI means the Byte Enable can be either one 2 2 stand for the bit enable can be either 1700 1 b1 3 x means the invert of x 7 3 4 ROM SRAM Controller Registers Table 37 ROM RISC IO Register Mapping RISC Address Register Description lt 11 0 gt 0 0000 ROM CFGO ROM configure register for CSO 0x0004 ROM CFG1 ROM configure register for CS1 0x0008 ROM CFG2 ROM configure register for CS2 0 000 ROM CFG3 ROM configure register for CS3 Others e ROM CSO Configure Register ROM_CFGO 0x0000 0 controls the timing amp access mode for ROM port CSO Name Default Description Bit Write interval WGAP pci between each two write R W lt 5 0 gt Access time Tak pci is the read write signal R W active time CS active time TCES before read write signal
267. bO Match status channel 5 0 OS timer match register lt 5 gt has not matched the OS timer counter since the last clear 1 OS timer match register lt 5 gt has matched the OS timer counter e OS Timer Interrupt Enable Register TIMER INT 0x0024 Each match register has a corresponding enable bit Clearing an enable bit will prevent the corresponding interrupt status bit be generated Centrality Communications Inc 69 AT460A BI Developer s Manual Centrality Bit Name Default Description 0 R W 1 bO Interrupt enable channel 0 This bit is set by software and allows a match between match register 0 and the OS timer to assert interrupt bit MO in the TIMER STATUS 1 R W Interrupt enable channel 1 2 R W E2 750 Interrupt enable channel 2 _ 750 Interrupt enable channel 3 oo 4 R W 4 ____ 750 Interrupt enable channel 4 5 R W JES ____ 750 Interrupt enable channel 5 o 316 60 Reserved 0 e OS Timer Watchdog Enable Register TIMER WATCHDOG EN 0x0028 Bit Default _ Description 0 R W bO Watchdog match enable 0 OS timer match register lt 3 gt matches cause an interrupt request 1 OS timer match register 3 matches cause a reset 31 1 380 Reserved e OS Timer Division Register TIMER DIV 0x002C To generate the timer clock it needs to divide the clock input from system clock domai
268. bYYCr 110 YVUY YCbCrY 111 VYUY CbYCrY Centrality Communications Inc 27T AT460A BI Developer s Manual Centrality 13 12 R W OUT FORMAT 2600 RGB format send to the FIFO after YUV to RGB conversion 00 8 8 8 01 6 5 5 10 5 5 6 11 5 6 5 14 R W YUVRGB 1 bO 0 Bypass the conversion of YUV to RGB 1 Convert data format from YUV to RGB pin ees 8 5 5 8 8 17 16 R W X SCA 2100 Contraction ratio column direction 2 b00 no contraction 2 b01 1 2 contraction 2 b10 1 4 2 b11 1 8 19 18 R W Y SCA 2100 Contraction ratio row direction 2 b00 no contraction 2 b01 1 2 contraction 2 b10 1 4 2 b11 1 8 3020 Reserved 224 Just reset camera control module configuration data still reserved Logic remains in reset until a 0 is written to this bit e Camera Pixel Bit Select Setting Register CAM PIXEL SET 0x014 Bit Name Default Description 2 0 R W PIXEL_SEL 3710 Pixel bit select option We always connect the input pixel data to the lowest data pin 3 b000 select PXD lt 15 0 gt as valid data 3 b001 select PXD lt 7 0 gt as valid data 3 b010 select PXD lt 8 1 gt as valid data 3 b011 store PXD lt 9 2 gt as valid data 3 b100 select PXD lt 10 3 gt as valid data 3104 select PXD lt 11 4 gt as valid data 3 b110 select PXD lt 14 7 gt as valid data 3 b111 store PXD lt 15 8 gt as valid data 31 3 e Red Coefficient
269. been transferred and EOT is set in the descriptor table IDE DMA Error This bit becomes set when either a target or master abort is encountered during DMA transfers on the PBI bus 2 R INT STATUS 1 bO IDE Interrupt Status This bit is set when the IDE device asserts its IRQ signal It may be cleared by writing 1 to this bit even if the IDE IRQ signal is still active 5 rr HS CAP 1 bO Drive 0 DMA Capable When set to 1 the drive is Note Software controlled status bit does not affect hardware 6 R W 01 CAP Drive 1 DMA Capable When set to 1 the drive is capable of DMA transfer Note Software controlled status bit does not affect hardware 7 ____ fb 0 Reserved NOTE Bit 1 and 2 are read and clear bits e Bus Master Descriptor Table Base Address Register DT BASE offset 0x4 This register holds the base memory address for the Descriptor Table The Descriptor Table must be DWORD aligned and must not cross any 4Kbyte boundary Bit Default Description 10 20 Reserved 31 2 DTBA Descriptor Table Base Address DTBA RW 7 6 3 3 IDE Device Registers Table 55 IDE Device Port Map ADDRESS FUNCTION Centrality Communications Inc 220 AT460A BI Developer s Manual Centrality IDE IDE_CS _ Address Read Write 1 0 Offset Data Command 1 ta ata po Error Feature 2 __ 2 Sector Count Sector Count
270. ble 34 ROM SRAM Interface Pin Description Pin name Pin Direction Description X_FD lt 31 0 gt Bidirectional Data pin Depending on the device bus width some of them will be used If device only has 8 bit bus then X_FD lt 7 0 gt is used Data output enable Active low Data write enable Active low XFWEB X_FBE lt 3 0 gt Byte enable signals Active low Depending on the device bus width some of them will be used If device has 8 bit bus then only X 0 will be used X FRDY B Ready pin Active low Only device with variable access feature will need it Centrality Communications Inc 154 AT460A BI Developer s Manual Centrality 7 3 3 Address Mapping ROM SRAM interface supports read write to external 8 16 32 bit ROM SRAM or SRAM like devices User can access ROM SRAM through either RISC IO access RISC only or PCI IO access Both RISC and DSP The address mapping is shown in the following table Table 35 RISC IO access PCI IO access address Mapping RISC IO access PCIIO access address X FA X_FCE_B 8 0 address 0x10000000 0x60000000 0 0000000 X 0 active Ox13FFFFFF Ox63FFFFFF Ox3FFFFFF Other banks inactive Ox17FFFFFF 0x67FFFFFF Ox3FFFFFF Other banks inactive Ox1BFFFFFF 0x6BFFFFFF Ox3FFFFFF Other banks inactive Ox1FFFFFFF Ox6FFFFFFF Ox3FFFFFF Other banks inactive NOTE It is recommended to use PCI IO access mode ROM SRAM interface will accept either
271. card the data will be filled in to the first and second FIFO alternatively When data from first FIFO is transferring to the SD card the second FIFO will be filled and vice versa The two FIFO s are alternatively used to store data which will give maximum throughput During a read transaction data transferred from SD SDIO card to Host the data from SD card will be written in to the two FIFO s alternatively When data from one FIFO is transferring to the Host the second FIFO will be filled and vice versa and thereby the throughput will be maximized If the Host controller cannot accept any data from SD card then it will issue read wait to stop the data coming from card DAT lt 3 0 gt Control Logic The DAT lt 3 0 gt control logic block transmit data through the data line during write transaction and receive data through the data line during read transaction The interrupt generated from the SD SDIO card is detected Command Control Logic Centrality Communications Inc 163 AT460A BI Developer s Manual Centrality The Command control logic block sends the command through the CMD line and receives the response coming from the SD SDIO card Power Control The SD SDIO Host Controller supply SD Bus Power depending on the value programmed in the Power Control Register by the Host Driver The Host Driver has the responsibility to supply SD Bus Voltage according to card OCR and supply voltage capabilities depending on the Host Co
272. ce rounoaocz roncin caseo em re resosi rovaneocz onono semena Ps peme sonst aos OF ALEUTAG MODE __ 0 OR emoe ore m pn e e ems PDUWO8DGZ ROM SRAM Read Enable DF RD B nese v Ere e ree __________ Ene e ree sons orem ve Rowena oveenene ve pure e pure ouaz sonst teens 9 xr aooe pu ADDE osy us eroe D Dr ADDE pus xr CTS D Sr ADDED xo fuo DD pr ADDE Dm e ea eouwosocz p r eroe aooe Centrality Communications Inc 350 AT460A BI Developer s Manual KE Centrality COMMUNICATIONS 13 m PD IOPED TOMDF ADe10 IDE D 10 ma 10 lt 11 gt 0145 pw ms n6 012 lt gt lt 1 gt _ lt 13 gt _ lt 13 gt 137 wie PD lt 1as ED lt 14 gt DF_AD lt 14 gt IDE_D lt 14 gt PN X_FD lt 16 gt PDUWOBDGZ ROM SRAM Data ED lt 16 gt TRACEPKT lt 0 gt U13 ROM SRAM Data ED lt 17 gt
273. ch is at coordinate xy 0 0 pixel format 2 b00 26 0 valid pixel format 2 b01 26 1 valid and bitO should be 0 pixel format 7 2 b1X 26 2 valid and bit1 0 should be 00 31 27 1 Centrality Communications Inc 142 AT460A BI Developer s Manual Centrality e Destination Base Address SDRAM DES BASE 0x1C10 Bit Name Default Description 26 0 DES BASE 27 0 base memory address of destination with byte R W alignment the pixel which is at coordinate xy 0 0 pixel format 2000 26 0 valid pixel format 2 b01 26 1 valid bitO should be 0 pixel format 2 b1X 26 2 valid and bit1 0 should be 00 Reserved 3127 Reserved e 2D window dimension BLT WINDOW DIM 0x1C14 Name Default Description ee m HEIGHT 110 The 20 window s height in pixels Max 2047 lines height BE 4h0 Reserved 26 16 WIDTH 17 0 The 2D window s width in pixels R W Max 2047pixels wide 31 28 40 Reserved e Pitch of Source and Destination in pixels TWOD STRIDE 0x1C18 Bit Name Default Description DES STRIDE 12 h0 Line stride of destination specified in pixels R W oes 4mo _ _ _ I 27 16 SRC STRIDE 12 h0 Line stride of source specified in pixels R W 3128 Reserved The Source 2D Window XY Coordination SRC XY 0Ox1C1C Bit Default Description 10 0 SRC_Y
274. control register 0x0120 0x87 88 DMA CH LOOP CTRL DMA channel loop control register Others __ Reserved DMA Channel lt 11 0 gt Address Register DMA_CH lt 11 0 gt _ADDR The DMA channel start address is in the 32 bit D word boundary This must be the last register to be set among all the DMA configuration registers Setting this register will start the DMA Bit Name Default Description lt 24 0 gt 25 hO DMA start address in 32 bit D word boundary R W 25 70 Reserved 9 NOTE1 For burst mode DMA please set the start address to be 16 byte boundary Otherwise the burst will be cut into multiple single transfers and the efficiency is much lower NOTE2 For loop mode DMA set the start address will not start the DMA at once The user needs to set the DMA_CH_LOOP_CTRL to start the DMA But before start a new DMA user still needs to configure this start address register to clear the internal status of last DMA e DMA Channel lt 11 0 gt X Length Register DMA_CH lt 11 0 gt _XLEN The DMA X length is in 32 bit D word boundary The value specifies the number of D words transferred in each line The maximum length is 2047 DWORDS In burst mode X length should be in 16 byte boundary normally but it is allowed to be set to any value For example if X length 5 then the controller is actually doing 2 bursts However in the last burst the DMA controller will only do one DW
275. ct DMA WIDTH2 11 select DMA WIDTH3 2 R W DMA direction 1 DMA from SDRAM to peripheral FIFO 0 DMA from peripheral FIFO to SDRAM 3 R W BURST DMA transfer mode 1 DMA is in burst transfer mode 0 DMA is in single transfer mode 28 h0 Reserved DMA Width Registers WIDTHO 3 RISC 0x100 0x10C DSP 0x80 0x83 There are two separate sets of DMA Width registers in the Atals 1 one for RISC the other for the DSP It depends on the setting of the DSP ENto select which sets to use Each set has 4 Width registers Each DMA channel can select to use any one of these 4 Width registers To enable the correct 2 D DMA the DMA Width register has to be correctly set And the value of the DMA Width register has to be greater than or equal to the X length Otherwise the data will be overlapped Bit Default Description WIDTH lt 11 0 gt 12 hO DMA Width R W 3112 120 DMA Channel Valid Register CH VALID RISC 0x110 DSP 0x84 A one in this register means the corresponding DMA channel is active The user can write a 1 to each bit of this register to force the DMA of that channel to stop Name Default Description 11 7 VL lt 11 0 gt 12 0 IET channel valid bits This bit will be automatically set R W to 1 ifthe START ADDR register is written Write a 1 to each bit will stop that channel s DMA 31 12 120 Channel Interrupt Register DMA CH INT RI
276. ction is enabled Bit7 0 valid when pixel format is 00 Bit15 0 valid when pixel format is 01 Bit31 0 valid when pixel format is 1X The Destination Color Key DES COLORKEY 0x1C38 Bit Default Description 31 0 DES COLORKEY 32 hO Similar to COLORKEY except that if the R W destination is needed in a ROP and pixels from the destination bitmap is of this value thus if function enabled the destination pixel will not be changed Bit7 0 valid when pixel format is 00 Bit15 0 valid when pixel format is 01 Bit31 0 valid when pixel format is 1X BitBLT ROP Code 0x1C3C Name Default Description 7 m 870 Please refer to figure below for details ROP2 and R W ROP3 are treated coequally as those Bits lt 7 4 gt Bits lt 3 0 gt they are ROP2 otherwise they are ROP3 Writing into this register will start the BLT immediately if not in command queue mode 9 8 PIXEL FORMAT Pixel format for both the source and destination as R W 00 8bits pixel not index mode 01 16bits pixel 1X 32bits pixel Bm Source color key enable when 1 or disable when 0 R W When enabled source pixel with this color value as SRC_COLORKEY will not change the destination pixel 12 DES COLORKEY_EN Destination color key enable when 1 or disable when 0 R W When enabled result from the ROP logic with value of DES COLORKEY will not replace the destination pixel 3113
277. d 0 Aux TX FIFO full interrupt is disabled 1 R W 1 Aux TX FIFO empty interrupt is enabled 0 Aux TX FIFO empty interrupt is disabled 1 Aux TX FIFO underflow interrupt is enabled 0 Aux TX FIFO underflow interrupt is disabled 314 1280 3 R W TX AUX FIFO UFLOW EN 2 R W TX AUX OFLOW 150 1 Aux TX FIFO overflow interrupt is enabled 0 Aux TX FIFO overflow interrupt is disabled Centrality Communications Inc 298 AT460A BI Developer s Manual Centrality e CODEC RX FIFO DMA I O Control Register CODEC RX AUX DMA IO CTRL 0xBCO Bit Default Description O R W 10 DMA SEL 1 for mode 0 DMA mode 1 IO DMA RW 1 b1 1 read from CODEC 0 write to CODEC 2 R W DMA FLUSH 1 bO Flush the DMA receive FIFO in case the DATA LEN set at the peripheral side doesn t match the DWORD size set in the DMA control Reserved o 3 RW RW ENDIAN TbO f Reserved 314 e CODEC FIFO Control Register CODEC RX AUX FIFO 0 8 Name SBGSCHBROD DWORD mo A threshold in byte to trigger an interrupt An interrupt is triggered when the count of data in the FIFO reaches the threshold 318 12400 e CODEC Level Check Register CODEC AUX FIFO LEVEL OXBCC Description 5 Stop check DWORD 94 9 4 R W RAW Emm R W R W 3124
278. d and may hold its value in the flop If the Card Interrupt Status Enable is set to 0 the HC shall clear all internal signals regarding Card Interrupt To Detect CMD Line conflict the HD must set both the CMD TIMEOUT ERR INT EN bit and the CMD CRC ERR INT EN bit to 1 SDIO Interrupt Signal Enable Register SD INT SIGNAL EN 0x0034 Bertaut Description 1 Enabled 1 Enabled 1 Enabled r BUFF WT RDY INT SIG EN 0 Masked 1 Enabled 5 R W BUFF RD RDY INT SIG EN 0 Masked 1 Enabled Centrality Communications Inc 181 AT460A BI Developer s Manual Centrality 6 1 1 1 1 CURRENT LIM ERR INT SIG AUTO CMD12 ERR INT SIG R W CARD_INSERT_INT_SIG_EN 7 R W CARD REMV INT SIG 0 Masked 1 Enabled 2 2 DAT ENDBIT ERR INT SIG EN R W 2 2 DAT CRC ERR INT SIG EN 0 Masked R W 1 Enabled 0 Masked 1 Enabled 0 Masked 1 Enabled 59 CMD TIMOUT ERR INT SIG m mmm _ gee ee 0 Masked 1 Enabled 0 Masked 1 Enabled 0 Masked 1 Enabled 0 Masked 1 Enabled 0 Masked 1 Enabled 0 Masked 1 Enabled 0 Masked 1 Enabled 0 Masked 1 Enabled 1 hO 1 hO 1 hO 1 hO 1 hO 1 hO 1 hO 1 hO 1 hO 1 hO 1hO Reserved O 31 28 VEND SPEC ERR INT SIG EN 0 Masked 1 Enabled This register is used to
279. d at the end of the transfer Software can clear this bit by using EtdDmaChannelClear Register e USB OTG Endpoint DMA Enable Register USBOTG_DMA_EP_EN 0x0824 Bit Name Default Description Centrality Communications Inc 211 AT460A BI Developer s Manual Centrality 320 Endpoint DMA Enable Setting the EndpointDMAEnble bit will enable DMA transfer on the corresponding EP Will be auto disabled at the end of the transfer Software can clear this bit by using EpDmaChannelClear Register USB OTG ETD DMA Enable X Triger Request Register USBOTG TRIGX EN 0x0828 Bit Default Description 31 0 W ETDDMAXTEN 32 hO ETD DMA X Trigger Enable Writing a 1 sets the corresponding ETDDMAEnable bit and causes an external XTrigger for the client e USB OTG Endpoint DMA Enable X Triger Request Register USBOTG TRIGX 0x082C Bit Default Description 31 0 W EPDMAXTEN 3280 Endpoint Trigger Enable Writing a 1 sets the corresponding EndpointDMAEnable bit and causes an external XTrigger for the client USB OTG ETD DMA Enable XY Triger Request Register USBOTG DMA TRIGXY EN 0x0830 Bit Default Description 31 0 W ETDDMAXYTEN 32 h0 ETD DMA X and Y Trigger Enable Writing 1 sets the corresponding ETDDMAEnable and causes both XTrigger and YTrigger for the client e USB OTG Endpoint DMA Enable XY Triger Request Register
280. d modems or it can be configured as a half duplex synchronous system that can communicate with peripheral devices such as A D or D A integrated circuits serial EEPROMs or touch panel controllers There are a total of five 5 USPs identified as USP1 through USP5 on the Altas II Processor These USPs are identical to each other except that USP3 has an extra SIB Serial Interface Bus controller The SIB controller is used to support connections to touch panel controllers such as the UCB1200 1300 8 8 2 Supported Protocols and Devices Depending on the clock the USP can be configured in the following modes e Asynchronous no clock is need o Sample uses UART IrDA o data rate 115 200 bps Synchronous Master clock is generated by USP uses SPI bus PCM bus o Max clock frequency 1 6 the I O clock Synchronous Slave clock is generated by external chip o Max clock frequency 1 20 the I O clock Depending on the type of the serial bus the Altas I USP can support the following types of serial ports e ASYNC UART and IrDA SPI bus such as serial EEPROM 25 040 and Philsar PH2401 12S bus such as WM8978 8 8 3 Pin Description Each USP has 5 input output pins Table 80 USP Pin Descriptions Pin Name Direction Description X TXD n Bi directional TXD Transmit Data X RXD n Bi directional RXD Receive Data X TFS n Bi directional TFS Transmit Frame Sync X RFS n B
281. ding to the frequency of I O clock IRDA_WIDTH_DIV 1 6us fiock 1 IrDA received data IDLE level 0 low level for idle state 1 high level for idle state 318 AT460A BI Developer s Manual Centrality 31 R W TX UFLOW 1 bO TX underflow repeat mode T 0 repeat the last transmitted data 1 repeat zero e USP Mode Register 2 USP MODE2 ARM9 0x4 DSP 0x2 0x3 Name Default Description lt 7 gt RXD_DELAY_LEN 8710 Delay clock number between the FS and the first R W receive data It should be set to actual_delay_length in both the slave and master mode of RFS lt 15 8 gt TXD_DELAY_LEN Delay clock number between the FS and the first R W transmit data When TFS is slave it must be set to actual_delay_length 1 When TFS is master it must be set to actual_delay_length 16 R W ENA CTRL MODE 1 bO USP TX RX ENABLE register operation mode 1 b0 the TX ENA will not be cleared after the current operation finish You only need to setto TX ENA RX ENA bit only once before multi time transmit receive 1 b1 The TX ENA RX bit in the USP TX RX ENABLE register will be cleared automatically after the previous operation finish TX ENA RX ENA bit must be set before a new transmit receive operation begin FRAME CTRL MODE USP transmit and receive operation control mode 0 New frame transmit receive will begin only with new data in the TX FIFO 1 after the USP operation sta
282. dware reset Hardware reset is asserted through the RESET_B pin that is intended to be used for power on only It s a full chip reset so that every registers on chip will be reset to its default value and the content in the SDRAM will be lost Software reset There is a RESET_SWR register which can be programmed by user to reset most of the blocks on chip User can select to apply reset to each block of the Atlas II separately The assertion of system reset bit bit31 SYS_RST will reset the majority of Atlas II as well as causing the assertion of the RESET_OUT pin The Software reset will not cause the SDRAM data loss e Sleep reset Sleep reset is generated automatically by hardware when the Atlas II enters sleep mode During sleep mode the majority of the processor will be reset except the power manager RTC Resource Sharing Controller and GPIO controller Before sleep reset the SDRAM controller will issue a self refresh command to the SDRAM so that the data will not be lost during sleep mode After boot up software can check the reset controller reset status register RESET STATUS to determine which types of reset has just occurred 5 6 6 Reset Scheme Each block in Atlas II has its own reset control signal As described above the reset has 4 sources Hardware reset Software reset Watchdog reset and Sleep reset The following table shows that how each module is controlled by these 4 types of reset sources Table 2
283. e state of the wp niois16 signal the PC card This signal will reflect the status of the WP signal from the memory PC card socket 1 b0 Card is not write protected 1 b1 Card is write protected Either no card or cards Card is not fully inserted 1 b0 Card is not ready 1 b1 Card is ready This signal will reflect the status of the rdy signal from the memory PC card socket This bit indicates whether the power to the PC card is ON or OFF 1 b0 Power to card is not on 101 Power to Card is on 1b ltalways reads 151 for the M6730 e M6730 Power Control Register M6730 PWR CTRL Index 0x02 ncd1 inputs from the PC card READY BUSY This bit indicates the status of the rdy nireq 2 Card Detect Status signal input from the PC card CARD_PWR_ON Bit Name Default Description 1 0 R W VPP1 PWR Reference to the bellowing table 2 RW 2 0 Compatibility bits 4 R W VCC PWR 1 bO 1 b0 Power is not applied to the card the nvcc nvcc 5 socket power control Centrality Communications Inc 228 AT460A BI Developer s Manual Centrality signals inactive high 1 b1 Power is applied to the card if bit 5 is1 bO or bit 5 is1 b1 and 2 and ncd1 are active low then the selected Depending on the value of the bit 5 setting this bit to 161 applies the power to the card The Vcc3 3 bit determines whether 3 3v or 5v is applied to the card N
284. e Atlas II can be used in Telematics Infotainment and Navigation system Centrality Communications Inc 12 AT460A BI Developer s Manual Centrality gt ws a USB OTG UART IrDA LCD 3 CODEC 227 e v D e Q Centrality 9 460 CANBus Hard Drive o DDR SDRAM 2 Stream e SmartMedia SDIO PCMCIA Compact Flash A S Figure 2 4 as an Infotainment and Navigation Product Centrality Communications Inc 13 460 Developer s Manual LS Centrality COMMUNICATIONS 2 RISC Subsystem 2 1 Overview The RISC subsystem contains the ARM926EJ core the instruction and data caches and an RISC interface block Clock external interrupts RISC Subsystem Memory Bus ARM926 RISC Core Interface 16KB Bus DCache Figure 3 RISC Subsystem Block Diagram 2 2 Functional Description 2 2 1 ARM926EJ Processor ARM926EJ RISC Core in Atlas Il is a hardened version of ARM926EJ S processor which is member of the 9 family of general purpose microprocessors The ARM926EJ S processor is targeted at multi tasking applications where full memory management high performance small die size and low power are all important The ARM926EJ S processor supports the 32 bit ARM and 16 bit THUMB instruction sets enabling the user to tr
285. e DAT_TIMEOUT_VAL according to the Capabilities register 26 NOTE A reset pulse is generated when writing 1 to each bit of this register After completing the reset the HC shall clear each bit Because it takes some time to complete software reset the SD Host Driver shall confirm that these bits are 0 e SDIO Interrupt Status Register SD INT STATUS 0x0030 The interrupt status register include two sections low word for normal interrupt status and high word for error interrupt status The Interrupt Status Enable affects read of this register but Interrupt Signal Enable does not affect these reads An Interrupt is generated when the Interrupt Signal Enable is enabled and at least one of the status bits is set to 1 For all bits except ERR INT writing 1 to a bit clears it Bit Default Description 0 R W END 1 bO This bit is set when get the end bit of the command response Except Auto CMD12 Note CMD TIMEOUT ERR has higher priority than Command Complete If both are set to 1 it can be considered that the response was not received correctly 0 No Command Complete 1 Command Complete 1 R W TRAN END 1 bO This bit is set when a read write transaction is completed Read Transaction This bit is set at the falling edge of Centrality Communications Inc 176 460 Developer s Manual Centrality If the STOP AT GAP the SD HOST 0 Register is set
286. e address Each entry in the palette is 18 bits 6 each for each color Bits 17 12 Red Bits 11 6 Green Bits 5 0 Blue 3138 Reseved y The 64 x 32 RAM is written or read directly by RISC Interface to access the specified address It is used for dithering sequence of frame rate control in passive color mode It generates a 32 x 64 entry to support 32 grey scale levels for every R G B color As the dithering sequence for one gray color is 64 bit the bottom half RAM is used for the first 32 bits of the dithering sequence and the up half RAM is used for the other 32 bits of the dithering sequence e Read Write Color Dithering Sequence LCD COLORSEQ 0x1800 0x18FC Bit Name Default Description 31 0 as SEQ Values in the dithering sequence of frame rate control One R W dithering sequence entry is made of two 32 bit DWORD s 6 3 2D BitBLT Engine 6 3 5 Overview The Atlas II BitBLT engine is designed to accelerate Microsoft s DirectDraw applications The engine contains a 3 operand ALU with 256 raster operations source and destination FIFOs The Engine runs at the memory clock speed The BitBLT Engine supports these features 1 Support byte level BitBLT when 8bpp not index mode and word level when 16bpp and DWORD level when 32bpp pixel format 2 Supportrectangle clipping that is when clipping enabled only pixels inside this box will be affected by the operations 3 Support Destination Color
287. e bottom right corner pixel position e Horizontal start position for active OSD screen LCD OSD HSTART 0x10 Default Description 10 2 OSD_HSTART 1110 Horizontal Start Position in pixel number for the active R W OSD display This value along with the horizontal end position and vertical start and end positions define the rectangle for the active OSD display 31311 __ 21h0 __ Reseved e Vertical start position for active OSD screen LCD OSD VSTART 0x14 Bit Name Default Description 10 0 OSD_VSTART 1180 Vertical Start Position in line number for the active OSD R W display This value along with the horizontal start and end position and the vertical end positions define the rectangle for the active OSD display 31 11 270 Reserved 0 e Horizontal end position for active OSD screen LCD OSD HEND 0x18 Bit Name Default Description 10 0 11 Horizontal End Position pixel number for the active OSD R W display This value along with the horizontal start position and vertical start and end positions define the rectangle for Centrality Communications Inc 105 460 Developer s Manual Centrality PT the active OSD display 31 11 12190 Reserved e Vertical end position for active OSD screen LCD OSD VEND 0x1C Bit Default Description 10 0 OSD_VEND 11 h0 Vertical End Position in line numbe
288. e defined below when not in active region 0 Display the last pixel value when not in active region 31 25 7 0 Reserved o O Centrality Communications Inc 113 AT460A BI Developer s Manual gt Centrality Display mode and format register LCD_DISPLAYMODE 0x64 B Name Default Description FRAME_VALID Frame valid When this bit is set the frame is RAW considered valid i e the internal counters will count based on the pixel clocks and horizontal sync signals When this bit is cleared the frame is considered invalid and the counters do not change and thus there is no output Note that when the bit value changes in the middle of a frame it does not take effect until the beginning of the next frame i e there is a vertical sync signal 0 3 1 The current SCN layer source data bpp format 100 2 bit per pixel 000 4 bit per pixel 001 8 bit per pixel 010 12 bit per pixel 4 bit R 4 bit G 4 bit B 011 16 bit per pixel 5 4 Output format 00 01 10 6 6 6 18bit output 11 8 bit muxed RGB with color component determined by the RGB sequence Note If in bypass mode these two bits are OUT FORMAT 1 bO R W ignored BYPASS 1 bO Bypass mode 1 The data from the memory is directly sent to the output bypassing either the palette lookup for the 4 and 8 bit modes or the bit shifting for the 12 and 16 bit modes When this bit is set to 1 the display mode in bits 3 1 still is used
289. e on the bus using Centrality Communications Inc 330 AT460A BI Developer s Manual Centrality the self reception request command The CANBUS controller will perform a successful transmission even if no acknowledge is received 0 Normal operation An acknowledge is required for successful transmission 1 Single Filter Receive data filtered using one 4 byte filter 0 Dual Filter Receive data filtered using two shorter filters 31 4 209 Reserved e CANBUS Command Register CANBUSn CMD 0x0004 Bit Name Default Description 0 W Set to 1 when a message is to be transmitted 1 AT 10 Set to 1 to cancel the next transmission request provided this is not already in progress Set to 1 to release the Receive Buffer PP ul Li i Set to 1 to clear the data overrun condition signaled by the Data Overrun Status bit Note No further Data Overrun Interrupt will be generated while the Data Overrun Status bit remains set Set to 1 when a message is to be transmitted and received simultaneously Reseved e CANBUS Status Register CANBUSn SR 0x0008 Description 1 Receive Buffer Full One or more complete messages are available to be read from the Receive FIFO via the Receive Buffer 0 Receive Buffer Empty No message currently available to be read 1 Data Overrun A message has been lost becau
290. e source to a temp destination buffer SDRAM and use the temp destination buffer as the second BLT command s source instead Pattern for ROP3 is mono and designed as 8 8 The Command Queue must align on 4DW address Support only little endian mode O01 The BitBLT is reset by the system asynchronous reset which is low active And when the SW writes a BLT command the BLT will be started based on the ROP type and stop automatically when BLT over when in manual mode and if in auto mode SW can prepare a BLT command queue and tells hardware the queue start address the engine will automatically fetch the command one by one and stop when all command finishes 6 3 6 Functional Description Bus Hub ARB System MBUS 10 Bus LCD_CTRL Figure 30 Block Diagram of BitBLT Engine The parts in blue are the main BitBLT diagram CPU writes BLT command into BLT s Command queue which will be interpreted to configure the BLT DMA and ROP in different mode There are four DMA modules in the BLT two DMA Read modules DMAR load data from SDRAM as the operands of the ROP operation after which one DMA Write module DMAW stores data back into SDRAM and another is used to fetch BLT command from SDRAM when in auto mode These DMA s will be arbitrated along with the LCD controller s DMA s by the BUS HUB to access the System Bus This DMAR module takes charge of f
291. e to even further reduce power when the cards are inserted but no card accessibility is required Even though power may or may not be applied the pull up circuitry is disabled NOTE Insertion or removal of cards cannot be determined when this bit is 1 b1 Also if the card detect interrupts are enabled and the card is already in the socket A CARD DETECT INTERRUPT WILL BE GENERATED WHEN THIS BIT IS CHANGED T 6 RW Reserved 2 M6730 System Memory 0 4 Upper Address Register M6730 SM MAPO0 4 UA Extension Index 0x05 0x09 INV MGT IRQ 1 bO Invert Management IRQ Output 1 b0 The management irq is active high 1 b1 The management irq is active low This bit changes the active high ISA type card IRQ level to an active low output that complies with the PCI bus requirements 2n0 Bit Default Description Centrality Communications Inc 245 AT460A BI Developer s Manual Centrality 7 0 R W UA lt 7 0 gt Upper Address These bits are used in comparing the address bits 31 24 for each memory window 0 44 These bits are used in conjuction with the System Memory Map 0 4 Start Address and the System Memory Map 0 4 End Address registers M6730 External Data M6730_EXT_DAT Extension Index 0x0A Bit Name Default Description 0 R Socket A VS1 Input These bits indicate the values of the four 1 Socket VS2 Input voltage sense signal inputs from the t
292. ead only Bit Name Default Description O R W RISC DSP SEL 1 bO 0 the UART is accessed by RISC 1 the UART is accessed by DSP 31 1 3fh0 Reserved 2 2 8 7 4 2 UARTO TX FIFO Registers NOTE The data flow of TX FIFO is always from RISC DSP DMA to UART UART TX DMA MODE Register UART TX IO RISC 0x100 DSP 0x40 Bit Name Default Description R W 10 SEL 1 for mode 0 for DMA mode Centrality Communications Inc 310 AT460A BI Developer s Manual Centrality 37 390 Reserved TX ENDIAN MODE 316 26 e UART TX DMA I O Length Register UART TX DMA IO LEN RISC 0x104 DSP 0x42 0x43 Bit Default Description 31 0 DATA_LEN 3210 byte number of DMA or I O transfer If R W set to zero the I O or DMA transfer works continuously until it is stopped e UART TX FIFO Control Register UART TX FIFO CTRL RISC 0x108 DSP 0x44 Name Default Description FIFO_WIDTH lt 1 0 gt 2 0 Data width of FIFO 0 for byte 1 for word and 2 for DWORD Bit 1 0 R W FIFO_THD lt 5 0 gt A threshold in byte to trigger an interrupt R W An interrupt is triggered when the count of data in the FIFO reaches the threshold 318 Reserved UART TX FIFO Level Check Register UART TX FIFO LEVEL RISC 0x10C DSP 0x46 0x47 Bit Name Default Description Stop check in DWORD 94 1600 Reserved Low check in
293. edge of MEM_CLK t Control Signals Address and MBA Hold 2 ns dis after rising edge of MEM DQM valid after rising edge of MEM CLK 45 ns DQM hold after rising edge of MEM_CLK 30 ms MDQ hold after rising edge of MEM_CL 4 ns 1 tdata_setup 4 tdata_hold 277 Address 7 77 7 X ene 77777 777777 x dqm Data Mask x md Data thold Bank Saes NOTE Control Signals composed of RAS CAS MEM WE CS 51 and CLK EN Figure 78 Timing Diagram Standard SDRAM Memory Read Timing 9 4 11 2Memory Interface Timing Standard SDRAM Write Command Table 105 Standard SDRAM Write Timing Sym Description Min Units Centrality Communications Inc 364 AT460A BI Developer s Manual Centrality Control Signals Address and MBA Valid s valg after rising edge of MEM_CLK Control Signals Address and MBA Hold Diana vat ater sing edge or 45 ms DMs DoM aner rising edge ormem 30 ns _ setup orang edge oru cuc 7 tano MDG aner reing edge ormem_ct_ 5 rs Control signal NIE NICE GINA COND 789 DMhoid wam 001 LU ZZZIVZIN Data Mask lona voi _vaild lt gt gt tdata_hold CA 01 7772 E Gell MEINE 101 gt
294. efficient 12 for the RGB to YUV conversion matrix This RW value should be an 8 bit signed value vate shoud be an Stsined yale RW value should be an 8 bit signed value 3 242 __ 80 Reserved The suggested coefficients 0x264BOE which indicates Y 0 296875 0 5859375 G 0 109375 B e RGB to YUV Coefficient 2 LCD RGB YUV COEF2 0x78 Description RW value Should be an 8 bit signed value E value should be an 8 bit signed value O E Nate shoud bean btsigned vale RW value should be an 8 bit Lc m _________ value 31 24 80 Reserved 1 The suggested coefficients are OxEBD640 which indicates U 0 1640625 R 0 328125 G 0 5 B RGB to YUV Coefficient 3 LCD RGB YUV COEF3 0x7C Name Default Description 23 TA COEF1 8 hO Coefficient 31 for the RGB to YUV conversion matrix This TE value Should be an 8 bit signed value mw E9 aiue shou be value should be an 8 bit signed value _ value should be an 8 bit signed value dE 24 80 Reserved suggested coefficients are 0 40 Centrality Communications Inc 117 460 Developer s Manual Centrality which indicates V 0 5 R 0 4140625 G 0 078125 B e RGB to YUV conversion control register LCD YUV 0x80
295. egister ALT_VSYNC_VALID Valid T 1 Alternate VSYNC signal is valid along with the normal VSYNC defined by LCD_VSYNC_WIDTH Use start pixel and line values to define phase 0 Signal is not valid This bit gets higher priority than the VSYNC_SEL in LCD_TIMCTRL if this bit is on both VSYNC will be used Normally this mode will be used to generate the Odd and Even VSYNC in TV master mode 31 23 NOTE Please refer to the figure above for more details This register controls the red part of the VSYNC signal e OSC PIXCLK divider ratio register LCD OSC RATIO 0x50 Name Default Description 9 RATIO 1080 Divider ratio OSC_PIXCLK is obtained from SYSCLK R W divided by this value 1110 12500 12 HALF DUTY 1 bO 1 Generate OSC PIXCLK of 5096 duty cycle when the R W divider ratio OSC_RATIO lt 9 0 gt is odd Centrality Communications Inc 112 460 Developer s Manual Centrality 0 OSC_PIXCLK is not 50 duty cycle clock when the divider ratio OSC_RATIO lt 9 0 gt is odd 3113 1980 Reserved The pixel clock is divided from the system clock when Atlas drives the PIXCLK with this ratio as Flick Fsysclk DIV_RATIO 1 and the minimum DIV_RATIO value is 1 Timing Control Status Register LCD TIMING STATUS 0x54 This register is read only This is for test purpose only software shall ignore it Bit Name Default Description 1 0 R RGB_SEQ_STA 2 b00 Curren
296. either RGB values or converted YUV values and the parallel data of the Parallel Process unit to the format required by the external LCD controller or displays Because Atlas Processor supports different types of LCDs for different applications the output interface may output 16 bit RGB values 8 bit alternate R G or B values 8 bit RGB muxed format for color TFT LCDs or 4 8 or 16 bit outputs for S STNs or D STNs or 8 bit 4 2 2 mode and 16 bit 4 4 4 mode for YUV output etc The Timing Control block controls the timing information for the display It keeps track of the pixel and line number and generates pixel clocks and control signals to be used by the datapaths and the Output Interface The Bus Slave Interface provides the access interface for RISC Interface to read write LCD controller control registers palette and FIFOs The Bus Slave Interface will process the request and either read write a control register read write the palette or modify the data in one of the FIFOs The Control Registers block contains all the control registers used by the LCD interface These registers can be read or written to by the RISC Interface via the Bus Slave Interface The following sections describe some functional blocks within the LCD controller such as the DMA to memory interface palette RAMs and the frame rate control 6 2 3 1 Display Layers There are a total of 3 display layers that can be mixed before display to the LCD panel Layer
297. ended to program the current DMA before it finishes Centrality Communications Inc 255 AT460A BI Developer s Manual LS Centrality COMMUNICATIONS Register file Address Counter Figure 51 DMA Configuration Register file For the detail about register file please refer to the section of DMA Controller Registers 8 3 3 Basic DMA Operations 8 3 3 1 Single and Burst DMA As we specified before the DMA has two data transfer modes single transfer mode and burst transfer mode In single transfer mode the DMA controller executes one 32 bit word read write at a time while in burst mode 4 32 bit words a time The user can select the transfer mode by programming one of the register bit in DMA controller There is one thing needs to be notified in burst mode the DMA address is better to be in 16 DWORD boundary Otherwise the transfer will be split into multiple single word transfers in the system bus Because the system bus does not allow the non aligned burst transfer 8 3 3 2 1 D and 2 D DMA The Atlas II DMA controller supports both 1 D 2 0 DMA In 2 0 DMA the system memory space is interpreted as a 2 D layout instead of linear 1 D layout More specifically the system memory can be conserdered as multiple data lines The length of the data line is determined in the user selected DMA_WIDTH register The user can specify a data window that the user wants to access by three parameters e Start
298. endpoint e USB OTG Endpoint Done Enable Register USBOTG FC DONE EN 0 0074 Name Default 1 b0 R W EVEN EPnOUTDN_EN R W Description Endpoint n IN Done Enable When SET allows endpoint lt n gt IN direction to generate done interrupts The Endpoint lt n gt InDoneEnable must be SET for both immediate and SOF marker interrupts Endpoint n OUT Done Enable When SET allows endpoint lt n gt IN direction to generate done interrupts The Endpoint lt n gt OutDoneEnable must be SET for both immediate and SOF marker interrupts e USB OTG Endpoint Done Toggle Bits Register USBOTG FC TOGGLE BITS 0x0078 _____ Default Description ODD EPnINTOG 1 bO R W EVEN EPnOUTTOG R W e 5 Frame Number and Endpoint Ready Clear Register USBOTG_FC_FRM_NUM 0x007C Centrality Communications Inc 202 Description Endpoint n IN Toggle Bit This register is a toggle register Writing a 1 will toggle the value and writing a 0 will leave it unchanged The expected value of the current data PID is determined by the hardware from the last PID from the host for that endpoint Software should change this bit while the EP is currently full or disabled if they wish to change the next data toggle bit Endpoint n IN Toggle Bit This register is a toggle register Writing a 1 will toggle the value and writing a 0 will leave it unchanged the value of the nex
299. er Register Software must write to this bit to tell the Core whether or not the Endpoint is ready to be transferred If this bit is 0 and the EP is enabled then the function controller will return NAKs If this bit is 1 then the transfer will commence This bit is ignored if the EP is not enabled Bi Default Description commence This bit is ignored if the EP is not e USB OTG Immediate Interrupt Register USBOTG FC IMM 0x006C Name Default Description Bit ODD 1 bO Immediate n IN Interrupt R W When SET the Function controller will assert an interrupt immediately instead of waiting until the SOF EVEN IMnOUTINT 1 bO Immediate n OUT Interrupt R W When SET the Function controller will assert an interrupt immediately instead of waiting until the SOF Centrality Communications Inc 201 AT460A BI Developer s Manual Centrality COMMUNICATIONS 5 Endpoint Done Status Register USBOTG_FC_DONE_STATUS 0 0070 Bit Name Default EVEN EPnOUT_DONE 170 Description Endpoint n IN Done Status When asserted indicates that endpoint lt n gt IN has transferred all of the data currently set in the Function Endpoint Descriptor Endpoint n OUT Done Status When asserted indicates that endpoint lt n gt OUT has received all of the data currently set in the Function Endpoint Descriptor or the endpoint has received larger than the MaxPacketSize for this
300. erO RISC System Bus Master1 System Bus Master2 I O Bridge System Bus Master3 System Bus Master4 PCI Bridge When the bus master wants to access the memory bus it must own the bus first To own the bus the master must assert the request signal the System Arbiter can then grant the bus to the master with the grant signal 4 3 DRAM Controller 4 3 1 1 Overview The Atlas II DRAM Controller supports the following configurations e 200MHz DDR SDRAM at 2 5V 138MHz SDRAM at 3 3V The DRAM Controller supports both 16 bit and 32 bit data bus In 16 bit mode two consecutive pieces of data each 16 bits wide is fetched by the memory interface and returned to system memory as a 32 bit wide data The memory mapping from DRAM to system memory is done automatically through hardware logic 1 SRAM Controller is in PCI Subsystem Please refer to the corresponding section in PCI Subsystem for more details Centrality Communications Inc 30 AT460A BI Developer s Manual Centrality The following tables show some examples of DDR SDRAM configurations DDR SDRAM Configurations for a 16 bit Data Bus DDR SDRAM Type DDR SDRAM count Total Size byte 1 16 2 4 BMI 16MIS2M 16 1 32 64 32 16 4 128 Table 10 DDR SDRAM Configurations of 32 bit Data Bus DDR SDRAM type DDR SDRAM count Total Size byte 1 16 4MIBM Table 9 16 1 4 128 32 16 128
301. erated The first is when the last data is written to the card as specified by data length and Busy signal is released The second is when data transfers are stopped at the block gap by setting STOP AT GAP the SD HOST 0 Register and data transfers completed After valid data is written to the SD card and the busy signal is released Note TRAN END has higher priority than DAT TIMEOUT ERR If both bits are set to 1 the data transfer can be considered complete 0 No Data Transfer Complete 1 Data Transfer Complete Centrality 0 to 1 When the HD writes this bit to 1 to clear this status the status of the CARD_INSERTED in the SD_CUR_STA register should be confirmed Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated 0 Card State Stable or Debouncing 1 Card Inserted 7 R W CARD REMOVE 1 bO This status is set if the CARD INSERTED in the SD STATE register changes from 1 to 0 When the HD writes this bit to 1 to clear this status the status of the CARD INSERTED in the SD STA register should be confirmed Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated 0 Card State Stable or Debouncing 1 Card Removed 8 R W CARD INT Writing this bit to 1 does not clear this bit It is cleared by resetting the SD card interrupt factor I
302. eri E Rede 10 Figure 36 32 bit Data Fix latency Read BURST_READ 1 DWORD ACCESS 1 5 0 repr e en tes a o pub ews 10 Figure 37 32 bit Data Fix latency Write BURST_WRITE 1 DWORD_ACCESS 1 BUS WIDTH 70 1 2 VARI 0 10 Figure 38 32 bit Data Fix latency Write BURST_WRITE 0 DWORD 55 1 BUS_WIDTH 1 VARIZAGGO ctii at iet cate cue DUREE DEL oce Pans teo 10 Figure 39 16 bit Data Variable latency Read BURST_READ 0 DWORD_ACCESS 0 BUSSWIDTEZ41 bos tete dee e esee datei a i d 10 Figure 40 16 bit Data Variable latency Write BURST_WRITE 0 DWORD_ACCESS 0 BUS WIDTH 1 1 200 10 Figure 41 SD Host Block Diagram sess rnm rnnt rnnt rnnt nnns 10 Figure 42 USB OTG Controller Block 10 Figure 43 Block Diagram of USB OTG 10 Figure 44 PCMCIA Block Diagram sss enne nennen nnn etre nnns 10 Figure 45 Connect to Compact Flash 22 22220 4 0 0 enemies 10 Figure 46 _ PCMCIA Memory 1 2 enne 10 Figure 47 Peripheral Subsystem Diagr
303. errupt 3116 15680 e DSP Interrupt to RISC Register 05 INT TO RISC RISC 0x64 DSP 0x1C61 Bit Name _ Default _ Description 0 INT_RISC 1 bO The interrupt status bit RISC writes 1 to this bit will clear the interrupt 151 150 31 16 MSG TO RISC 16 h0 Message bit to RISC with the interrupt operation DSP R writes to this register will interrupt the RISC e DSP General Data Register 05 GEN REGO RISC 0x80 DSP 0x1C80 0x1C81 Bit Name Default Description 15 0 DATA_L 16 h0 The general registers used to exchange the R W information between RISC and DSP RISC had the priority to write this register R W e DSP General Data Register 05 GEN REG1 RISC 0x84 DSP 0x1C82 0x1C83 Bi Name Default Description t 15 0 DATA_L 16 h0 The general registers used to exchange the ue m information between RISC and DSP RISC had the priority to write this register 31 16 Same as above R W e DSP General Data Register DSP GEN REG2 RISC 0x88 DSP 0x1C84 0x1C85 Bit Name Default Description 15 0 DATA_L 16 h0 The general registers used to exchange the R W information between RISC and DSP RISC had the priority to write this register 31 16 DATA H 16 h0 Same as above R W e DSP General Data Register 05 GEN REG3 RISC 0x8C DSP 0x1C86 0x1C87 Bit Name Default Description DATA_L 16 0 The general registers used to exchange the Centrality Communications
304. erved e System to PCI Bridge Time Out Register SYS2PCI TIMEOUT 0x0010 Bit Name Default Description 15 0 R W TIMEOUT 15 16 hffff System to PCI Bridge timeout value 0 gt 76 S Reseved System PCI Bridge timeout value is 16 bit register that control the retry number on PCI side If a read write from RISC is retried for more than TIMEOUT times then this command will be discarded An interrupt will occur if user set the interrupt enable bit If this value is set to 0 retry number time out will never occur 7 2 2 PCI Bridge DSP IO Registers To Access PCI from DSP side System to PCI Bridge contains specific registers to convert the 16bit access on DSP side to 32 bit access on PCI side Table 33 PCI Brid DSP byte Address Register Description lt 5 0 gt 0x0000 0x0002 e DSP IO Register Mappin 0x0004 0x0006 0x0008 0x000a Others Cd Reserved To perform a read operation DSP needs to 1 DSP need to write SYS2PCI DSP ADDL SYS2PCI DSP ADDH for correct PCI address 2 Write SYS2PCI DSP OPERATE with correct BE RW 1 3 Poll SYS2PCI DSP OPERATE until RDY 1 4 Read data from SYS2PCI DSP DATAL SYS2PCI DSP DATAH To perform a write operation DSP needs to Write SYS2PCI DSP ADDL SYS2PCI DSP ADDH for correct PCI address Write SYS2PCI DSP DATAL SYS2PCI DSP DATAH for write data on PCI Write SYS2PCI DSP OPERATE with correct BE RW 0 Poll SYS2PCI DSP OPERATE until RDY 1
305. es that the YOUT buffer of endpoint n has been filled by the host e USB OTG XY Interrupt Enable Register USBOTG FC XY INT EN 0x0058 Bit Default Description XYnININT EN 1 bO XY Buffer of Endpoint n IN Interrupt Enable R W EVEN XYnOUTINT EN 1 bO XY Buffer of Endpoint n OUT Interrupt R W Enable e USB OTG X Buffer Filled Status Register USBOTG FC X STATUS 0x005C Bit Default Description ODD XFILLnIN 1 bO XIN Filled of Endpoint n R W When a bit is asserted it indicates to the Hardware that the n X Buffer has been filled and the function controller can begin sending the data on the next IN This register is a toggle register If it is set writing a 1 will clear it If itis cleared writing 1 will set it Writing a 0 has no effect EVEN XFILLnOUT XOUT Filled of Endpoint lt n gt R W When a bit is cleared it indicates to the Hardware that the n X Buffer has been drained and the function controller can begin receiving data from the next OUT This register is a toggle register If it is set writing a 1 will clear it If itis cleared writing 1 will set it Writing a 0 has no effect e USB OTG Y Buffer Filled Status Register USBOTG FC Y STATUS 0x0060 Bit Default Description ODD R YFILLnIN YIN Filled of Endpoint lt n gt EVEN YFILLnOUT YOUT Filled of Endpoint lt n gt R e Endpoint Enable Register USBOTG FC
306. eserved O 0x0848 USBOTG DMA ETD CLR ETD DMA Channel Clear Register egister 0x091C USBOTG ETD7 START ADDR ETD7 System Memory Start Address Register Ox920 0x97C f ___ __ 0x0980 USBOTG EPO OUT START ADDR EPO OUT System Memory Start Address Register 0x0984 USBOTG EPO IN START ADDR EPO IN System Memory Start Address Register 0x0988 USBOTG OUT START ADDR EP OUT System Memory Start Centrality Communications Inc 190 AT460A BI Developer s Manual Centrality Address Register Address Register Address Register Address Register Address Register 0x099C USBOTG EP3 IN START ADDR EP3 IN System Memory Start Address Register a ______________ 0x0A10 USBOTG ETD4 BUF ETD4 DMA Buffer Xfer Ptr Register poi Ox0A80 USBOTG EPO OUT BUF PTR EPO OUT DMA Buffer Xfer Ptr Register 0 0 84 USBOTG IN BUF EPO IN DMA Buffer Xfer Ptr Register 0x0A88 USBOTG EP1 OUT BUF PTR EP1 OUT DMA Buffer Xfer Ptr Register USBOTG BUF PTR IN DMA Buffer Xfer Ptr Register 0 0 90 USBOTG 2 OUT BUF EP2 OUT DMA Buffer Xfer Ptr Register 0 0 94 USBOTG 2 IN BUF 2 IN DMA Buffer Xfer Ptr Register 0x0A98 USBOTG EP3 OUT BUF PTR OUT DMA Buffer Xfer Ptr Register Ox0A9c USBOTG EP3 IN BUF PTR EP3 IN DMA Buffer Xfer Ptr Register Ox1000 Ox11FC DATA buffer add
307. esigned to output a clock frequency range between 50 400MHz The working modes are the same as PG13A1G3 Normal mode Power Down mode and Bypass mode 1 When Fin is 12MHz NR has to be 1 Centrality Communications Inc 43 460 Developer s Manual Centrality Rdivider Sbit Fdivider Butter Output Output Control logic Divider Driver Opi Figure 13 PG13E3G Block Diagram In Normal mode operation it is necessary to set suitable divider settings to make sure PLL functional e PLL Divider Value Setting There are divider values NR NF NO to set the PLL output clock frequency Four o Input Divider Value NR NR R lt 3 0 gt Feedback Divider Value NF 2 F lt 7 0 gt o Output Divider Value NO See Note Not allowed 1 e PLL Output Frequency Setting Four NF NR NO X Fin 1 When OD 2 or 3 FOUT would have around 50 duty cycle So it s suggested to set OD 2 or 3 if it s possible Centrality Communications Inc 44 460 5 LS Centrality COMMUNICATIONS Meanwhile the following constraints must be followed 2MHz lt Frer lt 8MHz where Frer Fin NR See Note 200MHz lt Fyco lt 400 2 where Fyco Fin NF NR For example if we want to get a 192MHz output frequency clock when using 12MHz crystal oscillator as input NR 2 NF 64 NO 2 384 2 Four 192 2 F lt 7 0 g
308. ess Register Description lt 11 0 gt lt 6 0 gt 0x000 GPIOO CTRLO GPIO control for GPIOO Centrality Communications Inc 85 460 Developer s Manual KS Centrality COMMUNICATIONS 0 004 0 008 0 00 0 010 0 014 0x018 Ox01C 0x020 0x08 GPIOO_CTRL8 GPlOcontr forGPIO8 0 024 0 028 0 02 0 030 0 034 0x038 0x03C GPIOO CTRLi5 GPlOcontr forGPIO15 0x040 0x044 0x048 0 04 0x13 0 CTRL19 GPIO control for GPIO19 0x050 0x14 GPIO0_CTRL20 GPIO control for GPIO20 0x13 0 054 0 058 0x05C 0x060 0x064 0x068 0x06C 0x070 0 074 0 078 0 07 0x080 0 084 0 088 0 08 GPIOO INT STATUS group0 interrupt status for RISC 0 90 0 _ EMEN no o pee c f Reserved 1 o 0x100 GPIOi CTRLO __ GPIO controlforGPIO32__ 0 104 GPIOi CTRL GPIO control for 603 0 108 CTRL2 GPlOcontr forGPIO34 0 10 GPIO controlforGPIO35__ 0 110 9 1 CTRLA GPIO control for 1 36 0 114 CTRL5 GPIO control for 07 GPIO controlforGPIO38_ CTRL7 GPIO control for 6039 GPIOi CTRL8 X GPlOcontrlforGPIO40 GPIOi CTRL9 GPlOcontr forGPIO41 GPIOi 0 GPlOcontro forGPIO42 GPIOi CT
309. essary This bit is cleared on hardware reset Flash hold control This bit is set upon exit from sleep mode and indicates that the Flash interface NAND amp NOR gets the hold of pins otherwise the pins will be held by GPIO so that the chip can boot from it after sleep The CPU can clear this bit by writing a one to it after the boot is done and then the pins will be released to GPIO again The CPU can also enable this bit if necessary This bit is cleared on hardware reset 315 1270 e Power Manager Scratch Pad Register PWR SCRATCH PAD 0x0010 Bit Default Description SP lt 31 0 gt 32 h0 Scratch Pad value e Power Manager Oscillator Status Register PWR_OSC_STATUS 0x001C Bit Name Default Centrality Communications Inc Description 52 AT460A BI Developer s Manual Centrality 0 R OSC OK 150 Oscillator OK This bit is cleared on a hardware reset and set after the 32KHz oscillator has stabilized 1 R OSC PD 1 0 12MHz Crystal power down 1 Crystal is in power down mode 0 Crystal is activated 31 2 _____ Reserved 0 0 e Power Manager Clocks Switch Register SWITCH 0x0020 Default Description SYS CS 2 00 System Clock Source Select 00 gt 12MHz crystal 01 gt Select PLL1 as the system clock source 10 gt Select PLL2 as the system clock source 11 gt 32KHz USB_CS 2 b00 USB Clock Source
310. etching one source for the ROP not the Pattern which is designed lying in internal SRAM For example as SRCAND BLT one DMAR will be configured to fetch the source image data and the other DMAR will be configured to fetch the destination image data Centrality Communications Inc 138 AT460A BI Developer s Manual Centrality DMAR is designed BURSTA that is every REQ GNT there will 4Dword fetched should also take charge of BYTE aligned barrel shift DMAR will barrel the data fetched in before writing them into the FIFO in a way as following Source BYTE Des BYTE Barrel Shift To FIFO position position Direction 0 efit byte ___ Directly eft bytes __ Directly Directly 10 Right 1 byte Delayed Nd rectly Directly 3 bytes Directly 2 Right 2 Delayed ___________ ________ Right 1 byte Delayed 2 Directly byte ___ Directly Right 3 bytes Delayed PCC Right 2 bytes Delayed Right 1 byte Delayed PSN rectly 1 Data SDRAM is little Endian 2 Directly means the current Read Data from the System Bus need no additional data in the next Read Data in fact some high bytes will be used by the next Read Data So the current will be directly stored into the FIFO 3 Delayed means the current Read Data from the System Bus will be merged with the following data t
311. fect this bit 1 Enable 0 Disable This bit enables wakeup event via CARD REMOVE assertion in the Normal Interrupt Status register FN WUS Wake up Support in CIS does not affect this bit 1 Enable 0 Disable There are three cases to restart the transfer after stop at the block gap Which case is appropriate depends on whether the HC issues a Suspend command or the SD card accepts the Suspend command 1 Ifthe HD does not issue Suspend command the CONTINUE REQ shall be used to restart the transfer 2 Ifthe HD issues a Suspend command and the SD card accepts it a Resume Command shall be used to restart the transfer 3 Ifthe HD issues a Suspend command and the SD card does not accept it the CONTINUE shall be used to restart the transfer Centrality Communications Inc 173 AT460A BI Developer s Manual Centrality Any time STOP AT BLK stops the data transfer the HD shall wait for TRAN END the SD INT STATUS register before attempting to restart the transfer When restarting the data transfer by CONTINUE REQ the HD shall clear STOP GAP before or simultaneously NOTE The Hardware Driver shall maintain voltage on the SD Bus by setting SD BUS to 1 in this register when wakeup event via card interrupt is desired e SDIO Host Control Register 1 SD HOST 1 0x002C At the initialization of the HC the HD shall set the SDCLK FR
312. flush the invalid data and prepare to accept the new data 12 R W USP RX TIMEOUT 1 bO If this bit is become 1 it means that since the last data had been received in the fifo there is no more new data received for then time specified by the timeout bit number in the USP AYSNC PARAM REG 13 R W USP TX ALLOUT 1 If this bit is become 1 it means that the data in both tx fifo and tx shifter has been transmitted out 0 disabled 1 enabled pers Rees e USP Pin I O Data Register USP PIN IO DATA ARM9 0x1C DSP OxE These bits can only be accessed by the ARM9 DSP when the corresponding pins of the USP are in I O mode Bit Name Default Description RFS PIN VALUE Pin value of GPIO function RFS 1 R W TFS PIN VALUE Pin value of GPIO function TFS Pin value of GPIO function RXD 4 R W Pin value of GPIO function SCLK lt 31 5 gt f 17 Reserved e USP ARM9 DSP Mode Register USP_RISC_DSP_MODE 9 0x20 DSP 0x10 This register can only be written by 9 For DSP it s read only Centrality Communications Inc 323 AT460A BI Developer s Manual Centrality Bit Name Default Description 0 R W RISC DSP SEL 1 bO 0 the USP is accessed by ARM9 1 the USP is accessed by DSP 311 __ 13110 Reserved e USP ASYNC PARAMETER Register USP AYSNC PARAM ARM9 0x24 DSP 0x12 This register can only be written by 9 For DSP it s
313. for Master Mode Vertical Sync LCD VSYNC WIDTH 0x3C 11 WIDTH UNIT 1 bO 1 7 Vertical sync pulse width defined below is in number of R W lines 0 Vertical sync pulse width defined below is in number of pixels Usually this bit is set with 1 10 0 VSYNC WIDTH 11 hO For master mode where Atlas I Processor generates the RAW sync signals this value defines the width of the horizontal sync pulse in either number of lines or number of pixels depending on bit 11 above For slave mode this register has no effect Bit Name Default Description The actual width is VSYNC_WIDTH 1 lines or pixels 3112 120 Note There are some conditions that must be satisfied 1 HSYNC PERIOD HSYNC END 2 VSYNC PERIOD gt VSYNC_END 1 3 HSYNC PERIOD MAX SCN HEND OSD HEND OSD2 HEND 4 VSYNC PERIOD MAX SCN VEND OSD VEND OSD2 VEND 6 2 4 3 Screen Control Registers The following registers specify certain modes and parameters for the display For example the timing control registers determines whether the pixel clocks and the sync signals are driven by Atlas II Processor or by the display and whether the signals are active high or low The display mode registers Centrality Communications Inc 109 460 Developer s Manual Centrality sets the display data format and the output format The RGBSEQ register determines the pixel sequence for those displays that requires one color at a
314. for the YUV to RGB transform CAM_YUV_COEF1 0x018 Bit Name Default Description 3130 Reserved Green Coefficient for the YUV to RGB transform CAM YUV COEF2 0x01C Bit Default Description 9 0 R W 10 h00 V coefficient for 19 10 R W 10h00 U coefficient for Centrality Communications Inc 278 AT460A BI Developer s Manual Centrality 29 20 R W 10 100 coefficient for 31 30 e Blue Coefficient for the YUV to RGB transform CAM YUV COEF3 0x020 Bit Name Default Description 10100 V coefficient for 3130 Reseved e Offset for the YUV to RGB transform CAM_YUV_OFFSET 0x024 Bit Name Default Description 31 30 Reserved e Camera Interrupt Control Enable Register CAM INT 0x028 Bit Name Default Description e Camera Interrupt Control Register CAM INT CTRL 0x02C Bit Default Description this interrupt will be generated Write a 1 to this bit will reset it bit will reset it this bit will reset it 313 __ 7 Reserved e Camera VSYNC Control Register CAM_VSYNC_CTRL 0 030 Bit Name Default Description 15 0 R W VSYNC_ACT_NUM 16 h0000 VSYNC active width in the number of HSYNC 31 16 VSYNC BLANK NUM 1610000 VSYNC blank width in the number of R W HSYNC e Camera HSYNC Control Register CAM HSYNC CTRL 0x034 Bit
315. gister _____ 0x054 0x2A 0x2B CAM FIFO OP FIFO operation register 0x058 0x2C 0x2D STATUS FIFO status register 0x05C Ox2E Ox2F CAM RD FIFO DATA FIFO data e Camera START Register 5 0 008 Bit Name Default Description 15 0 R W XS lt 15 0 gt 16 h0000 The value of start column of the active region 31 16 R W YS lt 15 0 gt 1610000 The value of start row of the active region e Camera END Register CAM END 0x00C Bit Default Description 15 0 R W XE lt 15 0 gt 16 h027F The value of end column of the active region 31 16 R W lt 15 0 gt 16 hO1DF The value of end row of the active region e Camera Control Register CAM CTRL 0x010 Bit Default Description 0 PIXCLK generate from external sensor 1 PIXCLK generate internally 0 HSYNC generate from external sensor 1 HSYNC generate internally 0 VSYNC generate from external sensor 1 VSYNC generate internally S z T 50 50 4 R W HSYNC_INV Invert the polarity of input HSYNC VSYNC_INV Invert the polarity of input VSYNC 6 RIW 50 50 SINGLE 1 b1 1 b1 Capture one frame image 1720 Continuous capture 1 PIXCLK sampled by IOCLK 0 Input pixel data is YCrCb format 11 9 R W YUV FORMAT 30000 Raw pixel data input sequence 000 YUYV YCrYCb 001 UYYV CrYYCb 010 YUVY YCrCbY 011 UYVY CrYCbY 100 YVYU YCbYCr 101 VYYU C
316. h baud rate when the frequency of IOCLK is low such as 12MHz the value of SAMPLE DIV can be changed to other value larger than 15 The exact high baud rate can be get if adjust both SAMPLE DIV and IOCLK For example if IOCLK is 12 2 to get baud rate of 115200 set the SAMPLE DIV to 25 and IOCLK DIV to 3 e UART Interrupt Enable Register UART INT EN RISC 0x54 DSP 0x2A Bit Default Description 0 disabled 1 enabled 1 R W TX DONE INT EN Transmit done interrupt enable 0 disabled 1 enabled 2 R W RX OFLOW INT EN 1 enabled all data is transmitted interrupt enable 0 disabled 1 enabled IO DMA receive interrupt enable 0 disabled 1 enabled Receive overflow interrupt enable 4 R W IO INT EN Receive FIFO full interrupt enable 0 disabled 1 enabled Transmit FIFO empty interrupt enable 0 disabled 1 enabled Receive FIFO threshold interrupt enable 6 R W RXFIFO FULL INT EN 7 R W TXFIFO EMPTY INT EN 8 R W RXFIFO THD INT EN 1 enabled g 0 disabled 9 R W TXFIFO THD INT EN ul Transmit FIFO threshold interrupt enable 0 disabled 1 enabled 10 R W FRAME ERR INT EN UART error frame interrupt enable 5 R W TX IO DMA INT EN 1 bO IO DMA transmit interrupt enable 0 disabled 1 enabled 1 bO 0 Centrality Communications Inc 308 AT460A BI Developer s Manual 0 disabled 1 enabled EN
317. h timer set controls how long a PC card cycle s command that is noe nwe niord or niowr active time will be in terms of the internal clock cycles The overall command time will be C 2 x Nval 1 The value of C representing the number of clock cycles for the command active is then multiplied by the clock period and the actual command active time is obtained Default Description 5 0 R W CMV lt 5 0 gt 6 3 9 Command Multiplier Value This field indicates the integer value Nval from 0 to 63 it is used to control the length of command active time 7 6 6 HO Reserved M6730 Recover Timing 0 1 Register M6730 REC TIMING 0 1 Index 0x3C Ox3F There are two separate Recovery Timing registers each with identical fields The recovery timing registers for each timer set controls how long a PC card cycle s recovery that is noe nwe niord or niowr time will be in terms of the internal clock cycles The overall command recovery time will be 2 x Nval 1 The value of R representing the number of clock cycles for the command recovery is then multiplied by the clock period and the actual command recovery time is obtained Centrality Communications Inc 247 AT460A BI Developer s Manual Centrality Name Default Description 5 0 m lt 5 0 gt 6 h02 Recover Multiplier Value This field indicates the integer value Nval from 0 to 63 itis used to control the command recovery ti
318. hO1FF FCOO 4 PAD EN 32 hFFC3 0000 GPIO5 PAD EN 32 h0000 0000 Please refer to the pin description list for what pins are enabled as GPIO by default Actually all peripherals except NOR NAND Flash interface are enabled as GPIO by default Bit Default Description 31 0 PAD_EN lt 31 Depend GPIO PAD MUX control R W 0 gt S 1 the pin is used by GPIO 0 the pin is used by other block e GPIO Wakeup eanble Register WAKEUP 0 5 Only GPIO group 0 5 can function as wake up Default Description WAKEUP E 32 h0 GPIO wake up enable N lt 31 0 gt 0 in sleep mode the corresponding GPIO will not wakeup the chip 1 in sleep mode the corresponding GPIO will wakeup the chip GPIO INTERRUPT STATUS Register GPIOx INT STATUS This register contain the interrupt status of all GPIOs in group x This register is read only write to this register have no effect To clear the interrupt write the INT_STATUS bit in GPIO Control register instead Bit Default Description 31 0 INT STATUS 32 h0 GPIO Interrupt Status R W lt 31 0 gt 0 No interrupt 1 There is interrupt request NOTE GPIO recommended operation modes e To Use as an input without interrupts set the GPIO as input and read its content Use as output set the output value first and then set the GPIO as output To Use as input which will generate an interrupt First mask the interrupt
319. has no effect After power up the default value is unknown Bit Name Unit Source Module Description IP31 System 0 R 29 R IP28 27 R Peripheral 26 R 25 R IP24 R LCD Controller LCD LCD Controller LCD 2D service request 2D IP23 R Serial Port 3 Serial Port 3 service request IP22 R Serial Port 2 Serial Port 2 service request IP21 R Serial Port 1 Serial Port 1 service request IP20 R Serial Port 0 Serial Port 0 service request IP19 R System System related block interrupt This interrupt is the bit or of IOBG SYS2PCI PCIARB CPUIF SYSARB These interrupt are for test only 18 R IP17 R IP16 R IP15 R Centrality Communications Inc 60 AT460A BI Developer s Manual Centrality Flash IP13 R YUV _____ IPI2 R IP11 Poe AM request access interrupt RISC information access DSP information 1 7 8 IP6 R 1 5 R GPIO EaR M 8 PR 1 2 R 1 PR GPIO interrupt request IPO GPIO interrupt request e Interrupt Controller IRQ FIQ Pending Register INT_IRQ_PENDING INT_FIQ_PENDING RISC 0x0004 0x0008 IP10 PE IP10 PE 9 uit d The INT PENDING the INT FIQ PENDING contain one flag per interrupt 32 total that indicates an interrupt request has been made by a unit Inside the interrupt service routi
320. hat is the current data should be latched for the next cycle maybe the next burst use This DMAW module takes charge of storing back the data after ROP operation into SDRAM The ROP module takes charge of Boolean operation including ROP2 Binary Raster Operations and ROP3 Ternary Raster Operations For detail of ROP2 and ROP3 definitions please see also BLT register There are two 9 Dword deep FIFOs for the storage of ROP operands 6 3 7 2D BitBLT Engine Registers Table 30 BitBLT Engine Regsiter Mapping RISC Address Register Description lt 11 0 gt 0x1C00 BLT_CONTROL The working mode and successive BLT command number 0x1C04 BLT_INT_MASK The BLT interrupt source mask 0x1C08 BLT_INT STATUS The BLT interrupt source and status 0x1COC BLT SRC BASE The source base memory address byte alignment Centrality Communications Inc 139 460 Developer s Manual Centrality address byte alignment 0 1 14 BLT_WINDOW_DIM The 2D window width and height specified in pixels source and destination window share the same dimension specified in pixels window and window y direction 0x1C20 BLT_DES XY The xy coordinate of the destination clipping rectangle The bottom right xy coordinate of the clipping rectangle 0x1C2C BLT FCOLOR The foreground color 0x1C30 BCOLOR The background color source destination 0x1C3C BLT_ROP The ROP code pixel format Clip mode color key enable Writing
321. he FIFO data register which is the bottom of the RX_FIFO 8 8 Univeral Serial Port 8 8 1 Overview Universal Serial ports are used for serial communication where only 1 bit is transmitted at a time The advantage of a serial port is that it requires relativley few pins so it is often more cost effective than parallel ports especially in long range communication The serial port is a general purpose interface that transmits or receives data a bit at one time and used for almost any type of devices There are 3 main categories PC peripherals modem mouse and printer etc Centrality Communications Inc 313 460 Developer s Manual Centrality e Communication devices Cable modem ISDN and xDSL etc e Embedded systems A D D A converters RF modules and serial EEPROMs etc The Altas I USP Universal Serial Port is a multi function serial interface to communicate with many common serial ports Universal does not mean that it can interface with any kind of serial devices but compared to the existed designs the Atlas 1 USP has better expendability configurability and flexibility The user can set the transfer frame parameters such as data length transmitting data length etc to configure out the right frame format According to different connection protocols it can be configured as a full duplex asynchronous system that can communicate with peripheral devices such as CRT terminals an
322. he HD should not use this status 7 5 USB OTG Interface 7 5 1 Overview The USB OTG interface is specifically designed and optimized for embedded applications It is particularly suited for self powered mobile small form factor and high volume peripherals It provides an intermediate SRAM for data transfer to from the application area to USB OTG interface Below is a functional block diagram of the USB OTG interface Internal USB PCI to AHB PCI BUS use Transceiver Tm Charge Pump Internal SRAM Figure 42 USB OTG Controller Block Diagram The USB OTG interface uses the USB OTG IP core provided by TransDimension Inc It is through this IP core that the USB OTG interface communicates with the actual USB transceiver USB OTG interface has the following features Host Controller Features USB Specification Revision 2 0 fully compliant USB Host Controller for full speed 12Mb s and low speed 1 5Mb s operations Advanced architecture resulting in easy programming and low microprocessor overhead In hardware ETD data structure management and scheduling to support simultaneous operation of up to 8 active USB pipes True transfer level operation with transaction scheduling and handling data sequence toggle error re try etc carried out in hardware Reliable isochronous transfer with loose timing requirements on the microprocessor Over current protection on host side if an over current condition occurs
323. he display data and two overlay data from the DMA controller and performs the bus protocol to transfer the data to the corresponding FIFO for each datapath The arbitrator for the DMA is moved into the outside BUS ARB to arbitrate the requests from the main display the second overlay the overlay2 along with requests from the 2D block Each datapath contains a 128x32bit FIFO to temporarily store data bursts from the DMA controller for the datapath to process The FIFOs send requests to the Bus Master DMA Interface when they are not full When they are almost empty they can send a high level request to the Bus Master Interface The levels for these requests can be programmed by registers The Main Display Datapath also named as SCN datapath processes the main display data that is the first DMA channel data from the FIFO The main display data can be defined as 1 2 4 8 12 or 16 bit per pixel image The datapath decomposes the pixel data from the 32 bit FIFO data according to the correct ordering The Second Overlay Datapath also named as OSD datapath is similar to the Main Display Datapath in function but processes the second overlay data The second data which means the second DMA channel data is defined for the half panel of the dual panel display The overlay data can be defined as 2 4 8 or 16 bit per pixel image And it is defined for only a sub portion or equal of the main display Centrality Communications I
324. he first type of divider can divide the input by 1 2 3 4 6 8 12 and 16 while the second type can only divide the input by 1 2 4 8 and 16 So there are 8 clock outputs for the first type and only 5 clock outputs for the second type 1 when Fin is 12MHz NR has to be 2 6 Centrality Communications Inc 45 AT460A BI Developer s Manual Centrality 5 2 6 3 8 to 1 4 5 to 1 MUX Because the clock divider for system clock domain has 8 different clock outputs 1x 1 2x 1 3x 1 4x 1 6x 1 8x 1 12x and 1 16x the MUX follows it will be an 8 to 1 MUX While the MUX follows the clock dividers in USB CKO_0 and CKO_1 domains will be 5 to 1 MUX In the system clock domain there are 4 8 to 1 MUX s in total They are used to generate the clocks for e CPU e System bus including Memory DSP e O In other clock domains USB 0 and 1 there is only 1 5 to 1 MUX in each domain The reason to have multiple 8 to 1 MUX in system clock domain is that the clocks to different parts of internal logic CPU Bus Memory DSP and IO can be different although they must be generated from a single source There is a register PIWR CLK RATIO that controls the different ratios of those clocks in system domain And software programmer needs to be aware of that there are certain limitations of the different configurations All the configurations supported in Atlas II are listed in the following table Table
325. he layout of the Receive Buffer is similar to the Transmit Buffer described in the previous section Indeed the configuration used was chosen specifically to be compatible with the layout of the Transmit Buffer Again it is important to distinguish between Standard Frame Format SFF messages and the Extended Frame Format EFF messages The Receive Buffer is subdivided into descriptor and data fields The first byte of the descriptor field holds frame information It describes the frame format SFF or EFF specifies remote or data frame and gives the data length This is then followed by either two identifier bytes for SFF or four bytes for EFF messages The data field contains up to eight data bytes Table 87 Receive Buffer Layout Standard Frame Format SFF Extended Frame Format EFF Centrality Communications Inc 339 AT460A BI Developer s Manual Centrality bit layout of the Descriptor Field of the Receive Buffer is shown below first for SFF then for EFF Table 88 Descriptor Field of Receive Buffer Receive Frame SFF CAN RD Adaress BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO 0x0040 FF RTR 0 DLC3 DLC2 0x0048 RIR o o o Receive Frame EFF Address BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO 0x0040 FF RTR DLC3 DLC2 10 2 0 0048 0 004 10 12 10 11 10 40 109 8 10 7 106 05 1D 0
326. he power manager And for wakeup event it s normally triggered by the GPIO After wakeup event triggered it takes at least 5 RTC cycles maybe more to raise the PWR EN signal again And after that it takes some other RTC cycles At least 3 but generally it will be much more so that the power supply and crystal can be stabilized to exit the sleep mode In the exit of the sleep mode the memory pins will be released 5 3 12 Power Manager Registers Table 17 PWR MGR Register Mapping RISC Address Register Description lt 11 0 gt 0 0014 0x0018 ________________ Reserved 2 PWR_OSC_STATUS 0x0024 Reserved 7 Power Manager PLL1 Configuration Register 1 Please refer to the previous sections about clock switching To switch the clock ratio when clock source is not 12 MHz may incur the unexpected result Please refer to the related document for more details about the wakeup Centrality Communications Inc 50 AT460A BI Developer s Manual Centrality Power Manager Clock Enable Register oxoose Reseved Others e Power Manager Control Register PWR_CTRL 0x0000 Bit Name Default Description 0 W SLEEP 1 Force the system enter sleep mode 1 W MEM STOP 1 bO 1 Force the DRAM controller to stop It needs to hold long enough at least 2 refresh cycles to make sure the DRAM controller is stopped 31 1 30 Reser
327. hip will detect BATT VDD fault and enter into sleep mode automatically e GPS Pin Pin Name GPS GPIO After reset GPIO will have control over these pins User can write corresponding GPIO control registers to give the control of these pins to GPS e LCD Pin Pin Name LCD GPIO X L BIAS XLDDO X D GPIO group offset 24 X LDD 7 GPIO group2 offset 31 GPIO group0 offset 8 X LDD 15 GPIO group0 offset 15 After reset GPIO will have control over these pins User can write corresponding GPIO control registers to give the control of these pins to GPS If only 8 bit LCD is used then X LDD 8 X LDD 15 can still be used as GPIO Flash Video Input Port Pin Mux Video Input Port NAND Flash GPIO 1 Please refer to the section of GPIO for detail information about GPIO groups Centrality Communications Inc 76 AT460A BI Developer s Manual Centrality X PXCLK PXCLK F RY BY GPIO group1 offset 18 X HSYNC HSYNC DF RE B GPIO group1 offset 17 X VSYNC VSYNC DF WE B GPIO group1 offset 16 X PXD 0 PXD 0 DF AD 0 GPIO group1 offset 15 X PXD 15 PXD 15 DF AD 7 GPIO group1 offset 0 DF ALE DF CLE DF AD 8 DF AD 13 X GPIO 27 GPIO 26 ___ After reset NAND Flash will have control over these pins User can write corresponding GPIO control registers to give the control of these pins to GPIO The priority of the above shared functions is as following e
328. hout wait cycles Three sizes can be defined as indicated below 00 512 byte 01 1024 byte 10 2048 byte 11 Reserved 20 8 D e 21 HIGH SPEED SUP This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 MHz 0 High Speed Not Supported 1 High Speed Supported 21 f Reserved 23 R 1 b1 This bit indicates whether the HC supports Suspend Resume functionality If this bit is 0 the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend Resume commands 0 Not Supported 1 Supported 1 3 3 V Supported 1 3 0 V Supported 1 1 8 V Supported 3127 Reserved 2 NOTE The Host System shall support at least one of these voltages above The HD sets the SD BUS VOL SEL in SD HOST 0 register according to these support bits If multiple voltages are supported select the usable lower voltage by comparing the OCR value from the card Centrality Communications Inc 184 AT460A BI Developer s Manual Centrality SDIO Maximum Current Capabilities Register SD_MAX_CURR 0x0048 These registers indicate maximum current capability for each voltage The value is meaningful only if the corresponding Voltage Support bit is set in the Capabilities register Bit Name Default Description MAX_CUR_33V Maximum Current for 3 3V 15 8 R MAX CUR 30V Ma
329. i directional RFS Receive Frame Sync X SCLK n Bi directional Serial Clock NOTE For the Pin Names means 0 to 5 Centrality Communications Inc 314 AT460A BI Developer s Manual Centrality Each pin of USP be configured to USP function or I O function Firstly you should configure pins of USP to be USP function If you only use some of five pins for serial interface the rest can be set to I O mode They are set in the register USP_MODE_REG1 You can read or write the USP_PIN_IO_DATA register if you configure it to be INPUT or OUTPUT mode 8 8 4 Functional Description There are five USPs in the Atlas II USP1 5 Each USP has three interfaces 1 RISC 2 DSP 3 DMA interface The USP can be accessed through either I O or DMA interface In I O mode either the RISC or DSP can access the USP In DMA mode it is controlled by the DMA controller in the I O Bridge Each USP be configured to DMA interface independently The five USPs share four 4 DMA channels channels 8 11 Please refer to the section of DMA Controller for more details All the registers can be accessed in I O mode by the RISC or DSP but they cannnot access these register simultanenously A register named USP_RISC_DSP_MODE can be only written by the RISC and it decide the USP is accessed and controlled by the RISC or DSP If it is 0 the RISC accesses the the USP only Because the DSP data bus is 16 bit if the DSP accesses the
330. i eia 10 CAN Bus Address Mapping 204004 0 enne eaa nnne t nent nnns 10 CAN DMA Register Mapping essere enne nnne 10 Transmit Buffer nnne a innen senten antennes nnne a a 10 Descriptor Field of Transmit Buffer 10 Receive Bunter OR REA Rie edo 10 Descriptor Field of Receive Buffer 10 Filter Bit Patterns 10 CAN Bus DMA Register 10 PWM Interface Register 10 GPS Pin Descriptions ir Mo UC til bete 10 ATA460A BI PirioUt icis cbe eee eee vete ee Do deep aee aerea eL ae duae aee 10 Recommended Operating Conditions essen emen 10 DC Electrical Specifications nnne 10 Drive Capability of Atlasll Output 10 ESD Characteristics ac un one eet et PU ota t pde dn 10 POWePr DISSIPAUOM m UEM 10 Thermal Resistance 10 ClocksErequencles u P Ue see spp oh uit 10 Xo MING THUG e eic rere 10 Minimum pulse width for external interrupts to be 10 S
331. ian write read 0 big endian write read 314 CODEC RX FIFO Control Register CODEC RX FIFO CTRL OxFC8 RW RW ENDIAN Default Description Bit R W DWORD 7 2 FIFO_THD lt 5 0 gt 6 hO A threshold in byte to trigger an interrupt R W An interrupt is triggered when the count of data in the FIFO reaches the threshold ______ 2210 e CODEC FIFO Level Check Register CODEC RX FIFO LEVEL CHK OxFCC Default Description FIFO_SC Stop check in DWORD High check in DWORD RW R W 3124 Cd ____ Reserved pq 13 10 FIFO LC 4 Low check in DWROD R W ho ho ho Centrality Communications Inc 302 AT460A BI Developer s Manual Centrality e CODEC FIFO Operation Register CODEC FIFO OP OxFDO Default Description 0 R W FIFO_START 1 bO Start the read write transfer when this bit is declared 1 R W FIFO RESET 1 bO Internally link to FIFO START INI Set to 1 to stop the FIFO and reset the FIFO internal status including the relevant interrupt status Set to 0 in normal operation 312 aoho Reserved 0 e CODEC RXFIFO Status Register CODEC FIFO STS 0xFD4 This register indicates the RX FIFO status Bit Default Description 0 R W RX FIFO FULL 1 bO RX FIFO full status 1 RX FIFO is in full state 0 RX FIFO is not in full state
332. if GPIO has control over these pins only GPIO can control the pin e Else the pin is distributed automatically between ROM NAND Flash IDE PCMCIA Bit 4 0 in RSC ROMPAD MUX register controls whether that block will be included in the distribution Notes Since PCMCIA port will not co exist Bit 0 and 3 in RSC ROMPAD MUX can not be 1 at the same time ROM Part 2 NAND Flash Part 2 IDE Part 2 Mux Pin Name ROM NAND Flash IDE GPIO xrcEBS3 cs B lt 3 gt X GPlOgroup4offset21 X FCE B2 xrcEB 2 DrcsB 2 X X jGPlOgroup4offset20 XFCE B1 xrcEB DrcsB t 4 19 xrcEBO cs 2 PIO group offset 29 2 ___ 2 GPIO group offset 28 OX FRE J GPIO group3 offset 27 XFBEO xrs amp EO 1 GPiOgroup30ffset26 _FRDY_B X FRDY B CL IDE_IORDY_B GPIO group3 offset 25 DE BY 3 10 205 B __ group4 26 LCS BO JIDE CSB O group4 offset 25 _ ____________________ DREQ GPIO group offset 24 DE DAC DE DACK GPlOgroup4offset23 JIDE IRQ GPlOgroup4offset 22 After reset GPIO will have control over pin X FCE B 3 0 X FBE 3 0 and X FRDY B User can write corresponding GPIO control registers to give the control of these pins to GPIO or ROM NAND Fl
333. ifferent bus masters The arbiter can support up to 4 bus masters but in Atlas II there are only one bus master DMA Controller All the other peripheral modules are under control of DMA Controller to accomplish the memory accesses 8 2 Bridge 8 2 1 Overview The I O Bridge transfers data between the I O Memory Bus Masters and system memory In the Atlas II the I O Masters are allocated as the following table Table 62 Memory Bus Masters Masters Block Name MasterO DMA Controller Centrality Communications Inc 249 AT460A BI Developer s Manual Centrality Master2 The I O Bridge is a slave device responding to an I O Master s data transfer request To transfer data the I O Master will request for bus access from the I O Bridge The I O bridge block will do the arbitration internally and grant the I O memory to the I O master Then the I O master will release a read or write command to the I O Bridge For read commands to the Bridge it will first read data from system memory and store it in FIFO and then transfer it to the master For a write command the Bridge will first read data from the I O master and store it in a FIFO and then transfer it to system memory 8 2 2 I O Bridge Registers The I O Bridge s address space is shared with the DMA address space 0 000 0000 0 000 FFFF The I O Bridge occupies address space from offset
334. iliary input slot selection only one slot allowed to be valid 0 Slot input is disabled 1 Slot input is enabled Bit 0 input frame Slot5 selection Bit 1 input frame Slot6 selection Bit 2 input frame 51017 selection Bit 3 input frame 51018 selection Bit 4 input frame 51019 selection Bit 5 input frame Slot10 selection Bit 6 input frame Slot11 selection 7 2510 Reserved e CODEC TX FIFO DMA Control Register CODEC TX AUX IO CTRL 0xB80 Bit Default Description 0 write to CODEC 2 FLUSH Flush the DMA receive FIFO in case the DATA_LEN set at the peripheral side doesn t match the DWORD size set in the DMA control 3 RW_ENDIAN 0 4461 280 e CODEC TX FIFO Control Register CODEC TX AUX FIFO 0xB88 Description RW DWORD 7 2 FIFO_THD lt 5 0 gt A threshold in byte to trigger an interrupt R W An interrupt is triggered when the count of data in the FIFO reaches the threshold 318 2450 e CODEC TX FIFO Level Check Register CODEC TX AUX FIFO LEVEL 8 Name Description RW EL mm RW R W R W 3124 80 Reseved Centrality Communications Inc 297 460 Developer s Manual Centrality e CODEC TX_FIFO Operation Register CODEC TX AUX FIFO OP 0XB90 Default Description 0 R W FIFO START Start the re
335. in Bayer RGB Mode with 1 4 Ratio in Row and 10 Contraction in YUV YCrCb Mode YUVRGB 1 with 1 2 ratio in Row and Column 10 Contraction in YUV YCrCb Mode YUVRGB 1 with 1 4 ratio in Row and Column 10 Active Region coe eren red Oe re I po RR FRE Sea MERE ek dE c dene 10 Block Diagram of Audio CODEC 10 AC link Output Frame Read Command Diagram 10 AC link Output Frame Write Command Diagram eese 10 AC link Input Frame Command 10 AC97 PCM Record Functional Block Diagram 10 AC97 PCM Record 044 40 A ennt eene nenne nettes 10 Stereo Mode Flowchart 1 11 1 1 1 0 nennen nennt 10 Mono Mode Left Right Flowcharts 44450000 10 AC97 PCM Playback Functional Diagram 10 UARTO Functional Block Diagram 10 CAN Bus Interface Connection nnne nnne 10 CAN Bus TIMING eee Pet rae agde uet cerea ee ete bee ee ees 10 Diagram of GPS 2 444 22200 enne nnne N enter entren 10 Timing Diagram X
336. ine number for the second active R W OSD display This value along with the horizontal start and end position and the vertical end positions define the rectangle for the second active OSD display 31 14 J21h0 Reseved o e Horizontal end position for the second active OSD screen LCD OSD2 HEND 0x28 Bit Name Default Description 31 11 Reserved 10 0 11780 Horizontal End Position pixel number for the second RAW active OSD display This value along with the horizontal start position and vertical start and end positions define the rectangle for the second active OSD display zu Centrality Communications Inc 106 460 Developer s Manual Centrality e Vertical end position for the second active OSD screen LCD_OSD2_VEND 0x2C Name Default Description 10 2 0502 VEND 110 Vertical End Position in line number the second R W active OSD display This value along with the horizontal start and end positions and vertical start position define the rectangle for the second active OSD display This line is not included in the display region as indicated in Figure 8 even OSD is not clipped IRAN OSD2 SETTING VALID Confirm the new Region and DMA setting by writing this bit with 1 This bit is self cleared after being written with 1 Remark Refer to the remark of OSD SETTING VALID 3112 200 NOTE SCN layer s setting valid bit is bound with its DMA START bit
337. ing Sym Description Min Max Units MEM CLK period Delay from write command to first risingedge of MDQS Tmem 02 1 1 5 ig Centrality Communications Inc 366 AT460A BI Developer s Manual Centrality x_mclkb_o Ly Ly Ly Control signal X Wie X Wie Wie x_dqs Data Strobe Was EN 1 tdgss i 1 1 1 1 NOTE Control Signals composed of RAS CAS MEM WE CS CS1 EN Figure 81 DDR SDRAM Memory Write Timing 9 4 13 Camera Specifications when camera work on master mode pixclk x vsync x hsync are output x pxd pixel data are input Table 108 Camera data Timing Sym Description Min Max Units Vsync output vala time ______ _____15 m Vemehodime o2 s Hayne output vaid tme 18 m m Heyne output holdtime os s input setup time ___ 08 s the input hold time Centrality Communications Inc 367 AT460A BI Developer s Manual Centrality thvaild thha x_hsync thd gt tsu gt gt i pix_data Figure 82 Camera data Timing 9 4 14 Lcd Specifications when Icd work on master mode pixclk x_vsync x_hsync are output Table 109 Lcd data Timing sym Description i Frame output valid time Frame hold time Line output hold time bias output hold time 04 m
338. ing Write 1 clear the interrupt pending 0 no effect 31 3 e Reserved System to PCI Bridge Master abort interrupt When there is master abort on PCI bus the current access will be cancelled A master abort interrupt will be generated System to PCI Bridge Time out interrupt When an access on PCI bus is terminated with retry gt TIMEOUT times the current access will be cancelled A time out abort interrupt will be generated PCI Bridge Write Buffer Enable Register SYS2PCI WRITEBUFFER 0x000C Bit Default Description 0 R W 1 bO System to PCI Bridge write buffer enable 1 enable write buffer 0 disable write buffer When write buffer is enabled RISC IO write to PCI device will be finished right away when System to PCI Bridge FIFO is ready to hold the command Then System to PCI Bridge will transfer the command into the FIFO on PCI bus But the write operation will only be truly finished when the command is issued on PCI bus and finished Centrality Communications Inc 151 AT460A BI Developer s Manual Centrality It is recommended to set the write buffer to enable which will speed up to write operation However user needs to perform a read to the same address to guarantee the write is really finished on device System to PCI Bridge read mode 1 read will wait for current transfer to system memory finish 0 IO read have no relation with transfer to system memor 31 22 __ Res
339. ing a 2 dimensional DMA The X size determines how many consecutive 4 DWORD bursts are in a line the Y size determines how many lines are required for the current display and the SKIP value determines the number of BYTE s to skip at the end of a line to get to the beginning of the next line Finally the base address specifies the starting address of the DMA The DMA is activated by setting the starting address so it is necessary to set the base address register last after all the other registers have been set With this type of definition any subset of a larger display memory can be specified to be used as the current display memory This may be especially useful for zooming or panning in a large memory The OSD and screen DMA s are configured identically A bit in the 0502 BASE OSD BASE SCN BASE register allows each DMA to operate in continuous mode This means that the DMA will repeat itself automatically with the exact same settings after it is completed for continuous display This saves the software from always having to generate DMA s Clearing this bit can stop the continuous DMA Centrality Communications Inc 128 460 Developer s Manual KE Centrality COMMUNICATIONS DMA Memory Starting Address X size Skip Y size Figure 27 LCD Controller DMA Memory Layout Starting Address N Figure 28 LCD Controller DMA Memory 2 D Layout Centrality Communications Inc 129 AT460A BI
340. ini Setto 1 to stop the fifo and reset the fifo internal status including the relevant interrupt status Set to 0 in normal operation 312 Reserved e CANBUS FIFO Status Register CANBUS FIFO STATUS 0 14 In case FIFO is full the value of this register is 0 thus user must concatenate FIFO FULL bit with this value to determine the actual data count in the FIFO 5 R W FIFO FULL 1 bO Fifo full status the fifo is full when read out as 1 This bit is concatenated with FIFO LEVEL to be the actual FIFO data count 6 R W FIFO_EMPTY 1 Fifo empty status equivalent to FIFO FULL FIFO LEVEL 77 CANBUS DMA Channel Register CANBUS_DMA_CHANNEL 0xF20 Bit Name Default Description Bit Name Default Description O R W SEL 1 bO 0 CANBUSO selected 1 CANBUS1 selected 7 3fn0 Reserved NOTE This register only exits in CANBUSO And the bit0 only take effect when DMA mode enabled e CANBUS DMA Message Counter Register CANBUS MSGONT 0xF24 Bit Name Default Description 15 0 R W MSG COUNT 16 hO The number of messages should be transferred 0 means unlimited Centrality Communications Inc 343 460 Developer s Manual Centrality 31 16 ________ 160 e CANBUS DMA Interrupt Register CANBUS DMA INT OxF28 The interrupt will be generated in DMA mode when one of the things below happens 1
341. insert wait states while accessing those devices The users can change the number of wait states that can be programmed by setting the wait state register There are only three exceptions 1 When the RISC accesses the variable latency IO device the cycle maybe variant in length 2 When RISC access the DSP shared memory through IDMA port 3 When RISC read from the Flash ROM controller at boot up the latency is also variable The following table shows the internal register mapping Table 2 Internal Register Mapping Address Range Device Mapped Clock Domain 0x800B_0000 Ox800B_FFFF Reserved 0x8012_0000 Ox8FFF_FFFF Reserved _ _ O Centrality Communications Inc 16 AT460A BI Developer s Manual Centrality 0x9008_0000 Ox9FFF_FFFF Reserved ______ 0xA002_0000 OxAFFF_FFFF_ _____ 0 001 0000 0 00 FFFF ___ Reserved 1 0xB011_0000 OxBFFF_FFFF_ Reserved 2 2 2 3 RISC Subsystem Registers Table 3 RISC Subsystem Register RISC Address Register Description lt 11 0 gt Others d 0x0014 RISCINT_WAIT2 RISC Interface FIFO Flush Register RISCINT FIFO FLUSH 0x0000 The RISC interface has three post write FIFO one for cacheable memory accesses one for non cacheable memory accesses and the other for I O accesses The FIFO will be flushed in the following cases e The FIFO is full and there are more data written e Inter
342. into this register will start the BitBLT operation immediately when configured as not auto mode 0 1 48 BLT_CMDQUE_ADDR When BLT was configured as auto mode this register contains the first BLT command address in SDRAM and every command is 16 DWORD lengths Writing to this register will start the successive BLT if in auto mode BitBLT hardware working mode setting BLT CONTROL 0x1C00 Name Default Description AUTO ThO BLT working mode as command queue mode when 1 single command mode when 0 eae _______ IM 31 16 160 When configured as command queue mode this R W contains the queued BLT commands number When read this register reflects the remaining BLT number Single command mode BLT hardware works as one command by one Software will program BLT hardware with one setting and start it before this is finished software will not allocate another Command queue mode Centrality Communications Inc 140 AT460A BI Developer s Manual Centrality Software prepares queue of BLT commands with data structure defined by BLT hardware memory and by telling the command number and queue memory address BLT hardware will fetch these commands and execute one by one Also when one queue is not finished software should not allocate another queue The command structures please refer to BLT_CMDQUE_ADDR notes e BitBLT interrupt mask
343. ion EE 10 8 6 7 Audio CODEC E A ENEAN 10 10 8 7 1 eu 10 8 7 2 Pin Description EE 10 8 7 3 Functional Description eiga rrt er ea er RE dere ER Ce RESP OR CE tue 10 8 7 4 UART Registers ic ee ae LI Le 10 8 8 Univeral Serial Port eene enne rennen nennen nnn nnn nnne nennen nens 10 8 8 1 OI Ed EE 10 8 8 2 Supported Protocols and 10 8 8 3 Pin Descr iO EIER 10 8 8 4 Functional DESCrIPUON eee ee e ea 10 8 85 USP Regista S 10 8 9 Bus Controller 220 2 40020 0 0 0 66000001 000000000 0000000 10 8 9 1 P 10 8 9 2 10 8 9 8 CAN Bus Registers 10 8 10 e 10 8 10 1 Overview 0 244 25 1 00000000000 0080 000 nnns 10 8 10 2 PWM Registers 10 8 11 GPS THEE qu eren RE 10 BAT
344. ion of system activity when a high to change is observed on the bvd1 nstschg nri signal input from the PC card e M6730 Megacell Information M6730 INFO Index 0x1F BL Description LEVEL 4 hxxxx This field contains the revision level of the M6730 megacell This field is to be decided by the customer DUAL SINGLE 1 b0 Megacell identified as a single socket controller 1 b1 Megacell identified as a dual socket controller This bit specifies that the M6730 supports two Sockets or one socket This bit always returns 1 b1 when read as the M6730 is a dual socket device 7 6 R f Host Adapter Identification 2 b00 Second read after I O write to this register Centrality Communications Inc 242 AT460A BI Developer s Manual Centrality 2911 First read after I O write to this register This field identifies the M6730 megacell After megacell reset or doing an I O write operation to this register the first read will return 11 The next read will return 00 This type of toggling on the reads can be used to identify the host adapter e M6730 ATA Control Register M6730 Index 0x26 Default Description ATA_MODE 1 bO ATA Mode 1 b0 Normal operation 1 b1 Configures the socket interface to handle ATA type disk drives This bit reconfigures the particular socket as an ATA drive interface R W SPKR LED Speaker is LED Input 1 b0 Norma
345. ircuit described as above there are two ways to change the clocks 1 Change the configuration of the PLL s 2 Change the clock sources 2 Change the clock ratios But certain constraints must be followed when switching between different clock configurations e When changing the clock ratios the clock source has to be the external 12 MHz crystal input e clock switching affects the DDR memory clock the DDR memory has to be put into self refresh mode during the switch 5 2 8 Real Time Clock Registers There is a programmable 16 bit divider DIV to divide the input 32 768 KHz clock to the frequency that users need E g 1 Hz The divided real time clock will be used to driven a 32 bit counter COUNTER that provides user the real time In each cycle of the divided real time clock there is a Hertz interrupt generated to the RISC User can also configure an alarm ALARM When the COUNTER matches the alarm there is an Alarm interrupt generated to the RISC Table 16 Register Mapping RISC Address Register Description lt 11 0 gt 0 0000 COUNTER RTC Counter Register 0 0004 RTC ALARM RTC Alarm Register 0x0008 RTC STATUS RTC Status Register 0 000 RTC_DIV RTC Division Register Others ____ Reserved RTC Counter Register RTC_COUNTER 0 0000 The RTC counter register RTC_COUNTER is a read write register and is not cleared by any reset source except the h
346. isplays the current status 2 R W SUSPDET 1 bO Suspend Detected When Software reads this bit to be 1 it indicates that the USB bus is in the SUSPEND state But it does not mean the function controller is in the SUSPEND state 0 indicates that the USB bus is not in the suspend state But it does not mean the function controller is not in the suspend state Writing a 0 leaves the hardware unchanged Writing a 1 sets the Function port in the SUSPEND state and sets the transceiver in the power savings mode It will not affect the value of the physical register bit 2 which Centrality Communications Inc 198 AT460A BI Developer s Manual Centrality merely reflects the status Note If SuspendDetected 1 it does not mean the Function controller is in the SUSPEND state It just means that the USB bus is in the suspend state Software needs to write 1 to set the Function Controller in the suspend state But the Function controller does not keep this state ina register 3 R W BADISOAP 1 b0 Bad ISO Accepted 1 function accept ISO packet with corrupted data 0 bad ISO packt are automatically dropped 6 4 Reserved 2 7 W SOFTRESET Software Reset Function Controller 3 8 2680 e USB OTG Device Address Register USBOTG FC DEV ADDR 0 0044 Bit Name Default Description 6 0 R W DEVADDR 7710 Device Address 317 1250 e USB OTG System Interrupt Status Registe
347. isters cce derer e iia d RT det dete dete aea ao 10 5 6 Reset Ier teste eret te ebbe e tts 10 56 5 OVGELVIGW et eer SRL RIETI 10 5 6 6 ResetScheme u coeno A tentus 10 56 7 10 5 6 8 Reset Controller Registers 10 5 7 Resource Sharing Controller reirante a aE A eene enne enne nnns nennen nnns 10 Centrality Communications Inc 2 AT460A BI Developer s Manual Centrality 5 7 9 DMA Sharing RR 10 res OMEN TESTO E scents 10 5 7 11 Resource Sharing Controller 10 58 icd esi ann cedar E E E A 10 58 12 seed a AE A 10 5 8 13 GPIO Registers NEATE sitet EE 10 BQ 10 59 14 m 10 5 9 15 PWM 0 10 6 Graphic Display 10 6 1 10 A ODEO aliro C 10000000000 10 6 2 1 RIMIS 10 6 2 2 Pin
348. it Name Default Description 31 0 W ETDnCLR 320 lt n gt Clear When SET indicates that ETD lt n gt is disabled This register cannot be read e USB OTG Immediate Interrupt Register USBOTG HC IMM INT 0x00CC Bit Name Default Description 31 0 IMnINT 320 Immediate lt gt Interrupt R W When SET the Host Controller will assert an interrupt immediately upon retirement of an ETD instead of waiting until the SOF e USB OTG ETD Done Status Register USBOTG HC DONE STATUS 0x00DO Bit Name Default Description 31 0 32 hO ETD lt n gt Done Status When asserted indicates that ETD lt n gt DoneStatus has been retired either through normal operation or through an error condition The CompletionCode field of the ETD should be read to determine the reason for retirement A complete list of completion codes is found in ETD completion code descriptions USB OTG Endpoint Done Enable Register USBOTG HC DONE EN 0x00D4 Bit Default Description 31 0 32 h0 ETD lt n gt Done Enable R W USB OTG Frame Number Register USBOTG HC FRM NUM 0x00E0 Bit Default Description Centrality Communications Inc 205 AT460A BI Developer s Manual Centrality 15 0 R 16 h0 Frame Number This contains the current frame number for the Host Controller This number is placed in the SOF packet used to signal the beginning of the new frame 31 16
349. it index 8 bit index 16 bit 5 6 5 5 5 6 6 5 5 and so on This mode is flexible but needs to calculate OSD2 CKEYB and OSD2 CKEYS values according to different data formats For 16 bit data format the 18bit CKEYB or CKEYS are calculated by expanding Red Green or Blue to 6bits and set the expanded LSB to 1 b0 3122 10 0502 color key small RGB value LCD OSD2CKEYS 0 0 Bit Name Default Description 17 0 OSD2_CKEYS 18 h0 Smaller value of color key for OSD2 channel display R W 31 18 __ 6 2 4 7 OSD Palette The OSD palette for OSD OSD2 is a four entry palette The index is determined by the 2 bit OSD pixel value when the OSD is in its active region Each palette entry contains the RGB value for the pixel and the mixing ratio that should be used Entry 0 is used when the OSD pixel value equals 2 b00 entry 1 is used when the OSD pixel value equals 2 b01 etc This palette is valid for both the first OSD OSD and the second OSD 0502 This Palette is only used by 2bpp mode OSD s OSD Palette Entry 0 LCD OSDPALO 0xA4 Note For bypass mode the LSB s of this register is used as the OSD value directly the number of bits corresponds to the display mode Mixing is performed normally for the 4 bit and 8 bit bypass mode but is not allowed for 12 bit and 16 bit bypass mode same as the following 3 registers Bit Name Default Description 7 0 R W BLUE Blue value for the OSD pi
350. ith identical fields Name Default Description 3 0 ES lt 23 20 gt 4 hO End Address 23 207 This register contains the most significant nibble of the address that specifies where in the memory space the corresponding memory map will begin Memory accesses that are equal or below this address and equal or above the corresponding System Memory Map Start Address will be mapped into the memory space of the corresponding PC card 5 4 Scratch pad bits 7 6 R W EARD SEL TIMER SEL 270 Card Timer Select 2 b00 Selects Timer Set O 2 b01 Selects Timer Set 1 2 b10 Selects Timer Set 1 2 b11 Selects Timer Set 1 This field determines the timer set Timer Set 0 and 1 reset to values compatible with the standard PCI and three wait state cycles e M6730 System Memory Map 0 4 Offset Address Low Register M6730 SM MAPO0 4 OAL Index 0x14 0x1C 0x24 0x2C 0x34 There are five separate System Memory Map Offset Address Low registers each with identical fields Bit Name Default Description 7 0 R W OA lt 19 12 gt 870 Offset Address lt 19 12 gt This register contains the least significant byte of the address that will be added to the system address to determine where in the PC card s memory map the memory access will occur M6730 System Memory 0 4 Offset Address High Register M6730_SM_MAP0 4_OAH Index 0x15 0x1D 0x25 0x2D 0x35 There are five separate System Memory Map Offset
351. ithin the Interrupt Enable Register Cleared when the release Receive Buffer command is issued provided there is no further data to read in the Receive Buffer Set whenever the Transmit Buffer Status changes from 0 to 1 released provided the TIE bit is set within the Interrupt Enable Register Set on every change set or clear of either the Bus Status or Error Status bits provided the EIE bit is set within the Interrupt Enable Register Set on a 0 10 1 transition of the Data Overrun Status bit provided the DOIE bit is set within the Interrupt Enable Register Set when bus activity is detected while the CAN controller is sleeping provided the WUIE bit is set within the Interrupt Enable Register Set when the CANBUS controller re enters error active state after being in error passive state or when at least one error counter exceeds the protocol defined level of 127 provided the EPIE bit is set within the Interrupt Enable Register Set when the CANBUS controller loses arbitration and becomes a receiver provided the ALIE bit is set within the Interrupt Enable Register Set when the CANBUS controller detects an error on the CAN bus provided the BEIE bit is set within the Interrupt Enable Register 318 240 e CANBUS Interrupt Enable Register CANBUSn IER 0x000C MD Bernui Description When set to 1 an interrupt will be generated when the Receive Buffer Status goes from 0
352. iting for a connection If the InsertionMode bit in HNP Timer3 Register is not set the timeout will cause the AwaitBConnectTimeOutlnterrupt Each unit is equivalent to 8 msec The default is Ox7d which is equivalent to 1 second 23 16 AWAITDISC 8 hC8 A Wait Disconnect Timer R W This timer is started by an A DEVICE when it enters the A SUSPEND state If the A DEVICE does not detect a downstream disconnect before a timeout then the A DEVICE can end the session 31 24 BWAITCONN 8 h4 B Wait Connect Timer R W This timer is used by a B DEVICE in the B WAIT CONN A state to wait for an A DEVICE to signal a connection If the A DEVICE does not connect before a timeout b wait conn tmout then the B DEVICE stops waiting for a connection NOTE The time unit is 1ms USB OTG HNP Timer2 Register USBOTG 2 0x0024 Name Default Description t 0 SRP Data Bus Pulse Width Defines the session request protocol data line pulse length generated by BDEVICE R W Defines the Session Request Protocol VBUS pulse length generated by BDEVICE 4 Bi RIW 45 10 Cd HO 31 16 BSRPFAIL 16 h138 B SRP Fail Timer R W 8 This timer is set by software to determine when a Session Request has failed The conditions of a failure are the VBUS must be over the b_session_vaild and the A_MASTER must drive a reset to the device e USB OTG HNP Timer3 Pulse Control Register USBOTG PULSE 0x0028 Bit Na
353. kage TOP VIEW Dimension n mm 5 460 Developer s Manual n m E es CONTROLLING DIMENSION MILLIMETER PRIMARY DATUM AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS BOTTOM VIEW THE SOLDER BALLS DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM THERE SHALL BE MINIMLIM CLEARANCE OF Q 25mm BETWEEN THE EDGE THE SOLDER BALL AND THE BODY EDGE REFERANCE DOCUMENT JEDEC MO 2D5 0006 0000 00000 aaoo nage 000000 TF324 SW1 we _ ET CODE TF32411 ENT REV ND DESCRIPTION DATE S F CHEN SHT Na CONTROLLED NOTE 5 JEDEC MO 205 INSTEAD OF 192 02 24 00 SILICONWARE PRECISION INDUSTRIES CO LTD 00000000 00000000 90000090050 357 Centrality Communications Inc Centrality 9 3 DC Electrical Characteristics 9 3 1 Absolute Maximum Ratings The tables in this section describe the DC Electrical characteristics Table 94 gives the absolute maximum ratings Table94 Absolute Maximum Ratings 1 Characteristic Symbol Supply voltage l O buffers VDDIO 0 3 4 V Supply voltage l O buffers XVDDIO 0 3 4 V Supply voltage mem bus VDD MEM 0 3 3 v DDR SDRAM VSSTL Supply voltage mem bus VDD_MEM 03 4 v SDRAM S
354. l configuration registers occupy the first 8 byte locations an identical set of registers for the Secondary channel occupy the 8 byte locations offset by 8 bytes from the primary channel locations The following is the register mapping Table 54 IDE Bus Master Control Register Mapping Address Register Description Offset 0 0 BMI RW CTRL Bus Master Read Write Control 0 1 pe 0 2 Netaffectoursystem e Bus Master Read Write Control Register BMI RW CTRL offset 0 0 Bit Name Default Description O R W START Start Stop Bus Master 1 Start 0 Stop DMA transfer is only enabled when this bit is true clearing this bit will halt Centrality Communications Inc 219 460 Developer s Manual Centrality data transfer Note If this bit is cleared while a bus master DMA operation is in progress the command will be abandoned and any data transferred from the IDE device discarded 21 29 Reserved 3 R W WRITE 1 bO Bus Master Read Write Control 0 Read 1 Write mm During a DMA transfer this bit is read only Note This bit must not be modified when bus master is active T4 4 __ Reserved e Bus Master Interrupt Status Register BMI INT STATUS offset 0x02 Name Default Description Bit 0 IDE_ACTIVE 1 bO Bus Master IDE Active This bit is set alongside bit 0 of the BMI RW CTRL register It is cleared after all data has
355. l operation 1 b1 The Card bvd2 nspkr nled signal will be used to drive 912 if Drive LED Enable is set This bit changes the function of the bvd2 nspkr nled signal from digital speaker input to disk status LED input When in I O Card Interface mode or ATA mode setting this bit to 1701 reconfigures the bvd2 nspkr nled input signal to serve as NLED input only This bit should be set to 1 bO if the interface is for Memory PC card 150 Scratch pad bit 3 R W 1 bO In ATA mode the value in this bit is applied to the ATA21 signal and is vendor specific Certain vendor specific performance enhancements beyond the PC card standard can be controlled through use of this bit This bit has no hardware control when not in the ATA mode 4 R W In ATA mode the value in this bit is applied to the ATA22 signal and is vendor specific Certain vendor specific performance enhancements beyond the PC card standard can be controlled through use of this bit This bit has no hardware control when not in the ATA mode 5 R W A23 VU In ATA mode the value in this bit is applied to the ATA23 signal and is vendor specific Certain vendor_specific performance enhancements beyond the PC card standard can be controlled through use of this bit This bit has no hardware control when not in the ATA mode 6 R W A23 M NS 1 bO In ATA mode the value in this bit is applied to the ATA24 signal and is vendor specific Centrality Communications I
356. lay drives pixel clock PCLK POLAR Invert pixel clock In master mode invert the internal pixel clock before output In slave mode invert input pixel clock before use by internal logic 1 Invert pixel clock i e pixel clock 72 phase off 0 Do not invert pixel clock 3 PCLK_EDGE 1 bO Determines whether pixel output changes on the rising or R W falling edge of the internal pixel clock 1 Pixel changes on falling edge of clock 0 Pixel changes on rising edge of clock 4 HSYNC IO 1 bO Horizontal sync signal master mode R W 1 Atlas I Processor drives horizontal sync 0 7 display drives horizontal sync 5 HSYNC POLAR 1 b0 Invert the horizontal sync signal In master mode invert the R W horizontal sync signal before output In slave mode invert the horizontal sync signal before used by internal logic 1 horizontal sync signal is active low Centrality Communications Inc 110 AT460A BI Developer s Manual KS Centrality hee 0 horizontal sync signal is active high 1 bO VSYNC IO Vertical sync signal master mode VSYNC POLAR HSYNC SEL 1 Atlas I Processor drives vertical sync 0 display drives vertical sync Invert the vertical sync signal In master mode invert the vertical sync signal before output In slave mode invert the vertical sync signal before used by internal logic 1 vertical sync signal is active low 0 vertical sync signal is active high External HSYNC selec
357. lds Default Description 7 1 cmm lt 7 1 gt 770 Offset Address lt 7 1 gt This register contains the least significant byte of the quantity that will be added to the system I O address that determines where in the PC Card s I O map the I O access will occur o bit must be programmed to zero e M6730 Card I O Map 0 1 Offset Address High Register M6730 CIO MAPO 1 OAH Index 0x37 0x39 There are two separate system I O Map Offset Address High registers each with identical fields Bit Default Description 7 0 R W OA lt 15 8 gt 810 Offset Address lt 15 8 gt This register contains the most significant byte of the quantity that will be added to the system address that determines where in the PC Card s I O map the I O access will occur M6730 System Memory 0 4 Start Address Low Register M6730 SM 4 SAL Index 0x10 0x18 0x20 0x28 0x30 There are five separate System Memory Map Start Address Low registers each with identical fields The following information about the memory map windows is important 1 The memory mapping register determines where in the PCI memory space and the PC card memory Space accesses will occur There are five memory windows that can be used independently Centrality Communications Inc 237 460 Developer s Manual Centrality 2 memory windows are enabled and disabled using the Mapping En
358. length in the transmit shifter in one RW transmit operation Must be set to actual tx shifter length 1 29 R W SLAVE CLK SAMPLE When sampling it by I O clock setting this bit can avoid the glitch of the slave SCLK 0 no filter for glitch of slave clock and the fmax of salve sclk is 1 8 of I O clock 1 filter for glitch of slave clock and the fmax of salve sclk is 1 10 of I O clock Ee EN jo In the ASYNC mode RS232 or IrDA this register has different meaning TX DATA LEN Data bit number 1 TX FRAME LEN Start bit number Data bit number Stop bit number 1 TX SHIFTER LEN Data bit number 1 The Parity bit is not supported in USP And the Stop bit number is not supported of 1 5 bit and should be set to TXD DELAY LEN bits in the USP MODE 2 register e USP Receive Frame Control Register USP RX FRAME CTRL 9 0xC DSP 0x6 0x7 Default Description lt 7 E gt DATA LEN 870 Received data length one frame R W Must be set to actual rx data length 1 158 RX FRAME LEN Receive frame length include active and idle R W state Must be set to actual_rx_frame_length 1 lt 20 16 gt RX_SHIFTER_LEN 5 0 Data length in the receive shifter in one R W transmit operation Must be set to actual rx shifter length 1 3121 2 J fthO0 Reserved In the ASYNC mode RS232 or IrDA this register has different meaning RX DATA LEN Data bit number 1 RX FRAME LEN Start bit
359. m Bus and PCI Bus For IO accesses the PCI Bridge will convert the RISC DSP IO accesses into PCI data transactions and passes to the corresponding PCI devices For memory access the PCI Bridge is both a master and a slave on the System Bus In most cases when PCI devices transfer data to from DRAM Controller the PCI Bridge acts as the bus master on the System Bus But in Some other cases user may select the SRAM Controller as the bus slave of some bus masters on the System Bus The following figure shows the block diagram of System to PCI Bridge Centrality Communications Inc 149 AT460A BI Developer s Manual gt Centrality E e umm Master PCI Slave PCI Master Internal PCI Bus 7777777 4 5 5555 Figure 33 Block Diagram of PCI Bridge Both RISC and DSP can access the System to PCI Bridge registers 7 2 1 Bridge RISC IO Registers Table 32 PCI Bridge RISC IO Register Mapping RISC Address Register Description lt 11 0 gt 0 000 SYS2PCI_WRITEBUFFER System to PCI Bridge write buffer set 0x0010 SYS2PCI TIMEOUT System to PCI Bridge timeout Others Cid Reserved e PCI Bridge Retry Value Register SYS2PCI RETRY 0x0000 Bit Name Default Description RETRY lt 5 0 gt System to Bridge retry value 3156 Resewed SYS2PCI RETRY is 6 bit register that control the retr
360. m uem v R W 1 gt enable dynamic power down 17 12 T_PDN 6 hO T PDN iis the number of system idle clocks R W When the system is idle more than T PDN clocks then DRAM will enter low power down mode CKE to DRAM will be asserted to low 3138 40 Reseved Centrality Communications Inc 35 AT460A BI Developer s Manual Centrality NOTE If user tries to write the read only bits PDN STATUS SF STATUS and DRAM RDY there might be unexpected results Memory Mode Register MEM MODE RISC 0xC Please refer user manual of DRAM from DRAM vendor e Memory Extend Register MEM EXTEND RISC 0x10 Please refer user manual of DRAM from DRAM vendor e Memory Initialization Register MEM START RISC 0x14 Bit Default Description 0 R RDY 0 gt DRAM is not ready to be accessed 1 gt DRAM is ready to be accessed 2 1 R W DRAM_INIT 11 gt Start DRAM initialization bus sequence if DRAM_RDY is 0 If DRAM_RDY is 1 the initialization is locked No programming can change DRAM internal registers Others gt no action HUM qme O o ee jee Write 0 to clear the reset Notes DRAM clock will be controlled by GPIO2_CTRL19 register On reset the DRAM clock is always enabled user can choose to disable DRAM clock output by software programming See DRAM application notes for detail description Centrality Communications Inc 3
361. me 7 6 210 __ Reseved M6730 Interrupt Status Register M6730 INT STATUS Index 0x80 Default Description 0 m MGT INT EN 1 bO Management Interrupt Enable 1 b0 the interrupt of the management is not enabled 1 b1 the interrupt of the management is enabled 1 R W CARD INT EN Card Interrupt Enable 1 b0 the interrupt of the card is not enabled 1 b1 the interrupt of the card is enabled 2 R W MGT INT STATUS 1 bO Management Interrupt Status 1 b0 the interrupt of the management is inactive 1 b1 the interrupt of the management is active 3 R W CARD INT STATUS 1 bO Card Interrupt Status UP 1 bO the interrupt of the card is inactive 1 b1 the interrupt of the card is active 74 daho Reseved Centrality Communications Inc 248 460 Developer s Manual Centrality 8 Peripheral Subsystem 8 1 Overview In Atlas II there are many peripheral I O modules not connected to the internal PCI Bus In another words they do not access the system memory through System to PCI Bridge Instead these I O modules are connected to the I O memory Bus and they access the system memory through the I O Bridge ARM926 DSP Core Core RISC DSP Interface Interface System Memory Bus ES Memory Bus 1 Figure 47 Peripheral Subsystem Diagram There is an arbiter inside of the I O Bridge to arbitrate the memory accesses from d
362. me Default Description 20 fe eno o O O 3 R W pem 1 b0 Use Session End Signal This bit should be set when a Session End Centrality Communications Inc 195 AT460A BI Developer s Manual LS Centrality COMMUNICATIONS VBUSPULSE Use VBus Pulse SRP Detection Use VBUS pulsing to detect session request by the B DEVICE Use Data Pulse SRP Detection Use data line pulsing to detect session request by the B DEVICE Insertion Mode Set When SET the HNP logic in Hardware HNP 5 R W DATAPULSE 6 R W INSERTION will disable the wait bcon tmout to allow for operation as a legacy host 15 7 R VBUSDISCHTIMER 9 hA VBus Discharge Timer Value W This value will be used in setting the waiting period that the Vbus will be discharged in order to get it below 0 8V This will be used in Hardware HNP mode when the B SESS END signal is not available such as when an OTG transceiver is being used B SESS END signal is available this timer will not be used and control of the Vbus discharge will be dependent on the signal In this case the user should set the USE B SESS END bit this register when this signal is available Each unit of time is 1 msec The default value is OxA which is equivalent to a discharge time of 10 msec 23 16 R A SDB WIN 8 h64 B Connect Short Debounce Window W This value is the maximum time the Hardware HNP should wait to do short de bouncing of the connection Once this timer expires
363. mined by the 1015 16 level returned by the card This bit controls the method that the width of the data path for the I O window 0 accesses to the card is determined Note that when this bit is 1 b1 the niois16 signal determines the data path width to the PC card Compatibility bit Timing Reigster Select 0 1 50 Accesses made with timing specified in Timer Set 0 registers 1 b1 Accesses made with timing specified in Timer Set 1 registers This bit determines the access timing specification for the window 0 Window 1 Size 1 b0 8 bit data path to I O Window 1 1 b1 16 bit data path to I O Window 1 When the bit 5 of this register is 1 b0 this bit determines the width of the data path for the O window 1 accesses to the PC card When the bit 5 is 1 b1 this bit is ignored AUTO SIZE IO WI 1 bO Auto size Window 1 N1 1 b0 I O Window 0 Size see bit 4 of this register determines the data path for I O Window 1 access 1 b1 The data path to I O Window 1 is determined by the niois16 level returned by This bit controls the method that the width of the data path for the window 1 accesses to Centrality Communications Inc 235 AT460A BI Developer s Manual Centrality card is determined Note that when this bit is 1 b1 the niois16 signal determines the data path width to the PC card ee TIMING REG SEL1 Timing Register Select 1 1 50 Acce
364. mode this bit determines whether the bvd1 nstschg nri input signal is used as the nri input so that the status is reflected in the nriout signal or not This bit is not valid in the Memory card interface M6730 Card Status Change Register M6730 CARD STATUS Index 0x04 This register indicates the source of a management interrupt generated by the M6730 For the management interrupts to be generated the corresponding enables should be set in the Management Interrupt register The management interrupts are acknowledged by reading from this register This register is used for the interrupt controlling Default Description Bit 0 R W BATT_DEAD STS_C 150 Battery Dead or Status Change HG 1 b0 A transition from high to low in Memory Card Interface mode or either high or low or low to high in I O card Interface mode on the bvd1 nstschg nri signal has not occurred since this register was last read 1 b1 A transition on bvd1 nstschg nri signal has occurred In a memory PC card interface this bit is set to 1 b1 when the bvd1 nstschg nri changes from high to low indicating a battery dead condition In the I O interface this bit is set to one when the bvd1 nstschg nri signal changes from high to low or from low to high In Card interface this bit is not affected by the fact that the nterrupt and General Control register bit 7 is set or not This bit is reset to 1 bO whenever this register is read 1 R W
365. mputational operation 3 2 Functional Description 3 2 1 DSP Memory 1 2X means the DSP runs at twice clock frequency as the system bus Centrality Communications Inc 21 AT460A BI Developer s Manual Centrality There re three memories in Atlas II DSP Subsystem e Program Memory PM e Data Memory DMX e Coefficient Memory DMY Three memory architecture allows the DSP core to fetch two operands in a single cycle one from coefficient memory and one from data memory In the same cycle the DSP core can also fetch the next instruction from program memory DM PM are further split to two parts part is accessed by DSP only named DMX in and respectively and another part can either be configured as accessed by DSP or accessed by DMA controller named DMX swap and PM swap respectively This gives flexibility to change program or move data when the DSP is running and is the compensation to small memory space The DSP can change memory settings by configure memory control registers and do DMA transfer by configure the DMA control registers DMX swap and PM swap can be configured as single buffer or double buffer When configured as double buffer the buffer is spitted into two parts one part is accessed by the DSP and another part is accessed by the DMA controller side When configured as single buffer the buffer is either accessed by the DSP or accessed by the DMA controller The size of DMX is 5K
366. n TIMER DIV SYS CLK TIMER CLK 2 1 Bit Default Description 15 0 DIV lt 15 0 gt 16 hO OS Timer clock division R W 3116 160 e OS Timer Latch Register TIMER LATCH 0x0030 When user writes 1701 into this register bit the value of the current OS timer counter will be latched into the TIMER_LATCHED_LO amp TIMER_LATCHED_ HI registers Name Default Description LATCH OS Timer Counter latch 31 a 31 hO Reserved R W e OS Timer Latched Low Register TIMER LATCHED LO 0x0034 The OS timer latched low register is the low 32 bit value of the 64 bit counter that latched when user write a 1 b1 into TIMER LATCH register Bit Name Default Description 31 0 LA lt 31 32 h0 The low 32 bit latched value R W 1 Note This is a write once bit that once written can only be changed after a hardware software or sleep mode reset Centrality Communications Inc 70 460 Developer s Manual Centrality e OS Timer Latched High Register LATCHED 0x0038 The OS timer latched high register is the high 32 bit value of the 64 bit counter that latched when user write 1 b1 into TIMER LATCH register Bit Default Description LA lt 63 32 h0 The high 32 bit latched value R W 5 6 Reset Controller 5 6 5 Overview The reset controller manages the various reset sources within the There 4 types of resets Har
367. n the same clock frequency until SDCLK is stopped Stop at SDCLK 0 If the HC detects the No Card state this bit shall be cleared 1 Enable 0 Disable Centrality Communications Inc 174 AT460A BI Developer s Manual Centrality Thus choose the smallest possible divisor which results in a clock frequency that is less than or equal to the target frequency 19 16 DAT_TIMEOUT_VAL This value determines the interval by which R W DAT line timeouts are detected Refer to the DAT_TIMEOUT_ERR in the SD_INT_STATUS register for information on factors that dictate timeout generation Timeout clock frequency will be generated by dividing the base clock TMCLK with this value When setting this register prevent inadvertent timeout events by clearing the DAT_TIMEOUT_ERR_EN in the SD_INT_EN 0x02 base clock divided by 4 0x01 base clock divided by 2 0x00 base clock 10MHz 63MHz Setting 0x00 specifies the highest frequency of the SD Clock When setting multiple bits the most significant bit is used as the divisor But multiple bits should not be set The two default divider values can be calculated by the frequency that is defined by the BASE FREQ for SD Clock in the Capabilities register 1 25 MHz divider value 2 400 KHz divider value The frequency of the SDCLK is set by the following formula Clock Frequency Base clock divisor register 1111 Reserved 1110 TMCLK 2 27
368. n 1 bit mode the HC shall detect the CARD INT without SD Clock to support wakeup In 4 bit mode the card interrupt signal is sampled during the interrupt cycle so there are some sample delays between the interrupt signal from the card and the interrupt to the Host system When this status has been set and the HD needs to start this interrupt service CARD INT EN in the SD INT EN register shall be set to 0 in order to clear the card interrupt statuses latched in the HC and stop driving the Host System After completion of the card interrupt service the reset factor in the SD card and the interrupt signal may not be asserted set CARD INT EN to 1 and start sampling the interrupt signal again 0 No Card Interrupt 1 Generate Card Interrupt Re ______________ EE ERR_INT If any of the bits of upper word of R W SD_INT_STATUS are set and the corresponding status enable bit are set too then this bit is set Therefore the SW can test for an error by checking this bit first 0 No Error 1 Error 16 CMD TIMOUT ERR 1 bO only if the no response is returned R W within 64 SDCLK cycles from the end bit of the command If the HC detects a CMD line conflict in which case CMD CRC ERR shall also be set This bit shall be set without waiting for 64 SDCLK cycles because the Centrality Communications Inc 178 AT460A BI Developer s Manual Centrality command will be aborted by the HC 0
369. n Completion Code If set the DMA controller will check the completion code of the transfer The data will only be transferred if the completion code shows no error 1 ARBMODE 1 bO Arbiter Mode Select 1 Puts the DMA arbiter in Round Robin mode The arbitration for the DMA servicing will proceed in a round robin fashion 0 Puts the DMA arbiter in Priority Access mode The DMA enabled transfers are serviced in a prioritized fashion in order of decreasing ETD EP number Zero gets highest priority 2 R W SKPRTRY 1 bO Skip on Retry Mode If set will skip current DMA transfer if an AHB RETRY response is encountered and will start next pending transfer The transfer will be retried after the rest of the pending transfers have been completed 3 R W ISOPRECFRM 1 b0 ISO OUT Previous Frame Mode If set the DMA will only service an ISO OUT ETD one frame before the transfer will start The frame number where the transfer will occur can be found in the StartingFrame field of the Host Isochronous ETD descriptor format Bis Reserved e USB OTG ETD DMA Channel Clear Register USBOTG CLR 0x0848 Bit Name Default Description 31 0 W ETDDMACHNCLR 320 ETD DMA Channel Clear Will clear the DMA channel corresponding to the bit that is set Will also clear the DMA enable bit for the ETD This register is a Write Clear register Software will always read 0 on this register USB OTG DMA Channel
370. n as 0 Enable write 1 write to ROM address will be written to ROM port 0 write to ROM address will be masked No write will occur on ROM port 31 30 BUS_WIDTH 2 b00 Define the bus width of ROM port R W 00 bus width is 8bit 01 bus width is 16bit 10 bus width is 32bit 11 reserved ROM CS2 Configure Register ROM CFG2 0x0008 R W R W R R W 29 R W ROM 2 controls the timing amp access mode for ROM port CS2 The detail register definition is the same as e CS3 Configure Register ROM CFG3 0x000C Centrality Communications Inc 157 AT460A BI Developer s Manual Centrality ROM CFG3 control the timing amp access mode for ROM port CS3 The detail register definition is the same ROM The following figures show some configuration examples X_FA i address 2 pum 14 12 15 i T6 Valid address 1 Figure 34 32 bit Data Fix latency Read BURST READzO DWORD_ACCESS 1 BUS WIDTH 1 VARI_ACC 0 X_FCE_B Valid address Figure 35 16 bit Data Fix latency Read BURST_READ 0 DWORD_ACCESS 0 BUS WIDTH 1 VARI_ACC 0 NOTE X_FD from ROM SRAM device will be latched 1 T clk_ edge pci ahead of X FOE B rising 1 T2 T3 T4 T5 6 T ok poi Centrality Communications Inc 158 AT460A BI Developer s Manual
371. n interrupt R W An interrupt is triggered when the count of data in the FIFO reaches the threshold 31 8 2480 e CODEC TX Level Check Register CODEC TX AUX FIFO LEVEL OXF8C Bit Default Description 9 4 RW __ Reserved 19 14 RW 60 Reseved 31 24 0 Reserved e CODEC TX FIFO Operation Register CODEC TX AUX FIFO OP 0 90 Bit Default Description 5 Start the read write transfer when this bit is declared 1 R W FIFO_RESET 1 bO Internally link to FIFO START INI Set to 1 to stop the FIFO and reset the FIFO internal status including the relevant interrupt status Set to 0 in normal operation 312 sono 2 e CODEC TXFIFO Status Register CODEC TX FIFO STS 0 94 This register indicates the TX FIFO status Bit Name Default Description 0 TX_FIFO_FULL 1 bO TX FIFO full status 1 TX FIFO is in full state 0 TX FIFO is not in full state It indicates the current TX FIFO full status Once the FIFO status changes the status bit is cleared automatically 1 TX 150 TX FIFO empty status 1 TX FIFO is in empty states 0 TX FIFO is not in empty states It indicates the current TX FIFO empty status Once the FIFO status changes the status bit is cleared automatically 2 R W TX FIFO OFLOW 1 b0 TX FIFO overflow status 1 TX FIFO overflow takes place
372. n progress until this signal is de asserted is not used X PC REG B Output In Memory Card Interface mode this output chooses between attribute and common memory In Card Interface mode this signal is active low X PC SPKR B Input In Memory Card Interface mode this input serves as the BVD2 battery warning status input In I O Card Interface mode this input can be configured to accept a card s NSPKR digital audio output X PC STSCHG B In Memory Card Interface mode this input serves as Centrality Communications Inc 222 AT460A BI Developer s Manual LS Centrality COMMUNICATIONS lt 2 1 gt m o the BVD1 battery dead status input In card Interface mode this input is the NSTSCHG input which indicates to the M6730 that the card s internal status has changed If bit 7 of the Interrupt and General Control register is set to 1 this signal serves as the ring indicate input for wake on ring system power management support These outputs are driven low by the Atlas II during card access cycles to control byte word card access X PC CE lt 1 gt enables odd numbered address bytes When configured for 8 bit cards only X PC CE lt 1 gt active and 0 is used to indicate access of odd or even numbered bytes These signals depend on the data size of the device at the PC card address and the Byte enables from the PCI bus This output goes active low to indicate
373. n read operation you should program the register index number into PCMCIA Configuration Register first too And after that you could read the PCMCIA Configuration Register the higher 8 bits is the data value you want to read out Table 57 PCMCIA Configuration Register POMCIA CONFIG 0x57C00000 Bit Default Description 7 0 8170 Register Index Number RW 15 8 VALUE 810 Register Data Value R W Centrality Communications Inc 225 AT460A BI Developer s Manual Centrality 126 60 Reserved 7 7 7 2 PC Card Space card may request I O space from system Atlas II from 0 57 0 0000 to 0x57D0_0000 will be PCMCIA I O space which will be converted to be 0 0000 0000 to 0 0000 FFFF by PCMCIA interface block as 64KB standard PCI I O space 7 7 7 3 PC Card Memory Space The PC card memory space is mapped from 0x2000 0000 to Ox2FFF FFFF When memory PC cards request memory from system the start and end addresses allocated in Atlas II will be written into M6730 window configuration register and M6730 will in charge of remapping the Atlas II address into physical PC card address 7 7 8 PCMCIA Interface Registers The M6730 s internal device control window mapping extension and timing registers are accessed through a pair of operation registers an index register and a data register The index register is accessed through base address 0 and the data register is accessed thro
374. nabled when BLK_CNT_EN in the Transfer Control R W register is set to 1 and is valid only for multiple block transfers The HC decrements the block count after each block transfer and stops when the count reaches zero It can be accessed only if no transaction s executing i e after a transaction has topped Read operations during transfer return an invalid value and write operations hall be ignored When saving transfer context as a result of Suspend command the number of blocks yet to be transferred can be determined by reading this register When restoring transfer context prior to issuing a Resume command the HD shall restore the previously save block count 0x0000 Stop Count 0 0001 1 block 0x0002 2 blocks OxFFFF 65535 blocks 5010 Command Argument Register SD CMD ARG 0x0008 Bit Default Description 31 0 CMD_ARG 320 The SD Command Argument is specified as bit lt 39 8 gt R W of Command Format e SDIO Transfer Control Register SD TRAN 0x000C Default Description SCENE 1 BLK CNT EN This bit is used to enable the BLK CNT in SD BLK register which is only relevant for multiple block transfers When this bit is 0 the Block Count register is disabled which is useful in executing an infinite transfer 0 Disable 1 Enable 2 R W AUTO CMD12 EN Multiple block transfers for memory require CMD12 to stop the transaction When this bit is set
375. nals Note that only the 49 and 410 work in the pulse mode where as the other IRQs are just interrupt sensors Speaker Enable 1 b0 nspkr out is high impedance 1 b1 nspkr out is driven from the of nspkr from each enabled socket This bit determines whether the card NSPKR signal will drive NSPKROUT ate qe 22 7 R W INPACK EN Input Acknowledge Enable The ninpack function is not applicable in the PCI bus environments This bit is provided for compatibility reasons The programming of this bit has no effect on the functionality of the M6730 e M6730 FIFO Control Register M6730 FIFO CTRL Index 0x17 Bit Name Default Description 6 0 170 Scratchbits FIFO_STATUS FLU SH 1 b1 FIFO Status Flush FIFO 1 b0 FIFO not empty No operation occurs 1 b1 FIFO empty Flush the FIFO This bit controls FIFO operation and reports FIFO status To reset the FIFO and the FIFO pointers write a1 b1 to this bit During read operations from this register when this bit is 151 the FIFO is empty During read operations when this bit is 1 bO the FIFO has valid data This bit is used to ensure the FIFO is empty before changing any register contents registers should not be modified while the write FIFO is not empty FIFO contents will be lost whenever any of the following occurs 1 nrst signal is active 2 The card is removed 3 Vcc power bit in the Power control regi
376. nc 243 AT460A BI Developer s Manual Centrality Certain vendor_specific performance enhancements beyond the PC card standard can be controlled through use of this bit This bit has no hardware control when not in the ATA mode 7 A25 CSEL 1710 In mode the value in this bit is applied to the ATA25 signal and is vendor specific Certain vendor_specific performance enhancements beyond the PC card standard can be controlled through use of this bit This bit has no hardware control when not in the ATA mode e M6730 Extend Index Register M6730_EXT_INDEX Index 0x2E Bit Name Default Description 7 0 R W EXT_INDEX 8 hO This register controls which of the following registers at index 2 be accessed Table 61 Extended Indexed Registers Extended Index Extended Register Description 10 00 Scratchpad 22 CoO Reserved Reserved Reserved e M6730 Extension Control 1 Register 6730 1 Extension Index 0x03 Bit Name Default Description 0 R W VCC_PWR_LOCK 1 b0 VCC Power Lock 1 b0 The Vcc Power bit bit 4 of Power Control register is not locked 1 b1 The Vcc Power bit bit 4 of Power Control register cannot be changed by software This bit can be used to prevent card drivers from overriding the Socket Services task of controlling power to the card thus preventing situations where cards are powered incorrectly 1 R W A
377. nc 97 AT460A BI Developer s Manual Centrality Overlay2 Datapath also named OSD2 datapath is similar to the Second Overlay Datapath function but processes the Overlay2 data It can be defined as 2 4 8 or 16 bit per pixel image The overlay2 data is defined for only a sub portion or equal of the main display The Palette RAM includes 256x18bit entry a 16x18bit entry and a 32x64bit entry They be either a color palette of RGB value or a dithering sequence for FRC The palette RAMs are written or read directly by RISC Interface to access the specified address The 2 4 or 8 bit pixel data can be an index of the palette RAMs The Mixer mixes the values from the Main Display Datapath and the two Overlay Datapaths It implements the two overlay layers alpha blending and or color keying on top of the main display layer The RGB YUV unit converts the screen output from 24 bit RGB value to 24 bit YUV value using a matrix multiplication with programmable coefficients Note that this unit is after the mixer so both the overlay data and the main screen data will be converted The Parallel Process unit converts the serial data outputted from frame rate control logic to 4 8 or 16 bit parallel data Thus for dual panel passive display the output data will be 8 or 16 bits This unit is only valid for STN S STN or D STN displays The Output Interface converts the RGB output of the RGB YUV unit
378. nd TSEG2 define the length of the bit period by giving the number of time quanta up to and after the point s at which incoming data will be sampled In terms of TSEG1 and TSEG2 the parameters tsyncseg ttseg1 and ttseg2 in above figure are tsyncseg 1xTQ 1 TQ x TSEG1 1 ttseg2 TQ x TSEG2 1 Note In theory it is possible to define bit periods of between 3 and 25 TQ through these register settings However the bit periods used in practice are required to follow the BOSCH standard which defines bit periods between 8 and 25 TQ in length The TSEG2 should not be set to 0 when configing the bit rate 1 The bus will be sampled three times This is recommended for low medium speed buses class A or B 0 The bus will be sampled once This is recommended for high speed buses SAE class e Arbitration Lost Capture Register CANBUSn_ALC 0x0018 Bit Name Default 4 0 R ALC 5 hO Centrality Communications Inc Description 57000000 Arbitration lost 1st bit of identifier ID 28 57000001 Arbitration lost in 2nd bit of identifier ID 27 57000010 Arbitration lost in 3rd bit of identifier 10 26 57000011 Arbitration lost in 4th bit of identifier 10 25 57000100 Arbitration lost in 5th bit of identifier 10 24 57000101 Arbitration lost in 6th bit of identifier 10 23 5 b001 10 Arbitration lost in 7th bit of identifier 10 22 500111 Arbitration lost in 8th bit of identifier 10
379. nd to issue Timing of generating the Auto CMD12 Error and writing to the SD TRAN register is Asynchronous Then bit 7 shall be sampled when driver never writing to the 50 TRAN CTRL register So just before reading the AUTO CMD12 ERR STATUS register is good timing to set the bit 7 status bit e SDIO Capabilities Register SD CAPABILITIES 0x0040 Centrality Communications Inc 183 AT460A BI Developer s Manual Centrality Default Description TIMEOUT FR 6130 This bit shows the base clock frequency used to detect EQ DAT TIMEOUT ERR Not 0 1Khz to 63Khz or 1Mhz to 63Mhz 000000b Get Information via another method eee 7 TIMEOUT_UNIT 1 b1 This bit shows the unit of base clock frequency used to detect DAT TIMEOUT ERR 0 KHz 1 MHz 13 8 R BASE FREQ 67130 This value indicates the base maximum clock frequency for the SD clock Unit values are 1Mhz If the real frequency is 16 5 MHZ the larger value shall be set 010001b 17 MHz because the HD uses this value to calculate the clock divider value and it shall not exceed the upper limit of the SD clock frequency The supported range is 10Mhz to 63 MHz If these bits are all 0 the Host System has to get information via another method Gua 17 16 ae MAX_BLK_LEN 2010 This value indicates the maximum block size that the HD can read and write to the buffer in the HC The buffer shall transfer this block size wit
380. ne the INT IRQ PENDING and INT FIQ PENDING registers are read by RISC to determine the interrupt Source In general software then reads status registers within the interrupting device to determine how to service the interrupt The following table shows the bit locations corresponding to the 32 separate interrupt pending status flags in the INT IRQ PENDING The next table shows the bit locations corresponding to the 32 separate interrupt pending status flags in the INT FIQ PENDING This is a read only register Default Description Bit 31 0 IP lt 31 0 gt 32 hO0 IRQ pending bits 0 No interrupt pending 1 Interrupt pending Bit Name Default Description 31 0 lt 31 0 gt 320 FIQ pending bits 0 No interrupt pending 1 Interrupt pending e Interrupt Controller DSP Pending Register INT DSPO PENDING RISC 0 000 DSP 0x006 0x007 The INT DSPO PENDING contain one flag per interrupt 32 total that indicates an interrupt request to IRQLO has been made by a unit Inside the interrupt service routine the INT DSPO PENDING are read by DSP to determine the interrupt source In general software then reads status registers within the interrupting device to determine how to service the interrupt Centrality Communications Inc 61 AT460A BI Developer s Manual Centrality The following table shows the bit locations corresponding to the 32 separate interrupt pending status fl
381. ne of DMA This value is in the register CHO XLEN Y value This a 16 bit value which defines how many lines of DMA to perform The actual line number of is Y 1 For example to DMA one line Y 0 to 10 lines Y 9 This value is in register DMA CHO YLEN e width This is a 10 bit value which specifies the spacing between two lines in DWORD For example if the width 100 X 10 and Y 5 then each time when the DMA gets 10th DWORD it will jump 90 DWORDS to reach the start of the next line Since width registers are often fixed for a particular application the Atlas 1 provides a set of 4 width values WIDTHO DMA_WIDTH17 etc that can be pre initialized A particular DMA only needs to specify which of the 4 registers to use in the register The entire configuration registers of DMA channels are implemented in a register file The active channel will load its configuration values into an address counter that changes values while the DMA going When the is interrupted the value in the counter will be updated back to the register file Thus the programmer can program the other DMA channels while there is one DMA channel running But if the programmer writes to the configuration registers of the currently active DMA channel the value may be invalid if this DMA is updating the address at the same time Thus it cannot guarantee the value to be valid So it s not recomm
382. ng set This status is useful for the HD in determining when to issue commands during write busy 1 transferring data 0 No valid data This status is used for detecting completion of a read transfer This bit is set to 1 for either of the following conditions 1 After the end bit of the read command 2 When writing a 1 to CONTINUE REQ the SD HOST 0 register to restart a read transfer This bit is cleared to 0 for either of the following conditions 1 When the last data block as specified by block length is transferred to the system 2 When all valid data blocks have been transferred to the system and no current block transfers are being sent As a result of the STOP AT BLK GAP REQ set to 1 A TRAN END interrupt is generated when this bit changes to 0 1 Transferring data 0 No valid data This status is used for IO write transfers This read only flag indicates if space is available for write data If this bitis 1 data can be written to the buffer A change of this bit from 1 to 0 occurs when all the block data is writ ten to the buffer A change of this bit from 0 to 1 occurs when top of block data can be written to the buffer and generates the BUFF WT RDY Interrupt 0 Write Disable 1 Write Enable This status is used for IO read transfers This read only flag indicates that valid data exists in the host side buffer status If this bit is 1 readable data exists in the buffer A change
383. ng to drive the Read Wait signal It is necessary to support Read Wait in order to use the suspending resuming function b In the case of write transactions this status indicates that a write transfer is executing on the SD bus Changing this value from 1 to 0 generate a TRAN_END interrupt in the SD_INT_STATUS register This bit shall be set in either of the following cases 1 After the end of the write command 2 When writing to 1 to CONTINUE in the SD HOST register to continue a write transfer This bit shall be cleared in either of the following cases 1 When the SD card releases write busy of the last data block the HC shall also detect if output is not busy If SD card does not drive busy signal for 8 SD clocks the HC shall consider the card drive Not Busy 2 When the SD card releases write busy prior to waiting for write transfer as a result of a STOP AT BLK GAP REQ NOTE HD can issue cmd12 cmd13 for memory and cmd52 for SDIO when the DAT lines are busy during data transfer These commands can be issued when Command Inhibit CMD is set to zero Other commands shall be issued when Command Inhibit DAT is set to zero SDIO Host Control Register 0 SD HOST 0 0x0028 Bit Default Description ae el 1 DAT_TRAN_WIDTH 1 bO This bit selects the data width of the HC The HD shall select it to match the data width of the SD card 1 4 bit mode 0
384. ns cam Specifications 9 4 17 Ide Specifications 9 4 18 GPIO Specifications Table 112 GPIO data Timing Sym Description Min Max Units Tx meuseupime ___ 48 ta _____ 12 rs X_xin tvaild Gpio_intput tet tha Centrality Communications Inc 370 AT460A BI Developer s Manual Centrality Figure 86 GPIO data Timing 9 4 19 Serial Port Specifications Table 113 Serial Port AC Timing Pin Name Symbol Parameter MIN MAX UNITs X_TXD Tvaid Txd valid ime 30 ns T dhd _ data time 03 ns X_TFS Tvalid valid time 30 ns TFSdataholdtime 04 ns X RXD Tsu__ RXDsetuptime 40 ns RXDholdtime __ 11 ns X RFS RFSsetptime 40 ns Thd __ __ 11 ns Figure 87 Serial Port AC Timing 9 4 20 CANBUS AC Specifications 9 4 21 PCMCIA AC Specifications 9 4 22 USBOTG AC Specifications Table 114 Timing Specifications USB Output Line 1 USB Bit width 1 83 3 667 ns 2 Signal falling time 4 20 ns 3 Signal rising time 4 20 ns 1 Defined in the USB config register 12 Mbit s or 1 5 Mbit s modes NOTE Output timing was specified at a nominal 50 pF load 3 2 gt X_USB_XDN 1 1 o gt lt 79 Figure 88 Timing Diagram USB Output Line 9 4 23 SDIO AC Specific
385. nt Equivalent to FIFO FULL FIFO LEVEL lt 317 gt 152580 e USP TX FIFO Data Register USP TX FIFO DATA 9 0x118 DSP 0x4c Bit Name Default Description 31 0 FIFO DATA 32 h0 The FIFO data register which is the bottom of the W TX_FIFO 8 8 5 3 USP RX_FIFO register NOTE The data flow of RX_FIFO is always from USP to ARM9 DSP DMA Centrality Communications Inc 325 AT460A BI Developer s Manual Centrality e USP RX MODE register USP IO CTRL 9 0x120 DSP 0x50 Erat Description IO SEL 1 for I O mode 0 for DMA mode ee 2 R W DMA FLUSH 1 bO Flush the DMA receive FIFO in case the DATA LEN set at the peripheral side doesn t match the DWORD size set in the DMA control eee i 1790 reserved 4 LN NN LE bO ODE lt 316 gt 2680 USP RX DMA I O length register USP IO LEN ARM9 0x124 DSP 0x52 0x53 Bit Default Description 31 0 DATA LEN 32 h0 The byte number of a DMA or I O transfer If set to R W zero the I O or DMA transfer works continuously until itis stopped e USP RX FIFO control register USP FIFO ARM9 0x128 DSP 0x54 Bit Name Default Description R W DWORD lt 6 2 gt FIFO_THD lt 4 0 gt 5 hO A threshold in byte to trigger an interrupt R W An interrupt is triggered when the count of data in the FIFO reaches the threshold lt 317
386. ntroller If the SD Bus power is set to 1 in the Power Control Register the Host Controller shall supply voltage to the Card If the Host Driver selects an unsupported voltage in the SD Bus Voltage Select field the Host Controller may ignore write to SD Bus Power and keep its value at zero 7 4 4 SDIO Host Controller Registers NOTE BASE address of SD host controller is 0x4600_0000 All the registers access of SD host controller by RISC is memory access Table 39 SDIO Host Controller Register Mapping RISC Address Register Description lt 11 0 gt 0x0000 3 Reserved 0 0004 Block size count register 0x0008 Command argument register 0 000 Transfer control register 0x0010 SD card response register 0 0 0014 SD card response register 1 0x0018 SD card response register 2 0x001C SD card response register 3 0x0020 Transfer data buffer register 0x0024 SD host controller state register 0x0028 SD host controller control register 0 0 002 SD host controller control register 1 0x0030 SD interrupt status register 0x0034 SD interrupt status enable register 0x0038 SD interrupt signal enable register 0x003C Automatical command 12 error status register 0x0040 SD host capabilities register 0x0044 2 Reserved 0 0048 Maximum current capability 0x004C SD bus clock delay register 0 0050 0 8 2 Reserved Slot interrupt status and version register Others Reserved 500 Block Size Count Register SD
387. number Data bit number Stop bit number 1 RX SHIFTER LEN Data bit number 1 Centrality Communications Inc 320 AT460A BI Developer s Manual Centrality The Parity bit is not supported in USP And the Stop bit number is not supported of 1 5 bit and should be set to TXD_DELAY_LEN bits in the USP_MODE2 register e USP Transmit Receive Enable Register USP TX RX ENABLE ARM9 0x10 DSP 0x8 If CTRL MODE 0 USP MODE REG2 The TX ENA RX bits will be cleared automatically after the previous operation finishes and they must be set before a new transmit receive operation begin If MODE 1 the TX ENA RX bits will not be cleared by writing a 0 to it You need to set them only 1 time before you want to begin multi times transmit receive operation You can set ENA TX ENA respectively according to requirement of the USP interfacing with external device Bit Name Default Description 0 R W 1 bO Receive enable bit 0 disabled 1 enabled 1 R W TX ENA 1 bO Transmit enable bit 0 disabled 1 enabled 3122 3000 Reserved e USP Interrupt Enable Register USP INT ENABLE ARM9 0x14 DSP 0xA 0xB Bit Default Description 0 R W DONE INT EN 1 bO Receive done interrupt enable 0 disabled 1 enabled 1 R W TX DONE INT EN 1 bO Transmit done interrupt enable 0 disabled 1 enabled 2 R W RX OFLOW INT EN 1 bO Receive overflow interrupt enable
388. o same as above RW SYS_RATIO lt 3 0 gt PLL OUT SYSCLK ratio same as above R W 15 12 lt 3 0 gt 4 h2 PLL OUT IOCLK ratio same as above R W 19 16 USB lt 3 0 gt 4 h1 PLL OUT USBCLK ratio R W It can be 1 2 4 8 or 16 Any other value written to it will be equivalent to the next value bigger than that e g 5 is equivalent to 8 9 is equivalent to 16 etc It s the same as all the following ratios 23 20 0 lt 3 0 gt PLL OUT CKO 0 ratio same as above R W 27 24 1 RATIO 3 0 4 h1 PLL OUT CKO 1 ratio same as above R W 3128 Reserved The following constraints must be followed e frequency of DSPCLK can only be 1X or 2X of SYSCLK e frequency of IOCLK can only be 1 2X of SYSCLK NOTE Any configurations violated the above constraints will incur unexpected result e Power Manager XIN Ratio Register PWR XIN RATIO 0x0044 Bit Default Description 0 R W RATIO 1 bO 1 b0 XIN is not divided by 2 1 b1 XIN is divided by 2 PLL OUT is determined by PWR CLK SWITCH register it can be 12MHz crystal 32KHz crystal PLL1 or PLL2 Centrality Communications Inc 56 AT460A BI Developer s Manual Centrality 3 7 13150 e Power Manager Pad Control Register PWR PAD CTRL 0x0048 Atlas II memory interface can be configured to 4 different modes LVCMOS18 SSTL2 LVCMOS5 LVCMOS3
389. o drive the LCD display LDD 17 8 can be configured as GPIO pins LCD Shift Pixel Clock programmable polarity Used by the LCD display to latch the pixel data and control signals X L LCLK L LCLK LCD Line Clock programmable polarity Used by the LCD display to signal the end or the beginning of a line Line Pulse for passive STN displays Horizontal sync for active TFT displays X L L FCLK LCD Frame Clock programmable polarity Used by the LCD display to signal the start of a new frame First Line marker for passive STN displays Vertical sync for active TFT displays X_L_BIAS L_BIAS AC Bias M signal Data Enable Switch signal of some passive STN displays to convert the liquid crystal drive waveform into AC Data Enable DE for active TFT displays The following table describes the LCD pins required for the various types of passive displays Table 28 Atlas II LCD Controller Data Pins for passive displays Centrality Communications Inc 95 AT460A BI Developer s Manual Centrality Color Single Abit Screen Pins Top left pixel Monochrome Dual Panel 8bit 16bit Portion Panel data parallel Color Single Abit Whole LDD lt 3 0 gt LDD lt 3 gt Monochrome Color Dual Abit Upper Lower LDD lt 3 0 gt LDD lt 3 gt Monochrome in a frame Lower Upper LDD lt 7 4 gt LDD lt 7 gt Color Single 8bit Whole LDD lt 7 0 gt LDD lt 7 gt Monochrome Color
390. om external memory 2 b01 FIFO is between Stop FIFO is between Stop and 0 ____ 2910 FIFO is between Low and High FIFO is between Low and High 2511 FIFO is between High and full FIFO is between High and empty There will be two FIFOs for the peripheral that needs to do bi directional data transfer one FIFO for each direction Thus there will be no case that both DMA controller and peripheral block try to write the same FIFO FIFO writes to FIFO read from Full external memory external memory High Check Stop Check Low Check Low Check Stop Check High Check Empty Figure 50 FIFO Request Level Checkpoints Some peripherals are relatively fast and may need to transfer several words of data at one time Then it can be programmed in burst DMA mode In burst mode the DMA will transfer 4 32bit words of data at one time instead of one word in normal mode The stop checkpoint of the input FIFO in burst mode should be set greater than or equal to the 4 It is necessary to configure a flush bit to the input FIFO so that the last few words under stop checkpoint of the inputs will not be stuck in the FIFO at the end of DMA When the flush bit is set the Centrality Communications Inc 254 460 Developer s Manual Centrality request level will maintain at 2501 even the FIFO is below the stop level This ensures the FIFO is emptied even if new data is not coming in Each DMA has its own interrup
391. ontain valid PCM data In 48 KHz sample rate the PCM left channel and right channel are always valid in each AC97 audio frame but in VRA Variable Rate Audio mode the PCM left channel and right channel may not be valid at the same frame In stereo mode the 32 bit PCM data is made up of a pair of PCM left channel and right channel Normally the MSB 16 bit is left channel the LSB 16 bit right channel in interlace mode left channel is saved in LSB 16 bit and right channel MSB 16 bit In mono mode the 16 bit left channel or right channel data is saved is LSB 16 bit first then the MSB 16 bit The PCM record process is shown in the following flowcharts Centrality Communications Inc 287 AT460A BI Developer s Manual LS Centrality COMMUNICATIONS Read in Tag Frame valid gt Mono Right Figure 68 AC97 PCM Record Flowchart Read in PCM left channel Set left_channel_valid Both left and right channel are valid Write 32 bit data to FIFO Clear left channel valid Read in PCM Right channel Clear right_channel_valid Set right channel valid Figure 69 Stereo Mode Flowchart Centrality Communications Inc 288 AT460A BI Developer s Manual LS Centrality COMMUNICATIONS Slot 3 valid Slot 4 valid Read in PCM right 32 bit PCM valid Read 32 bit PCM valid Write data to FIFO Write data to FIFO Figure 70 Mono Mode Left Right Flowcharts 8
392. operating frequency information of the Atlasll Table 101 Clock Frequencies 1 ARM core 276 MHz 2 Dsp core 200 MHz 3 SDRAM Clock 138 MHz 4 DDRAM Clock 100 MHz 9 4 8 Clock AC Specifications CVH 1 son d Nass Figure 76 Timing Diagram X XIN Table 102 X XIN Timing Description Min X_XIN cycle time 1 83 3 ns TRise X_XIN rise time 5 0 ns X fall time 5 0 ns TbDuty X_XIN duty cycle 40 0 60 0 CVIH X_XIN input voltage high 2 0 V CVIL X_XIN input voltage low 0 8 2 9 4 9 Resets When power on always power up the higher voltage domain first So if we have 1 8 2 5 3 3V power supply please follow the power on off sequence as shown in the following figure Centrality Communications Inc 362 AT460A BI Developer s Manual Centrality VDDIO 3 3V XVDDIO 3 3V VDD MEM 2 5V VSSTL VDD PHA 3 3V ME VDD PLA 1 2V EE VDD PLD 1 2V VTT 1 2V VREF 1 2V VDDPRE 1 2 X_PWR_EN output VDDPDN 1 2V t6 RESET t1 3 t ti gt 10ms 12 gt 08 t3 gt 50ms t4 gt 3ms 15 gt 2 5 gt 1 13 must wait for 12MHz Clock steadily Figure 77 Timing Diagram power and reset Timing 9 4 10 External Interrupts e Atlas II provides 32 external interrupts GPIO group 0 31 0 e
393. or AC97 CODEC response with the control register read data SYNC Slot 0 gt 51 1 re Slot 2 m bL uL uli as GG 0000 57 000008 CODEC Slot1 Slot2 Bit 18 12 Bit 11 2 Bit 19 4 Ready Reg Addr RSVC Reg Data Figure 66 AC link Input Frame Command Diagram 8 6 6 3 2 PCM Record The following figure shows the AC97 PCM record function block There are two records mode stereo mode and mode It depends on the Atlas II AC97 Controller configuration Centrality Communications Inc 286 460 Developer s Manual LS Centrality COMMUNICATIONS 16 bit PCM AD_DATA Left PCM x Shifter 16 bit Data 32 bit Data Judgment PCM Data 16 bit PCM Right SYNC SYNC Generatio n Write BIT CLK BIT_CLK Slot Control Counter Judgment Control Unit Figure 67 AC97 PCM Record Functional Block Diagram The data transfer over AC link data is in serial mode First the Atlas AC97 controller converts the serial input data into 16 bit data The 16 bit data maybe AC link tag status address status data PCM left channel data or PCM right channel data The BIT_CLK counter will make the slot judgment AC link input slot 0 is the AC link tag the bits in the tag indicate whether the slots contain valid data AC link input slot 3 and 4 are PCM record left and right channel output of AC97 s input MUX post ADC when bit 11 or bit 10 of AC link tag are asserted it indicates that slot 3 or slot 4 c
394. or Generated AUTO CMD12 ENDB Occurs when detecting that the end bit of IT ERR command response is 0 0 No Error 1 End Bit Error Generated AUTO CMD12 INDE Occurs if the Command Index error occurs in X ERR response to a command 0 No Error 1 Error CMD NOT ISSURED By Auto CMD12 Error Setting this bit to 1 BY CMD12 ERR means CMD WO DAT is not executed due to an Auto CMD12 error 004 001 in this register 0 No Error 1 Not Issued 28 Reserved 5 O Table 46 Relation between Auto CMD12 CRC Error and Auto CMD12 Timeout Error Auto Cmd12 CRC Error Auto CMD12 Timeout Error Kinds of Error pcc a dt LLL Response Timeout Error Table 47 Relation between Auto CMD12 CRC Error and Auto CMD12 Timeout Error Auto Cmd12 CRC Error Auto CMD12 Timeout Error Kinds of Error Response CRC Error CMD Line Conflict The timing of changing Auto CMD12 Error Status can be classified in three scenarios 1 When the HC is going to issue Auto CMD12 Set bit 0 to 1 b1 if Auto CMD12 cannot be issued due to an error in the previous command Set bit 0 to 1 bO if Auto CMD12 is issued 2 At the end bit of Auto CMD12 response Check received responses by checking the error bits 1 4 Set to 1 b1 if Error is detected Set to 1 bO if Error is Not Detected 3 Before reading the Auto CMD12 Error Status bit 7 Set bit 7 to 1 b1 if there is a command cannot be issued Set bit 7 to 1 bO if there is no comma
395. ords the number of messages currently available in the Receive FIFO It is automatically incremented by each Receive event and decremented by each Release Receive Buffer command It is available for Read only access in both Operating Mode and Reset Mode 31 5 20 Reserved CANBUS Receive Buffer Starter Address CANBUSn_RBSA 0x0078 Name Default Description RBSA 6 hO The Receive Buffer Start Address register records the R W current location of the RX FIFO Read Pointer within the 64 byte Receive FIFO as a value between 0 and 63 Location 0 maps to CAN address 0x80 Centrality Communications Inc 341 460 Developer s Manual Centrality Location 63 maps to CAN address 0 17 This register is reset to 00 by a hardware reset but is left unchanged by a software reset which also does not change the FIFO contents However a software reset sets the RX FIFO Write Pointer to the value of the RX FIFO Read Pointer so the data accessed by the Receive Buffer following a software reset will be overwritten by the next message to be recorded in the Receive FIFO 31 6 7 8 9 3 2 Control Registers Table 90 Bus DMA Register Mapping RISC Address Register Description lt 11 0 gt omes ____ __ Cd Reserved CANBUS DMA I O Mode Register CANBUS_DMA_IO_CTRL 0xF00 Name Description SEE SEL 0 for DM
396. ory auto sizing program The following table shows the memory address mapping of Atlas II Table 1 System Memory Mapping Usage Resource Size 0 000 0000 DFFF FFFF System Memory 512MB 1 After boot up the address space from 0x1000 0000 0x0FFF FFFF be re directed to the system memory DDR SDRAM and then user can only access the ROM Flash through 0x1000 0000 0x1FFF FFFF 2 The ROM Flash interface can be accessed a PCI device too in this case user can access the ROM Flash through PCI address space 0x6000 0000 0x6FFF FFFF Centrality Communications Inc 15 AT460A BI Developer s Manual Centrality 0x3000_0000 3FFF_FFFF PCMCIA Socket 1 256MB 0x2000_0000 2FFF_FFFF PCMCIA Socket 0 256MB 0x0000 0000 1FFF FFFF Flash ROM 512MB 2 2 3 Memory Bus Interface The Memory Bus Interface is responsible for translating the ARM926EJ AHB bus protocol to the system bus protocol 2 2 4 Bus Interface If the address the RISC issues is to a memory mapped register or an device or the FIFO storage the read write cycle will be redirected to the RISC I O Bus Interface All the registers interface to I O devices and FIFO storage in Atlas II will be based on 32 bit addresses except for some registers in SDIO and IDE interface Some of the registers are in System Clock Domain and others are in I O Clock Domain For those regsiters in Clock Domain RISC may
397. ote that this bit is reset to 1 bO when the card is removed from the socket unless the auto power off feature is disabled by setting Extension control 1 register bit 1 to 1 b1 5 AUTO PWR 1 bO 1 b0 Vcc and Vpp1 power control signals are activated independent of the socket s ncd2 and 1 input levels 1 b1 Vcc and Vpp1 power control signals are only activated if the socket s ncd2 and ncd1 inputs are both active low When this bit is set to 1 b1 the M6730 allows the power to the card to be turned on or off automatically with the insertion and removal of a PC card 61 170 Compatibility bit 7 CARD EN 1 b1 1 b0 Outputs to the card socket are not enabled and are floating 1 b1 Outputs to the card socket are enabled if ncd2 and 1 inputs are active low and bit 4 is1 b1 When this bit is 1 b1 the outputs to the PC card are enabled if a card is present and the card s power is being supplied The signals affected include ncef nce2 niord niowr noe nreg reset lt 25 0 gt d 15 0 Table 59 6730 Power Control Regi nrst Both Power Control Register Interface Status nvcc c and and Level 1 Register _5 levels vpp_vcc levels 2 from Power from Power active VCC_PWR AUTO_PWR ON Control Logic Control Logic low bit 4 bit 5 bit 6 Inactive Inactive low high Activated per Activated per MiscControl1 Power Control
398. over current status is reported collectively for all downstream ports Reserved OVRCURPM 12 R NOOVRCURP 2333 DEVTYPE Device Type This bit specifies that the Root Hub is not a compound device The Root Hub is not permitted to be a compound device This field should always read as 0 ____ Reserved _________ Centrality Communications Inc 206 AT460A BI Developer s Manual Centrality 31 24 PWRTOGOOD Power On to Power Good Time R This byte specifies the duration that software must wait before accessing a powered on port of the Root Hub e USB OTG Root Hub Descriptor B Register USBOTG HC RH DESC B 0x00EC Bit Default Description 7 0 R DEVREMOVE 870 Device Removable Each bit is dedicated to a port of the Root Hub When cleared the attached device is removable When set the attached device is not removable bit 0 this port can be OTG 1 port during HNP negotiation bit 1 Device attached to Port 2 bit 2 Device attached to Port 3 158 re 16 PRTPWRCM Port Power Control Mask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set When set the port s power state is only affected by per port power control Set ClearPortPower When cleared the port is controlled by the global power switch Set ClearGlobalPower bit 0 this port can be OTG 1 port during HNP negotiation bit 1 Port 2 bi
399. overflow takes place 0 3 R W RX_AUX_FIFO_UFLOW 0 Auxiliary RX FIFO underflow status 1 AUX RX FIFO underflow takes place 0 AUX RX FIFO is not underflow User needs to write 1701 to clear the register bit after the auxiliary RX FIFO underflow takes place i 128 e AUX CODEC RXFIFO Interrupt Enable Register CODEC_RX_ FIFO INT EN 0xBD8 Bit Name Default Description 0 AUX RX FIFO full interrupt is disabled 1 AUX RX FIFO empty interrupt is enabled 0 AUX RX FIFO empty interrupt is disabled 1 AUX RX FIFO overflow interrupt is enabled 0 AUX RX FIFO overflow interrupt is disabled RX FIFO underflow interrupt is disabled 314 8 Reseved e CODEC TX FIFO DMA Control Register CODEC TX AUX IO CTRL 0 80 Bit Name Default Description 0 R W 0 write to CODEC 2 R W DMA_FLUSH Tb Flush the DMA receive FIFO in case the DATA_LEN set at the peripheral side doesn t match the DWORD size set in the DMA control 0 3 R W oo 0 1 little endian write read 0 big endian write read 31 28 e CODEC Control Register CODEC TX AUX FIFO CTRL OxF88 Bit Default Description FIFO_WIDTH lt 1 0 gt Data width of FIFO 0 for byte 1 for word and 2 for Centrality Communications Inc 300 460 Developer s Manual Centrality X JDWORD 7 2 FIFO_THD lt 5 0 gt 6h A threshold in byte to trigger a
400. ow refresh per refresh request 01 gt two row refresh per refresh request 10 gt three row refresh per refresh request 11 gt four row refresh per refresh request 12 2 REFRESH TIME 11 h60 192 clocks of CLK 12M for default The R W base timing unit for refresh period is based on 12MHz clock 13 0 gt disable self refresh R W 1 gt enable self refresh 17 14 T_SREX 4 h7 Number of memory clock is required to return R W from self refresh to normal refresh Default is 7 memory clocks For DDR this is the interval from CKE rising high to beginning DLL reset delay counter 21 18 T RAS 4 h7 T RAS is number of memory clocks required R W for clock being stable before self refresh exit Default is 7 memory clocks 25 22 T RFC 4 h7 T RFC is the number of memory clocks R W required for refresh cycle Default is 7 memory clocks 27 26 2511 T RP is the number of memory clocks R W required for row precharge time interval between Precharge to RAS Default is 3 memory clocks 29 28 T_RCD 2611 T_RCD is the number of memory clocks R W required for CAS after RAS interval between Precharge to RAS Default is 3 memory clocks 31 30 250 This register can be change during DRAM operation if the memory clock period is changed Notice that one can only program these timing parameters when DRAM is idle e Memory Power Management Register MEM POWER RISC 0x8 Bit Default Description em OO R W i
401. owing parallel format definition is described for R W single scan panel And for monochrome STN only 4bit and 8bit parallel are supported Centrality Communications Inc 115 AT460A BI Developer s Manual Centrality 00 8bit parallel output 01 4bit parallel output 10 16bit parallel output 20 MSTN 1 0 1 Monochrome STN mode valid R W 0 Monochrome STN mode invalid 21 CSTN 1 bO 1 Color STN mode valid R W 0 Color STN mode invalid 3122 1050 e Pixel Linear Feedback Shift register LCD PIX LFSR 0x6C Bit Default Description LFSR_SEED 15 10 Initial value of the pixel LFSR LFSR advanced by PIXCLK R W 29 15 LFSR_VAL 150 Algorithm used for the LFSR If bit 1 then that bit of the R W shift register is used in the sum For instance for the algorithm g x 1 program the algorithm value to 000010000000010 33 ________ 2500 ___ Reserved e Frame rate modulation control register LCD FMOD 0x70 Default Description 6 m FMOD PERIOD 7 modulation period R W This parameter specifies half of the period of the FMOD signal i 1 FMOD_CLK Clock selection for FMOD signal generation IRR 1 Internal VSYNC generates FMOD 0 Internal HSYNC generates FMOD 8 SYN RESET 1 bO FMOD synchronous reset control only valid when using R W internal HSYNC to generate FMOD 1 FMOD polarity is reset at the beginning of frame 0 FMOD pol
402. p mode there is a two step procedure In the first step an internal timer begins to time the power ramp This timer waits for approximately 25ms by default In the second step another internal timer begins to time the oscillator as it begins to ramp up to speed This timer waits for 150ms by default If the oscillator is not powered off during sleep mode the second step is not needed Default Description OOK_WAIT_TIME 16 h327 wait time RW 31 16 OPU_WAIT_TIME 16 h1333 Oscillator Power up wait time R W Centrality Communications Inc 55 AT460A BI Developer s Manual Centrality e Power Manager Clock Stop Level Register PWR STOP LEVEL 0x0038 Bit Default Description 0 R W STOP AT LOW 1 b1 Clock stop level 1 Clock stops at low default 0 Clock stops at high 3151 13970 Reserved 2 2 e Power Manager CLK Ratio Register PWR CLK RATIO 0x0040 This register is used to configure the frequency of the clock by programming the divide parameter from the clock source Default Description 3 m CPU lt 3 0 gt 4 h1 The clock ratio PLL OUT CPUCLK default R W value is 1 It can be 1 2 3 4 6 8 12 or 16 Any other value written to it will be equivalent to the next value bigger than that e g 5 is equivalent to 6 9 is equivalent to 12 etc It s the same as all the following ratios DSP RATIO 3 0 PLL OUT DSPCLK rati
403. pace defined by those registers S RW 170 Compatibility bit 6 R W IO 1 bO Enable 1 b0 10 Window Mapping registers Window 0 disabled 1 b1 10 Window Mapping registers for Window 0 enabled When this bit is 1 b1 the Window Mapping registers for the window 0 are enabled and the controller will be able to respond to I O accesses in the space defined by those registers 7 R W 1 bO IO Map1 Enable 1 b0 10 Window Mapping registers for Memory Window 1 disabled Centrality Communications Inc 234 460 Developer s Manual Centrality 1 b1 IO Window Mapping registers for Memory Window 1 enabled When this bit is 1 b1 the Window Mapping registers for the I O window 1 are enabled and the controller will be able to respond to I O accesses in the space defined by those registers e M6730 I O Window Control Register M6730 IO WIN CTRL Index 0x07 Default Description Window 0 Size 1 b0 8 bit data path to Window 0 1 b1 16 bit data path to Window 0 When the bit 1 of this register is 1 b0 this bit determines the width of the data path for the I O window 0 accesses to the PC card When the bit 1 is 1 b1 this bit is ignored Auto size I O Window 0 1 b0 I O Window 0 Size see bit 0 of this register determines the data path for I O Window 0 access 1 b1 The data path to I O Window 0 is deter
404. power on always power up the higher voltage domain first So if we have 1 8 2 5 3 3V power supply please follow the power on off sequence as shown in the following figure T d dL 12 1 gt 1 gt 1ms gt 1 Figure 14 Power on off Sequence 5 3 11 Sleep Wakeup Sequence The sleep wakeup sequence is controlled by the 32 768 KHz RTC clock The following figure shows the major events in the sleep wakeup sequence Centrality Communications Inc 49 AT460A BI Developer s Manual Centrality Sleep event Power manager take control of memory pins RTC clock zl LI PWR_EN i i i 1 1 WAKEUP 25T 4 gt 3T 4 Release of memory pin Figure 15 Sleep Wakeup Sequence First of all there is a sleep event that triggers the sleep process Normally this event is generated by writing a SLEEP register bit in software Although by asserting the VDD FAULT BATT FAULT can also generate a sleep event it s not very applicable because the related clock switching may not be allowed to happen NOTE It S suggested to use the software sleep even in case that VDD FAULT BATT FAULT happens After sleep event is triggered it takes 5 RTC cycle 160us that the PWR EN signal will be disserted Then the power supply to the power down domain can be turned off In 2 RTC cycles after sleep event triggered the memory pins will be taken over by t
405. pt enable register UART INT STATUS UART interrupt status register Ox2E UART RISC DSP MODE UART accessing select register 0 60 0x100 UART TX IO CTRL UART TXFIFO DMA IO register 0x108 UART TXFIFO CTRL UART TXFIFO control register 0x104 0x42 0x43 UART TX IO LEN UART transmit data length register 0x10C 0 46 0 47 UART TXFIFO LEVEL UART TXFIFO check level register 0x110 UART_TXFIFO_OP UART TXFIFO operation register 0 114 UART TXFIFO STATUS UART TXFIFO status register cime A Loxe __ Reserved 8 7 41 UARTO Control Registers 0x118 UART TXFIFO DATA UART TXFIFO bottom UART Line Control Register UART LINE CTRL RISC 0x40 DSP 0x20 Bit Default Description 1 0 R W DATA LEN 2 b0 27000 5 data bits in one frame 2 b01 6 data bit in one frame 2 b10 7 data bits in one frame 2 b11 8 data bits in one frame 2 R W STOP BIT LEN 1 bO 1 b0 1 stop bit 1 b1 2 stop bits os ADAE 6 R W SET BREAK 1 bO 1750 TXD in normal transmit state 151 TXD is forced to low level 31 16 TIMOUT NUM 16 h0 This register specifies the bit number for receive operation R W timeout case If no more new data is received after those bit number time has passed since the last data is received Receive timeout interrupt will happen UART Modem Control Register UART MODEM RISC 0x44 DSP 0x22 Bit Default Description
406. ption SCNFIFO ADDRST 1 bO Soft reset of SCN FIFO addresses 1 7 Setting this bit to 1 will reset the read and the write address of SCN FIFO At the same time the fifo full and the FIFO request status will be also reset It can be used for recovery from abnormal operations such as FIFO underflow overflow and so on 0 After reset this bit should be set back to 0 for normal operation OSDFIFO ADDRST 160 Soft reset of OSD FIFO addresses 1 7 Setting this bit to 1 will reset the read and the write address of OSD FIFO At the same time the fifo full and the FIFO request status will be also reset It can be used for recovery from abnormal operations such as FIFO Centrality Communications Inc 127 460 Developer s Manual Centrality underflow overflow and so on 0 After reset this bit should be set back to 0 for normal operation Soft reset of OSD2 FIFO addresses 1 Setting this bit to 1 will reset the read and the write address of OSD2 FIFO At the same time the fifo_full and the FIFO request status will be also reset It can be used for recovery from abnormal operations such as FIFO underflow overflow and so on 0 After reset this bit should be set back to 0 for normal operation Make sure the DMA s are not working before doing software reset 313 290 6 2 4 9 DMA Address Registers The DMA address is generated by an address generator based on some parameters defin
407. quired for buffering signals to from the interface Power consumption is controlled by limiting the signal transitions on the PC Card bus In Atlas II The PCMCIA interface shares pins with ROM SRAM IDE Flash Centrality Communications Inc 221 460 Developer s Manual Centrality snq Socket power control M6730 PCI to PC Card Host Bus Adapter Socket Figure 44 PCMCIA Block Diagram 7 7 5 PCMCIA Signal Descriptions Table 56 PCMCIA Interface Signal Description Direction Description lt 25 0 gt Output card address outputs PC D lt 15 0 gt PC D lt 15 0 gt D lt 15 0 gt Bidirectional card 16 bit data bus X_PC_VS lt 2 1 gt Bidirectional The two signals are used to determine the operating voltage of the card These two signals should externally pull high signals should be externally pulled high X_PC_IOIS16_B Input In memory card interface this input is interpreted as the status of the write protect switch In I O card interface this input indicates the size of the data at the current address on PC card X PC IORD B Output This output goes active low for I O reads from PC card to Atlas II This output goes active low for writes from Atlas Il to PC card X_PC_WAIT_B Output This input indicates a request by the card to Atlas Il to delay the cycle i
408. r USBOTG FC SYS INT STATUS 0x0048 Description RESETINT Reset Detected Interrupt RSMFININT Resume Finished Interrupt SUSPDETINT Suspend Detected Interrupt 3 R DONEREGINT 1 bO Done Register Interrupt When asserted this bit indicates one or more bits in EndpointDoneStatus Register 0x0070 is set SOFDETINT SOF Detected Interrupt 315 __ 12780 e USB OTG System Interrupt Enable Register USBOTG FC SYS INT EN 0x004C Bit Default Description 31 55 __ 1270 Reserved USB OTG X Buffer Interrupt Status Register USBOTG FC X INT STATUS 0x0050 Bit Default Description ODD R XBUFFERnININT 1 bO X Buffer of Endpoint n IN Interrupt When asserted indicates that the XIN buffer of Centrality Communications Inc 199 460 Developer s Manual Centrality endpoint lt gt has been emptied by the host E XBUFFERnOUTINT X Buffer of Endpoint n OUT Interrupt R When asserted indicates that the XOUT buffer of endpoint n has been filled by the host USB OTG Y Buffer Interrupt Status Register USBOTG FC Y INT STATUS 0x0054 Bit Name Default Description ODD R YBUFFERnININT 1 bO Y Buffer of Endpoint n IN Interrupt When asserted indicates that the YIN buffer of endpoint n has been emptied by the host EVEN YBUFFERnOUTINT 1 bO Y Buffer of Endpoint n OUT Interrupt R When asserted indicat
409. r for the active R W OSD display This value along with the horizontal start and end positions and vertical start position define the rectangle for the active OSD display This line is not included in the display region as indicated in Figure 8 even OSD is not clipped 11 0 Confirm the new Region and DMA setting by writing this bit with 1 This bit is self cleared after being written with 1 Remark As the layer gets a group of setting such as OSD HSTART OSD HEND OSD VSTART OSD VEND along with the OSD DMA settings they should effect synchronously when one register is changed it should not take effect immediately so this bit is used as a confirm of the setting group 3112 200 For effects of the OSD region settings please refer to figure of Screen and OSC Active Region They define the top left and the bottom right corner pixel position e Horizontal start position for the second active OSD screen LCD OSD2 HSTART 0x20 Name Default Description Bit 10 0 OSD2 HSTART 11 hO Horizontal Start Position in pixel number for the second 4 active OSD display This value along with the horizontal end position and vertical start and end positions define the rectangle for the second active OSD display 3111 2770 Reserved e Vertical start position for the second active OSD screen LCD OSD2 VSTART 0x24 Bit Default Description 10 0 OSD2_VSTART 1110 Vertical Start Position in l
410. r 16 grey levels For 4bit pixel mode bits lt 15 0 gt of entry 0 and entry 16 combine as 32 bits for one gray color and bits lt 15 0 gt of entry 1 and entry 17 as another gray color and so on And for 2bit pixel mode only entry 0 3 and entry 16 19 are used e Read Write 8 bit Palette LCD PALETTE 0x1000 0x13FC Bit Name Default Description 17 0 wii DATA Values in the color palette Can directly read or write values R W any palette value by specifying the index using bits 9 2 in the address Each entry in the palette is 18 bits 6 each for each color Bits 17 12 Red Bits 11 6 Green Bits 5 0 Blue Values in the dithering sequence of frame rate control bits 15 0 are used 3138 J Reseved The 16 x 18 palette RAM is written or read directly by RISC Interface to access the specified address This palette is always a color palette and each address contains RGB value for a color that has an index corresponding to the address The color component is 6 bits each specifying the 6 MSB of a 4 bit value This palette is used for 4 bit color value e Read Write 4 bit Color Palette LCD PALETTE16 0x1400 0x143C Bit Default Description PALETTE16 DATA Values in the color palette Can directly read or write Centrality Communications Inc 136 AT460A BI Developer s Manual Centrality R W values any palette value by specifying the index using bits lt 5 2 gt in th
411. r register value will be automatically loaded into the manual mode BitBLT registers when doing corresponding Writing this register will start the queued BitBLT immediately if in auto mode 31 27 SHO Reserved Centrality Communications Inc 148 AT460A BI Developer s Manual Centrality 7 Subsystem 7 1 Overview Atlas II implements a high speed internal PCI bus that can run up to 100MHz The PCI Bus Arbiter can support up to 9 PCI devices ROM SRAM Controller SDIO Host Controller 05 Interface IDE Interface PCMCIA CF Interface and etc All the PCI device registers in PCI Subsystem share the same 256MB segment of the RISC address space 0x5000 0000 5FFF FFFF Table 31 PCI Device Registers Mapping RISC Address Range Usage Resource Size 0 5700 0000 57DF FFFF IDE 0x5600 0000 560F FFFF 60 Others Cd Reserved J NOTE The address space from 0 6000 0000 6FFF FFFF is also accessed through PCI Bus but itis only used for mapping the ROM SRAM when it s programmed to be the system memory controller Besides the address space from 0x2000 0000 3FFF FFFF is also accessed through PCI Bus but it is only used for mapping the PC Card Memory Space Please refer to the following sections for more details 7 2 System to PCI Bridge There is a bridge between the System Bus and PCI Bus which coverts the 10 and memory accesses between the Syste
412. rality Communications Inc 132 AT460A BI Developer s Manual Centrality DMA_MODE Continuous mode DMA R W 1 when this DMA completes will automatically generate a DMA with exactly the same setting 0 each DMA must be explicitly started by software Size for 0502 DMA LCD 0502 XSIZE 0x134 0502 data Name Default Description 12 0 1370 This value specifies the number of consecutive 4 DWORD R W bursts per line for the OSD2 DMA This value should be inclusive of any partial DWORD s used per line OSD2_XSIZE OSD2_HEND OSD2_HSTART 1 3113 1980 Reserved Y Size for OSD2 LCD_OSD2_YSIZE 0x138 Bit Name Default Description 12 0 OSD2 YSIZE 13 h0 This value specifies the number of lines for the OSD2 R W DMA Each line designates a segment of consecutive DWORD s with a skip in between OSD2 YSIZE OSD2 VEND OSD2 VSTART 1 3143 190 Reserved o e Skip value for 0502 LCD OSD2 SKIP 0x13C Bit Name Default Description 12 0 130 This value specifies the number of BYTE s for DMA R W address generator to skip in between lines of the OSD2 DMA OSD2_SKIP ByteWidthOfOsd2FrameBuf OSD2_XSIZE 16 And the ByteWidthofOSD2FrameBuf must be a multiple of 16 3113 1980 Reserved e Current DMA Address for the 0502 Display LCD OSD2 ADDR 0x144 Writing to this register will activate the OSD2 DMA Make
413. ration Three watermarks are all useful request value can 2 b00 2101 2b 10 2b 11 31 25 70 Reserved e Screen FIFO Write Suppress Register LCD SCNFIFO SUPPRESS 0xD8 Since the only type of DMA that the LCD supports is a 4 DWORD burst the LCD can only DMA data in 4 DWORD increments However if the screen size or location requires the start of a new line in the middle of a burst the DMA interface will write extra DWORD s to the FIFO and causes data mismatch In order to avoid this we can use this register to suppress the extra writes to the FIFO at the end of a line To do this write the number of VALID DWORD writes to bits 23 12 and the number of writes to SUPPRESS to bits 11 0 For example to write 17 DWORD per line we will request 5 bursts 20 DWORD s from the DMA and suppress the last 3 DWORD s Thus we will set this register to Ox011 003 It is a must that the frame buffer s start address must lay on 4 DWORD s burst boundary and the frame buffer s width is also a multiple of the DMA 4 Dword boundary ine Second DMA New DMA New DMA Y start address Y address Y margin gt gt Valid Dwords Supppress Dwords Figure 26 FIFO Suppress Bit Name Default Description Centrality Communications Inc 126 AT460A BI Developer s Manual Centrality 11 0 R W 1270 number of DWORD writes to the FIFO tha
414. rectangle for the active LCD display 31 11 Reseved Vertical start position for active screen LCD SCN VSTART 0x4 Bit Name Default Description Centrality Communications Inc 104 AT460A BI Developer s Manual Centrality 10 0 SCN VSTART 11710 Vertical Start Position in line number for the active LCD R W display This value along with the horizontal start and end position and the vertical end positions define the rectangle for the active LCD display 3131 210 e Horizontal end position for active screen LCD SCN 0x8 Bit Default Description 10 0 SCN_HEND 11 hO Horizontal End Position in pixel number for the active LCD R W display This value along with the horizontal start position and vertical start and end positions define the rectangle for the active LCD display 31 11 21h0 Reserved e Vertical end position for active screen LCD SCN VEND 0xC Bit Default Description 10 0 SCN VEND 1110 Vertical End Position in line number for the active LCD R W display This value along with the horizontal start and end positions and vertical start position define the rectangle for the active LCD display This line is not included in the display region as indicated in Figure 8 31 11 21h0 Reserved For effects of the SCN region settings please refer to figure of Screen and OSC Active Region They define the top left and th
415. register bit for OS Timer2 in IP29 Interrupt extended mask register bit for OS Timer3 in IP29 Interrupt extended mask register bit for OS Timer4 in IP29 Interrupt extended mask register bit for OS Timer5 in IP29 31 317 __ ______ 1570 Reserved e Interrupt Controller DSP Mask Extended Register INT DSP MASK EXT RISC 0x0030 DSP 0x018 0x019 The definition of each bit is the same as above Bit tame Description extended interrupts mask bits WIR 0 Pending interrupt is masked from becoming active 1 Pending interrupt is allowed to become active 3117 150 j Reseved 0 2 2 e Interrupt Controller Pending Extended Register INT PENDING EXT RISC 0x0034 DSP 0x01A 0x1C This register contains the extended interrupt pending for MUXED interrupt IP 11 IP 15 IP 24 IP 26 IP 27 29 Following table details the extended interrupt pending register content Bit Name Default Description O R Interrupt extended bit for PCMCIA in IP11 1 R Interrupt extended bit for EXTPORT in 11 Centrality Communications Inc 64 460 5 Centrality tO Reserved 0 2 8 ___ lt 8 gt 1170 Interruptextended bit for USP4 in 26 ________ Interrupt extended bit for OS Timer1 in IP29 31 217 _________ 1570 Reserved 0 ________ e Interrupt Controller IRQ FIQ Extended Pending Register INT IRQ PENDING EXT INT FIQ PENDI
416. registers match the counter at this time then the corresponding status bit in the TIMER STATUS is set Default Description 31 0 lt 31 0 gt 32 h0 OS Timer match value R W e OS Timer Status Register TIMER STATUS 0x0020 These bits are set when the Timer match event occurs and cleared by writing a one to it Writing zeros to this register has no effect All reserved bits read as zeros and are unaffected by writes Name Default Description Match status channel 0 0 OS timer match register 0 has not matched the OS timer counter since the last clear 1 OS timer match lt 0 gt has matched the OS timer counter Match status channel 1 0 OS timer match register lt 1 gt has not matched the OS timer counter since the last clear 1 OS timer match register lt 1 gt has matched the OS timer counter Match status channel 2 0 OS timer match register lt 2 gt has not matched the OS timer counter since the last clear 1 OS timer match register lt 2 gt has matched the OS timer counter Match status channel 3 0 OS timer match register 3 has not matched the OS timer counter since the last clear 1 OS timer match register lt 3 gt has matched the OS timer counter 1 bO Match status channel 4 0 OS timer match register lt 4 gt has not matched the OS timer counter since the last clear 1 OS timer match register lt 4 gt has matched the OS timer counter 1
417. ress space e USB OTG Hardware Mode Register USBOTG TL HW MODE 0x0000 Name Default Description Bit 1 0 CRECFG 2911 Core Configuration R W 00 Hardware HNP 01 Host 10 Function 11 software HNP 1 Accesses to the data memory in big endian 3 __ 5 4 HOSTXCVR 2 b10 Host Transceiver Properties 00 TX differential RX differential 10 TX single ended RX differential 01 TX differential RX single ended 11 TX singled ended RX singled ended 7 6 R OTGXCVR 2 b10 OTG Transceiver Properties Same as host transceiver Centrality Communications Inc 191 AT460A BI Developer s Manual Centrality 13 8 8 660 Reserved 14 OTG Analog Signal Short Debounce Enable R W 1 enable the VBUS and ID signal short debounce logic 15 TSTMDE Test Mode R W 23 16 HSTREV 8 h20 Host Revision R 31 24 FUNCREV 8 h20 Function Revision R e USB OTG Core Interrupt Status Register USBOTG TL INT STATUS 0x0004 Name Default Description Bit 0 HCINT 1 bO Host Interrupt To clear this bit all interrupt source flags from HostInterruptStatus register must be cleared or disabled 1 R FCINT 1 bO Function Interrupt To clear this bit all interrupt source flags from FunctioniInterruptStatus register must be cleared or disabled 2 R HNPINT 1 bO HNP Interrupt To clear this bit all interrupt source flags from HnpinterruptStatus regis
418. rface can be implemented with General purpose The Audio CODEC interface is controlled by RISC through RBUS and the audio data transfer between memory and Audio CODEC is through Atlas DMA channel The Audio CODEC interface can support AC97 UDA 125 and LSB justified format but these two formats can t work simultaneously user need to configure the audio codec interface to select the audio format For UDA I F and AC97 PCM data stream there are two DMA channels for PCM audio data in channel 6 and audio data out channel 7 respectively For AC97 I F there is an extra pair of DMA channels for data in channel 8 and data out channel 9 The auxiliary DMA channels can be used for hardware audio mixer function and to transfer some non audio data information such as touch panel sample data The whole Audio CODEC interface can be divided into five parts RISC DSP I O interface register files DMA Interface AC97 Controller Centrality Communications Inc 282 AT460A BI Developer s Manual Centrality Control Tod DSP Register Interface BIT CLK RX FIFO UDA Controller FRAME SYNC DMA Interface TX FIFO AD DATA AC97 DA_DATA Controller Figure 63 Block Diagram of Audio CODEC Interface 8 6 5 Signal Description 8 6 5 1 AC97 CODEC Interface In this AC97 interface Atlas operates as an AC97 codec controller The AC97 interface is a 4 wire digital serial interface with BIT FRAME SYNC AD DATA
419. rial Port 4 5 6 7 IP27 CANBUS 0 1 29 OS Timer 1 5 So there needs to have some 2 level mask bits for those interrupts Please refer to the INT RISC MASK EXT INT DSP MASK EXT registers for the 2 level mask bits e Interrupt Controller DSP Mask Register INT DSP MASK RISC 0x0014 DSP 0x00A 0x00B The definition of each bit is the same as above Bit Default Description 31 0 DM lt 31 0 gt 32 h0 DSP interrupts mask bits W R 0 Pending interrupt is masked from becoming active 1 Pending interrupt is allowed to become active e Interrupt Controller Level Register INT RISC LEVEL RISC 0x0018 The RISC interrupt controller level register INT RISC LEVEL controls whether a pending interrupt generates an FIQ or an IRQ RISC interrupt This register can only be accessed by RISC Centrality Communications Inc 62 460 Developer s Manual Centrality If a pending interrupt is unmasked the corresponding INT_LEVEL bit field is decoded to select which interrupt should be asserted If the interrupt is masked then the corresponding bit in the INT_LEVEL has no effect The following table shows the location of all interrupt level bits in the INT LEVEL question marks indicate that the values are unknown at reset Name Default Description 31 a RIL lt 31 0 gt 3270 Aas Interrupts level bits W R Interrupt routed to RISC IRQ interrupt input i Interrupt routed to
420. ripheral to memory and DMA Channel 9 amp 11 are only for DMA write memory to peripheral Name Default Description 2 m CH8 lt 2 0 gt 3 b000 DMA Channel 8 enable R W CH8 lt 2 0 gt DMA channel 8 is used for CH9 lt 2 0 35000 DMA Channel 9 enable same as above RW 10 lt 2 0 gt 3 b011 DMA Channel 10 enable same as above 11_ lt 2 0 gt 36011 Channel 11 enable same as above R W 3112 12090 e ROM Pad Multiplex Register RSC ROMPAD MUX 0xC Bit Default Description 0 R W PCMCIA interface enable CS 0 s default value is defined by sampling input pad during reset If the pad is pulled low then its default value is 1700 Centrality Communications Inc 82 AT460A BI Developer s Manual Centrality 1 Enabled PCMCIA access ROM pads 0 Disabled PCMCIA cannot access ROM pads 1 R W 1 b1 ROM interface enable mm pis 0 Disabled 2 R W 1761 SmartMedia NAND Flash interface enable 1 Enabled 0 Disabled 3 JReeved 4 R W 1 bO IDE interface enable 0 Disabled 5 R W EXTPAD EN 1 bO External companion chip enable 0 Disabled 31 6 2680 NOTE All reserved register bits have to be written with 0 Otherwise there will be unexpected results 5 8 GPIO 5 8 12 Overview In Atlas II there a total of 188 GPIO Each of the GPI
421. rrupt amp _ SDIO SD Controller Generator rxfifo1 Logic Card Figure 41 SD Host Block Diagram SD SDIO Host Controller provides Programmed IO data transfer method In programmed IO method the Host Driver transfer data using the Buffer Data Port Register Interrupt controller The SD SDIO Host Controller generates interrupt to the RISC SDIO SD Host Controller SDIO SD Host Controller comprises of Host interface SD SDIO controller registers Bus monitor Clock Generator CRC generator and checker CRC7 and CRC16 The SD SDIO controller registers are programmed by the Host Driver Interrupts are generated to the Host based on the values set in the Interrupt Status register SD_INT_STATUS and Interrupt Enable register SD_ NT_EN Bus monitor will check for any violations occurring in the SD bus and timeout conditions The Clock Generator will generate the SD clock depending on the value programmed by the Host Driver in the Host Control Register SD_HOST_CTRL_1 The CRC7 and CRC16 generator calculate the CRC for command and Data respectively to send the CRC to the SD SDIO card The CRC7 and CRC16 checker checks for any CRC error in the Response and Data send by the SD SDIO card DATA FIFO The SD SDIO Host Controller uses four 1K dual port FIFO for performing data transactions two 1K FIFO for read transaction and two 1K FIFO for write transaction During a write transaction data transferred from Host to SD SDIO
422. rt frame transmit receive will continue to send the data in the USP TX DATA no matter whether there are new data 18 R W SOURCE MODE The sync signal source mode 0 TFS is generated by hardware 1 TFS is generated by software from the upper 16 bit of the 32 bit data in the TX FIFO 19 R W Receive sync signal source mode 0 RFS is master mode and output 1 RFS is slave mode and input from the external device O R W MS MODE Transmit sync signal source mode 0 TFS is master mode and output 1 TFS is slave mode and input from the external device 30 21 USP CLK DIVISOR USP serial clock divider R W For ASYNC mode USP CLK DIVISOR fio clock baud ASYNC_DIV2 1 For SYNC mode USP CLK DIVISOR fio clock is 2 1 31 R W IRDA_DATA_WIDTH 1 bO IrDA logic 1 pulse width select ASYNC_DIV2 must be set to 16 in mode Centrality Communications Inc 319 AT460A BI Developer s Manual Centrality e USP Transmit Frame Control Register USP_TX_FRAME_CTRL 9 0 8 DSP 0x4 0x5 Default Description TX_DATA_LEN j Transmitted data length in one frame Must be set to actual tx data length 1 R W 15 8 TX SYNC LEN 870 Valid length of transmitted sync signal TFS Must be set to actual tfs valid length 1 23 16 TX FRAME LEN 870 Transmit frame length include active state and R W idle state Must be set to actual tx frame length 1 i Data
423. rt up time and the small frequency deviation in deciding the CL value The smaller ESR with a higher price also helps to reduce the start up time Please refer to the following table for the CL amp ESR selection guidance This table is for reference only and applicable for typical conditions Table 14 Selection Guide of Crystal for PDXOE3DG Target Freq Hz 2M 6M 6M 10M 10M 20M 20M 30M erep 6 2 fe 5 Oscillator Crystal C2 Figure 11 Oscillator Tank Circuit Centrality Communications Inc 40 AT460A BI Developer s Manual Centrality The above figure shows reference tank circuit for a crystal oscillating in the fundamental mode It shows several components that decide the behavior of the oscillation and they affect the loop in many aspects e Rf represents the feedback resistor to bias the inverter in the high gain region Rf cannot be too low or the loop may fail to oscillate Normally and Rf of 1Mohm is sufficient for MHz band applications Rd represents the damping resistor that helps increase stability save power and suppresses the gain in the high frequency area The trade off for inserting Rd is the reduction of negative resistance Therefore Rd cannot be too large or the loop could fail to oscillate Sometimes users may drop Rd in high frequency applications to reduce the production costs e C1 and C2 are decided according to
424. rupt or Abort exception happen e User writes a 1 to the control bit of this register After the FIFO is flushed the flush control bit will be cleared automatically Bit Name Default Description 0 R W FIFO_FLUSH FIFO flush control bit Set to 1 will flush the FIFO 2 R FIFO_EMPTY FIFO empty bit 31 3 __ 7 2970 1 R W AUTO_FIFO 1 b1 FIFO auto flush bit Set to 1 will enable the automatic flush when exceptions happen RISC Interface Cacheable Memory Size Register RISCINT_MEM_SIZE 0x0004 Centrality Communications Inc 17 AT460A BI Developer s Manual Centrality During boot up the boot program needs to do memory auto sizing and then writes the cacheable non cacheable memory size into the corresponding registers in RISC interface Bit Name Default Description 5 lt 24 0 gt 25 n1FFFFFF Cacheable memory size 32 bit D word R W 31 25 hod Reserved RISC Interface ROM Size Register RISCINT ROM SIZE 0 0008 Bit Name Default Description 28 0 RS lt 28 0 gt 29 htFFFFFFF ROM size in byte R W 31 29 __ 130 X XJ Reseved 0 __ 96_ ________ RISC Interface Boot up Register RISCINT BOOT UP 0x000C After boot up the boot program needs to do re direct the ROM access to the shadowed SDRAM memory space To make sure the setting taking effect as soon as possible user can issue a Flush IO FIFO instruction right after set this Boot up register
425. ry Controller and some other system control modules The clock to these modules can also be disabled when the chip enters Sleep mode because user can power down the PLL and 12 MHz oscillator Centrality Communications Inc 54 AT460A BI Developer s Manual LZ Bit Name Default Description 0 R W 1 bO DSP Core clock enable 1 Enable The following are the same 0 Disable 1 R W ROM EN 151 Flash Controller clock enable 2 R W DMA EN ____ 750 ___ DMA Controller clock enable 4 R W GPS EN ____ 60 GPSclckenable 5 R W USB EN 152 ___ USB clock enable 10 R W SP1 EN ____ 60 Port 1 clock enable O 11 R W 5 2 bo j SeralPor2clockenabe 12 R W SPS 152 SeralPor3clockenabe 13 R W 4_ 152 X SeralPort4clockenabe 14 R W 5_ 1750 SerialPorbclockenabe 16 Rw ________ 60 ___ Reserved 17 5010 ____ 760 SDlOintefaceclockenable ___ 18 R W SM 151 SmartMedia interface clock enable 20 RW 40 Reserved 21 R W lO o VO clock enable 29 R W XINW_EN 151 XINWolockenable 30 R W IDE 60 interface clock enable O 31 bd Reserved NOTE UARTO 6 7 share the same clock enable bit e Power Manager Oscillator Wait Time Register PWR WAIT TIME 0x0034 During wake up sequence from slee
426. s Pixel byte sequence PXD 15 8 PXD 7 0 Table 69 YUV YCrCb 4 2 2 8 bit format Data Bus Pixel byte sequence 8 5 2 3 Pixel Data Processing Input pixel data will be processed as the following steps 1 The pixel data will combine 2 16 bit pixel data to a 32 bit data 2 Reorganize the 32 bit data as CAM SHIFT defined Centrality Communications Inc 270 AT460A BI Developer s Manual Centrality 3 If the input data is YUV YCrCb format YUV to RGB conversion is enabled receiving data will be converted to RGB format data According the LCD display mode the RGB data will be reorganized in 656 565 655 and 888 pattern Scaling the picture as defined in CAM_CTRL register Write the finial data to the FIFO anf 8 5 2 4 Pixel Data Shifting The Video Input Port supports 2 format pixel data 16 bit and 8 bit In 16 bit mode camera interface will receive whole the 16 bit pixel data whatever whether it is connected on the board In 8 bit mode camera interface will select 8 of 16 bit pixel data as a valid input and combine 4 8 bit data to a 32 bit Following table gives an example Table 70 Shift example SHIFT_NUM 3 b000 375011 36010 370001 P1 9 2 P2 9 2 P1 8 1 P2 8 1 P1 7 0 P2 7 0 P3 9 2 P4 9 2 P3 8 1 P4 8 1 P3 7 0 P4 7 0 P5 9 2 P6 9 2 P5 8 1 P6 8 1 P5 7 0 P6 7 0 P7 9 2 P8 9 2 7 8 1 8 8 1 P7 7 0 P8 7 0 P9 9 2 P10 9 2 9 8 1 10 8 1 P9 7 0 P10
427. s arising from future changes to them The may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Centrality sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Centrality literature may be obtained by calling 1 408 982 1818 or by visiting Centrality s website at http www centralitycomm com Copyright O Centrality Communications Inc 2004 Third party brands and names are the property of their respective owners ARM and the ARM Powered logo are trademarks of ARM Limited Centrality Communications Inc 1 460 Developer s Manual LS Centrality COMMUNICATIONS Table of Contents 15 eo petes pe 10 151 QVerview cene te a Ee ee eee 10 1 2 Example System gn den pee ple o ne tie ath die 10 Be RISC ec 10 2 17 OQVervIe Wo eee ieu e e TE nee 10 2 2 Functional Deser iON oiii rea eR e ac E Ree ER Teo e Ead Ra ek ERA e qned eR 10 2 2 1 AISM926EJ o pete in etait tte e s 10 2 2 2 Address Mapping id Ee ro edd ede dau dann ene deco 10 2 2
428. s bit is asserted when HnpState enters A_SLAVE A_MASTER to inform the application so that appropriate action can be taken by software AVBUSVALID VBUS Valid Change Interrupt This interrupt is only valid in Software HNP and Function Host Mode When asserted this means that the VBUS has crossed the a_vbus_vld level Software should read the HnpControlStatus Register to determine the current status of the VBUS ABSESVAILD AB Session Valid Change Interrupt This interrupt is only valid in Software HNP and Function Host Mode When asserted this means that the VBUS has crossed the b_session_vld threshold Software should read the HnpControlStatus Register to determine the current status of the VBUS 4 VBUSERROR VBUS Error Interrupt This interrupt is only valid in Hardware HNP A DEVICE VBUS error due to over current or battery problem 5 SRPINT Session Request Detect Interrupt After receiving this interrupt software must decide if it wants to respond to the Session Request This interrupt is asserted when either a VBUS pulse is detected and or a Data pulse is detected SRPSUCFAIL SRP Success Fail Interrupt This interrupt is only valid in Hardware HNP B DEVICE needs two conditions to know that its session request is successful 1 The state must be in B SLAVE 2 It must detect that A DEVICE is resetting it within the BSrpFailTimer value AIDLEBDTO A Idle B Disconnect Time Out Interrupt This timer is only used in Hardware H
429. s error Read write error counters Lasterror register Programmable error limit warning Capability Atlas II has two CAN Bus Controller CANBUSO and CANBUS 1 These two controllers can work at the same time Besides the normal IO transfer mode canbus also support the DMA transfer A group of registers are implemented to control the DMA transfer There are two DMA channels Channel 0 1 shared by CANBUSO and CANBUS1 Channel 0 for receiving and Channel 1 for sending At one time only one CAN Bus Controller can use the DMA function Please refer to the section of Controller for more details 8 9 2 Pin Description Each CAN Bus Controller has 2 input output pins Table 82 CAN Bus Pin Descriptions Direction Description X_CAN_TXD_n Output Transmit Data X_CAN_RXD_n NOTE For the Pin Names n means 0 to 1 The following figure shows the connection of CAN Bus interface Centrality Communications Inc 328 AT460A BI Developer s Manual Centrality Atlas CAN Bus Controller Figure 73 Bus Interface Connection 8 9 3 CAN Bus Registers The following table shows the address mapping for CAN Bus Controllers Table 83 CAN Bus Address Mapping Block Address 8 9 3 1 CAN Bus Control Registers Table 84 CAN Bus DMA Register Mapping RISC Address Register Description lt 11 0 gt 0 0014 Reserved 7 2 000
430. s status is used to check DAT line level to recover from errors and for debugging This is especially useful in detecting the busy signal level from lt 0 gt 023 DAT lt 3 gt 022 DAT lt 2 gt 021 DAT lt 1 gt 020 DAT lt 0 gt 24 LINE_LEVEL ERE eer This status is used to check CMD line level to recover from errors and for debugging pC Reserved NOTE DAT line active indicates whether one of the DAT line is on SD bus is in use a In the case of read transactions this status indicates if a read transfer is executing on the SD bus Changes of this value from 1 to 0 between data block generates a BLK_GAP_EVT interrupt in the SD_INT_STATUS register This bit shall be set in either of the following cases 1 After the end bit of the read command 2 When writing a 1 to CONTINUE REQ the SD HOST CTRL 0 register to restart a read transfer This bit shall be cleared in either of the following cases 1 When the end bit of the last data block is sent from the SD bus to the HC Centrality Communications Inc 170 AT460A BI Developer s Manual Centrality 2 When beginning wait read transfer at a stop at the block gap initiated by STOP_AT_BLK_GAP_REQ The HC shall wait at the next block gap by driving Read Wait at the start of the interrupt cycle If the Read Wait signal is already driven data buffer cannot receive data the HC can wait for current block gap by continui
431. s the DAT line or the end bit position of the CRC status 0 No Error 1 Error 2 CURRENT LIM ERR By setting the SD BUS PWhAh bit in the RAW SD HOST 0 Register the HC is requested to supply power for the SD Bus If the HC supports the Current Limit Function it can be protected from an Illegal card by stopping power supply to the card in which case this bit indicates a failure status Reading 1 means the HC is not supplying power to SD card due to some failure Reading 0 means Centrality Communications Inc 179 AT460A BI Developer s Manual Centrality 24 that the is supplying power and no error has occurred This bit shall always set to be 0 if the HC does not support this function 0 No Error 1 Power Fail _ o 31 28 VEND_SPEC_ERR i in thi Additional status bits can be defined in this register by the vendor Table 43 Relation between Transfer Complete and Data Timeout Error Transfer Complete Data Timeout Error Meaning of the Status ____ 0 interrupted by Another Factor Timeout occur during transfer Table 44 Relation between Command Complete and Command Timeout Error Command Complete Command Timeout Error Meaning of the Status Interrupted by Another Factor AUTO CMD12 ERR 1 bO Occurs when detecting that one of the bits in R W AUTO CMD12 ERR STATUS register has changed from 0 to 1 This bit is set to 1 also when Auto CMD12 is not executed due to
432. se there was not enough space for that message in the Receive FIFO 0 No data overrun has occurred since the last Clear Data Overrun command was given 1 Transmit Buffer Released The CPU may write a message to the Transmit Buffer 0 Transmit Buffer Locked The CPU cannot access the Transmit Buffer because a message is either waiting for transmission or is in the process of being transmitted 1 The last requested transmission has been successfully completed 0 The last requested transmission has not been completed yet 1 The CANBUS controller is in the process of receiving a message 0 Nothing is currently being received 1 The CANBUS controller is in the process of Centrality Communications Inc 331 AT460A BI Developer s Manual Centrality 6 R 750 transmitting a message 0 No message is being transmitted 1 At least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register EWL 0 Both error counters are below the warning limit 1 The CANBUS controller is in Bus Off state and is not involved in bus activities 0 The CANBUS controller is involved in bus activities 3 8 1240 e CANBUS Interrupt Register CANBUSn IR 0x000C Name ee Default 1 b1 Description Set whenever the Receive Buffer contains one or more messages provided the RIE bit is set w
433. se the same reference clock input from PDXOE3DG 5 2 5 1 PG13A1G3 1GHz PLL 1 The dummy pad is muxed with X SCLK 3 By default the Dummy XIN is disabled If user wants to enable it please contact the Centrality IC Design Group Centrality Communications Inc 41 AT460A BI Developer s Manual Centrality INPUT CHARGE DIVIDER PUMP FIN R 0 3 POWER FEEDBACK DIVIDER DOWN DIVIDER BUFFER FOUT F 0 5 OD BP OEB Figure 12 PG13A1G3 Block Diagram PG13A1G3 is designed to output a clock frequency range between 250MHz 1GHz There are 3 operation modes in PG13A1G3 Normal mode Power Down mode and Bypass mode Normal mode synthesizes suitable FOUT value by programming divider values Power Down mode forces PLL in low power consuming state Bypass mode provides FOUT with the same frequency as FIN It needs a Tready time Pull in Time Locking Time to relock the FIN clock when PLL wakes up from Power Down mode to Normal mode In general it should be reserved a Tready time for re locking when PLL is changed to Normal mode from Power Down or Bypass mode or when any divider setting is changed In Normal mode operation it is necessary to set suitable divider values to make sure PLL functional e PLL Divider Value Setting There divider values NR NF NO to set the PLL output clock frequency Four o Input Divider Value NR NR R lt 3 0 gt 1 o Feedback Divider Value NF NF 3 NO F lt 5 0 gt
434. select which interrupt status is indicated to the Host System as he Interrupt These status bits all share the sample 1 bit interrupt line Setting any of these bits to 1 b1 enables interrupt generation R R R R W 7 R W 8 R W 9 R W 0 DAT TIMEOUT ERR INT SIG EN S TNEOUTERRINT SIOEN 1 R W 2 R W 3 R W 4 R W R W 5010 Auto CMD12 Error Status Register SD AUTO CMD12 ERR STATUS When Auto CMD12 Error Status is set the HD shall check this register to identify what kind of error Auto CMD12 indicated This register is valid only when the Auto CMD12 Error is set Default Description AUTO_CMD12_NOT_ 160 If memory multiple block data transfer is not EXEC started due to command error this bit is not set because it is not necessary to issue Auto CMD12 Setting this bit to 1 means the HC cannot issue Auto CMD12 to stop memory multiple block transfer due to some error If this bit is set to 1 other error status bits 004 001 are meaningless 0 Executed 1 Not Executed command If this bit is set to 1 the other error AUTO_CMD12_TIME 1 bO Occurs if the no response is returned within OUT_ERR 64 SDCLK cycles from the end bit of the status bits 004 002 are meaningless Centrality Communications Inc 182 AT460A BI Developer s Manual Centrality a 1 Timeout AUTO_CMD12_CRC_ Occurs when detecting a CRC error in the ERR command response 0 No Error 1 CRC Err
435. served e Interrupt Mask LCD INT MASK 0x184 This register provides the interrupt mask for all the LCD interrupt sources If a mask bit is set to 1 that interrupt is enabled Then if the interrupt status bit goes to 1 an interrupt is generated to the RISC If the mask bit is set to 0 then no interrupt is generated although the status bit can still be set to 1 and be cleared by writing to the above register Bit Default Description 3110 20 Reserved e Interrupt Line Number LCD SCN INT LINE 0x188 Bit Name Default Description 10 0 LINE_NUM 11 h0 This value represents the line number at which a screen R W interrupt will be generated This allows the user to specify a line during which an interrupt will be generated for each frame The interrupt is generated at the beginning of that Centrality Communications Inc 134 AT460A BI Developer s Manual Centrality particular line a ENTE AUD LINE VALID 1 bO This bit determines whether the line number below is valid R W for generating a screen interrupt This differs from the mask in that if this bit is not set then the interrupt status bit for the screen interrupt will not be set When this bit is set then the interrupt status bit is set each time the line count is equal to the value below 31 13 6 2 4 11 FIFO Data Read Write Registers These registers are only for test purpose Both the screen and
436. sh used case of command address command see Samsung s NAND Flash more than 128MB 31 16 160 Reserved Flash Low Address Register SM LOW ADDR 0x14 Name Default Description Bit LO_ADD lt 31 0 gt 32h0 Start address to data flash R W Flash High Address Register SM_HIGH_ADDR 0x18 Bit Default Description 7 0 R W 0 lt 7 0 gt Start address to data flash 318 Flash Page Size Register SM PAGE SIZE 0x1C The default value of PAGE SIZE is 528 bytes which is the NAND Flash page size User need not change it if NAND Flash has no change The bit2 bitO will be ignored i e this value must be DWORD size Bit Name Default Description 11 0 R W PAGE SIZE 12 h210 528 bytes per page Centrality Communications Inc 265 460 Developer s Manual Centrality 21 12 2040 Reserved NAND Flash Interrupt Enable Register SM INT EN 0x20 Default value is 0 Set the bit to 1 will enable the interrupt but the according bit in SM NT STATUS will be set no matter whether the interrupt is enabled Bit Name Default Description Reserved 1 R W WT ADD DONE EN 1 bO Interrupt raised when write address to smartmedia is done 2 R W IO DMA DONE EN p Interrupt raised when I O or DMA transfer is done 3 R W FIFO THRESHOLD E 1 b0 Interrupt raised when the number of data N in
437. should only be changed when the FIFO is empty Centrality Communications Inc 246 AT460A BI Developer s Manual Centrality 2 Selection of Timer Set 0 or Timer Set 1 register sets is controlled by the I O Window Control bits 7 and 3 and the Memory End Address High register bits 7 6 There are two separate Setup Timing registers each with identical fields The setup timing registers for each timer set controls how long a PC card cycle s command that is noe nwe niord or niowr setup time will be in terms of the internal clock cycles The overall command setup time will be S 22x Nval 1 The value of S representing the number of clock cycles for the command setup is then multiplied by the clock period and the actual command setup time is obtained Default Description 5 0 R W SMV lt 5 0 gt 6 h1 Setup Multiplier Value CD This field indicates the integer value Nval from 0 to 63 it is used to control the length of setup time before a command becomes active 7 6 R 270 __ e M6730 Command Timing 0 1 Register M6730 TIMING 0 1 Index Ox3B 0x3E NOTE The Command timing set 0 resets to 6 h03 for socket timing equal to 230ns PC card timing whereas Timing set 1 resets to 6 h09 for socket timings equal to 59015 card timing There are two separate Command Timing registers each with identical fields The command timing registers for eac
438. sses made with timing specified in Timer Set 0 registers 1 b1 Accesses made with timing specified in Timer Set 1 registers This bit determines the access timing specification for the I O window 1 e M6730 System I O 0 1 Start Address Low Register M6730 SIO MAPO 1 SAL Index 0x08 0x0C There are two separate System I O Map Start Address Low registers each with identical fields Bit Default Description 7 0 R W SA lt 7 0 gt 870 Start Address lt 7 0 gt This register contains the least significant byte of the address that specifies where in the O space the corresponding map will begin accesses that are equal or above this address and equal or below the corresponding system I O map end address will be mapped into the space of the corresponding PC card e M6730 System I O Map 0 1 Start Address High Register M6730 SIO MAPO 1 SAH Index 0x09 0 00 There are two separate system Map Start Address High registers each with identical fields Bit Name Default Description 7 0 R W SA lt 15 8 gt 8 hO Start Address lt 15 8 gt This register contains the most significant byte of the address that specifies where in the O space the corresponding I O map will begin accesses that are equal or above this address and equal or below the corresponding system I O map end address will be mapped into the I O space of the corresponding PC card M6730 System I O Map 0 1 End
439. ster is reset to 1 bO 4 An address phase comes for an window when the earlier data transfer is still going on to the PC card 5 When a1 b1 is written to the bit 7 of the register M6730 Misc Control 2 Register M6730 MISC CTRL2 Index 0x1E Centrality Communications Inc 241 AT460A BI Developer s Manual Centrality Bit Name Default Description ORW ____________ 160 f Reserved 1 R W LPD MODE 1 bO Low power Dynamic Mode 1 b0 Clock runs always 1 b1 Normal operation stop clock when possible This bit determines whether Low power dynamic mode is enabled or not 2 R W SPD_MODE 1 bO Suspend Mode 1 b0 Normal operation 1 b1 Stop internal clock enable all low power modes and disable socket access This bit enables or disables the Suspend mode 5 3 RW J HO Reserved 6 R W 1 bO Debounce Enable 1 b0 Disable debounce 1 b1 Enable debounce When ever this bit is set ncd1 and ncd2 signals from port are passed through the debouncing circuit which is used to avoid glitches and bouncing of card detect signals 7 R W RI OUT 1 bO nriout nintb irq10 is nriout 1 b0 Normal interrupt operation on the nri out nintb irq10 signal 161 nri out nintb irq10 is connected to ring indicate signal on the system logic This bit determines the function of the nriout nintb irq10 signal When this bit is set to 1 b1 nriout nintb irq10 can be used to trigger restorat
440. sure this register is written last after all the other DMA registers are setup correctly already x Description OSD2_DMA Write 1 to start OSD2 layer DMA this bit is self cleared 31 1 __ 130 X Reserved 6 2 4 10 Interrupt Registers The LCD can generate interrupts from several different sources It can generate an interrupt when the screen the OSD FIFO or the OSD2 FIFO underflows or overflows it can generate an interrupt when the vertical counter reaches a pre determined line number i e can be used as a frame interrupt finally it Centrality Communications Inc 133 460 Developer s Manual Centrality can generate an interrupt when the screen the OSD FIFO or the OSD2 FIFO DMA is completed Each interrupt source can be independently masked and cleared e Current Interrupt Status and Interrupt Clear LCD_INT_CTRL_STATUS 0x180 Read this register to determine source of interrupt If a particular bit reads 1 then that interrupt is asserted Writing a 1 to a particular bit clears the interrupt for that source This is the only way to clear the interrupt The hardware will not clear any interrupts Note The interrupt bit for each source can be read and or cleared even if the mask bit is not set Without the mask bit however an interrupt will not be generated to the RISC Bit Name Default Description 1 RW OSD_OFLOW_INT OSD FIFO Overflow Interrupt 3130 HOT Re
441. t 0 Use normal HSYNC signal i e generated from HSYNC width and HSYNC period 01 Use 1 alternate HSYNC signal alt hsync1 The alt hsync1 register must be set to a valid value Note HSYNC signals with different timing may be required for different display modes such as the STN modes Test Purpose register software writes this with 0 Remark Mask pixel clock control1 1 7 Pixel clock is masked to O whenever the pixel output data are invalid Note This signal only masks the pixel clock to the external pin The internal pixel clock is not masked so logic operation remains the same Note Masking the PIXCLK is useful for certain display modes such as STN displays Test Purpose register software writes this with 0 PCLK MASK1 PCLK MASK2 HSYNC MASK Remark Mask pixel clock control2 1 7 Pixel clock is masked to 0 whenever the pixel output data in a line are valid but is not masked for lines in vertical blank time This bit is not valid in FRC valid mode Test Purpose register software writes this with 0 Remark Mask HSYNC control 1 7 Disable the HSYNC during vertical blank time 0 Enable the HSYNC during vertical blank time CS LATENCY Test Purpose register software writes this with 0 R W Centrality Communications Inc 111 AT460A BI Developer s Manual VSYNC SEL 1 bO External VYSNC select 0 Use normal VYSNC signal i e generated from VYSNC width and VYSNC period 1 Use
442. t 32 0x20 R lt 3 0 gt 2 OD 2 PG13E3G requires 2 pairs of power supply in single voltage 1 2V as following e AVDD AVSS Analog Power amp Ground DVDD DVSS Digital Power amp Ground In system design all power AVDD DVDD and ground AVSS DVSS should be considered as analog power DO NOT share these power ground with any other power ground planes in the system 5 2 6 Multiplexer amp Divider There are 3 stages of multiplexer amp divider 1 4 to 1 MUX 2 Clock Divider 3 8 to 1 or 5 to 1 MUX 5 2 6 1 4 to 1 MUX There 4 of such 4 1 MUX s one for each of the following clock domains system clock USB clock 0 1 Each MUX have 4 input clock sources e High speed oscillator PDXOE3DG Real time oscillator PDXOE4DG PLL1 PG13A1G3 e PLL2 PG13E3G There is a 2 bit select signal for each of the MUX to choose one of the 4 input sources These signals are controlled by the PWR_CLK_SWITCH register Please refer to the Atlas 2 Developer s Manual for more details 5 2 6 2 Clock Divider Each 4 to 1 is followed by a clock divider The purpose of the clock divider is to divide the clock output of the 4 to 1 MUX to a lower frequency clock so that it can be used by the internal logic of Atlas 2 There are two types of clock dividers though First type is only for the system clock domain And the second type is for USB CKO_0 and CKO_1 domains The difference is t
443. t PXD Figure 56 Block Diagram of Video Input Port Centrality Communications Inc 269 AT460A BI Developer s Manual Centrality 8 5 2 Functional Description 8 5 2 1 Control Signals The Video Input Port can work in master mode or slave mode with three main control signals PIXCLK HSYNC and VSYNC PIXCLK toggles once for every pixel HSYNC toggles once at the beginning of each line and VSYNC toggles once at the beginning of each image frame These signals define the size of one frame of picture The programmer can select VSYNC HSYNC and PXCLK generate internal or provided by external device by setting register CAM In master mode the programmer must select VSYNC HSYNC generate internal after setting the HSYNC and VSYNC period to provide a control interface for external device PXCLK can also be provided internally by setting register CAM PXCLK CTRL and CAM CTRL In slave mode these three signals are provided by external devices 8 5 2 2 Data Signals The Video Input Port supports following data format 1 Upto 16 bit RGB data 2 YUV or YCrCb 4 2 2 8 bit and 16 bit Column gt 97618161816 RIGIRIGIRIG RIG R G R G R G R G RIG GB Figure 57 16 bit RGB Data Format Table 68 YUV YCrCb 4 2 2 16 bit format Data Bu
444. t 2 Port 3 3124 Reserved e USB OTG Root Hub Status Register USBOTG HC RH STATUS 0 00 0 Bit Default Description IA Reserved 1 R OVRCURI Over Current Indicator This bit reports over current conditions when the global reporting is implemented When set an over current condition exists When cleared all power operations are normal If per port over current protection is implemented this bit is always 0 142 LSEVEWWUE reg ae DEVCONWUE Device Connect Wakeup Enable R W This bit enables a ConnectStatusChange bit as a resume event causing a USBSUSPEND to USBRESUNE state transition and setting the ResumeDetected interrupt 0 ConnectStatusChange is not a remote wakeup event 1 ConnectStatusChange is a remote wakeup event Centrality Communications Inc 207 AT460A BI Developer s Manual Centrality Writing a 1 sets DeviceRemoveWakeupEnable Writing a 0 has no effect 16 J Reserved 17 OVRCURCHG 1 bO Over Current Indicator Change This bit is set by hardware when a change has occurred to the OCI field of this register The HCD clears this bit by writing a 1 Writing a 0 has no effect 30 18 f Reserved O 31 CLRMTWUE Clear Remote Wakeup Enable USB OTG Port Status1 Register USBOTG HC PORT1 STATUS 0x00F4 Bit Default Description 0 R W CURCONST 1 bO Current Connect Status
445. t data PID to be sent by hardware is determined by this bit This bit is updated by Hardware after each successful transmission Software should change this bit while the EP is currently empty or disabled if they wish to change the next data toggle bit AT460A BI Developer s Manual Centrality This register has different definitions when it s read or written Bit Name Default Description 10 0 R 17 0 Last Frame Number Hardware will set this value based upon the FrameNumber contained in the last received SOF packet Bit Name Default Description 31 0 W EPRDYCLEAR 320 Endpoint Ready Clear Writing a 1 to this register will clear the corresponding Endpoint Ready bit but will not affect the Frame Number This is a workaround that had to be implemented due to a register contention condition that exists in the Core Since address space was not available the Frame Number register was multiplexed with this functionality e USB OTG Host Control Register USBOTG HC CONFIG 0x0080 Name Default Description CTLBLKSR 270 Control Bulk Service Ratio This setting dictates the number of CONTROL packets sent out for each BULK packet 00 1 1 01 2 1 10 4 1 11 8 1 3 2 HCUSBSTE Host Controller USB State R W Software uses these bits to control the state of the USB state machine 00 USB reset 01 USB resume 10 USB operational 11 USB suspend 4 R W RMTWUEN
446. t flag and enable disable bit If the disable bit is asserted the DMA will be stopped If a DMA is finished it will generate an interrupt to the RISC or DSP The interrupt can also be enabled or disabled 8 3 2 3 DMA Configuration Register file In order to setup a DMA the programmer needs to know the following 1 Is this a read from memory or write to memory 2 Where to get the data 3 Where to put the data 4 How to get the data i e consecutively or with jumps in between 5 Whatis the priority of this transfer These parameters are defined by a series of registers that the programmer must set in order to setup a DMA properly Each of the channels listed above has its own registers which means that the DMA s four 4 different channels can co exist at the same time Each set of the registers define the following values Note registers for DMA channel 0 is used as an example here All the channels have the same register definitions e Starting Address This is a 25 bit address that defines the starting address of the DMA transfer in System Memory i e either SDRAM or SRAM If SRAM is used then the top bits are ignored The starting address is defined in register CHO Note ADDR will trigger the start of a DMA and must be set AFTER all the other registers The Starting Address is a DWORD address e Xvalue This is a 16 bit value which defines how many consecutive DWORDS to access per li
447. t must be suppressed at the end of each DMA line For example if bits lt 23 12 gt is set to 17 and bits lt 11 0 gt is set to 3 then for every 17 DWORD is that is written to the FIFO 3 DWORD writes are suppressed 23 12 VALID DW NUM 1210 The number of valid DWORD writes to the FIFO per line R W 31 24 180 Reseved 0 NOTE Keeping this register as zero means all the DWORD s are valid no suppress e OSD FIFO Write Suppress Register LCD OSDFIFO SUPPRESS 0xDC Similar to LCD SCNFIFO SUPPRESS Bit Default Description 11 0 1270 number of DWORD writes to the FIFO that must be R W suppressed at the end of each DMA line For example if bits lt 23 12 gt is set to 17 and bits lt 11 0 gt is set to 3 then for every 17 DWORD is that is written to the FIFO 3 DWORD writes are suppressed R W 31 24 Cd HOT Reserved e 0502 FIFO Write Suppress Register LCD OSD2FIFO SUPPRESS OxEO Bit 11 0 R W 23 12 VALID DW NUM 1210 The number of valid DWORD writes to the FIFO per line R W 3124 0 0 j e FIFO Address Reset Register LCD FIFOADD RST OxE4 Default Description 12 h0 The number of DWORD writes to the FIFO that must be suppressed at the end of each DMA line For example if bits 23 127 is set to 17 and bits 11 0 is set to 3 then for every 17 DWORD is that is written to the FIFO 3 DWORD writes are suppressed Default Descri
448. t value of the RGB select index for choosing which color to output based on the RGB sequence for displays which require outputs of a single color at a time 2 R OSD2 HVALID STA Current value of the valid signal for the OSD2 region 3 R VOSD2 VALID STA 1 bO Current value of the vertical valid signal for OSD2 region 4 OSD HVALID STA Current value of the valid signal for the OSD region 5 R VOSD VALID STA Current value of the vertical valid signal for OSD region 6 R SCN VALID STA 1 bO Current value of the screen valid signal i e the current line count and pixel count are all within the active region VSCN VALID STA Current value of the vertical screen valid signal i e the current line count is within the active SR VsYNC STA 150 of the internal vertical sync signal 9 R HSYNC STA Current value of the internal horizontal sync signal 10 R PCLK STA Current value of internal pixel clock 31131 230 Blanking Register LCD BLANK 0x60 Bit Default Description 23 0 Blank 2470 Pixel value to be used for the inactive region R W Value Bits 23 16 R value Bits 15 8 G value Bits 7 0 B value Note In BYPASSMODE or FRC mode the LSB of this value is used for the inactive region for 4 bit mode it s 4 LSB for 8 bit mode it s 8 LSB for 12 bit mode it s 12 LSB and for 16 bit mode it s 16 LSB 24 Blank 1 bO Use blank value R W Valid 1 Use blank valu
449. tandard SDRAM Memory Read Timing 2 440040 0 0 1 10 Standard SDRAM Write Timing sese nennen ener 10 DDR SDRAM Memory Read 10 DDR SDRAM Memory Write 10 Timing eerte LH RERO RN AR RIO a SERO 10 bed data TIMING ite eet e P is 10 Nand rom read data Timing 011004 nennen nnne entren nennen tenen 10 Nand rom write data 10 Centrality Communications Inc 9 AT460A BI Developer s Manual LS Centrality COMMUNICATIONS Table 112 Table 113 Table 114 Table 115 2 ee uu ea eed do eos 10 Serial Port AC Timing 2 10 Timing Specifications USB Output 10 HAG Timing SpecifICation c e ere eie deed reet Hee a D SER SERT 10 Centrality Communications Inc 10 AT460A BI Developer s Manual gt Centrality 1 Introduction 1 1 Overview Centrality Atlas l 6 application processor is a highly integrated SoC that incorporates a 32 bit ARM RISC processor core 16 bit DSP core a GPS baseband LCD controller a SDRAM DDR memory controller and multiple peripheral interfaces Compared with Atlas I application processor family the AT
450. ted four bit wait state registers which specify up to 15 wait states to be automatically generated for each of four regions The Block memory DMA BDMA transfer allows loading and storing of program instructions and data The BDMA circuit is able to access the external memory space while the processor is operating normally In Atlas II DSP subsystem there are two types of peripheral devices that can be accessed by DSP core One is slow device that can run at slower clock frequency than DSP core the other is fast device that always run at the same clock frequency as the DSP core There are many slow devices that can be Centrality Communications Inc 23 AT460A BI Developer s Manual Centrality accessed by DSP core but fast device is only GPS which occupies the DMX memory space 0x2000 0x2FFF Either or BDMA can be used to access slow devices but only the 16bit mode is supported following table shows the IO space mapping of the DSP in Atlas Il Every slow device occupies 128 16 bit WORD space Table 6 DSP IO Device Address Mapping DSP Address Address space Device Mapped 0x000 0x07F 10 Interrupt controller ____ Video Input Port 0x100 0x17F_ 0 Audio CODEC 2 0x180 0x1FF 0 2 0 200 0 27 0 0x280 0x2FF 0 50 OX300 0x37F J 989 1 _ 0 152 0 583 _
451. ter must be cleared or disabled ASHCINT Asynchronous Host Interrupt To clear this bit the HostClockEnable bit must be set in the Clock Control Register ASFCINT Asynchronous Function Interrupt To clear this bit the FunctionClockEnable bit must be set in the Clock Control Register 5 R ASHNPINT Asynchronous HNP Interrupt To clear this bit the MainClockEnable bit must be set in the Clock Control Register 46 160 jResevd 5 Core Interrupt Enable Register USBOTG TL INT 0 0008 Bit Name Default Description 76 1 e USB OTG Clock Control Register USBOTG TL CTRL 0 000 Bit Default Description 0 R W MAINCLK Main Clock Enable Centrality Communications Inc 192 AT460A BI Developer s Manual Centrality HSTCLK Host Clock Enable 2 R W FUNCCLK Function Clock Enable 3 3 __ 2980 e USB OTG Reset Control Register USBOTG TL RST 0x0010 This register allows for independent reset of the block of the core When set the bit will reset all of the registers of the block to their default condition Each bit is self clearing after the reset is complete Bit Default Description 76 260 Reseved e 5 Frame Interval Register USBOTG TL FRM INTERVAL 0x0014 Name Default Description Bit 13 0 FRMINTERVAL 14 h2bED Frame Interval R W F The value written her sets the width of a frame
452. th between the end of last R W line to the beginning of next line i DSP DMA Byte Mode Register DSP_BYTE_MODE RISC 0x1C DSP 0 1 0 Bit Name Default Description 0 Not enabled 0 The first DWORD write to DMX is not a dummy write 31 2 __ 310 Reserved DSP DMA Memory Mode Register DSP MEM MODE RISC 0x20 DSP 0x1C00 Bit Default Description 0 R W 1 bO 0 PM is organized as single buffer 1 PM is organized as double buffer 1 R W 1 bO If single buffer 0 DSP takes it 1 System bus takes it If double buffer 0 PM is organized as double buffer mode 1 DSP takes buffer 2 System bus takes buffer 3 1 PM is organized as double buffer mode 2 DSP takes buffer 3 System bus takes buffer 2 2 R W 1 bO 0 DMX is organized as single buffer 1 DMX is organized as double buffer 3 R W 1 bO If single buffer 0 DSP takes it 1 System bus takes it If double buffer 0 DMX is organized as double buffer mode 1 DSP Centrality Communications Inc 26 460 Developer s Manual Centrality takes buffer 2 System bus takes buffer 3 1 DMX is organized as double buffer mode 2 DSP takes buffer 3 System bus takes buffer 2 4 R W DMA ENDIAN 1 bO 0 Inverted endian 1 Normal endian 6 5 DMY MODE 290 00 DSP takes both DMY SRAM and GPS SRAM R W 01 System bus takes DMY SRAM DSP takes the GPS SRAM 10 DSP takes DMY SRAM system bus takes GPS SRAM 11 System bus t
453. the OSD FIFO can be pushed and popped by writing and reading into the PUSH POP registers respectively The read or write pointer will be incremented automatically This can be used to insert or remove values from the FIFO The other way the FIFO memory can be accessed is directly reading or writing the memory location In this case the address specifies which location in the FIFO is being accessed e Push Pop Screen FIFO LCD SCN FIFO PUSH POP 0x400 Bit Name Default Description 31 0 PUSH POP If this register is read the first value in the screen FIFO will be popped out i e the value read and the read index increased Ifthis register is written then the value is pushed into the screen FIFO i e the value is written to the end of the FIFO and the write index is increased e Read Write ScreenFIFO LCD SCN FIFO 0x600 0x7FC Bit Default Description 31 0 FIFO_DATA Values in the screen FIFO Can directly read or write values R W anywhere in the FIFO by specifying the corresponding address Push Pop OSD FIFO LCD OSD FIFO PUSH POP 0x800 Bit Default Description 31 0 PUSH_POP If this register is read the first value in the OSD FIFO will be R W popped out i e the value read and the read index increased If this register is written then the value is pushed into the OSD FIFO i e the value is written to the end of the FIFO and the write index is increased e Read Write OSD FIFO LCD_O
454. the SD card supports Read Wait and has set RD WAIT CTRL to 1 In case of write transfers in which the HD writes data to the SD BUF DATA register the HD shall set this bit after all block data is written If this bit is set to 1 the HD shall not write data to Buffer data port register This bit affects RD TRAN ACTIVE WT TRAN ACTIVE DAT LINE ACTIVE and CMD INHIBIT DAT the 5D CUR STATE register 1 Stop 0 Transfer CONTINUE REQ This bit is used to restart a transaction which was stopped using the STOP AT BLK GAP To cancel stop at the block gap set STOP AT BLK GAP REQ to 0 and set this bit to restart the transfer The HC automatically clears this bit in either of the following cases 1 In the case of a read transaction the DAT LINE ACTIVE changes from 0 to 1 asa read transaction restarts 2 In the case of a write transaction the WR TRAN ACTIVE changes from 0 to 1 as the write transaction restarts Therefore it is not necessary for Host driver to set this bit to O If STOP AT GAP is set to 1 any write to this bit is ignored 1 Restart Ignored 0 RD_WAIT_ ee 1 bO The read wait function is optional for SDIO cards If the card supports read wait set this bit Centrality Communications Inc 172 460 Developer s Manual register the HD shall check the Voltage Support bits in the Capabilities register If an unsupported voltage is selected the Host System shall not supply S
455. the crystal CL specification In the steady state of oscillating CL is defined as the C1xC2 C1 C2 In fact the I O ports the bond pad and package pin all contribute the parasitic capacitance to C1 and C2 Therefore we can rewrite CL to be C1 xC2 C1 C2 where C1 C1 Cin stray C2 C2 Cout stray In this example the required C1 and C2 would be reduced This tank circuit is for parallel resonance but not for series resonance Since C1 C2 Rd and Rf vary with the crystal specifications there is no single set of component specifications for all applications For reference values please contact the Centrality Design Group with your crystal specifications For the PDXOE3DG oscillator there are two extra design considerations 1 There is divide by 2 circuit on the output of PDXOE3DG By default this divide by 2 circuit is disabled If user wants to enable it please contact the Centrality IC Design Group first 2 There is a dummy pad sitting besides of PDXOE3DG This is for test purpose only on ATE tester PDXOE3DG will not allow a high speed clock to feed in through it So if we want to do high speed test on ATE tester we need to use a dummy IO This dummy XIN is enabled when TEST_MODE lt 1 0 gt JTAG_MODE lt 1 0 gt Dummy XIN 750 5 2 5 PLL There are two different PLL s in Atlas 2 one is 1GHz PLL TSMC PG13A1G3 the other is 400MHz PLL TSMC PG13E3G Both PLL s u
456. the current request level for each FIFO High Mid Low Watermark WaterMark WaterMark T T T FIFOFULL Empty FIFO 0 COUNT DMA Request gt lt gt lt gt lt gt Level 3 2 1 0 Figure 25 Screen and OSD FIFOs Request Level The DMA requests to the bus interface are generated based on the FIFO fullness counter Atlas Processor provides two methods of requests generation selected by bit24 of SCNFIFO register When this bit is 0 four request values 00 01 10 11 are valid When the FIFO reaches the low water mark then it will generate a low level request 01 When the FIFO reaches the middle water mark then it will generate a mid level request 10 When the FIFO reaches the high water mark then it will generate a high level request 11 When bit24 is equal to 1 only high and low water marks are useful and only two request values 00 11 are valid When the FIFO fullness is less than the high water mark it will generate a high level request 11 When the FIFO fullness is over the low watermark the request stops 00 The second method will lead much more continuous data dumps from memory than the first method It is obvious that enlarge any of the watermark will make the FIFO more aggressive e Screen FIFO Control Register LCD SCNFIFO 0xCO Bit Name Default Description 6 0 LO 7 h60 Value for the low request w
457. the output frame Slot 2 contains the valid data and the tag bit of Slot 1 is asserted if read operation the tag bit of Slot 2 is de asserted the data stream in Slot 2 is abandoned input frame from AC97 CODEC to Atlas II AC97 Controller interface Slot 1 echoes the control register read address bit 18 to bit 12 and for the variable sample rate it delivers the request flags for all output slots bit 11 to bit 2 The echoed address is valid only when Slot 1 is tagged valid but the request flags are independent of the tag bit When Slot 2 is tagged valid the input frame Slot 2 contains the 16 bit control register read data When Atlas II AC97 Controller issues the control register read write command the AC link output frame is illustrated in the following diagrams Centrality Communications Inc 285 AT460A BI Developer s Manual Centrality SYNC eho tle lt Slot 0 l Slot 1 UL ER A Frame Slot1 Slot2 M ID Bit 19 ES 18 12 Bit 11 0 Valid Read 1 Reg Addr RSVC 0 Figure 64 AC link Output Frame Read Command Diagram SYNC 4 Slot 0 pla Slot 1 e Slot 2 gt m JUL UL HE Ib BUD DA DATA 02067 062067 0000078 Frame Slot1 Slot2 CODECID Bit 19 Bit 18 12 Bit 11 0 Bit 19 4 Valid Write Reg Addr RSVC Write Data Figure 65 AC link Output Frame Write Command Diagram The following figure is the diagram f
458. the valid data length is define by the TXFIFO WIDTH 0 invalid 1 valid 2 R W RX OFLOW 1 bO RXFIFO overflow Interrupt 1 valid 3 R W TX UFLOW 1 bO TXFIFO underflow interrupt 0 invalid 1 valid 4 R W DMA IO RX DONE 1 bO RXFIFO has received all data of the data package whose SIZE is defined by USP RX DMA IO LEN REG 0 invalid 1 valid 5 R W DMA IO TX DONE 1 bO TXFIFO has transmitted all the data of a data package whose SIZE is defined by USP TX DMA IO LEN REG 0 invalid 1 valid 6 R W RXFIFO FULL 1 bO RXFIFO full interrupt 0 invalid 1 valid 0 invalid Centrality Communications Inc 322 AT460A BI Developer s Manual Centrality RXFIFO_THD_REACH It s time to read USP_ RXFIFO when the number of data in the USP_ RXFIFO reaches the threshold 0 invalid 1 valid u 9 R TXFIFO THD REACH It s time to write USP_TXFIFO when the number of data in the USP_TXFIFO reaches the threshold 0 invalid 1 valid 1 bO 1 bO 10 R W UART FRM ERR 1 bO Receive an error UART frame interrupt 1 bO 0 invalid 1 valid W 11 UART BREAK If this bitis become 1 it mean that the RXD line become low level Then receiving action must stop Disable the RX ENA bit in the TX RX ENA register and wait UART BREAK become to high then delay some time to double check this bit again if no new break happens enable the RX wait some time reset and restart the USP RXFIFO to
459. time and the BLANK registers define the output value for the blank region In order to accommodate different timings for HSYNC and VSYNC for different types of displays two alternative signals can be generated to use as HSYNC and VSYNC signals These signals are defined by the ALT HSYNC1 and ALT_VSYNC7 registers The bit8 and the bit9 of TIMCTRL register are used to select the source of HSYNC and VSYNC signals Also to accommodate certain displays the pixel clock can be masked by setting the mask pixel clock bits bit10 bit11 of LCD TIMCTRL And the HSYNC signal can also be masked by setting the bit12 of TIMCTRL e Sequence for RGB outputs LCD RGBSEQ 0x40 Bit Name Default Description 5 0 EVEN RGBSEQ 6 h0 These bits represent the RGB output sequence for even R W number lines 11 6 ODD RGBSEQ 6 hO For displays requiring only one color per pixel these bits R W represent the RGB output sequence for the odd number lines Two bits each represent a color 00 Red 01 Green 10 Blue For example 000110 means the sequence is R G B R G B and 100100 represent B G R B G R etc For displays requiring all three color values per pixel this register has no effect 3142 20 0 Reserved Timing Control Register LCD TIMCTRL 0x44 Description Reserved This bit should always be 1 b0 tao IO 1 50 Pixel clock master mode 1 Atlas I Processor drives pixel clock 0 7 disp
460. to specify whether each pixel is 4 bits 8 bits 12 bits or 16 bits 0 Follow the display mode in bits 3 1 Note One of the main uses for the bypass mode is for STN type displays Note The palettes for the OSD and the blank values are also bypassed i e they are not broken up into RGB components and bits R W lt 15 0 gt are used directly to determine the output Note In 12 bit or 16 bit bypass mode OSD mixing is no longer valid The OSD mixer value must be either 000 or 100 i e 100 screen or 100 OSD Dual scan mode 1 Dual scan for STN LCD The channel for the OSD display is used for the dual scan s second channel that is OSD is invalid in this mode This mode is generally used with the bypass mode and with the 4 bit or 8 bit output format 0 Dual scan mode is invalid 8 OSD DW BLE Big Little Endian selection of byte for OSD image 6 7 DUAL_SCAN it SCN_BPP R W Centrality Communications Inc 114 460 Developer s Manual Centrality 9 SCN_DW_BLE Big Little Endian selection of byte for screen R W image data from SDRAM 1 Little Endian MSB byte3 byte2 byte1 byte0 LSB 0 Big Endian MSB byte0 byte1 byte2 byte3 LSB OSD_BYTE_BLE Big Little Endian selection in the OSD image byte R W data the second channel image data in dual scan mode only for 4 bit pixel 2 bit pixel 1 Little Endian 0 Big Endian data the
461. to 32 channels share 1 baseband processor RF FIFO store RF data it is a 1 5Kx32bit RAM The processor s frequency can be more than 100 2 Processor switches to process next channel after correlating 1023 chip of current channel During switch the current channel s correlation results reading address of RF FIFO DDFS NCO value and code NCO value store into the data RAM and then the next channel s DDFS frequency code NCO frequency PRN number RF FIFO address DDFS NCO value and code NCO value load from data RAM After all channels being processed interrupt is generated to DSP or RISC DPS or RISC will process the data from baseband processor and write the new DDFS frequency and code NCO frequency back The architecture of shared baseband processor can reduce circuit scale If the speed of DSP or RISC and baseband processor is higher more channels can be supported Sample clock is generated on chip or can also be supplied off chip Host interface is the interface between GPS baseband processor and DSP or RISC The Timing control block generate timing control signal for correlator channel switch and so on GPS Interface block will have a 8KB dual port RAM for communication with RISC DSP and external memory The RAM can be accessed by either RISC or DSP but not at the same time 8 11 2 Pin Description Table 92 GPS Pin Descriptions Direction Description X_RF_DATAIN 1 Sign bit of GPS baseband signals from GPS RF X_RF_DATAI
462. to the address The color component is 6 bits each specifying the 6 MSB of a 4 bit value This palette is used for 4 bit color value The 64x32bit RAM is used for dithering sequence of frame rate control in passive color mode It generates a 32 x 64 entry to support 32 grey scale levels for every R G B color As the dithering sequence for one gray color is 64 bit the bottom half RAM is used for the first 32 bits of the dithering sequence and the up half RAM is used for the other 32 bits of the dithering sequence 6 2 4 LCD Controller Registers Table 29 LCD Controller Regsiter Map ping RISC Address Register Description lt 12 0 gt Centrality Communications Inc 101 AT460A BI Developer s Manual KS Centrality COMMUNICATIONS 008 1 f Reserved Ox005C 7 RGB to conversion control register 0x0084 LCD_SCN_FIELD Screen control for external TV encoder register 0x0088 LCD_OSDALPHA OSD and OSD2 Alpha blending control register 0 0004 ne 0 0000 LCD SCNFIFO SUPPRESS PON ne et LCD_SCNFIFO_SUPPRESS Centrality Communications Inc 102 AT460A BI Developer s Manual Centrality 0x0108 LCD SCN YSIZE Y Size for screen DMA 0x010C LCD SCN SKIP Skip value for screen DMA 0 0110 Reserved 0 0114 LCD_SCN_ADDR Current DMA Address for the Screen Display 0x0118 LCD_OSDBASE OSD Memory Base Register 0x011C LCD OSD XSIZE X Size for OSD DMA
463. trality 50 duty cycle 0 Not bypass the PLL 12 RW FOUT enable A 0 Enabled 3 R W Power down mode 0 Power up 3114 __ 80 e Power Manager PLL2 Configuration Register PWR PLL2 CONFIG 0x002C lt 7 0 gt and lt 4 0 gt determine the clock frequency by the following equation Four NF NR NO X Fin NOTE NF 2 F lt 7 0 gt NR R lt 3 0 gt NO please refer to the following table Meanwhile the following constraints must be followed e 2MHz lt Frer lt 8MHZ where Frer Fin NR when Fin is 12MHz NR has to be 2 6 e 200MHz lt Fyco lt 400MHZ where Fyco Fin NF NR For example if Fn 12 2 by default NR 2 NO 2 NF 64 so the PLL output will be 192MHz Bit Name Default Description 7 0 R W F lt 7 0 gt 8120 Feedback divider 1 255 Note F lt 7 0 gt cannot be 0 12 8 a pe 0 WE divider 1 31 p R lt 4 0 gt cannot be 0 13 0 gt 2510 Output divider R W 2 b00 Not Allowed 2 b01 NO 1 2 b10 2 2511 4 Note When is 2010 2911 FOUT would have around 50 duty cycle 15 LET 1 Bypass the PLL 0 Not bypass the PLL 16 R W FOUT enable 1 Disabled 0 Enabled 17 R W Power down mode 0 Power up 31 18 e Power Manager Clocks Enable Register PWR CLK 0x0030 User can enable disable the clock of majority logic in Atlas except the RISC Core Memo
464. tware compatibility Because there is no NINTR on the PCI bus setting this bit to 1791 would cause management interrupts not to occur This bit has to be set to1 b0 if any of the four management interrupts are to occur If this bit is1 b1 management interrupts would not occur even if they are individually enabled in the management interrupt register 5 R W CARD IS IO 1 b0 Sets memory card Interface mode card socket is configured to support memory only type cards All dual function socket interface signals are defined to perform memory only type interface functions Centrality Communications Inc 230 460 Developer s Manual Centrality 151 Sets I O Card Interface mode card socket is configured to support IO only This bit determines how the dual function socket interface will be used whether the PC card is configured as I O or Memory 6 R W CARD_RESET 1 bO 1 b0 The cdreset signal to the card socket is set high for normal low for ATAmode 1 b1 The cdreset signal to the card socket is set inactive low for normal high for ATA mode This bit will determine whether the cdreset signal to the card is active or not When the card enable bit is 1 bO the cdreset signal is high impedance 7 R W 1 bO Ring Indicator Enable 1 b0 bvd1 nstschg nri signal is status change function 1 b1 bvd1 nstschg nri signal is ring indicate input signal from card In I O card interface
465. ual Centrality e PWM Output Enable Register PWM OE 0x00 Bit Name Default Description Set 0 disenable PWMO output mo 0 Set 0 disenable PWM1 output PWM Output Enable b Set 1 enable 2 output Set 0 disenable PWM2 output 3 R W PWMS Output Enable 1 bO Set 1 enable PWMS output Set 0 disenable PWM3 output 304 1280 e PWM Wait State Register PWM_WAITO 1 2 3 0 04 OxC 0x14 0x1C Name Default Description 31 WS_COUNT 32 h0 Number of IO clock R W 0 1 clock 1 2clock PWM Hold Register PWM HOLDO 1 2 3 0x08 0x10 0x18 0x20 Bit Name Default Description 31 0 HD_COUNT 320 Number of IO clock R W 0 1 clock 1 2clock 8 11 GPS Baseband NN control 8 11 1 Overview Off Chip On Chip GPS Block E Baseband 2 bit data DSP or RISC sample clock clock Figure 75 Diagram of GPS Baseband Centrality Communications Inc 345 AT460A BI Developer s Manual Centrality The GPS baseband specific hardware with DSP RISC can process IF signal from GPS RF to get position fix e Complete L1 Band C A and NMEA 0183 compatibility e Wide Area Augmentation System WAAS support e to 32 parallel tracking channels and 1856 correlators Nemerix SiGe NEC and Mitel RF Front end compatible In fig 1 up
466. ugh base address 0 plus one Please refer to the section of Register Space for the PCMCIA Configuration Register Table 58 6730 Device Control Register Mapping Index Value Register Name Description Centrality Communications Inc 226 AT460A BI Developer s Manual Centrality Ox1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0 2 0 2 0 2 0 20 0 2 Ox2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3B 0 3 0 30 Ox3F 0x40 0x7F 0x80 M6730 Megacell Revision Register M6730 REV Index 0x00 Bit Name Default Description 3 0 R REVISION 4 h2 This field indicates the M6730 s compatibility with the M82365 54 120 Reserved 0 7 6 R INTERFACE ID 2 h2 These bits are used to identify the interface supported by this controller The M6730 supports both Memory and interfaces Centrality Communications Inc 227 AT460A BI Developer s Manual Centrality 2 b00 only 2001 Memory Only 2 b10 Memory and 2 b11 Reserve e M6730 Interface Status Register M6730 IF STATUS 0x01 Bit Default Description 1 0 R BATT_VOLT_DET 2 1 Battery Voltage Detect These bits give the status of the bvd2 and bvd1 inputs from the PC card 3 2 R CARD_DET Card Detect These bits give the status of the 2 and 4 _ In memory card interface this bit indicates th
467. using OS timer match register 5 no 3 Add SD card detected pin note in the pin description Replace all the register description of USP 1 9 5 2 2005 Weijie Zhu No field in ROM RAM Controller register to control write hold time in fact it shall be equal to one 2 0 7 14 2005 Jin xu Updated DC AC Electrical Characteristics The ARM core frequency is not be confirmed at last the 300MHz is the reference 8 3 2005 Modified some text error about DC AC eg Icd ac 8 18 2005 sheng GPIO2 CTRL19 register notes CLOCK DELAY bits change Pad mux default value change ROM timing change 8 20 2005 Qingyi sheng JTAG mode amp TEST mode change Change LCD module base address Change VDD PHA voltage to 3 3V 8 23 2005 Qingyi sheng Change engineering reserved parts Change CPU clock frequency Change PLL configuration table Centrality Communications Inc 974 460 Developer s Manual
468. utput frame contains the valid data 0 Indicates that the output frame is invalid After AC97 playback channel initialization the Frame valid bit should be set Otherwise AC97 CODEC will abandon all output frames from AC97 interface 14 R W Tag bit of 1 Inform the AC97 interface that output frame Slot 1 is Slot 1 enabled in next output frame 0 Indicates that output frame Slot 1 is disabled Before issuing read write command to AC97 CODEC user needs to program the command type and CODEC register index into the CODEC AC97 COMMAND register and then set the tag bit of slot 1 to inform the AC97 interface to issue the command to AC97 CODEC in next output frame After the command is sent to AC97 CODEC the bit will be cleared by hardware send the 97 DATA to AC97 CODEC through Slot 2 in next output frame After the command data is written to AC97 CODEC the tag bit will be cleared by hardware 12 R W Tag bit of 1 1 7 Indicates that output frame Slot 3 is enabled Slot 3 0 Indicates that output frame Slot is disabled For stereo and mono left mode the output frame Slot 3 and AC97 playback left channel must be enabled for mono right mode if output frame slot 3 is enabled the 1 bO 13 R W Tag bit of 1 bO 1 Inform the AC97 interface that output frame Slot 2 is Slot 2 enabled in the next output frame 0 Indicates that output frame Slot 2 is not enabled When issuing the write command to AC97 CODEC the
469. values of DLC 3 0 greater than eight are automatically interpreted as eight You should also note that although no data bytes are transmitted from the local host in the case of a remote frame transmission the data length of the remote frame should still be specified to avoid bus errors if two CAN controllers start a remote frame transmission with the same Identifier simultaneously Identifier ID The identifier acts as the message s name used in a receiver for acceptance filtering and also determines the bus access priority The lower the binary value of the identifier the higher the priority In Standard Frame Format SFF the identifier consists of 11 bits ID 28 to ID 18 In Extended Frame Format EFF messages the identifier consists of 29 bits ID 28 to ID 0 ID 28 is the most significant bit and is transmitted first on the bus Data Field The data field should comprise the number of data bytes defined by the data length code The most significant bit of data byte 1 at CAN address 19 SFF or CAN address 21 EFF is transmitted first CANBUS Receive Window Register CANBUSn RWIN 0x0040 0x0070 The Receive Buffer provides the window through which the CPU accesses the Receive FIFO Like the Transmit Buffer the Receive Buffer has a length of 13 bytes enough to accommodate one Receive message of up to eight data bytes Read only access to the Receive Buffer is provided in Operating Mode using RISC addresses 40x0 70 T
470. ved e Power Manager Configuration Register PWR CONFIG 0x0004 Bit Default Description 0 R W 1 bO 12 MHz oscillator power down enable 0 Do not turn off the oscillator during sleep mode reset condition 1 Turn off the 12 MHz oscillator during sleep mode 1 R W OSC FD 150 Force 12 MHz oscillator power down This bit is used to force the 12 MHz oscillator power down during normal operation mode Before enable this bit user needs to switch the clock source to the 32 KHz oscillator 2 R W OSC FO 150 Force 12 MHz oscillator on This bit is used to allow software to force the Atlas to use the 12 MHz oscillator instead of waiting for it to stabilize in the normal way 31 3 29 313 __ 29h0 Reserved e Power Manager Wake up Enable Register WAKEUP EN 0x0008 Bit Default Description 0 R W 1 b1 Sleep wake up enable by GPIO 0 Wake up by GPIO disabled 1 Wake up by GPIO enabled Reserved 30 16 WAIT lt 14 0 gt 15 h3ff GPIO wake up de bounce wait cycle number real time R W clock To ensure a success GPIO wake up the GPIO must perform a 2 stage de active gt active toggle Each stage should be longer than the period defined by this register 1 Note This bit can be and only be cleared on wake up or hardware reset Centrality Communications Inc 51 AT460A BI Developer s Manual Besides of the WE lt 15 0 gt
471. voltage inter model VDDPDN 1 2 1 28 1 36 V Input ic standard Vin 0 VDDIO VDDIO V Input voltage memory V 0 VDD_MEM V I O buffers SDR SDRAM Input voltage memory V 0 VDD_MEM V buffers DDR ddr VSSTL operating temperature range Top 20 70 1 These recommended and tested operating conditions Proper device operation outside these conditions is not guaranteed 9 3 3 DC Electrical Specifications Table 96 gives the DC Electrical characteristics for the Atlasll at recommended operating conditions Table 96 Electrical Specifications Characteristic Condition Symbol Min Max Unit Input high voltage Input type CMOS VIH 18 V Input high voltage VE CD MEM vH 20 V Input high voltage 2 VH 15 Input high voltage VH 20 V Input high voltage X XINW VIH 2 0 V Input low voltage Input type CMOS VIL 1 1 V Input low voltage VoU VIL 08 V Input low voltage VIL 08 V Input low voltage VIL E et ay Input low voltage X_XIN X_XINW VIL 0 8 V Centrality Communications Inc 359 460 Developer s Manual Centrality Input leakage Vin 0 or VDD IO lin 107 Vin 0 40 110 uA up resistor Input current Pull down resistor Vin VDD IO 40 110 uA IOH is driver dependent
472. ween X start and X end then the pixel is valid These values are defined using the registers CAM START and CAM END Another thing the user can set is an interrupt line The Video Input Port will then generate an interrupt whenever it reaches that line Usually this interrupt line is defined before or after the active region and can be used to as a frame interrupt for video applications or do some setup before or after an image capture The interrupt line is set using the CAM YINT register Of course the interrupt must be enabled in the INT RISC MASK register and the interrupt is edge triggered Centrality Communications Inc 275 AT460A BI Developer s Manual Centrality HSYNC m VSYNC X start Y start Active Region VSYNC Period X end Y end YINT 4 Period Figure 62 Active Region NOTE The maximum frequency of pixel clock we can support is the half of IOCLK 8 5 3 Video Input Port Registers Table 72 Video Input Port Register Mapping RISC DSP Register Description Address Address lt 11 0 gt lt 7 0 gt 0 000 0 00 0 01 Reserved _____ 0 004 0 02 0 03 ___ _____ ______ Reserved register register register register Centrality Communications Inc 276 AT460A BI Developer s Manual Centrality register 0 20 0 21 0 050 0 28 0 29 FIFO_LEVEL_CHE FIFO level check register CK FIFO operation re
473. wing 1 Commands using only CMD line ex CMD52 2 Commands with no data transfer but using busy signal on DAT lt 0 gt line R1b or R5b ex CMD38 3 Resume Command 0 No Data Present 1 Data Present 23 22 CMD_TYPE 270 There are three types of special commands R W Suspend Resume and Abort These bits shall bet set to 00b for all other commands Suspend Command If the Suspend command succeeds the HC shall assume the SD Bus has been released and that it is possible to issue the next command that uses the DAT line The HC shall de assert Read Wait for read transactions and stop checking busy for write transactions The Interrupt cycle shall start in 4 bit mode If the Suspend command fails the HC shall maintain its current state And the HD shall restart the transfer by setting Continue Request in the Block Gap Centrality Communications Inc 166 AT460A BI Developer s Manual Centrality Control Register Resume Command The HD re starts the data transfer by restoring the registers in the range of 000 00Dh HC shall check for busy before starting write transfers Abort Command If this command is set when executing a read transfer the HC shall stop reads to the buffer If this command is set when executing a write transfer the HC shall stop driving the DAT line After issuing the Abort command the HD should issue a software reset 00b Normal 01b Suspend 10b Resume 11b Abort
474. with INT_EN 0 then set the GPIO as input Set the INT_TYPE to level or edge Then set the INT_HT INT_LT for high low level or rising falling edge interrupt Clear the GPIO interrupt status register before enabling the GPIO interrupt 5 9 PWM 5 9 14 Overview PWM Pulse Wide Modulate generator is actually part of the GPIO logic It can generate 4 independent outputs Each output duty cycle can be adjusted by setting the corresponding wait and hold registers The PWM output pins are multiplexed with the GPIO lt 7 4 gt Please refer to the PWM_OE register to find how to enable the PWM outputs Centrality Communications Inc 92 AT460A BI Developer s Manual Centrality 5 9 15 PWM Registers Table 26 PWM Interface Register Mapping RISC Address Register Description lt 11 0 gt 0x00 PWM output enable PWM_WAITO PWM output 0 wait state for high pulse PWM_HOLDO PWM output 0 hold state for low pulse PWM_WAIT1 PWM output 1 wait state for high pulse PWM_HOLD1 PWM output 1 hold state for low pulse PWM_WAIT2 PWM output 2 wait state for high pulse PWM_HOLD2 PWM output 2 hold state for low pulse PWM_WAIT3 PWM output 3 wait state for high pulse PWM_HOLD3 PWM output 3 hold state for low pulse e PWM Output Enable Register PWM_OE 0x00 Bit Name Default Description Set 0 disenable PWMO output Set 0 disenable PWM1 output Set 0 disenable PWM2 output Set 0 disenable PWM3 output
475. wo PC Socket B VS1 Input card sockets These bits are used to determine 3 R Socket B VS2 Input the operating voltage of the PC cards inserted 7 4 RW daho Reserved e M6730 Misc Control 3 Register M6730 MISC 3 Extension Index 0x25 During the power on reset or hardware reset the bits 1 and 0 are loaded with the values of the signals misc1 in miscO in respectively Default Description 1 0 emm 2 bxx System Interrupt Signalling Mode 2 b00 Reserved 2 b01 External hardware Interrupt Signalling mode 2 b10 Reserved 2 b11 PCI Interrupt Signalling Mode The M6730 supports four interrupt signalling modes The configuration of each of the modes given earlier 3 2 R W Currently reserved These bits are to be used for future expansion These bits can be used for Socket Power Control Signalling Modes With the help of external power control chips it is possible to have different power control modes TA RW HO Reserved 0 M6730 Extend Data Register M6730 EXT DATA Index Ox2F Bit Name Default Description 7 0 R W EXT_DATA 880 The data in this register allows the registers indicated by the Extended Index register to be read and written The value of this register is the value of the register selected by the Extended Index register e M6730 Setup Timing 0 1 Register M6730_SETUP_TIMING_0 1 Index 0x3D 1 All timing registers take effect immediately and
476. x000C To generate a 1 Hz divided real time clock it needs to divide the clock input from the external real time crystal CLK 32 768 KHz RTC DIV RTC CLK 2 1 To generate real time clock in frequency other than 1Hz for example X Hz then it needs to setup the register as the following DIV RTC CLK X 2 1 Bit Default Description 15 0 DIV lt 15 0 gt 1610 Division value R W 3116 160 5 3 Power Manager 5 3 9 Overview Just as Atlas II has multiple power management modes such as Normal mode Idle Mode and Sleep mode Please refer to the Datasheet for the description of these modes Besides of that Atlas II has two new power down modes Standby mode and Deep Sleep mode Centrality Communications Inc 48 460 Developer s Manual LS Centrality COMMUNICATIONS e In Deep Sleep mode the major part of the silicon will be powered off except the Real Time Clock Power Manager Reset Controller Resource Sharing Controller and GPIO all clocks are stopped except the RTC Atlas II has multiple power domains as following e power domains SSTL IO power domain 1 8 2 5 3 3V General IO power domain 2 5 3 3V e Core power domains Power down domain 1 2V Non powerdown domain 1 2V e PLL power domains 1 2 or 3 3V Please refer to the PLL in previous sections 5 3 10 Power On Off Sequence When
477. xel type 0 15 8 R W GREEN 8hO Green value for the OSD pixel type 0 23 16 80 Red value for the OSD pixel type 0 Centrality Communications Inc 122 AT460A BI Developer s Manual Centrality RW 26 24 MIX RATIO 35000 Mixing value for the OSD pixel type 0 R W 000 100 screen value 001 34 screen value OSD value 010 72 screen value OSD value 011 screen value OSD value 100 100 OSD value Note For 12 bit and 16 bit bypass mode only 10096 screen and 10096 OSD are allowed 31 27 50 jReseved e OSD Palette Entry 1 LCD OSDPAL1 0xA8 Bit Default Description 7 0 BLUE Blue value for the OSD pixel type 1 15 8 R W GREEN 80 Green value for the OSD pixel type 1 23 16 880 Red value for the OSD pixel type 1 R W 26 24 MIX RATIO 3 b000 Mixing value for the OSD pixel type 1 RW 000 100 screen value 001 screen value OSD value 010 72 screen value OSD value 011 screen value OSD value 100 100 OSD value Note For 12 bit and 16 bit bypass mode only 100 screen and 100 OSD are allowed 31 27 50 Reserved OSD Palette Entry 2 LCD OSDPAL2 0xAC Bit Name Default Description 7 0 R W BLUE Blue value for the OSD pixel type 2 15 8 R W GREEN 810 Green value for the OSD pixel type 2 23 16 Red value for the OSD pixel type 2 MIX_RATIO R W 26 24 372000
478. ximum Current for 3 0V 23 16 R MAX CUR 18V Maximum Current for 1 8V 3124 R Reserved Table 48 Maximum Current Value Definition Register Value Current Value 0 Gt Information another method eg CE e SD Bus Clock Delay Register SD DELAY 0x004C Default Description Bit 5 0 CLK_DELAY 6 hO The register is used to adjust to the bus clock R W delay Ww R e 5010 5101 Interrupt Status and Version Register SD SLOT INT VER 0 00 7 0 R INT SIG FOR 810 These status bit indicate the logical OR of Interrupt SLOT signal and Wakeup signal for each slot A maximum of 8 slots can be defined If one interrupt signal is associated with multiple slots The HD can know which interrupt is generated by reading these status bits By a power on reset or by SOFT RST ALL the Interrupt signal shall be disserted and this status shall read 00 Bit 00 Slot 1 Bit 01 Slot 2 Bit 02 Slot 3 Bit 07 Slot 8 158 Reswed Bit Default Description 00 SD Host Specification version 1 0 Others Reserved 23 16 SPEC_VER 8 hO This Status indicates the Host Controller Spec R W Version The Upper and Lower 4 bits indicate the version Centrality Communications Inc 185 460 Developer s Manual Centrality 31 24 VENDOR VER 880 This status is reserved for the vendor version number R W T
479. y 0x56 0x57 Bit Name Default Description 3 0 R W FIFO 5 lt 3 0 gt Stop check in DWORD 9 4 gt ________ 6 __ Reserved 19 14 fs HO Reserved 7 3124 80 __ UART RX FIFO Operation Register UART RISC 0x130 DSP 0x58 This register is different from FIFO of other peripheral operation register and reset bit is at bit 0 Bit Name Default Description 0 R W RESET 1 bO Set to 1 to stop the FIFO and reset the FIFO internal status including the relevant interrupt status Set to 0 in normal operation FIFO START Start the read write transfer when this bit is declared 3010 e UART RX FIFO Status Register UART FIFO STATUS RISC 0x134 DSP 0x5A Name Default Description 5 0 FIFO LEVEL 6710 The byte number of the valid data in the FIFO In case FIFO is full the value of this register is O thus user must concatenate FIFO FULL bit with this value to determine the actual data count in the FIFO 6 R FIFO FULL FIFO full status the FIFO is full when read out as 1 This bit is concatenated with FIFO LEVEL to be the actual FIFO data count 7 R FIFO EMPTY 150 FIFO empty status Equivalent to FIFO FULL FIFO LEVEL Reserved 318 240 __ e UART RX FIFO Data Register UART RX FIFO DATA RISC 0x138 DSP 0x5C Bit Default Description 31 0 R FIFO_DATA 320 T
480. y time on the PCI side When PCI access is terminated with retry the System to PCI Bridge will wait for SYS2PCI_LRETRY before it retry the same PCI access PCI Bridge Interrupt Enable Register SYS2PCI INT EN 0x0004 Bit Name Default Description 0 R W Need to be written with 0 Centrality Communications Inc 150 AT460A BI Developer s Manual pim Centrality System to PCI Bridge Master abort interrupt enable 1 enable the interrupt 0 disable the interrupt 2 R W TIMOUT 1 bO System to PCI Bridge Time out interrupt enable 1 enable the interrupt 0 disable the interrupt 313 Reserved 2 System to PCI Bridge Master abort interrupt enable When there is master abort on PCI bus the current access will be cancelled A master abort interrupt will be generated ui System to PCI Bridge Time out interrupt enable When an access on PCI bus is terminated with retry X gt VALUE times the current access will be cancelled A time out abort interrupt will be generated e PCI Bridge Interrupt Statue Register SYS2PCI INT STATUS 0x0008 Bit Name eraut Description IO RW Reserved Need to be written with 0 1 R W MABT 1 bO System to Bridge Master abort interrupt Read 1 interrupt pending 0 no interrupt pending Write 1 clear the interrupt pending 0 no effect TIMOUT System to PCI Bridge Time out interrupt Read 1 interrupt pending 0 no interrupt pend

Atlas™-II AT460A-BI Application Processor

Contents

Download Pdf Manuals

Related Search

Related Contents

Atlas&trade;-II AT460A-BI Application Processor

Contents

Download Pdf Manuals

Related Search

Related Contents

Atlas™-II AT460A-BI Application Processor