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DE0-Nano-SoC User Manual 1 www.terasic.com April 2, 2015

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1. 28 3 7 Peripherals Connected to Hard Processor System HPsS 3l 3 1 UssrPush buttons and LEES kno vo 3l Det S ERE 3l UAR H H 33 ou DDOR 34 DEO Nano SoC 1 www terasic com Tijasic User Manual April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM J u u uu 36 UP O 37 a u 38 ERR 38 CHAPTER4 DEO NANO SOC SYSTEM BU LDER 40 Introd HO u eis RE IUE 40 J Do LI ns 40 4 3 Using DE0 Nano SoC System Bulilder 41 CHAPTERS EXAMPEES FOR FF GPL 47 5 1 DE0 Nano SoC Factory Configuration 47 2 2 ADCR 48 CHAPIER6 EAAMFLES SOC ais choc ulus 51 LT Ti E MINE 51 Usern LED and KPY uuu u u u uuu u T u 53 uuu u uuu uuu uuu u EM 59 CHAPTER7 EXAMPLES FOR USING BOTH HPS SOC
2. 63 J Control FPGA LED a ____ _ __ __ __ 63 8 PROGRAMMING THE EPCS 67 8 1 Before Programming _4__ __ ___ 67 68 6 3 Write JIC File into the EPCS Device 2 0000 1 12 73 9 2 Nios Boot from EPCS Device in Quartus 141 75 CHAPTER9 JAPPENDIX 76 LOA SION 9800000090 000 009000 76 DEO Nano SoC 2 www terasic com Tijasic User Manual April 2 2015 www terasic com UNIVERSITY PROGRAM TIT enr 76 asic DEO Nano SoC 3 WWW terasic com User Manual April 2 2015 Chapter 1 DEO Nano SoC Development kit The DEO Nano SoC Development Kit presents a robust hardware design platform built around the Altera System on Chip SoC FPGA which combines the latest dual core Cortex A9 embedded cores with industry leading programmable logic for ultimate design flexibility Users can now leverage the power of tremendous re configurability paired with a high performance low power processor system Altera s SoC integrates an ARM based hard processor system HPS consisting of processor peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high bandwidth interconnect backbone The DEO N
3. lt gt ADC Controller convener 2x5 Header Figure 5 2 Block diagram of ADC reading Figure 5 3 depicts the pin arrangement of the 2x5 header This header is the input source of ADC convertor in this demonstration Users can connect a trimmer to the specified ADC channel ADC_INO ADC_IN7 that provides voltage to the ADC convert The FPGA will read the associated register in the convertor via serial interface and translates it to voltage value to be displayed on the Nios II console VCC5 ADC IN1 ADC IN3 ADC IN5 ADC IN7 ADC INO IN2 1 4 IN6 GND Figure 5 3 Pin distribution of the 2x5 Header for the ADC DEO Nano SoC 1 24 51 User Manual www terasic com 49 www April 2 2015 B System Requirements The following items are required for this demonstration e DEO Nano SoC board x1 e Trimmer Potentiometer x1 e Wire Strip x3 B Demonstration File Locations e Hardware project directory DEO NANO SOC ADC e Bitstream used DEO NANO SOC ADC sof e Software project directory DEO SOC software e Demo batch file DEO SOC Memo batchh DEO NANO SOC ADC bat B Demonstration Setup and Instructions Connect the trimmer to corresponding ADC channel on the 2x5 header as shown in Figure 5 4 as well as the 5V and GND signals The setup shown above is connected to ADC channel 0 Execute the demo b
4. 5 I2C1 SDAT MOSI SDA HPS SPIM CLK HPS I2C1 SCLK HPS LTC GPIO TS3A5018 Figure 3 26 Connections between the HPS and LTC connector Table 3 21 Pin Assignment of LTC Connector FPGA Pin No VO Standard P HPS LTC GPIO HPS LTC GPIO HPS I2C1 SCLK PIN B21 HPSI2C1 Clock HPS I2C1 SDAT HPS I2C1 Data 33V nal Name HPS SPIM CLK HPS SPIM MISO PIN B19 SPI Master Input Slave Output HPS SPIM MOSI PIN B16 SPI Master Output Slave Input 19 SPI Clock 3V DEO Nano SoC 39 www terasic com Tijasic User Manual April 2 2015 www terasic com Chapter 4 DEO Nano SoC System Builder This chapter describes how users can create a custom design project with the tool named DEO Nano SoC System Builder 4 1 Introduction The DEO Nano SoC System Builder is a Windows based utility It is designed to help users create a Quartus II project for DEO Nano SoC within minutes The generated Quartus II project files include e Quartus II project file qpf e Quartus II setting file qsf e Top level design file v e Synopsis design constraints file sdc e Pin assignment document htm The above files generated by the DEO Nano SoC System Builder can also prevent occurrence of situations that are prone to compilation error when users manually edit the top level design file or place pin assignment The common mistakes that users encounter are
5. 2 USB Blaster CLK UB2 24 24MHz Gigabit Ethernet CLK_ENET_25 25MHz nm CLK USB 24 24MHz X USB OTG PHY Figure 3 13 Block diagram of the clock distribution on DEO Nano SoC Table 3 5 Pin Assignment of Clock Inputs FPGA CLKi 50 PIN_V11 50MHzclockinput FPGA CLK2 50 PIN 50MHzclockinput FPGA CLK3 50 PIN 50 MHz clock input share with FPGA CLK1 50 3 HPS 25 PIN E20 25MHzclockinput HPS CLK2 25 D20 25MHzclockinu 3 6 Peripherals Connected to the FPGA This section describes the interfaces connected to the FPGA Users can control or monitor different interfaces with user logic from the FPGA asIC DEO Nano SoC 21 WWW terasic com lt User Manual April 2s 2015 3 6 1 User Push buttons Switches LEDs The board has two push buttons connected to the FPGA as shown in Figure 3 14 Connections between the push buttons and the Cyclone V SoC FPGA Schmitt trigger circuit is implemented and act as switch debounce in Figure 3 15 for the push buttons connected The two push buttons named KEYO and coming out of the Schmitt trigger device are connected directly to the Cyclone V SoC FPGA The push button generates a low logic level or high logic level when it is pressed or not respectively Since the push buttons are debounced they can be used as clock or reset inputs in a Circuit VCC3P3 KEYO
6. A 2 4 w E E M M jo F I gt 2 Eno c 20 EDI 6 Re 42992226 s T Re LA f OY LAL r w Y gt x d E zt 0 BP TENET EPCS128 y P MicroSD Card Socket Figure 2 2 DE0 Nano SoC development board bottom view The DE0 Nano SoC board has many features that allow users to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware is provided on the board B FPGA Altera Cyclone SE 5CSEMA4U23C6N device Serial configuration device EPCS 128 USB Blaster II onboard for programming JTAG Mode 2 push buttons 4 slide switches 6 green user LEDs Three 50MHz clock sources from the clock generator Two 40 pin expansion header One Arduino expansion header Uno R3 compatibility can connect with Arduino shields One 10 pin Analog input expansion header shared with Arduino Analog input asic DEO Nano SoC 4 www terasic com User Manual April 2s 2015 JAN DTE RYA U P NIVERSITY ROGRAM A D converter 4 wire SPI interface with FPGA Hard Processor System 800MHz Dual core ARM Cortex A9 processor IGB DDR3 SDRAM 32 bit data bus 1 Gigabit Ethernet PHY with RJ45 connector port USB OTG USB Micro AB connector Micro SD card socket Accelerometer I2C i
7. al Save File SOCVHPS pu Down Figure 3 8 Program sof file into the FPGA device B Configure the FPGA in AS Mode The DEO Nano SoC board uses a serial configuration device EPCS 128 to store configuration data for the Cyclone V SoC FPGA This configuration data 15 automatically loaded from the serial configuration device chip into the FPGA when the board is powered up Users need to use Serial Flash Loader SFL to program the serial configuration device via JTAG interface The FPGA based SFL is a soft intellectual property IP core within the FPGA that bridge the JTAG and Flash interfaces The SFL Megafunction is available in Quartus II Figure 3 9 shows the programming method when adopting SFL solution Please refer to Chapter 8 Steps of Programming the Serial Configuration Device for the basic programming instruction on the serial configuration device DEO Nano SoC 17 www terasic com asic User Manual April 2 2015 www terasic com Quartus SFL Image Programmer USB Blaster to Bridge Circuit The JTAG and ASMI AS x1 Figure 3 9 Programming a serial configuration device with SFL solution 3 3 Board Status Elements In addition to the 9 LEDs that FPGA HPS device can control there are 6 indicators which can indicate the board status See Figure 3 10 please refer the details in Table 3 3 UART TXD RXD JTAG TX RX CONF_DONE 3 3V Power ud Figure 3 10 LED Indicators o
8. DE0 Nano S0 USER MANUAL Lu A It n Zl n p B 1 ELI er 2111 UNIVERSITY www terasic com PROGRAM Copyright 2003 2015 Terasic Inc All Rights Reserved CONTENTS DECEM CHAPTER1 DEO NANO SOC DEVELOPMENT 4 I E RETE 4 1 2 DEO Nano s56C System Cc 5 J i ID 5 CHAPTER2 NTRODUCTION OF THE DE0 NANO SOC BOAR0X 6 2 T Layout and BMC ROT 6 2 2 Block Diagram of the DE0 Nano SoC Boatd CHAPTER3 USING THE DEO NANO SOC BOARD 11 3 1 Settings of FPGA Configuration 11 3 2 Configuration of Cyclone V SoC FPGA on DE0 Nano SoC 12 5205 uuu u a 18 14 Board Reset uuu 19 Seule d rici TU T I Tm 20 3 0 Peripherals Connected to the ea Es bela ipu 21 3 6 User Push buttons Switches and LEDS 27 202 2x20 GPIO Expansion Head Gr uuu uuu aie 25 3 6 3 Arduino Uno Expansion 27 3 6 4 A D Converter and Analog Input
9. User Manual April 2 2015 PIN_W15 PIN_AA24 PIN V16 JA DTE RYAN pm vis y PIN AF26 26 16 23 Figure 3 17 Connections between the LEDs and the Cyclone V SoC FPGA LEDO LED1 LED2 LED3 LED4 LED5 LED6 LED LEDO LED1 LED2 LED3 LED4 LEDS LED6 LED Table 3 6 Pin Assignment of Slide Switches Standard 3 3V 3 3V 3 3V 3 3V I O Standard 3 3V 3 3V I O Standard 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V Signal Name FPGA Pin No Description SW 0 PIN_L10 Slide Switch 0 SW 1 PIN_L9 Slide Switch 1 SW 2 PIN_H6 Slide Switch 2 SW 3 PIN_H5 Slide Switch 3 Table 3 7 Pin Assignment of Push buttons Signal Name FPGA Pin No Description KEY 0 PIN_AH17 Push button 0 KEY 1 PIN AH16 Push button 1 Table 3 8 Pin Assignment of LEDs Signal Name FPGA Pin No Description LED 0 PIN W15 LED 0 LED 1 PIN AA24 LED 1 LED 2 PIN V16 LED 2 LED 3 PIN V15 LED 3 LED 4 PIN AF26 LED 4 LED 5 PIN AE26 LED 5 LED 6 PIN Y16 LED 6 LED 7 PIN AA23 LED 7 DEO Nano SoC 24 asic User Manual www terasic com 3 3V www terasic com April 2 2015 3 6 2 2x20 GPIO Expansion Headers The board has two 40 pin expansion headers Each header has 36 user pins connected directly to the Cyclone SoC FPGA It also comes with DC 5 V VCC5 DC 3 3V VCC3P3 and two GND pins The maximum power consumption allowed for a daughter card
10. Conversion setup files Output programming file Programming file type Indirect Configuration File jic File name output_file jic Remote Local update difference file NONE Create Memory Map File Generate output file map Create CvP files Generate output file periph jic and output file core rbf Create config data Generate output file auto rpd Start Address Figure 8 3 Dialog of Convert Programming Files 7 Click Add File 5 Select the sof to be converted to a J1c file from the Open File dialog 9 Click Open 10 Click on the Flash Loader and click Add Device as shown in Figure 8 4 11 Click OK and the Select Devices page will appear DEO Nano SoC 69 www terasic com Tijasic User Manual April 2 2015 www terasic com IAN DTE RYN UNIVERSITY PROGRAM Ta Convert Programming File D SVN DEO nano DEO0 SOC Default DEO SOC Default DEO 5 2 w Search altera com a Output programming file Programming file type Options Configuration device vode output file jic m name Remote Local update difference file NONE Create Memory File Generate output File Create CvP files Generate output file periph jic and output file core rbf 7 Create config data RPO Generate output file auto rpd File Data area Flash Loader SOF Data Page DEO SOC Default sof B5CSEMA3U23 Remove up
11. DEO Nano SoC 71 www terasic com Tijasic User Manual April 2 2015 www terasic com 8 3 Write JIC File into the EPCS Device When the conversion of SOF to JIC file is complete please follow the steps below to program the EPCS device with the jic file created Quartus II Programmer 1 Set MSEL 4 0 10010 2 Choose Programmer from the Tools menu and the Chain cdf window will appear 3 Click Auto Detect and then select the correct device SCSEMA4 Both FPGA device and HPS should be detected as shown in Figure 8 7 4 Double click the red rectangle region shown in Figure 8 7 and the Select New Programming File page will appear Select the jic file to be programmed 5 Program the EPCS device by clicking the corresponding Program Configure box A factory default SFL image will be loaded as shown in Figure 8 8 6 Click Start to program the EPCS device p Programmer D SVN DEO nano DEO SOC Default DEO SOC Default DEO SOC Default 2 s File Edit View Processing Tools Window Hep Search altera com DE SoC vode j Enable real time ISP to allow background programming when available Checksum Usercode Program Verify Blank ipu Start Configure Check 00000000 lt none gt 00000000 lt none gt wit Stop x amp Delete Change File
12. alt clrbits word set specified bit value to zero for a specified register The program must include the following header files to use the above API to access the registers of GPIO controller include lt stdio h gt include lt unistd h gt include lt fcntl h gt DEO Nano SoC 56 Tijasic User Manual www terasic com www April 2 2015 include lt sys mman h gt include hwlib h include socal socal h include socal hps h include socal alt_gpio h B LED and KEY Control Figure 6 4 shows the HPS users LED and KEY pin assignment for the DEO NANO SoC board The LED is connected to HPS_GPIO53 and the KEY is connected to HPS_GPIO54 They controlled by the GPIOI controller which also controls HPS_GPIO29 5 7 A20 HPS_LED HPS_GPIO53 HPS 54 PPS Figure 6 4 Pin assignment of LED and KEY Figure 6 5 shows the gpio swporta ddr register of the GPIOI controller The bit O controls the pin direction of HPS_GPIO29 The bit 24 controls the pin direction of HPS_GPIO53 which connects to 5 LED the bit 25 controls the pin direction of HPS_GPIO54 which connects to HPS KEY and so on The pin direction of 5 LED and 5 KEY are controlled by bit 24 and bit 25 in the gpio swporta ddr register of the GPIOI controller respectively Similarly the output status of 5 LED 15 controlled by the bit 24 in the gpio swporta dr register of
13. 22 DEO Nano SoC User Manual GPIO Connection 0 28 GPIO Connection 0 29 GPIO Connection 0 30 GPIO Connection 0 31 GPIO Connection 0 32 GPIO Connection 0 33 GPIO Connection 0 34 GPIO Connection 0 35 GPIO Connection 1 0 GPIO Connection 1 1 GPIO Connection 1 2 GPIO Connection 1 3 GPIO Connection 1 4 GPIO Connection 1 5 GPIO Connection 1 6 GPIO Connection 1 7 GPIO Connection 1 8 GPIO Connection 1 9 GPIO Connection 1 10 GPIO Connection 1 11 GPIO Connection 1 12 GPIO Connection 1 13 GPIO Connection 1 14 GPIO Connection 1 15 GPIO Connection 1 16 GPIO Connection 1 17 GPIO Connection 1 18 GPIO Connection 1 19 GPIO Connection 1 20 GPIO Connection 1 21 GPIO Connection 1 22 GPIO Connection 1 23 GPIO Connection 1 24 GPIO Connection 1 25 GPIO Connection 1 26 GPIO Connection 1 27 GPIO Connection 1 28 GPIO Connection 1 29 GPIO Connection 1 30 GPIO Connection 1 31 GPIO Connection 1 32 GPIO Connection 1 33 GPIO Connection 1 34 GPIO Connection 1 35 26 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V WWw terasic com April 2 2015 UNIVERSITY PROGRAM 3 6 3 Arduino Uno R3 Expansion Header The board provides Arduino Uno revision 3 compatibility expansion header which
14. AH16 Figure 3 14 Connections between the push buttons and the Cyclone V SoC FPGA hbutton depressed pou released Before Debouncing Schmitt Trigger Debounced gt Figure 3 15 Switch debouncing There are four slide switches connected to the FPGA as shown in Figure 3 16 These switches are DEO Nano SoC 22 www terasic com Tijasic User Manual April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM not debounced and to be used as level sensitive data inputs to a circuit Each switch is connected directly and individually to the FPGA When the switch is set to the DOWN position towards the edge of the board it generates a low logic level to the FPGA When the switch is set to the UP position a high logic level is generated to the FPGA JA DTE RYN Cyclone V La SW3 SW2 SW1 SW0 Logic 0 fhs Logic 1 Figure 3 16 Connections between the slide switches and the Cyclone V SoC FPGA There are also eight user controllable LEDs connected to the FPGA Each LED 15 driven directly and individually by the Cyclone V SoC FPGA driving its associated pin to a high logic level or low level to turn the LED on or off respectively Figure 3 17 shows the connections between LEDs and Cyclone V SoC FPGA Table 3 6 Table 3 7 and Table 3 8 list the pin assignment of user push buttons switches and LEDs asic DEO Nano SoC 23 WWW terasic com
15. 3 14 Pin Assignment of Gigabit Ethernet PHY Signal Name FPGA No Description Standard HPS ENET TX EN PIN A12 GMII and MII transmit enable 3 3V HPS TX DATA 0 PIN A16 MII transmit data 0 3 3V HPS TX DATA 1 PIN J14 MII transmit data 1 3 3V HPS TX DATA 2 PIN A15 MII transmit data 2 3 3V HPS ENET TX DATA 3 PIN D17 MII transmit data 3 3 3V HPS ENET RX DV PIN J13 GMII and MII receive data valid 3 3V HPS RX DATA O PIN A14 GMII and MII receive data 0 3 3V HPS ENET RX DATA 1 PIN A11 GMII and MII receive data 1 3 3V HPS ENET RX DATA 2 PIN C15 GMII and MII receive data 2 3 3V HPS DATA 3 PIN A9 GMII and MII receive data 3 3 3V HPS ENET RX CLK PIN J12 GMII and MII receive clock 3 3V HPS ENET RESET N PIN B14 Hardware Reset Signal 3 3V HPS ENET MDIO PIN E16 Management Data 3 3V HPS ENET MDC PIN A13 Management Data Clock Reference 3 3V HPS ENET INT PIN B14 Interrupt Open Drain Output 3 3V HPS GTX PIN 415 GMII Transmit Clock 3 3V There are two LEDs green LED LEDG and yellow LED LEDY which represent the status of Ethernet PHY KSZ9031RN The LED control signals are connected to the LEDs on the RJ45 connector The state and definition of LEDG and LEDY are listed in Table 3 15 For instance the connection from board to Gigabit Ethernet 1s established once the LEDG lights on DEO Nano SoC 32 User Manual www April 2 2015 www terasic c
16. 4 6 DEO Nano SoC 45 www terasic com User Manual April 2 2015 UNIVERSITY PROGRAM DEO Nano SoC V1 0 0 System Configuration L om Project Name DEO NANO SOC DEO Nano SoC FPGA Board CLOCK 8 Button x 2 Switch x 4 ADC 2x5 Header Arduino Header HPS GPIO 0 Header None Prefix Name GPIO 1 Header Swe seting Generate Prefix Name Figure 4 6 Project Settings B Project Generation When users press the Generate button the DEO Nano SoC System Builder will generate the corresponding Quartus II files and documents as listed in Table 4 1 Table 4 1 Files generated by the DEO Nano SoC System Builder Top level Verilog HDL file for Quartus T Project name gt qpf Quartus Project File ui Project name gt qsf Quartus Setting File Project name gt sdc Synopsis Design Constraints file for Quartus Il lt Project name gt htm Pin Assignment Document Users can add custom logic into the project in Quartus H and compile the project to generate the SRAM Object File sof DEO Nano SoC 46 www terasic com Tijasic User Manual April 2 2015 www terasic com Chapter 5 Examples FPGA This chapter provides examples of advanced designs implemented by RTL or Qsys on the DEO Nano SoC board These reference designs cover the features of peripherals connected to the FPGA such as A D C
17. 4 DDR3 Memory Standard 3 3V 3 3V 3 3V The DDR3 devices connected to the HPS are the exact same model as the ones connected to the FPGA The capacity is 1GB and the data bandwidth is in 32 bit comprised of two x16 devices with a single address command bus The signals are connected to the dedicated Hard Memory Controller for HPS I O banks and the target speed 15 400 MHz Table 3 17 lists the pin assignment of DDR3 and its description with I O standard Signal Name HPS DDR3 A 0 HPS DDR3 A 1 HPS DDR3 A 2 HPS DDR3 A 3 HPS DDR3 A 4 HPS DDR3 A 5 HPS DDR3 A 6 HPS DDR3 A T7 HPS DDR3_A 8 HPS DDR3 A 9 HPS DDR3 A 10 HPS DDR3 11 HPS DDR3 A 12 HPS DDR3 A 13 HPS DDR3 A 14 HPS DDR3 0 HPS DDR3 BA 1 HPS DDR3 BA 2 HPS DDR3 CAS n HPS DDR3 CKE HPS DDR3 CK n HPS DDR3 CK p HPS DDR3 CS n HPS DDR3 DM O0 HPS DDR3 DM i HPS DDR3 DM 2 www terasic com Table 3 17 Pin Assignment of DDR3 Memory FPGA Pin No PIN C28 PIN B28 PIN E26 PIN D26 PIN J21 PIN J20 PIN C26 PIN B26 PIN F26 PIN F25 PIN A24 PIN B24 PIN D24 PIN C24 PIN G23 PIN A27 PIN H25 PIN G25 PIN A26 PIN L28 PIN N20 PIN N21 PIN L21 PIN G28 PIN P28 PIN W28 DEO Nano SoC User Manual Description HPS DDR3 Address 0 HPS DDR3 Address 1 HPS DDR3 Address 2 HPS DDR3 Address 3 HPS DDR3 Address 4 HPS DDR3 Address 5 HPS DDR3 Address 6 HPS DDR3 Address 7 HPS DDR3 Address 8 HPS DDR3 Address 9 HPS DDR3 Address 1
18. 47 www terasic com Tijasic User Manual April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM EPCS by executing the test bat file shown in Figure 5 1 If users want to program a new design into the EPCS device the easiest method is to copy the new sof file into the demo_batch folder and execute the test bat Option 2 will convert the sof to and option 3 will program Jic file into the EPCS device C Windows system32 cmd exe Makesure MSEL 4 61 is set to choose your operation programming sof to FPGA converting sof to jic programming to EPCS erasing From EPCS PERERA EHHH H AE K DE RD X SK Please enter your choise 1 2 3 4 Figure 5 1 Command line of the batch file to program the FPGA and EPCS device 5 2 ADC Reading This demonstration illustrates steps to evaluate the performance of the 8 channel 12 bit A D Converter LTC2308 The DC 5 0V on the 2x5 header is used to drive the analog signals by a trimmer potentiometer The voltage can be adjusted within the range between 0 and 4 096V The 12 bit voltage measurement is displayed on the NIOS II console Figure 5 2 shows the block diagram of this demonstration If the input voltage 1s 2 0V 2 0V a pre scale circuit can be used to adjust it to 0 4V DEO Nano SoC 48 www terasic com Tijasic User Manual April 2 2015 www terasic com Old qe 1 9 1910
19. App Memory Mapped Driver PIO b Controller LED Figure 7 1 FPGA LED are controlled by HPS B LED Control Software Design The Lightweight HPS to FPGA Bridge is a peripheral of HPS The software running on Linux cannot access the physical address of the HPS peripheral The physical address must be mapped to the user space before the peripheral can be accessed Alternatively a customized device driver module can be added to the kernel The entire CSR span of HPS is mapped to access various registers within that span The mapping function and the macro defined below can be reused if any other peripherals whose physical address 1s also in this span define HW REGS BASE ALT STM OFST define HW REGS SPAN 0x04000000 fdefine HW REGS MASK HW REGS SPAN 1 The start address of Lightweight HPS to FPGA Bridge after mapping can be retrieved by ALT LWFPGASLVS OFST which is defined in altera hps hardware library The slave IP connected to the bridge can then be accessed through the base address and the register offset in these IPs For instance the base address of the PIO slave IP in this system is 0 0001 0040 the direction control register offset is 0x01 and the data register offset 15 0x00 The following statement is used to retrieve the base address of PIO slave IP h2p Iw led addr virtual base unsigned long ALT_LWFPGASLVS_OFST LED BASE amp unsigned long HW
20. Down Properties Figure 8 4 Click on the Flash Loader 12 Select the targeted FPGA to be programed into the EPCS as shown in Figure 8 5 13 Click OK and the Convert Programming Files page will appear as shown in Figure 8 6 14 Click Generate DEO Nano SoC 70 www terasic com User Manual April 2 2015 ANU RYAN UNIVERSITY PROGRAM 3p Select Devices Arria II GX Arria II GZ Export Arria V Arria V GZ Cydone Remove Cydone Cydone Uncheck All Cydone III LS Cydone IV E Cydone IV GX Cydone V II HardCopy III HardCopy IV MAX 10 FPGA MAX II Import Edit Figure 8 5 Select Devices page qu 5 wr Convert Programming File D SVN DEO nano DEO SOC Default DEO NANO SOC Default DEO NANO S 12 w Search altera com a Conversion setup files Output programming file Programming file type Ours J es gt File name output file jic Remote _ocal update difference file NONE Create Memory Map File Generate output file map Create files Generate output file periph jic and output file core rbf Create config data RPD Generate output file auto rpd area 5CSEMA4 sof Page 4 SOF Data Page 0 auto gt Add Device DEO SOC Default sof SCSEMASU23 Remove Up Down Properties Figure 8 6 Convert Programming Files page after selecting the device
21. Figure 3 6 vo File Edit View Processing Tools Window Help 5 Search altera com Enable real time ISP to allow background programming when available Checksum Usercode Program Verify Blank Examine Check Configure PI PI 00000000 A Save File Add IPS File Change IPS File Delete IPS File Change PR Programming File Delete PR Programming File Figure 3 6 Open the sof file to be programmed into the FPGA device DEO Nano SoC 15 www terasic com User Manual April 2 2015 www terasic com ANU S RYAN UNIVERSITY PROGRAM 5 Select the sof file to be programmed as shown in Figure 3 7 x Programming File Type Date Modified File lder 2014 12 29 LF 11 03 21 16 0MB jicFile 2014 12 29 09 24 43 3 8 sofFile 2014 12 26 02 11 01 DEO SOC Default sof Programming Files sof pof jam jbc ekp jic Figure 3 7 Select the sof file to be programmed into the FPGA device 6 Click Program Configure check box and then click Start button to download the sof file into the FPGA device as shown in Figure 3 8 DEO Nano SoC 16 www terasic com asic User Manual April 2 2015 www terasic com File Edit View Processing Tools Window Help 5 lt none gt SOCVHPS 00000000 D DED SOC Def 5CSEMA4U23 D0440CB8 us Change File
22. P 2 1 1 4 5 Lilt 0 MSE Figure 3 1 DIP switch SW10 setting of Active Serial AS mode at the back of DE0 Nano SoC board DEO Nano SoC 11 www terasic com Tijasic User Manual April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM Table 3 1 shows the relation between MSEL 4 0 and DIP switch SW10 Table 3 1 FPGA Configuration Mode Switch SW10 Board Reference Signal Name Description Default SW10 1 MSELO ON 0 SW10 2 MSEL1 Use th ins t tthe FPGA OFF 1 n SW10 3 MSEL2 0 Configuration scheme SW10 4 MSEL3 ON 0 SW10 5 MSEL4 OFF 1 SW10 6 N A N A N A Table 3 2 shows MSEL 4 0 setting of AS mode which is also the default setting on DEO Nano SoC When the board 1s powered on the FPGA 15 configured from EPCS which 15 pre programmed with the default code If developers wish to reconfigure FPGA from an application software running on Linux the MSEL 4 0 needs to be set to 01010 before the programming process begins If developers using the Linux Console with frame buffer or Linux LXDE Desktop SD Card image the MSEL 4 0 needs to be set to 00000 before the board is powered on Table 3 2 MSEL Pin Settings for FPGA Configure of DE0 Nano SoC MSEL 4 0 Configure Scheme Description 10010 AS FPGA configured from EPCS default 01010 FPPx32 FPGA configured from HPS software Linux FPGA configured from HPS software U Boot with 0000
23. REGS MASK DEO Nano SoC 64 www terasic com Tijasic User Manual April 2 2015 www terasic com Considering this demonstration only needs to set the direction of PIO as output which 15 the default direction of the PIO IP the step above can be skipped The following statement is used to set the output state of the PIO alt write word h2p Iw led addr Mask The Mask in the statement decides which bit in the data register of the PIO IP is high or low The bits In data register decide the output state of the pins connected to the LED B Demonstration Source Code e Build tool Altera SoC EDS V 14 0 e Project directory Demonstration SoC FPGAMPS CONTROL LED e FPGA configuration file HP5 CONTROL LED rbf e Binary file HPS CONTROL LED e Build app command make make clean to remove all temporal files e Execute app command 5 CONTROL FPGA LED B Demonstration Setup e Quartus II and SoCEDS must be installed on the host PC e The MSEL 4 0 15 set to 00000 Connect a USB cable to the USB to UART connector J4 on the DEO Nano SoC board and the host PC Copy the executable files 5 CONTROL LED and the FPGA configuration file HPS CONTROL FPGA LED rbf into the microSD card under the home root folder in Linux e Insert the booting microSD card into the DEO Nano SoC board Please refer to the chapter 5 Running Linux on the DEO Nano SoC board on DEO Nano SoC Getti
24. SSTL 15 Class HPS DDR3 DQ 9 PIN L25 HPS DDR3 Data 9 SSTL 15 Class HPS DDRS3 DQ 10 PIN J27 HPS DDR3 Data 10 SSTL 15 Class HPS DDR3_DQ 11 PIN J28 HPS DDR3 Data 11 SSTL 15 Class HPS DDRS3 DQ 12 PIN M27 HPS DDR3 Data 12 SSTL 15 Class HPS DDRS3 DQ 13 PIN M26 HPS DDR3 Data 13 SSTL 15 Class HPS DDRS3 DQ 14 PIN M28 HPS DDR3 Data 14 SSTL 15 Class HPS DDRS3 DQ 15 PIN N28 HPS DDR3 Data 15 SSTL 15 Class HPS DDRS3 DQ 16 PIN N24 HPS DDR3 Data 16 SSTL 15 Class HPS DDRS3 DQ 17 PIN N25 HPS DDR3 Data 17 SSTL 15 Class HPS DDRS3 DQ 18 PIN T28 HPS DDR3 Data 18 SSTL 15 Class HPS DDRS3 DQ 19 PIN U28 HPS DDR3 Data 19 SSTL 15 Class HPS DDRS3 DQ 20 PIN N26 HPS DDR3 Data 20 SSTL 15 Class HPS DDRS3 DQ 21 PIN N27 HPS DDR3 Data 21 SSTL 15 Class HPS DDRS3 DQ 22 PIN R27 HPS DDR3 Data 22 SSTL 15 Class HPS DDRS3 DQ 23 PIN V27 HPS DDR3 Data 23 SSTL 15 Class HPS DDRS3 DQ 24 PIN R26 HPS DDR3 Data 24 SSTL 15 Class HPS DDRS3 DQ 25 PIN R25 HPS DDR3 Data 25 SSTL 15 Class HPS DDRS3 DQ 26 PIN AA28 HPS DDR3 Data 26 SSTL 15 Class HPS DDRS3 DQ 27 PIN W26 HPS DDR3 Data 27 SSTL 15 Class HPS DDRS3 DQ 28 PIN R24 HPS DDR3 Data 28 SSTL 15 Class HPS DDRS3 DQ 29 PIN T24 HPS DDR3 Data 29 SSTL 15 Class HPS DDRS3 DQ 30 PIN Y27 HPS DDR3 Data 30 SSTL 15 Class HPS DDRS3 DQ 31 PIN AA27 HPS DDR3 Data 31 SSTL 15 Class HPS DDRS3 DQGS n 0 PIN 16 HPS DDR3 Data Strobe n 0 D
25. comes with four independent headers The expansion header has 17 user pins 16pins GPIO and Ipin Reset connected directly to the Cyclone V SoC FPGA 6 pins Analog input connects to ADC and also provides DC 9V VCC9 DC 45V VCC5 DC 3 3V VCC3P3 and IOREF and three GND pins Please refer to Figure 3 18 for detailed pin out information The blue font represents the Arduino Uno R3 board pin out definition SCL SCL SDA SDA Analog Vref NC GND IOREF Arduino 013 D13 SCK Reset Arduino Reset N Arduino 1012 D12 MISO VCC3P3 Arduino 1011 D11 MOS VCC5 Arduino 1010 010 55 GND Arduino 109 D9 GND Arduino 108 D8 VCC9 Arduino 107 07 _106 06 ADC INO amp Arduino_lO5 D5 A1 ADC IN1 i Arduino 104 D4 A2 ADC_IN2 Arduino D3 Arduino 102 D2 _101 D1 TX _100 D0 RX A3 ADC_IN3 A4 ADC_IN4 A5 ADC_IN5 D12 MISO Arduino 1012 1 i 1 he VCC5 D13 SCK Arduino_1013 1 1 1 Arduino 1014 D11 MOSI Arduino Reset GND Figure 3 18 lists the all the pin out signal name of the Arduino Uno connector The blue font represents the Arduino pin out definition The 16 GPIO pins are provided to the Arduino Header for digital I O Table 3 11 lists the all the pin assignments of the Arduino Uno connector digital signal names relative to the Cyclone V SoC FPGA DEO Nano SoC 27 www terasic com Ti
26. each other via these interconnect bridges This chapter provides demonstrations on how to achieve superior performance and lower latency through these interconnect bridges when comparing to solutions containing a separate FPGA and discrete processor 7 1 HPS Control FPGA LED This demonstration shows how HPS controls the FPGA LED through Lightweight HPS to FPGA Bridge The FPGA is configured by HPS through FPGA manager in HPS B A brief view on FPGA manager The FPGA manager in HPS configures the FPGA fabric from HPS It also monitors the state of FPGA and drives or samples signals to or from the FPGA fabric The command 15 provided to configure FPGA through the FPGA manager The FPGA configuration data 15 stored in the file with rbf extension The MSEL 4 0 must be set to 00000 before executing the command on HPS B Function Block Diagram Figure 7 1 shows the block diagram of this demonstration The HPS uses Lightweight HPS to FPGA AXI Bridge to communicate with FPGA The hardware in FPGA part 15 built into Qsys The data transferred through Lightweight HPS to FPGA Bridge is converted into Avalon MM master interface The PIO Controller works as Avalon MM slave in the system They control the associated pins to change the state of LED This is similar to a system using Nios II processor to control LED DEO Nano SoC 63 www terasic com Tijasic User Manual April 2 2015 www terasic com HPS FPGA 4 Control Block User
27. id block Active low input affects the system reset domain for debug purpose DEO Nano SoC 19 www terasic com Tijasic User Manual April 2 2015 www terasic com VCC3P3 Cyclone V SoC KEY 3 HPS FPGA HPS_WARM_RST_N WARM_RST HPS RESET HPS NPOR KEY 4 DEV_CLRN HPS_ENET_RESET_N GPIO43 HPS RST GPIO42 10 100 1000 Base T Ethernet RSZ9031RN RESET N USB 2 0 OTG PHY USB3300 RESET HPS RESET PHY Inverter Figure 3 12 HPS reset tree on DEO Nano SoC board 3 5 Clock Circuitry Figure 3 13 shows the default frequency of all external clocks to the Cyclone V SoC FPGA A clock generator is used to distribute clock signals with low jitter The two 50MHz clock signals connected to the FPGA are used as clock sources for user logic Three 25MHz clock signal are connected to two HPS clock inputs and the other one is connected to the clock input of Gigabit Ethernet Transceiver One 24MHz clock signal is connected to the USB controller for USB Blaster II circuit and FPGA One 24MHz clock signals are connected to the clock inputs of USB OTG PHY The associated pin assignment for clock inputs to FPGA pins is listed in Table 3 5 DEO Nano SoC 20 www terasic com asic User Manual April 2 2015 www terasic com CDCE937 ANU S RA Cyclone FPGA CLK1 50 50MHz 59 FPGA CLK2 50 50MHz crx FPGA CLK3 50 50MHz HPS CLK1 25 25MHz CLK4P HPS_CLK2_25 25MHz E
28. ie Save File I Down Figure 8 7 Two devices are detected in the Quartus Programmer DEO Nano SoC www terasic com Tijasic User Manual April 2 2015 www terasic com UNIVERSITY PROGRAM Programmer D SVN DEO nano DEO NANO SOC Default DEO NANO SOC Default DEO SOC Default E wz Edit View Processing Tools Window Help Search altera com A Hardware Setup DE SoC USB 1 Enable real time ISP to allow background programming when available nane gt SOCVHPS 00000000 Factory default enhanced SCSEMA4 005 Change File Save File Figure 8 8 Quartus II programmer window with file 8 4 Erase the EPCS Device The steps to erase the existing file in the EPCS device are Set MSEL 4 0 10010 2 Choose Programmer from the Tools menu and the Chain cdf window will appear 3 Click Auto Detect and then select correct device both FPGA device and HPS will detected See Figure 8 7 4 Double click the red rectangle region shown in Figure 8 7 and the Select New Programming File page will appear Select the correct jic file 5 Erase the EPCS device by clicking the corresponding Erase box A factory default SFL image will be loaded as shown in Figure 8 9 DEO Nano SoC 73 www terasic com Tijasic User Manual April 2 2015 www terasic com JAN DTE RYAN UNIVERSITY PROGRAM ns 3 Programmer D SVN DE0_n
29. the GPIOI controller The status of KEY can be queried by reading the value of the bit 24 in the ext porta register of GPIOI controller GPIO1 Controller gpio_swporta_ddr register tz 2 Controls the Direction of HPS GPIO29 Controls the Direction of HPS GPIO30 Controls the Direction of HPS GPIO31 Controls the Direction of HPS_GPIO53 HPS_LED Controls the Direction of HPS GPIOS54 HPS KEY Controls the Direction of HPS GPIO55 Controls the Direction of HPS GPIO56 Controls the Direction of HPS GPIO57 Figure 6 5 swporta ddr register in the GPIO1 controller DEO Nano SoC 57 www terasic com Tijasic User Manual April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM The following mask is defined in the demo code to control LED and KEY direction and LED s output value define USER_IO_DIR 0x01000000 define BIT_LED 0x01000000 define BUTTON_MASK 0x02000000 The following statement is used to configure the LED associated pins as output pins alt setbits word virtual base Cuint32 t CALT SWPORTA DDR ADDR 6 uint32 t REGS MASK USER IO DIR The following statement 1s used to turn on the LED alt setbits word virtual base Cuint32 t C ALT SWPORTA DR ADDR amp 011132 t HW REGS MASK LED The following statement is used to read the content of gpio ext porta register
30. 0 HPS DDR3 Address 11 HPS DDR3 Address 12 HPS DDR3 Address 13 HPS DDR3 Address 14 HPS DDR3 Bank Address 0 HPS DDR3 Bank Address 1 HPS DDR3 Bank Address 2 DDR3 Column Address Strobe HPS DDR3 Clock Enable HPS DDR3 Clock HPS DDR3 Clock p HPS DDR3 Chip Select HPS DDR3 Data Mask 0 HPS DDR3 Data Mask 1 HPS DDR3 Data Mask 2 34 Standard SSTL 15 Class l SSTL 15 Class SSTL 15 Class l SSTL 15 Class SSTL 15 Class l SSTL 15 Class SSTL 15 Class SSTL 15 Class l SSTL 15 Class SSTL 15 Class l SSTL 15 Class SSTL 15 Class l SSTL 15 Class l SSTL 15 Class SSTL 15 Class l SSTL 15 Class SSTL 15 Class l SSTL 15 Class SSTL 15 Class SSTL 15 Class l Differential 1 5 V SSTL Class l Differential 1 5 V SSTL Class l SSTL 15 Class SSTL 15 Class l SSTL 15 Class l SSTL 15 Class www terasic com April 2 2015 UNIVERSITY PROGRAM HPS DDR3 DN 3 PIN AB28 HPS DDR3 Data Mask 3 SSTL 15 Class HPS DDR3 DQ 0 PIN J25 HPS DDR3 Data 0 SSTL 15 Class HPS DDR3 DQ 1 PIN J24 HPS DDR3 Data 1 SSTL 15 Class HPS DDR3 DQ 2 PIN E28 HPS DDR3 Data 2 SSTL 15 Class HPS DDR3 DQ 3 PIN D27 HPS DDR3 Data 3 SSTL 15 Class HPS DDR3 DQ 4 PIN J26 HPS DDR3 Data 4 SSTL 15 Class HPS DDR3 DQ 5 PIN K26 HPS DDR3 Data 5 SSTL 15 Class HPS DDR3 DQ 6 PIN G27 HPS DDR3 Data 6 SSTL 15 Class HPS DDR3 DQ 7 PIN F28 HPS DDR3 Data 7 SSTL 15 Class HPS DDR3 DQ S PIN K25 HPS DDR3 Data 8
31. 0 FPPx16 image stored on the SD card like LXDE Desktop or console Linux with frame buffer edition 3 2 Configuration of Cyclone V SoC FPGA on DEO Nano SoC There are two types of programming method supported by DEO Nano SoC 1 JTAG programming It is named after the IEEE standards Joint Test Action Group The configuration bit stream 15 downloaded directly into the Cyclone V SoC FPGA The FPGA will retain its current status as long as the power keeps applying to the board the configuration information will be lost when the power is off 2 AS programming The other programming method is Active Serial configuration DEO Nano SoC 12 www terasic com Tijasic User Manual April 2 2015 www terasic com UNIVERSITY PROGRAM The configuration bit stream Is downloaded into the serial configuration device 128 which provides non volatile storage for the bit stream The information is retained within EPCS 128 even if the DEO Nano SoC board is turned off When the board is powered on the configuration data in the EPCS128 device is automatically loaded into the Cyclone V SoC FPGA B JTAG Chain on DEO Nano SoC Board The FPGA device can be configured through JTAG interface on DEO Nano SoC board but the JTAG chain must form a closed loop which allows Quartus II programmer to the detect FPGA device Figure 3 2 illustrates the JTAG chain on DEO Nano SoC board gt y FPGA_TDI 4 g
32. Arduino 107 Arduino 106 Arduino_lO5 ADC_CONVST 4 INO ADC INO Arduino_104 ADC SCK eae N1 ________ Arduino lt ADC_IN3 ADC_IN2 _102 SDO ADC Em ADC_IN3 Arduino 101 lt a IN4 ADC_SDI IN6 Arduino 100 lt ADC_IN7 ADC INS Arduino 1012 1 do VCC5 LTC2308 Arduino 1013 1 1 1 1 Arduino 1011 Arduino Reset n GND VCC5 ADC_INO ADC_IN1 ADC_IN2 IN3 5 IN4 ADC IN5 ADC IN6 ADC 9 10 GND Figure 3 20 Connections between the FPGA 2x5 header and the A D converter Table 3 12 Pin Assignment of ADC Signal Name FPGA Pin No VO Standard ADC_CONVST 09 Conversion Start PIN V10 Serial Data Clock 33V S PIN erial Data Out ADC FPGA DEO Nano SoC 30 www terasic com Tijasic User Manual April 2 2015 www terasic com 3 7 Peripherals Connected to Hard Processor System HPS This section introduces the interfaces connected to the HPS section of the Cyclone V SoC FPGA Users can access these interfaces via the HPS processor 3 7 1 User Push buttons and LEDs Similar to the FPGA the HPS also has its set of switches buttons LEDs and other interfaces connected exclusively Users can control these interfaces to monitor the status of HPS Table 3 13 gives the pin assig
33. CLOCK LED x8 Button x 2 Switch x 4 4 ADC 2x5 Header Arduino Header 5 0 Header Prefix Name GPIO 1 Header None Prefix Name Figure 4 4 System configuration group B GPIO Expansion If users connect any Terasic GPIO based daughter card to the GPIO connector s on DEO Nano SoC the DEO Nano SoC System Builder can generate a project that include the corresponding module as shown in Figure 4 5 It will also generate the associated pin assignment automatically including pin name pin location pin direction and I O standard DEO Nano SoC 44 www terasic com Tijasic User Manual April 2 2015 www terasic com ANU RYAN UNIVERSITY PROGRAM DEO Nano SoC V1 0 0 System Configuration 2 m www terasic com Project Name PROGRA DEO NANO SOC DEO Nano SoC FPGA Board CLOCK vl LED x 8 Button x 2 Switch x 4 2 5 Header Arduino Header HPS GPIO 0 Header D5M 5M Pixel Camera M Prefix Name GPIO 1 Header Prefix Name Load Setting Figure 4 5 GPIO expansion group The Prefix Name is an optional feature that denote the pin name of the daughter card assigned in your design Users may leave this field blank B Project Setting Management The DEO Nano SoC System Builder also provides the option to load a setting or save users current board configuration in cfg file as shown in Figure
34. EDS v14 0 e Project directory Demonstration SoC hps_gsensor e Binary file gsensor e Build command make make clean to remove all temporal files e Execute command gsensor loop count B Demonstration Setup e Connect a USB cable to the USB to UART connector J4 on the DEO Nano SoC board and the host PC e Copy the executable file esensor into the microSD card under the home root folder in Linux e Insert the booting microSD card into the DEO Nano SoC board e Power on the DEO Nano SoC board asic DEO Nano SoC 61 www terasic com User Manual April 2 2015 JAN DTE RYA UNIVERSITY PROGRAM e Launch PuTTY to establish connection to the UART port of DEO Nano SoC board Type root to login Yocto Linux e Execute gsensor in the UART terminal of PuTTY to start the G sensor polling e The demo program will show the X Y and Z values in the PuTTY as shown in Figure 6 8 iB Cn na LEJ L Cn I LEJ LEJ 1 I Figure 6 8 Terminal output of the G sensor demonstration e Press CTRL C to terminate the program DEO Nano SoC 62 www terasic com 1 24 51 User Manual www terasic com Apr 2s 2015 Chapter 7 Examples for using both HPS SoC and FGPA Although HPS and FPGA can operate independently they are tightly coupled via a high bandwidth system interconnect built from high performance ARM AMBA AXITM bus bridges Both FPGA fabric and HPS can access to
35. EO Nano SoC 52 www terasic com Tijasic User Manual April 2 2015 www terasic com UNIVERSITY PROGRAM The make command will build the project The executable file my first hps will be generated after the compiling process is successful The clean all command removes all temporary files B Demonstration Source Code e Build tool Altera SoC EDS 14 0 e Project directory Demonstration SoC my_first_hps e Binary file first hps e Build command make make clean to remove all temporary files e Execute command my first hps B Demonstration Setup e Connect a USB cable to the USB to UART connector 74 on the DEO Nano SoC board and the host PC e Copy the demo file my first hps into a microSD card under the home root folder in Linux e Insert the booting microSD card into the DEO Nano SoC board e Power on the DEO Nano SoC board e Launch PuTTY and establish connection to the UART port of Putty Type root to login Altera Yocto Linux e Type my first hps in the UART terminal of PuTTY to start the program and the Hello World message will be displayed in the terminal 6 2 Users LED and KEY This demonstration shows how to control the users LED and KEY by accessing the register of GPIO controller through the memory mapped device driver The memory mapped device driver allows developer to access the system physical memory B Function Block Diagram Figure 6 1 shows the function block diagram of thi
36. SB_STP USB_DP HPS USB_ID CLK_USB_24 mo RST_n MR_n HPS RESET USB TPS3831 Figure 3 24 Connections between the HPS and USB OTG PHY Table 3 19 Pin Assignment of USB OTG PHY Signal Name FPGA Pin No Description Standard HPS USB CLKOUT PIN G4 60MHz Reference Clock Output 3 3V HPS USB DATA 0 PIN C10 HPS USB DATA 0 3 3V HPS USB DATA 1 PIN F5 HPS USB DATA 1 3 3V HPS USB DATA 2 PIN C9 HPS USB DATA 2 3 3V HPS USB DATA 3 PIN C4 HPS USB DATA 3 3 3V HPS USB DATA 4 PIN C8 HPS USB DATA 4 3 3V HPS USB DATA 5 PIN D4 HPS USB DATA 5 3 3V HPS USB DATA 6 PIN C7 HPS USB DATA 6 3 3V HPS USB DATA T PIN F4 HPS USB DATA 7 3 3V HPS USB DIR PIN E5 Direction of the Data Bus 3 3V HPS USB NXT PIN D5 Throttle the Data 3 3V HPS USB RESET PIN H12 HPS USB PHY Reset 3 3V HPS USB STP PIN C5 Stop Data Stream on the Bus 3 3V DEO Nano SoC 37 www terasic com Tijasic User Manual April 2 2015 www terasic com 3 7 7 G sensor The board comes with a digital accelerometer sensor module 345 commonly known as G sensor This G sensor 15 a small thin ultralow power assumption 3 axis accelerometer with high resolution measurement Digitalized output is formatted as 16 bit in two s complement and can be accessed through I2C interface The I2C address of G sensor is OxA6 OxA7 More information about this chip can be found in its datasheet which is available on manufactu
37. The bit mask is used to check the status of the key alt read word virtual base 011132 ALT GPIO1 EXT PORTA ADDR amp uint32 t REGS MASK B Demonstration Source Code e Build tool Altera SoC EDS V14 0 e Project directory Demonstration SoC hps_gpio e Binary file hps_gpio e Build command make make clean to remove all temporal files e Execute command hps gpio B Demonstration Setup e Connect a USB cable to the USB to UART connector J4 on the DEO Nano SoC board and the host PC e Copy the executable file hps_gpio into the microSD card under the home root folder in Linux ter 58 www User Manual April 2 2015 www terasic com UNIVERSITY PROGRAM e Insert the booting SD card Into the DE0 Nano SoC board e Power on the DEO Nano SoC board e Launch PuTTY and establish connection to the UART port of Putty Type root to login Altera Yocto Linux e hps gpio the UART terminal of PuTTY to start the program e HPS LED will flash twice and users can control the user LED with push button e Press 5 KEY to light up 5 LED e Press CTRL C to terminate the application 6 3 I2C Interfaced G sensor This demonstration shows how to control the G sensor by accessing its registers through the built in I2C kernel driver in Altera Soc Yocto Powered Embedded Linux B Function Block Diagram Figure 6 6 shows the fu
38. aiwan Email support terasic com Tel 886 3 575 0880 Website deO nano soc terasic com DEO Nano SoC 5 www terasic com Tijasic User Manual April 2 2015 www terasic com Chapter 2 Introduction of the DEO Nano SoC Board This chapter provides an introduction to the features and design characteristics of the board 2 1 Layout and Components Figure 2 1 and Figure 2 2 shows a photograph of the board It depicts the layout of the board and indicates the location of the connectors and key components FPGA FPGA Configuration HPS edo 2x20 GPIO FPGA LTC 2x7 Header System Arduino Header USB PHY USB OTG USB Micro AB 5V DC Power Jack HPS DDR3 Altera 28 nm 91 Mal eo 5 906909 HEL ki UART to USB Cyclone V FPGA puer F vit 89860909 Pen USB with ARM Cortex A9 r UART to USB USB Blaster Controller USB Mini B G Sensor Ethernet PHY HPS Gigabit Ethernet WARM RST HPS User Button HPS RST LED x8 Clock Generator MAX Slide Switch x4 72 ot M 291 GPIO 1 SVADC mln 2 5 Button 2 2x20 GPIO FPGA HPS User LED Figure 2 1 DEO Nano SoC development board top view DEO Nano SoC 6 www terasic com Tijasic User Manual April 2 2015 www terasic com A T X 014120025
39. ano DE0_NANO_SOC_Default DE0_NANO_SOC_Default DEO NANO SOC Default DEO SOC Default cdf File Edit View Processing Tools Window Hep 5 5 Hardware Setup DE SoC 158 1 Mode JTAG Enable real time ISP to allow background programming when available Checksum Usercode Program Verify Blank Examine Security Erase ISP Configure Check Bit CLAMP ipli Start lt none gt SOCVHPS 00000000 lt none gt Factory default enhanced 5CSEMA4 005BDA6A dii Auto Detect output file jic EPCS128 pu Stop Figure 8 9 Erase the EPCS device in Quartus Programmer 6 Click Start to erase the EPCS device 8 5 EPCS Programming via nios 2 flash programmer Before programming the EPCS via nios 2 flash programmer users must add an 5 patch file nios flash override txt into the Nios EDS folder The patch file is available in the folder DemonstationEPCS Patch of DEO Nano SoC System CD Please copy this to the folder QuartusInstalledFolder nios2eds bin e g C altera 14 INnios2edsWoin If the patch file is not included into the Nios II EDS folder an error will occur as shown in Figure 8 10 Using cable USEB Blaster LUSE 1 device instance ini and t Fo fh im gt Py ka Z nv m EPCS layout data looking for section 010216 1 Unable to we
40. ano SoC development board 15 equipped with high speed DDR3 memory analog to digital capabilities Ethernet networking and much more that promise many exciting applications The DEO Nano SoC Development Kit contains all the tools needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later 1 1 Package Contents Figure 1 1 shows a photograph of the DEO Nano SoC package DEO Nano SoC Board DEO Nano SoC Quick Start Guide Type A to Mini B USB Cable O Power DC Adapter 5V Figure 1 1 The DEO Nano SoC package contents DEO Nano SoC 4 www terasic com Tijasic User Manual April 2 2015 www terasic com The DE0 Nano SoC package includes The DEO Nano SoC development board DEO Nano SoC Quick Start Guide USB cable Type A to Mini B for FPGA programming or UART control 5 2 DC power adapter 1 2 DEO Nano SoC System CD The DEO Nano SoC System CD contains all the documents and supporting materials associated with DEO Nano SoC including the user manual system builder reference designs and device datasheets Users can download this system CD from the link http cd deO nano soc terasic com 1 3 Getting Help Here are the addresses where you can get help if you encounter any problems Altera Corporation 101 Innovation Drive San Jose California 95134 USA Email university altera com Terasic Technologies 9F No 176 Sec 2 Gongdao 5th Rd East Dist Hsinchu City 30070 T
41. ata8 sizeof unsigned char The step 4 above can also be changed to the following to read multiple byte values read file amp szData8 sizeof szDataS8 where szData 15 an array of bytes The step 4 above can be changed to the following to write multiple byte values DEO Nano SoC 60 www terasic com Tijasic User Manual April 2 2015 www terasic com write file amp szData8 sizeof szData8 where szData 15 an array of bytes B G sensor Control The ADI ADXL345 provides I2C and SPI interfaces I2C interface is selected by setting the CS pin to high on the DEO Nano SoC board The ADI ADXL345 G sensor provides user selectable resolution up to 13 bit 16g The resolution can be configured through the DATA FORAMT 0x31 register The data format in this demonstration is configured as Full resolution mode lt 16g range mode Left justified mode The X Y Z data value can be derived from the DATAX0 0x32 DATAX1 0x33 DATAYO 0x34 DATAY 1 0x35 DATAZO 0x36 DATAX1 0x37 registers The represents the least significant byte and the DATAXI represents the most significant byte It is recommended to perform multiple byte read of all registers to prevent change in data between sequential registers read The following statement reads 6 bytes of X Y or Z value read file szData8 sizeof szData8 where szData is an array of six bytes B Demonstration Source Code e Build tool Altera SoC
42. atch file DEO NANO SOC to load the bitstream and software execution file to the FPGA The Nios II console will display the voltage of the specified channel voltage result information 0090000 vil OOOO Tr o I J 2 4 ati 5 gt 2 sk TOUT OD gt j 1 fale U5 45378 LI LI 2 82 4 T Che 0 eo 9 5888 T w aa Lm Figure 5 4 Hardware setup for the ADC reading demonstration DEO Nano SoC 50 www terasic com Tijasic User Manual April 2 2015 www terasic com Chapter Examples for HPS SoC This chapter provides several C code examples based on the Altera SoC Linux built by Yocto project These examples demonstrate major features of peripherals connected to HPS interface on DEO Nano SoC board such as users LED KEY I2C interfaced G sensor All the associated files can be found in the directory Demonstrations SOC of the DEO Nano SoC System CD Please refer to Chapter 5 Running Linux on the DE0 Nano SoC board from the DEO Nano SoC Getting Started Guide pdf to run Linux on DEO Nano SoC board B Installation of the Demonstrations To install the demonstrations on the host computer Copy the directory Demonstrations into a local directory of your choice Altera SoC EDS v14 0 is required for users to compile the c code
43. connected to one or two GPIO ports is shown in Table 3 9 Supplied Voltage 5V 3 3V Signal Name GPIO_0 0 GPIO O 1 GPIO O 2 GPIO_0 3 GPIO_0 4 _0 5 _0 6 0 7 GPIO 08 GPIO O 9 GPIO 0 10 GPIO 0 11 GPIO 0 12 GPIO 0 13 GPIO 0 14 GPIO 0 15 GPIO 0 16 GPIO 0 17 GPIO 0 18 GPIO 0 19 GPIO 0 20 GPIO 0121 GPIO 0 22 GPIO 01231 GPIO 01241 GPIO 0 25 GPIO O 26 GPIO 0127 www terasic com Max Current Limit Table 3 9 Voltage and Max Current Limit of Expansion Header s 1A depend on the power adapter specification 1 5A Table 3 10 Pin Assignment of Expansion Headers Standard FPGA Pin No PIN V12 PIN AF7 PIN W12 PIN AF8 PIN Y8 PIN AB4 PIN W8 PIN Y4 PIN Y5 PIN U11 PIN T8 PIN T12 PIN AH5 PIN AH6 PIN 4 PIN AG5 PIN AH3 PIN AH2 PIN 4 PIN AG6 PIN AF5 4 PIN T13 PIN T11 PIN AE7 PIN AF6 PIN AF9 PIN AES DEO Nano SoC User Manual Description GPIO Connection O 0 GPIO Connection 0 1 GPIO Connection 0 2 GPIO Connection 0 3 GPIO Connection 0 4 GPIO Connection 0 5 GPIO Connection O 6 GPIO Connection 0 7 GPIO Connection O 8 GPIO Connection 0 9 GPIO Connection 0 10 GPIO Connection 0 11 GPIO Connection 0 12 GPIO Connection 0 13 GPIO Connection 0 14 GPIO Connection 0 15 GPIO Connection 0 16 GPIO Connection 0 17 GPIO Connection 0 18 GPIO Connection 0 19 GPIO Connection 0 20 GPIO Connection 0 21 GPIO Conn
44. e Board 15 damaged due to incorrect bank voltage setting or pin assignment e Board is malfunctioned because of wrong device chosen declaration of pin location or direction 1s incorrect or forgotten e Performance degradation due to improper pin assignment 4 2 Design Flow This section provides an introduction to the design flow of building a Quartus II project for DEO Nano SoC 40 www terasic com Tijasic User Manual April 2 2015 www terasic com ANU S RYN UNIVERSITY PROGRAM DEO Nano SoC under the DEO Nano SoC System Builder The design flow is illustrated in Figure 4 1 The DEO Nano SoC System Builder will generate two major files a top level design file v and a Quartus II setting file qsf after users launch the DEO Nano SoC System Builder and create a new project according to their design requirements The top level design file contains a top level Verilog HDL wrapper for users to add their own design logic The Quartus II setting file contains Information such as FPGA device type top level pin assignment and the I O standard for each user defined I O pin Finally the Quartus II programmer 15 used to download sof file to the development board via JTAG interface start Launch Quartus II Launch 0 50 and Open Project System Builder Add User Create New 0 50 Design Logic System Builder Project Compile to Generate Quartus II generate SOF Project and Document Config
45. e EPCS device Leaving target processor paused Figure 8 10 Error Message No EPCS Layout Data DEO Nano SoC 74 www terasic com Tijasic User Manual April 2 2015 www terasic com 8 6 Nios ll Boot from EPCS Device in Quartus ll v14 1 There is a known problem in Quartus II software that the Quartus Programmer must be used to program the EPCS device on DEO Nano SoC board Please refer to Altera s website here with details step by step asIC DEO Nano SoC 75 WWW terasic com User Manual April 2 2015 Chapter 9 Appendix 9 1 Revision History Change Log Initial Version Preliminary Minor corrections fixing typos and broken links Copyright 2015 Terasic Inc All rights reserved DEO Nano SoC 76 www terasic com Tijasic User Manual April 2 2015 www terasic com Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information Terasic P0286
46. ection 0 22 GPIO Connection 0 23 GPIO Connection 0 24 GPIO Connection 0 25 GPIO Connection 0 26 GPIO Connection 0 27 25 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V www April 2 2015 JAN DTE RYA UNIVERSITY PROGRAM GPIO O 28 GPIO_0 29 GPIO_0 30 GPIO 0 31 GPIO 0 32 GPIO 0133 GPIO 0134 GPIO 0 35 GPIO 1 0 GPIO 1 1 GPIO 1 2 GPIO 1 3 GPIO 1 4 GPIO 1 5 GPIO 1 6 GPIO 1 7 GPIO 1 8 GPIO 1 9 GPIO 1 10 GPIO 1 11 GPIO 1 12 GPIO 1 13 GPIO 1 14 GPIO 1 15 GPIO 1 16 GPIO 1 17 GPIO 1 18 GPIO 1 19 GPIO 1 20 GPIO 1 21 GPIO 1 22 GPIO 1 23 GPIO 1 24 GPIO 1 25 GPIO 1 26 GPIO 1 27 GPIO 1 28 GPIO 1 29 GPIO 1 30 GPIO 1 31 GPIO 1 32 GPIO 1 33 GPIO 1 34 GPIO 1 35 www terasic com PIN AD10 PIN 9 PIN AD11 PIN AF10 PIN AD12 PIN AE11 PIN AF11 PIN AE12 PIN Y15 PIN AG28 PIN AA15 PIN AH27 PIN AG26 PIN AH24 PIN AF23 PIN AE22 21 20 AG19 20 AC23 AG18 26 19 AG24 25 23 AG23 19 18 AD19 20 24 AD20 22 22 19 21 21 18 23 23 18
47. er II Mini B USB connector DEO Nano SoC 9 www terasic com Tijasic User Manual April 2 2015 www terasic com Memory Device IGB 2x256Mx16 DDR3 SDRAM on HPS Micro SD card socket on HPS Communication One USB 2 0 OTG ULPI Interface with USB Micro AB connector UART to USB USB Mini B connector e 10 100 1000 Ethernet Connectors Two 40 pin expansion headers Arduino expansion header One 10 pin ADC input header One LTC connector one Serial Peripheral Interface SPI Master one I2C and one GPIO interface ADC 12 Bit Resolution 5 00Ksps Sampling Rate SPI Interface 8 Channel Analog Input Input Range OV 4 096V Switches Buttons and Indicators 3 user Keys FPGA x2 HPS x1 4 user switches FPGA x4 9 user LEDs FPGA x8 HPS x 1 2 HPS reset buttons HPS_RESET_n and HPS WARM RST n Sensors G Sensor on HPS Power e 5V DC input DEO Nano SoC 10 www terasic com ter User Manual April 2 2015 www terasic com Chapter Using the DEO Nano SoC Board This chapter provides an instruction to use the board and describes the peripherals 3 1 Settings of FPGA Configuration Mode When the DEO Nano SoC board is powered on the FPGA can be configured from EPCS or HPS The MSEL 4 0 pins are used to select the configuration scheme It is implemented as a 6 pin DIP switch SW10 on the DEO Nano SoC board as shown in Figure 3 1 5 NO WE P 6
48. et SoC Figure 3 23 Connections between the FPGA and SD card socket Table 3 18 Pin Assignment of Micro SD Card Socket Signal Name FPGA Pin No Description Standard HPS SD CLK PIN B8 HPS SD Clock 3 3V HPS_SD_CMD PIN_D14 HPS SD Command Line 3 3V HPS_SD_DATA 0 PIN C13 HPS SD Data 0 3 3V HPS SD DATA 1 PIN B6 HPS SD Data 1 3 3V HPS_SD_DATA 2 PIN B11 HPS SD Data 2 3 3V HPS SD DATA 3 PIN B9 HPS SD Data 3 3 3V DEO Nano SoC 36 www terasic com Tijasic User Manual April 2 2015 www terasic com 3 7 6 USB 2 0 OTG The board provides USB interfaces using the SMSC USB3300 controller SMSC USB3300 device a 32 pin QFN package device 15 used to Interface to a single Type Micro USB connector This device supports UTMI Low Pin Interface ULPI to communicate to USB 2 0 controller In HPS As defined by OTG mode the PHY can operate In Host or Device modes When operating in Host mode the interface will supply the power to the device through the Micro USB interface Figure 3 24 shows the connections of USB PTG PHY to the HPS Table 3 19 lists the pin assignment of USB OTG PHY to the HPS HPS USB DATA 7 0 USB CPEN USB VCC5 DATA 0 CPEN EN OUT USB EXTVBUS NRB S SYN CLKOUT EXTVBUS FAULT_N USB_VBUS HPS USB NXT UR E TPS2553DRVR HPS_USB_DIR ony 1098 0 HPS_U
49. hannel 12 bit ADC with a SPI MICROWIRE compatible serial interface This ADC includes an internal reference and a fully differential sample and hold circuit to reduce common mode noise The internal conversion clock allows the external serial output data clock SCK to operate at any frequency up to 40MHz It can be configured to accept eight input signals at inputs INO through ADC_IN7 These eight input signals are connected to a 2x5 header as shown in Figure 3 19 DEO Nano SoC 28 www terasic com Tijasic User Manual April 2 2015 www terasic com a lt EJ gt ds POS O csp 89868998 E VCC5 IN1 IN3 ADC IN5 ADC IN7 Figure 3 19 Signals of the 2x5 Header ADC INO ADC IN2 ADC IN4 ADC IN6 GND These Analog inputs are shared with the Arduino s analog input pin INO ADC INS Figure 3 20 shows the connections between the FPGA 2x5 header Arduino Analog input and the A D converter More information about the A D converter chip is available in its datasheet It can be found on manufacturer s website or in the directory Datasheet ADC of DEO Nano SoC system CD www terasic com DEO Nano SoC User Manual 29 www April 2 2015 Analog Vref GND Arduino 1013 Arduino 1012 Arduino 1011 Arduino 1010 Arduino 109 Arduino 108 NC IOREF Arduino Reset n VCC3P3 VCC5 GND GND VCC9 Arduino
50. ifferential 1 5 V SSTL Class HPS DDRS3 DQGS n 1 PIN R18 HPS DDR3 Data Strobe n 1 Differential 1 5 V SSTL Class HPS DDR3 DQS n 2 PIN T18 HPS DDR3 Data Strobe n 2 Differential 1 5 V SSTL Class HPS DDRS3 DQGS n 3 PIN T20 HPS DDR3 Data Strobe n 3 Differential 1 5 V SSTL Class HPS DDR3 005 p 0 PIN R17 HPS DDR3 Data Strobe p 0 Differential 1 5 V SSTL Class HPS DDR3 DQS p 1 PIN 819 HPS DDR3 Data Strobe p 1 Differential 1 5 V SSTL Class HPS DDRS3 005 p 2 PIN T19 HPS DDR3 Data Strobe p 2 Differential 1 5 V SSTL Class HPS DDR3 DQS p 3 PIN U19 HPS DDR3 Data Strobe p 3 Differential 1 5 V SSTL Class HPS DDR3 ODT PIN D28 HPS DDR3 On die Termination SSTL 15 Class HPS DDRS3 RAS n PIN A25 DDR3 Row Address Strobe SSTL 15 Class HPS DDR3 RESET n PIN V28 HPS DDR3 Reset SSTL 15 Class Nano 35 2 2015 www terasic com ANU RYAN UNIVERSITY PROGRAM HPS DDR3 WE PIN E25 HPS DDR3 Write Enable SSTL 15 Class HPS DDR3 RZQ PIN D25 External reference ball for 1 5 V output drive calibration 3 7 5 Micro SD Card Socket The board supports Micro SD card interface with x4 data lines It serves not only an external storage for the HPS but also an alternative boot option for DEO Nano0 SoC board Figure 3 23 shows signals connected between the HPS and Micro SD card socket Table 3 18 lists the pin assignment of Micro SD card socket to the HPS SD CLK SD CMD e Micro SD Card C Dy Sock
51. input state 15 high and the value 0 indicates the input state 15 low B GPIO Register Address Mapping The registers of HPS peripherals are mapped to HPS base address space OXFC000000 with 64K B size The registers of GPIO1 controller are mapped to the base address OXFF708000 with 4KB size and the registers of the GPIO2 controller are mapped to the base address OXFF70A000 with 4KB size as shown in Figure 6 3 DEO Nano SoC 23 www terasic com Tijasic User Manual April 2 2015 www terasic com HPS Identifier HPS Access R W Description Address map for the HHP HPS system domain Reserved 0 QSPI Flash Controller Module QSPIREGS OxFF705000 OxFF705100 e mu manager Module Vianner R ACEL ACPID Reserved 12 JOxFF708080 Reserved 12 O OxFF709080 OFFA AXI Slave EMAC Module EMACI OxFF702000 Figure 6 3 GPIO address map B Software API Developers can use the following software API to access the register of GPIO controller open open memory mapped device driver mmap map physical memory to user space alt_read_word read a value from a specified register alt_write_word write a value into a specified register munmap clean up memory mapping close close device driver Developers can also use the following MACRO to access the register alt setbits word set specified bit value to one for a specified register
52. jasic User Manual April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM Table 3 11 Pin Assignments for Arduino Uno Expansion Header connector Schematic Specific features FPGA Pin Description 5 Signal Name For Arduino Arduino 100 PIN AG13 Arduino 100 RXD 3 3 V Arduino 101 PIN AF13 Arduino 101 TXD 3 3 V Arduino 102 PIN AG10 Arduino 102 3 3 V Arduino 103 PIN AG9 Arduino 103 3 3 V Arduino 104 PIN 014 Arduino 104 3 3 V Arduino 105 U13 Arduino 105 3 3 V Arduino 106 PIN 8 Arduino IO6 3 3 V Arduino 107 PIN AH8 Arduino 107 3 3 V Arduino 108 PINAFI7 Arduino 108 3 3 V Arduino 109 PIN AE15 gt Arduino 109 3 3 V Arduino 1010 PIN AF15 Arduino 1010 SS 3 3 V Arduino 1011 PIN AG16 Arduino 1011 MOSI 3 3 V Arduino 1012 PIN AH11 Arduino 1012 MISO 3 3 V Arduino 1013 PIN AH12 Arduino 1013 SCK 3 3 V Arduino 1014 PIN AH9 Arduino 1014 SDA 3 3 V Arduino 1015 PIN AG11 Arduino 1015 SCL 3 3 V Arduino Reset PIN AH7 Reset signal low active 3 3 V Besides 16 pins for digital GPIO there are also 6 analog inputs on the Arduino Uno R3 Expansion Header INO IN5 Consequently we use ADC LTC2306 from Linear Technology on the board for possible future analog to digital applications We will introduce in the next section 3 6 4 A D Converter and Analog Input The DEO Nano SoC has an analog to digital converter LTC2308 The LTC2308 is a low noise 500ksps 8 c
53. n DEO Nano SoC Table 3 3 LED Indicators Board Reference _ Reference LED LED Name LED 3 V Power Illuminate when 3 3V 3 3V power Is active LED10 DONE Illuminates when the FPGA i is successfully configure configured DEO Nano SoC 18 www terasic com Tijasic User Manual April 2 2015 www terasic com UNIVERSITY PROGRAM LED11 JTAG TX Illuminate when data is transferred from JTAG to USB Host LED12 JTAG RX Illuminate when data is transferred from USB Host to JTAG TD TXD Illuminate when data is transferred from FT232R to USB Host RXD UART RXD when data is transferred from USB Host to FT232R 3 4 Board Reset Elements There two HPS reset buttons on DE0 Nano SoC HPS cold reset and HPS warm reset as shown in Figure 3 11 Table 3 4 describes the purpose of these two HPS reset buttons Figure 3 12 15 the reset tree for DEO Nano SoC B E ER 26000 vi UAM UG E HPS RESET N HPS WARM Figure 3 11 HPS cold reset and warm reset buttons on DEO Nano SoC Table 3 4 Description of Two HPS Reset Buttons DE0 Nano SoC Board Reference Signal Name Cold reset to the HPS Ethernet PHY and USB host device KEYA HPS RESET N keva Reser n 08 low input which resets all HPS logics that can be reset KEY3 HPS WARM RST N Warm reset to the
54. nction block diagram of this demonstration The G sensor on the DEO Nano SoC board is connected to the 2 0 controller in HPS The G Sensor I2C 7 bit device address 15 0x53 The system I2C bus driver 1s used to access the register files in the G sensor The G sensor interrupt signal 15 connected to the PIO controller This demonstration uses polling method to read the register data asic DEO Nano SoC 59 www terasic com User Manual April 2 2015 FPGA SoC DDR3 ARM Program HPS Linux User Mode 2 SDA G Sensor I2C address 0x53 Linux Kernel Mode m K I Figure 6 6 Block diagram of the G sensor demonstration B 2 Driver The procedures to read a register value from G sensor register files by the existing I2C bus driver in the system are 1 Open I2C bus driver dev 12c 0 file 2 0 O_RDWR 2 Specify G sensor s I2C address 0x53 ioctl file 2C_SLAVE 0x53 3 Specify desired register index in g sensor write file amp Addr8 sizeof unsigned char 4 Read one byte register value read file amp Data8 sizeof unsigned char The G sensor I2C bus is connected to the I2CO controller as shown in the Figure 6 7 The driver name given is dev i2c 0 I2CO SDA A19 5 2 0 SDAT 220 scL 18 5 1260 SCLK Figure 6 7 Connection HPS 2 signals The step 4 above can be changed to the following to write a value into a register write file amp D
55. ng Started Guide pdf on how to build a booting microSD card image e Power on the DEO Nano SoC board e Launch PuTTY to establish connection to the UART port of the DEO Nano SoC board Type root to login Altera Yocto Linux e Execute dd if HPS CONTROL LED rbf of dev fpea0 bs 1M in the UART terminal of PuTTY to configure the FPGA through the FPGA manager After the configuration is successful the message shown in Figure 7 2 will be displayed in the terminal DEO Nano SoC 65 www terasic com Tijasic User Manual April 2 2015 www terasic com Figure 7 2 Running command to configure the FPGA e Execute HPS_CONTROL FPGA LED in UART terminal of PuTTY to start the program e The message shown in Figure 7 3 will be displayed in the terminal The LED 7 0 will be flashing Figure 7 3 Running result in the terminal of PuTTY e Press CTRL C to terminate the program DEO Nano SoC 66 www terasic com Tijasic User Manual April 2 2015 www terasic com Chapter 8 Programming the EPCS Device This chapter describes how to program the serial configuration EPCS device with Serial Flash Loader SFL function via the JTAG interface Users can program EPCS devices with a JTAG indirect configuration jic file which is converted from a user specified SRAM object file sof in Quartus The sof file is generated after the project compilation is successful The steps of converting sof to jic in Quartus II are lis
56. nment of all the LEDs switches and push buttons Table 3 13 Pin Assignment of LEDs Switches and Push buttons Signal Name _ FPGA Pin HPS GPIO Register bit Function HPS_KEY PIN Ji8 Plo 5 HPS LED PIN A20 GPIO53 1 24 I O 3 7 2 Gigabit Ethernet The board supports Gigabit Ethernet transfer by an external Micrel KSZ9031 RN PHY chip and HPS Ethernet MAC function The KSZ9031RN chip with integrated 10 100 1000 Mbps Gigabit Ethernet transceiver also supports RGMII MAC interface Figure 3 21 shows the connections between the HPS Gigabit Ethernet PHY and RJ 45 connector The pin assignment associated to Gigabit Ethernet interface is listed in Table 3 14 More information about the KSZ9031RN PHY chip and its datasheet as well as the application notes which are available on the manufacturer s website DEO Nano SoC 3l www terasic com Tijasic User Manual April 2 2015 www terasic com HPS TX 0 HPS ENET GTX CLK oU GR HPS ENET TX EN HPS RX DATA 3 0 ATERA m yclone V HPS HPS HPS ENET MDIO Mpio T HPS INT NTN Hc HPS ENET RESET pesg TN CLK_ENET_25 y KSZ9031RN RJ45 Figure 3 21 Connections between the HPS and Gigabit Ethernet Table
57. nterface interrupt UART to USB USB Mini B connector Warm reset button and cold reset button One user button and one user LED LTC 2x7 expansion header 2 2 Block Diagram of the DEO Nano SoC Board Figure 2 5 is the block diagram of the board All the connections are established through the Cyclone V SoC FPGA device to provide maximum flexibility for users Users can configure the FPGA to implement any system design www terasic com www terasic com User Manual April 2 2015 JA DTE RYA UNIVERSITY PROGRAM CLOCK 25 2 5V 2A Power Adaptor 5V DC Jack Micro SD Card ee Ethernet USB OTG 58 1GB DDR3 2 chip x32 USB Mini B Accelerometer MSEL 4 0 L 2 4 5 EPCS128 CLOCK 50MHz Cyclo ety 5CSEMA4U23C6 2x20 pin GPIO 2x20 pin GPIO Digital Arduino Header Analoc ADC LTC 2x7 Header SB F F BP fee Pr 228202211 User LED HES RST Push Button 2 Slide Switch x4 LE Button 2x5 Header Figure 2 3 Block diagram of DEO Nano SoC Detailed information about Figure 2 3 are listed below FPGA Device Cyclone SoC 5CSEMA4U23C6N Device Dual core ARM Cortex A9 HPS 40K programmable logic elements 2 460 Kbits embedded memory 5 fractional PLLs 2 hard memory controllers Configuration and Debug Serial configuration device EPCSI28 on FPGA Onboard USB Blast
58. om Table 3 15 State and Definition of LED Mode Pins LED State LED Definition Link Activity LEDG LEDY LEDG LEDY H H OFF OFF Link off L H ON OFF 1000 Link No Activity Toggle H Blinking OFF 1000 Link Activity RX TX H L OFF ON 100 Link No Activity H Toggle OFF Blinking 100 Link Activity RX TX L L ON ON 10 Link No Activity Toggle Toggle Blinking Blinking 10 Link Activity RX TX 3 7 3 UART The board has one UART interface connected for communication with the HPS This interface doesn t support HW flow control signals The physical interface is implemented by UART USB onboard bridge from a FT232R chip to the host with an USB Mini B connector More information about the chip is available on the manufacturer s website or In the directory Datasheets UART_TO_USB of DEO Nano SoC system CD Figure 3 22 shows the connections between the HPS FT232R chip and the USB connector Table 3 16 lists the pin assignment of UART interface connected to the HPS FT232 DP Gam Cyclone J FT232 DM 5 USB Figure 3 22 Connections between the HPS and FT232R Chip DEO Nano SoC 33 www terasic com Tijasic User Manual April 2 2015 www terasic com Signal Name HPS_UART_RX HPS_UART_TX HPS_CONV_USB_N Table 3 16 Pin Assignment of UART Interface FPGA Pin No Description PIN A22 HPS UART Receiver PIN 21 HPS UART Transmitter PIN C6 Reserve 3 7
59. onverter All the associated files can be found in the directory Demonstrations FPGA of DEO Nano SoC System CD B Installation of Demonstrations Install the demonstrations on your computer Copy the folder Demonstrations to a local directory of your choice It 1s important to make sure the path to your local directory contains NO space Otherwise it will lead to error in Nios Note Quartus v14 0 or later is required for all DEO Nano SoC demonstrations to support Cyclone SoC device 5 1 DEO Nano SoC Factory Configuration The DEO Nano SoC board has a default configuration bit stream pre programmed which demonstrates some of the basic features on board The setup required for this demonstration and the location of its files are shown below B Demonstration Setup File Locations and Instructions e Project directory DEO SOC Default e Bitstream used DEO SOC Default sof or DEO SOC Default jic e Power on the DEO Nano SoC board with the USB cable connected to the USB Blaster II port If necessary that 1s 1f the default factory configuration 1s not currently stored in the EPCS device download the bit stream to the board via JTAG interface e You should now be able to observe the LEDs are blinking e For the ease of execution a demo batch folder 1s provided in the project It 15 able to not only load the bit stream into the FPGA in command line but also program or erase jic file to the DEO Nano SoC
60. project 6 1 Hello Program This demonstration shows how to develop first HPS program with Altera SoC EDS tool Please refer to First HPS pdf from the system CD for more details The major procedures to develop and build HPS project are Install Altera SoC EDS on the host PC Create program c h files with a generic text editor Create a Makefile with a generic text editor Build the project under Altera SoC EDS DEO Nano SoC 5I www terasic com ter www terasic com User Manual April 2 2015 ANU S RYAN UNIVERSITY PROGRAM B Program File The main program for the Hello World demonstration 15 finclude lt stdio h gt int mainfint argc char argv bprintf Hello World rimn returni B B Makefile A Makefile is required to compile a project The Makefile used for this demo 1s TARGET my first CROSS COMPILE arm linux gnueabihf CFLAGS Wall I SOCEDS DEST ROOT ip altera hps altera hps hwlib include LDFLAGS g Wa ll CROSS COMPILE ARCH arm build TARGET TARGET main o LDFLAGS o 8 s due CFLAGS c lt o clean rm TARGET B Compile Please launch Altera SoC EDS Command Shell to compile a project by executing C altera 14 0 embedded Embedded_Command_ Shell bat The cd command can change the current directory to where the Hello World project 1s located D
61. r block There are three 32 bit registers in the GPIO controller used in this demonstration The registers are pio swporta dr write output data to output I O pin pio swporta ddr configure the direction of I O pin pio ext porta read input data of I O input pin The gpio swporta ddr configures the LED pin as output pin and drives it high or low by writing data to the gpio swporta dr register The first bit least significant bit of gpio swporta dr controls the direction of first IO pin in the associated GPIO controller and the second bit controls the direction of second IO pin in the associated GPIO controller and so on The value 1 in the register bit indicates the I O direction is output while the value 0 in the register bit indicates the I O direction 15 input The first bit of gpio swporta dr register controls the output value of first I O pin in the associated GPIO controller the second bit controls the output value of second I O pin in the associated GPIO controller and so on The value 1 in the register bit indicates the output value is high and the value 0 indicates the output value is low The status of KEY can be queried by reading the value of gpio ext porta register The first bit represents the input status of first IO pin in the associated GPIO controller and the second bit represents the input status of second IO pin in the associated GPIO controller and so on The value in the register bit indicates the
62. rer s website or in the directory Datasheet G Sensor folder of DEO Nano SoC system CD Figure 3 25 shows the connections between the HPS and G sensor Table 3 20 lists the pin assignment of G senor to the HPS U19 5 12 0 SCLK P SCL SCLK Cyclone y Ds enn Sp SoC HPS GSENSOR INT INT1 HPS ADXL345 Figure 3 25 Connections between Cyclone V SoC FPGA and G Sensor Table 3 20 Pin Assignment of G senor Signal Name FPGA Pin No Description Standard HPS GSENSOR INT PIN A17 HPS GSENSOR Interrupt Output 3 3V HPS 2 0 SCLK PIN C18 HPS 2 0 Clock 3 3V HPS 2 0 SDAT PIN A19 HPS 2 0 Data 3 3V 3 8 LTC Connector The board has a 14 pin header which is originally used to communicate with various daughter cards from Linear Technology It is connected to the SPI Master and I2C ports of HPS The communication with these two protocols is bi directional The 14 pin header can also be used for GPIO SPI or 2 based communication with the HPS Connections between the HPS and LTC DEO Nano SoC 38 www terasic com Tijasic User Manual April 2 2015 www terasic com connector are shown in Figure 3 26 and the pin assignment of LTC connector 15 listed in Table 3 21 VCC9 VCC3P3 HPS SPIM HPS SPIM SS 3 4 S B4AN HPS SPIM MOSI amp Lc HPS SPIM MISO VCC3P3 5 Soc HPS I2C1 SDAT 0 ohm HPS I2C1 SCLK 0 1uF HPS HPS LTC GPIO U2 HPS SPIM MOSI I
63. s demonstration The users LED and KEY are connected to the GPIOI controller in HPS The behavior of GPIO controller is controlled by the register in GPIO controller The registers can be accessed by application software through the memory mapped device driver which 15 built into Altera SoC Linux DEO Nano SoC 53 www terasic com Tijasic User Manual April 2 2015 www terasic com FPGA SoC DDR3 ARM Program HPS Linux User Mode Linux Kernel Mode Figure 6 1 Block diagram of GPIO demonstration LED KEY B Block Diagram of GPIO Interface The HPS provides three general purpose I O GPIO interface modules Figure 6 2 shows the block diagram of GPIO Interface GPIO 28 0 is controlled by the GPIOO controller and GPIO 57 29 is controlled by the GPIOI controller GPIO 70 58 and input only GPI 13 0 are controlled by the GPIO2 controller 0 Interface Reset gpio_rst_n n Interrupt amp Manager Control Register Manager GPIO 28 0 pu 57 29 Interface GPIO 70 58 L4 Peripheral Bus Figure 6 2 Block diagram of GPIO Interface Cortex A9 Subsystem Core Generic Interrupt Controller gpioO Intr In DEO Nano SoC 54 www terasic com Tijasic User Manual April 2 2015 www terasic com JAN DTE RYA UNIVERSITY PROGRAM GPIO Register Block The behavior of I O pin 1s controlled by the registers 1n the registe
64. t USB Figure 3 2 Path of the JTAG chain B Configure the FPGA in JTAG Mode There are two devices FPGA and HPS on the JTAG chain The following shows how the FPGA 15 programmed in JTAG mode step by step Open the Quartus II programmer and click Auto Detect as circled In Figure 3 3 DEO Nano SoC 13 www terasic com Tijasic User Manual April 2 2015 www terasic com Search altera com a E Save File Ti up Jp Down Figure 3 3 Detect FPGA device in JTAG mode 2 Select detected device associated with the board as circled in Figure 3 4 Figure 3 4 Select 5CSEMA4 device DEO Nano SoC 14 www terasic com User Manual April 2 2015 www terasic com 3 Both FPGA and HPS are detected as shown in Figure 3 5 E Chain1 File Edit View Processing Tools Window Help Enable real time ISP to allow background programming when available Device Checksum Usercode Program Verify Blank peli Start Configure Check gt 5 00000000 lt none gt a 5CSEMA4 00000000 lt none gt m Delete Add File nu Change File Al Save File Down Figure 3 5 FPGA and HPS detected in Quartus programmer 4 Right click on the FPGA device and open the sof file to be programmed as highlighted in
65. t name in the circled area as shown in Figure 4 3 The project name typed in will be assigned automatically as the name of your top level design entity DEO Nano SoC 42 Tijasic User Manual www terasic com www terasic com April 2 2015 ANU RYAN UNIVERSITY PROGRAM DEO Nano SoC V1 0 0 gt ws System Configuration UNIVERSITY Project Name www Teresic com DEO Nano SoC FPGA Board CLOCK LED x8 7 Button x 2 Switch x 4 7 ADC 2x5 Header Arduino Header 5 0 Header Prefix Name GPIO 1 Header Prefix Name Load Setting Exit Figure 4 3 Enter the project name B System Configuration Users are given the flexibility in the System Configuration to include their choice of components in the project as shown in Figure 4 4 Each component onboard is listed and users can enable or disable one or more components at will If a component is enabled the DEO Nano SoC System Builder will automatically generate its associated pin assignment including the pin name pin location pin direction and I O standard DEO Nano SoC 43 www terasic com Tijasic User Manual April 2 2015 www terasic com ANU RYAN UNIVERSITY PROGRAM DEO Nano SoC V1 0 0 ha wa System Configuration U NIVE RSITY www Lterasic com Project Name PROGRA DE0_NANO_SOC DE0 Nano SoC FPGA Board
66. ted below 8 1 Before Programming Begins The FPGA should be set to AS mode i e MSEL 4 0 10010 to use the Flash as a FPGA configuration device as shown in Figure 8 1 5 P 2 1 WE 1 3 0 2 MSEL Figure 8 1 DIP switch SW10 setting of Active Serial AS mode DEO Nano SoC 67 www terasic com Tijasic User Manual April 2 2015 www terasic com 8 2 Convert SOF File to JIC File 1 Choose Convert Programming Files from the File menu of Quartus II as shown in Figure 8 2 New Project Wizard Open Project Save Project Close Project Save Save All File Properties Convert Programming Files Page Setup Figure 8 2 File menu of Quartus 2 Select JTAG Indirect Configuration File jic from the Programming file type field in the dialog of Convert Programming Files 3 Choose EPCS128 from the Configuration device field 4 Choose Active Serial from the Mode filed 5 Browse to the target directory from the File name field and specify the name of output file 6 Click on the SOF data in the section of Input files to convert as shown in Figure 8 3 DEO Nano SoC 68 www terasic com Tijasic User Manual April 2 2015 www terasic com Specify the input files to convert and the type of programming file to generate You can also import input file information from other files and save the conversion setup information created here for future use
67. ure FPGA End Figure 4 1 Design flow of building a project from the beginning to the end 4 3 Using DEO Nano SoC System Builder This section provides the procedures in details on how to use the DEO Nano SoC System Builder DEO Nano SoC 4 www terasic com Tijasic User Manual April 2 2015 www terasic com UNIVERSITY PROGRAM B Install and Launch the DE0 Nano SoC System Builder The DEO Nano SoC System Builder is located in the directory Tools SystemBuilder of the DEO Nano SoC System CD Users can copy the entire folder to a host computer without installing the utility A window will pop up as shown in Figure 4 2 after executing the DEO Nano SoC SystemBuilder exe on the host computer cm uw Www 7 w DEO Nano SoC V1 0 0 NB S RYAN System Configuration HARE Project Name DEO NANO SOC DEO Nano SoC FPGA Board E CLOCK V LED x8 www terasic com Button x 2 Switch x 4 ADC 2x5 Header 4 Arduino Header HPS GPIO 0 Header a TO f ater rata 24 L 2 1 23 I 4 A f uil ee To None M gt E Prefix Name GPIO 1 Header Prefix Name Load Setting Exit Figure 4 2 The GUI of DE0 Nano SoC System Builder B Enter Project Name Enter the projec

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