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Automotive 8-bit MCU, with up to 32 Kbytes Flash, data EEPROM

1. Table 13 General hardware register map continued Address Block Register label Register name iba 0x00 53E0 ADC DBORH ADC data buffer register 0 high 0x00 0x00 53E1 ADC DBORL ADC data buffer register 0 low 0x00 0x00 53E2 ADC DB1RH ADC data buffer register 1 high 0x00 0x00 53E3 ADC DBIRL ADC data buffer register 1 low 0x00 0x00 53E4 ADC DB2RH ADC data buffer register 2 high 0x00 0x00 53E5 ADC DB2RL ADC data buffer register 2 low 0x00 0x00 53E6 ADC DB3RH ADC data buffer register 3 high 0x00 0x00 53E7 ADC DB3RL ADC data buffer register 3 low 0x00 0x00 53E8 ADC DB4RH ADC data buffer register 4 high 0x00 0x00 53E9 ADC DB4RL ADC data buffer register 4 low 0x00 0x00 53EA pus ADC DB5RH ADC data buffer register 5 high 0x00 0x00 53EB ADC DB5RL ADC data buffer register 5 low 0x00 0x00 53EC ADC DB6RH ADC data buffer register 6 high 0x00 0x00 53ED ADC DB6RL ADC data buffer register 6 low 0x00 0x00 53EE ADC DB7RH ADC data buffer register 7 high 0x00 0x00 53EF ADC DB7RL ADC data buffer register 7 low 0x00 0x00 53F0 ADC _DB8RH ADC data buffer register 8 high 0x00 0x00 53F 1 ADC _DB8RL ADC data buffer register 8 low 0x00 0x00 53F2 ADC _DB9RH ADC data buffer register 9 high 0x00 0x00 53F3 ADC _DB9RL ADC data buffer register 9 low 0x00 sa Ee Reserved area 12 bytes 0x00 5400 ADC CSR ADC control status register 0x00 0x00 5401 ADC CR1 ADC configuration register 1 0x00 0x00 5402 ADC CR2 ADC configuration register 2 0x0
2. 10 3 3 HSE user external clock External clock sources and timing characteristics Subject to general operating conditions for Vpp and T4 Table 30 HSE user external clock characteristics Symbol Parameter Conditions Min Typ Max Unit f User external clock source TA is 40 to MHz HSE eX frequency 150 C VuseguL Comparator hysteresis V OSCIN input pin high level HSEH voltage V V OSCIN input pin low level HSEL voltage OSCIN input leakage ILEAK HSE current 2 9 Vss lt Vin lt Vpp 1 1 KA 1 In CSS is used the external clock must have a frequency above 500 kHz J DoclD14952 Rev 9 55 91 Electrical characteristics STM8AF61xx STM8AF62xx Figure 16 HSE external clock source fuse External clock source OSCIN OMI H STM8A HSE crystal ceramic resonator oscillator The HSE clock can be supplied using a crystal ceramic resonator oscillator of up to 16 MHz All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy Table 31 HSE oscillator characteristics
3. 1 Data based on characterization results not tested in production Absolute maximum ratings electrical sensitivity Based on two different tests ESD and LU using specific measurement methods the product is stressed to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic discharges 3 positive then 3 negative pulses separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin This test conforms to the JESD22 A114A A115A standard For more details refer to the application note AN1181 Table 46 ESD absolute maximum ratings T Maximum i Symbol Ratings Conditions Class 1 Unit value V Electrostatic discharge voltage Ta 25 C conforming to ESD HBM Human body model JESD22 A114 V Electrostatic discharge voltage Ta 25 C conforming to ESD CDM Charge device model JESD22 C101 V Electrostatic discharge voltage Ta 25 C conforming to ESD MM Machine model JESD22 A115 1 Data based on characterization results not tested in production d DoclD14952 Rev 9 73 91 Electrical characteristics STM8AF61xx STM8AF62xx 10 4 74 91 Static latch up Two complementary static tests are required on 10 parts to assess the latch up performan
4. Symbol Parameter Conditions Min Typ Max Unit Rp Feedback resistor 220 kQ C 4C Recommended load capacitance 20 pF Im Oscillator transconductance 5 mA V euer _ Startup time ae 2 8 ms 1 The oscillator needs two load capacitors C 4 and C 9 to act as load for the crystal The total load capacitance Cjgaq is Ci 4 C 2 C4 4 Cho If Cj 4 Cj o Cioag C14 2 Some oscillators have built in load capacitors C 4 and C 9 2 This value is the startup time measured from the moment it is enabled by software until a stabilized 16 MHz oscillation is reached It can vary with the crystal type that is used Figure 17 HSE oscillator circuit diagram fuse to core de R Co F Lm I C4 IC OSCIN ke ai L Sm Resonator Current control TI Resonator STM8A Ly 56 91 DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Electrical characteristics 10 3 4 d HSE oscillator critical gm formula The crystal characteristics have to be checked with the following formula Im Imerit where Gpmerit can be calculated with the crystal parameters as follows Imerit 2x Hx HSEY xR 2Co C Rm Notional resistance see crystal specification Lm Notional inductance see crystal specification Cm Notional capacitance see crystal specification Co Shunt capacitance see crystal specification C 4 C 2 C Grounded external
5. 2 asal akak akak aaa 48 10 2 Absolute maximum ratings 48 10 3 Operating conditions ixi tasse ikka Hua ukki kik Olek 50 10 3 4 VCAP external capacitor 52 10 3 2 Supply current characteristics 52 10 3 3 External clock sources and timing characteristics 55 10 3 4 Internal clock sources and timing characteristics 57 10 3 5 Memory characteristics ee 59 10 3 6 I O port pin characteristics 000 eee 60 DoclD14952 Rev 9 3 91 Contents 11 12 13 14 4 91 STM8AF61xx STM8AF62xx 10 3 7 Reset pin characteristics 0000 cee ees 64 10 3 8 TIM 1 2 3 and 4 timer specifications 66 10 3 9 SPI serial peripheral interface 66 10 3 10 12C interface characteristics 00 69 10 3 11 10 bit ADC characteristics 70 10 3 12 EMC characteristics 00200 72 10 4 Thermal characteristics rer ereeee 74 10 4 4 Reference document 75 10 4 2 Selecting the product temperature range 75 Package characteristics cece eee eee eee eee 76 11 1 Package mechanical data 77 Ordering information na 83 STM8 development tools 84 13 1 Emulation and in circuit debugging tools 84 13 1 4 STice key features 1 2 2 2 21 k v ad a ka eae 84 13 2 Software tools saak akak akka 85 13 2 1 STMB8 tool
6. Deviation error if automatic resynchronization is enabled Framing error in synch field or identifier field A Header time out d DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Product overview 5 10 J UART mode e Full duplex asynchronous communications NRZ standard format mark space e High precision baud rate generator Acommon programmable transmit and receive baud rates up to fyasteR 16 e Programmable data word length 8 or 9 bits 1 or 2 stop bits parity control e Separate enable bits for transmitter and receiver e Error detection flags e Reduced power consumption mode e Multi processor communication enter mute mode if address match does not occur e Wakeup from mute mode by idle line detection or address mark detection e Two receiver wakeup modes Address bit MSB Idle line input output specifications The product features four different I O types e Standard I O 2 MHz e Fast I O up to 10 MHz e High sink 8 MA 2 MHz e True open drain IC interface To decrease EMI electromagnetic interference high sink I Os have a limited maximum slew rate The rise and fall times are similar to those of standard I Os The analog inputs are equipped with a low leakage analog switch Additionally the schmitt trigger input stage on the analog I Os can be disabled in order to reduce the device standby consumption STMBA I Os are designed to withstand current injection For a negative injection
7. Table 3 STM8AF H61xx product line up SPI description in Features The typical and maximum values for trepp reset release delay in Table 24 Operating conditions at power up power down The symbol for NRST Input not filtered pulse duration in Table 38 NRST pin characteristics The address and comment of Reset interrupt in Table 16 STM8A interrupt table Added the three footnotes to Figure 42 VFOFPN 32 lead very thin fine pitch quad flat no lead package 5 x 5 18 Jul 2012 04 Apr 2014 Updated Table 32 HSI oscillator characteristics Added HSI accuracy and removed temperature range B in Figure 47 Ordering information scheme 24 Jun 2014 Updates in Table 32 HSI oscillator characteristics HSI oscillator accuracy factory calibrated values and Figure 47 Ordering information scheme changed the value for 1 12 Nov 2014 d DoclD14952 Rev 9 STM8AF61xx STM8AF62xx IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selectio
8. 59 Flash program Memory 1 0 ete 59 Data Memo ma unda l AN an le MALM ha 59 I O static characteristics 0c eee eee 60 NRST pin characteristics 64 TIM 1 2 3 and 4 electrical specifications sssssssss nes 66 SPI characteristics 66 C PHA EN Spe sara ah NA NAA NG ANNA IUS uia iuc Videt qu ata Rap ue 69 ADC characteristicS Jo sa rhe eu dee RO ERA EU eae le Pos ue prO FUR ORA e 70 ADC accuracy for Vppa 5 V 2 2 2 2 2 2 2 a a a a a a a ee 71 EMO dala aa a a ama le a L III a RES 72 EMI data AA 73 ESD absolute maximum rang 73 DoclD14952 Rev 9 5 91 List of tables STM8AF61xx STM8AF62xx Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 6 91 Electrical sensitivities 0 0 0 00 020 eh 74 Thermal characteristics 0c eee eee 75 VFQFPN 32 lead very thin fine pitch quad flat no lead package mechanical data 78 LQFP 48 pin low profile quad flat package mechanical data 79 LQFP 32 pin low profile quad flat package mechanical data 81 Document revision history s vk ba a s kk a a ll a a s aaa 87 DocID14952 Rev 9 Ly STM8AF61xx STM8AF62xx List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure
9. C W x 134 mW 82 C 6 C 88 C This is within the range of the suffix B version parts 40 lt T lt 105 C Parts must be ordered at least with the temperature range suffix B J DoclD14952 Rev 9 75 91 Package characteristics STM8AF61xx STM8AF62xx 11 76 91 Package characteristics In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark d DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Package characteristics 11 1 Package mechanical data In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACKA is an ST trademark DoclD14952 Rev 9 77191 J Package characteristics 78 91 STM8AF61xx STM8AF62xx Figure 42 VFQFPN 32 lead very thin fine pitch quad flat no lead package 5 x 5 Seating plane Bottom view 42 ME There is an exposed die pad on the underside of the VFQFPN package It is recommended to connect and solder this backside pad to PCB ground The drawing is not to scale 3 All leads pad
10. Digital ground Digital power supply O power supply 1 8 V regulator capacitor X Port F4 Analog input 12 X PortA3 Timer 2 channel 3 X Port A4 X Port A5 TIM3 CH1 AFR1 Analog power supply Analog ground DEEL X X Analog input 7 X Port B6 Analog input 6 01 2 C SDA 17 11 PB5 AIN5 vol x x lO1 X x Analog input 5 AFRE HHC SCL 18 12 PB4 AIN4 volx x x oil x x Analog input 4 AFRE 19 13 PB3 AIN3 wolx x x o1 x x Port B3 Analog input 3 MEE AFR5 TIM1 20 14 PB2 AIN2 wolx x x J o1 X x Port B2 Analog input NCC3 AFR5 26 91 DoclD14952 Rev 9 Ly STM8AF61xx STM8AF62xx Pinouts and pin description Table 10 STM8AF61xx 62xx 32 Kbytes microcontroller pin description continued Pin numbe Input Output r lt m 2 9 Alternate R g Default alternate function after Pin name gt 2 3 A o o Elo 2 lt 5 function remap wv we A Q lt sla ls elalal 355 option bit w z S e 2 Sona s Cla 9 5 95 0 br E G x ind ui gt TIM1_ 21 15 PB4 AIN1 wvolx x x lolx Analog input 1 NCC2 AFR5 TIM1_ JO X X X Analog input 0 NCC1 AFR5 22 16 PBO AINO 23 PE7 AIN8 1 O X 24 PEG AIN9 1 O X 25 17 PE5 SPI_NSS O X X Analog input 8 X Analog input 9
11. loal MAI Figure 31 Typ Vpp Vou Vpp 3 3 V high sink ports 40 C 25 C 85 C 1 5 125 C Von Vou IV ls MA 40 C 25 C 1 75 85 C 125 C Figure 32 Typ Vpp Vo Vpp 5 0 V high sink ports a 40 C 25 C 175 85 C 1 5 125 C 25 J DoclD14952 Rev 9 63 91 Electrical characteristics 10 3 7 64 91 Reset pin characteristics STM8AF61xx STM8AF62xx Subject to general operating conditions for Vpp and Ta unless otherwise specified Table 38 NRST pin characteristics 1 Data based on characterization results not tested in production 2 Data guaranteed by design not tested in production Figure 33 Typical NRST Vj and Vu vs Vpp four temperatures Symbol Parameter Conditions Min Typ Max Unit VIL NRST NRST input low level voltage Vss 0 3 x Vpp Vuen NRST input high level voltage 07xVpp Vpp Voumpsen NRST output low level voltage lo 2 3 mA 2 0 6 V Humpen NRST pull up resistor 30 40 60 kQ bes NRST input filtered pulse 85 315 ns NRST Input not filtered pulse INFP NRST duration P 500 ns Voo V DoclD14952 Rev 9 J STM8AF61xx STM8AF62xx J Electrical characteristics
12. 0x00 521C DC CCRH I2C clock control register high 0x00 0x00 521D I2C TRISER I2C TRISE register 0x02 Mul dus Reserved area 24 bytes 34 91 DoclD14952 Rev 9 d STM8AF61xx STM8AF62xx Memory and register map General hardware register map continued Address Register label Register name ee 0x00 5240 UART2_SR LINUART status register 0xCO 0x00 5241 UART2 DR LINUART data register OxXX 0x00 5242 UART2 BRR1 LINUART baud rate register 1 0x00 0x00 5243 UART2 BRR2 LINUART baud rate register 2 0x00 0x00 5244 NUART UART2_CR1 LINUART control register 1 0x00 0x00 5245 UART2_CR2 LINUART control register 2 0x00 0x00 5246 UART2 CR3 LINUART control register 3 0x00 0x00 5247 UART2 CR4 LINUART control register 4 0x00 0x00 5248 Reserved 0x00 5249 UART2 CR6 LINUART control register 6 0x00 pos pet Reserved area 6 bytes 0x00 5250 TIM1 CR1 TIM1 control register 1 0x00 0x00 5251 TIM1 CR2 TIM1 control register 2 0x00 0x00 5252 TIM1 SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1 ETR TIM1 external trigger register 0x00 0x00 5254 TIM1 IER TIM1 Interrupt enable register 0x00 0x00 5255 TIM1 SR1 TIM1 status register 1 0x00 0x00 5256 TIM1 SR2 TIM1 status register 2 0x00 0x00 5257 TIM1 EGR TIM1 event generation register 0x00 0x00 5258 TIM1 CCMR1 TIM1 capture compare mode register 1 0x00 0x00 5259 TIM1 CCMR2 TIM1 capture compare mode register 2 0x00 0x00 525A TIM1 C
13. Figure 34 Typical NRST pull up resistance Rpy vs Vpp 60 40 C 25 C E 55 85 C bi 125 C o 50 o 8 q Q g 45 a zi 5 40 a 35 30 2 5 3 3 5 4 4 5 5 5 6 Vop IVI Figure 35 Typical NRST pull up current 1 vs Vpp 140 120 S 100 5 80 o 2 60 40 C a b L25 C g 85 C 20 129 C 0 0 1 2 3 4 5 6 Voo VI The reset network shown in Figure 36 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below Vi ugs max see Table 38 NRST pin characteristics otherwise the reset is not taken into account internally Figure 36 Recommended reset pin protection External reset circuit optional Internal reset Filter DoclD14952 Rev 9 65 91 Electrical characteristics STM8AF61xx STM8AF62xx 10 3 8 TIM 1 2 3 and 4 timer specifications Subject to general operating conditions for Vpp fmaster and Ta unless otherwise specified Table 39 TIM 1 2 3 and 4 electrical specifications wee Paramor ems min wp vax un 1 Not tested in production On 64 Kbyte devices the frequency is limited to 16 MHz 10 3 9 SPI serial peripheral interface Unless otherwise specified the parameters given in Table 40 are derived from
14. STM8AF61xx STM8AF62xx Block diagram 4 d Block diagram Figure 1 STM8A block diagram Reset block lt XTAL 1 16 MHz Clock controller Reset CI lt RC int 16 MHz Detector RC int 128 kHz tyty Clock to peripherals and core Window WDG STM8A CORE IWDG Single wire debug interf Debug SWIM Up tana ca program Flash Master slave ji SUMANG ENBART Up to 1 Kbytes resynchronization 2 data EEPROM a D 400 Kbit s lt 5 Up to 2 Kbytes g RAM o 10 Mbit s lt TH 3 Boot ROM 16 bit advanced control 16 channels EE gt timer TIM1 Up to 9 CAPCOM 16 bit general purpose channels timers TIM2 TIM3 8 bit basic timer AWU timer e TIM4 1 Legend ADC Analog to digital converter beCAN Controller area network BOR Brownout reset IC Inter integrated circuit multimaster interface IWDG Independent window watchdog LINUART Local interconnect network universal asynchronous receiver transmitter POR Power on reset SPI Serial peripheral interface SWIM Single wire interface module USART Universal synchronous asynchronous receiver transmitter Window WDG Window watchdog DoclD14952 Rev 9 11 91 Product overview STM8AF61xx STM8AF62xx 5 5 1 12 91 Product overview This section is intended to describe the family features that are actually implemented in the products covered by this datasheet For more detailed information on each
15. production data LQFP48 7x7 mm LQFP32 7x7 mm VFQFPN32 5x5 mm Window and independent watchdog timers e Communication interfaces LINUART LIN 2 1 compliant master slave modes with automatic resynchronization SPI interface up to 8 Mbit s or fuAsTER 2 PC interface up to 400 Kbit s e Analog to digital converter ADC 10 bit accuracy 2LSB TUE accuracy 2LSB TUE linearity ADC and up to 10 multiplexed channels with individual data buffer Analog watchdog scan and continuous sampling mode e I Os Up to 38 user pins including 10 HS I Os Highly robust I O design immune against current injection e Operating temperature up to 150 C e Qualification conforms to AEC Q100 rev G Table 1 Device summary Reference Part number STM8AF624x STM8AF6246 STM8AF6248 STM8AF626x STM8AF6266 STM8AF6268 STM8AF6126 STM8AF6146 2 STM8AF6148 STM8AF612x 4x STM8AF616x STM8AF6166 2 STM8AF61689 1 In the order code F applies to devices with Flash program memory and data EEPROM while H refers to devices with Flash program memory only F is replaced by P for devices with FASTROM see Tables 2 and 3 and Figure 47 2 Notrecommended for new design 3 Obsolete products DoclD14952 Rev 9 1 91 www st com Contents STM8AF61xx STM8AF62xx Contents 1 Introduction Sie NAKAREG anda Su bee abet See kad sadada aaa a a 8 2 Description e nasv Vode ee eed edad e
16. 0x00 O9FFF J DoclD14952 Rev 9 STM8AF61xx STM8AF62xx 7 2 J Register map Memory and register map In this section the memory and register map of the devices covered by this datasheet is described For a detailed description of the functionality of the registers refer to the reference manual RM0016 Table 12 I O port hardware register map E 0x00 5000 PA ODR Port A data output latch register 0x00 0x00 5004 Port A control register 2 0x00 0x00 5005 Port B data output latch register 0x00 0x00 5006 Port B input pin value register 0xXX 1 0x00 5007 Port B Port B data direction register 0x00 0x00 500A Port C data output latch register 0x00 0x00 500B Port C input pin value register 0xXX 1 0x00 500C Port C Port C data direction register 0x00 0x00 500D Port C control register 1 0x00 0x00 5010 Port D input pin value register Oxxx 0x00 5011 Port D Port D data direction register 0x00 0x00 5012 Port D control register 1 0x02 0x00 5013 Port D control register 2 0x00 0x00 5016 Port E Port E data direction register 0x00 0x00 5017 Port E control register 1 0x00 0x00 5018 Port E control register 2 0x00 0x00 5019 Port F data output latch register 0x00 0x00 501C PF CR1 Port F control register 1 0x00 0x00 501D PF CR2 Port F control register 2 0x00 DoclD14952 Rev 9 31 91 Memory and register map STM8AF61xx STM8AF62xx Table
17. 12 I O port hardware register map continued Address Block Register label Register name KR tl status 0x00 501E Port G data output latch register 0x00 0x00 501F Port G input pin value register Oxxx 0x00 5020 Port G Port G data direction register 0x00 0x00 5021 PG_CR1 Port G control register 1 0x00 0x00 5022 PG_CR2 Port G control register 2 0x00 1 Depends on the external circuitry Table 13 General hardware register map Address Block Register label Register name Reset status 0x00 505A FLASH CR1 Flash control register 1 0x00 0x00 505B FLASH CR2 Flash control register 2 0x00 0x00 505C FLASH NCR2 Flash complementary control register 2 OxFF 0x00 505D Flash FLASH FPR Flash protection register 0x00 0x00 505E FLASH NFPR Flash complementary protection OxFF m register 0x00 505F FLASH IAPSR Flash in application programming 0x40 status register 0x00 5060 to 0x00 5061 Reserved area 2 bytes 0x00 5062 Flash FLASH_PUKR Flash Program memory unprotection 0x00 register 0x00 5063 Reserved area 1 byte 0x00 5064 Flash FLASH_DUKR Data EEPROM unprotection register 0x00 0x00 5065 to 0x00 509F Reserved area 59 bytes 0x00 50A0 EXTI CR1 External interrupt control register 1 0x00 ITC 0x00 50A1 EXTI CR2 External interrupt control register 2 0x00 0x00 50A2 to 0x00 50B2 Reserved area 17 bytes 0x00 50B3 RST RST SR Reset status register 0xxx 0x00 50B4 to 0
18. 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Ly STMBA block diagram ENEE ssaa de m n pd E Rn RR OR a RUE cR ee 11 Flash memory organization of STM8A products 000 eee ees 14 VFQFPN LQFP 32 pin pinout 2 0000 eee 24 LOFP 48 pinplnout sf aine ee dd ee FCRC RR ERR Eee eG wad Pee eR ERU QR UR a 25 Register and memory map of STM8A products 00 eee ees 30 Pin loading conditions deupa K Kar DK eens 47 Pin input Voltage 0 2 paa ma e mma hala liiast A OR E ed ea 48 fcPUmax VETSUS Von 51 External capacitor Cer 52 Typ IDD RUN HSE VS VDD fcpu 16 MHz peripheral ON Ars ING Selatan hee ise cae 54 Typ IDD RUN HSE VS fopy VDD 5 0V peripheral SION er tg uu Imi ate hes qd BS ip ne cesa 54 Typ IDD RUN HSI VS VDD fopy 16 MHz peripheral Olt mm kak 55 Typ IDD WFI HSE VS Vpp fopy 16 MHz peripheral Ii 55 Typ IDD WFI HSE VS fcpu Vpp 5 0V peripheral EOD dag eere o Cal RO uo ea c 55 Typ IDD WFDHSI VS Vpp fcpu 16 MHz peripheral TOM we Aus Veces e NAN NGA DA 55 HSE external clock source 56 HSE oscillator circuit diagram llle 56 Typical HSI frequency vs Men 58 Typical LSI frequency
19. O X X X HS X 1 O X X X HS X Port D3 PD4 TIM2 CH1 Timer 2 channel 2 ADC ETR AFRO BEEP output Port D4 Timer 2 channel 1 AFR7 LINUART data transmit PD6 LINUART RX 47 31 X X X X 1 O X X Port D6 1 Referto Table 9 for the definition of the abbreviations Reset state is shown in bold In Halt Active halt mode this pad behaves in the following way the input output path is disabled ifthe HSE clock is used for wakeup the internal weak pull up is disabled ifthe HSE clock is off internal weak pull up setting from corresponding OR bit is used By managing the OR bit correctly it must be ensured that the pad is not left floating during Halt Active halt LINUART data receive s is x x X 0 XXPenor Hopton 4 On this pin a pull up resistor as specified in Table 37 I O static characteristics is enabled during the reset phase of the product 5 AIN12 is not selectable in ADC scan mode or with analog watchdog In the open drain output column T defines a true open drain I O P buffer week pull up and protection diode to Vpp are not implemented 7 The PD1 pin is in input pull up during the reset phase and after reset release If this pin is configured as interrupt pin it will trigger the TLI 28 91 DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Pinouts and pin description 6 2 d Alternate function remapping A
20. SPH Stack pointer high 0x17 0x00 7F09 SPL Stack pointer low OxFF 0x00 7F0A CC Condition code register 0x28 ndi Reserved area 85 bytes 0x007F60 CPU CFG GER 0x00 0x00 7F70 ITC SPR1 Interrupt software priority register 1 OxFF 0x00 7F71 ITC SPR2 Interrupt software priority register 2 OxFF 0x00 7F72 ITC SPR3 Interrupt software priority register 3 OxFF 0x00 7F73 ITC SPR4 Interrupt software priority register 4 OxFF 0x00 7F74 ITC SPR5 0x00 7F75 ITC SPR6 Interrupt software priority register 6 OxFF Interrupt software priority register 5 OxFF 0x00 7F76 to 0x00 7F79 Reserved area 4 bytes 0x00 7F80 SWIM SWIM CSR SWIM control status register 0x00 Ly DoclD14952 Rev 9 39 91 Memory and register map STM8AF61xx STM8AF62xx Table 14 CPU SWIM debug module interrupt controller registers continued Address Block Register label Register name bagi yore dd Reserved area 15 bytes 0x00 7F90 DM BK1RE DM breakpoint 1 register extended byte OxFF 0x00 7F91 DM BK1RH OxFF 0x00 7F92 DM BKIRL OxFF 0x00 7F93 DM BK2RE DM breakpoint 2 register extended byte OxFF 0x00 7F94 DM BK2RH DM breakpoint 2 register high byte OxFF 0x00 7F95 DM DM BK2RL DM breakpoint 2 register low byte OxFF 0x00 7F96 DM CR1 DM debug module control register 1 0x00 0x00 7F98 DM CSR1 0x10 0x00 7F99 DM_CSR2 DM debug module control status register 2 0x00 0x00 7F9A DM_ENFCTR DM en
21. SPI master slave select X T io x x x es 0 x peser jai amit Z rf x xs X EST EE 28 20 PC3 TIM1 CH3 l O X X Timer 1 channel 3 29 21 PC4 TIM1_CH4 l O X X X HS O3 X Timer 1 channel 4 30 22 PC5 SPI SCK VO X X X O3 X SPI clock Vssio 2 I O ground 31 S Bo Ae X X 03 33 23 PC6 SPI MOSI I O X SPI master out slave in 34 24 PC7 SPI MISO 35 PGO 1 O X 1 O X 1 O X PG1 37 SET uo ESESESEIGJEJES Port E3 Timer 1 break input a peresoa hofa fe oe x lt x lt SPI master in slave out X X 39 PEUPG SCL O X 01 T Port E1 me 40 PEUCLK cco 1 o X x x 03 x X Port EO ao J DoclD14952 Rev 9 27191 Pinouts and pin description STM8AF61xx STM8AF62xx Table 10 STM8AF61xx 62xx 32 Kbytes microcontroller pin description 2 continued 41 43 27 PD2 TIM3 CH1 UO Ew 7 ZE Pin numbe Input Output r c SF N e 2 M e A Pin name c 2 v Fia T O EG E ET c J Ei 3 o gt 5 BII SIS E SS Cla o E D er J L s G x I ui gt Default alternate function Timer 3 channel 2 Timer 3 channel 1 Alternate function after remap option bit TIM1 BKIN AFR3 CLK CCO AFR2 Port D1 SWIM data interface TIM2 CH AFR1 44 28 PD3 TIM2 CH2 PD5 DES LINUART TX 1
22. Table 18 Option byte description continued Option byte no OPT3 OPT4 OPT5 OPT6 OPT7 Description HSITRIM Trimming option for 16 MHz internal RC oscillator 0 3 bit on the fly trimming compatible with devices based on the 128K silicon 1 4 bit on the fly trimming LSI EN Low speed internal clock enable 0 LSI clock is not available as CPU clock source 1 LSI clock is available as CPU clock source IWDG HW Independent watchdog 0 IWDG independent watchdog activated by software 1 IWDG independent watchdog activated by hardware WWDG HW Window watchdog activation 0 WWDG window watchdog activated by software 1 WWDG window watchdog activated by hardware WWDG HALT Window watchdog reset on Halt 0 No reset generated on Halt if WWDG active 1 Reset generated on Halt if WWDG active EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN CKAWUSEL Auto wakeup unit clock 0 LSI clock source selected for AWU 1 HSE clock with prescaler selected as clock source for AWU PRSC 1 0 AWU clock prescaler 00 Reserved 01 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to 128 kHz prescaler HSECNT 7 0 HSE crystal oscillator stabilization time This configures the stabilization time to 0 5 8 128 and 2048 HSE cycles with corresponding option byte values of 0xE1 OxD2 0xB4 and 0x00 TMU 3 0 Enable temporary mem
23. capacitance Internal clock sources and timing characteristics Subject to general operating conditions for Vpp and Ta High speed internal RC oscillator HSI Table 32 HSI oscillator characteristics Symbol Parameter Conditions Min Unit fusi Frequency MHz P e x 40 met gillal rk ssr Trimmed by the application 1 trimming accurac for any Vpp and Ta 1 9 y conditions 0 5 ACCus 3 0 V lt Vpp lt 5 5 V 5 HSI oscillator accuracy 740 C lt Ta 150 C factory calibrated 3 0V lt Vpp lt 5 5V 252 40 C x Tas 125 C t HSI oscillator wakeup su HSI time HS 1 Depending on option byte setting OPT3 and NOPT3 2 These values are guaranteed for STM8AF62x6ITx order codes only 3 Guaranteed by characterization not tested in production DoclD14952 Rev 9 57 91 Electrical characteristics STM8AF61xx STM8AF62xx 58 91 Figure 18 Typical HSI frequency vs Vpp 3 40 C 2 m 25 C 85 C 125 C 0 r s p Ia 1 4 1 HSI frequency variation 2 3 T T T T T J 2 5 3 3 5 4 4 5 5 5 5 6 Vo V Low speed internal RC oscillator LSI Subject to general operating conditions for Vpp and Ta Table 33 LSI oscillator characteristics sis nee conattons un tm war un Xs Fa i eee oe kam ota 5 1 Data based on characterization results not tested in production Figure 19 Ty
24. characteristics 1 v v va H ald n t n D LS b mb V Rl GR R SR RRR RR 71 VFQFPN 32 lead very thin fine pitch quad flat no lead package 5 x 5 78 LQFP 48 pin low profile quad flat package ix 79 LQFP 48 pin recommended footprint aaae eee 80 LQFP 32 pin low profile quad flat package ix 81 LQFP 32 pin recommended footprint ee 82 Ordering information scheme amaan Sie 83 DoclD14952 Rev 9 7191 Introduction STM8AF61xx STM8AF62xx 8 91 Introduction This datasheet refers to the STM8AF61xx STM8AF612x STM8AF6 14x STM8AF6166 and STM8AF6168 and STM8AF62xx products with 16 to 32 Kbytes of Flash program memory In the order code the letter F refers to product versions with data EEPROM and H refers to product versions without data EEPROM The identifiers F and H do not coexist in a given order code The datasheet contains the description of family features pinout electrical characteristics mechanical data and ordering information e For complete information on the STM8A microcontroller memory registers and peripherals please refer to STM8S and STM8A microcontroller families reference manual RM0016 e For information on programming erasing and protection of the internal Flash memory please refer to the STM8 Flash programming manual PM0051 e For information on the debug and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual
25. clock output CCO This feature permits to outputs a clock signal for use by the application 16 MHz high speed internal RC oscillator HSI e Default clock after reset 2 MHz 16 MHz 8 e Fast wakeup time User trimming The register CLK_HSITRIMR with three trimming bits plus one additional bit for the sign permits frequency tuning by the application program The adjustment range covers all possible frequency variations versus supply voltage and temperature This trimming does not change the initial production setting For reason of compatibility with other devices from the STM8A family a special mode with only two trimming bits plus sign can be selected This selection is controlled with the HSITRIMO bit in the option byte registers OPT3 and NOPT3 DoclD14952 Rev 9 15 91 Product overview STM8AF61xx STM8AF62xx 5 5 3 5 5 4 5 5 5 5 5 6 16 91 128 kHz low speed internal RC oscillator LSI The frequency of this clock is 128 kHz and it is independent from the main clock It drives the independent watchdog or the AWU wakeup timer In systems which do not need independent clock sources for the watchdog counters the 128 kHz signal can be used as the system clock This configuration has to be enabled by setting an option byte OPT3 OPT3N bit LSI EN 16 MHz high speed external crystal oscillator HSE The external high speed crystal oscillator can be selected to deliver the main clock in normal Run mode It operates wit
26. ek k 17 5 7 1 Watchdog timers sanaa 0 kn eh 17 5 7 2 Auto wakeup counter nsa eee eee eee 18 5 7 3 Beeper ves DEAN RU RUN a RU eee ING 18 2 91 DoclD14952 Rev 9 Ly STM8AF61xx STM8AF62xx Contents 10 J 5 7 4 Advanced control and general purpose timers 18 5 7 5 Basic Umer uses Vis atkal BM eh ea pa P n rr 19 5 8 X Analog to digital converter ADC 22 llu 20 5 9 Communication interfaces r r ree 20 5 9 1 Serial peripheral interface SPI r rea 21 5 9 2 Inter integrated circuit I C Interface oboe h ma de hasan TES 21 5 9 3 Universal asynchronous receiver transmitter with LIN support LINUART i2 3 baa s sat det peta iod were a nde dates 22 5 10 Input output specifications 23 Pinouts and pin description nnnenne 24 6 1 Package pinouts 0 00 ees 24 6 2 Alternate function remapping 29 Memory and register map 30 7 1 Memory map 30 1 2 Register Map ses nak dat SoRS sk kukk Pek k ana d k RK ER 31 Interrupt Table saagas osak va 54 saapa anarka a aed SY skat a 41 Option bytes saan Sr NNN Ali la rr EN SNE EN a RE 42 Electrical characteristics llle 47 10 1 Parameter conditions 47 10 1 1 Minimum and maximum values 47 10 1 2 Typical values inc RR ahead ete Mie PN TAE ENG NG 47 10 4 3 Typicalcurves RR III 47 10 1 4 Loading capacitor 47 10 1 5 Pin input voltage
27. feature please refer to the STM8S and STM8A microcontroller families reference manual RM0016 STMB8A central processing unit CPU The 8 bit STM8A core is a modern CISC core and has been designed for code efficiency and performance It contains 21 internal registers six directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e Harvard architecture e 3 stage pipeline e 32 bit wide program memory bus with single cycle fetching for most instructions e XandY 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations e 8 bit accumulator e 24 bit program counter with 16 Mbyte linear memory space e 16 bit stack pointer with access to a 64 Kbyte stack e 8 bit condition code register with seven condition flags for the result of the last instruction Addressing e 20 addressing modes es Indexed indirect addressing mode for look up tables located anywhere in the address space e Stack pointer relative addressing mode for efficient implementation of local variables and parameter passing Instruction set e 80 instructions with 2 byte average instruction size e Standard data movement and logic arithmetic functions e 8 bit by 8 bit multiplication e 16 bit by 8 bit and 16 bit by 16 bit division e Bit manipulation e Data transfer between stack and acc
28. tests performed under ambient temperature fyaster frequency and Vpp supply voltage conditions tMASTER V MASTER Refer to I O port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 40 SPI characteristics Symbol Parameter Conditions Min Max Unit Master mode 0 10 fsck SPI clock frequency Vpp 4 5 V 0 6 1 MHz Vt SCK Slave mode Vpp 4 5 V to 5 5 V 0 e tsok SPI clock rise and fall time Capacitive load C 30 pF 25 2 f SCK tsuNss NSS setup time Slave mode 4 tMASTER tnNss NSS hold time Slave mode 70 8 3 AO SCK high and low time Master mode tsck 2 15 tsck 2 15 w SCKL t 3 Master mode 5 su Ml Data input setup time tsu S1 Slave mode 5 3 Master mode 7 thm Data input hold time ns tn si Slave mode 10 so DO Data output access time Slave mode 3 MASTER tdissoy 0 Data output disable time Slave mode 25 Von lt 4 5 V 75 tuso Data output valid time a ders d ld after enable edge 4 5 V to 5 5 V 53 two Data output valid time Master mode after enable edge 30 t 3 Slave mode after enable edge 31 ae Data output hold time tr mo Master mode after enable edge 12 1 fsck lt fmasteR 2 2 The pad has to be configured accordingly fast mode 66 91 J DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Electrical characteristics Values based on design simulation and or ch
29. th MO gt ai14136 1 Measurement points are at CMOS levels 0 3 Vpp and 0 7 Vpp d 68 91 DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Electrical characteristics 10 3 10 PC interface characteristics Table 41 12C characteristics Standard mode PC Fast mode 12c Symbol Parameter A 2 PC EKTA HER twScLH SCL clock high time 4 0 tsu SDA SDA setup time tn SDA SDA data hold time 043 t SDA SDA and SCL rise time 1000 trscL Vpp 3 to 5 5 V tysDA SDA and SCL fall time trscL Vpp 3 to 5 5 V th STA START condition hold time tsu STA Repeated START condition setup time tsu STO STOP condition setup time Capacitive load for each bus line 400 pF faster must be at least 8 MHz to achieve max fast DC speed 400 kHz 2 Data based on standard BC protocol requirement not tested in production The maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL J DoclD14952 Rev 9 69 91 Electrical characteristics STM8AF61xx STM8AF62xx 10 3 11 10 bit ADC characteristics Subject to general operating conditions for Vppa faster and Ta unless otherwise specified Table 42 ADC characteristics S
30. vs Vpp sesse re 58 Typical Vj and Vip vs Vpp four temperatures 00 000 000000 61 Typical pull up resistance Rpy vs Vpp four temperatures 61 Typical pull up current lp vs Vpp four temperatures eee eee 62 Typ Vor Vpp 3 3 V standard porte 62 Typ Vor Vpp 5 0 V standard porte 62 Typ Vol Vpp 3 3 V true open drain ports 00 0000 22 eee 62 Typ Vor Vpp 5 0 V true open drain ports 00 00 02 62 Typ Vor Vpp 3 3 V high sink ports ee 63 Typ Vor Vpp 5 0 V high sink ports ee 63 Typ Vpp Vou Vpp 3 3 V standard ports 63 Typ Vpp Von Vpp 5 0 V standard ports 63 Typ Vpp Von Vpp 3 3 V high sink ports e 63 Typ Vpp Von Vpop 5 0 V high sink ports 63 Typical NRST Vj and Vj vs Vpp four temperatures 0 64 Typical NRST pull up resistance Rpy ve Von 65 Typical NRST pull up current lp vs VDD sssseee eee eee 65 Recommended reset pin protection 00 000 cee eee 65 SPI timing diagram where slave mode and CPHA Q 2 2222 eee kana 67 SPI timing diagram where slave mode and CPHA 1 67 SPI timing diagram master mode s sssss sasa aaa aaa 68 Typical application with ADC 0000 eee eee 70 ADC accuracy
31. 0 0x00 5403 ADC CR3 ADC configuration register 3 0x00 0x00 5404 ADC DRH ADC data register high OxXX 0x00 5405 ADC DRL ADC data register low OxXX 0x00 5406 ADS ADC_TDRH ADC Schmitt R disable register 0x00 0x00 5407 ADC_TDRL ADC Schmitt ok disable register 0x00 0x00 5408 ADC HTRH ADC high threshold register high OxFF 0x00 5409 ADC HTRL ADC high threshold register low 0x03 0x00 540A ADC LTRH ADC low threshold register high 0x00 38 91 DoclD14952 Rev 9 J STM8AF61xx STM8AF62xx Memory and register map Table 13 General hardware register map continued Address Block Register label Register name esq 0x00 540B ADC LTRL ADC low threshold register low 0x00 0x00 540C ADC AWSRH ADC watchdog status register high 0x00 0x00 540D ADC ADC AWSRL ADC watchdog status register low 0x00 0x00 540E ADC AWCRH ADC watchdog control register high 0x00 0x00 540F ADC AWCRH ADC watchdog control register low 0x00 seda SC Reserved area 16 bytes 1 Depends on the previous reset source 2 Write only register Table 14 CPU SWIM debug module interrupt controller registers Address Block Register label Register name Reset status 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x80 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 CPU XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F08
32. 14952 Rev 9 81 91 Package characteristics STM8AF61xx STM8AF62xx Figure 46 LQFP 32 pin recommended footprint 9 40 oo OO 7 70 en lt OOOOOOUOU 1 0 54 OOOGOUOOUL DUDU JOOU 3 J 0 80 5V FP 1 Drawing is not to scale Dimensions are in millimeters d 82 91 DoclD14952 Rev 9 STM8AF61xx STM8AF62xx 12 d Ordering information Ordering information Figure 47 Ordering information scheme Example STM8A F 62 Product class 8 bit automotive microcontroller Program memory type F Flash EEPROM P FASTROM H Flash no EEPROM Device family 61 Silicon rev Y LIN only 62 Silicon rev X and rev W LIN only Program memory size 6 6 T D xxx 2 v 2 8 Kbytes 4 16 Kbytes 6 32 Kbytes Pin count 6 32 pins 8 48 pins HSI accuracy Blank 5 Yo 1522 5 Yo Package type T LQFP U VFQFPN Temperature range A 40 to 85 C C 40 to 125 C D 40 to 150 C 4 Packing Y Tray U Tube X 7 Tape and reel compliant with EIA 481 C For a list of available options e g memory size package and orderable part numbers or for further information on any aspect of this device please go to www st com or contact the ST Sales Office nearest to you Customer specific FASTROM code or custom device configuration This field shows SSS if the device contains a super set silicon usually equi
33. CMR3 TIM1 capture compare mode register 3 0x00 0x00 525B TIM1 CCMRA TIM1 capture compare mode register 4 0x00 0x00 525C TIM1 CCER1 TIM1 OI e enable register 0x00 0x00 525D TIM1 CCER2 TIM1 n enable register 0x00 0x00 525E TIM1_CNTRH TIM1 counter high 0x00 0x00 525F TIM1_CNTRL TIM1 counter low 0x00 0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1 PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1 ARRH TIM1 auto reload register high OxFF 0x00 5263 TIM1 ARRL TIM1 auto reload register low OxFF 0x00 5264 TIM1 RCR TIM1 repetition counter register 0x00 er DoclD14952 Rev 9 35 91 STM8AF61xx STM8AF62xx Memory and register map 36 91 Table 13 General hardware register map continued Address Block Register label Register name iba 0x00 5265 TIM1 CCR1H TIM1 capture compare register 1 high Ox00 0x00 5266 TIM1 CCRIL TIM1 capture compare register 1 low 0x00 0x00 5267 TIM1 CCR2H TIM1 capture compare register 2 high 0x00 0x00 5268 TIM1 CCR2L TIM1 capture compare register 2 low 0x00 0x00 5269 TIM1 CCR3H TIM1 capture compare register 3 high 0x00 0x00 526A TIM1 TIM1 CCR3L TIM1 capture compare register 3 low 0x00 0x00 526B TIM1 CCR4H TIM1 capture compare register 4 high 0x00 0x00 526C TIM1 CCRAL TIM1 capture compare register 4 low 0x00 0x00 526D TIM1 BKR TIM1 break register 0x00 0x00 526E TIM1 DTR TIM1 dead time register 0x00 0x00 526F TIM1 OISR TIM1 output idle state r
34. Hx and TIMn CHxN respectively Section 7 2 Register map Replaced tables describing register maps and reset values for non volatile memory global configuration reset status clock controller interrupt controller timers communication interfaces and ADC by Table 13 General hardware register map Added Note 1 for Px IDR registers in Table 12 O port hardware register map Updated register reset values for Px IDR registers Added SWIM and debug module register map J DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Revision history Table 52 Document revision history continued Date Revision Changes Renamed Fast Active Halt mode to Active halt mode with regulator on and Slow Active Halt mode to Active halt mode with regulator off Updated Table 26 Total current consumption in Halt and Active halt modes General conditions for Vpp apply Ta 40 to 55 C in particular IDD FAH and IDD SAH renamed IDD AH twu FAH and twu sAH renamed tyyu aHy and temperature condition added Removed Ipp usarr from Table 29 Typical peripheral current consumption Vpp 9 0 V Updated general conditions in Section 10 3 5 Memory characteristics Modified Tyyg maximum value in Table 35 Flash program memory and Table 36 Data memory Update liq ana maximum value for T4 ranging from 40 to 150 C in Table 37 I O static characteristics Added tjp nRsT and renamed Vre ygsr tipp in Table 38 NRST pin characteristics Added recommenda
35. OPT6 NOPT6 option bytes Clock controller The clock controller distributes the system clock coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features e Clock sources 16 MHz high speed internal RC oscillator HSI 128 kHz low speed internal RC LSI 1 16 MHz high speed external crystal HSE Up to 16 MHz high speed user external clock HSE user ext e Reset After reset the microcontroller restarts by default with an internal 2 MHz clock 16 MHz 8 The clock source and speed can be changed by the application program as soon as the code execution starts e Safe clock switching Clock sources can be changed safely on the fly in Run mode through a configuration register The clock signal is not switched until the new clock source is ready The design guarantees glitch free switching e Clock management To reduce power consumption the clock controller can stop the clock to the core or individual peripherals e Wakeup In case the device wakes up from low power modes the internal RC oscillator 16 MHz 8 is used for quick startup After a stabilization time the device switches to the clock source that was selected before Halt mode was entered e Clock security system CSS The CSS permits monitoring of external clock sources and automatic switching to the internal RC 16 MHz 8 in case of a clock failure e Configurable main
36. Table 37 I O static characteristics added new condition and new max values for rise and fall time updated footnote 2 18 Jul 2012 J DoclD14952 Rev 9 89 91 Revision history STM8AF61xx STM8AF62xx 90 91 Table 52 Document revision history continued Date Revision Changes Section 10 3 7 Reset pin characteristics updated text below Figure 35 Typical NRST pull up current ly vs Von Figure 36 Recommended reset pin protection updated unit of capacitor Table 40 SPI characteristics updated SCK high and low time conditions and values Figure 39 SPI timing diagram master mode replaced SCK input signals with SCK output signals Updated Table 49 VFOFPN 32 lead very thin fine pitch quad flat no 6 lead package mechanical data Table 50 LQFP 48 pin low profile continued quad flat package mechanical data and Table 51 LQFP 32 pin low profile quad flat package mechanical data Replaced Figure 43 LQFP 48 pin low profile quad flat package 7 x 7 and Figure 45 LQFP 32 pin low profile quad flat package 7 x 7 Added Figure 44 LOFP 48 pin recommended footprint and Figure 46 LQFP 32 pin recommended footprint Figure 47 Ordering information scheme added footnote 1 added xxx and footnote 2 updated example and device family added FASTROM Section 13 2 2 C and assembly toolchains added www iar com Updated Table 1 Device summary Table 2 STM8AF62xx product line up
37. UM0470 e For information on the STM6 core please refer to the STM8 CPU programming manual PM0044 d DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Description 2 J Description The STM8AF61xx and STM8AF62xx automotive 8 bit microcontrollers offer from 16 to 32 Kbytes of Flash program memory and integrated true data EEPROM They are referred to as medium density STM8A devices in the STM8S and STM8A microcontroller families reference manual RM0016 All devices of the STM8A product line provide the following benefits reduced system cost performance and robustness short development cycles and product longevity The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k write erase cycles and a high system integration level with internal clock oscillators watchdog and brown out reset Device performance is ensured by a clock frequency of up to 16 MHz CPU and enhanced characteristics which include robust I O independent watchdogs with a separate clock source and a clock security system Short development cycles are guaranteed due to application scalability across a common family product architecture with compatible pinout memory map and and modular peripherals Full documentation is offered with a wide choice of development tools Product longevity is ensured in the STM8A family thanks to their advanced core which is made in a state of the art technology for automotive applications with 3 3 V to 5
38. V operating supply All STM8A and ST7 microcontrollers are supported by the same tools including STVD STVP development environment the STice emulator and a low cost third party in circuit debugging tool DoclD14952 Rev 9 9 91 Product line up STM8AF61xx STM8AF62xx 3 Product line up Table 2 STM8AF62xx product line up Medium density UO Order code Package Flash RAM Data EE 10 bit Timers Serial w ksu ge program bytes bytes A D ch IC OC PWM interfaces Vi memory p bytes STM8AF P6268 1x8 bit TIM4 LQFP48 3x16 bit TIM1 LIN UART 20135 STM8AF P6248 7x7 TIM2 TIM3 SPI IC 9 9 9 STM8AF P6266 1x8 bit TIM4 LQFP32 3x16 bit TIM1 LIN UART 25 93 STMBAF P6246 7X7 TIM2 TIM3 SPI 12C 8 8 8 STMB8AF P6266 1x8 bit TIM4 3x16 bit TIM1 LIN UART STMBAFIP6246 O ANO TIM2 TIRIS spec BB 8 8 8 Medium density O Order code Packade Flash RAM Data EE 10 bit Timers Serial wake 9 program bytes bytes A D ch ICJOC PWM interfaces eg memory p bytes STMBAF H P6168 1 1x8 bit TIM4 LQFP48 3x16 bit TIM1 LIN UART 29 95 sTM8AF H Pe148 0 7x7 e TIM2 TIM3 SPI PC 9 9 9 STMB8AF H P6166 1x8 bit TIM4 LQFP32 3x16 bit TIM1 LIN UART STMB8AF H P6146 7x7 TIM2 TIM3 SPI PC 25 23 STMB8AF H P6126 8 8 8 1 Obsolete products 2 Notrecommended for new design 10 91 DoclD14952 Rev 9 Ly
39. VD provides seamless integration of the Cosmic and Raisonance C compilers for STM8 STM8 toolset The STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www st com This package includes ST visual develop Full featured integrated development environment from STMicroelectronics featuring e Seamless integration of C and ASM toolsets e Full featured debugger e Project management e Syntax highlighting editor e Integrated programming interface e Support of advanced emulation features for STice such as code profiling and coverage ST visual programmer STVP Easy to use unlimited graphical interface allowing read write and verification of the STM8A microcontroller s Flash memory STVP also offers project mode for saving programming configurations and automating programming sequences C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of your application directly from an easy to use graphical interface Available toolchains include C compiler for STM8 All compilers are available in free version with a limited code size depending on the compiler For more information refer to www cosmic software com www raisonance com and www iar com STM8 assembler linker Free assembly toolchain included in the STM8 tool
40. WU control status register 1 0x00 0x00 50F1 AWU AWU APR AWU asynchronous prescaler buffer Ox3F register 0x00 50F2 AWU TBR AWU timebase selection register 0x00 0x00 50F3 BEEP BEEP CSR BEEP control status register Ox1F 0x00 50F4 to 0x00 50FF Reserved area 12 bytes ky DoclD14952 Rev 9 33 91 Memory and register map STM8AF61xx STM8AF62xx Table 13 General hardware register map continued Address Block Register label Register name esq 0x00 5200 SPI CR1 SPI control register 1 0x00 0x00 5201 SPI CR2 SPI control register 2 0x00 0x00 5202 SPI ICR SPI interrupt control register 0x00 0x00 5203 SPI SR SPI status register 0x02 0x00 5204 ka SPI DR SPI data register Ox00 0x00 5205 SPI CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI RXCRCR SPI Rx CRC register OxFF 0x00 5207 SPI TXCRCR SPI Tx CRC register OxFF e SE Reserved area 8 bytes 0x00 5210 I2C_CR1 I2C control register 1 0x00 0x00 5211 I2C_CR2 I2C control register 2 0x00 0x00 5212 I2C FREQR I2C frequency register 0x00 0x00 5213 DC OARL I2C own address register low 0x00 0x00 5214 I2C OARH I2C own address register high 0x00 0x00 5215 Reserved area 1 byte 0x00 5216 DC DR I2C data register 0x00 0x00 5217 e DC SR1 I2C status register 1 0x00 0x00 5218 DC SR2 I2C status register 2 0x00 0x00 5219 I2C_SR3 I2C status register 3 0x00 0x00 521A I2C_ITR I2C interrupt control register 0x00 0x00 521B I2C_CCRL I2C clock control register low 0x00
41. able function register OxFF pu dus Reserved area 5 bytes 1 Accessible by debug module only 2 Product dependent value see Figure 5 Register and memory map of STM8A products Table 15 Temporary memory unprotection registers Address Block Register label Register name eas 0x00 5800 Temporary memory unprotection key register 1 0x00 0x00 5801 Temporary memory unprotection key register 2 0x00 0x00 5802 Temporary memory unprotection key register 3 0x00 0x00 5803 Temporary memory unprotection key register 4 0x00 0x00 5804 Temporary memory unprotection key register 5 0x00 0x00 5805 Temporary memory unprotection key register 6 0x00 0x00 5806 Temporary memory unprotection key register 7 0x00 0x00 5807 TMU_K8 Temporary memory unprotection key register 8 0x00 0x00 5808 TMU_CSR Temporary memory SE control and status 0x00 40 91 DoclD14952 Rev 9 er STM8AF61xx STM8AF62xx Interrupt table 8 Interrupt table Table 16 STM8A interrupt table det Source NO Interrupt vector Wakeup Priority block Description address from Halt Comments Reset 0x00 8000 Yes User RESET vector SW interrupt 0x00 8004 External top level interrupt 0x00 8008 Auto wakeup from Halt 0x00 800C Clock Main clock controller 0x00 8010 controller 3 MISC Ext interrupt EO 0x00 8014 Yes Port A interrupts 4 MISC Ext interrupt E1 0x00 8018 Yes Port B interrupts 5 MISC Ext interrupt E2 0x00 801C Port C interrupts 6 MISC Ext interrup
42. anical data mm inches 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 44 LQFP 48 pin recommended footprint 0 50 1 20 36 25 0 30 CJ I E u R DD c UN 0 20 DJ CD C 9 70 5 80 EG E EJ DD DD DD 7 80 HI CD D 48 13 DU S 1 20 5 80 9 70 5B_FP 1 Drawing is not to scale Dimensions are in millimeters J DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Package characteristics Figure 45 LQFP 32 pin low profile quad flat package 7 x 7 ttr e 5V ME Table 51 LAFP 32 pin low profile guad flat package mechanical data mm inches Dim Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 600 0 2205 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 600 0 2205 e 0 800 0 0315 0 0 3 5 7 0 3 5 7 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 CCC 0 100 0 0039 1 Values in inches are converted from mm and rounded to 4 decimal digits J DoclD
43. aracterization results and not tested in production Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z Figure 37 SPI timing diagram where slave mode and CPHA 0 5 Q 1 1 B E l i d x CPHA 0 wSCKH UA m i n o t ahi AA EUR t4SCK t v SO vr A OT Ween dis SO 4 gt udo 1 wssour tsu SI e H r aun Xn GE INPUT E e e WSI ai14134 1 Measurement points are at CMOS levels 0 3 Vpp and 0 7 Vpp Figure 38 SPI timing diagram where slave mode and CPHA 1 NSS input A f SU NSS gt le SCkj wi h NSS CPHA 1 v ouf V V i CPOL 0 _ f i Se CPHA 1 t i CPOL 1 L N SCK Input it h SO lt gt SO OO MISO ae OUTPUT mon BIT6 OUT Leon OUT me Sl aria SI gt MOSI MSN IN BITI IN isn IN INPUT Se ai14135 1 Measurement points are at CMOS levels 0 3 Vpp and 0 7 Vpp J DoclD14952 Rev 9 67 91 Electrical characteristics STM8AF61xx STM8AF62xx Figure 39 SPI timing diagram master mode High NSS input SCK output CPHA 1 CPHA 1 SON YON N CPOL 0 i SCK output i PG MISO s s USC INPUT MSBIN BIT6 IN LSB IN a hM gt OUTUT i LG ty MO
44. ata corruption control registers Prequalification trials Most of the common failures unexpected reset and program counter corruption can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Table 44 EMS data Level clas S Symbol Parameter Conditions Vpp 3 3 V Taz 25 C fmastER 16 MHz HSI clock Conforms to IEC 1000 4 2 V Voltage limits to be applied on any I O pin to FESD induce a functional disturbance Fast transient voltage burst limits to be Vpp 3 3 V Ta 25 C Verte applied through 100 pF on Vpp and Vss fmaster 16 MHz HSI clock pins to induce a functional disturbance Conforms to IEC 1000 4 4 DoclD14952 Rev 9 Ly STM8AF61xx STM8AF62xx Electrical characteristics Electromagnetic interference EMI Emission tests conform to the SAE J 1752 3 standard for test software board layout and pin loading Table 45 EMI data Conditions Symbol Parameter Unit Monitored freguency band General conditions Vpp 5 V Peak level TA 25 C 30 MHz to 130 MHz 22 SEMI LQFP80 package dBuV conforming to SAE J 130 MHz to 1 GHz 3 SAE EMi level 1752 3 See
45. ce e A supply overvoltage applied to each power supply pin and e A current injection applied to each input output and configurable I O pin are performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 47 Electrical sensitivities Parameter Conditions Static latch up class 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC specifications that means when a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international standard 2 Available on STM8AF62xx devices only Thermal characteristics In case the maximum chip junction temperature T jmax specified in Table 23 General operating conditions on page 50 is exceeded the functionality of the device cannot be guaranteed Tjmax in degrees Celsius may be calculated using the following equation T max Tamax PDmax X OJA Where Tamax is the maximum ambient temperature in C jpis the package junction to ambient thermal resistance in C W PDmax is the sum of Pintmax and Pyomax PDmax PINTmax Piromax PiNTmax is the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power Pyomax represents the maximum power dissipation on output pins Where Piromax X Vor Toy 2 V
46. current of 4 mA the resulting leakage current in the adjacent input does not exceed 1 pA Thanks to this feature external protection diodes against current injection are no longer required DoclD14952 Rev 9 23 91 Pinouts and pin description STM8AF61xx STM8AF62xx 6 Pinouts and pin description 6 1 Package pinouts Figure 3 VFQFPN LQFP 32 pin pinout Ng c m z E ro O T uo 8 amp ol a s was X Ik O ITI K 0 0 O FRA NOoZo Pr233232 SStttotrt g2322222 Eu d ole e AANDANDA DOO aaonnn Yoooonnon 32 31 30 29 28 27 2625 NRST Die 24H PC7 SPI MISO OSCIN PA1 CZ 230 PC6 SPI MOSI OSCOUT PA2 13 220 PC5 SPI SCK Vss 04 210 PC4 HSyTIM1 CH4 VCAP 05 200 PC3 HSyTIM1 CH3 Vpp ae 190 PC2 HS TIM1 CH2 Vppio H7 18H PC1 HSYTIM1 CH1 AIN12 PF4 18 PE5 SPI NSS 9 10111213141516 Oo LT LATIAN TO a opm cda oo o o 22012010008 wot ON 222222 EES Eet EES OO oe ANWI II o Q zo 9 9 A NB rpzg2z FFF 1 HS high sink capability 24 91 DocID14952 Rev 9 Ly STM8AF61xx STM8AF62xx Pinouts and pin description Figure 4 LAFP 48 pin pinout c a H uo ua ma rizr s SC 99 99 H H NANNMSN O g CE 223 20355 SSEEESEOGBII DODONA X lE 222222223993 SERA LOLLDLACLALNAA C C O CE 1 O O PT fi 171710 48 40393 NRST Cie 38HPG1 OSCIN PA1 350 PGO OSCOUT PA2 340 PC7 SPI MISO Vssio 1 330 PC6 SPI_MOSI Vss Vppio 2 VCAP Vs
47. d to be generated for use in the application 5 7 4 Advanced control and general purpose timers STMBA devices described in this datasheet contain up to three 16 bit advanced control and general purpose timers providing nine CAPCOM channels in total ACAPCOM channel can be used either as input compare output compare or PWM channel These timers are named TIM1 TIM2 and TIM3 Table 5 Advanced control and general purpose timers Counter Counter Prescaler Inverted Repetition trigger External Break Timer E Channels 4 z width type factor outputs counter unit trigger input TIM1 16 bit Up down 1 to 65536 4 3 Yes Yes Yes Yes 27 TIM2 16 bit Up n 0to15 3 None No No No No 27 TIM3 16 bit Up n 0to 15 2 None No No No No 18 91 DoclD14952 Rev 9 Ly STM8AF61xx STM8AF62xx Product overview TIM1 Advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and bridge driver e 16 bit up down and up down AR auto reload counter with 16 bit fractional prescaler e Four independent CAPCOM channels configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output e Trigger module which allows the interaction of TIM1 with other on chip peripherals In the pres
48. e fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to trim the watchdog behavior to match the application timing perfectly The application software must refresh the counter before time out and during a limited time window If the counter is refreshed outside this time window a reset is issued DoclD14952 Rev 9 17 91 Product overview STM8AF61xx STM8AF62xx Independent watchdog timer The independent watchdog peripheral can be used to resolve malfunctions due to hardware or software failures Itis clocked by the 128 kHz LSI internal RC clock source and thus stays active even in case of a CPU clock failure If the hardware watchdog feature is enabled through the device option bits the watchdog is automatically enabled at power on and generates a reset unless the key register is written by software before the counter reaches the end of count 5 7 2 Auto wakeup counter This counter is used to cyclically wakeup the device in Active halt mode It can be clocked by the internal 128 kHz internal low frequency RC oscillator or external clock LSI clock can be internally connected to TIM3 input capture channel 1 for calibration 5 7 3 Beeper This function generates a rectangular signal in the range of 1 2 or 4 kHz which can be output on a pin This is useful when audible sounds without interference nee
49. e function remapping option 7 0 Port D4 alternate function TIM2 CH1 1 Port D4 alternate function BEEP AFR6 Alternate function remapping option 6 0 Port B5 alternate function AIN5 port B4 alternate function AIN4 1 Port B5 alternate function HHC SDA port B4 alternate function I c SCL AFR5 Alternate function remapping option 5 0 Port B3 alternate function AIN3 port B2 alternate function AIN2 port B1 alternate function AIN1 port BO alternate function AINO 1 Port B3 alternate function TIM1 ETR port B2 alternate function TIM1 CH3N port B1 alternate function TIM1 CH2N port BO alternate function TIM1 CHIN AFR4 Alternate function remapping option 4 OPT2 Reserved bit must be kept at O AFR3 Alternate function remapping option 3 0 Port DO alternate function TIM3 CH2 1 Port DO alternate function TIM1 BKIN AFR2 Alternate function remapping option 2 0 Port DO alternate function TIM3 CH2 1 Port DO alternate function CLK CCO Note AFR2 option has priority over AFR3 if both are activated AFR1 Alternate function remapping option 1 0 Port A3 alternate function TIM2 CH3 port D2 alternate function TIM3 CH1 1 Port A3 alternate function TIM3 CH1 port D2 alternate function TIM2 CH3 AFRO Alternate function remapping option 0 0 Port D3 alternate function TIM2_CH2 1 Port D3 alternate function ADC_ETR J 44 91 DoclD14952 Rev 9 STM8AF61xx STM8AF62xx J Option bytes
50. e resistor slope goes through 0 Figure 23 to Figure 32 show typical output level curves measured with output on a single pin Figure 23 Typ Vo Vpp 3 3 V standard ports Figure 24 Typ Vo Vpp 5 0 V standard ports 40 C 25 C lo MA Figure 25 Typ Vo Vpp 3 3 V true open drain ports 40 C 25 C 85 C 1 75 1 5 1 25 Va IV 0 75 0 5 0 25 40 C 25 C Vol IV Figure 26 Typ Vo Vpp 5 0 V true open drain ports 40 C L25 C 85 C 1 75 1 5 1 25 Vor V 0 75 0 5 0 25 25 62 91 DoclD14952 Rev 9 J STM8AF61xx STM8AF62xx Figure 27 Typ Vo Vpp 3 3 V high sink ports 40 C 25 C 85 C 125 C 1 25 Va VI lo mA Electrical characteristics Figure 28 Typ Vo Vpp 5 0 V high sink ports 40 C li 25 C 1 25 85 C 125 C 25 lo mA Figure 29 Typ Vpp z Vou Vpp 3 3 V standard ports Figure 30 Typ Vpp 8 VoH Vpp 5 0V standard ports 40 C 25 C 85 C 15 E a
51. ed in this datasheet 30 I O port hardware register map 31 General hardware register map ssssssssnsnnnnnnnnnnnnnnnnnnna 32 CPU SWIM debug module interrupt controller registers 2 22 39 Temporary memory unprotection registers llle 40 STMBA interrupt table 0 00 ce tees 41 Option CA AA 42 Option byte description rr 44 Voltage characteristics 0 m a k Ka a K AG K Ra K R K A 9 H Ka R a aR KR RR ka 48 Current characteristics 1s 2ssssansnssaaaaaa saa aaa naa an 49 Thermal characteristics aaa aaa aaa 49 Operating lifetime scs 2 n n x v s URA NRK K CR RK ARK KEN RR RRR RR e 49 General operating conditions 50 Operating conditions at power up power down 51 Total current consumption in Run Wait and Slow mode General conditions for Vpp apply Ta 40 to 150 C ee 52 Total current consumption in Halt and Active halt modes General conditions for Vpp apply Ta 40 to 55 C ee 53 Oscillator current consumption le 53 Programming current consumption isses nn 54 Typical peripheral current consumption Vpp DOUM 54 HSE user external clock characteristics cece eee ees 55 HSE oscillator characteristics ass alasaaakaka kaa a 56 HSI oscillator characteristics sss s aks aa seh 57 LSI oscillator characteristics 111 22s sss s aks eee 58 Flash program memory data EEPROM memory
52. egister 0x00 EE Reserved area 147 bytes 0x00 5300 TIM2 CR1 TIM2 control register 1 0x00 0x00 5301 TIM2 IER TIM2 interrupt enable register 0x00 0x00 5302 TIM2 SR1 TIM2 status register 1 0x00 0x00 5303 TIM2 SR2 TIM2 status register 2 0x00 0x00 5304 TIM2 EGR TIM2 event generation register 0x00 0x00 5305 TIM2 CCMR1 TIM2 capture compare mode register 1 0x00 0x00 5306 TIM2 CCMR2 TIM2 capture compare mode register 2 0x00 0x00 5307 TIM2 CCMRS TIM2 capture compare mode register 3 0x00 0x00 5308 TIM2 CCER1 TIM2 EE enable register 0x00 0x00 5309 tiii TIM2_CCER2 TIM2 ELE enable register 0x00 0x00 530A TIM2 CNTRH TIM2 counter high 0x00 0x00 530B TIM2 CNTRL TIM2 counter low 0x00 00 530COx TIM2 PSCR TIM2 prescaler register 0x00 0x00 530D TIM2 ARRH TIM2 auto reload register high OxFF 0x00 530E TIM2 ARRL TIM2 auto reload register low OxFF 0x00 530F TIM2 CCR1H TIM2 capture compare register 1 high 0x00 0x00 5310 TIM2 CCR1L TIM2 capture compare register 1 low 0x00 0x00 5311 TIM2 CCR2H TIM2 capture compare reg 2 high 0x00 0x00 5312 TIM2 CCR2L TIM2 capture compare register 2 low 0x00 0x00 5313 TIM2 CCR3H TIM2 capture compare register 3 high 0x00 J DoclD14952 Rev 9 STM8AF61xx STM8AF62xx d Memory and register map Table 13 General hardware register map continued Address Block Register label Register name esq 0x00 5314 TIM2 TIM2 CCR3L TIM2 capture compare register 3 lo
53. ent implementation it is possible to trigger the ADC upon a timer event e External trigger to change the timer behavior depending on external signals e Break input to force the timer outputs into a defined state e Three complementary outputs with adjustable dead time e Interrupt sources 4 x input capture output compare 1 x overflow update 1 x break TIM2 and TIM3 16 bit general purpose timers e 16 bit auto reload up counter e 15 bit prescaler adjustable to fixed power of two ratios 1 32768 e Timers with three or two individually configurable CAPCOM channels e interrupt sources 2 or 3 x input capture output compare 1 x overflow update 5 7 5 Basic timer The typical usage of this timer TIM4 is the generation of a clock tick Table 6 TIM4 Counter Counter Prescaler Inverted Repetition trigger External Break Timer Channels width type factor outputs counter unit trigger input 2n TIM4 8 bit Up None No No No No n 0to7 e 8 bit auto reload adjustable prescaler ratio to any power of two from 1 to 128 e Clock source master clock e interrupt source 1 x overflow update d DoclD14952 Rev 9 19 91 Product overview STM8AF61xx STM8AF62xx 5 8 Note 5 9 20 91 Analog to digital converter ADC The STM8A products described in this datasheet contain a 10 bit successive approximation ADC with up to 16 multiplexed input channels depending on the package The ADC name differs bet
54. ey values increments the counter When the option byte value reaches 0x08 the Flash memory and data EEPROM are erased BL 7 0 Bootloader enable If this option byte is set to 0x55 complementary value OxAA the OPT17 bootloader program is activated also in case of a programmed code memory for more details see the bootloader user manual UM0560 d 46 91 DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Electrical characteristics 10 10 1 10 1 1 10 1 2 10 1 3 10 1 4 d Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referred to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at Ta 40 C Ta 25 C and TA TAmax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Typical values Unless otherwise specified typical data are based on Ta 25 C Vpp 5 0 V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range Typical curves Unless other
55. g product characterization Functional EMS electromagnetic susceptibility While executing a simple application toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 1000 4 2 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 1000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Software recommendations The software flowchart must include the management of runaway conditions such as e Corrupted program counter e Unexpected reset e Critical d
56. gh sink I Os Load 20 pF Digital input pad leakage kg current Vss lt ViN lt Von Analog input pad leakage 40 C TA lt 125 C Ikg ana current Vss ViN lt Vis 40 C lt TA lt 150 C Leakage current in 109 Kon adjacent 1 08 z Ippio EES Including injection currents 60 mA Vppio or Vssio 1 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested in production 60 91 DoclD14952 Rev 9 Ly STM8AF61xx STM8AF62xx Electrical characteristics 2 Guaranteed by design 3 Data based on characterization results not tested in production Figure 20 Typical Vj and Vi vs Vpp four temperatures 6 40 C 5 A 25 C 85 C 4 125 C 2 Sg 3 N Voo V Figure 21 Typical pull up resistance Rpy vs Vpp four temperatures 60 u u a o Pull Up resistance Kk ohm R u i 40 C 2 25C 35 85 C 125 C 30 3 35 4 4 5 5 5 5 6 Voo VI Ly DocID14952 Rev 9 61 91 Electrical characteristics STM8AF61xx STM8AF62xx Figure 22 Typical pull up current l u vs Vpp four temperatures Typical output level curves 140 120 100 lt 5 80 5 40 C 2 60 gt 25 C amp 40 85 C 20 t 125 C 0 Po 0 1 2 3 4 5 6 Vip VI Note The pull up is a pur
57. h allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers STice key features e Program and data trace recording up to 128 K records e Advanced breakpoints with up to 4 levels of conditions e Data breakpoints e Real time read write of all device resources during emulation e Occurrence and time profiling and code coverage analysis new features e In circuit debugging programming via SWIM protocol e 8 bitprobe analyzer e 1 input and 2 output triggers e USB 2 0 high speed interface to host PC e Power supply follower managing application voltages between 1 62 to 5 5 V e Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements e Supported by free software tools that include integrated development environment IDE programming software interface and assembler for STM8 d DoclD14952 Rev 9 STM8AF61xx STM8AF62xx STM8 development tools 13 2 13 2 1 13 2 2 d Software tools STM8 development tools are supported by a complete free software package from STMicroelectronics that includes ST visual develop STVD IDE and the ST visual programmer STVP software interface ST
58. h quartz crystals and ceramic resonators e Frequency range 1 MHz to 16 MHz e Crystal oscillation mode preferred fundamental e Os standard I O pins multiplexed with OSCIN OSCOUT External clock input An external clock signal can be applied to the OSCIN input pin of the crystal oscillator The frequency range is 0 to 16 MHz Clock security system CSS The clock security system protects against a system stall in case of an external crystal clock failure In case of a clock failure an interrupt is generated and the high speed internal clock HSI is automatically selected with a frequency of 2 MHz 16 MHz 8 Table 4 Peripheral clock gating bit assignments in CLK PCKENR1 2 registers Bit Periphera Bit Peripheral Bit Peripheral Peripheral I clock clock clock clock PCKEN17 TIM1 PCKEN13 LINUART PCKEN27 PCKEN23 ADC PCKEN16 TIM3 PCKEN12 Reserved PCKEN26 PCKEN22 AWU PCKEN15 TIM2 PCKEN11 PCKEN25 Reserved PCKEN21 Reserved PCKEN14 TIM4 PCKEN10 pi PCKEN24 Reserved PCKEN20 Reserved DocID14952 Rev 9 Ly STM8AF61xx STM8AF62xx Product overview 5 6 5 7 5 7 1 J Low power operating modes For efficient power management the application can be put in one of four different low power modes You can configure each mode to obtain the best compromise between lowest power consumption fastest start up time and available wakeup sources e Wait mode In this mode the CPU is st
59. he parameter maximum value must be respected for the full application range 2 This frequency of 1 MHz as a condition for VcAp parameters is given by design of internal regulator 3 Available on STM8AF62xx devices only d 50 91 DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Electrical characteristics Figure 8 fcpumax Versus Vpp fcpu MHz Functionality not guaranteed in this area Functionality guaranteed d Q T4 40 to 150 C 5 5 3 0 4 0 5 0 Supply voltage V 1 This figure is valid only for STM8AF62xx devices Table 24 Operating conditions at power up power down 1 Guaranteed by design not tested in production Symbol Parameter Conditions Min Typ Max Unit Vpp rise time rate oo typp us V Vpp fall time rate 5 po Reset release delay Vpp rising 1 1 7 ms tTEMP Reset generation delay Vpp falling 3 US Power on reset Vire threshold ii zx Brown out reset Vir threshold s SR Brown out reset 1 VHYS BOR hysteresis 70 id 2 If Vpp is below 3 V the code execution is guaranteed above the Vir and Vir thresholds RAM content is kept The EEPROM programming sequence must not be initiated DoclD14952 Rev 9 51 91 Electrical characteristics STM8AF61xx STM8AF62xx 10 3 1 10 3 2 52 91 VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor Cer to the Vcap pi
60. ions Typ Max Unit Quartz or fosc 24 MHz HSE oscillator current Sec fosc 16 MHz IDD OSC Wach resonator consumption j CL 33 pF f 8 MH Vpp 25V Osc 7 z mA Quartz or fosc 24 MHz A ceramic land HSE kaia ae resonator fosc 16 MHz consumption i CL 33 pF f 8 MH Vpp 3 3V se 9 MHZ 1 During startup the oscillator current consumption may reach 6 mA 2 The supply current of the oscillator can be further optimized by selecting a high quality resonator with small Rpm value Refer to crystal manufacturer for more details 3 Informative data J DoclD14952 Rev 9 53 91 Electrical characteristics STM8AF61xx STM8AF62xx Table 28 Programming current consumption Symbol Parameter Conditions Typ Vpp 25 V 40 C to 150 C Max Unit IDD PROG Programming current erasing and programming data 1 0 1 7 mA or Flash program memory Table 29 Typical peripheral current consumption Vpp 5 0 v Symbol Parameter Hed DP maat Unit IDD TIM1 TIM1 supply current IDD TIM2 TIM2 supply current 2 IDD TIM3 TIM3 supply current IDD TIM4 TIM4 supply current IDD LINUART LINUART supply current IDD SPI SPI supply current mA IDD 12C 12C supply current IDD AWU AWU supply current IDD TOT DIG All digital peripherals on been aid GE current when g 1 Typical values not tested in production Since the peripherals are powered by an internal
61. its size can be adjusted in increments of 512 bytes by programming the UBC and NUBC option bytes see Section 9 Option bytes on page 42 Figure 2 Flash memory organization of STM8A products r Programmable area UBC area maximum 32 Kbytes Remains write protected during IAP Flash program memory Flash program memory area Write access possible for IAP Data Data memory area 1 Kbytes EEPROM memory y 2 _ J Option bytes N p yt Read out protection ROP The STMB8A provides a read out protection of the code and data memory which can be activated by an option byte setting see the ROP option byte in section 10 The read out protection prevents reading and writing Flash program memory data memory and option bytes via the debug module and SWIM interface This protection is active in all device operation modes Any attempt to remove the protection by overwriting the ROP option byte triggers a global erase of the program and data memory The ROP circuit may provide a temporary access for debugging or failure analysis The temporary read access is protected by a user defined 8 byte keyword stored in the option byte area This keyword must be entered via the SWIM interface to temporarily unlock the device DoclD14952 Rev 9 Ly STM8AF61xx STM8AF62xx Product overview 5 5 5 5 1 5 5 2 J If desired the temporary unlock mechanism can be permanently disabled by the user through
62. k x life augmented STM8AF6x26 4x 66 68 Automotive 8 bit MCU with up to 32 Kbytes Flash data EEPROM 10 bit ADC timers LIN SPI 12C 3 to 5 5 V Features November 2014 Core Max fepy 16 MHz Advanced STMBA core with Harvard architecture and 3 stage pipeline Average 1 6 cycles instruction resulting in 10 MIPS at 16 MHz fcpy for industry standard benchmark Memories Flash Program memory 16 to 32 Kbytes Flash data retention 20 years at 55 C after 1 kcycle Data memory 0 5 to 1 Kbyte true data EEPROM endurance 300 kcycles RAM 1 to 2 Kbytes Clock management Low power crystal resonator oscillator with external clock input Internal user trimmable 16 MHz RC and low power 128 kHz RC oscillators Clock security system with clock monitor Reset and supply management Wait auto wakeup Halt low power modes with user definable clock gating Low consumption power on and power down reset Interrupt management Nested interrupt controller with 32 vectors Up to 34 external interrupts on 5 vectors Timers Up to 2 general purpose 16 bit PWM timers with up to 3 CAPCOM channels each IC OC or PWM Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronization 8 bit AR basic timer with 8 bit prescaler Auto wakeup timer This is information on a product in full production Datasheet
63. lock 16 MHz 1 50 fcpu 125 kHz LSI internal RC fcpu 128 kHz 1 50 Unit mA 1 The current due to I O utilization is not taken into account in these values 2 Values not tested in production Design guidelines only J DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Electrical characteristics Table 26 Total current consumption in Halt and Active halt modes General conditions for Vpp apply Ta 40 to 55 C Conditions Main Clock source and T voltage Flash specific yp regulator mode temperature MVR U condition Parameter Max Unit Clocks stopped Supply current in Halt mode Clocks stopped Ta 25 C Ext clock 16 MHz 3 MASTER 125 kHz 170 900 Supply current in Active halt mode with regulator on HA LSI clock 128 kHz 150 230 IDD AH bad LSI clock 128 kHz 25 42 Supply current in Active halt mode with regulator off LSI clock 128 kHz Ta 25 C Wakeup time from Active halt mode with regulator on On 10 309 yaa Ta 40 to 150 C us Wakeup time from Active Of moge 50 go halt mode with regulator off 0 1 Configured by the REGAH bit in the CLK ICKR register 2 Configured by the AHALT bit in the FLASH CR1 register 3 Data based on characterization results Not tested in production Current consumption for on chip peripherals Table 27 Oscillator current consumption Symbol Parameter Condit
64. ly insured if Vy maximum is respected If Vu maximum cannot be respected the injection current must be limited externally to the liy pin value A positive injection is induced by Vj gt Vpp while a negative injection is induced by Vin lt Vss For true open drain pads there is no positive injection current and the corresponding Vum maximum must always be respected J 48 91 DoclD14952 Rev 9 STM8AF61xx STM8AF62xx J Table 20 Current characteristics Electrical characteristics Symbol Ratings Max kapp Total current into Vppjo power lines source X23 100 lvssio Total current out of Vss jo ground lines sink 2X 100 Output current sunk by any I O and control pin 20 lo Output current source by any I Os and control pin 20 wuel Injected current on any pin 10 IiNJ TOT Sum of injected currents 50 1 All power Vpp Vppio VppA and ground Vss Vssio Vssa pins must always be connected to the external supply The total limit applies to the sum of operation and injected currents Unit mA Vppio includes the sum of the positive injection currents Vssjo includes the sum of the negative injection currents 4 This condition is implicitly insured if Vu maximum is respected If Vu maximum cannot be respected the injection current must be limited externally to the li pin Value A positive injection is induced by Vin gt Von while a negative injection is induced by Vi lt V
65. ly regulated constant digital supply voltage the values are similar in the full supply voltage range 2 Data based on a differential Ipp measurement between no peripheral clocked and a single active peripheral This measurement does not include the pad toggling consumption 3 Data based on a differential Ipp measurement between reset configuration and continuous A D conversions Current consumption curves Figure 10to Figure 15 show typical current consumption measured with code executing in RAM Figure 10 Typ IDD RUN HSE vs Vpp fcpy 16 MHz peripheral on Figure 11 Typ IDD RUN HSE vs fcPu Vpp 5 0 V peripheral on IDD RUN HSE mA IppRUN HsE mA fcpu MHz 54 91 DoclD14952 Rev 9 J STM8AF61xx STM8AF62xx Electrical characteristics Figure 12 Typ IDD RUN HSI vs Vpp Figure 13 Typ IDD WFI HSE vs Vpp fcpy 16 MHz peripheral off fcpy 16 MHz peripheral on T E3 E o TTE yug Jh 4 E I 3 g 5 z m 25 C vali i 25 C K1 85 C ch 85 C S R 125 C E mmi n 25 39 4 5 5 5 6 5 2 5 3 5 4 5 5 9 6 5 VDD V VDD V Figure 14 Typ IDD WFI HSE vs fcPu Figure 15 Typ IDD WFI HSI vs Vpp Vpp 5 0 V peripheral on fcpy 16 MHz peripheral off E E iy fcpu MHz Vop V
66. n Cgxr is specified in Table 23 Care should be taken to limit the series inductance to less than 15 nH Figure 9 External capacitor Cex7 Y ESL Rleak ESR 9 rt 3j 1 Legend ESR is the equivalent series resistance and ESL is the equivalent inductance Supply current characteristics The current consumption is measured as described in Figure 6 on page 47 and Figure 7 on page 48 If not explicitly stated general conditions of temperature and voltage apply Table 25 Total current consumption in Run Wait and Slow mode General conditions for Vpp apply Ta 40 to 150 C Symbol Parameter Condi All peripherals clocked code tions fopy 16 MHz Max IDD SLOW 1 Run mode Supply current in Slow mode external clock without resonator fepy scaled down all peripherals off code executed from RAM fepy 16 MHz 1 Supply executed from Flash fcpu 8 MHz 4 0 740 IDD RUN current in program memory 2 fcpu 4 MH 24 AIS HSE external clock CPU E without resonator fopy 2 MHz 1 5 2 5 All peripherals fopy 16 MHz 3 7 5 0 S clocked code 2 1 SCC in executed from RAM fcpu 8 MHz 22 3 02 DD RUN and EEPROM HSE fopy 4 MHz 1 5 Supply CPU stopped all fcpu 8 MHz 1 92 Ipp weiy V current in peripherals off HSE Wait mode external clock fcpu 4 MHz 1 62 fcpu 2 MHz Ext c
67. n and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces information previously supplied in any prior versions of this document 2014 STMicroelectronics All rights reserved J DoclD14952 Rev 9 91 91
68. o 125 C 100 ka Ta 525 C 40023 tRET Data retention time years Ta 55 C 2000 1 The physical granularity of the memory is four bytes so cycling is performed on four bytes even when a write erase operation addresses a single byte 2 More information on the relationship between data retention time and number of write erase cycles is available in a separate technical document 3 Retention time for 256B of data memory after up to 1000 cycles at 125 C J DoclD14952 Rev 9 59 91 Electrical characteristics STM8AF61xx STM8AF62xx 10 3 6 UO port pin characteristics General characteristics Subject to general operating conditions for Vpp and Ta unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor Table 37 I O static characteristics Symbol Parameter Conditions Min Typ Max Unit Vu Input low level voltage Vum Input high level voltage Vhys Hysteresis Standard 1 0 Vpp 5 V 12 3mA Vou Output high level voltage Standard 1 0 Vpp 3 V 12 1 5 mA High sink and true open drain 1 0 Vpp 5 V 12 8mA VoL Output low level voltage Standard 1 0 Vpp 5 V 12 3mA Standard 1 0 Vpp 3 V 12 1 5 mA Rpu Pull up resistor Vpp 5 V Vin Vss Fast I Os Load 50 pF Standard and high sink I Os te t Rise and fall time Load 50 pF RF 1 10 90 Fast I Os Load 20 pF Standard and hi
69. ode except the ROP and UBC options that can only be toggled in ICP mode via SWIM Refer to the STM8 Flash programming manual PM0051 and STM8 SWIM communication protocol and debug module user manual UM0470 for information on SWIM programming procedures Table 17 Option bytes Option bits Factory default setting 0x00 Read out 4800 protection OPTO ROP 7 0 0x00 ROP pes Userboot OPT Reserved UBC 5 0 0x00 code pen UBC NoPT1 Reserved NUBC 5 0 OxFF 0x00 Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFRO 0x00 4803 function 0x00 remapping NAFR MAER NAFR NAFR NAFR NAFR MAER NAFR 4804 AFR NOPT2 gt 37 6 5 4 3 2 1 0 OXEF 0x00 16MHZ LSI IWDG WWDG WWDG 4805 Watchdog SETS Reserved TRIMO EN HW Hw HALT 000 0x00 option N16MHZ NLSI NIWDG NWWD NWWG 4806 NOPTS ae TRIMO EN HW G Hw Har OFF 0x00 EXT CKAWU PRS PRS 4807 Bn OPT4 Reserved CLK SEL C1 CO 0x00 0x00 option NEXT NCKAW NPR NPR 4808 x Reseived cik useL sc1 sco CFF pali OPT5 HSECNT 7 0 0x00 4809 HSE clock 0x00 startup 480A NOPT5 NHSECN 7 0 OxFF J 42 91 DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Option bytes Table 17 Option bytes continued Option bits Factory byte ti default OPT6 TMU 3 0 NOPT6 NTMU 3 0 OxFF OPT7 Reser
70. oller pin description Added Section 13 4 5 LIN header error when automatic resynchronization is enabled 10 Aug 2009 22 Oct 2009 Updated title on cover page Added VFQFPN32 5x 5 mm package Added STM8AF62xx devices and modified cover page header to clarify the part numbers covered by the datasheets Updated Note 1 below Table 1 Device summary Updated D temperature range to 40 to 150 C Content of Section 5 Product overview reorganized Renamed Section 7 Memory and register map and content merged with Register map section Renamed BL EN and NBL EN BL and NBL respectively in Table 17 Option bytes Added Table 22 Operating lifetime Added CEXT and Pp power dissipation in Table 23 General operating conditions and Section 10 3 1 VCAP external capacitor Suffix D maximum junction temperature Ty updated in Table 23 General operating conditions Update tvoo in Table 24 Operating conditions at power up power down Moved Table 29 Typical peripheral current consumption Vpp 5 0 V to Section Current consumption for on chip peripherals and removed IDD CAN Updated Section 12 Ordering information for the devices supported by the datasheet Updated Section 13 STM8 development tools 08 Jul 2010 J DoclD14952 Rev 9 87 91 Revision history 88 91 STM8AF61xx STM8AF62xx Table 52 Document revision history continued Date 31 Jan 2011 Revision Changes Modified refe
71. opped but peripherals are kept running The wakeup is performed by an internal or external interrupt or reset e Active halt mode with regulator on In this mode the CPU and peripheral clocks are stopped An internal wakeup is generated at programmable intervals by the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption is higher than in Active halt mode with regulator off but the wakeup time is faster Wakeup is triggered by the internal AWU interrupt external interrupt or reset e Active halt mode with regulator off This mode is the same as Active halt with regulator on except that the main voltage regulator is powered off so the wake up time is slower e Halt mode CPU and peripheral clocks are stopped the main voltage regulator is powered off Wakeup is triggered by external event or reset In all modes the CPU and peripherals remain permanently powered on the system clock is applied only to selected modules The RAM content is preserved and the brown out reset circuit remains activated Timers Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications The watchdog timer activity is controlled by the application program or option bytes Once the watchdog is activated it cannot be disabled by the user program without going through reset Window watchdog timer The window watchdog is used to detect the occurrence of a softwar
72. ory unprotection 0101 TMU disabled permanent ROP Any other value TMU enabled Reserved OPT8 TMU KEY 1 7 0 Temporary unprotection key 0 Temporary unprotection key Must be different from 0x00 or OxFF OPT9 TMU KEY 2 7 0 Temporary unprotection key 1 Temporary unprotection key Must be different from 0x00 or OxFF OPT10 TMU KEY 3 7 0 Temporary unprotection key 2 Temporary unprotection key Must be different from 0x00 or OxFF OPT11 TMU KEY 4 7 0 Temporary unprotection key 3 Temporary unprotection key Must be different from 0x00 or OxFF DoclD14952 Rev 9 45 91 Option bytes STM8AF61xx STM8AF62xx Table 18 Option byte description continued Option byte no Description OPT12 TMU KEY 5 7 0 Temporary unprotection key 4 Temporary unprotection key Must be different from 0x00 or OxFF OPT13 TMU KEY 6 7 0 Temporary unprotection key 5 Temporary unprotection key Must be different from 0x00 or OxFF OPT14 TMU KEY 7 7 0 Temporary unprotection key 6 Temporary unprotection key Must be different from 0x00 or OxFF OPT15 TMU KEY 8 7 0 Temporary unprotection key 7 Temporary unprotection key Must be different from 0x00 or OxFF TMU MAXATT 7 0 TMU access failure counter TMU MAXATT can be initialized with the desired value only if TMU is disabled TMU 3 0 0101 in OPT6 option byte OPT16 When TMU is enabled any attempt to temporary remove the readout protection by using wrong k
73. pical LSI frequency vs Vpp 396 296 196 E 25 C ge eee 1 LSI frequency variation 2 3 T T T T T T 2 5 3 3 5 4 Voo V 4 5 5 5 6 C1 J DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Electrical characteristics 10 3 5 Memory characteristics Flash program memory data EEPROM memory General conditions Ta 40 to 150 C Table 34 Flash program memory data EEPROM memory Symbol Parameter Conditions Min Typ Max Unit V Operating voltage fcpu is 0 to 16 MHz BD all modes execution write erase with O ws V Operating voltage fcpu is 0 to 16 MHz DB code execution with O ws Standard programming time including erase for byte word block t 1 byte 4 bytes 128 bytes Fast programming time for 1 block 128 bytes terase Erase time for 1 block 128 bytes 7 3 3 3 ms Table 35 Flash program memory Symbol Parameter Twe Temperature for writing and erasing N Flash program memory endurance WE erase write cycles tRET Data retention time 1 The physical granularity of the memory is four bytes so cycling is performed on four bytes even when a write erase operation addresses a single byte Table 36 Data memory Symbol Parameter Condition Min Max Unit TwE Temperature for writing and erasing C Data memory endurance Ta 25 C 300 k Nwe H cycles erase write cycles Ta 40 C t
74. pp Vou lon taking into account the actual Volle and Vop lop of the I Os at low and high level in the application d DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Electrical characteristics Table 48 Thermal characteristics Symbol Parameter Value Unit Thermal resistance junction ambient LQFP 32 7 x 7 mm Thermal resistance junction ambient VFQFPN32 1 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment 10 4 1 Reference document JESD51 2 integrated circuits thermal test method environment conditions natural convection still air Available from www jedec org 10 4 2 Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the order code see Section 12 Ordering information The following example shows how to calculate the temperature range needed for a given application Assuming the following application conditions Maximum ambient temperature Tamax 82 C measured according to JESD51 2 Ippmax 14 mA Vpp 5 V maximum 20 l Os used at the same time in output at low level with lo 8 mA Vo 0 4 V Pintmax 14 mA x 5 V 70 mW Piomax 20 x 8 mA x 0 4 V 64 mW This gives Pintmax 70 mW and Pjomax 64 mW Ppmax 70 mW 64 mW Thus Ppmax 134 mW Using the values obtained in Table 48 Thermal characteristics on page 75 T Jmax is calculated as follows For LOFP64 46 C W Timax 82 C 46
75. pped with bigger memory and more I Os This silicon is supposed to be replaced later by the target silicon Not recommended for new design 4 Available on STM8AF62xx devices DoclD14952 Rev 9 83 91 STM8 development tools STM8AF61xx STM8AF62xx 13 13 1 13 1 1 84 91 STM8 development tools Development tools for the STM8A microcontrollers include the e Slice emulation system offering tracing and code profiling e STVD high level language debugger including assembler and visual development environment seamless integration of third party C compilers e SIVP Flash programming software In addition the STM8A comes with starter kits evaluation boards and low cost in circuit debugging programming tools Emulation and in circuit debugging tools The STM8 tool line includes the STice emulation system offering a complete range of emulation and in circuit debugging features on a platform that is designed for versatility and cost effectiveness In addition STM8A application development is supported by a low cost in circuit debugger programmer The STice is the fourth generation of full featured emulators from STMicroelectronics It offers new advanced debugging capabilities including tracing profiling and code coverage analysis to help detect execution bottlenecks and dead code In addition STice offers in circuit debugging and programming of STM8A microcontrollers via the STM8 single wire interface module SWIM whic
76. rences to reference manual and Flash programming manual in the whole document Added reference to AEC Q100 standard on cover page Renamed timer types as follows Auto reload timer to general purpose timer Multipurpose timer to advanced control timer System timer to basic timer Introduced concept of medium density Flash program memory Updated timer names in Figure 1 STM8A block diagram Added TMU brief description in Section 5 4 Flash program and data EEPROM and updated TMU MAXATT description in Table 18 Option byte description Updated clock sources in clock controller features Section 5 5 1 Changed 16MHZTRIMO to HSITRIM bit in Section User trimming Added Table 4 Peripheral clock gating bits in Section 5 5 6 Updated Section 5 6 Low power operating modes Added calibration using TIM3 in Section 5 7 2 Auto wakeup counter Added Table 7 ADC naming and Table 8 Communication peripheral naming correspondence Added Note 1 related AIN12 pin in Section 5 8 Analog to digital converter ADC and Table 10 STM8AF61xx 62xx 32 Kbytes microcontroller pin description Updated SPI data rate to 10 Mbit s or fyaster 2 in Section 5 9 1 Serial peripheral interface SPI Added reset state in Table 9 Legend abbreviation Table 10 STM8AF61xx 62xx 32 Kbytes microcontroller pin description added Note 7 related to PD1 SWIM modified Note 6 corrected wpu input for PE1 and PE2 and renamed TIMn CCx and TIMn NCCx to TIMn C
77. rface SPI The devices covered by this datasheet contain one SPI The SPI is available on all the supported packages e Maximum speed 10 Mbit s or fuAsrER 2 both for master and slave e Full duplex synchronous transfers e Simplex synchronous transfers on two lines with a possible bidirectional data line e Master or slave operation selectable by hardware or software e CRC calculation e 1 byte Tx and Rx buffer e Slave mode master mode management by hardware or software for both master and slave e Programmable clock polarity and phase e Programmable data order with MSB first or LSB first shifting e Dedicated transmission and reception flags with interrupt capability e SPI bus busy status flag e Hardware CRC feature for reliable communication CRC value can be transmitted as last byte in Tx mode CRC error checking for last received byte Inter integrated circuit 12C interface The devices covered by this datasheet contain one I2C interface The interface is available on all the supported packages e l C master features Clock generation Start and stop generation e lC slave features Programmable DC address detection Stop bit detection e Generation and detection of 7 bit 10 bit addressing and general call e Supports different communication speeds Standard speed up to 100 kHz A Fast speed up to 400 kHz e Status flags Transmitter receiver mode flag End of byte transmission flag C b
78. s should also be soldered to the PCB to improve the lead pad solder joint life Table 49 VFQFPN 32 lead very thin fine pitch quad flat no lead package mechanical data inches Dim A1 A3 D E2 e L ddd DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Package characteristics J 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 43 LQFP 48 pin low profile quad flat package 7 x 7 D pi Kl eec C D3 36 25 37 24 E3 E1 E 48 13 Pin 1 n TO E identification 1 12 5B ME Table 50 LQFP 48 pin low profile quad flat package mechanical data mm inches Dim Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 500 0 2165 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 500 0 2165 e 0 500 0 0197 0 0 3 5 7 0 3 5 7 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 DoclD14952 Rev 9 79 91 Package characteristics STM8AF61xx STM8AF62xx 80 91 Table 50 LQFP 48 pin low profile quad flat package mech
79. s shown in the rightmost column of Table 10 some alternate functions can be remapped at different I O ports by programming one of eight AFR alternate function remap option bits Refer to Section 9 Option bytes on page 42 When the remapping option is active the default alternate function is no longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers Alternate function remapping does not effect GPIO capabilities of the I O ports see the GPIO section of the STM8S and STM8A microcontroller families reference manual RM0016 DoclD14952 Rev 9 29 91 Memory and register map STM8AF61xx STM8AF62xx 7 TA 30 91 Memory and register map Memory map Figure 5 Register and memory map of STM8A products 00 0000 Up to 2 Kbytes RAM RAM end A BIEN 00 4000 Reserved Up to 1 Kbyte data EEPROM 00 4400 Reserved 00 4800 A 00 4900 Option bytes Reserved 00 5000 HW registers 00 581D i Reserved 00 6000 2 Kbytes of Boot ROM 00 6800 l 00 7F00 CPU SWIM Debug ITC registers 00 8000 IT vectors 00 8080 Up to 32 Kbytes of Flash program memory Flash Program memory end Table 11 Memory model for the devices covered in this datasheet Flash program memory end RAM size address RAM end Stack roll over address address Flash program memory size 32K 0x00 OFFFF 16K 0x00 OBFFF 2K 0x00 07FF 0x00 0600 8K
80. set 2 ka k ali sta alia Bd lin a a ses 85 13 2 2 C and assembly toolchains 85 13 3 Programming AER Ee EE dE x EY b REX kak dansk shd 86 Revision history AA ese dis us vaga ass SS Sho seakael kv 87 d DoclD14952 Rev 9 STM8AF61xx STM8AF62xx List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Ly Device SUMMA bk ea oda al ipee aX eid fe Pid aa a va ee eta aa e 1 STM8AF62xx product line up 2 0 2 2 eee 10 STM8AF H61xx product line up asal aka saal aaa aaa a 10 Peripheral clock gating bit assignments in CLK_PCKENR1 2registers 16 Advanced control and general purpose timers sissa kanan 18 uU v E EN 19 ADGC narrilnt skan euet e ren R Ree e Rue Alert RR R bea 20 Communication peripheral naming correspondence skan 20 Legend abbreviationi ois mma sc Eee R ks EG e haa wee endis 25 STM8AF61xx 62xx 32 Kbytes microcontroller pin description 26 Memory model for the devices cover
81. set which allows you to assemble and link your application source code DoclD14952 Rev 9 85 91 STM8 development tools STM8AF61xx STM8AF62xx 13 3 86 91 Programming tools During the development cycle STice provides in circuit programming of the STM8A Flash microcontroller on your application board via the SWIM protocol Additional tools are to include a low cost in circuit programmer as well as ST socket boards which provide dedicated programming platforms with sockets for programming your STM8A For production environments programmers will include a complete range of gang and automated programming solutions from third party tool developers already supplying programmers for the STM8 family d DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Revision history 14 Revision history Table 52 Document revision history Date Revision Changes 22 Aug 2008 Initial release Document revised as the following Updated Features on page 1 Updated Table 1 Device summary Updated Section 3 Product line up Changed Section 5 Product overview Updated Section 6 Pinouts and pin description Changed Section 7 2 Register map Updated Section 8 Interrupt table Updated Section 9 Option bytes Updated Section 10 Electrical characteristics Updated Section 11 Package characteristics Updated Section 12 Ordering information Added Section 13 STM8 development tools Adapted Table 10 STM8AF61xx 62xx 32 Kbytes microcontr
82. sio 2 Von PC5 SPI SCK Vppio 1 PC4 HS TIM1 CH4 TIM2 CH3 P 3 Hg PC3 HS TIM1_CH3 PA4 C10 PC2 HS TIM1 CH2 PA5 111 PC1 HS TIM1 CH1 2 HS high sink capability 11441 A A TIM1_CH3N A TIM1_CH2N A TIM1 CHIN A TIM1 ETR A Table 9 Legend abbreviation 250 PES SPI_NSS Port and control configuration Input Type l input O output S power supply Level Input CM CMOS standard for all I Os Output HS High sink 8 mA Output speed 01 Standard up to 2 MHz O2 Fast up to 10 MHz 03 Fast slow programmability with slow as default state after reset OA Fast slow programmability with fast as default state after reset float floating wpu weak pull up Output T true open drain OD open drai n PP push pull Reset state Bold X pin state after reset release Unless otherwise specified the pin state is the same during the reset phase i e under reset and after internal reset release i e at reset state d DoclD14952 Rev 9 25 91 Pinouts and pin description STM8AF61xx STM8AF62xx Table 10 STM8AF61xx 62xx 32 Kbytes microcontroller pin description Pin LQFP48 VFQFPN LQFP32 numbe Pin name Type floating wpu Default alternate function Main function after reset Resonator crystal in Alternate function after remap option bit Resonator crystal out I O ground
83. ss For true open drain pads there is no positive injection current allowed and the corresponding Vjy maximum must always be respected Table 21 Thermal characteristics Symbol Ratings Value Unit TsrG Storage temperature range 65 to 150 C Tj Maximum junction temperature 160 Table 22 Operating lifetime Symbol Value Unit 40 to 125 C Grade 1 OLF Conforming to AEC Q100 rev G 40 to 150 C Grade 0 1 For detailed mission profile analysis please contact your local ST Sales Office DoclD14952 Rev 9 49 91 Electrical characteristics STM8AF61xx STM8AF62xx 10 3 Operating conditions Table 23 General operating conditions Symbol Parameter Conditions Min Max Unit fcpu Internal CPU clock frequency Ta 40 C to 150 C 0 16 MHz Vpp Vppio Standard operating voltage 2 3 0 5 5 V Cext capacitance of external 470 3300 nF capacitor Vcap D ESR of external capacitor 0 3 0 at 1 MHz O ESL of external capacitor 15 nH LQFP32 85 Pp Power dissipation all VFQFPN32 200 mW temperature ranges LQFP48 88 Suffix A 85 Suffix B 105 TA Ambient temperature Suffix C 125 Suffix DO 150 40 C Suffix A 90 Suffix B 110 Tj Junction temperature range Suffix C 130 Suffix DO 155 1 Care should be taken when selecting the capacitor due to its tolerance as well as the parameter dependency on temperature DC bias and frequency in addition to other factors T
84. sses paese EE st va 9 3 Product line up Me 10 4 Block diagrami ansa a EEN Ua PSS aaa E ha RE 11 5 Product overview nona use EERE ANAN sete RU ut DT Jako SES 12 5 1 STMBA central processing unit CPU 12 5 1 1 Architecture and registers 12 5 1 2 Addressing ioci eder iocos nee a t e B et a a 12 5 1 3 Instr ctomiset usse eden im Pad sse E des deuten 12 5 2 Single wire interface module SWIM and debug module DM 13 5 2 1 SWIM 240 5034 paha ns khmm am n ses tab hahaa end het naa 13 5 2 2 Debug module 2 ccena br uses e Re e Rete e Rn 13 5 3 Interrupt controller 2 3 unt 1n CR Re koe tro S ttp a eR x dones 13 5 4 Flash program and data EEPROM e 13 5 4 1 Architecture ues KAN eave a DR Re enel ema ERR A 13 5 4 2 Write protection WP IRA 14 5 4 3 Protection of user boot code UBC 14 5 4 4 Read out protection ROP 14 5 5 Clock controller ues exu dk p ERR E ROCK GUR OR XR RRMR wee shee RE REGE 15 5 5 1 IS e uc ar oe hee Rh Ge a dane Gogh eg Netter 15 5 5 2 16 MHz high speed internal RC oscillator HSI 15 5 5 3 128 kHz low speed internal RC oscillator LSI 16 5 5 4 16 MHz high speed external crystal oscillator HSE 16 5 5 5 External clock input 16 5 5 6 Clock security system Cie 16 5 6 Low power operating modes 17 57 TIMES eui eek ER Run RE Gon nee ee C OR RC vakamaad c
85. t E3 0x00 8020 KON Port D interrupts 7 MISC Ext interrupt E4 0x00 8024 Yes Port E interrupts Reserved Reserved SPI End of transfer 0x00 8030 Yes Timer 1 a a 0x00 8034 z 12 Timer 1 Capture compare V Timer 2 Update overflow 0x00 803C Timer 2 Capture compare 0x00 8040 Timer 3 Update overflow 0x00 8044 Timer 3 EE 0x00 8048 Reserved 12C Ic interrupts LINUART Tx complete error LINUART Receive data full reg 0x00 8054 0x00 8058 0x00 805C 0x00 8060 Timer4 Update overflow 0x00 8064 E 24 EEPROM EI of Programming 0x00 8068 Write in not allowed area 1 All reserved and unused interrupts must be initialized with IRET for robust programming End of conversion d DoclD14952 Rev 9 41 91 Option bytes STM8AF61xx STM8AF62xx 9 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated block of the memory Each option byte has to be stored twice for redundancy in a regular form OPTx and a complemented one NOPTx except for the ROP read out protection option byte and option bytes 8 to 16 Option bytes can be modified in ICP mode via SWIM by accessing the EEPROM address shown in Table 17 Option bytes below Option bytes can also be modified on the fly by the application in IAP m
86. tions concerning NRST pin level above Figure 36 Recommended reset pin protection and updated external capacitor value Added Raisonance compiler in Section 13 2 Software tools Moved know limitations to separate errata sheet 5 continued 31 Jan 2011 Updated wildcards of document part numbers Table 1 Device summary updated footnote 1 and added footnote 2 to all STM8AF61xx part numbers Section 1 Introduction small text change in first paragraph Table 2 STM8AF62xx product line up added P version for all order codes updated RAM Table 3 STM8AF H61xx product line up added P version for all order codes Figure 1 STM8A block diagram updated POR BOR and WDG updated LINUART input added legend Section 5 4 Flash program and data EEPROM removed nonrelevant bullet points and added a sentence about the factory programme Table 4 Peripheral clock gating bit assignments in CLK PCKENR1 2 registers updated ADC features updated ADC input range Table 11 Memory model for the devices covered in this datasheet updated 16 Kbyte and 8 Kbyte information Table 17 Option bytes updated factory default setting for NOPT17 added footnote 7 Section 10 1 1 Minimum and maximum values T 40 C not 40 C Table 23 General operating conditions updated Vcap Table 25 Total current consumption in Run Wait and Slow mode General conditions for Vpp apply T4 40 to 150 C updated conditions for IDD RUN
87. ty single voltage program Flash memory e Upto 1 Kbytes true not emulated data EEPROM e Read while write writing in the data memory is possible while executing code in the Flash program memory The whole Flash program memory and data EEPROM are factory programmed with 0x00 Architecture e The memory is organized in blocks of 128 bytes each e Read granularity 1 word 4 bytes e Write erase granularity 1 word 4 bytes or 1 block 128 bytes in parallel e Writing erasing word and block management is handled automatically by the memory interface DoclD14952 Rev 9 13 91 Product overview STM8AF61xx STM8AF62xx 5 4 2 5 4 3 5 4 4 14 91 Write protection WP Write protection in application mode is intended to avoid unintentional overwriting of the memory The write protection can be removed temporarily by executing a specific sequence in the user software Protection of user boot code UBC If the user chooses to update the Flash program memory using a specific boot code to perform in application programming IAP this boot code needs to be protected against unwanted modification In the STM8A a memory area of up to 32 Kbytes can be protected from overwriting at user option level Other than the standard write protection the UBC protection can exclusively be modified via the debug interface the user software cannot modify the UBC protection status The UBC memory area contains the reset and interrupt vectors and
88. umulator push pop with direct stack access e Data transfer using the X and Y registers or direct memory to memory transfers DoclD14952 Rev 9 Ly STM8AF61xx STM8AF62xx Product overview 5 2 5 2 1 5 2 2 5 3 5 4 5 4 1 d Single wire interface module SWIM and debug module DM SWIM The single wire interface module SWIM together with an integrated debug module permits non intrusive real time in circuit debugging and fast memory programming The interface can be activated in all device operation modes and can be connected to a running device hot plugging The maximum data transmission speed is 145 bytes ms Debug module The non intrusive debugging module features a performance close to a full flavored emulator Besides memory and peripheral operation CPU operation can also be monitored in real time by means of shadow registers e R W of RAM and peripheral registers in real time e R W for all resources when the application is stopped e Breakpoints on all program memory instructions software breakpoints except the interrupt vector table e Two advanced breakpoints and 23 predefined breakpoint configurations Interrupt controller e Nested interrupts with three software priority levels e 21 interrupt vectors with hardware priority e Five vectors for external interrupts up to 34 depending on the package e Trap and reset interrupts Flash program and data EEPROM e 8 Kbytes to 32 Kbytes of medium densi
89. usy flag e Error flags Arbitration lost condition for master mode Acknowledgement failure after address data transmission Detection of misplaced start or stop condition Overrun underrun if clock stretching is disabled DoclD14952 Rev 9 21 91 Product overview STM8AF61xx STM8AF62xx 5 9 3 22191 e Interrupt Successful address data communication Error condition Wakeup from Halt e Wakeup from Halt on address detection in slave mode Universal asynchronous receiver transmitter with LIN support LINUART The devices covered by this datasheet contain one LINUART interface The interface is available on all the supported packages The LINUART is an asynchronous serial communication interface which supports extensive LIN functions tailored for LIN slave applications In LIN mode it is compliant to the LIN standards rev 1 2 to rev 2 1 Detailed feature list LIN mode Master mode e LIN break and delimiter generation e LIN break and delimiter detection with separate flag and interrupt source for read back checking Slave mode e Autonomous header handling one single interrupt per valid header D Mute mode to filter responses e Identifier parity error checking e LIN automatic resynchronization allowing operation with internal RC oscillator HSI clock source e Break detection at any time even during a byte reception e Header errors detection Delimiter too short Synch field error
90. ved 0x00 480D Flash wait 0x00 States NWAIT 480E NOPT7 Reserved STATE OxFF 0x00 480F Reserved OPT8 TMU KEY 1 7 0 0x00 OPT9 TMU KEY 2 7 0 0x00 OPT10 TMU_KEY 3 7 0 0x00 OPT11 TMU_KEY 4 7 0 0x00 OPT12 TMU_KEY 5 7 0 0x00 OPT13 TMU_KEY 6 7 0 0x00 OPT14 TMU_KEY 7 7 0 0x00 OPT15 TMU_KEY 8 7 0 0x00 2x00 OPT16 TMU_MAXATT 7 0 OxC7 4818 0x00 4819 Reserved to 487D 0x00 487E EN OPT17 BL 7 0 0x00 1 ox00 loader 487E NOPT17 NBL 7 0 OxFF 1 This option consists of two bytes that must have a complementary value in order to be valid If the option is invalid it has no effect on EMC reset J DoclD14952 Rev 9 43 91 Option bytes STM8AF61xx STM8AF62xx Table 18 Option byte description Option byte no Description ROP 7 0 Memory readout protection ROP OxAA Enable readout protection write access via SWIM protocol OPTO Note Refer to the STM8S and STM8A microcontroller families reference manual RM0016 section on Flash EEPROM memory readout protection for details UBC 5 0 User boot code area 0x00 No UBC no write protection 0x01 Page 0 to 1 defined as UBC memory write protected 0x02 Page 0 to 3 defined as UBC memory write protected SPI 0x03 to Ox3F Pages 4 to 63 defined as UBC memory write protected Note Refer to the STM8S and STM8A microcontroller families reference manual RM0016 section on Flash EEPROM write protection for more details AFR7 Alternat
91. w 0x00 weed aa Reserved area 11 bytes 0x00 5320 TIM3 CR1 TIM3 control register 1 0x00 0x00 5321 TIM3 IER TIMS interrupt enable register 0x00 0x00 5322 TIM3 SR1 TIMS status register 1 0x00 0x00 5323 TIM3 SR2 TIMS status register 2 0x00 0x00 5324 TIM3 EGR TIM3 event generation register 0x00 0x00 5325 TIM3 CCMR1 TIM3 capture compare mode register 1 0x00 0x00 5326 TIM3 CCMR2 TIM3 capture compare mode register 2 0x00 0x00 5327 TIM3 CCER1 TIM3 A AG enable register 0x00 0x00 5328 TIMS TIM3_CNTRH TIM3 counter high 0x00 0x00 5329 TIM3 CNTRL TIM3 counter low 0x00 0x00 532A TIM3 PSCR TIM3 prescaler register Ox00 0x00 532B TIM3 ARRH TIM3 auto reload register high OxFF 0x00 532C TIM3 ARRL TIM3 auto reload register low OxFF 0x00 532D TIM3 CCR1H TIM3 capture compare register 1 high 0x00 0x00 532bE TIM3 CCRIL TIM3 capture compare register 1 low 0x00 0x00 532F TIM3 CCR2H TIM3 capture compare register 2 high 0x00 0x00 5330 TIM3 CCR2L TIM3 capture compare register 2 low 0x00 E Se Reserved area 15 bytes 0x00 5340 TIM4 CR1 TIM4 control register 1 0x00 0x00 5341 TIM4 IER TIM4 interrupt enable register 0x00 0x00 5342 TIM4 SR TIM4 status register 0x00 0x00 5343 TIM4 TIM4 EGR TIM4 event generation register Ox00 0x00 5344 TIM4 CNTR TIM4 counter 0x00 0x00 5345 TIM4 PSCR TIM4 prescaler register 0x00 0x00 5346 TIM4 ARR TIM4 auto reload register OxFF EC Reserved area 185 bytes DoclD14952 Rev 9 37 91 Memory and register map STM8AF61xx STM8AF62xx
92. ween the datasheet and the STM8A S reference manual see Table 7 Table 7 ADC naming A Peripheral name in reference manual Peripheral name in datasheet RM0016 ADC ADC1 ADC features e 10 bit resolution e Single and continuous conversion modes e Programmable prescaler fmaster divided by 2 to 18 e Conversion trigger on timer events and external events e Interrupt generation at end of conversion e Selectable alignment of 10 bit data in 2 x 8 bit result register e Shadow registers for data consistency e ADC input range VssA lt Vin lt VppA e Analog watchdog e Schmitt trigger on analog inputs can be disabled to reduce power consumption e Scan mode single and continuous e Dedicated result register for each conversion channel e Buffer mode for continuous conversion An additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog Values converted from AIN12 are stored only into the ADC DRH ADC DRL registers Communication interfaces The following sections give a brief overview of the communication peripheral Some peripheral names differ between the datasheet and the STM8A S reference manual see Table 6 Table 8 Communication peripheral naming correspondence Peripheral name in reference manual Peripheral name in datasheet RM0016 LINUART UART2 d DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Product overview 5 9 1 5 9 2 d Serial peripheral inte
93. wise specified all typical curves are given only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6 Figure 6 Pin loading conditions STMBA pin 50 pF DoclD14952 Rev 9 47 91 Electrical characteristics STM8AF61xx STM8AF62xx 10 1 5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7 Figure 7 Pin input voltage STMBA pin 10 2 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 19 Voltage characteristics Symbol Ratings Min Max Unit Vppx Vss Supply voltage including Vppa and Vppio Input voltage on true open drain pins PE1 PE2 2 ViN Input voltage on any other pinf IVoox Vool Variations between different power pins IVssx Vss Variations between all the different ground pins see Absolute maximum ratings VESD Electrostatic discharge voltage electrical sensitivity on page 73 1 All power Vpp Vppio VppA and ground Vss Vssio Vssa pins must always be connected to the external power supply 2 linypiny must never be exceeded This is implicit
94. x00 50BF Reserved area 12 bytes 0x00 50C0 T CLK ICKR Internal clock control register 0x01 0x00 50C1 CLK ECKR External clock control register 0x00 0x00 50C2 Reserved area 1 byte 32 91 d DoclD14952 Rev 9 STM8AF61xx STM8AF62xx Memory and register map Table 13 General hardware register map continued Address Block Register label Register name Reset status 0x00 50C3 CLK_CMSR Clock master status register OxE1 0x00 50C4 CLK SWR Clock master switch register OxE1 0x00 50C5 CLK SWCR Clock switch control register OxXX 0x00 50C6 Aix CLK_CKDIVR Clock divider register 0x18 0x00 50C7 CLK PCKENR1 Peripheral clock gating register 1 OxFF 0x00 50C8 CLK CSSR Clock security system register 0x00 0x00 50C9 CLK CCOR Configurable clock control register 0x00 0x00 50CA CLK PCKENR2 Peripheral clock gating register 2 OxFF 0x00 50CB Reserved area 1 byte 0x00 50CC CLK HSITRIMR HSI clock calibration trimming register 0x00 CLK 0x00 50CD CLK SWIMCCR SWIM clock control register DEEN 0x00 50CE to 0x00 50D0 Reserved area 3 bytes 0x00 50D1 WWDG CR WWDG control register Ox7F WWDG 0x00 50D2 WWDG WR WWDR window register Ox7F 0x00 50D3 to 0x00 50DF Reserved area 13 bytes 0x00 50E0 IWDG KR IWDG key register 0xxx 2 0x00 50E1 IWDG IWDG PR IWDG prescaler register 0x00 0x00 50E2 IWDG RLR IWDG reload register OxFF 0x00 50E3 to 0x00 50EF Reserved area 13 bytes 0x00 50F0 AWU CSR1 A
95. y error 0 7 1 5 Total unadjusted error 1 9 4 40 LSB Offset error 130 40 Gain error fapc 4 MHz 0 6 3 Differential linearity error 1 54 2 4 JELI Integral linearity error 1 20 1 50 Max value is based on characterization not tested in production 2 ADC accuracy vs injection current Any positive or negative injection current within the limits specified for IiNj piN and linypin in Section 10 3 6 does not affect the ADC accuracy TUE 2LSB can be reached on specific salestypes on the whole temperature range Target values Figure 41 ADC accuracy characteristics 1LSB DDA SSA 0 1 2 3 4 5 6 7 1021102210231024 Vssa DDA 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line Er Total unadjusted error Maximum deviation between the actual and the ideal transfer curves Eo Offset error Deviation between the first actual transition and the first ideal one Eg Gain error Deviation between the last ideal transition and the last actual one Ep Differential linearity error Maximum deviation between actual steps and the ideal one E 7 Integral linearity error Maximum deviation between any actual transition and the end point correlation line d DoclD14952 Rev 9 71 91 Electrical characteristics STM8AF61xx STM8AF62xx 10 3 12 72 91 EMC characteristics Susceptibility tests are performed on a sample basis durin
96. ymbol Parameter Conditions Min Typ Max Unit fapc ADC clock frequency 111 kHz 4 MHz kHz MHz VDDA Analog supply 3 E 5 5 Vrer Positive reference voltage VDDA VREF Negative reference voltage 0 5 V VDDA VAIN Conversion voltage range Devices with external Vpep VREF Veer pins Csamp Internal sample and hold capacitor 3 pF 1 Sampling time fApc 2 MHz E ts 3 x 1 fapc fapc 4 MHz 5 fADC 2MHz teTAB Wakeup time from standby us fADC 4MHz Total conversion time including fapc 2 MHz tcony sampling time 14 x 1 fapc fapc 4 MHz z Rswitch 30 kQ 1 During the sample time the sampling capacitance Csamp 3 pF typ can be charged discharged by the external source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within ts After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result Figure 40 Typical application with ADC Von STM8A Rswitch NG conversion Cain T Csamp 1 Legend Rain external resistance Cay capacitors Csamp internal sample and hold capacitor 70 91 DoclD14952 Rev 9 Ly STM8AF61xx STM8AF62xx Electrical characteristics Table 43 ADC accuracy for Vppa 5 V Symbol Parameter Conditions Typ Max Unit Total unadjusted error Offset error 0 8 3 Gain error fApc 2 MHz 0 1 2 Epl Differential linearity error 0 9 1 IE Integral linearit

Automotive 8-bit MCU, with up to 32 Kbytes Flash, data EEPROM

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