XEM3010 User`s Manual
Contents
1. a 583000 33 90 olman E S E O casuo ww ceo 080 28 3000 wwo O O xuw veuso O O veusa ww O seuss wwz vws O xeuss S S S vw seuss xeusr vus O O veusr mus xeuse vwe veuse wwo O xeusea vwo O O wwz xeusis wwz 0 O vws mw O vws O O mws O vws O vevaz mwe 0 O xeune wwe O wwo 66 73 wan svecas 000006 O exo 72 mwm O ewa O vua wwz O xeuezs wuz O veuens 88 88 2 80 Lo 1 2 71 12 m L Eas 88 30 xuez vwx vexeas xsuszr yeuszs O eves O wwz yeusz0 O wuwa 039 wwz Olmus vun O veuses xeussr veusss O O veca 900007 osx O xevess www O O raves ww wusa O xsue s wwen O O www veusas veus dci aloes ost xeuses wz O vws 5 19 vus O O veusss CN Galas fOpal Kelly gosse 8809010 20051027 0 10 146 2 54 AN 150 All dime2. continuous current Itis unlikely that the XEM3010 will consume this much current so much of this power will be available to expansion devices using the expansion connectors DC Power Connector The DC power connector on the XEM3010 is part number PJ 102A from CUI Inc It has a stan dard 2 1mm 5 5mm power jack The outer ring is attached to DGND The center pin is attached 6 www opalkelly com XEM3010 User s Manual to VDC on expansion connector JP3 as well as the inputs to the two switching regulators on the XEM3010 Expansion Bus Power The expansion bus has pins for VDC 3 3V and 1 2V making it flexible for nearly any supply scenario In particular the following scenarios have been considered e VDC is provided to an expansion device which use or regulate it as necessary e VDC is provided by an expansion device to power the XEM3010 e 3 3V and or 1 2V are provided to expansion devices as regulated reliable supplies e 3 3V and or 1 2V are provided by an expansion device to power the XEM3010 In this case the switching regulators on the board must be removed This option may be useful to applications where a switching supply is not desired USB Bus Power The USB 2 0 specification allows for up to 2 5 W 500mA at 5v to be provided to external periph erals over the USB cable While power consumption of an unconfigured XEM3010 is quite low due to the flexibility allowed in FPGA design the Spartan 3 and SDRAM
3. could easily consume over 2 5 W during operation with a user design thus violating the USB specification However to support users who may not be consuming that much power in their design and who may still wish to use the XEM3010 in a bus powered situation we have provided a solder jumper J3 on the bottom of the XEM3010 WIth a bead of solder in place across this jumper the USB 5V is connected to VDC Before relying on USB power you should be aware of the limitations and the fact that using USB power may render the XEM3010 a USB noncompliant device Supply Heat Dissipation IMPORTANT Due to the limited area available on the small form factor of the XEM3010 and the density of logic provided heat dissipation may be a concern This depends entirely on the end application and cannot be predicted in advance by Opal Kelly Heat sinks may be required on any of the devices on the XEM3010 Of primary focus should be the FPGA U11 the two switching power supplies U1 U2 and the SDRAM U14 Although the two switching supplies are high efficiency they are very compact and consume a small amount of PCB area for the current they can provide If you plan to put the XEM3010 in an enclosure be sure to consider heat dissipation in your de sign USB 2 0 Interface The XEM3010 uses a Cypress CY7C68013A FX2LP USB microcontroller to make the XEM a USB 2 0 peripheral As a USB peripheral the XEM is instantly recognized as a plug and play peri
4. debounced on the XEM3010 In order to deglitch the signals from the pushbuttons proper debouncing should be done inside the FPGA Reconfiguration Using S1 When a jumper is installed across J2 51 is electrically connected to the PROG_B pin on the FPGA In this configuration S1 may be used to force the FPGA to reprogram itself using the im age in PROM Note that this mode is only available when the XEM3010 is configured for PROM configuration of the FPGA When the XEM3010 is configured for USB configuration no jumper should be installed across J2 www opalkelly com 13 XEM3010 User s Manual PLL Connections JTAG JP1 JTAG Connector 14 The PLL contains six output pins one of which is left unconnected The other five are labelled SYS CLK1 through SYS CLK5 SYS CLKA connects to JP2 and SYS CLK5 connects to The other three pins are connected directly to the FPGA The pin mapping table below details the PLL connections PLL Pin Clock Name SYS_CLK1 FPGA N9 CLKB SYS CLK2 FPGA P9 SDRAM Clock The SDRAM clock pin U14 F2 is connected to SYS CLK1 which is CLKA on the Cypress CY22393 PLL U8 10 Note that this connection is shared with FPGA GCLK3 U11 N9 JP1 is the 2mm 6 pin JTAG connector on board and connects to the on board JTAG chain which includes the FPGA configuration PROM and expansion connector These pins can be con nected to an external JTAG command converter such as the Xilinx JTAG cables
5. more information on this please refer to the Xilinx Answer Record and other references avail able within that record Power On I O State PCB revision 20070117 In all versions of the XEM3010 PCB prior to 20070117 YY YYMMDD datecode the HSWAP EN pin E6 on the FPGA was directly connected to DGND This enables pull up resistors on all User I Os from power on throughout configuration See the Spartan 3 Data Sheet from Xilinx With version 20070117 a 0 Q resistor has been added R43 By default this resistor IS NOT LOADED This resistor connects HSWAP_EN to DGND Therefore for version 20070117 there are two possible configurations Remove R43 Default Configuration HSWAP allowed to float and an internal pull up pulls HSWAP EN high This disables the user I O pull up resistors allowing the I Os to float from power on throughout configuration www opalkelly com 17 XEM3010 User s Manual 18 Insert R43 0 O Resistor HSWAP is grounded This enables user I O pull up resistors from power on throughout con figuration See the Xilinx Spartan 3 Data Sheet for details regarding the characteristics of these pull ups Considerations for Differential Signals The XEM3010 PCB layout and routing has been designed with several applications in mind including applications requiring the use of differential LVDS pairs Please refer to the Xilinx Spartan 3 datasheet for details on using differential I O standards with th
6. you created in the previous step to the XCFO8P device You may bypass the XC381500 device since we will only be configuring the PROM Program the PROM Once a configuration file has been assigned to the PROM device you will be able to program it by right clicking on the device and selecting Program from the context menu In the options dialog setup the following options e Select Rev 0 and ER to erase any existing configuration e PROM is Configuration Master Internal Clock e Clock Frequency set to 40 MHz e Configuration is Serial Mode www opalkelly com 21 XEM3010 User s Manual 22 Advanced PROM Programming Options Denon and Cocke Selec Fen and Ender Catone Code Hie Das Desayi Head Woe Erase Free Hurra Cuore Protect Check Code Ret RP Wr If ER VAR FRC nei sur rar Tap Owe rn FRPP we F lo Dung Configuration Configuration T Sawn estery Serial Mode Te PROH 2 Confiquention Maher areri clock source Temm um O Extemal Clock Erber B Hex Digis IT Clock Dock Frequency 40 MHz Once you acknowledge this dialog the programming operation will start Once complete the PROM should be setup with your new FPGA programming file Booting from PROM In order to boot the XEM3010 from PROM
7. you must remove the jumper on J1 This allows the PROM to configure the FPGA from power on If your FPGA design has MUXSEL 0 the design will still be able to communicate with FrontPanel if it is connected to a PC www opalkelly com XEM3010 User s Manual Statement of Volatility The devices listed below are the non volatile memory devices on the XEM3010 which retain their contents after power is removed All other memory devices on the XEM3010 lose their contents after a short period without power U6 Firmware EEPROM This is a 64 KiB kibibyte non volatile EEPROM that stores the FrontPanel firmware PLL set tings and a 32 byte device ID string The FrontPanel firmware is Opal Kelly proprietary and cannot be removed without affecting functionality PLL settings and Device ID would not typi cally contain anything confidential proprietary or secure but may be reset by the user using FrontPanel software Sanitization Procedure The PLL settings may be reprogrammed using the FrontPanel software The Device ID string may be reprogrammed using the FrontPanel software U10 Xilinx Platform Flash XEM3010 1500P only This is a 1 MiB mebibyte non volatile PROM that may optionally store a Xilinx bitfile Sanitization Procedure This PROM may be erased using the Xilinx iMPACT software JTAG It may not be erased using FrontPanel software Please refer to the Xilinx iMPACT documentation on the proper use of their JTAG capabl
8. 1 R12 112 v4 U4 EDS cur Each of the samples installed with FrontPanel includes copy of a template constraints file that lists all the XEM3010 pins and maps them to the appropriate FPGA pins using LOC location constraints You can use this template to quickly get the pin locations correct on a new design MUXSEL MUXSEL is a signal on the XEM3010 which selects the signal path to the FPGA programming signals DO and CCLK When low deasserted the FPGA and USB microcontroller are connect ed When high asserted the and PROM are connected In normal USB programmed operation J1 is inserted pulling MUXSEL low and connecting the FPGA and USB microcontroller at all times This allows USB based programming of the FPGA and subsequent USB communication with the FPGA design after configuration In order to allow the PROM to configure the FPGA J1 must be removed In order to deassert MUXSEL post configuration your design must deassert MUXSEL This allows the FPGA design to properly startup and allows for communication over USB even after the PROM has configured it The end result is that your FPGA design should tie HI_MUXSEL to 0 This is the case regardless of how the design was configured via PROM or USB and even if you have a PROM less version of the XEM3010 For example in Verilog assign hi_muxsel 1 0 Connections The FPGA on the XEM3010 is at
9. 7 s Opal Kelly XEMS3010 User s Manual A compact 75mm x 50mm integration board featuring the Xilinx Spartan 3 FPGA and on board SDRAM The XEM3010 is a compact USB based FPGA integration board featuring the Xilinx Spartan 3 FPGA 32 MB 16 bit wide SDRAM high efficiency switching power supply Xilinx configuration PROM and two high density 0 8 mm expansion connectors The USB 2 0 interface provides fast configuration down loads and FPGA PC communication as well as easy access with our popular FrontPanel software and developer s API An on board clock generation device has three independent PLLs and five flexible outputs available to the FPGA SDRAM and expansion connectors Software documentation samples and related materials are Copyright 2006 2014 Opal Kelly Incorporated Opal Kelly Incorporated Portland Oregon http www opalkelly com All rights reserved Unauthorized duplication in whole or part of this document by any means except for brief excerpts in published reviews is prohibited without the express written permission of Opal Kelly Incorporated Opal Kelly the Opal Kelly Logo and FrontPanel are trademarks of Opal Kelly Incorporated Linux is a registered trademark of Linus Torvalds Microsoft and Windows are both registered trademarks of Microsoft Corporation All other trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed Revision History
10. DRAM XCFO8P MT48LC16M16 l Spartan 3 FPGA Host Interface XC3S1 000 4FG320 Bus PLL or XC3S1500 4FG320 1010 CY22393 2 Pushbuttons i 8 LEDs 1PLLCLK 1 PLLCLK gt YBUS JP3 Power Supply The XEM3010 is designed to be operated from one of three power sources depending on user requirements One of these three sources provides power for the two high efficiency switching regulators on board to provide 3 3v and 1 2v 2 5v and 1 8v are derived from the 3 3v supply us ing small low dropout LDO regulators The three sources and the respective XEM3010 configuration for each are shown in the table below In all configurations the XEM3010 requires a clean well regulated supply between 4 5v and 5 5v XEM3010 Configuration DC Power Jack P1 No configuration is required Attach a DC power source to P1 that supplies a clean regulated voltage of 4 5v to 5 5v Expansion Connector No configuration is required Provide a clean regulated voltage of JP3 4 5v to 5 5v to the VDC pins on JP3 USB Bus Power See section on USB Bus Power IMPORTANT NOTE Only one power source should be connected at any time Attaching mul tiple power sources could damage the XEM3010 and possibly the power source and void the warranty on the XEM3010 There two switching regulators on board one for the 3 3v supply and one for the 1 2v supply Each supply has been designed to provide up to 3 A of
11. Date Descipion o Added SDRAM to FPGA pin connections 20070221 Added note about BRK3010 connections 20070604 Added note about R43 on PCB revision 20070117 20070226 Updated host interface pin list 20070519 Added note regarding heat dissipation Contents Introducing the XEM3010 5 POBTOOUD BD ua hah de ed dE epus 5 BRK3010 Breakout Board 5 Functional Block 6 Power SUDO tone Sea 6 DC Power COnHRector oorr te 6 Expansion Bus Power 7 USB Bus POWOI RR PER T Supply Heat Dissipation 7 USB 20 Ite face Lac 1m a Toe HUP Poe GH OA T On board 8 Seal EEPROM 522 2 9 92209 19 2S bU QT RE OT 8 Cypress G122999 PLL aai tented acies 8 Xilinx Configuration PROM 8 32 MByte Word Wide Synchronous DRAM 8 LEDS and Puslibuttoris 8 Expansion Connectors a dees gana is a e RU e ois 8 FrontPanel Suppoll ouai de 9 Programmer s 1 9 Applying the XEM3010 11 Host Interface iussa ke ERR Ru RE RSS DE 11 orato dos etos eto 12 PC CONNECTIONS nt
12. a compact 75mm x 50mm 2 95 x 1 97 FPGA board featuring the Xilinx Spartan 3 FPGA Designed as a full featured integration system the XEM3010 provides access to over 110 I O pins on its 320 pin Spartan 3 device and has a 32 MByte SDRAM available to the FPGA The XEM3010 is designed to work with small to medium sized FPGA designs with a wide variety of external interface requirements PCB Footprint A mechanical drawing of the XEM3010 is shown at the end of this manual The PCB is 75mm x 50mm with four mounting holes spaced as shown in the figure These mounting holes are electrically isolated from all signals on the XEM3010 The two connectors USB and DC power overhang the PCB by approximately 4mm in order to accomodate mounting within an enclosure The XEM3010 has two high density 80 pin connectors on the bottom side which provide access to many FPGA pins power JTAG and the microcontroller s I2C interface BRK3010 Breakout Board A simple breakout board the BRK3010 is provided as an optional accessory to the XEM3010 This breakout board provides easy access to the high density connectors on the XEM3010 by routing them to lower density 0 1 spaced thru holes The breakout board also provides a conve nient reference for building boards that will mate to the XEM3010 A mechanical drawing of the BRK3010 is also shown at the end of this document www opalkelly com 5 XEM3010 User s Manual Functional Block Diagram PROM S
13. ally for pins routed to differential pair I Os on the FPGA the FPGA signal names and routed track lengths have been provided to help you equalize lengths on differential pairs Setting I O Voltages The Spartan 3 FPGA allows users to set I O bank voltages in order to support several different I O signalling standards This functionality is supported by the XEM3010 by allowing the user to connect independent supplies to the VCCO pins on four of the FPGA banks By default ferrite beads have been installed which attach each VCCO bank to the 3 3VDD supply If you intend to supply power to a particular I O bank you MUST remove the appropriate ferrite beads Power can then be supplied through the expansion connectors The table below lists details for user supplied I O bank voltages I O Bank FPGA Pins Ferrite Bead 2 pese J12 H12 F16 N16 L12 K12 K7 L7 N3 FB4 JP3 56 F3 H7 J7 FB5 Clock Inputs and Bank Voltages Note that the four clock inputs available on the expansion connectors are connected to FPGA banks 0 and 1 Bank voltages for these two banks are fixed on the XEM3010 to 3 3VDD How ever Xilinx Answer Record 18095 states Differential Input Buffers are powered by VCCAUX and are not VCCO depen dent Consequently you can put LVDS_25 LVPECL 25 input buffers in a 3 3V bank without damaging the device Instantiating LVDS_25 or LVPECL 25 input buffer in 3 3V bank does not generate a software error For
14. d 79 of this connector are wired to global clock inputs on the FPGA and can therefore be used as inputs to the global clock network Pin 11 on this connector is SYSCLKA and is directly connected to CLKD on the Cypress CY22393 PLL Using FrontPanel s PLL Configuration Dialog you can configure the clock signal present on this pin Pin mappings for JP2 are listed at the end of this document in the Quick Reference section For each JP2 pin the corresponding board connection is listed For pins connected to the FPGA the corresponding FPGA pin number is also shown Finally for pins routed to differential pair Os on the FPGA the FPGA signal names and routed track lengths have been provided to help you equalize lengths on differential pairs JP3 is an 80 pin high density connector providing access to FPGA Banks 6 and 7 Pins 77 and 79 of this connector are wired to global clock inputs on the FPGA and can therefore be used as inputs to the global clock network Pin 8 on this connector is SYSCLK5 and is directly connected to CLKE on the Cypress CY22393 PLL Using FrontPanel s PLL Configuration Dialog you can configure the clock signal present on this pin www opalkelly com XEM3010 User s Manual Pin mappings for JP3 are listed at the end of this document in the Quick Reference section For each JP3 pin the corresponding board connection is listed For pins connected to the FPGA the corresponding FPGA pin number is also shown Fin
15. e Spartan 3 FPGA FPGA I O Bank Voltages In order to use differential I O standards with the Spartan 3 you must set the VCCO voltages for the appropriate banks to 2 5v according to the Xilinx Spartan 3 datasheet Please see the sec tion above entitled Setting I O Voltages for details Characteristic Impedance The characteristic impedance of all routes from the FPGA to the expansion connector is 50 O with the exception of routes that are labelled with T in the mapping table These exception routes are routed on inner layers without a proximity ground plane and therefore do not match the 50 O impedance exactly Differential Pair Lengths In many cases it is desirable that the route lengths of a differential pair be matched within some specification Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible We have also included the lengths of the board routes for these connections to help you equalize lengths in your final application Due to space con straints some pairs are better matched than others Digitally Controlled Impedance The Xilinx Spartan 3 supports digitally controlled impedance This functionality is supported when precision resistors are connected externally between the FPGA VRN VRP lines and VCCO DGND respectively Pads for these resistors have been placed and routed on the XEM3010 but resistors have NOT been installed The end user mus
16. for additional programming capability The JP1 pins are connected as shown below apt Pin Signa 2 ws TD 5 JTAG Connection Chain The JTAG chain is configured as shown in the diagram below The PROM and expansion port of this chain may be bypassed using optional resistors as shown R16 bypasses the PROM and has been inserted on PROM less versions of the XEM3010 R16 is not inserted on XEM3010 versions with the PROM R30 bypasses the expansion connector and has been inserted on all versions of the XEM3010 If your application places additional components in the JTAG chain you must remove R30 Note that the JTAG signal level on the XEM3010 is 2 5 v If your expansion board extends this chain it must also operate at 2 5 v or use level translation to be compatible www opalkelly com TDI 2 9 TDO JP2 8 SDRAM Connections TDO TDI JP 1 4 XEM3010 User s Manual PROM TDI 816 The Micron SDRAM is connected exclusively to the 3 3v I O on Bank 0 and Bank 1 of the FPGA The tables below list these connections paw os Clock Configuration The XEM3010 has been designed to support SDRAM clocking in both system synchronous p fa ps b po c pp p fe p fe and source synchronous modes Both configurations are often referenced in Xilinx application notes describin
17. g SDRAM controllers and interfaces www opalkelly com 15 User s Manual System Synchronous In this mode the clock signal is sourced at the system level by the PLL on the XEM3010 The same clock is fanned out to both the FPGA pin N9 and the SDRAM CLK The FPGA there fore considers this signal an input and synchronizes its logic fabric to it typically using a DCM Source Synchronous In this mode the clock signal is sourced by the FPGA rather than the PLL To avoid signal con tention the corresponding output SYS_CLK1 on the PLL must be disabled or increased power consumption and potential damage may be done The FPGA pin 9 is configured as an output and provides the clock signal to the SDRAM Typi cally this setup uses the DDR features of the IOB to provide a clock that is well synchronized with the signals output to and input from the SDRAM thus minimizing signal skew with respect to the clock Expansion Connectors 16 JP2 JP3 Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly FPGA integration modules It provides additional information on pin capabilities pin character istics and PCB routing Additionally Pins provides a tool for generating constraint files for place and route tools Pins can be found at the URL below http www opalkelly com pins JP2 is an 80 pin high density connector providing access to FPGA Banks 2 and 3 Pins 77 an
18. ity to clear this PROM www opalkelly com 23 XEM3010 User s Manual XEM3010 Mechanical Drawing 50 00 47 00 47 00 42 33 34 50 18 90 3 00 3 00 2 33 0 0 eo ee 45 00 9e ao Re TUS Ll Bs 99 k 88 g _ ger ep 62910510 Cow Eo S aus REM 4 13 12 60 f7 310 1 57 0 7 All dimensions in mm 24 www opalkelly com XEM3010 User s Manual BRK3010 Mechanical Drawing O N cw ME NE e O ON ON OO ot AN OR Oo A x e gt o 3 52 50 4 TPA TPS m UP9 PO P N 24 80 samo ow ome saa O 32 27 saam O O sa se 20 90 olo f aloj seue E E S
19. nsions in mm inches www opalkelly com 25
20. nual 10 www opalkelly com XEM3010 User s Manual Applying the XEM3010 Host Interface There are 26 pins that connect the on board USB microcontroller to the FPGA These pins com prise the host interface on the FPGA and are used for configuration downloads After configura tion these pins are used to allow FrontPanel communication with the FPGA If the FrontPanel okHostInterface module is instantiated in your design you must map the in terface pins to specific pin locations using Xilinx LOC constraints This may be done using the Xilinx constraints editor or specifying the constraints manually in a text file An example is shown below Xilinx constraints for okHostlnterface pin mappings www opalkelly com 11 XEM3010 User s Manual 12 hi in 0 hi lt 1 gt hi in 2 hi in lt 3 gt hi in 4 hi in lt 5 gt hi in 6 hi in lt 7 gt hi out 0 hi_out lt 1 gt hi inout lt gt hi inout lt 1 gt hi inout lt 2 gt hi inout lt 3 gt hi inout lt 4 gt hi inout lt 5 gt hi inout lt 6 gt hi inout lt 7 gt hi inout lt 8 gt hi inout lt 9 gt hi_inout lt 10 gt hi inout lt 11 gt hi inout lt 12 gt hi inout lt 13 gt hi inout lt 14 gt hi inout lt 15 gt N10 2 855 185 eye Ve v10 E EDS ERIS v9 u9 Spa N1
21. pheral on millions of PCs More importantly FPGA downloads to the XEM happen blazingly fast virtual instruments under FrontPanel update quickly and data transfers are much faster than the parallel port interfaces common on many FPGA experimentation boards www opalkelly com 7 XEM3010 User s Manual On board Peripherals The XEM3010 is designed to compactly support a large number of applications with a small num ber of on board peripherals These peripherals are listed below Serial EEPROM A small serial EEPROM is attached to the USB microcontroller on the XEM3010 but not directly available to the FPGA The EEPROM is used to store boot code for the microcontroller as well as PLL configuration data and a device identifier string The PLL configuration data is loaded from EEPROM and used to reconfigure the PLL each time a new configuration file is loaded to the FPGA Therefore stable and active clocks will be pres ent on the FPGA pins as soon as it comes out of configuration The stored PLL configuration may be changed at any time using FrontPanel s PLL Configuration Dialog The EEPROM also stores a device identifier string which may be changed at any time using FrontPanel The string serves only a cosmetic purpose and is used when multiple XEM devices are attached to the same computer so you may select the proper active device Cypress CY22393 PLL A multi output triple PLL clock generator can provide up to five clocks three to
22. r is already familiar with this procedure and it will not be covered here Generate a PROM Programming File In this step the Xilinx iMPACT tool is used to format a PROM programming file with the FPGA programming file created previously In the next step the PROM programming file will be trans ferred e g via JTAG to the PROM Start IMPACT Once the FPGA programming file bitfile has been created you can start iMPACT from within Project Navigator by clicking on Generate PROM ACE or JTAG File in the processes list Tipe Lig sign Cia Generate Programming File E gf Programming File Generation Report Generate PROM ACE o JTAG Fila Configure Device IMPACT This will start IMPACT When asked tell it you would like to create a PROM File www opalkelly com 19 XEM3010 User s Manual Setup PROM File Format At the next screen select Xilinx PROM as a target with the MCS format Here you can also specify a filename for your programming file ward t target f knee Generic Parallel PROM File Feemat amp MES C TEK C C EM C HEX C BIN C 5 Checkrum Fil Value 2 Hex Digi FF PROM File CourtersPROM Locahonc e Nace Select the PROM Device At the next screen check Enable Revisioning This is necessary in order to enable some features of the Xilinx PROM that allow it to boot the FPGA as a programming master Select the PROM de
23. s oa durs cade aries 12 LEDs and PUShbUttons 5 2 cca ees eos rrente sered 13 Reconfiguration Using 51 13 PEL COMMECUOMS 2 2 025 1539 14 SDRAM GIOGK eati tech 14 14 JP1 JTAG 14 JTAG Connection 14 SDRAM Connections dit 15 Clock Configuration eunte erg 15 Expansion 5 16 PD T O 16 dc UR 16 Setting VO Voltages 2 22 ep bed ucro 17 Power On I O State PCB revision 20070117 17 Considerations for Differential Signals 18 BRK3010 Breakout 19 Xilinx Configuration 19 Generate FPGA Programming File 19 Generate a PROM Programming File 19 Programming the Configuration PROM 21 Booting from PROM das tnd Boole 22 Statement of 23 U6 Firmware EEPROM 23 XEM3010 User s Manual U10 Xilinx Platform Flash XEM3010 1500P only 23 XEM3010 Mechanical Drawing BRK3010 Mechanical Drawing www opalkelly com XEM3010 User s Manual Introducing the XEM3010 The XEM3010 is
24. t install these resistors in order to use DCI The table below lists the resistor designators and the banks they control Resistor FPGAPin FPGA Signal Connection www opalkelly com XEM3010 User s Manual BRK3010 Breakout Board The BRK3010 is a simple two layer breakout board which can be used to evaluate or transi tion to the XEM3010 It provides standard 0 1 thru hole connections to the 0 8 mm high density connectors on the XEM3010 Please visit the Pins reference for the XEM3010 for pin mapping details Schematics and layout files for the BRK3010 are available on the Opal Kelly website Xilinx Configuration PROM Some versions of the XEM3010 are built with a Xilinx configuration PROM inserted This PROM allows the FPGA to be configured upon power up without a USB connection as some applica tions may require the FPGA to control a user s device and only occasionally be connected to a PC The USB connection may therefore be used for extracting acquired data adjusting param eters and so on Getting the XEM3010 to boot from a PROM based FPGA configuration is a multistep process consisting of the following steps 1 Generate an FPGA programming file 2 Generate a PROM programming file from the FPGA programming file 3 Program the PROM Generate an FPGA Programming File This step is performed for either PROM boot or USB boot and is the final step in a typical FPGA synthesis flow It is assumed that the use
25. t number BSE 040 01 F D A The table below lists the appropriate Samtec mating connectors along with the total mated height 8 www opalkelly com XEM3010 User s Manual Samtec Part Number Mated Height BTE 040 01 F D A 5 00mm 0 197 BTE 040 02 F D A 8 00mm 0 315 BTE 040 03 F D A 11 00mm 0 433 BTE 040 04 F D A 16 10mm 0 634 BTE 040 05 F D A 19 10mm 0 752 FrontPanel Support The XEM3010 is fully supported by Opal Kelly s FrontPanel software FrontPanel augments the limited peripheral support with a host of PC based virtual instruments such as LEDs hex displays pushbuttons toggle buttons and so on Essentially this makes your PC a reconfigu rable I O board and adds enormous value to the XEM3010 as an experimentation or prototyping system Programmers Interface In addition to complete support within FrontPanel the XEM3010 is also fully supported by the FrontPanel programmer s interface API a powerful C class library available to Windows and Linux programmers allowing you to easily interface your own software to the XEM In addition to the C library wrappers have been written for Java and Python making the API available under those languages as well Java and Python extensions are available under Win dows and Linux Sample wrappers are also provided for Matlab and LabVIEW Complete documentation and several sample programs are installed with FrontPanel www opalkelly com 9 XEM3010 User s Ma
26. tached to the lines from the USB microcontroller In order to avoid contention with the I C bus these lines should be set to high impedance within your design If this is not done FrontPanel may timeout or hang when trying to communicate with the XEM3010 particularly when programming the on board PLL www opalkelly com XEM3010 User s Manual The following lines in your UCF contraints file will attach pull ups to the lines i2c scl LO NET i2c sda LO U13 PULLUP R13 PULLUP In addition you will need to set these signals to high impedance in your HDL Here is exam ple of how to do this in Verilog assign i2c_sd a 1 bz assign i2c_scl 1 bz LEDs and Pushbuttons There are eight LEDs and two pushbuttons on the XEM3010 Each is wired directly to the FPGA according to the table below p fus p vy fue The LED anodes are connected to a pull up resistor to 3 3VDD and the cathodes wired directly to the FPGA To turn ON an LED the FPGA pin should be brought low To turn OFF an LED the FPGA pin should be brought high Button FPGA Pin The pushbuttons are connected between their respective FPGA pin and DGND The FPGA side of the connection has a pull up resistor to 2 5VDD Therefore in the pressed state the FPGA pin will be at DGND low and in the unpressed state the FPGA pin will be at 2 5VDD high Note that the pushbuttons are not
27. the FPGA and another two to the expansion connectors JP2 and JP3 The PLL is driven by a 48 MHz signal output from the USB microcontroller The PLL can output clocks up to 150 MHz and is config ured through the FrontPanel software interface or the FrontPanel API Xilinx Configuration PROM An 8 Mbit Xilinx PROM XCFO8P is included on some variants of the XEM3010 This PROM allows the XEM3010 to operate without its USB tether by automatically configuring the on board FPGA during power up This PROM may be programmed over the board s JTAG port using a Xilinx configuration cable and the iMPACT software 32 MByte Word Wide Synchronous DRAM The XEM also includes a 32 MByte SDRAM with a full 16 bit word wide interface to the FPGA This SDRAM is attached exclusively to the FPGA and does not share any pins with the expan sion connector The maximum clock rate of the SDRAM is 133 MHz The SDRAM is a Micron MT48LC16M16A2BG 75 D or compatible LEDs and Pushbuttons Eight LEDs and two pushbuttons are available for general use as debug inputs and outputs Expansion Connectors Two high density 80 pin expansion connectors are available on the bottom side of the XEM3010 PCB These expansion connectors provide user access to several power rails on the XEM3010 two clock generator outputs four FPGA clock inputs the USB microcontroller 12C lines the JTAG chain and 116 non shared I O pins on the FPGA The connectors on the XEM3010 are Samtec par
28. vice as xcf08p the device on the XEM3010 and add it to the list Auto Select PROM iv Enable Revicioning Humber ol Enable Comprercion Select aPROM me adi Position Pat Hane 0 20 www opalkelly com XEM3010 User s Manual Add Bitfiles to PROM The final step in creating the PROM is to add your bitfile to the PROM Simply select the file e g counters bit that you generated previously Once you complete the Wizard the MCS program ming file will be created in the directory specified In our case we have CountersPROM mcs Programming the Configuration PROM Once we have a PROM programming file we can transfer that file to the Xilinx Configuration PROM on the XEM3010 using a JTAG cable The Xilinx Parallel IV or Xilinx USB JTAG cables will work just fine for this process Connecting to the JTAG Chain At this point you may attach your programming cable to the XEM3010 Be sure to connect the pins correctly or you could damage the XEM3010 or the programming cable If you are still in iMPACT you can switch to Configuration Mode using the Mode menu at the top of the window Allow iMPACT to automatically discover the JTAG chain and you will end up with a graphical representation of the chain TDI xci Ein File Fle TRO Assign the PROM Configuration File Assign the PROM configuration file CountersPROM mcs that
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