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8XC196NP, 80C196NU Microcontroller User`s Manual

1. Shift Direct Immediate Indirect Indexed Mnemonic Length Opcode Length Opcode Length Opcode Length Opcode NORML 3 SHL 3 09 SHLB 3 19 SHLL 3 oD SHR 3 08 SHRA 3 0A SHRAB 3 1A SHRAL 3 SHRB 3 18 SHRL 3 0 Special Direct Immediate Indirect Indexed Mnemonic Length Opcode Length Opcode Length Opcode Length Opcode CLRC 1 F8 CLRVT 1 FC DI 1 FA El 1 FB IDLPD 1 F6 NOP 1 FD RST 1 FF EN SETC 1 F9 SKIP 2 00 PTS Direct Immediate Indirect Indexed Mnemonic Length Opcode Length Opcode Length Opcode Length Opcode DPTS 1 EC EPTS 1 ED NOTES 1 Indirect normal and indirect autoincrement share the same opcodes as do short and long indexed modes Because word registers always have even addresses the address can be expressed in the upper seven bits the least significant bit determines the addressing mode Indirect normal and short indexed modes make the second byte of the instruction even LSB 0 Indirect autoincrement and long indexed modes make the second byte odd LSB 1 2 For indexed instructions the first column lists instruction lengths as S L where S is the short i
2. Direct Immediate Indirect eee Mnemonic Length Opcode Length Opcode Length Opcode p rd Opcode DJNZ 3 EO DJNZW 3 1 JBC 3 30 37 JBS 3 38 3F JC 2 2 2 D6 JGT 2 D2 JH 2 09 2 DA JLT 2 DE JNC 2 D3 JNE 2 D7 JNH 2 D1 JNST 2 DO JNV 2 D5 JNVT 2 D4 JST 2 D8 JV 2 DD JVT 2 DC NOTES 1 Indirect normal and indirect autoincrement share the same opcodes as do short and long indexed modes Because word registers always have even addresses the address can be expressed in the upper seven bits the least significant bit determines the addressing mode Indirect normal and short indexed modes make the second byte of the instruction even LSB 0 Indirect autoincrement and long indexed modes make the second byte odd LSB 1 2 For indexed instructions the first column lists instruction lengths as S L where S is the short indexed instruction length and L is the long indexed instruction length 3 For the SCALL and SJMP instructions the three least significant bits of the opcode are concatenated with the eight bits to form an 11 bit 2 s complement offset A 58 intel Table A 8 Instruction Lengths and Hexadecimal Opcodes Continued INSTRUCTION SET REFERENCE
3. 32 byte Windows 64 byte Windows Register Memory 0060 007FH 0040 007FH Mnemonic Location F WSR1 address SP address BUSCON5 1F6CH 7BH 006CH 3DH 006CH CON REGO 1FB6H 7DH 0076H 0076 EP DIR 1FE3H 7FH 0063H 0063H EP MODE 1FE1H 7FH 0061H 0061 EP PIN 1FE7H 7FH 0067H 0067 EP REG 1FE5H 7FH 0065H 0065 EPA_MASK 1F9CH 7CH 007CH 3EH 005CH EPA_PEND 1F9EH 7CH 007EH 3EH 005EH EPAO CON 1F80H 7CH 0060H 0040 EPAO TIME 1F82H 7CH 0062H 0042 EPA1 CON 1F84H 7CH 0064H 0044 EPA1 TIME 1F86H 7CH 0066H 0046 2_ 1F88H 7CH 0068H 0048 EPA2 TIME 1F8AH 7CH 006AH 004 EPA3 CON 1F8CH 7CH 006CH 004CH EPA3 TIME 1F8EH 7CH 006 004 P1 DIR 1FD2H 7EH 0072H 0052 P1 MODE 1FDOH 7EH 0070H 3FH 0050H P1_PIN 1FD6H 7EH 0076H 3FH 0056H P1_REG 1FD4H 7EH 0074H 3FH 0054H P2_DIR 1FD3H 7EH 0073H 3FH 0053H P2_MODE 1FD1H 7EH 0071H 3FH 0051H P2_PIN 1FD7H 7EH 0077H 3FH 0057H P2_REG 1FD5H 7EH 0075H 3FH 0055H P3_DIR 1FDAH 7EH 007AH 3FH 005AH P3_MODE 1FD8H 7EH 0078H 3FH 0058H P3_PIN 1FDEH 7EH 007EH 3FH 005EH P3_REG 1FDCH 7EH 007CH 3FH 005CH P4_DIR 1FDBH 7EH 007BH 3FH 005BH P4_MODE 1FD9H 7EH 0079H 0059 PIN 1FDFH 7EH 007FH 005 P4 REG 1FDDH 7EH 007DH 005DH Must be addressed as a word C 53 8 196 80C196NU USER S MANUAL WSR1 In
4. 7 11 7 3 EROR 7 11 7 3 1 ese a Years 7 12 7 3 1 1 322 EM 7 14 7 9 1 2 Output Enable deer im e ee d dre n o td 7 14 7 3 1 3 Complementary Output Mode 7 14 vi intel CONTENTS 7 3 1 4 Open drain Output Mode 2 22 2 222 000 00000 erede ttd s 7 14 31 5 Ihp t Mode rem etre nep et ip tto ede RE Pal Lena eet pedea nata 7 16 7 3 2 Configuring EPORT Pins 7 3 2 1 Configuring EPORT Pins for Extended address Functions iso metodo 7 17 7 3 8 2 Configuring EPORT Pins for l O 7 17 7 9 3 EPORT Considerations 22 ngonissd 18 7 3 3 1 EPORT Status During Reset CCB Fetch Idle Powerdown and Hold 718 7 3 3 2 REG Settings for Pins Configured as Extended address Signals 7 18 7 3 8 8 EPORT Status During Instruction Execution sese 7 18 7 3 3 4 Design Considerations sese eene enne 7 19 CHAPTER 8 SERIAL SIO PORT 8 1 SERIAL I O SIO PORT FUNCTIONAL OVERVIEW 8 1 8 2 SERIAL I O PORT SIGNALS AND REGISTERS 8 2 8 3 SERIAE PORTIMOBENS tenti tiene tiet d edet eret ete tonta 40 4 8 3 1 Synchronous
5. 10 22 EPA Interrupt Pending EPA 10 23 Minimum Hardware 11 3 Power and Return 11 4 On chip Oscillator 11 5 External Crystal Connections eem emend 1 6 External Clock eene nnne 11 7 External Clock Drive eee em enne 11 7 Reset Timing 11 8 Internal Reset 11 9 Minimum Reset GIrcult 2 uet eerte edente ent aerea 11 10 Example System Reset 2 nenne 11 10 Clock Control During Power saving Modes 8 196 12 4 Clock Control During Power saving Modes 80 196 0 12 5 Power up and Powerdown Sequence When Using an External 12 9 External RC Circuit n Typical Voltage on the RPD Pin While Exiting Powerdown Calculation of a Chip select emm 13 6 Address Compare ADDRCOM x 13 7 Address Mask ADDRMSKxX Register sseeeeene emen 13 8 Bus Control 5 13 10 Example Syste
6. 6 23 Comparison of PWM nennen nennen i nene enean 6 26 PWM Toggle Mode enne eene entere nnne nennen ene 6 28 PWM Remap Mode PTSCB eese ennemis O70 Device I O Ports ie etn err ation bent cere tae Ee PO T Ho gene peat 7 1 Bidirectional POr PINS eiciia eter te e 7 2 Bidirectional Port Control and Status Registers 7 3 Logic Table for Bidirectional Ports in l O Mode se 7 6 Logic Table for Bidirectional Ports in Special function Mode 7 6 Control Register Values for Each 7 8 Port Configuration Example EET Port Pin States After Reset and After Example Code Execution n 7 9 intel Table 7 9 7 10 7 11 7 12 7 13 8 1 8 2 8 3 9 1 9 2 9 4 9 5 10 1 10 2 10 3 10 4 10 5 11 1 11 2 12 1 12 2 12 3 13 1 13 2 13 3 13 4 13 5 13 6 13 7 13 8 13 9 13 10 13 11 13 12 13 13 13 14 13 15 13 16 1 1 2 A 3 CONTENTS TABLES Page EPORM P dA 7 11 EPORT Control and Status 7 12 Logic Table for EPORT in enne 7 16 Logic Table for EPORT in Addres
7. Address Description FFFFFFH FF3000H External memory code or far constants FF2FFFH Program memory 80C196NP and 80C196NU External memory FF2080H 83C196NP Internal ROM EA 1 external memory EA 0 FF207FH Special purpose memory 80C196NP and 80C196NU external memory FF2000H far constants 83C196NP Internal ROM EA 1 external memory EA 0 FF1FFFH FF0100H External flash memory code or far constants FFOOFFH FF0000H Reserved FEFFFFH FCO000H External flash memory far code far constants FBFFFFH 020000H Unimplemented 01FFFFH 010000H 64 Kbyte external RAM far data OOFFFFH 008000H 32 Kbyte external RAM near data 007FFFH 003000H Unimplemented 002FFFH 80 196 and 80C196NU Unimplemented 002080H 83C196NP Program memory remapped from internal ROM CCB1 2 1 1 00207FH 80C196NP and 80C196NU Unimplemented 83C196NP Special purpose memory near constants remapped from internal ROM 001FFFH 001F00H Internal peripheral special function registers SFRs 001EFFH 001C00H Unimplemented future SFR expansion 001BFFH 000400H Unimplemented 0003FFH 000100 Upper register file general purpose register RAM 0000FFH f 3 000018 Lower register file general purpose register RAM and stack pointer 00001 7H 000000H Lower register file CPU SFRs 5 32 intel Standard and PTS Interrupts intel CHAPTER 6 STANDAR
8. NOTE The column entitled Reg lists the instruction execution times for accesses to the register file or peripheral SFRs The column entitled Mem lists the instruction execution times for accesses to all memory mapped registers I O or memory See Table 5 1 on page 5 4 for address information A 61 8XC196NP 80C196NU USER S MANUAL intel Table A 9 Instruction Execution Times in State Times Continued Stack Register Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long Reg Reg Mem Reg Mem Reg Mem POP 8 10 12 11 13 11 13 12 14 POPA 12 POPF 7 PUSH 6 7 9 12 10 13 10 13 11 14 PUSHA 12 PUSHF 6 Stack Memory Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long Reg Reg Reg Mem Reg Mem POP 11 13 15 14 16 14 16 15 17 POPA 18 POPF 10 PUSH 8 9 11 14 12 15 12 15 13 16 PUSHA 18 PUSHF 8 NOTE The column entitled Reg lists the instruction execution times for accesses to the register file or peripheral SFRs The column entitled Mem lists the instruction execution times for accesses to all memory mapped registers I O or memory See Table 5 1 on page 5 4 for address information A 62 intel INSTRUCTION SET REFERENCE T
9. Chip Address Size of B SUE Contents of Contents of Select Range Address Range ADDRMSKx ADDRCOMx ADDRMSKx 0 80000 FFFFFH 512 Kbytes 219 bytes n 20 19 1 0800H 0800H 1 01E00 01EFFH 256 bytes 28 bytes 20 8 12 001 OFFFH 2 7E000 7FFFFH 8 Kbytes 213 bytes 20 13 7 07 OFEOH 13 4 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES Two chip configuration registers CCRs have bits that set parameters for chip operation and ex ternal bus cycles The CCRs cannot be accessed by code They are loaded from the chip config uration bytes CCBs which have internal addresses FF2018H CCBO and FF201AH CCB1 If the CCBs are stored in external memory their external addresses depend on the number of EPORT lines used in the external system see Internal and External Addresses on page 13 1 When the device returns from reset the bus controller fetches the CCBs and loads them into the CCRs From this point these CCR bit values define the chip configuration until the device is reset again The CCR bits are described in Figures 13 6 and 13 7 The remainder of this section de scribes the state of the chip following reset and the process of fetching the CCBs 13 14 intel INTERFACING WITH EXTERNAL MEMORY CCRO no direct access The chip configuration 0 CCRO register enables or disables powerdown and standby 80C196NU only modes and selects the write control mode It a
10. Title Order Number AP 445 8XC196KR Peripherals A User s Point of View 270873 AP 449 A Comparison of the Event Processor Array EPA and High Speed 270968 Input Output HSIO Unit AP 475 Using the 8 196 272315 AP 477 Low Voltage Embedded Design 272324 AP 483 Application Examples Using the 8XC 196MC MD Microcontroller 272282 AP 700 Intel Fuzzy Logic Tool Simplifies ABS Design t 272595 AP 711 EMI Design Techniques for Microcontrollers in Automotive Applications 272324 AP 715 Interfacing 2 Serial EEPROM to an MCS 96 Microcontroller 272680 Included in Automotive Products handbook order number 231792 Included in Embedded Applications handbook order number 270648 tit Included in Automotive Products and Embedded Applications handbooks Table 1 3 MCS 96 Microcontroller Datasheets Commercial Express Title Order Number 8XC196KR KQ JR JQ Commercial Express CHMOS Microcontroller 270912 8XC196KT Commercial CHMOS Microcontroller 272266 87C196KT 87C196KS 20 MHz Advanced 16 Bit CHMOS Microcontroller 272513 8XC196MC Industrial Motor Control Microcontroller 272323 87C196MD Industrial Motor Control CHMOS Microcontroller 270946 8XC196NP Commercial CHMOS 16 Bit Microcontroller 272459 8XC196NT CHMOS Microcontroller with 1 Mbyte Linear Address Space 272267 80C196NU Commercial CHMOS 16 Bit Microcontroller 272644 Included in Embedded Microcontr
11. geb ei RI nunI ee TT 4 2 4 1 3 SHORT INTEGER OperandsS eee ete tt PR uni 4 2 41 4 WORD eee ere tee eere Re Ro dE ru de 4 3 4 1 5 INTEGER Operands essen eene 4 3 4 1 6 DOUBLE WORD 4 3 4 1 7 LONG INTEGER Operands 4 4 4 1 8 QUAD WORD Operands sese emere ennemi nens 4 4 4 1 9 Converting Operands 4 4 4 1 10 Conditional Jumps 4 4 4 1 11 Floating Point Operations 4 5 4 1 12 Extended Instructions 4 5 4 2 ADDRESSING MODES Her Eee RU eain deste 4 6 4 2 1 Direct Addressing eee a aot 4 7 4 2 2 Immediate Addressing dde 4 2 3 Indirect Addressing 2 4 4 4 4 7 4 2 3 1 Extended Indirect Addressing emm 4 8 4 2 3 2 Indirect Addressing with Autoincrement 2 4 8 4 2 8 8 Extended Indirect Addressing with Autoincrement 4 8 4 2 8 4 Indirect Addressing with the Stack 4 9 4 2 4 Indexed Addressing crt E gud eei eate 4 9 4 2 41 Shortindexed Addressing 2 4 9 4 2 4 2 Long indexed Addressing 2 9 4 2 4 8 Extended
12. register 10H OFFH with a value in the range of 0 to 31 1FH inclusive The left bits of the result are filled with zeros The last bit shifted out is saved in the carry flag Temp lt COUNT do while Temp 0 C lt Low order bit of DEST DEST DEST 2 Temp lt 1 end while PSW Flag Settings Z N C V VT ST 0 0 Operation Instruction Format SHRAL ARITHMETIC RIGHT SHIFT DOUBLE WORD Shifts the destination double word SHRAL operand to the right as many times as specified by the count operand The count 00001110 count Ireg may be specified either as an immediate or value in the range of 0 to 15 OFH inclusive SHRAL Ireg breg or as the content of any register 10H with a value in the range of 0 to 31 00001110 breg Ireg 1FH inclusive If the original high order bit value was 0 zeros are shifted in If the NOTES This instruction clears the value was 1 ones are shifted in sticky bit flag at the beginning Temp lt COUNT of the instruction If at any time do while Temp 0 during the shift a 1 is shifted C lt Low order bit of DEST into the carry flag and another DEST lt DEST 2 shift cycle occurs the instruc Temp Temp 1 tion sets the sticky bit flag end while In this operation DEST 2 rep PSW Flag Settings resents signed divi
13. 2 5 2 3 5 Multiply accumulate 80C196NU Only seem 2 3 6 Interrupt Service 2 6 2 4 INTEBRNALETIMIING 2 7 2 5 INTERNAL 6 2 11 2 54 l OYPOrIS iet ete Peck elas id em 2 11 2 5 2 Serial O SIO Port ene eem ce esee ni cei ER Coach 2 11 2 5 3 Event Processor Array EPA and Timer Counters eene 2 11 2 5 4 Pulse width Modulator PWM 2 2 em emn 2 12 2 6 SPECIAL OPERATING 2 12 2 6 1 Reducing Power Consumption 2 2 12 2 6 2 Testing the Printed Circuit Board sese 2 13 2 7 DESIGN CONSIDERATIONS FOR 80C196NP TO 80C196NU CONVERSIONS 2 13 8XC196NP 80C196NU USER S MANUAL intel CHAPTER 3 ADVANCED MATH FEATURES 3 1 ENHANCED MULTIPLICATION 3 1 3 2 OPERATING 3 2 3 2 1 Sat ration MOMS ra wee ie EE RUBER Ee ene em ned 3 2 3 2 2 Fractional Mode need etse be ote eR da Era 3 3 3 3 ACCUMULATOR REGISTER 0x ssssseee eem 3 4 3 4 ACCUMULATOR CONTROL AND STATUS REGISTER STAT 3 5 CHAPTER 4 PROGRAMMING CONSIDERATIONS 4 1 OVERVIEW OF THE INSTRUCTION 6 eem eene 4 1 4 1 1 BIT Operands PMID 4 2 4 1 2
14. Boc Description Demultiplexed Bus ns Multiplexed Bus ns Max time from RD asserted to valid input data on the bus ae ie Max time from A19 0 and CSx Tavov valid to valid input data on the bus 4 90 Ser Max time from RD deasserted t t RHDZ until data bus is at high impedance Minimum time that WR is asserted 2010 Uem Minimum time from valid data on the bus to WR deasserted E Anm Consult the device datasheet for the latest specifications 13 6 WAIT STATES READY CONTROL An external device can use the READY input to request wait states in addition to the wait states that are generated internally by the 8 196 device When an address is placed on the bus for an external bus cycle the external device can pull the READY signal low to indicate it is not ready In response the bus controller inserts wait states to lengthen the bus cycle until the external device raises the READY signal Each wait state adds one CLKOUT period 1 one state time or 2t to the bus cycle The READY signal is effective for all bus cycles including the CCBO fetch which has three in ternal wait states Bits WSO and WS1 in CCBO specify the wait states for the CCB1 fetch There after the WSO and WS1 bits in the BUSCON x registers control the wait states and the READY signal can be used to insert additional wait states See Controlling Wait States Bus Width and
15. 13 38 Demultiplexed System Bus Timing 8 196 13 39 Demultiplexed System Bus Timing 80 196 0 13 40 Deferred Bus cycle Mode Timing Diagram 80619630 13 41 8XC196NP 100 lead SQFP Package seem 2 8XC196NP 100 lead QFP B 3 80C196NU 100 lead SQFP Package seen eene 80C196NU 100 lead QFP xiii 8XC196NP 80C196NU USER S MANUAL intel xiv TABLES Page Handbooks and Product 1 6 Application Notes Application Briefs and Article Reprints 1 6 MCS 96 Microcontroller Datasheets 1 7 MCS 96 Microcontroller Datasheets Automotive MCS 96 Microcontroller Quick References Features of the 8XC196NP and 80C196NU State Times at Various Relationships Between Input Frequency Clock Multiplier and State Times 2 10 Multiply Accumulate Example Code sse em ener 3 2 Effect of SME and FME Bit 3 6 Operand Type 4 1 Equivalent Operand Types for Assembly and C Programming Languages
16. 4 2 Definition of Temporary 4 7 8XC196NP and 80C196NU Memory 5 4 Program Memory Access for the 83C196NP sss eee 5 5 8XC196NP and 80C196NU Special purpose Memory Addresses 5 6 Special purpose Memory Access for the 83 196 5 6 oe ee REPE nen nep 5 8 Register File Memory 0 5 11 E aria DTE Te EE 5 12 Selecting a Window of Peripheral 5 5 5 15 Selecting a Window of the E 5 15 Windows m Windowed Base Addresses Is bak eed OE IRE D e Ye wi tbe NYSE eae 5 18 Memory Map for the System in Figure 5 9 5 28 Memory Map for the System in Figure 5 10 sss 5 30 Memory Map for the System in Figure 5 11 5 32 Interrupt Sighals os eee tte te ond ita 6 3 Interrupt and PTS Control and Status 6 3 Interrupt Sources Vectors and renerne 6 5 Execution Times for PTS Cycles emm 6 10 Single Transfer Mode 6 23 Block Transfer Mode PTSCB
17. 7 2 4 Bidirectional Port Operation Figure 7 1 shows the logic for driving the output transistors Q1 and Q2 On ports 1 2 and 3 Q1 can source at least 3 mA at Voc 0 7 volts On port 4 which has a high current sink capability for the PWMs Q1 can source at least 3 mA at 0 45 volts Q2 can sink at least 10 mA at 0 45 volts Consult the datasheet for specifications In I O mode selected by clearing MODE y REG and Px DIR are input to the multiplex ers These signals combine to drive the gates of Q1 and Q2 so that the output is high low or high impedance Table 7 4 is a logic table for I O operation of these ports 8XC196NP 80C196NU USER S MANUAL intel In special function mode selected by setting Px MODE y SFDIR and SFDATA are input to the multiplexers These signals combine to drive the gates of Q1 and Q2 so that the output is high low or high impedance Special function output signals clear SFDIR special function input sig nals set SFDIR Table 7 5 is a logic table for special function operation of these ports Even if a pin is to be used in special function mode you must still initialize the pin as an input or output by writing to Px DIR Resistor R1 provides ESD protection for the pin Input signals are buffered The ports use Schmitt triggered buffers for improved noise immunity The signals are latched into the Px PIN sample latch and output onto the internal bus when the Px PIN register is rea
18. Name Type Description ALE Address Latch Enable This active high output signal is asserted only during external memory cycles ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address data bus A19 16 and AD15 0 for a multiplexed bus A19 0 for a demultiplexed bus ALE differs from ADV in that it does not remain active during the entire bus cycle An external latch can use this signal to demultiplex address bits 0 15 from the address data bus in multiplexed mode BHE Byte High Enable During 16 bit bus cycles this active low output signal is asserted for word reads and writes and high byte reads and writes to external memory indicates that valid data is being transferred over the upper half of the system data bus Use BHE in conjunction with AO to determine which memory byte is being transferred over the system bus BHE 0 Byte s Accessed 0 0 both bytes 0 1 high byte only 1 0 low byte only is multiplexed with WRH t The chip configuration register 0 CCRO determines whether this pin functions as or WRH CCRO 2 1 selects BHE CCRO 2 0 selects WRH BREQ Bus Request This active low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle The device can assert BREQ at the same time as or after it asserts HLDA Once it is asserted BREQ remains asserted until HO
19. DEST SRC1 SRC2 ADDB Sbreg baop 010101aa baop Sbreg Dbreg ADDC ADD WORDS WITH CARRY Adds the Source and destination word operands and the carry flag 0 or 1 and stores the sum into the destination operand DEST lt DEST SRC PSW Flag Settings 7 V VT ST DEST SRC ADDC wreg waop 101001aa waop wreg 8XC196NP 80C196NU USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format ADDCB ADD BYTES WITH CARRY Adds the source DEST SRC and destination byte operands and the breg baop flag 0 or 1 and stores the sum into the destination operand 10110122 baop breg DEST lt DEST SRC PSW Flag Settings Z N C V VT ST AND LOGICAL AND WORDS ANDs the source DEST SRC 2 operands and destination word operands and stores AND wreg waop the result into the destination operand The result has ones in only the bit positions in 011000aa waop wreg which both operands had a 1 and zeros in all other bit positions DEST lt DEST AND SRC PSW Flag Settings Z N C V VT ST 0 0 1 LOGICAL AND WORDS ANDs the two DEST SRC1 SRC2 8 operands source word operands and stores the result AND into the destination operand
20. JV 11011101 disp NOTE The displacement disp is sign extended to 24 bits A 26 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format JVT JUMP IF OVERFLOW TRAP FLAG IS SET Tests the overflow trap flag If the flag is clear cadd control passes to the next sequential instruction If the overflow trap flag is set this 11011100 disp instruction clears the flag and adds to the program counter the offset between the end NoTE The displacement disp is sign of this instruction and the target label extended to 24 bits effecting the jump The offset must be in range of 128 to 127 if VT 2 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST 0 LCALL LONG CALL Pushes the contents of the program counter the return address onto LCALL cadd the stack then adds to the program counter the offset between the end of this instruction 11101111 disp low disp high and the target label effecting the call The offset must be in the range of 32 768 to NOTE The displacement disp is sign 32 767 extended to 24 bits the 1 Mbyte 64 Kbyte mode addressing mode This displace SP lt SP 2 ment may cause the program SP lt counter to cross page boundary PC lt 16 bit disp 1 Mbyte mode
21. lists the instruction execution times for accesses to all memory mapped registers I O or memory See Table 5 1 on page 5 4 for address information A 60 intel INSTRUCTION SET REFERENCE Table A 9 Instruction Execution Times in State Times Continued Arithmetic Group II Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long Reg Mem Reg Mem Reg Mem Reg Mem DIV 26 27 28 31 29 32 29 32 30 33 DIVB 18 18 20 23 21 24 21 24 22 25 DIVU 24 25 26 29 27 30 27 30 28 31 DIVUB 16 16 18 21 19 22 19 22 20 23 MUL 2 ops 16 17 18 21 19 22 19 22 20 23 MUL 3 ops 16 17 18 21 19 22 19 22 20 23 MULB 2 ops 12 12 14 17 15 18 15 18 16 19 MULB 3 ops 12 12 14 17 15 18 15 18 16 19 MULU 2 ops 14 15 16 19 17 19 17 20 18 21 MULU 3 ops 14 15 16 19 17 19 17 20 18 21 MULUB 2 ops 10 10 12 15 13 15 12 16 14 17 MULUB 3 ops 10 10 12 15 13 15 12 16 14 17 Logical Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long Reg Mem Reg Mem Reg Mem Reg Mem AND 2 ops 4 5 6 8 7 9 6 8 7 9 AND 3 ops 5 6 7 10 8 11 7 10 8 11 ANDB 2 ops 4 4 6 8 7 9 6 8 7 9 ANDB 3 ops 5 5 7 10 8 11 7 10 8 11 NEG 3 NEGB 3 NOT 3 NOTB 3 OR 4 5 6 8 7 9 6 8 7 9 ORB 4 4 6 8 7 9 6 8 7 9 XOR 4 5 6 8 7 9 6 8 7 9 XORB 4 4 6 8 7 9 6 8 7 9
22. 13 36 13 9 1 Deferred Bus cycle Mode 80C196NU Only 13 40 13 9 2 Explanation of AC Symbols sse eee 13 42 13 9 3 AC Timing Definitions iis ere re rt reete err eds 13 42 8 196 80C196NU USER S MANUAL APPENDIX A INSTRUCTION SET REFERENCE APPENDIX B SIGNAL DESCRIPTIONS B 1 FUNCTIONAL GROUPINGS OF SIGNALS eee B 2 SIGNAL DESCRIPTIONS esee B 3 DEFAULT CONDITIONS tn a rete ten teet APPENDIX C REGISTERS GLOSSARY INDEX intel CONTENTS Figure 2 1 2 2 2 4 2 5 3 1 3 2 5 2 5 3 5 5 5 6 5 8 5 9 5 10 5 11 6 1 6 2 6 3 6 5 6 6 6 8 6 9 6 10 6 11 6 12 6 13 6 14 6 15 6 16 6 17 6 18 7 1 7 2 7 3 8 1 8 2 8 4 FIGURES Page 8XC196NP and 80C196NU Block Diagram eee 2 2 Block Diagram of the 2 3 Clock Circuitry 8BXC196NP n siirsi 2 7 Clock Circuitry 806196 0 2 8 Internal Clock Phases essen ener nnne 2 9 Effect of Clock Mode on CLKOUT eme 2 10 Accumulator 0x Register 3 4 Accumulator Control and Status STAT 3 5 16 Mbyte Address Space alae eene sine rei ient tere
23. 2 FF2038H 12 PTS12 FF2058H 27 a 2 igi n 1 INT11 FF2036H 11 PTS11 FF2056H 26 EPA Capture Compare 3 EPAS3 INT10 FF2034H 10 PTS10 FF2054H 25 EPA Capture Compare 2 EPA2 09 FF2032H 09 509 2052 24 Capture Compare 1 1 08 FF2030H 08 508 2050 23 Unimplemented FF2012H Software TRAP Instruction OFF2010H EPA Capture Compare 0 EPAO INTO7 FF200EH 07 507 FF204EH 22 SIO Receive RI 06 FF200CH 06 506 FF204CH 21 SIO Transmit TI 05 FF200AH 05 505 FF204AH 20 04 FF2008H 04 504 FF2048H 19 EXTINTO Pin EXTINTO INTO3 FF2006H 03 503 FF2046H 18 Reserved Reserved INTO2 FF2004H 02 502 2044 17 Timer 2 Overflow OVRTM2 INTO1 FF2002H 01 501 FF2042H 16 Timer 1 Overflow OVRTM 1 INTOO FF2000H 00 PTSOO FF2040H 15 PTS service is not recommended because the PTS cannot determine the source of shared interrupts 6 3 1 1 Unimplemented Opcode If the CPU attempts to execute an unimplemented opcode an indirect vector through location FF2012H occurs This prevents random software execution during hardware and software fail ures The interrupt vector should contain the starting address of an error routine that will not fur ther corrupt an already erroneous situation The uni
24. Load TICONTROL with C2H enables timer 1 selects up counting at f 4 and enables the divide by four prescaler Enable the EPAO interrupt and select PTS service for it Set INT MASK 7 Set PTSSEL 7 Enable the interrupts and the PTS The EI instruction enables interrupts the EPTS instruction enables the PTS intel STANDARD AND PTS INTERRUPTS PTS PWM Toggle Mode Control Block In PWM toggle mode the PTS uses a single EPA channel to generate a pulse width modulated PWM output signal The control block contains registers that contain the PWM on time PTSCONST1 the PWM off time PTSCONST2 the address pointer PTSPTR1 and a control register PTSCON 7 0 PTSCONST2 PWM Off time high byte 7 0 PTSCONST2 L PWM Off time low byte 15 8 PTSCONST1 H PWM On time high byte 7 0 PTSCONST1 L PWM On time low byte 15 8 PTSPTR1 Pointer 1 Value high byte 7 0 PTSPTR1 L Pointer 1 Value low byte 7 0 PTSCON M2 M1 MO TMOD TBIT 7 0 Unused 0 0 0 0 0 0 0 0 Register Location Function PTSCONST2 PTSCB 6 PWM Off time Write the desired PWM off time to these bits PTSCONST1 PTSCB 4 PWM On time Write the desired PWM on time to these bits PTSPTR1 PTSCB 2 Pointer 1 Value These bits point to a memory location usually EPAx TIME PTSPTR1 can point to any unreserved memory loca
25. EP PIN 1FE7H EPORT Pin State Each bit of EP PIN reflects the current state of the corresponding pin regardless of the pin configuration EP REG 1FE5H EPORT Data Output Each bit of EP_REG contains data to be driven out by the corre sponding pin When pin is configured as standard I O EP MODE x 0 the result of a CPU write to EP REG is immediately visible on the pin During nonextended data accesses REG contains the value of the memory page that is to be accessed For compatibility with software tools clear the REG bit for any EPORT pin that is configured as an extended address signal MODE x set 80C196NU Only For nonextended data accesses the 80C196NU forces the page address to 00H You cannot change pages by modifying REG 7 31 Operation As Figure 7 2 shows each EPORT pin serves either as I O or as an address line as selected by the I O multiplexer This multiplexer is controlled by the EP MODE register If EP is clear I O mode the pin serves as I O until EP MODE is changed intel PORTS Internal Bus MUX Vo Vcc Address MUX 0 Extended Code Address from CPU ek from Force Page 00H 1 9 Q1 Extended Data Address EDAR DATA VO Pin from CPU Combinational r Logic Data Address Control from Bus Controller MODE64 Control Q2 from CPU EP_MODE gt EP DIR V Sample 5
26. i etn repetir eret Prae dero 12 13 Example of Internal and External 13 1 External Memory Interface eene eme 13 2 Chip select Registers rS ADDRCOMx Addresses and Reset Values eee inte Ead sag Ges candi ee EET Opes 13 7 ADDRMSKx Addresses and Reset Values esee 13 8 Base Addresses for Several Sizes of the Address Range 13 9 BUSCONx Addresses and Reset Values sss 13 11 BUSCONx Registers for the Example 13 13 Results for the Chip select Example seem 13 14 Comparison of AC Timings for Demultiplexed and Multiplexed 16 bit Buses 13 26 READY Signal Timing Definitions 13 27 HOLD HLDA Timing Definitions 13 31 Maximum Hold Latency i e eer EA 13 33 Write Signals for Standard and Write Strobe 13 34 AC Timing Symbol 19 42 AG Timing Definitions ro e Eee di s ei ERRARE 13 42 Opcode Map Left Half A 2 Opcode Map Right eren A 3 Processor Status Word PSW Flags esee eene 4
27. 10 8 PROGRAMMING EXAMPLES FOR EPA CHANNELS The three programming examples provided in this section demonstrate the use ofthe EPA channel for a compare event for a capture event and for generation of a PWM signal The programs dem onstrate the detection of events by a polling scheme by interrupts and by the PTS AII three ex amples were created using ApBUILDER an interactive application program available through Intel Literature Fulfillment or the Intel Applications Bulletin Board system BBS See Chapter 1 Guide to This Manual for information about ordering information from Intel Literature and downloading files from the BBS These sample program were written in the C programming lan guage ASM versions are also available from ApBUILDER NOTE The initialization file 80c196np h used in these examples is available from the Intel Applications BBS 10 8 1 EPA Compare Event Program This example C program demonstrates an EPA compare event It sets up EPA channel 0 to toggle its output pin whenever timer 1 is zero This program uses no interrupts a polling scheme detects the EPA event The program initializes EPA channel 0 for a compare event pragma model EX include 80c196np h define COMPARE 0x40 define RE_ENABLE 0x08 define TOGGLE_PIN 0x30 define USE TIMERI 0x00 define EPAO_INT_BIT 7 void init_epa0 0 con COMPARE TOGGLE PIN RE ENABLE USE TIMER1 0 time 0 setbit pl reg 0
28. Voc A2385 02 Figure 12 5 Typical Voltage on the RPD Pin While Exiting Powerdown When selecting the capacitor determine the worst case discharge time needed for the oscillator to stabilize then use this formula to calculate an appropriate value for C Tpis X C EON t where C is the capacitor value in farads Tpis is the worst case discharge time in seconds is the discharge current in amperes VE is the threshold voltage NOTE If powerdown is re entered and exited before C charges to Vec it will take less time for the voltage to ramp down to the threshold Therefore the device will take less time to exit powerdown 12 11 8XC196NP 80C196NU USER S MANUAL intel For example assume that the oscillator needs at least 12 5 ms to discharge 12 5 ms V is 2 5 V and the discharge current is 200 UA The minimum capacitor size is 1 ns 0 0125 0 0002 zd 2 5 When using an external oscillator the value of C can be very small allowing rapid recovery from powerdown For example 100 pF capacitor discharges in 1 25 us 12 6 ONCE MODE On circuit emulation ONCE mode isolates the device from other components in the system to allow printed circuit board testing or debugging with a clip on emulator During ONCE mode all pins except XTALI XTAL2 Va and Voc are weakly pulled high or low During ONCE mode must be held high or the device will exit ONCE mode and enter
29. if C 2 0 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JNE JUMP IF NOT EQUAL Tests the zero flag If the flag is set control passes to the next JNE cadd sequential instruction If the zero flag is clear this instruction adds to the program counter 11010111 disp the offset between the end of this instruction and the target label effecting the jump The NOTE The displacement disp is sign offset must be in the range of 128 to 127 extended to 24 bits if Z 0 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST A 24 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format JNH JUMP IF NOT HIGHER UNSIGNED Tests both the zero flag and the carry flag If the JNH cadd carry flag is set and the zero flag is clear control passes to the next sequential 11010001 disp instruction If either the carry flag is clear or the zero flag is set this instruction adds tothe NoTE The displacement disp is sign program counter the offset between the end extended to 24 bits of this instruction and the target label effecting the jump The offset must be in range of 128 to 127 if C 2 0 ORZ 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JNST JUMP IF STICK
30. int reg clrbit pl dir 0 make output pin setbit pl mode 0 select EPA mode void init timerl tlcontrol COUNT ENABLE COUNT UP CLOCK INTERNAL DIVIDE BY 1 10 24 intel EVENT PROCESSOR ARRAY EPA void poll 0 if checkbit int pend EPAO INT BIT Insert user code for event channel 0 here Since this event is absolute and re enabled no polling is neccessary clrbit int pend EPAO INT void main void Initialize the timers before using the epa init timerl init 0 EPA events can be serviced by polling int pend or epa pend while 1 poll 0 10 8 2 EPA Capture Event Program This example C program demonstrates an EPA capture event It sets up EPA channel 0 to capture edges rising and falling on the EPAO pin The program also shows how to set up an the EPA interrupt You can add your own code for the interrupt service routine pragma model EX include 80c196np h define COUNT_ENABLE 0x80 define COUNT UP 0x40 define CLOCK_INTERNAL 0x00 define DIVIDE_BY_1 0x00 define CAPTURE 0x00 define BOTH_EDGE 0x30 define USE_TIMER1 0x00 define EPAO_INT_BIT 7 void init 0 0 con CAPTURE BOTH EDGE USE setbit pl reg 0 int reg setbit pl dir 0 make input pin setbit pl mode 0 select EPA mode setbit int mask INT BIT unmask EPA int
31. CLKOUT Clock Output Output of the internal clock generator The CLKOUT frequency is gt the internal operating frequency f CLKOUT has a 50 duty cycle P2 7 CS5 0 Chip select Lines 0 5 The active low output CS x is asserted during an external memory cycle when the address to be accessed is in the range programmed for chip select x If the external memory address is outside the range assigned to the six chip selects no chip select output is asserted and the bus configuration defaults to the CS5 values Immediately following reset CSO is automatically assigned to the range FF2000 FF20FFH F2000 F20FFH if external P3 5 0 13 3 8 196 80C196NU USER S MANUAL Table 13 2 External Memory Interface Signals Continued intel Name Type Description Multiplexed With External Access This input determines whether memory accesses to special purpose and program memory partitions FF2000 FF2FFFH are directed to internal or external memory These accesses are directed to internal memory if is held high and to external memory if is held low For an access to any other memory location the value of EA is irrelevant is not latched and can be switched dynamically during normal operating mode Be sure to thoroughly consider the issues such as different access times for internal and external memory before using this dynamic switching capability
32. CON REGO 0 2 Address 1FB6H Reset State FEH The control CON 0 register controls the clock prescaler for the three pulse width modulators d 0 8XC196NP 0 80C196NU CLK1 CLKO 0 Function i NU Reserved for compatibility with future devices write zeros to these bits 0 NP CLKO Enable PWM Clock Prescaler This bit controls the PWM output period by enabling or disabling the clock prescaler divide by two on the three pulse width modulators PWM2 0 0 disable PWM output period is 512 state times 1 enable PWM output period is 1024 state times 1 0 NU CLK1 0 Enable PWM Clock Prescaler These bits control the PWM output period on the three pulse width modulators PWM2 0 CLK1 CLKO 0 0 disable clock prescaler 0 1 enable divide by two prescaler PWM output period is 1024 state times 1 X enable divide by four prescaler PWM output period is 2048 state times This bit was called SLOW in earlier documentation for the 8XC196NP Figure 9 4 Control CON REGO Register 9 5 PROGRAMMING THE DUTY CYCLE The value written to PVMx CONTROL register controls the width of the high pulse effec tively controlling the duty cycle The 8 bit value written to the control register is loaded into a buffer and this value is used during the next period Use the
33. DEST SRC1 SRC2 MUL lreg wreg waop 11111110 010011aa waop wreg Ireg NOTE 8XC196NU only A destination address in the range 00H 0FH enables the multiply accumulate function When set bit 3 of the destination address causes the accumulator to be cleared before the results of the multiply are added to the contents of the accu mulator For example if the desti nation address is 08H the accumulator is cleared and then the results of the multiply are added However if the destination address is 00H the results of the multiply are added to the current contents of the accumulator MULB 2 operands MULTIPLY SHORT INTEGERS Multiplies the source and destination short integer operands using signed arithmetic and stores the 16 bit result into the destination integer operand The sticky bit flag is undefined after the instruction is executed DEST lt DEST x SRC PSW Flag Settings 7 VT ST DEST SRC wreg baop 11111110 011111 wreg 29 8XC196NP 80C196NU USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format MULB MULTIPLY SHORT INTEGERS Multiplies DEST SRC1 SRC2 8 operands the two source short integer operands MULB wreg breg baop using signed arithmetic and stores the 16 bit result into the destination integer operand The sticky bit fla
34. di im in ix 5x ANDB ADDB di im in ix di im in ix 6x AND 2 ADD 2 di im in ix di im in ix 7x ANDB 2op ADDB 2 di im in ix di im in ix OR XOR 8x E di im in ix di im in ix ORB XORB 9x di im in ix di im in ix Ax LE bids di im in ix di im in ix LDB ADDCB Bx di im in ix di im in ix ST BMOV ST STB CMPL STB ex di in ix di in ix Dx JNST JNH JGT JNC JNVT JNV JGE JNE Ex DJNZ DJNZW LJMP in Fx RET ECALL PUSHF POPF PUSHA POPA IDLPD TRAP NOTE The first digit of the opcode is listed vertically and the second digit is listed horizontally The related instruction mnemonic is shown at the intersection of the two digits Shading indicates reserved opcodes If the CPU attempts to execute an unimplemented opcode an interrupt occurs For more information see Unimplemented Opcode on page 6 5 intel INSTRUCTION SET REFERENCE Table A 1 Opcode Map Right Half Opcode x8 x9 xB xC xD xE xF ox SHR SHL SHRA XCH SHRL SHLL SHRAL NORML ix ix SHRB SHLB SHRAB XCHB EST EST ESTB ESTB ix in ix in ix 2x SCALL ax JBS bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 4x SUB MULU Note 2 di im in ix di im in ix 5x SUBB MULUB Note 2 di im
35. lel Table C 19 WSR1 Settings and Direct Addresses for Windowable SFRs Continued C 54 32 byte Windows 64 byte Windows Register Memory 0060 007 FH 0040 007FH Mnemonic Location 2 WSR1 address WSR address PWMO_CONTROL 1FBOH 7DH 0070H 3EH 0070H PWM1_CONTROL 1FB2H 7DH 0072H 3EH 0072H PWM2_CONTROL 1FB4H 7DH 0074H 3EH 0074H SBUF_RX 1FB8H 7DH 0078H 3EH 0078H SBUF_TX 1FBAH 7DH 007AH 3EH 007AH SP_BAUD 1FBCH 7DH 007CH 3EH 007CH SP_CON 1FBBH 7DH 007BH 3EH 007BH SP_STATUS 1FB9H 7DH 0079H 0079 T1CONTROL 1F90H 7CH 0070H 0050 T2CONTROL 1F94H 7CH 0074H 0054 TIMER1 1F92H 7CH 0072H 0052 TIMER2 1F96H 7CH 0076H 0056 Must be addressed as a word intel REGISTERS ZERO REG ZERO REG The two byte zero register ZERO REG is always equal to zero It is useful as a fixed source of the constant zero for comparisons and calculations Address Reset State 00H 0000H 15 B Zero high byte 7 0 Zero low byte ence Function 15 0 Zero This register is always equal to zero C 55 intel Glossary intel GLOSSARY This glossary defines acronyms abbreviations and terms that have special meaning in this man ual Chapter 1 discusses notational conventions and general terminology 1 Mbyte mode 64 Kbyte mode accumulator ALU assert
36. on circuit emulation ONCE mode electrically isolates the 8 196 device from the system By invoking ONCE mode you can test the printed circuit board while the device is soldered onto the board 2 7 DESIGN CONSIDERATIONS FOR 80C196NP TO 80C196NU CONVERSIONS This section summarizes differences to consider when converting your design requirements from the 80C196NP to the 80C196NU The 80C196NU can achieve an operating frequency of 50 MHz while the 80C196NP can achieve only 25 MHz The 80C196NU is pin compatible with the 80C196NP The functions of four pins differ the 80C196NU has PLLENI in place of a no connection pin of the 80C196NP the 80C196NU has PLLEN2 in place of a Vg pin of the 80C196NP the 80C196NU has a Vec pin in place of a no connection pin of the 80C196NP the 80C196NU has a no connection pin in place of the EA pin of the 80C196NP The 80C196NU requires that you tie the PLLENI and PLLEN2 pins either high or low depending on the clock multiplier mode you select The 80C196NU requires that you connect an external capacitor to the RPD pin if your design uses both powerdown mode and a clock multiplier mode The 80C196NU has a new 32 bit accumulator register and an accumulator status register to support its multiply accumulate functions The 80C196NU since it has no nonvolatile memory has no REMAP bit in the CCB The 80C196NU can window additional memory into the lower register file via a second window
37. 0 0 SHR wreg count 00001000 count wreg or SHR wreg breg 00001000 breg wreg NOTES This instruction clears the sticky bit flag at the beginning of the instruction If at any time during the shift a 1 is shifted into the carry flag and another shift cycle occurs the instruc tion sets the sticky bit flag In this operation DEST 2 rep resents unsigned division A 38 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format SHRA ARITHMETIC RIGHT SHIFT WORD Shifts the destination word operand to the right as SHRA wreg count many times as specified by the count operand The count be specified either 00001010 count wreg as an immediate value in the range of O to 15 or OFH inclusive or as the content of any SHRA wreg breg register 10H OFFH with a value in the range of 0 to 31 1FH inclusive If the 00001010 breg wreg original high order bit value was 0 zeros are shifted in If the value was 1 ones are NOTES This instruction clears the shifted in The last bit shifted out is saved in sticky bit flag at the beginning the carry flag of the instruction If at any time Temp lt COUNT during the shift a 1 is shifted do while Temp 0 into the carry flag and another C lt Low order bit of DEST shift cycle occurs the
38. 11100011 treg NOTE For 20 bit addresses the offset must be in the range of 524287 to 524288 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format ECALL EXTENDED CALL Pushes the contents of the program counter the return address onto the stack then adds to the program counter the offset between the end of this instruction and the target label effecting the call The operand may be any address in the address space This instruction is an unconditional relative call to anywhere in the 16 Mbyte address space It functions only in extended addressing mode SP lt SP 4 SP lt PC PC lt PC 24 bit disp PSW Flag Settings Z N C V VT ST ECALL 1111 0001 disp low disp high disp ext NOTE For 20 bit addresses the offset must be in the range of 524287 to 524288 EI ENABLE INTERRUPTS Enables interrupts following the execution of the next statement Interrupt calls cannot occur immediately following this instruction Interrupt Enable PSW 1 lt 1 PSW Flag Settings Z N C V VT ST EI 11111011 EJMP EXTENDED JUMP Adds to the program counter the offset between the end of this instruction and the target label effecting the jump The operand may be any address in the entire address space
39. 16 RAM stores far data in page 01H Using the WRL and WRH signals makes this RAM both byte and word accessible The 128 16 flash memory stores code and far constants in pages FCH FDH and FFH With the write signals connected as shown the flash memory is word accessible only Table 5 14 lists the memory addresses For memory map details see Table 5 3 on page 5 6 83C196NP only The code and data FF2000 FF2FFFH are implemented by internal ROM Remapping this area into page OOH by setting the REMAP bit CCB1 2 makes the far constants in FF2000 FF2FFFH of ROM accessible as near constants An access to this address range is di rected to external memory if EA is low and to internal ROM if EA is high Pages FC FFH Page 00H Page 01H 17 0 16 0 14 0 14 0 Flash RAM RAM 128Kx16 32Kx8 32Kx16 8XC196NP Code amp Data Data Data NU FC0000 008000 010000 FFFFFFH 00FFFFH 01FFFFH AD15 0 D15 0 D15 0 M A2476 03 Figure 5 11 Example System Using the 1 Mbyte Mode Notice that the microcontroller s A1 line connects to a word wide memory device s line For byte wide memory the microcontroller s line selects the byte to be read For a word wide memory the microcontroller reads an entire word then selects the required byte internally 5 31 8XC196NP 80C196NU USER S MANUAL intel Table 5 14 Memory Map for the System in Figure 5 11
40. CHAPTER 12 SPECIAL OPERATING MODES 12 1 SPECIAL OPERATING MODE SIGNALS AND 12 1 12 2 REDUCING POWER 12 3 viii intel CONTENTS 1239 IDEEMODBE Une crai essere d inti det dec 12 5 12 4 STANDBY 80C196NU 12 6 12 4 4 Enabling and Disabling Standby Mode seem 12 6 12 4 2 Entering Standby Mode eese nennen 12 6 12 4 8 Exiting Standby Mode see eene d 2 77 12 5 POWERDOWN aco nero ede au 12 7 12 5 1 Enabling and Disabling Powerdown 12 7 12 5 2 Entering Powerdown Mode esee eene 12 7 12 5 8 Exiting Powerdown Mode 2 12 8 12 5 3 1 Generating a Hardware Reset sse emen 12 8 12 5 3 2 Asserting an External Interrupt Signal eee 12 8 12 5 3 3 Selecting scirent ertet ene init read 12 10 12 6 ONGE MODE de ree E cg Tete m Eee e eese 12 12 12 7 RESERVED TEST MODES 80C196NU 12 12 CHAPTER 13 INTERFACING WITH EXTERNAL MEMORY 13 1 INTERNAL AND EXTERNAL ADDRESSES see eene 13 1 13 2 EXTERNAL MEMORY INTERFACE SIGNALS s
41. Capture Buffer Action taken when a valid edge occurs P amp EPAx TIME 0 empty Edge is captured and event time is loaded into the capture buffer and EPAx TIME register 0 full New data is ignored no capture EPA interrupt or transfer occurs OVRx interrupt pending bit is set 1 empty Edge is captured and event time is loaded into the capture buffer and EPAx TIME register 1 full Old data is overwritten in the capture buffer OVRx interrupt pending bit is set An input capture event does not set the interrupt pending bit until the captured time value actually moves from the capture buffer into the EPAx TIME register If the buffer contains data and the PTS is used to service the interrupts then two PTS interrupts occur almost back to back that is with one instruction executed between the interrupts 10 4 1 1 EPA Overruns Overruns occur when an EPA input transitions at a rate that cannot be handled by the EPA inter rupt service routine If no overrun handling strategy is in place and if the following three condi tions exist a situation may occur where both the capture buffer and the EPAx TIME register contain data and no EPA interrupt is generated e input signal with a frequency high enough to cause overruns is present on an enabled EPA pin and e the overwrite bit is set EPAx_CON 0 1 old data is overwritten on overrun and the EPAx TIME register is read at the exact instant that the EPA recognizes the capture
42. During transmissions setting the 8 bit in the SP CON register before writing to SBUF TX sets the ninth transmission bit The hardware clears the TB8 bit after every transmission so it must be set if desired before each write to SBUF TX During receptions the RI flag and RI interrupt pending bit are set only if the TB8 bit is set This provides an easy way to have selective reception on a data link See Multi processor Communications on page 8 8 Parity cannot be enabled in this mode Bop N Sa 00 X Di 92 X95 6 X DB Sup 8 Bits of Data Programmable 9th Bit k 11 Bit Frame gt 0111 01 Figure 8 5 Serial Port Frames in Mode 2 and 3 8 3 2 3 Mode 3 Mode 3 is the asynchronous ninth bit mode The data frame for this mode is identical to that of mode 2 Mode 3 differs from mode 2 during transmissions in that parity can be enabled in which case the ninth bit becomes the parity bit When parity is disabled data bits 0 7 are written to the serial port transmit buffer and the ninth data bit is written to bit 4 TB8 bit in the SP CON reg ister In mode 3 a reception always sets the RI interrupt pending bit regardless of the state of the ninth bit If parity is disabled the SP STATUS register bit 7 RB8 contains the ninth data bit If parity is enabled then bit 7 RB8 is the received parity error RPE flag 8 3 2 4 Mode 2 and 3 Timings Operation in modes 2 and 3 is similar to mo
43. PTS Block Size Specifies the number of bytes or words in each block Valid values are 1 32 inclusive PTSDST PTSCB 4 PTS Destination Address Write the destination memory location to this register A valid address is any unreserved memory location within page 00H however it must point to an even address if word transfers are selected PTSSRC PTSCB 2 PTS Source Address Write the source memory location to this register A valid address is any unreserved memory location within page 00H however it must point to an even address if word transfers are selected Figure 6 13 PTS Control Block Block Transfer Mode 6 24 intel STANDARD AND PTS INTERRUPTS PTS Block Transfer Mode Control Block Continued Register Location Function PTSCON PTSCB 1 PTS Control Bits M2 0 PTS Mode These bits select the PTS mode M2 Mi MO 0 0 0 block transfer mode BW Byte Word Transfer 0 word transfer 1 byte transfer SU Update PTSSRC 0 reload original PTS source address after each block transfer is complete 1 retain current PTS source address after each block transfer is complete DU Update PTSDST 0 reload original PTS destination address after each block transfer is complete 1 retain current PTS destination address after each block transfer is complete SI PTSSRC Autoincrement 0 do not increment the contents of PTSSRC after each byte or word transfer 1 increment the contents
44. PUSH ALL This instruction is used instead of PUSHF to support the eight additional interrupts It pushes two words PSW INT MASK and INT MASK1 WSR onto the stack This instruction clears the PSW INT MASK and INT MASK1 registers and decrements the SP by 4 Interrupt calls cannot occur immediately following this instruction SP lt SP 2 SP lt PSW INT MASK PSW INT MASK lt 0 SP lt SP 2 SP INT MASK1 WSR INT MASK1 lt 0 PSW Flag Settings V 5 0 0 0 0 0 0 PUSHA 11110100 PUSHF PUSH FLAGS Pushes the PSW onto the top of the stack then clears it Clearing the PSW disables interrupt servicing Interrupt calls cannot occur immediately following this instruction SP lt SP 2 SP lt PSW INT MASK PSW INT MASK lt 0 PSW Flag Settings V 5 0 0 0 0 0 0 PUSHF 11110010 RET RETURN FROM SUBROUTINE Pops the PC off the top of the stack 64 Kbyte mode 1 Mbyte mode PC lt SP PC lt SP SP lt SP 2 SP lt 4 PSW Flag Settings Z N C V VT ST RET 11110000 A 35 8 196 80C196NU USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format RST RESET SYSTEM Initializes the PSW to zero the EPC PC to FF2080H and the pins and SFRs to the
45. SXC196NP 80C196NU Microcontroller User s Manual August 1995 Information in this document is provided solely to enable use of Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel s Terms and Conditions of Sale for such products Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein Intel retains the right to make changes to these specifications at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation Intel Corporation and Intel s FASTPATH are not affiliated with Kinetics a division of Excelan Inc or its FASTPATH trademark or products Other brands and names are the property of their respective owners Additional copies of this document or other Intel literature may be obtained from Intel Corporation Literature Sales P O Box 7641 Mt Prospect IL 60056 7641 or call 1 800 879 4683 INTEL CORPORATION 1996 intel CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1 1 MANUAL CONTENTS 5 ir n re er ERE e Ee p ERE LH ETE Dev Ep oa P equ 1 1 1 2 NOTATI
46. Table 9 3 shows the PWM output frequencies for common operating frequencies on the 8XC196NP The value of CON REGO 0 determines the output fre quency by enabling or disabling the clock prescaler Use the following formulas to calculate the output frequency or output period T wym Clock Prescaler 2 Clock Prescaler 4 Clock Prescaler Disabled Enabled Enabled 3 f f Few in MHz 512 1024 2048 512 1024 2048 Tpwm inus E PROS E 80C196NU only 9 5 8 196 80C196NU USER S MANUAL er NOTE intel For the 80C196NU the PWM module provides three selectable fixed PWM output frequencies for a specified internal operating frequency f Table 9 3 shows the PWM output frequencies for common operating frequencies The value of bits 0 and 1 in the REGO register determines the output frequency by enabling or disabling the divide by two or divide by four clock prescal Use the EPA module to produce variable PWM output frequencies see Operating in Compare Mode on page 10 12 Table 9 3 PWM Output Frequencies 8XC196NP f CLKO 16 MHz 20 MHz 25 MHz 0 31 25 kHz 39 06 kHz 48 83 kHz 1 15 63 kHz 19 53 kHz 24 41 kHz Table 9 4 PWM Output Frequencies 80C196NU CLK1 CLKO 12 5 MHz 25 MHz 50 MHz 0 0 24 41 kHz 48 83 kHz 97 66 kHz 0 1 12 21 kHz 24 41 kHz 48 83 kHz 1 X 6 10 kHz 12 21 kHz 24 41 kHz 9 6 intel PULSE WIDTH MODULATOR
47. The EI and DI instructions enable and disable servicing of all maskable interrupts INT MASK1 can be read from or written to as a byte register PUSHA saves this register on the stack and POPA restores it 7 0 NMI 2 OVR2 3 1 2 1 Bit z Number Function 7 0 Setting a bit enables the corresponding interrupt The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector NMI Nonmaskable Interrupt FF203EH EXTINT3 EXTINTS pin FF203CH EXTINT2 EXTINT2 pin FF203AH OVR2 31 EPA Capture Channel 2 or 3 Overrun FF2038H OVRO 1 EPA Capture Channel 0 or 1 Overrun FF2036H EPAS3 EPA Capture Compare Channel 3 FF2034H EPA2 EPA Capture Compare Channel 2 FF2032H EPA1 EPA Capture Compare Channel 1 FF2030H An overrun on the EPA capture compare channels can generate the multiplexed capture overrun interrupts The EPA MASK and EPA PEND registers decode these multiplexed interrupts Write to EPA MASK to enable the interrupt sources read EPA PEND to determine which source caused the interrupt Figure 6 6 Interrupt Mask 1 INT MASK1 Register 6 5 2 Modifying Interrupt Priorities Your software can modify the default priorities of maskable interrupts by controlling the interrupt mask registers INT MASK and INT For example you can specify which interrupts if any can interrupt an interrupt service routine
48. and INST are weakly held in their inactive states Figure 13 16 shows the timing for bus hold protocol and Table 13 12 on page 13 31 lists the timing pa rameters and their definitions Refer to the datasheet for timing parameter values 13 30 intel INTERFACING WITH EXTERNAL MEMORY HOLD HLDA BREQ INST RD WR CLKOUT um x TuvcH gt gt 19 0 15 0 CSx BHE WRL WRH Hold Latency gt gt gt lt lt THALAZ gt THAHAX gt 2 gt THAHBV gt Weakly held inactive P Start of strongly driven ALE A2460 03 Figure 13 16 HOLD HLDA Timing Table 13 12 HOLD HLDA Timing Definitions Symbol Parameter Tuvcn HOLD Setup Time CLKOUT Low to HLDA Low Ternan CLKOUT Low to HLDA High CLKOUT Low to BREQ Low CLKOUT Low to BREQ High Tharaz HLDA Low to Address Float High to Address No Longer Float Low to BHE INST RD WR WRL WRH Weakly Driven HLDA High to BHE INST RD WR WRL WRH valid Tou Clock Falling to ALE Rising Use to derive other timings When the external device is finished with the bus it reli
49. for selecting an external device during an ex ternal bus cycle During an external memory access a chip select output 5 is asserted if the address falls within the address range assigned to that chip select The bus width the number of wait states and multiplexed or demultiplexed address data lines are programmed independently for each of the six chip selects If the external address is outside the range of the six chip selects the chip select 5 bus control register determines the wait states bus width and multiplexing and no chip select is asserted Table 13 3 lists the chip select registers 13 5 8XC196NP 80C196NU USER S MANUAL intel Table 13 3 Chip select Registers Register Em Mnemonic Address Description ADDRCOMO 1F40H Address Compare Register IECUR This 16 bit register holds the upper 12 bits of the base fth i ADDRCOM3 1F58H address of the address range assigned to 5 ADDRCOM4 1F60H ADDRCOMS5 1F68H ADDRMSKO 1F42H Address Mask Register ADDRMSK1 1F4AH This register determines the size of the address range ADDRMSK2 1F52H 256 bytes 1 Mbyte ADDRMSK3 1F5AH ADDRMSK4 1F62H ADDRMSK5 1F6AH BUSCONO 1F44H Bus Control Register BUSCON1 1F4CH This register determines the bus configuration for external BUSCON2 1 54 accesses to the address range assigned to CSx The BUSCON3 1FSCHI bus parameters are 8 or 16 bit bus width multiplexed or BUSCON4 1 demultiplexed address data lin
50. numbers register bits register names reserved bits signal names 1 4 Italics identify variables and introduce new terminology The context in which italics are used distinguishes between the two possible meanings Variables in registers and signal names are commonly represented by x and y where x represents the first variable and y represents the second variable For example in register MODE y x represents the variable that identifies the specific port associated with the register and y represents the register bit variable 7 0 or 15 0 Variables must be replaced with the correct values when configuring or programming registers or identifying signals Hexadecimal numbers are represented by a string of hexadecimal digits followed by the character H Decimal and binary numbers are represented by their customary notations That is 255 is a decimal number and 1111 1111 is a binary number In some cases the letter B is appended to binary numbers for clarity Bit locations are indexed by 7 0 or 15 0 where bit O is the least significant bit and bit 7 or 15 is the most significant bit An individual bit is represented by the register name followed by a period and the bit number For example WSR 7 is bit 7 of the window selection register In some discussions bit names are used Register mnemonics are shown in upper case For example TIMER2 is the timer 2 register timer 2 is the timer A register name containin
51. 60 opcode map A 2 A 3 opcodes A 47 A 52 overview 4 1 4 5 protected instructions 6 7 reference A 1 A 3 See also RISM INTEGER defined 4 3 Interrupts 6 1 6 36 and bus hold See bus hold protocol controller 2 6 6 1 end of PTS 6 18 inhibiting 6 7 latency 6 7 6 9 6 23 calculating 6 8 pending registers See EPA PEND EPA PENDI INT PEND INT PENDI priorities 6 4 6 5 modifying 6 13 6 15 procedures PLM 96 4 13 processing 6 2 programming 6 10 6 15 selecting PTS or standard service 6 10 service routine processing 6 14 sources 6 5 unused inputs 11 2 vectors 5 7 6 1 6 5 memory locations 5 6 5 7 Italics defined 1 4 J JBC instruction A 2 A 5 A 21 A 47 A 58 A 66 JBS instruction A 3 A 5 A 21 A 47 A 58 A 66 JC instruction 3 A 5 A 22 A 51 A 58 A 66 JE instruction A 3 A 5 A 22 A 51 A 58 A 66 JGE instruction A 2 A 5 A 22 A 51 A 58 A 66 JGT instruction 2 5 A 23 51 A 58 A 66 JH instruction A 3 A 5 A 23 A 51 A 58 A 66 JLE instruction 3 A 5 A 23 A 51 A 58 A 66 JLT instruction 3 A 5 24 51 58 A 66 Index 5 8 196 80C196NU USER S MANUAL JNC instruction A 2 A 5 A 24 A 51 A 58 66 JNE instruction A 2 A 5 24 51 58 66 instruction 2 5 25 51 58 66 JNST instruction 2 5 A 25 51 A 58 66 JNV instruction 2 5 25 51 58 66 JNVT in
52. 8 196 80C196NU USER S MANUAL intel Table A 9 Instruction Execution Times in State Times Continued Jump Mnemonic Direct Immed Extended indirect Extended indexed Normal Autoinc EBR 9 LI EJMP 8 Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long BR 7 T LJMP 7 SJMP 7 TIJMP register register _ _ 15 Er memory register 18 memory memory 21 Call Register Extended indirect Mnemonic Direct Immed Extended indexed Normal Autoinc ECALL 1 Mbyte mode 16 Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long LCALL 15 1 Mbyte mode E 11 64 Kbyte mode RET 1 Mbyte mode 16 64 Kbyte mode 11 SCALL 15 1 Mbyte mode 11 64 Kbyte mode TRAP 1 Mbyte mode 19 64 Kbyte mode 16 NOTE The column entitled Reg lists the instruction execution times for accesses to the register file or peripheral SFRs The column entitled Mem lists the instruction execution times for accesses to all memory mapped registers I O or memory See Table 5 1 on page 5 4 for address information A 64 intel INSTRUCTION SET REFERENCE Table A 9 Instruction Execution Times in State Times Continued Call Memory Extended indi
53. 8XC196NP intel SPECIAL OPERATING MODES Disable PLL Powerdown Phase Comparator Phase locked Oscillator XTAL2 Disable Disable Clock Input Ph i ase locked Loop ACH Mm Powercown Clock Multiplier Divide by two Circuit Disable Clocks PLLEN1 Standby Powerdown Generators CPU Clocks PH1 PH2 Disable Clocks Idle Standby Powerdown A3063 02 Figure 12 2 Clock Control During Power saving Modes 80C196NU 12 3 IDLE MODE In idle mode the device s power consumption decreases to approximately 4096 of normal con sumption Internal logic holds the CPU clocks at logic zero causing the CPU to stop executing instructions Neither the phased locked loop circuitry 80 19630 only the peripheral clocks nor CLKOUT are affected so the special function registers SFRs and register RAM retain their data and the peripherals and interrupt system remain active Table B 5 on page B 13 lists the val ues of the pins during idle mode 12 5 8XC196NP 80C196NU USER S MANUAL intel The device enters idle mode after executing the IDLPD 1 instruction Any enabled interrupt source either internal or external or a hardware reset can cause the device to exit idle mode When an interrupt occurs the CPU clocks restart and the CPU executes the corresponding inter rupt service or PTS routine When the routine is complete the CPU fetches and then execu
54. ADDRMSK1 Address Mask 1 1F4AH XXXX 1111 1111 1111 ADDRMSK2 Address Mask 2 1F52H XXXX 1111 1111 1111 ADDRMSK3 Address Mask 3 1F5AH 1111 1111 1111 ADDRMSK4 Address Mask 4 1F62H XXXX 1111 1111 1111 ADDRMSK5 Address Mask 5 1F6AH XXXX 1111 1111 1111 BUSCONO Bus Control 0 1F44H 0000 0011 BUSCON1 Bus Control 1 1F4CH 0000 0000 BUSCON2 Bus Control 2 1F54H 0000 0000 BUSCON3 Bus Control 3 1F5CH 0000 0000 BUSCON4 Bus Control 4 1F64H 0000 0000 BUSCONS Bus Control 5 1F6CH 0000 0000 CCRO Chip Configuration 0 FF2018H XXXX XXXX CCR1 Chip Configuration 1 FF201AH XXXX XXXX CON REGO PWM Clock Prescaler Control 0 1FB6H 1111 1110 EP DIR Extended Port I O Direction 1 1111 1111 EP MODE Extended Port Mode 1FE1H 1111 1111 PIN Extended Port Pin Input 1FE7H XXXX XXXX EP REG Extended Port Data Output 1FE5H XXXX 0000 EPA MASK EPA Mask 1F9CH 1010 1010 EPA PEND EPA Pending 1F9EH 1010 1010 EPAO CON EPA Capture Comp 0 Control 1F80H 0000 0000 EPA1 CON EPA Capture Comp 1 Control 1F84H 0000 0000 0000 0000 intel REGISTERS Table C 2 Register Name Address and Reset Status Continued Binary Reset Value eria Register Name 2_ EPA Capture Comp 2 Control 1F88H 0000 0000 EPA3 CON EPA Capture Comp 3 Control 1F8CH 0000 0000 0000 0000 EPAO TIME EPA Capture Comp 0 Time 1F82H 0000 0000 0000 0000 EPA1 TIME EPA C
55. Address ADDRCOMO 1F40H OOEOH 3DH 00COH 1EH 00COH ADDRCOM 1 1F48H 00 8 3DH 00C8H 1EH 00C8H ADDRCOM2 1F50H 7AH OOFOH 3DH 00DOH 1EH 00DOH ADDRCOMS 1F58H 00 8 3DH 00D8H 1EH 00D8H ADDRCOM4 1F60H 7BH OOEOH 3DH 00 1 00 ADDRCOM5 1F68H 7BH 00E8H 3DH 00 8 1 0 8 ADDRMSKO 1F42H 7AH 00 2 3DH 00C2H 1EH 00C2H ADDRMSK1 1 00 3DH 00 1 00 ADDRMSK2 1F52H 7AH 00F2H 3DH 00D2H 1EH 00D2H ADDRMSK3 1F5AH 7AH 00 3DH 00DAH 1EH 00DAH ADDRMSK4 1F62H 7BH 00 2 00 2 1 00 2 ADDRMSK5 1F6AH 7BH 00 3DH 00 1 00 BUSCONO 1F44H 00 4 3DH 00C4H 1EH 00C4H Must be addressed as a word C 49 8XC196NP 80C196NU USER S MANUAL intel WSR Table C 18 WSR Settings and Direct Addresses for Windowable SFRs Continued 32 byte Windows 64 byte Windows 128 byte Windows Register Memory 00E0 00FFH 00 0 0 0080 00FFH Mnemonic Location F WSR address WSR address WSR address BUSCON1 1F4CH 7AH 00 3DH 00CCH 1EH 00CCH BUSCON2 1F54H 7AH 00F4H 3DH 00D4H 1EH 00D4H BUSCONS3 1F5CH 7AH 00 3DH 00DCH 1EH 00DCH BUSCON4 1F64H 7BH 00 4 3DH 00 4 1 00E4H BUSCON5 1F6CH 7BH 00 3DH 00 1EH 00 REGO 1FB6H 7DH 00 6 OOF6H 1FH 00B6H EP DIR
56. BREQ HLDA HOLD software protection 13 32 timing parameters 13 30 Byte accesses and write control signals 13 34 BYTE defined 4 2 Call instructions A 57 A 64 A 65 Carry C flag 4 5 A 4 A 5 A 11 A 22 A 23 24 A 25 36 Cascading timers 10 6 CCBs 5 6 5 7 11 8 13 11 13 14 fetching 13 14 13 17 13 26 CCRO 12 2 CCRs 5 7 11 8 12 6 12 7 13 14 Chip configuration See CCBs CCRs Chip select 13 1 address range size 13 9 base address 13 9 conditions after reset 13 11 example 13 9 13 12 initializing 13 11 13 17 overlapping ranges 13 9 13 11 overview 2 6 registers 13 11 13 12 Clear defined 1 3 CLKOUT 12 1 13 3 13 18 13 22 B 7 and HOLD 13 30 and internal timing 2 8 and interrupts 6 6 and READY 13 27 considerations 7 10 reset status 7 4 Clock external 11 7 generator 11 7 internal and idle mode 12 5 12 6 12 7 modes 80C196NU 12 13 phases internal 2 9 slow 10 6 CLR instruction 2 A 11 A 47 A 53 A 60 CLRB instruction A 2 A 11 A 47 A 53 A 60 CLRC instruction A 3 A 11 A 52 A 59 A 67 CLRVT instruction 3 11 A 52 59 67 intel CMP instruction A 3 A 11 A 49 A 53 A 60 CMPB instruction A 3 A 12 A 50 A 53 A 60 CMPL instruction A 2 A 12 A 51 A 53 A 60 Code execution 2 4 2 5 Code fetches 5 25 CompuServe forums 1 10 Conditional jump instructions 5 CON 0 C 50 C 53 Constants near 5 24 CPU 2 3 CS5 0 B
57. COUNT 1 if COUNT 0 then go to LOOP PSW Flag Settings Z N C V VT ST PTRS CNTREG BMOVI wreg 11001101 wreg Ireg NOTE The pointers are autoincre mented during this instruction However CNTREG is decre mented only when the instruction is interrupted When BMOVI is interrupted CNTREG is updated to store the interim word count at the time of the interrupt For this reason you should always reload CNTREG before starting BMOVI BR BRANCH INDIRECT Continues execution at the address specified in the operand word register PC lt DEST PSW Flag Settings Z N C V VT ST DEST BR wreg 11100011 wreg NOTE 1 Mbyte mode the BR instruc tion always branches to page FFH Use the EBR instruction to branch to an address on any other page intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued operand The flags are altered but the Operands remain unaffected If a borrow occurs the carry flag is cleared otherwise it is set DEST SRC PSW Flag Settings 2 V VT ST 711 Mnemonic Operation Instruction Format CLR CLEAR WORD Clears the valu
58. Device 16 bit Demultiplexed Bus Bus Control 16 bit Multiplexed Address Data 8XC196 Device 16 bit Multiplexed Bus Bus Control Driven with the data currently on the internal bus 8XC196 Device 8 bit Demultiplexed Bus Bus Control 8 bit Multiplexed Address Data 8XC196 Device 8 bit Multiplexed Bus A2364 03 Figure 13 8 Multiplexing and Bus Width Options 13 19 8XC196NP 80C196NU USER S MANUAL intel A design can incorporate external devices that operate with different bus widths and multiplex ing The bus parameters used during a particular bus cycle are determined by the chip select out put that is assigned to the address being accessed Figure 13 9 shows the address and data bus configurations for the four combinations of bus width and multiplexing For detailed waveforms see 16 bit Bus Timings on page 13 22 and System Bus AC Timing Specifications on page 13 36 ALE N N ALE __ A19 0 A19 0 AD15 0 AD15 8 AD7 0 16 bit Demultiplexed Bus 8 bit Demultiplexed Bus ALE N N ALE N N 19 0 19 0 AD15 0 AD15 8 AD7 0 16 bit Multiplexed Bus 8 bit Multiplexed Bus AD15 8 drive the data currently on the high byte of the internal bus A2463 02 Figure 13 9 Bus Activity for Four Types of Buses In an 8 or 16 bit demultiplexed mode top of Figure 13 8 and Figure 13 9 the external device receives the address from A19 0 In a 16 bit syst
59. During an external memory access a chip select out put is asserted if the address falls within the address range assigned to that chip select The bus width the number of wait states and multiplexed or demultiplexed address data lines are pro grammed independently for the six chip selects The address range of the chip selects can be pro grammed for various granularities 256 bytes 512 bytes 512 Kbytes or 1 Mbyte The base address can be any address that is evenly divisible by the selected address range See Chapter 13 Interfacing with External Memory for more information 2 3 5 Multiply accumulate 80C196NU Only The 80C196NU is able to process multiply accumulate operations through the use of a hardware accumulator and enhanced multiplication instructions The accumulator includes a 16 bit adder a 3 to 1 multiplexer a 32 bit accumulator register and a control register The multiply accumu late function is enabled by any 16 bit multiplication instruction with a destination address that is in the range 00 The instructions can operate on signed integers unsigned integers and signed fractional numbers The control register allows you to enable saturation mode and frac tional mode for signed multiplication Chapter 3 Advanced Math Features describes the accu mulator 2 3 6 Interrupt Service The device s flexible interrupt handling system has two main components the programmable in terrupt controller and the perip
60. In the U S and Canada technical support representatives are available to answer your questions between 5 a m and 5 p m PST You can also fax your questions to us Please include your voice telephone number and indicate whether you prefer a response by phone or by fax Outside the U S and Canada please contact your local distributor 1 800 628 8686 U S and Canada 916 356 7599 U S and Canada 916 356 6100 fax U S and Canada 1 6 PRODUCT LITERATURE You can order product literature from the following Intel literature centers 1 800 468 8118 ext 283 U S and Canada 708 296 9333 U S from overseas 44 0 1793 431155 Europe U K 44 0 1793 421333 Germany 44 0 1793 421777 France 8 1 0 120 47 88 32 Japan fax only 1 11 intel Architectural Overview intel CHAPTER 2 ARCHITECTURAL OVERVIEW The 16 bit 8XC196NP and 80C196NU CHMOS microcontrollers are designed to handle high speed calculations and fast input output I O operations They share a common architecture and instruction set with other members of the MCS 96 microcontroller family In addition to their 16 bit address data buses both microcontrollers have extended addressing ports consisting of 4 external address pins for a total of 20 address pins With 20 address pins these microcontrollers can access up to 1 Mbyte of linear address space Both devices also have chip select units that provide a glueless interface to external memory devices The extended add
61. P1 7 0 B 9 See also port 1 P1 DIR C 50 C 53 P1 MODE C 50 C 53 P1 PIN C 50 C 53 P1 REG C 50 C 53 P2 2 considerations 12 9 P2 7 0 B 9 See also port 2 P2 DIR C 50 C 53 P2 MODE C 50 C 53 P2 PIN C 50 C 53 P2 REG C 50 C 53 P3 7 0 B 9 See also port 3 P3 DIR C 50 C 53 P3 MODE C 50 C 53 P3 PIN C 50 C 53 P3 REG C 50 C 53 P4 3 0 B 9 See also port 4 P4 DIR C 51 C 53 P4 MODE C 51 C 53 P4 PIN C 51 C 53 P4 REG C 51 C 53 Pages memory 5 1 5 2 page 00H 5 3 5 22 page OFH 5 2 page FFH 5 2 5 25 accessing 5 22 INDEX page number and EPORT 5 23 Parameters passing to subroutines 4 13 Parity 8 6 8 7 PC program counter 2 4 5 23 extended 2 6 5 23 5 25 7 13 master 2 4 2 5 slave 2 5 2 6 Period t 2 9 Peripherals internal 2 11 Pin diagrams B 1 PLLEN 2 1 2 9 12 2 B 10 PLM 96 conventions 4 11 4 12 4 13 interrupt procedures 4 13 POP instruction A 3 A 33 A 51 A 55 A 62 POPA instruction 2 A 34 A 52 A 55 A 62 POPF instruction 2 A 34 A 52 A 55 A 62 Port 1 2 11 B 9 considerations 7 9 input buffer 7 4 logic tables 7 6 operation 7 1 7 3 overview 7 1 SFRs 7 3 See also EPA Port 2 2 11 B 9 considerations 7 9 operation 7 1 7 3 overview 7 1 P2 2 considerations 7 9 P2 4 considerations 7 9 P2 5 considerations 7 9 P2 7 considerations 7 10 P2 7 reset status 7 4 7 10 SFRs 7 3 See also SIO port Port 3 consideration
62. PORT In mode 0 RXD must be enabled for receptions and disabled for transmissions See Program ming the Control Register on page 8 8 When RXD is enabled either a rising edge on the RXD input or clearing the receive interrupt RI flag in SP STATUS starts a reception When RXD is disabled writing to SBUF TX starts a transmission Disabling RXD stops a reception in progress and inhibits further receptions To avoid a partial or undesired complete reception disable RXD before clearing the RI flag in SP STATUS This can be handled in an interrupt environment by using software flags or in straight line code by using the interrupt pending register to signal the completion of a reception During a reception the RI flag in SP STATUS is set after the stop bitis sampled The RI pending bit in the interrupt pending register is set immediately before the RI flag is set During a transmis sion the TI flag is set immediately after the end of the last eighth data bit is transmitted The TI pending bit in the interrupt pending register is generated when the TI flag in SP STATUS is set TXD RXD OUT CY X 9 XC X 9 GD AD RXD IN os Expanded ise UL fus ee RXD OUT Co eee RXD IN Tr A0109 02 Figure 8 3 Mode 0 Timing 8 3 2 Asynchronous Modes Modes 1 2 and 3 Modes 1 2 and 3 are full duplex serial
63. PTS control blocks and the stack are most efficient when located in the upper register file 5 2 4 2 Stack Pointer SP Memory locations 0018H and 0019H contain the stack pointer SP The SP contains the address of the stack The SP must point to a word even address that is two bytes for 64 Kbyte mode or four bytes for 1 Mbyte mode greater than the desired starting address Before the CPU exe cutes a subroutine call or interrupt service routine it decrements the SP by two in 64 Kbyte mode by four in 1 Mbyte mode Next it copies PUSHes the address of the next instruction from the program counter onto the stack It then loads the address of the subroutine or interrupt service routine into the program counter When it executes the return from subroutine RET in struction at the end of the subroutine or interrupt service routine the CPU loads POPs the con tents of the top of the stack that is the return address into the program counter Finally it increments the SP by two in 64 Kbyte mode by four in 1 Mbyte mode intel Subroutines may be nested That is each subroutine may call other subroutines The CPU PUSH es the contents of the program counter onto the stack each time it executes a subroutine call The stack grows downward as entries are added The only limit to the nesting depth is the amount of available memory As the CPU returns from each nested subroutine it POPs the address off the top of the stack and the
64. TABLE BX loads AX with the contents of the memory location that re sides at address TABLE BX That is the instruction adds the contents of BX the offset to the constant TABLE the base address then loads AX with the contents of the resulting address For example if TABLE equals 4000H and BX contains 12H then AX is loaded with the contents of location 4012H Long indexed addressing is typically used to access elements in a table where TABLE is a constant that is the base address of the structure and BX is the scaled offset x el ement size in bytes into the structure 4 2 4 3 Extended Indexed Addressing The extended load and store instructions can use extended indexed addressing The only differ ence from long indexed addressing is that both the base address and the offset must be 24 bits to support access to the entire 1 Mbyte address space The following instructions use extended in dexed addressing In these instructions OFFSET is a 24 bit variable containing the offset and EX is a double word aligned 24 bit register containing the base address AX OFFSET EX ELDB AL OFFSET EX EST AX OFFSET EX ESTB AL OFFSET EX AX lt MEM WORD EX OFFSET AL lt MEM BYTE EX OFFSET MEM WORD EX OFFSET lt AX EX OFFSET lt AL 4 2 4 4 Zero indexed Addressing In a zero indexed instruction you specify the address as a 16 bit variable the offset is zero and you can express it in o
65. TB CE M1 MO RE ROT ON RT 7 0 0 2 M1 MO RE ROT ON RT Bit Bit Function Number Mnemonic 1 ROT Reset Opposite Timer Controls different functions for capture and compare modes In Capture Mode 0 causes no action 1 resets the opposite timer In Compare Mode Selects the timer that is to be reset if the RT bit is set 0 selects the reference timer for possible reset 1 selects the opposite timer for possible reset The TB bit bit 7 selects which is the reference timer and which is the opposite timer 0 ON RT Overwrite New Reset Timer The ON RT bit functions as overwrite new in capture mode and reset timer in compare mode In Capture Mode ON An overrun error is generated when an input capture occurs while the event time register EPAx TIME and its buffer are both full When an overrun occurs the ON bit determines whether old data is overwritten or new data is ignored 0 ignores new data 1 overwrites old data in the buffer In Compare Mode RT 0 disables the reset function 1 resets the ROT selected timer These bits apply to the EPA1 CON and CON registers only Figure 10 10 EPA Control EPAx CON Registers Continued 10 21 8XC196NP 80C196NU USER S MANUAL intel 10 6 ENABLING THE EPA INTERRUPTS The EPA generates four individual event interrupts EPA3 0 from the four capture compare chan nels and two timer interrupts OVRTM1 and
66. The maximum output frequency depends upon the total interrupt latency and the interrupt service execution times used by your system As additional EPA channels and the other functions of the microcontroller are used the maximum PWM frequency decreases because the total interrupt la tency and interrupt service execution time increases To determine the maximum low speed PWM frequency in your system calculate your system s worst case interrupt latency and worst case interrupt service execution time and then add them together The worst case interrupt la tency is the total latency of all the interrupts both normal and PTS used in your system The worst case interrupt service execution time is the total execution time of all interrupt service rou tines and PTS routines Assume a system with a single EPA channel a single enabled interrupt and the following inter rupt service routine If EPA0 3 interrupt is generated EPA0 3 ISR PUSHA LD EPAx CON fstoggle command ADD EPAx TIME TIMERx next duty ptr Load next event time POPA RET worst case interrupt latency for a single interrupt system is 56 state times for external stack usage and 54 state times for internal stack usage see Standard Interrupt Latency on page 6 8 To determine the execution time for an interrupt service routine add up the execution time of the instructions Table A 9 total execution time for the ISR that services interrupts EPA3 0 is 79 sta
67. and they cannot be windowed ttt The EPA_PEND register was called EPA STAT in previous documentation for the 8XC196NP tttt The 8XC196NP can be identified by its signature word 80EFH at locations 1F46 1F47H The 8XC196NU has no signature word locations 1F46 1F47H are reserved intel MEMORY PARTITIONS Table 5 5 Peripheral SFRs Continued EPA Timer 1 and Timer 2 SFRs Continued Chip select SFRs Continued Address High Odd Byte Low Even Byte Address High Odd Byte Low Even Byte 1F7EH Reserved Reserved 1 Reserved Reserved 1F7CH Reserved Reserved 1F4CH Reserved BUSCON 1 1F7AH Reserved Reserved 1F4AH ADDRMSK1 H ADDRMSK1 L 1F78H Reserved Reserved 1F48H ADDRCOM H ADDRCOM L 1F76H Reserved Reserved 1F46H Signature Signature 1117 1F74H Reserved Reserved 1F44H Reserved BUSCONO 1F72H Reserved Reserved 1F42H ADDRMSKO H ADDRMSKO L 1F70H Reserved Reserved 1F40H ADDRCOMO H ADDRCOMO L t Must be addressed as a word tt For the 8XC196NP these are memory mapped locations They must be addressed with indirect or indexed instructions and they cannot be windowed ttt The EPA PEND register was called EPA STAT in previous documentation for the 8XC196NP tttt The 8XC196NP can be identified by its signature word 80EFH at locations 1 46 1 47 The 8XC196NU has no signature word locations 1F46 1F47H are r
68. circuitry Capacitive coupling between the crystal oscillator and traces carrying fast rising digital signals can introduce noise spikes To reduce this coupling mount the crystal oscillator and ca pacitors near the device and use short direct traces to connect to XTALI XTAL2 and To further reduce the effects of noise use grounded guard rings around the oscillator circuitry and ground the metallic crystal case 8XC196 Device Quartz Crystal Note Mount the crystal and capacitors close to the device using short direct traces to XTAL1 XTAL2 and Vss When using a crystal 1 2 20 pF When using a ceramic resonator consult the manufacturer for recommended oscillator circuitry A0273 02 Figure 11 4 External Crystal Connections In cost sensitive applications you may choose to use a ceramic resonator instead of a crystal os cillator Ceramic resonators may require slightly different load capacitor values and circuit con figurations Consult the manufacturer s datasheet for the requirements intel MINIMUM HARDWARE CONSIDERATIONS 11 5 USING AN EXTERNAL CLOCK SOURCE To use an external clock source apply a clock signal to XTAL1 and let XTAL2 float Figure 11 5 To ensure proper operation the external clock source must meet the minimum high and low times and Ty xx and the maximum rise and fall transition times Ty and Figure 11 6 The longer the rise and fall times t
69. knowledgment is four state times plus the execution time of the next instruction When a standard interrupt request is acknowledged the hardware clears the interrupt pending bit and forces a call to the address contained in the corresponding interrupt vector When a PTS in terrupt request is acknowledged the hardware immediately vectors to the PTSCB and begins ex ecuting the PTS routine 6 4 4 Situations that Increase Interrupt Latency If an interrupt request occurs while any of the following instructions are executing the interrupt will not be acknowledged until after the next instruction is executed the signed prefix opcode FE for the two byte signed multiply and divide instructions any of these eight protected instructions DI EI DPTS EPTS POPA POPF PUSHA PUSHF see Appendix A for descriptions of these instructions any of the read modify write instructions AND ANDB OR ORB XOR XORB Both the unimplemented opcode interrupt and the software trap interrupt prevent other interrupt requests from being acknowledged until after the next instruction is executed Each PTS cycle within a PTS routine cannot be interrupted A PTS cycle is the entire PTS re sponse to a single interrupt request In block transfer mode a PTS cycle consists of the transfer of an entire block of bytes or words This means a worst case latency of 500 states if you assume a block transfer of 32 words from one external memory location to another
70. maskable interrupt can be assigned to the PTS for processing Most significant bit of a byte or most significant byte of a word The configuration in which the device uses both A19 0 and AD15 0 for address and also uses AD15 0 for data See also demultiplexed bus An operation performed by the 8XCI96NU s enhanced multiplication instructions The result of the operation is stored in a dedicated 32 bit accumulator A field effect transistor with an n type conducting path channel Semiconductor material with introduced impurities doping causing it to have an excess of negatively charged carriers Constants that can be accessed with nonextended instructions Constants in page are near constants REG is assumed See also far constants Data that can be accessed with nonextended instruc tions Data in page 00H is near data EP REG 00H is assumed See also far data Interrupts that cannot be masked disabled and cannot be assigned to the PTS for processing The nonmaskable interrupts are unimplemented opcode software trap and NMI intel nonvolatile memory npn transistor p channel FET p type material PC phase locked loop PIC PLL prioritized interrupt program memory protected instruction GLOSSARY Read only memory that retains its contents when power is removed Many MCS 96 microcontrollers are available with either masked ROM EPROM or OTPROM Consult the Automotive
71. the address can be expressed in the upper seven bits the least significant bit determines the addressing mode Indirect normal and short indexed modes make the second byte of the instruction even LSB 0 Indirect autoincrement and long indexed modes make the second byte odd LSB 1 2 For indexed instructions the first column lists instruction lengths as S L where S is the short indexed instruction length and L is the long indexed instruction length 3 Forthe SCALL and SJMP instructions the three least significant bits of the opcode are concatenated with the eight bits to form an 11 bit 2 s complement offset A 55 8XC196NP 80C196NU USER S MANUAL intel Table A 8 Instruction Lengths and Hexadecimal Opcodes Continued Data UT Extended Direct Immediate Extended indirect indexed Length Opcode Length Opcode Length Opcode Length Opcode EBMOVI 3 E4 ELD 3 E8 6 E9 ELDB 3 EA 6 EB EST 3 1C 6 1D ESTB 3 1E 6 1F Direct Immediate 51 eee Mnemonic Length Length Opcode Length Opcode Length Opcode S L Opcode BMOV 3 C1 BMOVI 3 CD LD 3 4 1 3 A2 4 5 LDB 3 BO 3 B1 3 B2 4 5 B3 LDBSE 3 BC 3 BD 3 BE 4 5 BF LDBZE 3 AC 3 AD 3 AE 4 5 AF ST 3 CO 3 C2 4 5 C3 STB 3 C4 3 C6 4 5 C7 XCH 3 04 4 5 0B XCHB
72. window selection register WSR onto the stack and then clears the PSW INT MASK and INT 5 registers In addition to the arithmetic flags the PSW contains the global interrupt enable bit I and the PTS enable bit PSE By clearing the PSW and the interrupt mask registers PUSHA effectively masks all maskable interrupts disables standard interrupt servicing and disables the PTS Because PUSHA is a protected instruction it also inhibits interrupt calls until after the next instruction executes LDB INT instruction enables those interrupts that you choose to allow to interrupt the service routine In this example only EXTINT3 can interrupt the receive interrupt service routine By enabling or disabling interrupts the software establishes its own interrupt servicing priorities The EI instruction re enables interrupt processing and inhibits interrupt calls until after the next instruction executes The actual interrupt service routine executes within the priority structure established by the software intel STANDARD AND PTS INTERRUPTS 6 Attheend of the service routine the POPA instruction restores the original contents of the PSW INT MASK INT MASKI and WSR registers any changes made to these registers during the interrupt service routine are overwritten Because interrupt calls cannot occur immediately following a POPA instruction the last instruction RET will execute before another interrupt call can occ
73. 035F 5AH 2DH 0320 033F 59H 0300 031F 58H 2CH 16H 02bE0 02FF 57H 02C0 02DF 56H 2BH 02A0 02BF 55H 0280 029F 54H 2AH 15H 0260 027F 53H 0240 025 52 29H 0220 023F 51H 0200 021 50 28H 14H 01E0 01FF 4FH 01C0 01 DF 4EH 27H 01A0 01BF 4DH 0180 019 4 26 13 0160 017 4 0140 015 4 25H 0120 013 49H 0100 011 48H 24H 12H 5 3 2 Addressing Location Through a Window After you have selected the desired window you need to know the direct address of the memory location the address in the lower register file For SFRs refer to the WSR tables in Appendix C For register file locations calculate the direct address as follows 1 Subtract the base address of the area to be remapped from Table 5 10 on page 5 17 from the address of the desired location This gives you the offset of that particular location 2 Add the offset to the base address of the window from Table 5 11 The result is the direct address intel MEMORY PARTITIONS Table 5 10 Windows Base WSR or WSR1 Value WSR or WSR1 Value for Address for 32 byte Window for 64 byte Window Win diu Hex 00E0 00FFH or 0060 007 00C0 00FFH or 0040 007 0080 00FFH Peripheral SFRs HFEO T7FH 1FCO 7EH T8FH 1 0 7DH 1F80 7CH 1 60 7BH 1F40 7AH 3DH 1F20 79H 1F00 78H 3CH 1EH Up
74. 1 00 00 1 00 EP MODE 1FE1H 7FH 00 00 1 00 1FE7H 7FH 00E7H 00 7 1FH 00 7 REG 1FE5H 7FH 00 5 00 5 1 00 5 EPA MASK 1F9CH 7CH 00 00DCH 1FH 009CH EPA PEND 1F9EH 7CH 00 00DEH 1FH 009 0 1F80H 7CH 00 00 0 1 0080H EPA1 1F84H 7CH 00 4 00C4H 1FH 0084H EPA2 CON 1F88H 7CH 00 8 00 8 1 0088 1F8CH 7CH 00 00CCH 1FH 008CH EPAO TIME 1F82H 7CH 00 2 00C2H 1FH 0082H EPA1 1F86H 7CH 00 6 00C6H 1FH 0086H EPA2 1F8AH 7CH 00 00 1 008AH EPA3 1F8EH 7CH 00 00 1 008 P1 DIR 1FD2H 7EH 00 2 00D2H 1FH 00D2H P1 MODE 1FDOH 7EH OOFOH 3FH 00DOH 1FH 00DOH P1 PIN 1FD6H 7EH 00 6 00D6H 1FH 00D6H P1 REG 1FD4H 7EH 00 00D4H 1FH 00D4H P2 DIR 1FD3H 7EH O0F3H 00D3H 1FH 00D3H P2_MODE 1FD1H 7EH 00 00D1H 1FH 00D1H P2 PIN 1FD7H 7EH 00F7H 00D7H 1FH 00D7H P2 REG 1FD5H 7EH 00 5 00D5H 1FH 00D5H P3 DIR 1FDAH 7EH OOFAH 3FH 00DAH 1FH 00DAH P3 MODE 1FD8H 7EH 00 8 00D8H 1FH 00D8H P3 PIN 1FDEH 7EH 00 00DEH 1FH 00DEH P3 REG 1FDCH 7EH 00 00DCH 1FH 00DCH Must be addressed as a word C 50 In lel REGISTERS WSR Tabl
75. 1 Handbooks and Product Information Title and Description Order Number Intel Embedded Quick Reference Guide 272439 Solutions for Embedded Applications Guide 240691 Data on Demand fact sheet 240952 Data on Demand annual subscription 6 issues Windows version 240897 Complete set of Intel handbooks on CD ROM Handbook Set handbooks and product overview 231003 Complete set of Intel s product line handbooks Contains datasheets application notes article reprints and other design information on microprocessors periph erals embedded controllers memory components single board computers microcommunications software development tools and operating systems Automotive Products 231792 Application notes and article reprints on topics including the MCS 51 and MCS 96 microcontrollers Documents in this handbook discuss hardware and software implementations and present helpful design techniques Embedded Applications handbook 2 volume set 270648 Datasheets architecture descriptions and application notes on topics including flash memory devices networking chips and MCS 51 and MCS 96 microcon trollers Documents in this handbook discuss hardware and software implementa tions and present helpful design techniques Embedded Microcontrollers 270646 Datasheets and architecture descriptions for Intel s three industry standard micro controllers the MCS 48 MCS 51 and MCS 96 microcontrollers Periphe
76. 1 EPA1 yo EPA P1 2 EPA2 yo EPA P1 3 yo EPA P1 4 T1CLK Timer 1 P1 5 T1DIR Timer 1 P1 6 T2CLK Timer 2 P1 7 T2DIR Timer 2 P2 0 TXD SIO P2 1 RXD SIO P2 2 EXTINTO Interrupts P2 3 BREQ Bus controller P2 4 EXTINT1 Interrupts P2 5 HOLD Bus controller P2 6 Bus controller P2 7 CLKOUT O Clock generator P3 0 50 Chip select unit P3 1 51 Chip select unit P3 2 52 Chip select unit P3 3 53 Chip select unit P3 4 54 Chip select unit P3 5 55 Chip select unit P3 6 EXTINT2 Interrupts P3 7 Interrupts P4 0 PWMO PWM PWM1 PWM P4 2 PWM2 PWM P4 3 Vo Table 7 3 lists the registers associated with the bidirectional ports Each port has three control reg isters Px DIR and Px REG they can be both read and written The Px PIN regis ter is a status register that returns the logic level present on the pins it can only be read The registers are byte addressable and can be windowed Bidirectional Port Considerations page 7 9 discusses special considerations for reading P2 7 intel PORTS Table 7 3 Bidirectional Port Control and Status Registers Mnemonic Address Description P1 DIR 1FD2H Port x Direction P2 DIR 1FCBH DIR 1FDAH Each bit of Px DIR controls the direction of the corresponding pin P4 DIR 1FDBH 0 complementary output output only T 1 input or ope
77. 2 See also MUL instruction MULU instruction Multiprocessor communications SIO port 8 7 8 8 MULU instruction 3 1 A 3 A 30 A 48 A 49 A 52 A 54 A 61 MULUB instruction A 3 A 31 A 48 A 49 A 54 A 61 N Naming conventions 1 3 1 4 NEG instruction 2 A 31 A 47 A 54 A 61 Negative N flag A 4 A 5 A 22 A 23 A 24 NEGB instruction A 2 A 31 A 47 A 54 A 61 NMI 6 3 6 4 6 6 B 9 and bus hold protocol 13 33 hardware considerations 6 6 Noise reducing 7 1 7 4 11 4 11 5 11 6 Nonextended addressing 5 23 NOP instruction 4 14 A 3 A 31 A 52 A 59 A 67 two byte See SKIP instruction NORML instruction 4 5 A 3 32 A 47 A 59 A 66 NOT instruction 2 A 32 A 47 A 54 A 61 Notational conventions 1 3 1 4 NOTB instruction A 2 A 32 A 47 A 54 A 61 Numbers conventions 1 4 ONCE 12 1 B 9 ONCE mode 2 12 12 12 entering 12 12 exiting 12 12 Opcodes A 47 EE and unimplemented opcode interrupt A 3 A 52 FE and signed multiply and divide A 3 intel map A 2 reserved A 3 A 52 Operand types See data types Operands addressing 4 12 Operating modes 2 12 See also 1 Mbyte mode 64 Kbyte mode OR instruction A 2 A 33 A 49 A 54 A 61 ORB instruction A 2 A 33 A 49 A 54 A 61 Oscillator and powerdown mode 12 7 external crystal 11 6 on chip 11 5 Overflow V flag A 4 A 5 A 25 A 26 Overflow trap VT flag A 4 A 5 A 11 A 26 27
78. 3 saturation mode 3 2 setting mode bits SME and FME 3 6 C 7 Accumulator RALU 2 4 AD15 0 5 1 13 2 13 20 B 6 after reset 13 18 ADD instruction A 2 A 7 A 48 A 53 A 60 ADDB instruction A 2 A 7 A 48 A 49 A 53 A 60 ADDC instruction A 2 A 7 50 A 53 A 60 ADDCB instruction A 2 A 8 A 50 A 53 A 60 ADDRCOM2 C 49 C 52 ADDRCOM3 C 49 C 52 ADDRCOM4 C 49 C 52 ADDRCOMS C 49 C 52 ADDRCOM x 13 6 13 9 13 11 example 13 13 initializing 13 12 Address lines extended See A19 16 EPORT Address space 2 6 5 1 16 Mbyte address space 5 1 INDEX 1 Mbyte address space 5 1 5 25 accessing pages 01 7 18 external 5 1 internal 5 2 partitions 5 3 5 12 register RAM 5 11 SFRs See SFRs special purpose memory See special purpose memory Address data bus 2 5 13 30 AC timing specifications 13 36 13 45 bus width See bus width contention 13 17 for CCBO fetch 13 17 for CCB1 fetch 13 17 multiplexing 13 1 13 5 13 12 13 18 13 25 Addresses internal and external 1 3 5 1 13 1 notation 1 3 Addressing modes 4 6 4 7 6 ADDRMSKO C 49 C 52 ADDRMSKI C 49 C 52 ADDRMSK2 C 49 C 52 ADDRMSK3 C 49 C 52 ADDRMSKA C 49 C 52 ADDRMSKS C 49 C 52 ADDRMSKx 13 6 13 9 13 11 13 13 example 13 13 initializing 13 12 ALE 13 3 13 22 B 7 during bus hold 13 30 Analog outputs generating 9 9 AND instruction A 2 A 8 A 47 A 48 A 54 A 61 ANDB instruction A 2 A 8 A 9 A 48 A 49
79. 3 14 4 5 1B NOTES 1 Indirect normal and indirect autoincrement share the same opcodes as do short and long indexed modes Because word registers always have even addresses the address can be expressed in the upper seven bits the least significant bit determines the addressing mode Indirect normal and short indexed modes make the second byte of the instruction even LSB 0 Indirect autoincrement and long indexed modes make the second byte odd LSB 1 2 For indexed instructions the first column lists instruction lengths as S L where S is the short indexed instruction length and L is the long indexed instruction length 3 For the SCALL and SJMP instructions the three least significant bits of the opcode are concatenated with the eight bits to form an 11 bit 2 s complement offset A 56 intel INSTRUCTION SET REFERENCE Table A 8 Instruction Lengths and Hexadecimal Opcodes Continued Jump UT Extended erant Direct Immediate Extended indirect indexed Length Opcode Length Opcode Length Opcode Length Opcode EBR 2 EJMP 4 E6 Direct Immediate Note 1 pane Mnemonic Length Opcode Length Opcode Length Opcode pi Opcode BR 2 E3 LJMP 3 7 SJMP Note 3 2 20 27 TIJMP 4 E2 4 E
80. 3 Reserved Memory Locations 5 7 5 2 2 4 Interr pt and PTS Vectors cn bene rtr eere ot cene ede d e danh 5 7 5 2 2 5 Chip Configuration Bytes eene 5 7 5 2 3 Peripheral Special function Registers SFRS sse 5 7 5 2 4 Register File erona e en 5 9 5 2 4 1 General purpose Register RAM sse emen 5 11 5 24 2 Stack Pointer SP seien ied iere ince en ceo monct d Rp Ucet 5 11 5 243 Special function Registers 5 12 5 3 WINDOWING 11 eS oe ei tiae eet 5 13 5 8 1 Selecting a WindOW soisten ie C shai th shack RE E UE ERE ip 5 14 5 3 2 X Addressing a Location Through a Window see 5 16 5 3 2 1 32 byte Windowing Example 2 emen 5 18 5 3 2 2 64 byte Windowing Example emm emen 5 18 5 3 2 3 128 byte Windowing Example OT WO 5 3 2 4 Unsupported Locations Windowing Example 8XC196NP Only 5 19 5 3 2 5 Using the Linker Locator to Set Up a Window eee 5 19 5 3 3 Windowing and Addressing Modes 3 A 5 4 REMAPPING INTERNAL ROM 83C196NP ONLY eese 5 22 5 5 FETCHING CODE AND DATA IN THE 1 AND 64 4 KBYTE MODES ipd 5 23 5 5 1 Fetching e RR 5 23 5 55 2 Accessing Data ae nd degere odes 5 23 5 5 8 Code
81. 6 Instruction Set Continued Mnemonic Operation Instruction Format SHLL SHIFT DOUBLE WORD LEFT Shifts the destination double word operand to the left as many times as specified by the count operand The count may be specified either as an immediate value in the range of 0 to 15 OFH inclusive or as the content of any register 10H OFFH with a value in the range of 0 to 31 1FH inclusive The right bits of the result are filled with zeros The last bit shifted out is saved in the carry flag Temp lt COUNT do while Temp 0 C lt High order bit of DEST DEST lt DEST x 2 Temp lt Temp 1 end while PSW Flag Settings 2 V VT ST SHLL lreg count 00001101 count breg or SHLL lreg breg 00001101 breg Ireg SHR LOGICAL RIGHT SHIFT WORD Shifts the destination word operand to the right as many times as specified by the count operand The count may be specified either as an immediate value in the range of 0 to 15 inclusive or as the content of any register 10H OFFH with a value in the range of 0 to 31 1FH inclusive The left bits of the result are filled with zeros The last bit shifted out is saved in the carry flag Temp lt COUNT do while Temp 0 C lt Low order bit of DEST DEST DEST 2 Temp Temp 1 end while PSW Flag Settings Z N C V VT ST
82. 7 during bus hold 13 30 Customer service 1 8 D D A converter 9 10 Data far 5 24 fetches 5 26 near 5 24 types 4 1 4 5 addressing restrictions 4 1 converting between 4 4 defined 4 1 iC 96 4 1 PLM 96 4 1 signed and unsigned 4 1 4 4 values permitted 4 1 Data instructions A 56 A 63 Datasheets online 1 10 ordering 1 7 Deassert defined 1 3 DEC instruction A 2 A 12 A 47 A 53 A 60 DECB instruction 2 A 12 A 47 A 53 A 60 DEMUX bit 13 11 13 17 Device minimum hardware configuration 11 1 reset 11 8 11 9 11 10 11 11 13 33 signal descriptions B 6 DI instruction A 3 A 13 A 52 A 59 A 67 Digital to analog converter 9 10 Direct addressing 4 7 4 11 5 11 and register RAM 5 11 and windows 5 13 5 21 DIV instruction A 13 52 54 A 61 DIVB instruction 13 A 52 A 54 61 INDEX DIVU instruction A 3 A 14 49 54 A 61 DIVUB instruction 3 A 14 A 50 A 54 61 DJNZ instruction A 2 A 5 A 14 A 51 A 58 66 DJNZW instruction 2 5 A 15 51 58 66 Documents related 1 5 1 8 DOUBLE WORD defined 4 3 DPTS instruction A 3 A 15 A 52 A 59 A 67 E EA 5 5 5 6 5 22 5 25 5 26 13 4 B 8 after reset 13 18 instruction 4 5 2 A 16 A 51 A 56 EBR indirect instruction 4 5 A 2 A 16 A 51 57 64 ECALL instruction 4 5 2 17 A 52 57 64 A 65 EDAR 7 13 EE opcode and unimplemented opcode i
83. 7 CE Counter Enable This bit enables or disables the timer From reset the timers are disabled and not free running 0 disables timer 1 enables timer 6 UD Up Down This bit determines the timer counting direction in selected modes see mode bits M2 0 0 count down 1 count up 5 8 M2 0 EPA Clock Direction Mode Bits These bits determine the timer clocking source and direction source M2 1 0 Clock Source Direction Source 0 0 0 f 4 UD bit T2CONTROL 6 X 0 1 T2CLK pin UD bit T2CONTROL 6 0 1 0 f 4 T2DIR pin 0 1 1 T2CLK pin T2DIR pin 1 0 0 timer 1 overflow UD bit T2CONTROL 6 1 1 0 timer 1 same as timer 1 1 1 1 quadrature clocking using T2CLK and T2DIR t If an external clock is selected the timer counts on both the rising and falling edges of the clock 2 0 P2 0 EPA Clock Prescaler Bits These bits determine the clock prescaler value P2 PO Prescaler Resolution 0 0 0 divide by 1 disabled 160 ns 0 0 1 divide by 2 320 ns 0 1 0 divide by 4 640 ns 0 1 1 divide by 8 1 28 us 1 0 0 divide by 16 2 56 us 1 0 1 divide by 32 5 12 us 1 1 0 divide by 64 10 24 us 1 1 1 divide by 128 NU only 20 48 us Atf 25 MHz Use the formula on page 10 6 to calculate the resolution at other frequencies Figure 10 9 Timer 2 Control T2CONTROL Register 10 17 8XC196NP 80C196NU USER S MANUAL intel 10 5 3 Programming the Capture Compare Channels The EPAx CON register contro
84. 93 XOR 3 84 4 85 3 86 4 5 87 XORB 3 94 3 95 3 96 4 5 97 NOTES 1 Indirect normal and indirect autoincrement share the same opcodes as do short and long indexed modes Because word registers always have even addresses the address can be expressed in the upper seven bits the least significant bit determines the addressing mode Indirect normal and short indexed modes make the second byte of the instruction even LSB 0 Indirect autoincrement and long indexed modes make the second byte odd LSB 1 2 For indexed instructions the first column lists instruction lengths as S L where S is the short indexed instruction length and L is the long indexed instruction length 3 Forthe SCALL and SJMP instructions the three least significant bits of the opcode are concatenated with the eight bits to form an 11 bit 2 s complement offset 54 intel INSTRUCTION SET REFERENCE Table A 8 Instruction Lengths and Hexadecimal Opcodes Continued Stack Indirect Indexed Direct Immediate Note 1 Notes 1 2 Mnemonic Length Length Opcode Length Opcode Length Opcode S L Opcode POP 2 CC 2 CE 3 4 CF POPA 1 F5 POPF 1 F3 PUSH 2 C8 3 C9 2 CA 3 4 CB PUSHA 1 F4 PUSHF 1 F2 NOTES 1 Indirect normal and indirect autoincrement share the same opcodes as do short and long indexed modes Because word registers always have even addresses
85. A 54 A 61 ApBUILDER software downloading 1 10 Application notes ordering 1 6 Arithmetic instructions A 53 A 54 A 60 A 61 Assert defined 1 3 Baud rate SIO port 8 8 8 13 Index 1 8 196 80C196NU USER S MANUAL Baud rate generator SIO port 8 8 BAUD VALUE 8 11 42 BHE 13 3 7 during bus hold 13 30 See also write control signals BIT defined 4 2 Bit test instructions A 21 Block diagram address data bus 7 11 clock circuitry 2 7 core 2 3 core and peripherals 2 2 EPA 10 2 EPORT 7 13 I O ports 7 1 7 5 7 11 7 13 7 15 SIO port 8 1 10 2 Block transfer mode See PTS instruction 2 9 A 51 56 BMOVI instruction 3 9 A 10 A 51 56 BR indirect instruction A 2 A 10 A 51 A 57 A 64 BREQ 13 3 13 30 B 7 Bulletin board system BBS 1 9 Bus contention See address data bus contention Bus controller 2 5 Bus width 13 5 8 and 16 bit comparison 13 18 13 22 and write control signals 13 34 CCBO fetch 13 17 control bit 13 11 13 17 selecting 13 1 BUSCONO C 49 C 52 BUSCONI C 50 C 52 BUSCON2 50 C 52 BUSCON3 C 50 52 BUSCONA C 50 C 52 BUSCONS C 50 C 53 BUSCONx 13 10 13 11 13 26 example 13 12 Bus hold protocol 13 1 13 30 13 33 and code execution 13 33 and interrupts 13 33 and reset See reset disabling 13 32 enabling 13 32 hold latency 13 32 regaining bus control 13 33 Index 2 intel signals 13 30 See also port 2
86. Because EPAO is not used as an output port pin P1 0 can be used for standard I O Clear DIR 1 selects output Set PI MODE 1 selects the EPAO special function signal Set P1 REG 1 initializes the output to 1 intel STANDARD AND PTS INTERRUPTS Table 6 9 PWM Remap Mode PTSCB PTSCBO for EPAO PTSCB1 for EPA1 Unused Unused Unused Unused PTSCONST1 T2 HI PTSCONST1 T2 HI PTSCONST1 LO T2 LO PTSCONST1 LO T2 LO PTSPTR 1FH EPAO TIME HI PTSPTR 1FH EPA1 TIME HI PTSPTR1 LO 82H EPAO TIME LO PTSPTR1 LO 86H 1 TIME LO PTSCON 40H Mode 010 TMOD 0 PTSCON 40H Mode 010 TMOD 0 Unused Unused Set up EPAO and EPA1 Load EPAO_CON with 68H timer 1 compare mode assert output pin re enable Load EPA1_CON with 158H timer 1 compare mode deassert output pin re enable remap enabled Load EPAO TIME with 0000H selects time 0 as first event time for EPAO Load TIME with the value of T1 selects time as first event time for 1 Load timer 1 with FFFFH to ensure that the EPAO event time time 0 is matched first Load TICONTROL with C2H enables timer 1 selects up counting at f 4 and enables the divide by four prescaler Enable the EPAO and 1 interrupts and select PTS service for them Set INT MASK 7 and
87. Continues if DJNZ decremented byte 0 decremented byte 0 DJNZW decremented word 0 decremented word 0 JBC specified register bit 0 specified register bit 1 JBS specified register bit 1 specified register bit 0 JNC 0 1 JNH C 0ORZ 1 C 1ANDZ 0 JC 1 0 JH C 1ANDZ 0 C 0ORZ 1 JGE N 0 N 1 JGT N 0ANDZ 0 N 1ORZ 1 JLT N 1 N 0 JLE N 10ORZ 1 N 0ANDZ 0 JNST ST 0 ST 1 JST ST 1 ST 0 JNV V 0 V 1 JV 1 V 0 JNVT VT 0 VT 1 clears VT JVT VT 1 clears VT VT 0 JNE Z 0 Z 1 JE Z 1 Z 0 Table A 4 PSW Flag Setting Symbols Symbol Description The instruction sets or clears the flag as appropriate The instruction does not modify the flag 2 instruction may clear the flag if it is appropriate but cannot set it T The instruction may set the flag if itis appropriate but cannot clear it 1 The instruction sets the flag 0 The instruction clears the flag The instruction leaves the flag in an indeterminate state 8XC196NP 80C196NU USER S MANUAL intel Table A 5 defines the variables that are used in Table A 6 to represent the instruction operands Table A 5 Operand Variables Variable Description aa A 2 bit field within an opcode that selects the basic addressing mode used This field is present only in those opcodes that allow addressing mode options The field is encoded as follows 00 register direct 01 immediate
88. During 8 bit bus cycles WRH is asserted for all write operations WRH is multiplexed with BHE t The chip configuration register 0 CCRO determines whether this pin functions as BHE or WRH CCRO 2 1 selects BHE CCRO 2 0 selects WRH WRL Write Lowt During 16 bit bus cycles this active low output signal is asserted for low byte writes and word writes During 8 bit bus cycles WRL is asserted for all write operations WRL is multiplexed with WR t The chip configuration register 0 CCRO determines whether this pin functions as WR WRL CCRO 2 1 selects WR CCRO 2 0 selects WRL4 XTAL1 Input Crystal Resonator or External Clock Input Input to the on chip oscillator internal phase locked loop circuitry 80C196NU and the internal clock generators The internal clock generators provide the peripheral clocks CPU clock and CLKOUT signal When using an external clock source instead of the on chip oscillator connect the clock input to XTAL1 The external clock signal must meet the V specification for XTAL1 see datasheet XTAL2 Inverted Output for the Crystal Resonator Output of the on chip oscillator inverter Leave XTAL2 floating when the design uses a external clock source instead of the on chip oscillator intel B 3 DEFAULT CONDITIONS SIGNAL DESCRIPTIONS Table B 5 lists the default functions of the I O and control pins of the 8XC196NP and 80C196NU with their values during various o
89. EP MODE selecting address mode en ables the logic gate preceding Q1 The value of DATA determines which transistor is turned on If DATA is equal to one Q1 is turned on and the pin is pulled high If DATA is equal to zero Q2 is turned on and the pin is pulled low 7 3 1 4 Open drain Output Mode For open drain output mode the gate that controls Q1 must be disabled Setting EP DIR select ing open drain mode and clearing EP MODE selecting I O mode disables the logic gate pre ceding Q1 The value of DATA determines whether Q2 is turned on If DATA is equal to one both QI and Q2 remain off and the pin is left in high impedance state floating If DATA is equal to zero Q2 is turned on and the pin is pulled low 7 14 intel PORTS Internal Bus RESET Vcc Address Bit from Address MUX POWERDOWN IDLE HOLD 1500 to 2002 R1 Read Port PH1 Clock Medium Pullup Q3 A0241 02 Figure 7 3 EPORT Structure 7 15 intel 8XC196NP 80C196NU USER S MANUAL 7 3 1 5 Input Mode Input mode is obtained by configuring the pin as an open drain output EP DIR set and MODE clear and writing a one to EP REG x In this configuration Q1 and Q2 are both off allowing an external device to drive the pin To determine the value of the I O pin read EP PIN x Table 7 11 is a logic table for I O operation and Table 7 12 is a logic table for address mode op eration of EPORT Table 7
90. FFH in this register causes the PWM to have its maximum duty cycle 99 6 duty cycle 7 0 PWM Duty Cycle Bit Number 7 0 PWM Duty Cycle This register controls the PWM duty cycle A zero loaded into this register causes the PWM to output a low continuously 0 duty cycle An FFH in this register causes the PWM to have its maximum duty cycle 99 6 duty cycle Function Table C 15 PWMx_CONTROL Addresses and Reset Values Register Address Reset Value PWMO CONTROL 1FBOH 00H PWM1 CONTROL 1FB2H 00H PWM2 CONTROL 1FB4H 00H C 38 intel REGISTERS SBUF RX SBUF RX Address 1FB8H m Reset State 00H The serial port receive buffer SBUF register contains data received from the serial port The serial port receiver is buffered and can begin receiving a second data byte before the first byte is read Data is held in the receive shift register until the last data bit is received then the data byte is loaded into If data in the shift register is loaded into before the previous byte is read the overflow error bit is set SP STATUS 2 The data in SBUF_RX will always be the last byte received never a combination of the last two bytes 7 0 Data Received Bit Number Function 7 0 Data Received This register contains the last byte of data received from the serial port 39 8XC196NP 80C196NU USER S
91. INT 0 Set PTSSEL 7 and PTSSEL 8 Enable the interrupts and the PTS The EI instruction enables interrupts the EPTS instruction enables the PTS 6 33 8 196 80C196NU USER S MANUAL intel PTS PWM Remap Mode Control Block In PWM remap mode the PTS uses two EPA channels to generate a pulse width modulated PWM output signal The control block contains registers that contain the PWM on time PTSCONSTI1 the address pointer PTSPTR1 and a control register PTSCON 7 0 Unused 0 0 0 0 0 0 0 0 7 0 Unused 0 0 0 0 0 0 0 0 15 8 PTSCONSTI HI PWM Const 1 Value high byte 7 0 PTSCONST1 LO PWM Const 1 Value low byte 15 8 PTSPTR1 Pointer 1 Value high byte 7 0 PTSPTR1 LO Pointer 1 Value low byte 7 0 PTSCON M2 M1 MO TMOD TBIT 7 0 Unused 0 0 0 0 0 0 0 0 Register Location Function PTSCONST1 PTSCB 4 PWM Const 1 Value Write the desired PWM on time to these bits PTSPTR1 PTSCB 2 Pointer 1 Value These bits point to a memory location usually EPAx TIME PTSPTR1 can point to any unreserved memory location within page 00H Figure 6 17 PTS Control Block PWM Remap Mode 6 34 intel STANDARD AND PTS INTERRUPTS PTS PWM Remap Mode Control Block Continued Register Location Function PTSCON PTSCB 1 PTS Control Bits M2 0 PTS Mode T
92. MHz 80 ns 160 ns 12 5 MHz 10 2 25 MHz 40 ns 80 ns 11 4 50 MHz 20 ns 40 ns Assumes an external clock The maximum frequency for an external crystal oscillator is 25 MHz lt gt XTAL1 T OO O O 12 5 MHz NE EE f PLLEN2 1 00 t 80ns CLKOUT cee ue 3b 3 PLLEN2 1 10 a t 40ns gt CLKOUT po _ G NENNEN 7 a ey PLLEN2 1 11 gt t 20ns CLKOUT 160 01 Figure 2 6 Effect of Clock Mode on CLKOUT Frequency intel ARCHITECTURAL OVERVIEW 2 5 INTERNAL PERIPHERALS The internal peripheral modules provide special functions for a variety of applications This sec tion provides a brief description of the peripherals subsequent chapters describe them in detail 2 5 4 W O Ports 8XC196NP and 80C196NU have five I O ports ports 1 4 and the EPORT Individual port pins are multiplexed to serve as standard I O or to carry special function signals associated with an on chip peripheral or an off chip component If a particular special function signal is not used in an application the associated pin can be individually configured to serve as a standard I O pin Port 4 has a higher drive capability than the other ports to support pulse width modulator PWM high drive outputs Ports 1 4 are eight bit bidirectional standard I O ports Only the lower nibble of port 4 is imple mented
93. Mode Mode 0 8 4 8 3 2 Asynchronous Modes Modes 1 2 3 8 5 8 33 2 1 Mod 1 see urere bet SRNR el it eae ides 8 6 8 3 2 2 MOdG2 unb iUe i td 8 7 8 3 2 39 Mode 3 ieu eret deren a AAE AE chest hing HERES 8 7 8 3 24 Mode 2 TIMINGS 8 7 8 3 2 5 Multiprocessor COMMUNICATIONS 8 8 8 4 PROGRAMMING THE SERIAL 8 8 8 4 1 Configuring the Serial Port Pins UL LIN LA TD 8 4 2 Programming the Control Register 8 6 8 4 3 Programming the Baud Rate and Clock Sores nO sette 8 4 4 Enabling the Serial Port Interrupts 8 13 8 4 5 Determining Serial Port Status sese 19 CHAPTER 9 PULSE WIDTH MODULATOR 9 1 PWM FUNCTIONAL 9 1 9 2 PWM SIGNALS AND REGISTERS eee eee enne 9 2 9 3 PWM OPERATION ore terea tere E Mee eia 9 3 9 4 PROGRAMMING THE FREQUENCY AND 9 5 9 5 PROGRAMMING THE DUTY OCYQCLE seem 9 7 9 5 1 Sample Calculations 2 nennen enn 9 9 9 5 2 Enabling the PWM emm emen nennen 9 9 9 5 3 Generating Analog Outputs sse eem mener 9 9 CHAPTER 10 EVENT PROCESSOR ARRAY EP
94. PTS cycles The PTSCB in Table 6 6 sets up three PTS cycles that will transfer five bytes from memory loca tions 20 24H to 6000 600 cycle 1 6005 6009 cycle 2 and 600 600 cycle 3 The source and destination are incremented after each byte transfer but the original source address is reloaded into PTSSRC at the end of each block transfer cycle In this routine the PTS always gets the first byte from location 20H Table 6 6 Block Transfer Mode PTSCB Unused PTSBLOCK 05H PTSDST HI 60H PTSDST LO 00H PTSSRC HI 00H PTSSRC LO 20H PTSCON 17H Mode 000 DI SI DU BW 1 SU 0 PTSCOUNT 03H 6 23 8XC196NP 80C196NU USER S MANUAL intel PTS Block Transfer Mode Control Block In block transfer mode the PTS control block contains a block size PTSBLOCK a source and destination address PTSSRC and PTSDST a control register PTSCON and a transfer count PTSCOUNT 7 0 Unused 0 0 0 0 0 0 0 0 7 0 PTSBLOCK PTS Block Size 15 8 PTSDST HI PTS Destination Address high byte 7 0 PTSDST LO PTS Destination Address low byte 15 8 PTSSRC HI PTS Source Address high byte 7 0 PTSSRC LO PTS Source Address low byte 7 0 PTSCON M2 M1 MO BW SU DU SI DI 7 0 PTSCOUNT Consecutive Block Transfers Register Location Function PTSBLOCK PTSCB 6
95. PUSH Indirect CB PUSH Indexed CD BMOVI CE POP Indirect POP Indexed DO JNST D1 JNH D2 JGT D3 JNC D4 JNVT D5 JNV D4 JNVT D5 JNV D6 JGE D7 JNE D8 JST D9 JH DA JLE DB JC DC JVT DD JV DE JLT DF JE EO DJNZ E1 DJNZW E2 TIJMP BR Indirect 64 Kbyte mode EBR Indirect 1 Mbyte mode E4 EBMOVI E5 Reserved A 51 8XC196NP 80C196NU USER S MANUAL intel Table A 7 Instruction Opcodes Continued Hex Code Instruction Mnemonic E6 EJMP E7 LJMP E8 ELD Indirect E9 ELD Indexed EA ELDB Indirect EB ELDB Indexed EC DPTS ED EPTS EE Reserved Note 1 EF LCALL FO RET 1 ECALL F2 PUSHF F3 POPF F4 PUSHA F5 POPA F6 IDLPD F7 TRAP F8 CLRC F9 SETC FA DI FB EI FC CLRVT FD NOP FE DIV DIVB MUL MULB Note 2 FF RST NOTES 1 This opcode is reserved but it does not generate an unimplemented opcode interrupt 2 Signed multiplication and division are two byte instructions For each signed instruction the first byte is FE and the second is the opcode of the corresponding unsigned instruction For example the opcode for MULU 3 operands direct is 4C so the opcode for MUL 3 oper ands direct is FE 4C Table A 8 lists instructions along with their lengths and opcodes for each applicable addressing mode A dash in any column indicates not applicable A 52 intel INSTRUCTI
96. RD is asserted only during external memory reads READY Ready Input This active high input signal is used to lengthen external memory cycles for slow memory by generating wait states in addition to the wait states that are generated internally When READY is high CPU operation continues in a normal manner with wait states inserted as programmed in CCRO or the chip select x bus control register READY is ignored for all internal memory accesses RES Reset A level sensitive reset input to and open drain system reset output from the microcontroller Either a falling edge on RESET or an internal reset turns on a pull down transistor connected to the RESET pin for 16 state times In the powerdown standby and idle modes asserting RESET causes the chip to reset and return to normal operating mode After a device reset the first instruction fetch is from FF2080H or F2080H in external memory For the 80C196NP and 80C196NU the program and special purpose memory locations FF2000 FF2FFFH reside in external memory For the 83C196NP these locations can reside either in external memory or in internal ROM SIGNAL DESCRIPTIONS Table B 3 Signal Descriptions Continued Name Type Description RPD Return from Powerdown Timing pin for the return from powerdown circuit If your application uses powerdown mode connect a capacitor between RPD Vss if eith
97. SIO port you must configure the port pins to serve as special function signals and set up the SIO channel 8 4 1 Configuring the Serial Port Pins Before you can use the serial port you must configure the associated port pins to serve as special function signals Table 8 1 on page 8 2 lists the pins associated with the serial port Table 8 2 lists the port configuration registers and Chapter 7 I O Ports explains how to configure the pins 8 4 2 Programming the Control Register The SP CON register Figure 8 6 selects the communication mode and enables or disables the receiver parity checking and nine bit data transmissions Selecting a new mode resets the serial I O port and aborts any transmission or reception in progress on the channel 8 4 8 Programming the Baud Rate and Clock Source The SP BAUD register Figure 8 7 on page 8 11 selects the clock input for the baud rate gen erator and defines the baud rate for all serial modes This register acts as a control register during write operations and as a down counter monitor during read operations WARNING Writing to the SP BAUD register during a reception or transmission can corrupt the received or transmitted data Before writing to SP BAUD check the SP STATUS register to ensure that the reception or transmission is complete 8 8 intel SERIAL 1 0 SIO PORT SP CON Address 1FBBH B Reset State 00H The serial port control SP CON register selects the com
98. See Table 6 4 on page 6 10 for PTS cycle execution times 6 7 8XC196NP 80C196NU USER S MANUAL intel 6 4 2 Calculating Latency The maximum latency occurs when the interrupt request occurs too late for acknowledgment fol lowing the current instruction The following worst case calculation assumes that the current in struction is not a protected instruction To calculate latency add the following terms Time for the current instruction to finish execution 4 state times If this is a protected instruction the instruction that follows it must also execute before the interrupt can be acknowledged Add the execution time of the instruction that follows a protected instruction Time for the next instruction to execute The longest instruction NORML takes 39 state times However the BMOV instruction could actually take longer if it is transferring a large block of data If your code contains routines that transfer large blocks of data you may get a more accurate worst case value if you use the BMOV instruction in your calculation instead of NORML See Appendix A for instruction execution times For standard interrupts only the response time to get the vector and force the call in 64 Kbyte mode 11 state times for an internal stack or 13 for an external stack assuming a zero wait state bus in 1 Mbyte mode 15 state times for an internal stack or 18 for an external stack assuming a zero wait state bus 6 4
99. Ser dei pe 6 18 PTS Service PTSSRV 6 19 PTS Mode Selection Bits PTSCON Bits 7 5 sse 6 20 PTS Control Block Single Transfer Mode sese 6 21 PTS Control Block Block Transfer 6 24 A Generic PWM Waveform esses eene 6 27 PTS Control Block PWM Toggle 6 29 EPA and PTS Operations for the PWM Toggle Mode 6 31 PTS Control Block PWM Remap Mode ae uibeluienibeig 9 94 EPA and PTS Operations for the PWM Remap Mode Example 6 36 Bidirectional Port LOO EPORT Block Diagram e rei o Taaie 7 13 EPOR T Structure RR dre ee tet 7 15 SIO Block Diagram pnto tint eren Din rre 8 1 Typical Shift Register Circuit for 0 8 4 ro MEL IDEE 8 5 Serial Port Frames for Mode 1 8 6 xi 8XC196NP 80C196NU USER S MANUAL intel Figure 8 5 8 6 8 8 9 1 9 3 9 4 9 6 9 7 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 10 10 10 11 10 12 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 11 10 12 1 12 2 12 3 12 4 12 5 13 1 13 2 13 3 13 4 13 5 13 6 xii FIGURES Page
100. Serial Port Frames in Mode 2 ns 9 7 Serial Port Control SP CON 8 9 Serial Port Baud Rate SP BAUD 8 11 Serial Port Status SP STATUS Register sse 8 14 PWM Block Diagram 8XC196NP Only seen emm eem eem n 9 1 PWM Block Diagram 80C196NU mene 9 2 PWM Output 9 5 Control REGO Register 9 7 PWM Control PWMx CONTROL po e pe 9 8 D A Buffer Block Diagram EI PWM to Analog Conversion Circuitry uere E a e beer EU EE VERAT Sole 9 10 EPA Block DIagtatm ndm eed te reni reta o Lus Re d 10 2 EPA Timer Counters ni Une Den ar on tec deve Rug 10 5 Quadrature Mode Interface 10 7 Quadrature Mode Timing mmn 10 8 A Single EPA Capture Compare 10 9 EPA Simplified Input capture Structure sese eem 10 10 Valid EPA Input Events ieri RE E de 10 10 Timer 1 Control TICONTROL 10 16 Timer 2 Control T2CONTROL 10 17 EPA Control EPAx CON Registers esee em eee 10 19 EPA Interrupt Mask EPA MASK
101. Special purpose Memory Addresses 8XC196NP 80C196NU Address Address Description Hex Hex FF207F FF207F FF205E FF2060 Reserved each byte must contain FFH FF205D FF205F FF2040 FF2040 PTS vectors FF203F FF203F FF2030 FF2030 Upper interrupt vectors FF202F FF202F FF201B FF201B Reserved each byte must contain FFH FF201A FF201A CCB1 FF2019 FF2019 Reserved must contain 20H FF2018 FF2018 CCBO FF2017 FF2017 FF2014 FF2010 Reserved each byte must contain FFH FF2013 FF200F 4 FF2000 FF2000 Lower interrupt vectors 80C196NP and 80C196NU This partition is in external memory external addresses 2000 207 83C196NP REMAP bit CCB1 2 the EA input and the type of instruction extended or nonextended control access to this partition as shown in Table 5 4 Table 5 4 Special purpose Memory Access for the 83 196 a EA Pin ed Memory Location Accessed X Asserted Extended or nonextended External memory F2000 F207FH 0 Deasserted Extended or nonextended Internal ROM FF2000 FF207FH Extended Internal ROM FF2000 FF207FH 1 Deasserted Nonextended External memory 02000 0207FH 5 6 l ntel MEMORY PARTITIONS 5 2 2 3 Reserved Memory Locations Several memory locations are reserved for testing or for use in future products Do not read or write these locations except to initialize them to the values shown in
102. Table 5 3 The function or contents of these locations may change in future revisions software that uses reserved locations may not function properly 5 2 2 4 Interrupt and PTS Vectors The peripheral transaction server PTS vectors contain the addresses of the PTS control blocks upper and lower interrupt vectors contain the addresses of the interrupt service routines See Chapter 6 Standard and PTS Interrupts for more information 5 2 2 5 Chip Configuration Bytes The chip configuration bytes CCBO and 1 specify the operating environment They specify the bus width bus mode multiplexed or demultiplexed write control mode wait states power down enabling and the operating mode 1 Mbyte or 64 Kbyte mode For the 833C196NP CCB1 also controls ROM remapping For the 80C196NP and 80C196NU the CCBs are stored in exter nal memory locations F2018 F201 AH For the 83C196NP the CCBs can be stored either ex ternal memory locations F2018 F201AH or in the on chip ROM locations 2018 FF201AH The chip configuration bytes are the first bytes fetched from memory when the device leaves the reset state The post reset sequence loads the CCBs into the chip configuration registers CCRs Once they are loaded the CCRs cannot be changed until the next device reset Typically the CCBs are programmed once when the user program is compiled and are not redefined during nor mal operation Chip Configuration Register
103. Tavyv min gt r TLHLH 2t LLL MS TRLRH 2t Tripv 4 2t 4 Tavpv 4 2t Data gt 2 TovwH 4 2t Data Valid T0007 02 Figure 13 14 READY Timing Diagram Demultiplexed Mode 8XC196NP 13 29 8 196 80C196NU USER S MANUAL CLKOUT READY ALE RD AD15 0 read WR AD15 0 write BHE INST A19 16 CSx min 4 2t TR RH 2t Tavpv 2t Data Valid R 2 4 Tovwu 2t Data Valid T0014 02 Figure 13 15 READY Timing Diagram Demultiplexed Mode 80C196NU 13 7 BUS HOLD PROTOCOL The 8XC196Nx supports a bus hold protocol that allows external devices to gain control of the address data bus The protocol uses three signals all of which are port 2 special functions HOLD P2 5 bus hold request HLDA P2 6 bus hold acknowledge and BREQ P2 3 bus request When an external device wants to use the 8XC196Nx bus it asserts the HOLD signal HOLD is sampled while CLKOUT is low The 8XC196Nx responds by releasing the bus and asserting HLDA During this hold time the address data bus floats and signals CSx ALE RD WR WRL BHE WRH
104. The offset must be in the range of 8 388 607 to 8 388 608 for 24 bit addresses This instruction is an unconditional relative jump to anywhere in the 16 Mbyte address space It functions only in extended addressing mode PC PC 24 bit disp PSW Flag Settings Z N C V VT ST EJMP cadd 11100110 disp low disp high disp ext NOTE For 20 bit addresses the offset must be in the range of 524287 to 524288 8 196 80C196NU USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format ELD EXTENDED LOAD WORD Loads the value DEST SRC 0 k ii ext indirect 11101000 treg wreg This instruction allows you to move data from f anywhere in the 16 Mbyte address space into Xt indexed 11101001 treg disp low the lower register file disp high disp ext wreg ext indirect DEST SRC di NOTE For 20 bit addresses the offset t indexed DEST lt SRC 24 bit dis ior Hon d a must be in the range of 524287 PSW Flag Settings 195384298 Z N C V VTI ST ELDB EXTENDED LOAD BYTE Loads the value of DEST SRC byte operand into the destination ELDB breg treg duda ext indirect 11101010 treg breg This instruction allows you to move
105. The offset must be in the extended to 24 bits range of 128 to 127 if C 2 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JE JUMP IF EQUAL Tests the zero flag If the flag is clear control passes to the next JE cadd sequential instruction If the zero flag is set 4 this instruction adds to the program counter 11011111 disp the offset between the end of this instruction and the target label effecting the jump The NOTE The displacement disp is sign offset must be in the range of 128 to 127 extended to 24 bits if Z 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JGE JUMP IF SIGNED GREATER THAN OR EQUAL Tests the negative flag If the JGE cadd negative flag is set control passes to the next sequential instruction If the negative flag is 11010110 disp clear this instruction adds to the program counter the offset between the end of this NOTE The displacement disp is sign instruction and the target label effecting the extended to 24 bits jump The offset must be in the range of 128 to 127 if N 0 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST A 22 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format JGT JUMP IF SIGNED
106. The result has ones in only the bit positions in which both 010000aa waop Swreg Dwreg operands had a 1 and zeros in all other bit positions DEST lt SRC1 AND SRC2 Dwreg Swreg waop PSW Flag Settings Z N C V VT ST 0 LOGICAL AND BYTES ANDs the source DEST SRC 2 operands and destination byte operands and stores the ANDB breg result into the destination operand The result i has ones in only the bit positions in which 011100aa baop breg both operands had a 1 and zeros in all other bit positions DEST lt DEST AND SRC PSW Flag Settings Z N C V VT ST 0 0 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format ANDB 8 operands LOGICAL AND BYTES ANDs the two source byte operands and stores the result into the destination operand The result has ones in only the bit positions in which both operands had a 1 and zeros in all other bit positions DEST SRC1 AND SRC2 PSW Flag Settings Z N C V VT ST 10 0 DEST SRC1 SRC2 ANDB Sbreg baop 010100aa baop Sbreg Dbreg BMOV BLOCK MOVE Moves a block of word data from one location in memory to another The Source and de
107. To disable any interrupt clear its mask bit To enable an interrupt for standard interrupt service set its mask bit and clear its PTS select bit To enable an interrupt for PTS service set both the mask bit and the PTS select bit When you assign an interrupt to the PTS you must set up a PTS control block PTSCB for each interrupt source see Initializing the PTS Control Blocks on page 6 17 and use the EPTS in struction to globally enable the PTS When you assign an interrupt to a standard software service routine use the EI enable interrupts instruction to globally enable interrupt servicing NOTE The DI disable interrupts instruction does not disable PTS service However it does disable service for the end of PTS interrupt request If an interrupt request occurs while interrupts are disabled the corresponding pending bit is set in the INT PEND or INT PENDI register 6 10 intel STANDARD AND PTS INTERRUPTS PTSSEL Address 0004H Reset State 0000H The PTS select PTSSEL register selects either a PTS microcode routine or a standard interrupt Service routine for each interrupt request Setting a bit selects a PTS microcode routine clearing a bit Selects a standard interrupt service routine When PTSCOUNT reaches zero hardware clears the corresponding PTSSEL bit The PTSSEL bit must be set manually to re enable the PTS channel 15 EXTINT3 EXTINT2 OVR2 3 OVRO 1 EPA3 EPA2
108. a normal manner with wait states inserted as programmed in CCRO or the chip select X bus control register READY is ignored for all internal memory accesses 19 4 INTERFACING WITH EXTERNAL MEMORY Table 13 2 External Memory Interface Signals Continued Name Type Description Multiplexed With WR Writet This active low output indicates that an external write is occurring This signal is asserted only during external memory writes The chip configuration register 0 CCRO determines whether this pin functions as WR or WRL CCRO 2 1 selects WR CCRO 2 0 selects WRL WRL WRH Write High During 16 bit bus cycles this active low output signal is asserted for high byte writes and word writes to external memory During 8 bit bus cycles WRH is asserted for all write operations The chip configuration register 0 CCRO determines whether this pin functions as BHE or WRH CCRO 2 1 selects BHE CCRO 2 0 selects WRH 5 5 WRL Write Lowt During 16 bit bus cycles this active low output signal is asserted for low byte writes and word writes During 8 bit bus cycles WRL is asserted for all write operations The chip configuration register 0 CCRO determines whether this pin functions as WR or WRL CCRO 2 1 selects WR CCRO 2 0 selects WRL WR 13 3 THE CHIP SELECT UNIT The chip select unit provides six outputs CS5 0
109. address is FF2018H the 20 external address pins output F2018H Further the address seen by an external device depends on how many of the extended address lines are connected to the device See Internal and External Addresses on page 13 1 20 external address pins can address 1 Mbyte of external memory For purposes of discussion only it is convenient to view this 1 Mbyte address space as sixteen 64 Kbyte pages numbered 00H O0FH see Figure 5 1 on page 5 2 The lower 16 address lines enable the device to address page 00H The four extended address lines enable the device to address the remaining external address space pages 01 5 1 8XC196NP 80C196NU USER S MANUAL intel Because the four most significant bits MSBs of the internal address can take any values without changing the external address these four bits effectively produce 16 copies of the 1 Mbyte ad dress space for a total of 16 Mbytes in 256 pages 00H FFH Figure 5 1 For example page 01H has 15 duplicates 11H 21H The shaded areas in Figure 5 1 represent the overlaid areas 16 Mbyte 3 Mbyte 2 Mbyte 1 Mbyte Externally Addressable A2541 02 Figure 5 1 16 Mbyte Address Space The memory pages of interest are FFH Pages 01H OEH are external memory with unspecified contents they can store either code or data Pages 00H and FFH shown in Figure 5 2 have special significance Page 00H contains the regis
110. addressing depending on the value of the index expression If the value can be expressed in eight bits the assembly lan guage chooses a short indexed reference If the value is greater than eight bits it chooses a long indexed reference 4 3 8 Extended Addressing If the operand is outside page 00H then you must use the extended load and store instructions ELD ELDB EST and ESTB 4 4 DESIGN CONSIDERATIONS FOR 1 MBYTE DEVICES In general you should avoid creating tables or arrays that cross page boundaries For example if you are building a large array start it at a base address that will accommodate the entire array within the same page If you cannot avoid crossing a page boundary keep in mind that you must use extended instructions to access data outside the original page 4 5 SOFTWARE STANDARDS AND CONVENTIONS For a software project of any size it is a good idea to develop the program in modules and to es tablish standards that control communication between the modules These standards vary with the needs of the final application However all standards must include some mechanism for passing parameters to procedures and returning results from procedures We recommend that you use the conventions adopted by the C programming language for procedure linkage These standards are usable for both the assembly language and C programming environments and they offer compat ibility between these environments 4 11 8XC196NP 80C1
111. an unconditional indirect jump to anywhere in the address space It functions only in extended addressing modes ECALL Extended call This instruction is an unconditional relative call to anywhere in the address space It functions only in extended addressing modes EJMP Extended jump This instruction is an unconditional relative jump to anywhere in the address space It functions only in extended addressing modes ELD Extended load word Loads the value of the source word operand into the destination operand This instruction allows you to move data from anywhere in the address space into the lower register file It operates in extended indirect and extended indexed modes ELDB Extended load byte Loads the value of the source byte operand into the destination operand This instruction allows you to move data from anywhere in the address space into the lower register file It operates in extended indirect and extended indexed modes 4 5 8XC196NP 80C196NU USER S MANUAL intel EST Extended store word Stores the value of the source leftmost word operand into the destination rightmost operand This instruction allows you to move data from the lower register file to anywhere in the address space It operates in extended indirect and extended indexed modes ESTB Extended store byte Stores the value of the source leftmost byte operand into the destination rightmost operand This instruction allows you to move data from the lower r
112. and Timer Counter Port Pins Before you can use the EPA you must configure the pins of port 1 to serve as the special function signals for the EPA and optionally for the timer counter clock source and direction control sig nals See Bidirectional Ports 1 4 on page 7 1 for information about configuring the port pins NOTE If you use T2CLK as the timer 2 input clock you cannot use EPA capture compare channel 0 If you use T2DIR as the timer 2 direction control source you cannot use EPA capture compare channel 1 Table 10 1 on page 10 2 lists the pins associated with the EPA and the timer counters Pins that are not being used for an EPA channel or timer counter can be configured as standard I O 10 5 2 Programming the Timers The control registers for the timers are TICONTROL Figure 10 8 and T2CONTROL Figure 10 9 Write to these registers to configure the timers Write to the TIMERI and TIMER2 regis ters see Table 10 2 on page 10 3 for addresses to load a specific timer value 10 15 8XC196NP 80C196NU USER S MANUAL intel T1CONTROL Address 1F90H Reset State 00H The timer 1 control T1 CONTROL register determines the clock source counting direction and count rate for timer 1 7 0 CE UD M2 M1 MO P2 P1 PO Bit Bit Function Number Mnemonic 7 CE Counter Enable This bit enables or disables the timer From reset the timers are disabled and not free running 0 disab
113. and set the MODE x bit Clearing REG x is required for compatibility with software development tools 7 3 2 2 Configuring EPORT Pins for I O To configure a pin for I O write the appropriate values to the control registers in this order 1 EP DIR 2 EP MODE 3 EP REG Table 7 13 lists the register settings for the EPORT pins Table 7 13 Configuration Register Settings for EPORT Pins Configuration Register Settings EP PIN Desired Pin Configuration Value EP DIR EP MODE EP REG Address xi 1 ott address Complementary output 0 0 data value data value Open drain output 1 0 data value data value Input 1 0 1 I O pin value X Don t care tt Must be zero for compatibility with software tools 8XC196NP 80C196NU USER S MANUAL intel 7 33 EPORT Considerations This section outlines considerations for using the EPORT pins 7 3 3 1 EPORT Status During Reset CCB Fetch Idle Powerdown and Hold During reset the EPORT pins are forced to their extended address functions and are weakly pulled high During the CCB fetch FFH is strongly driven onto the pins This value remains strongly driven until either the pin is configured for I O or a different extended address is access ed If the pins remain configured as extended address functions they are placed in a high imped ance state during idle powerdown standby 80C196NU only and hold If they are configured as I O they retain the
114. as a special function input see Bidirec tional Port Pin Configurations on page 7 7 If the EXTINTx interrupt is enabled the CPU executes the interrupt service routine Otherwise the CPU executes the instruction that immediately follows the command that invoked the power saving mode In idle mode asserting any enabled interrupt causes the device to resume normal operation NMI Nonmaskable Interrupt In normal operating mode a rising edge on NMI generates a nonmaskable interrupt NMI has the highest priority of all prioritized interrupts Assert NMI for greater than one state time to guarantee that it is recognized Table 6 2 Interrupt and PTS Control and Status Registers Mnemonic Address Description EPA MASK 1 1FA1H EPA Interrupt Mask Register This register enables disables the four capture overrun interrupts OVRO 3 EPA PEND 1FA2H 1FA3H EPA Interrupt Pending Register The bits in this register are set by hardware to indicate that a capture overrun has occurred INT MASK INT MASK1 0008H Interrupt Mask Registers 0013H These registers enable disable each maskable interrupt that is each interrupt except unimplemented opcode software trap and NMI 8XC196NP 80C196NU USER S MANUAL intel Table 6 2 Interrupt and PTS Control and Status Registers Continued Mnemonic Address Description INT PEND 0009H Interrupt Pending Registers INT PE
115. bit BIT byte BYTE CCBs CCRs The addressing mode that allows code to reside anywhere in the 1 Mbyte addressing space The addressing mode that allows code to reside only in page FFH A register or storage location that forms the result of an arithmetic or logical operation The 80C196NU has enhanced multiplication instruc tions that use a new 32 bit accumulator for multiply accumulate operations Arithmetic logic unit The part of the RALU that processes arithmetic and logical operations The act of making a signal active enabled The polarity high or low is defined by the signal name Active low signals are designated by a pound symbol f suffix active high signals have no suffix To assert RD is to drive it low to assert ALE is to drive it high A binary digit A single bit operand that can take on the Boolean values true and false Any 8 bit unit of data An unsigned 8 bit variable with values from 0 through 25 1 Chip configuration bytes The chip configuration registers CCRs are loaded with the contents of the CCBs after a device reset Chip configuration registers Registers that define the environment in which the device will be operating The chip configuration registers are loaded with the contents of the CCBs after a device reset Glossary 1 8XC196NP 80C196NU USER S MANUAL intel chip select unit clear deassert demultiplexed bus doping double word DOUBL
116. can be used to drive motors that require an unfiltered PWM waveform for optimal efficiency or they can be filtered to produce a smooth analog signal This chapter provides a functional overview of the pulse width modulator module describes how to program it and provides sample circuitry for converting the PWM outputs to analog signals For detailed descriptions of the signals and registers discussed in this chapter please refer to Ap pendix B Signal Descriptions and Appendix C Registers 91 PWM FUNCTIONAL OVERVIEW The PWM module has three channels each of which consists of a control register PWMx CONTROL where x is 0 1 or 2 a buffer a comparator an RS flip flop and an output pin Two other components an eight bit counter and a clock prescaler are shared across the PWM module s three channels completing the circuitry see Figures 9 1 and 9 2 Load Buffer Bufferx 8 CON 0 0 CLKO Bit pm Hp RS Flip flopx a Port 4 Control Up Counter I Overflow Shared Circuitry Internal Clock Signal A2382 03 Figure 9 1 PWM Block Diagram 8XC196NP Only 9 1 8XC196NP 80C196NU USER S MANUAL intel Load Buffer CON REGO 0 CLKO Bit CON_REGO 1 CLK1 Bit RS Flip flopx Port 4 Prescaler q Control Internal Ge 00 P4 MODE n bi PWMx P4 x Clock Signal Output PWMx 10 Shared Circuitry A3158 01 Fig
117. clears the Temp lt COUNT sticky bit flag at the beginning do while Temp 0 of the instruction If at any time C Low order bit of DEST during the shift a 1 is shifted DEST lt DEST 2 into the carry flag and another Temp Temp 1 shift cycle occurs the instruc end while tion sets the sticky bit flag PSW Flag Settings In this operation DEST 2 rep 7 N resents unsigned division 0 0 SJMP SHORT JUMP Adds to the program counter the offset between the end of this instruction s up cadd and the target label effecting the jump The offset must be in the range of 1024 to 00100xxx disp low 1023 inclusive PC lt PC 11 bit disp NOTE The displacement disp is sign extended to 16 bits in the 64 PSW Flag Settings Kbyte addressing mode and to 24 bits in the 1 Mbyte addressing 2 VoL VE GST mode This displacement may cause the program counter to cross a page boundary in 1 Mbyte mode SKIP TWO BYTE NO OPERATION Does nothing Control passes to the next sequential SKIP breg instruction This is actually a two byte NOP in which the second byte can be any value and is simply ignored PSW Flag Settings Z N C V VT ST 00000000 breg A 41 8XC196NP 80C196NU USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format ST STORE WORD Stores the value of the SR
118. configures the pins but also turns off the transistor that weakly holds the pins high Q4 in Figure 7 1 on page 7 5 For this reason even if port 2 is to be used as it is configured at reset you should still write data into 2 MODE Writing to P2 MODE sets the EXTINTO interrupt pending bit INT PEND 3 After configuring the port pins clear the interrupt pending registers before globally enabling interrupts See Design Considerations for External Interrupt Inputs on page 7 11 Writing to P2 MODE sets EXTINTI interrupt pending bit INT PEND 4 After configuring the port pins clear the interrupt pending registers before globally enabling interrupts See Design Considerations for External Interrupt Inputs on page 7 11 If P2 5 is configured as a standard I O port pin the device does not recognize signals on this pin as HOLD Instead the bus controller receives an internal HOLD signal This enables the device to access the external bus while it is performing I O at P2 5 7 9 8XC196NP 80C196NU USER S MANUAL intel P2 7 CLKOUT P2 7 Port 3 P3 0 CSO P3 6 EXTINT2 P3 7 EXTINT3 Port 4 7 10 Following reset P2 7 carries the strongly driven CLKOUT signal It is not held high When P2 7 is configured as CLKOUT it is always a complementary output A value written to P2 REG 7 is held in a buffer until P2 MODE 7 is cleared at which time the value is loaded into P2_REG 7 A value read from P2 7 is the
119. contents 7 0 80C196NU FME SME STOVF OVE STSAT Bit Bit Function Number Mnemonic unen 7 FME Fractional Mode Enable Set this bit to enable fractional mode See Table 3 2 In this mode the result of a signed multiplication instruction is shifted left by one bit before it is added to the contents of the accumulator For unsigned multiplication this bit is ignored 6 SME Saturation Mode Enable Set this bit to enable saturation mode See Table 3 2 In this mode the result of a signed multiplication operation is not allowed to overflow or underflow For unsigned multiplication this bit is ignored 5 3 Reserved for compatibility with future devices write zeros to these bits STOVF Sticky Overflow Flag For unsigned multiplication this bit is set if a carry out of bit 31 occurs Unless saturation mode is enabled this bit is set for signed multiplication to indicate that the sign bit of the accumulator and the sign bit of the addend are equal but the sign bit of the result is the opposite See Table 3 2 Software can clear this flag hardware does not clear it 1 OVF Overflow Flag This bit indicates that an overflow occurred during the preceding accumu lation See Table 3 2 This flag is dynamic it can change after each accumulation 0 STSAT Sticky Saturation Flag This bit indicates that a saturation has occurred during accumulation with saturation mo
120. data from anywhere the 16 Mbyte address space into Xt indexed 11101011 treg disp low the lower register file disp high disp ext breg ext indirect DEST SRC t indexed DEST lt SRC 24 bit dis NOTE For 20 bit addresses the offset jest must be the range of 524287 PSW Flag Settings 107924288 2 VTI ST EPTS ENABLE PERIPHERAL TRANSACTION SERVER PTS Enables the peripheral EPTS t i PTS ransaction server PTS 11101101 PTS Enable PSW 2 lt 1 PSW Flag Settings Z N C V VTI ST intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format EST EXTENDED STORE WORD Stores the SRC DEST value of the source leftmost word operand EST wreg treg into the destination rightmost operand EN ext indirect 00011100 treg wreg This instruction allows you to move data from 3 the lower register file to anywhere in the 16 ext indexed 00011101 treg disp low Mbyte address space disp high disp ext wreg ext indirect DEST SRC NOTE For 20 bit addresses the offset DEST lt SRC 24 bit d Hon id a must be in the range of 524287 PSW Flag Settings 10 920208 2 V VI ST ESTB EXTENDED STORE BYTE Stores the value SRC DEST of the source leftmost byte op
121. datasheets are available first from the BBS To access the files complete these steps 1 TypeF from the BBS Main menu The BBS displays the Intel Apps Files menu 2 L and press Enter The BBS displays the list of areas and prompts for the area number 3 Type 25 and press Enter to select ApBUILDER Hypertext The BBS displays several options one for ApBUILDER software and the others for hypertext documents for specific product families 4 1 and press Enter to list the latest ApBUILDER files or type 2 and press Enter to list the hypertext manuals and datasheets for MCS 96 microcontrollers 5 the file numbers to select the files you wish to download for example 1 6 for files 1 and 6 or 3 7 for files 3 4 5 6 and 7 and press Enter The BBS displays the approx imate time required to download the selected files and gives you the option to download them 1 43 CompuServe Forums The CompuServe forums provide a means for you to gather information share discoveries and debate issues Type intel for access For information about CompuServe access and service fees call CompuServe at 1 800 848 8199 U S or 614 529 1340 outside the U S 1 10 intel GUIDE TO THIS MANUAL 1 4 4 World Wide Web We offer a variety of information through the World Wide Web URL http www intel com Se lect Embedded Design Products from the Intel home page 1 5 TECHNICAL SUPPORT
122. external device The event processor array EPA was designed to reduce the CPU overhead associated with these types of event control This chapter describes the EPA and its timers and explains how to configure and program them 10 1 EPA FUNCTIONAL OVERVIEW The EPA performs input and output functions associated with two timer counters timer 1 and timer 2 Figure 10 1 In the input mode the EPA monitors an input pin for an event a rising edge a falling edge or an edge in either direction When the event occurs the EPA records the value of the timer counter so that the event is tagged with a time This is called an input capture Input captures are buffered to allow two captures before an overrun occurs In the output mode the EPA monitors a timer counter and compares its value with a value stored in a register When the tim er counter value matches the stored value the EPA can trigger an event a timer reset or an output event set a pin clear a pin toggle a pin or take no action This is called an output compare Each input capture or an output compare sets an interrupt pending bit This bit can optionally cause an interrupt The EPA has four capture compare channels 0 10 1 8XC196NP 80C196NU USER S MANUAL intel Timer Counter Unit TIMER1 TIMER2 Capture Compare Channel 0 m U gt g Interrupt Capture Compare Channel 1 EPA1 Interrupt m U x g Capture Compare Channe
123. file or the upper register file accesses the actual location in memory The following sample code illustrates the difference between direct and indexed addressing when using windowing PUSHA Pushes the contents of WSR onto the stack LDB WSR 17H Selects window 17H a 128 byte block windows 0380 03FFH into 0080 00FFH The next instruction uses direct addr ADD 40H 80H mem word 40H mem word 40H mem word 380H The next two instructions use indirect addr ADD 40H 80H 0 mem word 40H mem word 40H mem word 80H 0 ADD 40H 380H 0 mem word 40H mem word 40H mem word 380H 0 POPA reloads the previous contents into WSR 5 21 8XC196NP 80C196NU USER S MANUAL intel 5 4 REMAPPING INTERNAL ROM 83C196NP ONLY The 83C196NP s 4 Kbytes of ROM are located in 2000 2 By using the REMAP bit 1 2 and the EA input you can also access these locations in external memory page OFH or page The REMAP bit is loaded from upon leaving reset and cannot be changed until the next reset Tie low to access external memory or tie it high to access the on chip ROM Refer to the EA description in Appendix B for additional information on using the EA pin NOTE The EA input is effective only for accesses to the 33C196NP s on chip ROM FF2000 FF2FFFH For an access to any other location the value of EA is irrelevant Without remapping CCB1 2 0 an access to FF2000 FF2
124. following formula to calculate a de sired pulsewidth by extrapolating an appropriate value for PVUMx CONTROL from the range 00 and then write the value to the PVMx CONTROL register 8 196 80C196NU USER S MANUAL Pulsewidth in us Duty Cycle in 96 where PWMx CON Pulsewidth f Tpwm 80C196NU only Clock Prescaler 2 Clock Prescaler Disabled Enabled PWMx CONx2 PWMx CON x4 f f Pulsewidth X 300 Town 8 bit value to load into the PWMx_CONTROL register width of each high pulse operating frequency in MHz output period on the PWM pin in us intel 4 Clock Prescaler Enabled PWMx CONx8 f PWMx CONTROL x 0 2 Address Table 9 2 Reset State 00H PWM control PNMx CONTROL register determines the duty cycle of the PWM x channel zero loaded into this register causes the PWM to output a low continuously 096 duty cycle An FFH in this register causes the PWM to have its maximum duty cycle 99 6 duty cycle 7 0 PWM Duty Cycle Bit Number Function 7 0 PWM Duty Cycle This register controls the PWM duty cycle A zero loaded into this register causes the PWM to output a low continuously 096 duty cycle An FFH in this register causes the PWM to have its maximum duty cycle 99 6 duty cycle Figure 9 5 PWM Control PWMx CONTROL Register intel PULSE WIDTH MODULATOR 9 5 1 Sample Calculations For example assume that the operating f
125. future devices write zeros to these bits 6 4 2 0 OVR3 Setting this bit enables the corresponding source as shared overrun OVR2 interrupt source The shared overrun interrupts OVRO 1 and OVR2 3 OVR1 are enabled by setting their interrupt enable bits in the interrupt mask 1 OVRO INT MASK1 register intel REGISTERS EPA PEND EPA PEND Address 1F9EH Reset State AAH OVR2 3 in the INT PEND 1 register 7 When hardware detects a pending EPA3 0 overrun interrupt OVR3 0 it sets the corresponding bit in the EPA interrupt pending EPA PEND register OVRO and OVR1 are multiplexed to share one bit OVRO 1 the INT PEND1 register Similarly OVR2 and OVR3 are multiplexed to share another bit OVR3 OVR2 OVR1 OVRO Bit Number Function 7 5 3 1 Reserved These bits are undefined 6 4 2 0 Any set bit indicates that the corresponding overrun interrupt source is pending NOTE This register was called STAT in previous documentation for the 83XC196NP 8 196 80C196NU USER S MANUAL intel EPAx CON EPAx CON Address Table C 8 xz0 3 Reset State The EPA control EPAx CON registers control the functions of their assigned capture compare channels The registers for EPAO andEPA2 are identical The registers for EPA1 and have an additional bit the remap bit This added bit bit 8 requires an additional byte so
126. generates a positive sign bit Saturation mode prevents an underflow or overflow of the accumulated value The 1 value of a bit or the act of giving it a 1 value See also clear Special function register An 8 bit signed variable with values from 29 through 42 1 A method for converting data to a larger format by filling the upper bit positions with the value of the sign This conversion preserves the positive or negative value of signed integers Current flowing into a device to ground Always a positive value Current flowing out of a device from Voc Always negative value Stack pointer Any of the three nonmaskable interrupts unimple mented opcode software trap or NMI Glossary 7 8XC196NP 80C196NU USER S MANUAL intel special purpose memory standard interrupt state time or state UART WDT word WORD zero extension Glossary 8 A partition of memory used for storing the interrupt vectors PTS vectors chip configuration bytes and several reserved locations Any maskable interrupt that is assigned to the interrupt controller for processing by an interrupt service routine The basic time unit of the device the combined period of the two internal timing signals PH1 and PH2 The internal clock generator produces PH1 and PH2 by halving the frequency of the signal on XTALI The rising edges of the active high PH1 and PH2 signals generate CLKOUT the output of the interna
127. gles the output to one and generates an interrupt to initiate the second PTS cycle PWM Toggle Cycle 2 Because TBIT is zero the PTS adds the on time value T1 to EPAO TIME and toggles the TBIT to one The next timer match occurs at time T2 T1 The EPA toggles the output to zero and initiates the third PTS cycle The PTS actions are the same as in cycle 1 and generation of the PWM output continues with PTS cycle 1 and cycle 2 alternating 6 30 intel STANDARD AND PTS INTERRUPTS Toggle Output PTS Cycle EPAO TIME EPAO TIME T1 EPAO TIME EPAO TIME T2 T1 Toggle TBIT A2552 02 Figure 6 16 EPA and PTS Operations for the PWM Toggle Mode Example You can modify the duty cycle without interrupting the PWM operation To change the duty cycle during a PWM cycle the PTS service routine should write new T1 and T2 1 values to 5 and CSTORE2 and select normal interrupt service for the next EPAO interrupt When the next timer match occurs the output is toggled and the device executes a normal interrupt ser vice routine which performs these operations 1 The routine writes the new value of T1 in CSTOREI to and the new value of T1 T2 in CSTORE2 to PISCONST2 2 It selects PTS service for the EPAO interrupt 6 31 8XC196NP 80C196NU USER S MANUAL intel When the next timer match occurs the PTS cycle Figure 6 16 increments EPAO TIME by if T
128. gt Address Out Data tn TCHWH I TWHLH TLLWL 4 I TwHax Se TavwH AddressOut JK Data Out TRHBX Address Out 1 TwHax TwHsH TRHSH abiss asie SSS C 0011 02 13 38 Figure 13 21 Multiplexed System Bus Timing 80C196NU INTERFACING WITH EXTERNAL MEMORY CLKOUT ALE RD AD15 0 read WR AD15 0 write BHE INST A19 0 CSx TRHAX TWHAX Address Out Address TCHCL A2368 05 Figure 13 22 Demultiplexed System Bus Timing 8XC196NP 13 39 8XC196NP 80C196NU USER S MANUAL intel Toot T TcuwH CLKOUT ALE RD Tcupv I Trov 1 Tsipv gt TwHax T TwHax WR AD15 0 Mus write jJ gt TwHBX TRHBX BHE INST A19 0 o T0012 02 Figure 13 23 Demultiplexed System Bus Timing 80C196NU 13 9 1 Deferred Bus cycle Mode 80C196NU Only The 80C196NU offers a deferred bus cycle mode This bus mode enabled by 1 5 see Figure 13 7 on page 13 16 reduces bus contention when using the 80C196NU in demultiplexed mo
129. in current package offerings Port 1 provides I O pins for the four event processor array EPA modules and the two timers Port 2 is used for the serial I O SIO port two external inter rupts and bus hold functions Port 3 is used for chip select functions and two external interrupts Port 4 functionally only a 4 bit port provides I O pins associated with the three on chip pulse width modulators The EPORT provides address lines A19 16 to support extended addressing See Chapter 7 I O Ports for more information 2 5 2 Serial SIO Port The serial I O SIO port is an asynchronous synchronous port that includes a universal asynchro nous receiver and transmitter UART The UART has one synchronous mode mode 0 and three asynchronous modes modes 1 2 and 3 for both transmission and reception The asynchronous modes are full duplex meaning that they can transmit and receive data simultaneously The re ceiver is buffered so the reception of a second byte can begin before the first byte is read The transmitter is also buffered allowing continuous transmissions See Chapter 8 Serial I O SIO Port for details 2 5 3 Event Processor Array EPA and Timer Counters The event processor array EPA performs high speed input and output functions associated with its timer counters In the input mode the EPA monitors an input for signal transitions When an event occurs the EPA records the timer value associated with it This
130. in ix di im in ix 6x SUB 2 MULU 2 Note 2 di im in ix di im in ix 7 SUBB 20 20 Note 2 di im in ix di im in ix 8x CMP DIVU Note 2 di im in ix di im in ix 9x CMPB DIVUB Note 2 di im in ix di im in ix SUBC LDBZE Ax 1 f im in ix di im in ix SUBCB LDBSE Bx di im in ix di im in ix Cx PUSH POP BMOVI POP di im in ix di in ix Dx JST JH JLE JC JVT JV JLT JE Ex ELD ELD ELDB ELDB DPTS EPTS Note 1 LCALL in ix in ix CLRC SETC DI CLRVT NOP signed RST Fx MUL DIV Note 2 NOTES 1 This opcode is reserved but it does not generate an unimplemented opcode interrupt 2 Signed multiplication and division are two byte instructions The first byte is FE and the second is the opcode of the corresponding unsigned instruction 8XC196NP 80C196NU USER S MANUAL intel Table A 2 Processor Status Word PSW Flags Mnemonic Description C The carry flag is set to indicate an arithmetic carry from the MSB of the ALU or the state of the last bit shifted out of an operand If a subtraction operation generates a borrow the carry flag is cleared Value of Bits Shifted 0 VeLSB 1 gt LSB Normally the result is rounded up if the carry flag is set The sticky bit flag allows a finer resolution in the rounding decision C ST Value of Bits Shifted Off 0 0 0 0 1 gt 0 and lt 15 1 0 2 LSB 1 1 gt Ve LSB and lt 1 LSB N The negative flag i
131. input capture In compare mode specifies the action that the EPA executes when the reference timer matches the event time Mi 0 Capture Mode Event 0 0 no capture 0 1 capture on falling edge 1 0 capture on rising edge 1 1 capture on either edge Mi Compare Mode Action 0 0 no output 0 1 clear output pin 1 0 Set output pin 1 1 toggle output pin 3 RE Re enable Re enable applies to the compare mode only It allows a compare event to continue to execute each time the event time register EPAx TIME matches the reference timer rather than only upon the first time match 0 compare function is disabled after a single event 1 compare function always enabled 2 Reserved always write as zero These bits apply to the EPA1 CON and EPA3 CON registers only Figure 10 10 EPA Control EPAx CON Registers Continued 10 20 intel EVENT PROCESSOR ARRAY EPA EPAx CON Continued Address Table 10 2 on page 10 3 0 3 Reset State 00H The EPA control EPAx CON registers control the functions of their assigned capture compare channels The registers for EPAO andEPA2 are identical The registers for EPA1 and have an additional bit the remap bit This added bit bit 8 requires an additional byte so EPA1 CON and must be addressed as words while the others can be addressed as bytes 15 8 x 1 3 RM 7 0
132. instruc DEST lt DEST 2 tion sets the sticky bit flag Temp lt Temp 1 end while In this operation DEST 2 rep resents signed division PSW Flag Settings Z N C V VT ST 0 v SHRAB ARITHMETIC RIGHT SHIFT BYTE Shifts the destination byte operand to the right as many times as specified by the count operand The count may be specified either as an immediate value in the range of 0 to 15 OFH inclusive or as the content of any register 10H OFFH with a value in the range of 0 to 31 inclusive If the original high order bit value was 0 zeros are shifted in If the value was 1 ones are shifted in The last bit shifted out is saved in the carry flag Temp lt COUNT do while Temp 0 C Low order bit of DEST DEST lt DEST 2 Temp lt Temp 1 end while PSW Flag Settings Z N C V VT ST 0 SHRAB breg zcount 00011010 count breg or SHRAB breg breg 00011010 breg breg NOTES This instruction clears the Sticky bit flag at the beginning of the instruction If at any time during the shift a 1 is shifted into the carry flag and another shift cycle occurs the instruc tion sets the sticky bit flag In this operation DEST 2 rep resents signed division A 39 8 196 80C196NU USER S MANUAL intel Table A 6 Instruction Set Continued
133. instruction Use the BMOVI instruction for an interrupt ible operation 8 196 80C196NU USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format BMOVI INTERRUPTIBLE BLOCK MOVE Moves a block of word data from one location in memory to another The instruction is identical to BMOV except that BMOVI is interruptible The source and destination addresses are calculated using the indirect with autoincrement addressing mode A long register PTRS addresses the source and destination pointers which are stored in adjacent word registers The source pointer SRCPTR is the low word and the destination pointer DSTPTR is the high word of PTRS A word register CNTREG specifies the number of transfers The blocks of data can be located anywhere in page 00H of register RAM but should not overlap Because the source SRCPTR and destination DSTPTR pointers are 16 bits wide this instruction uses nonexteneded data moves It cannot operate across page boundaries If you need to cross page boundaries use the EBMOVI instruction PTSSRC and PTSDST will operate from the page defined by EP REG EP REG should be set to 00H to select page 00H see Accessing Data on page 5 23 The 80C196NU forces REG to 00H COUNT lt CNTREG LOOP SRCPTR lt PTRS DSTPTR lt 2 DSTPTR lt SRCPTR PTRS lt SRCPTR 2 PTRS 2 lt DSTPTR 2 COUNT lt
134. loop counter are either 16 or 17 bits 16 bits plus a sign extension Some of these registers can reduce the ALU s workload by per forming simple operations The RALU uses the upper and lower word registers together for the 32 bit instructions and as temporary registers for many instructions These registers have their own shift logic and are used for operations that require logical shifts including normalize multiply and divide operations The six bit loop counter counts repetitive shifts The second operand register stores the second operand for two operand instructions including the multiplier during multiply operations and the divisor during divide operations During subtraction operations the output of this register is com plemented before it is moved into the ALU The RALU speeds up calculations by storing constants e g 0 1 and 2 in the constants register so that they are readily available when complementing incrementing or decrementing bytes or words In addition the constants register generates single bit masks based on the bit select reg Ister for bit test instructions 2 3 3 1 Code Execution The RALU performs most calculations for the device but it does not use an accumulator Instead it operates directly on the lower register file which essentially provides 256 accumulators Be cause data does not flow through a single accumulator the device s code executes faster and more efficiently 2 4 intel ARCHITECT
135. low byte Bit Number Function 15 0 Timer Read the current timer x value from this register or write a new timer x value to this register Table C 17 TIMERx Addresses and Reset Values Register Address Reset Value TIMER1 1F92H 0000H TIMER2 1F96H 0000H C 48 intel REGISTERS WSR WSR Address 0014H Reset State 00H The window selection register WSR has two functions One bit enables and disables the bus hold protocol The remaining bits select windows Windows map sections of RAM into the top of the lower register file in 32 64 or 128 byte increments PUSHA saves this register on the stack and POPA restores it 7 0 HLDEN W6 W5 WA W3 W2 W1 WO Bit Bit Number Mnemonic ponen 7 HLDEN HOLD HLDA Protocol Enable This bit enables and disables the bus hold protocol see Chapter 13 Interfacing with External Memory It has no effect on windowing 1 enable 0 disable 6 0 W6 0 Window Selection These bits specify the window size and window number See Table 5 8 on page 5 15 or Table 5 9 on page 5 15 Table C 18 WSR Settings and Direct Addresses for Windowable SFRs 32 byte Windows 64 byte Windows 128 byte Windows Register Memory 00 0 00 00 0 0080 00FFH Mnemonic Location 5 3 n WSR address WSR address WSR
136. nonextended data accesses to page 00H You cannot use EP REG to change pages Single Transfer Block Transfer ee Unused Unused PTSCONST2 Unused Unused PTSBLOCK PTSCONST2 L Unused PTSDST H PTSDST H PTSCONST1 H PTSCONST1 PTSDST L PTSDST L PTSCONST1 L PTSCONST1 L PTSSRC H PTSSRC H PTSPTR1 PTSPTR1 PTSSRC L PTSSRC L PTSPTR1 L PTSPTR1 L PTSCON PTSCON PTSCON PTSCON PTSVECT PTSCOUNT PTSCOUNT Unused Unused Figure 6 9 PTS Control Blocks 6 6 1 Specifying the PTS Count For single and block transfer routines the first location of the PTSCB contains an 8 bit value called PISCOUNT This value defines the number of interrupts that will be serviced by the PTS routine The PTS decrements PPSCOUNT after each PTS cycle When PTSCOUNT reaches zero hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit Figure 6 10 which re quests an end of PTS interrupt The end of PTS interrupt service routine should reinitialize the PTSCB if required and set the appropriate PTSSEL bit to re enable PTS interrupt service 6 18 intel STANDARD AND PTS INTERRUPTS PTSSRV Address 0006H Reset State 0000H The PTS service PTSSRV register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine When PTSCOUNT reaches zero hardware clears the co
137. not exact and the resulting baud rate is slightly different than desired The tables show the percentage of error when using the sam ple SP BAUD values In most cases a serial link will work with up to 5 0 difference in the re ceiving and transmitting baud rates Table 8 3 SP BAUD Values When Using the Internal Clock at 25 MHz SP BAUD Register Value Note 1 Error Baud Rate Mode 0 Mode 1 2 3 Mode 0 Mode 1 2 3 9600 8515H 80A2H 0 0 15 4800 8A2BH 8144H 0 0 16 2400 9457H 828AH 0 0 1200 A8AFH 8515H 0 0 300 Note 2 9457H Note 2 0 NOTES 1 Bit 15 is always set when the internal peripheral clock is selected as the clock source for the baud rate generator 2 For mode 0 operation at 25 MHz the minimum baud rate is 381 47 BAUD VALUE 7FFFH For mode 0 operation at 300 baud the maximum internal clock frequency is 19 6608 MHz BAUD VALUE 7FFFH intel SERIAL 1 0 SIO PORT Table 8 4 BAUD Values When Using the Internal Clock at 50 MHz 80C196NU Only SP BAUD Register Value Error Baud Rate Mode 0 Mode 1 2 3 Mode 0 Mode 1 2 3 9600 8A2CH 8145H 0 0 15 Bit 15 is always set when the internal peripheral clock is selected as the clock source for the baud rate generator 8 4 4 Enabling the Serial Port Interrupts The serial port has both a transmit interrupt TT and a receive interrupt RI To enable an inter rupt set the corresponding mask bit in the i
138. of 00 FEH XXX The three high order bits of displacement D or S prefix is used only when it could be unclear whether a variable refers to a destination or a Source register A 6 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Mnemonic Operation Instruction Format ADD ADD WORDS Adds the source and DEST SRC 2 operands destination word operands and stores the ADD wreg waop sum into the destination operand DEST lt DEST SRC PSW Flag Settings 2 V VT ST 011001 wreg ADD 8 operands ADD WORDS Adds the two source word operands and stores the sum into the destination operand DEST lt SRC1 SRC2 PSW Flag Settings 2 V VT ST Vi vi I7111 DEST SRC1 SRC2 ADD Dwreg Swreg waop 010001 waop Swreg Dwreg ADDB 2 operands ADD BYTES Adds the source and destination byte operands and stores the sum into the destination operand DEST lt DEST SRC PSW Flag Settings 2 V VT ST DEST SRC ADDB breg baop 011101 breg ADDB 8 operands ADD BYTES Adds the two source byte operands and stores the sum into the destination operand DEST lt SRC1 SRC2 PSW Flag Settings 2 V VT ST
139. of PTSSRC after each byte or word transfer DI PTSDST Autoincrement 0 do not increment the contents of PTSDST after each byte or word transfer 1 increment the contents of PTSDST after each byte or word transfer PTSCOUNT PTSCB 0 Consecutive Block Transfers Defines the number of blocks that will be transferred during the block transfer routine Each block transfer is one PTS cycle Maximum number is 255 Figure 6 13 PTS Control Block Block Transfer Mode Continued 6 25 8XC196NP 80C196NU USER S MANUAL intel 6 6 5 PWM Modes The PWM toggle and PWM remap modes are designed for use with the event processor array EPA to generate pulse width modulated PWM output signals These modes can also be used with an interrupt signal from any other source The PWM toggle mode uses a single EPA channel to generate a PWM signal The PWM remap mode uses two EPA channels but it can generate signals with duty cycles closer to 096 or 10096 than are possible with the PWM toggle mode Ta ble 6 7 compares the two PWM modes For code examples see AP 445 8XC196KR Peripherals A User s Point of View and PWM Output Program on page 10 26 Table 6 7 Comparison of PWM Modes PWM Toggle Mode PWM Remap Mode Uses a single EPA channel Uses two EPA channels Reads the location specified by PTSPTR1 Reads the location specified by PTSPTR1 usually EPAx TIME usu
140. on the device pins The address decoded by an external device depends on how many of these address lines the external system uses See also internal address Constants that can be accessed only with extended instructions See also near constants far data FET fractional mode hold latency input leakage integer INTEGER internal address interrupt controller interrupt latency interrupt service routine interrupt vector GLOSSARY Data that can be accessed only with extended instruc tions See also near data Field effect transistor Lowercase f represents the frequency of the internal clock For the 8XC196NP f is always equal to the input frequency on XTAL For the 80C196NU which employs a phase locked loop with clock multiplier circuitry f is equal to either 1 2 OF 4By144 The multiplier depends on the clock mode which is controlled by the PLLEN1 and PLLEN2 input pins Figure 2 4 on page 2 8 illustrates the clock circuitry of the 80C196NU A mode of the multiply accumulate function in which the multiplier result is shifted left one bit before being written to the accumulator This left shift eliminates the extra sign bit when both operands are signed leaving a correctly signed result The time it takes the microcontroller to assert HLDA after an external device asserts HOLD Current leakage from an input pin to power or ground Any member of the set consistin
141. outputs The system in Figure 13 5 on page 13 13 illustrates a mixture of 8 bit and 16 bit devices with different num bers of wait states 13 5 1 A 16 bit Example System Figure 13 10 shows a 16 bit system in demultiplexed mode The flash memory receives the ad dress A18 1 data is transferred on AD15 0 Using the WR signal as shown this system writes words and not single bytes to the memory Using WRL and WRH you can write single bytes on a 16 bit bus 13 21 8XC196NP 80C196NU USER S MANUAL intel CS CS Flash Flash 8 5196 256 16 256Kx16 A19 0 A17 0 A17 0 A2438 03 Figure 13 10 16 bit External Devices in Demultiplexed Mode 13 5 2 16 bit Bus Timings Figure 13 11 shows idealized 16 bit external bus timings for the 8XC196NP The signals are di vided into two groups signals for a demultiplexed bus top and signals for a multiplexed bus bottom Several bus signals are omitted from the figure to focus on a comparison of multiplexed and demultiplexed buses The timing parameters are addressed in Comparison of Multiplexed and Demultiplexed Buses on page 13 26 Comprehensive timing specifications for both the 8XC196NP and the 80C196NU are shown in Figures 13 20 through 13 23 CLKOUT and ALE are the same in multiplexed and demultiplexed buses The CLKOUT period is twice the internal oscillator period 2t The bus cycles shown here which have no wait states require two CLKOUT periods two st
142. power conservation mode standby is available on the 80C196NU On circuit emulation ONCE mode electrically isolates the microcontroller from the system See Chapter 12 Special Operating Modes for more information about idle powerdown standby and ONCE modes 2 6 1 Reducing Power Consumption The power saving modes selectively disable internal clocks to reduce power consumption Figure 2 3 on page 2 7 and Figure 2 4 on page 2 8 illustrate the clock circuitry of the 8XC196NP and 80C196NU respectively In idle mode the CPU stops executing instructions but the peripheral clocks remain active Pow er consumption drops to about 40 of normal execution mode consumption Either a hardware reset or any enabled interrupt source will bring the device out of idle mode The 80C196NU has an additional power saving mode standby In standby mode all internal clocks are frozen at logic state zero but the oscillator and phase locked loop continue to run Power consumption drops to about 1096 of normal execution mode consumption Either a hard ware reset or any enabled external interrupt source will bring the device out of standby mode In powerdown mode all internal clocks are frozen at logic state zero and the oscillator is shut off The register file and most peripherals retain their data if V is maintained Power consumption drops into the uW range 2 12 intel ARCHITECTURAL OVERVIEW 2 6 2 Testing the Printed Circuit Board
143. prt2 reg between any two locations in the 16 Mbyte address space This instruction is inter NOTES The pointers are autoincre ruptable mented during this instruction The source and destination addresses are However CNTREG is decre calculated using the extended indirect with mented only when the instruc autoincrement addressing mode A quad tion is interrupted When word register PTRS addresses the 24 bit is interrupted Source and destination pointers which are CNTREG is updated to store stored in adjacent double word registers The the interim word count at the Source pointer SRCPTR is the low double time of the interrupt For this word and the destination pointer is the high reason you should always double word of PTRS A word register reload CNTREG before starting CNTREG specifies the number of transfers an EBMOVI The blocks of data can reside anywhere in memory but should not overlap For 20 bit addresses the offset COUNT lt CNTREG must be in the range of LOOP SRCPTR lt PTRS 524287 10524266 DSTPTR lt 2 DSTPTR lt SRCPTR PTRS lt SRCPTR 2 PTRS 2 DSTPTR 2 COUNT COUNT 1 if COUNT 0 then go to LOOP PSW Flag Settings Z N C V VT ST EBR EXTENDED BRANCH INDIRECT Continues DEST execution at the address specified in the EBR cadd operand word register This instruction is an unconditional indirect jump to anywhere in the 16 Mbyte address space EBR treg
144. range The base address of a 2 byte address range must be on 2 byte boundary Table 13 4 15 8 BASE19 BASE18 BASE17 BASE16 7 0 BASE15 BASE14 BASE13 BASE12 BASE11 BASE10 BASE9 BASE8 iiu 15 12 Reserved for compatibility with future devices write zeros to these bits 11 0 5 19 8 Base Address Bits These bits are the 12 most significant bits of the base address of the address range assigned to chip select x Figure 13 2 Address Compare ADDRCOM Y Register Table 13 4 ADDRCOMXx Addresses and Reset Values Register Address Reset Value ADDRCOMO 1F40H OF20H ADDRCOM1 1F48H X000H ADDRCOM2 1F50H X000H ADDRCOM3 1F58H X000H ADDRCOM4 1F60H X000H ADDRCOM5 1F68H X000H 13 7 8 196 80C196NU USER S MANUAL intel ADDRMSKx x 0 5 Address Reset State Table 13 5 The address mask ADDRMSK register together with the address compare register defines the address range that is assigned to the chip select x output CSx The address mask register determines the size of the address range which must be 2 bytes where n 8 9 20 Fora 2 byte address range calculate n 20 n and set the most significant bits of MASK19 8 in the address mask register 15 8 MASK19 MASK18 MASK17 MASK16 7 0
145. receives data into the receive buffer it transmits data from the port through the transmit buffer The transmit and receive buffers are separate registers permitting simultaneous reads and writes to both The transmitter and receiver are buffered to support continuous trans missions and to allow reception of a second byte before the first byte has been read 8 1 8XC196NP 80C196NU USER S MANUAL intel An independent 15 bit baud rate generator controls the baud rate of the serial port Either the in ternal peripheral clock or TICLK can provide the clock signal The baud rate register SP BAUD selects the clock source and the baud rate 8 2 SERIAL I O PORT SIGNALS AND REGISTERS Table 8 1 describes the SIO signals and Table 8 2 describes the control and status registers Table 8 1 Serial Port Signals Serial Port Serial Port Port e Pin Signal Signal Description Type P2 0 TXD Transmit Serial Data In modes 1 2 and 3 TXD transmits serial port output data In mode 0 it is the serial clock output P2 1 RXD VO Receive Serial Data In modes 1 2 and 3 RXD receives serial port input data In mode 0 it functions as an input or an open drain output for data P1 4 Timer 1 Clock External clock source for the baud rate generator input Table 8 2 Serial Port Control and Status Registers Mnemonic Address Description INT_MASK 0013H Interrupt Mask Setting the TI bit enable
146. routine will read the EPAx TIME regis ter After the CPU reads the EPAx TIME register the buffered data moves from the buffer to the EPAx TIME register This sets the EPA interrupt pending bit 10 4 2 Operating in Compare Mode When the selected timer value matches the event time value the action specified in the control register occurs 1 the pin is set cleared or toggled If the re enable bit EPAx CON 3 is set the action reoccurs on every timer match If the re enable bit is cleared the action does not reoc cur until a new value is written to the event time register See Programming the Capture Com pare Channels on page 10 18 for configuration information In compare mode you can use the EPA to produce a pulse width modulated PWM output The following sections describe four possible methods 10 4 2 1 Generating a Low speed PWM Output You can generate a low speed pulse width modulated output with a single EPA channel and a standard interrupt service routine Configure the EPA channel as follows compare mode toggle output and the compare function re enabled Select standard interrupt service enable the EPA interrupt and globally enable interrupts with the EI instruction When the assigned timer counter value matches the value in the event time register the EPA toggles the output pin and generates an interrupt The interrupt service routine loads a new value into EPAx TIME 10 12 intel EVENT PROCESSOR ARRAY EPA
147. selected by chip configuration register 0 Figure 13 6 on page 13 15 Figure 13 17 shows the waveforms of the asserted write control signals in the two modes Note that only is valid throughout the bus cycle 13 33 8XC196NP 80C196NU USER S MANUAL intel Standard Mode Write Strobe Mode WR WRL Active for low or high byte write Active for low byte write BHE N Nf Active for high byte write Active for high byte write A2472 02 Figure 13 17 Write control Signal Waveforms Table 13 14 compares the values of the write control signals for write operations in the standard mode and the write strobe mode The table lists values of WR and BHE and values of WRL and WRH for 8 bit and 16 bit writes on an 8 bit and 16 bit bus Table 13 14 Write Signals for Standard and Write Strobe Modes Standard Write Strobe Bus Word Byte AO CCRO 2 1 CCRO 2 0 Width Written WR BHE WRL WRH Low Byte 0 1 0 0 8 High Byte 1 0 0 0 0 0 Word 1 Illegal Illegal Low Byte 0 1 0 1 High Byte 1 0 1 16 icd 0 0 Word 1 Illegal Illegal To select the standard write control mode set 2 In standard mode the WR WRL pin operates as WR and the BHE W RHf pin operates as BHE WR is asserted for every external memory write BHE is asserted for word accesses read and write and for byte accesses to odd addresses can be used to sel
148. standby modes 1 enable powerdown and standby modes If your design uses powerdown or standby mode set this bit when you program the CCBs If it does not clearing this bit when you program the CCBs will prevent accidental entry into powerdown and standby mode Chapter 12 Special Operating Modes discusses powerdown and standby modes The CCRs are loaded with the contents of the chip configuration bytes CCBs after a device reset The CCBs reside in nonvolatile memory at addresses FF2018H CCBO and FF201AH CCB1 Figure 13 6 Chip Configuration 0 CCRO Register 18 15 8XC196NP 80C196NU USER S MANUAL intel CCR1 no direct accesst The chip configuration 1 CCR1 register selects the 16 bit or 24 bit addressing mode and for the 8XC196NP only controls whether the internal ROM is mapped into two address ranges 2000 FF2FFFH and 002000 002FFFH or into FF2000 FF2FFFH only 7 0 8 196 1 1 0 1 1 REMAP MODE64 7 0 80C196NU 1 1 DM 1 1 MODE64 Bit Bit Number Mnemonic Function 7 6 1 To guarantee device operation write ones to these bits 5ft DM Deferred Mode Enables the deferred bus cycle mode If the 80C196NU is using a demulti plexed bus and deferred mode is enabled a delay of 2t occurs in the first bus cycle following a chip select output change and the first write cycle following a read cycle See Deferred Bus c
149. tables individual descriptions of the registers are ar ranged alphabetically by mnemonic Table C 1 Modules and Related Registers Chip Configuration iu ird een 205 CCRO ADDRCOMx 0x 80C196NU EPA MASK CCR1 ADDRMSKx ACC STAT 80C196NU EPA PEND BUSCONx ONES REG EPAx CON PSW EPAx TIME SP ZERO REG Extended Port ns as Interrupts Memory Control EP DIR Px DIR INT MASK WSR EP MODE Px MODE INT MASK1 WSR 1 80C196NU EP PIN Px PIN INT PEND EP REG Px REG INT PEND1 P PTS Serial Port dpa CON REGO PTSSEL SBUF RX TIMERx PWMx CONTROL PTSSRV SBUF TX TxCONTROL SP_BAUD SP_CON SP_STATUS 8 196 80C196NU USER S MANUAL Table C 2 Register Name Address and Reset Status In lel Binary Reset Value Register Name KG i e 00 NU Accumulator 0 000CH 0000 0000 0000 0000 _02 NU 2 000 0000 0000 0000 0000 STAT NU Accumulator Control and Status 000BH 0000 0000 ADDRCOMO Address Compare 0 1F40H 0000 1111 0010 0000 ADDRCOM1 Address Compare 1 1F48H XXXX 0000 0000 0000 ADDRCOM2 Address Compare 2 1F50H XXXX 0000 0000 0000 ADDRCOMS Address Compare 3 1F58H XXXX 0000 0000 0000 ADDRCOM4 Address Compare 4 1F60H XXXX 0000 0000 0000 ADDRCOM5 Address Compare 5 1F68H XXXX 0000 0000 0000 ADDRMSKO Address Mask 0 1F42H 1111 1111 1111
150. te ie e ect ie 6 8 6 4 8 1 Standard Interrupt Latency 2 8 6 44 22 PTS Interrupt Latency 5 cene etr ba egeret 6 9 6 5 PROGRAMMING THE INTERRUPTS ae OHO 6 5 1 Programming Considerations for Multiplexed Interrupts Gall 6 5 2 Modifying Interrupt Priorities O7 19 6 5 3 Determining the Source of an Interrupt REP cmd Es 6 6 INITIALIZING THE PTS CONTROL 6 17 6 6 1 Specifying the PTS COUNT iniia e p ei nere ERR Po eA ere ades 6 18 6 6 2 Selecting tlie P TS MOGG fepe ea de pe de dest 6 19 6 6 3 Single Transfer Mode ennemis 720 6 6 4 erret rry tetto teen eat 6 23 6 6 5 PWM Modes ev wo ERU ERR eed n 6 26 6 6 5 1 PWM Toggle Mode Example esee mn Oo 6 6 5 2 PWM Remap Mode Example seem 6 32 CHAPTER 7 PORTS 7 1 V O PORTS OVERVIEW ee eric e Ee Pee ERE ento Pee E EYE RE ua 7 1 7 2 BIDIRECTIONAL PORIS JM uent e hata c ire Der e eden 7 1 7 2 1 Bidirectional Port Operation 2 7 3 7 2 2 Bidirectional Port Pin Configurations seem 7 7 7 2 3 Bidirectional Port Pin Configuration Example 7 8 7 2 4 Bidirectional Port Considerations 2 7 9 7 2 5 Design Considerations for External Interrupt Inputs
151. that the corresponding overrun interrupt source is pending This register was called EPA STAT in previous documentation for the 8XC196NP Figure 10 12 EPA Interrupt Pending EPA PEND Register The EPA interrupt pending register EPA PEND has the same bit structure as the EPA MASK register EPA PEND is similar to an interrupt pending register in that it shows the status of the individual capture compare overrun interrupts The bits in PEND be polled to deter mine the exact source of an OVRO 1 or OVR2 3 interrupt However hardware does not clear status bits in this register when it vectors to the interrupt service routine for an interrupt pair OVRO 1 OVR2 3 so the user s code must clear the register Instead it clears the OVRO 1 or OVR2 3 bitin the INT MASK register Also software cannot generate an interrupt by setting a bit in EPA PEND 10 7 1 Using Software to Service the Multiplexed Overrun Interrupts The multiplexed overrun interrupts should normally be serviced by interrupt service routines be cause the PTS cannot determine the exact source of the interrupt When an OVRO 1 or OVR2 3 occurs the user s software service routine can poll the bits of the EPA PEND register which has a bit for each overrun source to determine which of the four capture compare channels caused the interrupt The individual sources can be masked by bits in the EPA MASK register 10 23 8XC196NP 80C196NU USER S MANUAL intel
152. the external interrupt pins EXTINT low while the device is in standby mode 12 6 intel SPECIAL OPERATING MODES 12 4 3 Exiting Standby Mode The device will exit standby mode when a transition on an external interrupt pin EXTINT3 0 or a hardware reset occurs The interrupts need not be enabled for them to bring the device out of standby but the pin must be configured as a special function input see Bidirectional Port Pin Configurations on page 7 7 When an external interrupt brings the device out of standby mode the corresponding pending bit is set in the interrupt pending register If the interrupt is enabled the device executes the interrupt service routine then fetches and executes the instruction following the IDLPD 3 instruction If the interrupt is disabled masked the device fetches and executes the instruction following the IDLPD 3 instruction and the pending bit remains set until the interrupt is serviced or software clears it 12 5 POWERDOWN MODE Powerdown mode places the device into a very low power state by disabling the internal oscilla tor the phase locked loop circuitry 80C196NU only and clock generators Internal logic holds the CPU and peripheral clocks at logic zero which causes the CPU to stop executing instructions the system bus control signals to become inactive the CLKOUT signal to become high and the peripherals to turn off Power consumption drops into the microwatt range refer to the dat
153. the following events occurs ahardware reset is generated or atransition occurs on an external interrupt pin NOTE It was previously documented that the method of exiting powerdown mode by driving the RPD pin low was acceptable however we no longer recommend this method as an option for exiting powerdown 12 5 3 1 Generating a Hardware Reset The device will exit powerdown if is asserted If the phase locked loop circuitry is en abled or if the design uses an external clock input signal rather than the on chip oscillator RESET must remain low for at least 16 state times If the design uses the on chip oscillator then RESET must be held low until the oscillator and phase locked loop circuitry have stabilized 12 5 3 2 Asserting an External Interrupt Signal The final way to exit powerdown mode is to assert an external interrupt signal EXTINT3 0 for at least one state time Although EXTINT3 0 are normally sampled inputs the powerdown cir cuitry uses them as level sensitive inputs The interrupts need not be enabled to bring the device out of powerdown but the pin must be configured as a special function input see Bidirectional Port Pin Configurations on page 7 7 Figure 12 3 shows the power up and powerdown se quence when using an external interrupt to exit powerdown When an external interrupt brings the device out of powerdown mode the corresponding pending bit is set in the interrupt pending register I
154. the internal ROM mapping 0 ROM maps to FF2000 FF2FFFH only 1 ROM maps to FF2000 FF2FFFH and 002000 002FFFH 1 MODE64 Addressing Mode Selects 64 Kbyte or 1 Mbyte addressing 0 selects 1 Mbyte addressing 1 selects 64 Kbyte addressing 0 Reserved for compatibility with future devices write zero to this bit The CCRs are loaded with the contents of the chip configuration bytes CCBs after a device reset The CCBs reside in nonvolatile memory at addresses FF2018H CCBO and FF201AH CCB1 t Bit 5 is reserved on the 8XC196NP device and bit 2 is reserved on the 80C196NU device For compatibility with future devices write zeros to these bits intel REGISTERS CON REGO CON REGO Address 1FB6H Reset State FEH The control CON register controls the clock prescaler for the three pulse width modulators PWMO PWM 2 7 0 8 196 CLKO 7 0 80C196NU CLK1 CLKO ror NC Function 7 1 NP Reserved for compatibility with future devices write zeros to these bits 7 2 NU 0 NP CLKO Enable PWM Clock Prescaler This bit controls the PWM output period by enabling or disabling the clock prescaler divide by two on the three pulse width modulators PWMO0 PWM2 0 disable PWM output period is 512 state times 1 enable PWM output period is 1024 state times 1 0 NU CLK1 0 Enable PWM
155. timer counting direction in selected modes see mode bits M2 0 0 count down 1 count up 5 8 M2 0 EPA Clock Direction Mode Bits These bits determine the timer clocking source and direction control source M2 1 0 ClockSource Direction Source 0 0 0 f 4 UD bit TI CONTROL 6 X 0 1 UD bit T1CONTROL 6 0 1 0 f 4 T1DIR pin 0 1 1 T1CLK T1DIR pin 1 1 1 quadrature clocking using T1CLK and T1DIR If an external clock is selected the timer counts on both the rising and falling edges of the clock 2 0 P2 0 EPA Clock Prescaler Bits These bits determine the clock prescaler value P2 P1 PO Prescaler Divisor Resolution 0 0 0 divide by 1 disabled 160 ns 0 0 1 divide by 2 320 ns 0 1 0 divide by 4 640 ns 0 1 1 divide by 8 1 28 us 1 0 0 divide by 16 2 56 us 1 0 1 divide by 32 5 12 us 1 1 0 divide by 64 10 24 us 1 1 1 divide by 128 NU only 20 48 us t At f 25 MHz Use the formula on page 10 6 to calculate the resolution at other frequencies C 46 intel REGISTERS T2CONTROL T2CONTROL Address 1F94H Reset State 00H The timer 2 control T2CONTROL register determines the clock source counting direction and count rate for timer 2 7 0 CE UD M2 M1 MO P2 P1 PO Bit Bit Function Number Mnemonic 7 CE Counter Enable This bit enables or disables the timer From reset the timers are disabled and not free running
156. to your fax machine You can get product announcements change notifications product literature device characteristics de sign recommendations and quality and reliability information from FaxBack 24 hours a day 7 days a week 1 800 628 2283 U S and Canada 916 356 3105 U S Canada Japan Asia Pacific 44 0 1793 496646 Europe Think of the FaxBack service as a library of technical documents that you can access with your phone Just dial the telephone number and respond to the system prompts After you select a doc ument the system sends a copy to your fax machine Each document is assigned an order number and is listed in a subject catalog The first time you use FaxBack you should order the appropriate subject catalogs to get a complete listing of doc ument order numbers Catalogs are updated twice monthly In addition daily update catalogs list the title status and order number of each document that has been added revised or deleted dur ing the past eight weeks The daily update catalogs are numbered with the subject catalog number followed by a zero For example for the complete microcontroller and flash catalog request doc ument number 2 for the daily update to the microcontroller and flash catalog request document number 20 1 8 intel GUIDE TO THIS MANUAL The following catalogs and information are available at the time of publication 1 Solutions OEM subscription form Microcontroller and flash catalog Developmen
157. trap flag is clear this instruction adds to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in range of 128 to 127 if VT then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST 0 JNVT cadd 11010100 disp NOTE The displacement disp is sign extended to 24 bits JST JUMP IF STICKY BIT FLAG IS SET Tests the sticky bit flag If the flag is clear control passes to the next sequential instruction If the sticky bit flag is set this instruction adds to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in range of 128 to 127 if ST 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JST cadd 11011000 disp NOTE The displacement disp is sign extended to 24 bits JV JUMP IF OVERFLOW FLAG IS SET Tests the overflow flag If the flag is clear control passes to the next sequential instruction If the overflow flag is set this instruction adds to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in range of 128 to 127 if V 2 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST
158. value currently in the register not the value in the buffer Therefore any change to P2 7 can be read only after P2 MODE 7 is cleared After reset your software must configure the device to match the external system This is accomplished by writing appropriate config data into P3 MODE Writing to P3 MODE not only configures the pins but also turns off the transistor that weakly holds the pins high Q4 in Figure 7 1 on page 7 5 For this reason even if port 3 is to be used as it is configured at reset you should still write data into P MODE 0 50 is weakly pulled high during reset After reset it defaults to the 0 function This chip select signal detects address ranges that contain the CCBs and FF2080H program start up address See Chapter 13 Interfacing with External Memory for a detailed description of chip select signal functions after reset Writing to P3 MODE 6 sets the EXTINT2 interrupt pending bit INT PENDI 5 After configuring the port pins clear the interrupt pending registers before globally enabling interrupts See Design Considerations for External Interrupt Inputs on page 7 11 Writing to P3 MODE 7 sets EXTINT3 interrupt pending bit INT PENDI 6 After configuring the port pins clear the interrupt pending registers before globally enabling interrupts See Design Considerations for External Interrupt Inputs on page 7 11 After reset your software must configure the devic
159. values of the SFRs The device re mains in its reset state until RESET is deasserted When RESET is deasserted the bus control ler fetches the chip configuration bytes CCBs loads them into the chip configuration registers CCRs and then fetches the first instruction Figure 11 7 shows the reset sequence timing RESET Pin Internal Reset A15 0 2018H 201AH CCB1 AD7 0 OOH j iH jy XX AH XX Note 2 AD15 8 00H 20H Strongly Driven 2 20H Strong DyX A19 16 OFH Strongly Driven Bus parameters defined by CCBO bus width multiplexed or demultiplexed mode number of wait states take effect here at start of second bus cycle BUSCONO is changed here by value of CCBO Notes 1 Depends on number of wait states defined in CCBO 2 If bus is multiplexed AD15 8 strongly drive 20H If bus is demultiplexed AD15 8 drive the data that is currently on the high byte of the internal bus A2417 02 Figure 11 7 Reset Timing Sequence intel MINIMUM HARDWARE CONSIDERATIONS The following events will reset the device see Figure 11 8 anexternal device pulls the pin low the CPU issues the reset RST instruction the CPU issues an idle powerdown IDLPD instruction with an illegal key operand The following paragraphs describe each of these reset methods in more detail Internal i External 1 M Reset State oc 1 1 Internal Machine Reset Sign
160. when you program the CCBs will prevent accidental entry into powerdown and standby modet Chapter 12 Special Operating Modes discusses powerdown and standby modes The CCRs are loaded with the contents of the chip configuration bytes CCBs after a device reset The CCBs reside in nonvolatile memory at addresses FF2018H CCBO and FF201AH CCB1 8XC196NP 80C196NU USER S MANUAL intel CCR1 CCR1 no direct accesst The chip configuration 1 CCR1 register selects the 16 bit or 24 bit addressing mode and for the 8XC196NP only controls whether the internal ROM is mapped into two address ranges 2000 FF2FFFH and 002000 002FFFH or into FF2000 FF2FFFH only 7 0 8 196 1 1 0 1 1 REMAP MODE64 7 0 80C196NU 1 1 DM 1 1 MODE64 Bit Bit Number Mnemonic Function 7 6 1 To guarantee device operation write ones to these bits 5tt DM Deferred Mode Enables the deferred bus cycle mode If the 80C196NU is using a demulti plexed bus and deferred mode is enabled a delay of 2t occurs in the first bus cycle following a chip select output change and the first write cycle following a read cycle See Deferred Bus cycle Mode 80C196NU Only on page 13 40 0 deferred bus cycle mode disabled 1 deferred bus cycle mode enabled 4 3 1 To guarantee device operation write ones to these bits ait REMAP Internal ROM Mapping Controls
161. 0 disables timer 1 enables timer 6 UD Up Down This bit determines the timer counting direction in selected modes see mode bits M2 0 0 count down 1 count up 5 3 M2 0 EPA Clock Direction Mode Bits These bits determine the timer clocking source and direction source M2 1 0 Clock Source Direction Source 0 0 0 f 4 UD bit T2CONTROL 6 X 0 1 T2CLK pin UD bit T2CONTROL 6 0 1 0 f 4 T2DIR pin 0 1 1 T2CLK pint T2DIR pin 1 0 0 timer 1 overflow UD bit T2CONTROL 6 1 1 0 timer 1 same as timer 1 1 1 1 quadrature clocking using T2CLK and T2DIR t If an external clock is selected the timer counts on both the rising and falling edges of the clock 2 0 P2 0 EPA Clock Prescaler Bits These bits determine the clock prescaler value P2 Prescaler Resolution 0 0 0 divide by 1 disabled 160 ns 0 0 1 divide by 2 320 ns 0 1 0 divide by 4 640 ns 0 1 1 divide by 8 1 28 us 1 0 0 divide by 16 2 56 us 1 0 1 divide by 32 5 12 us 1 1 0 divide by 64 10 24 us 1 1 1 divide by 128 NU only 20 48 us At f 25 MHz Use the formula on page 10 6 to calculate the resolution at other frequencies C 47 8XC196NP 80C196NU USER S MANUAL intel TIMERx TIMERx Address Table C 17 x 1 2 Reset State This register contains the value of timer x This register can be written allowing timer x to be initialized to a value other than zero 15 8 Timer Value high byte Timer Value
162. 1 Address 0013H i Reset State 00H The interrupt mask 1 INT MASK1 register enables or disables masks individual interrupt requests The EI and DI instructions enable and disable servicing of all maskable interrupts INT MASK1 can be read from or written to as a byte register PUSHA saves this register on the stack and POPA restores it 7 0 NMI 2 OVR2 3 OVRO 1 2 1 Bit Number Function 7 0 Setting a bit enables the corresponding interrupt The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector NMI Nonmaskable Interrupt FF203EH EXTINT3 EXTINTS pin FF203CH EXTINT2 EXTINT2 pin FF203AH OVR2 3 EPA Capture Channel 2 or 3 Overrun FF2038H OVRO 11 EPA Capture Channel 0 or 1 Overrun FF2036H EPAS3 EPA Capture Compare Channel 3 FF2034H EPA2 EPA Capture Compare Channel 2 FF2032H EPA1 EPA Capture Compare Channel 1 FF2030H An overrun on the EPA capture compare channels can generate the multiplexed capture overrun interrupts The EPA MASK and EPA PEND registers decode these multiplexed interrupts Write to EPA MASK to enable the interrupt sources read EPA PEND to determine which source caused the interrupt C 26 intel REGISTERS INT PEND INT PEND Address 0009H Reset State 00H When hardware detects a pending interrupt it sets the corresponding bit in the interrupt pending INT PEND or INT PEN
163. 10 indirect 11 indexed baop A byte operand that is addressed by any addressing mode bbb A 3 bit field within an opcode that selects a specific bit within a register bitno A 3 bit field within an opcode that selects one of the eight bits in a byte breg A byte register in the internal register file When it could be unclear whether this variable refers to a source or a destination register it is prefixed with an S or a D The value must be in the range of 00 FFH cadd An address in the program code Dbregi A byte register in the lower register file that serves as the destination of the instruction operation disp Displacement The distance between the end of an instruction and the target label Dlregt A 32 bit register in the lower register file that serves as the destination of the instruction operation Must be aligned on an address that is evenly divisible by 4 The value must be in the range of 00 FCH Dwregt A word register in the lower register file that serves as the destination of the instruction operation Must be aligned on an address that is evenly divisible by 2 The value must be in the range of 00 FEH lreg A 32 bit register in the lower register file Must be aligned on an address that is evenly divisible by 4 The value must be in the range of 00 FCH ptr2 Adouble pointer register used with the EBMOVI instruction Must be aligned on an address that is evenly divisible by 8 The value must be in the range of 00 F8H
164. 11 Logic Table for EPORT in I O Mode Configuration Complementary Output PERDU Input EP MODE 0 0 0 0 EP DIR 0 0 1 Note 2 1 EP REG 0 1 0 1 Address Bit X X X X Q1 off on off off Q2 on off on off EP PIN 0 1 0 high impedance NOTES 1 X Don t care 2 If EP_REG is clear Q2 is on if EP REG is set Q2 is off Table 7 12 Logic Table for EPORT in Address Mode Configuration Complementary Output Note 1 EP MODE 1 1 EP DIR X X EP REG X Note 2 X Note 2 Address Bit 0 1 Q1 off on Q2 on off EP PIN 0 1 NOTES 1 X Dont care 2 EP_REG is output on EPORT during any nonextended external memory access 7 16 PORTS intel 7 3 2 Configuring EPORT Pins Each EPORT pin can be individually configured to operate either as an extended address signal or as an I O pin in one of these modes complementary output output only high impedance input or open drain output input output or bidirectional 7 3 2 1 Configuring EPORT Pins for Extended address Functions The EPORT pins default to their extended address functions upon reset see Table B 5 on page B 13 During program execution the pins can be reconfigured at any time from address to I O and back to address However this is not recommended unless you understand the implications of changing memory addressing the fly To change a pin from I O to address clear the EP REG x bit
165. 12 2 INT MASKI 6 3 6 10 6 14 10 3 12 3 INT PEND 6 3 6 4 6 15 8 2 10 3 12 3 INT PENDI 6 4 6 15 10 3 12 3 naming conventions 1 4 DIR 10 3 MODE 10 4 considerations 7 9 PIN 10 4 P1 REG 10 4 P2 DIR 8 3 12 3 P2 MODE 8 3 12 3 considerations 7 9 7 10 P2 PIN 8 2 8 3 P2 REG 8 3 12 3 considerations 7 10 P3 DIR 12 3 P3 MODE 12 3 P3 REG 12 3 PSW 6 4 6 14 PTSCON 6 19 PTSCOUNT 6 18 PTSSEL 6 4 PTSSRV 6 4 Px DIR 7 2 7 6 7 7 7 8 Px MODE 7 2 7 6 7 7 7 8 Px PIN 7 2 7 4 7 6 Px REG 7 2 7 6 7 7 7 8 RALU 2 4 SBUF RX 8 3 SBUF TX 8 3 SP BAUD 8 3 8 11 8 12 8 13 SP CON 8 3 8 9 INDEX SP STATUS 8 4 8 14 TICONTROL 10 4 T2CONTROL 10 4 TIMERI 10 4 TIMER2 10 4 using 4 12 WSR 6 14 WSRI 5 15 REMAP bit See ROM internal 83C196NP Reserved bits defined 1 4 Reserved memory See memory reserved Reset 11 9 13 14 13 16 and bus hold protocol 13 33 and CCB fetches 5 7 and chip select 13 11 and operating mode selection 5 23 circuit diagram 11 10 status CLKOUT P2 7 7 4 7 10 with illegal IDLPD operand 11 11 with RESET pin 11 9 with RST instruction 11 9 11 11 RESET 11 1 12 2 B 10 and CCB fetch 11 8 and device reset 11 8 11 9 11 10 13 33 and ONCE mode 12 12 and powerdown mode 12 8 pins after deassertion 13 18 Resonator ceramic 11 6 RET instruction A 2 A 35 A 52 A 57 A 64 A 65 ROM internal 83C196
166. 2 4 E2 Call 5 c Extended remm Direct Immediate Extended indirect indexed Length Opcode Length Opcode Length Opcode Length Opcode ECALL 4 F1 Indirect Indexed abeo Direct Immediate Note 1 Note 1 Length Opcode Length Opcode Length Opcode Length Opcode LCALL 3 EF RET 1 FO E SCALL Note 3 2 28 2 1 F7 NOTES 1 Indirect normal and indirect autoincrement share the same opcodes as do short and long indexed modes Because word registers always have even addresses the address can be expressed in the upper seven bits the least significant bit determines the addressing mode Indirect normal and short indexed modes make the second byte of the instruction even LSB 0 Indirect autoincrement and long indexed modes make the second byte odd LSB 1 2 For indexed instructions the first column lists instruction lengths as S L where S is the short indexed instruction length and L is the long indexed instruction length 3 Forthe SCALL and SJMP instructions the three least significant bits of the opcode are concatenated with the eight bits to form an 11 bit 2 s complement offset A 57 8 196 80C196NU USER S MANUAL intel Table A 8 Instruction Lengths and Hexadecimal Opcodes Continued Conditional Jump
167. 2 1 and a parity error occurred Reading SP_STATUS clears this bit 6 RI Receive Interrupt This bit is set when the last data bit is sampled Reading SP_STATUS clears this bit This bit need not be clear for the serial port to receive data 5 TI Transmit Interrupt This bit is set at the beginning of the stop bit transmission Reading SP_STATUS clears this bit 4 FE Framing Error This bit is set if a stop bit is not found within the appropriate period of time Reading SP_STATUS clears this bit 3 TXE SBUF_TX Empty This bit is set if the transmit buffer is empty and ready to accept up to two bytes It is cleared when a byte is written to SBUF TX 2 OE Overrun Error This bit is set if data in the receive shift register is loaded into SBUF RX before the previous bit is read Reading SP STATUS clears this bit 1 0 Reserved These bits are undefined C 45 8XC196NP 80C196NU USER S MANUAL intel T1CONTROL T1CONTROL Address 1F90H Reset State 00H The timer 1 control T1 CONTROL register determines the clock source counting direction and count rate for timer 1 7 0 CE UD M2 M1 MO P2 P1 PO Bit Bit _ Function Number Mnemonic neus 7 CE Counter Enable This bit enables or disables the timer From reset the timers are disabled and not free running 0 disables timer 1 enables timer 6 UD Up Down This bit determines the
168. 2 85 84 AD14 83 AD15 RESET 1 RD NMI BHE WRH NC ALE AO INST READY 3 RPD Vss ONCE A2 68 E PLLEN2 A3 67 he S8XC196NU 66 55 6 64 A7 A10 yoo 62 Ait 55 D 12 View of component as E P3 0 CSO mounted on PC board 58 A15 P3 1 51 57 P3 2 CS2 56 F Vss P3 3 CS3 55 XTAL1 ss 54 b XTAL2 P3 4 CS4 P3 5 CS5 P3 6 EXTINT2 3 P2 7 CLKOUT P1 1 EPA1 6 29 P1 2 EPA2 30 P1 3 amp 31 P1 6 T2CLK 35 P1 7 T2DIR E 37 P4 0 PWMO 38 P4 1 PWM1 39 4 2 PWM2 40 P2 0 TXD E 44 P2 1 45 2 2 EXTINTO E 46 P2 3 BREQ 47 P2 5 HOLD 49 P2 6 HLDA 50 P2 4 48 A2823 02 Figure B 3 80C196NU 100 lead SQFP Package SIGNAL DESCRIPTIONS PLLEN1 P3 0 50 P3 1 CS1 P3 2 CS2 P3 3 CS3 55 4 CS4 P3 5 CS5 P3 6 EXTINT2 NC P3 7 1 0 EPAO 1 1 1 amp 31 P1 2 EPA2 32 P1 3 EPA3 33 P1 4 T1CLK 34 83 A16 0 82 A17 EPORT 1 81 P Vcc a lt 1 eo 87 012 86 AD13 85 014 84 8 AD15 S8XC196NU View of component as mounted on PC board P1 5 TIDIR amp 35 P1 6 T2CLK 37 P1 7 T2DIR Q 39 P4 0 PWMO 40 PWM1 g 41 P4 2 PWM2 42 P2 0 TXD E 46 P2 1 RXD amp 47
169. 2 1 Standard Interrupt Latency In 64 Kbyte mode the worst case delay for a standard interrupt is 56 state times 4 39 11 2 if the stack is in external memory Figure 6 2 In 1 Mbyte mode the worst case delay increas es to 61 state times 4 39 15 3 Figure 6 2 This delay time does not include the time need ed to execute the first instruction in the interrupt service routine or to execute the instruction following a protected instruction 6 8 intel STANDARD AND PTS INTERRUPTS 1 Mbyte Mode 4 3 2 39 13 15 2 3 gt lt 12 6 d 64 Kbyte Mode 4 3 2 1 39 11 2 lt 12 6 gt Ending NogML End Call is If Stack wf Mt Stack SS Fxecution NORML Forced External PUSHA External Interrupt Routine Interrupt Interrupt Pending Set Cleared Bit Response 1 Mbyte Mode 61 State Times gt Time 64 Kbyte Mode 56 State Times A0261 02 Figure 6 2 Standard Interrupt Response Time 6 4 2 2 PTS Interrupt Latency In both 64 Kbyte and 1 Mbyte modes the maximum delay for a PTS interrupt is 43 state times 4 39 as shown in Figure 6 3 This delay time does not include the added delay if a protected instruction is being executed or if a PTS request is already in progress See Table 6 4 for execution times for PTS cycles 64 Kbyte or 1 Mbyte Mode 4 3 2 1 4 39 9 1 Ending End Vector to PTS lt PTS Interrupt Routine Interrupt I
170. 2 2 EXTINTO 48 P2 3 BREQ 49 P2 4 50 RD BHE WRH ALE INST READY RPD ONCE PLLEN2 Vss A8 A9 A10 A11 A12 A13 A14 A15 Vss XTAL1 XTAL2 ss P2 7 CLKOUT P2 6 HLDA P2 5 HOLD A2824 02 Figure B 4 80C196NU 100 lead QFP Package 8XC196NP 80C196NU USER S MANUAL intel B 2 SIGNAL DESCRIPTIONS Table B 2 defines the columns used in Table B 3 which describes the signals Table B 2 Description of Columns of Table B 3 Column Heading Description Name Lists the signals arranged alphabetically Many pins have two functions so there are more entries in this column than there are pins Every signal is listed in this column Type Identifies the pin function listed in the Name column as an input 1 output bidirectional I O power PWR or ground GND Note that all inputs except RESET are sampled inputs RESET is a level sensitive input During powerdown mode the powerdown circuitry uses EXTINTx as a level sensitive input Description Briefly describes the function of the pin for the specific signal listed in the Name column Also lists the alternate fuction that are multiplexed with the signal if applicable Table B 3 Signal Descriptions Name Type Description A15 0 VO System Address Bus These address lines provide address bits 0 15 during the entire external memory cycle during both multiplexed an
171. 2 DIR P1 DIR 1FB2H Reserved PWM1 CONTROL 1FDOH P2 MODE P1 MODE 1FBOH Reserved PWMO CONTROL 1FCEH Reserved Reserved 1FAEH Reserved Reserved 1FCOH Reserved Reserved 1FAOH Reserved Reserved EPA Timer 1 and Timer 2 SFRs Chip select SFRs Address High Odd Byte Low Even Byte Address High Odd Byte Low Even Byte 1F9EH Reserved EPA PEND ttt 1F6EH Reserved Reserved 1F9CH Reserved EPA_MASK 1F6CH Reserved BUSCON5 1F9AH Reserved Reserved 1F6AH ADDRMSKS ADDRMSKS5 L 1F98H Reserved Reserved 1F68H ADDRCOMB H ADDRCOMS5 L 1F96H 2 TIMER2 L 1F66H Reserved Reserved 1F94H Reserved T2CONTROL 1F64H Reserved BUSCON4 1F92H TIMER1 TIMER1 L 1F62H ADDRMSKA ADDRMSKA L 1F90H Reserved T1CONTROL 1F60H ADDRCOM4 ADDRCOM4 L 1F8EH EPA3 TIME H TIME L 1F5EH Reserved Reserved 1F8CH EPA3 CON H EPA3 CON L 1F5CH Reserved BUSCON3 1F8AH EPA2_TIME H EPA2_TIME L 1F5AH ADDRMSK3 ADDRMSK3 L 1F88H Reserved EPA2 CON 1F58H ADDRCOMS ADDRCOMS L 1F86H EPA1_TIME H EPA1_TIME L 1F56H Reserved Reserved 1F84H EPA1_CON H EPA1_CON L 1F54H Reserved BUSCON2 1F82H EPAO_TIME EPAO TIME L 1F52H ADDRMSK H ADDRMSK L 1F80H Reserved CON 1F50H ADDRCOM2 ADDRCOM2 L Must be addressed as a word tt For the 8XC196NP these are memory mapped locations They must be addressed with indirect indexed instructions
172. 5 Latch EP PIN Buffer lt D lt LE Read Port PH1 Clock NOTE Shaded area is unique to the 80C196NU A3113 01 Figure 7 2 EPORT Block Diagram If EP MODE x is set address mode the address multiplexer determines the address source For an instruction fetch the address multiplexer is set to the CODE input which selects the extended program counter EPC as the address source For a data fetch or when there is no external bus activity the address multiplexer is set to the DATA input which selects the extended data address register EDAR as the address source The EDAR is loaded from two different sources depending on whether the data access is extend ed or nonextended For extended data accesses the data multiplexer is set to the 1 Mbyte mode input and EDAR is loaded with the extended address For nonextended data accesses the data multiplexer is set to the 64 Kbyte mode input and EDAR is loaded from REG The last value loaded remains in EDAR until the next data access Refer to Fetching Code and Data in the 1 Mbyte and 64 Kbyte Modes on page 5 23 for more information 7 13 8XC196NP 80C196NU USER S MANUAL intel The 8XC196NP allows you to change the value of EP REG to control which memory page a non extended instruction accesses However software tools require that EP REG be equal to 00H The 80C196NU forces all nonextended data accesses to page You cannot use REG to change pages You c
173. 5 1 5 23 7 11 and external address 13 1 block diagram 7 13 complementary output mode 7 14 configuration register settings 7 17 configuring pins 7 17 for extended address 7 17 for 7 17 considerations 7 18 7 19 input buffers 7 19 input mode 7 16 logic tables 7 16 open drain output mode 7 14 operation 7 12 output enable 7 14 overview 7 1 pins 7 11 reset 7 14 SFRs 7 12 structure 7 15 EPORT 3 0 B 8 EPTS instruction 6 10 A 3 A 18 A 52 A 59 67 ESD protection 7 4 7 14 11 5 Index 4 intel EST instruction 4 6 A 3 A 19 A 47 A 56 A 63 ESTB instruction 4 6 A 3 A 19 A 47 A 56 63 Event 10 1 Event processor array See EPA EXT instruction A 2 A 19 A 47 A 53 A 60 EXTB instruction A 2 A 20 A 47 A 53 A 60 Extended address lines 5 1 Extended addressing 2 4 2 11 4 11 5 1 5 23 code execution 4 5 instructions 4 5 4 6 5 24 port See EPORT program counter 2 6 External memory 5 2 fetching code 5 25 flash example in 1 Mbyte mode 5 31 RAM example in 1 Mbyte mode 5 31 RAM example in 64 Kbyte mode 5 27 5 29 EXTINT 6 3 and idle mode 12 6 and powerdown mode 12 6 12 8 hardware considerations 12 9 EXTINT3 0 B 8 EXTINTx 12 1 F f defined 1 3 FaxBack service 1 8 FE opcode and inhibiting interrupts 6 7 Flash memory See external memory flash Floating point library 4 5 Formulas capacitor size powerdown circuit 12 11 clock period t 2 9 a
174. 6 9 1 and cascading timer counters 10 6 block diagram 9 1 calculating duty cycle 6 26 calculating frequency 6 26 Index 8 clock prescaler 9 4 D A converter 9 10 duty cycle 9 5 enabling outputs 9 9 generating 10 15 generating analog outputs 9 9 modes 6 26 6 36 output period 9 3 overview 9 1 programming duty cycle 9 5 remap mode 6 32 toggle mode 6 27 typical waveforms 9 5 waveform 6 27 with dedicated timer counter 10 15 See also EPA PTS PWMO 9 9 PWMO CONTROL C 51 C 54 PWMI 9 9 PWMI CONTROL C 51 C 54 2 9 9 2 0 9 9 10 PWM2 CONTROL 51 54 QUAD WORD defined 4 4 Quick reference guides ordering 1 8 R RALU 2 4 2 5 5 11 RAM internal register RAM 5 11 RD 13 4 13 36 B 10 during bus hold 13 30 READY 13 4 13 26 13 30 B 10 after reset 13 18 for CCB fetches 13 17 timing requirements 13 27 Ready control 13 26 13 30 REAL variables 4 5 Register bits naming conventions 1 4 reserved 1 4 Register file 2 3 5 9 and windows 5 10 5 13 lower 5 10 5 11 5 13 upper 5 10 5 11 intel See also windows Register RAM and idle mode 12 5 and powerdown mode 12 7 Registers ACC 0x 3 4 STAT 3 5 allocating 4 12 EPA MASK 10 3 EPA PEND 10 3 EP DIR 7 12 7 14 7 16 7 17 EP 7 12 7 14 7 16 7 17 7 18 EP PIN 7 12 7 14 7 16 7 17 EP REG 7 12 7 16 7 17 7 18 considerations 7 18 INT MASK 6 3 6 10 6 14 8 2 10 3
175. 60H X000H ADDRCOM5 1F68H X000H intel REGISTERS ADDRMSKx ADDRMSKx Address Table C 6 x 0 5 Reset State The address mask ADDRMSKx register together with the address compare register defines the address range that is assigned to the chip select x output CSx The address mask register determines the size of the address range which must be 2 bytes where n 8 9 20 Fora 2 byte address range calculate n 20 n and set the n most significant bits of MASK19 8 in the address mask register 15 8 MASK19 MASK18 MASK17 MASK16 7 0 MASK15 MASK14 MASK13 MASK12 MASK11 MASK10 MASK9 MASK8 Function 15 12 Reserved for compatibility with future devices write zeros to these bits 11 0 MASK19 8 Address Mask Bits For a 27 address range set the n most significant bits of MASK19 8 where n 20 n Table C 6 ADDRMSKx Addresses and Reset Values Register Address Reset Value ADDRMSKO 1F42H XFFFH ADDRMSK1 1 XFFFH ADDRMSK2 1F52H XFFFH ADDRMSK3 1F5AH XFFFH ADDRMSK4 1F62H XFFFH ADDRMSK5 1F6AH XFFFH 8XC196NP 80C196NU USER S MANUAL intel BUSCONx BUSCONx Address Table C 7 x 0 5 Reset State For the address range assigned to chip select x the bus control BUSCONX register specifies the number of wait states the bus width and the address data multipl
176. 64 bit controls whether the device operates in 1 Mbyte or 64 Kbyte mode is loaded with the contents of at reset When MODE64 is clear the device operates in 1 Mbyte mode In this mode code can execute from any page in the 1 Mbyte address space An extended jump branch or call instruction across pages changes the EPC value to the destina tion page For example assume that code is executing from page FFH The following code seg ment branches to an external memory location in page 00H and continues execution OFF2090H LD TEMP 12H ST TEMP PORT1 EBR 003000H 003000 ADD TEMP 50H code executing in page FFH code executing in page FFH jump to location 3000H in page 00H code executing in page 00H Code fetches are from external memory or internal memory depending on the device the instruc tion address and the value of the EA input 80C196NU Code executes from any page in external memory 80C196NP For devices without internal nonvolatile memory must be tied low and code executes from any page in external memory 83C196NP Code in all locations except FF2000 FF2FFFH executes from external memory Instruction fetches from FF2000 FF2FFFH are controlled by the EA input If EA is low code executes from external memory f EAf is high code executes from internal ROM Note that the EA input functions only for the address range FF2000 FF2FFFH 5 5 4 CodeFetches in the 64
177. 6NU External flash memory FF2080H 83C196NP Internal ROM 1 external memory EA 0 FF207FH Special purpose memory 80C196NP and 80C196NU External flash memory FF2000H far constants 83C196NP Internal ROM 1 external memory EA 0 FF1FFFH FF0100H External flash memory code or far constants FFOOFFH FF0000H Reserved FEFFFFH 010000H Unimplemented OOFFFFH 008000H 32 Kbyte external RAM near data 007FFFH 003000H Unimplemented 002FFFH 80C196NP and 80C196NU Unimplemented 002000H 83C196NP Program and special purpose memory remapped from internal ROM REMAP 1 EA 1 001FFFH 7 2 001F00H Internal peripheral special function registers SFRs 001EFFH 001C00H Unimplemented future SFR expansion 001BFFH 000400H Unimplemented 0003FFH 000100 Upper register file general purpose register RAM 0000FFH 5 000018H Lower register file general purpose register RAM and stack pointer 000017 000000H Lower register file CPU SFRs 5 28 l ntel MEMORY PARTITIONS 5 6 2 Example 2 A 64 Kbyte System with Additional Data Storage Figure 5 10 shows another system designed for operation in the 64 Kbyte mode Code executes from page FFH only This system is the same as the example in Example 1 Using the 64 Kbyte Mode on page 5 27 but with additional RAM The 64 Kbyte RAM stores near data in page 00H The 128 Kbyte RAM stores far data in page
178. 6NU USER S MANUAL intel Table 8 2 Serial Port Control and Status Registers Continued Mnemonic Address Description SP STATUS 1FB9H Serial Port Status This register contains the serial port status bits It has status bits for receive overrun errors OE transmit buffer empty TXE framing errors FE transmit interrupt receive interrupt RI and received parity error RPE or received bit 8 RB8 Reading SP STATUS clears all bits except TXE writing a byte to SBUF TX clears the TXE bit 8 3 SERIAL PORT MODES The serial port has both synchronous and asynchronous operating modes for transmission and re ception This section describes the operation of each mode 8 3 1 Synchronous Mode Mode 0 most common use of mode 0 the synchronous mode is to expand the I O capability of the device with shift registers see Figure 8 2 In this mode the TXD pin outputs a set of eight clock pulses while the RXD pin either transmits or receives data Data is transferred eight bits at a time with the least significant bit first Figure 8 3 shows a diagram of the relative timing of these sig nals Note that only mode 0 uses RXD as an open drain output Shift LOAD Clock Inhibit Shift Register 74HC165 Inputs 8XC196 Device Outputs Serial In A Shift Register 7AHC164 Enable A0264 02 Figure 8 2 Typical Shift Register Circuit for Mode 0 intel SERIAL 1 0 SIO
179. 6NU can operate at twice the frequency of the 8XC196NP therefore a state time for the 80C196NU is half that of the 8XC196NP These two factors combine to make the 80C196NU code execute in one fourth the time required for the 8XC196NP code 3 1 8XC196NP 80C196NU USER S MANUAL intel Table 3 1 Multiply Accumulate Example Code Device Instructions Execution Time 8XC196NP mul temp operand 2 operand 1 16 states 1280 ns 25 MHz 1 state time 80 ns temp 1 8 states 640 ns add 1 4 states 320 ns addc out h temp h 4 states 320 ns 32 states total 2560 ns total 80C196NU mul 08H operand 2 operand 1 16 states 640 ns 50 MHz 1 state time 40 ns 16 states total 640 ns total Because bit of the destination address 08H is set the 80C196NU clears the accumulator before adding the result of the current instruction to it If bit were clear destination address 07H 00H the 80C196NU would add the result of the current instruction to the existing value of the accumulator 3 2 OPERATING MODES The accumulator has two operating modes that allow you to control the results of operations on signed numbers These modes are called saturation mode and fractional mode 3 2 1 Saturation Mode Saturation occurs when the result of two positive numbers generates a negative sign bit or the re sult of two negative numbers generates a positive sign bit Without saturation mode an underflow or
180. 96NU USER S MANUAL intel 4 5 1 Using Registers The 256 byte lower register file contains the CPU special function registers and the stack pointer The remainder of the lower register file and all of the upper register file is available for your use Peripheral special function registers SFRs and memory mapped SFRs reside in higher memory The peripheral SFRs can be windowed into the lower register file for direct access Memory mapped SFRs cannot be windowed you must use indirect or indexed addressing to access them All SFRs can be operated as BYTEs or WORDS unless otherwise specified See Peripheral Special function Registers SFRs on page 5 7 and Register File on page 5 9 for more infor mation To use these registers effectively you must have some overall strategy for allocating them The C programming language adopts a simple effective strategy It allocates the eight or sixteen bytes beginning at address as temporary storage and treats the remaining area in the register file as a segment of memory that is allocated as required NOTE Using any SFR as a base or index register for indirect or indexed operations can cause unpredictable results because external events can change the contents of SFRs Also because some SFRs are cleared when read consider the implications of using an SFR as an operand in a read modify write instruction e g XORB 4 5 2 Addressing 32 bit Operands The 32 bit operands DOUBLE WORDs
181. A 10 1 FUNCTIONAL 7 10 1 vii 8XC196NP 80C196NU USER S MANUAL intel 10 2 EPA AND TIMER COUNTER SIGNALS AND 10 2 10 3 TIMER COUNTER FUNCTIONAL 1 eene 10 5 10 3 1 Cascade Mode Timer 2 Only 10 6 10 3 2 Quadrature Clocking Mode 10 6 10 4 EPA CHANNEL FUNCTIONAL 10 8 10 4 1 Operating Capture Mode 10 9 10 41 15 OVOGITUFIS iiie etit 10 11 10 4 1 2 Preventing EPA Overruns 10 12 10 4 2 Operating in Compare Mode 10 12 10 4 2 1 Generating a Low speed PWM Output 10 12 10 4 2 2 Generating a Medium speed PWM Output 10 13 10 4 2 3 Generating a High speed PWM Output sm 10 14 10 4 2 4 Generating the Highest speed PWM Output 10 15 10 5 PROGRAMMING THE EPA AND 0 10 15 10 5 1 Configuring the EPA and Timer Counter Port Pins 10 15 10 5 2 Programming the Timers nams TEE A 10518 10 5 3 P
182. A PEND registers decode these multiplexed interrupts Write to EPA MASK to enable the interrupt sources read EPA PEND to determine which source caused the interrupt Figure 6 8 Interrupt Pending 1 INT PEND1 Register 6 6 INITIALIZING THE PTS CONTROL BLOCKS Each PTS interrupt requires a block of data in register RAM called the PTS control block PTSCB The PTSCB identifies which PTS microcode routine will be invoked and sets up the specific parameters for the routine You must set up the PTSCB for each interrupt source before enabling the corresponding PTS interrupts 8XC196NP 80C196NU USER S MANUAL intel address of the first lowest PTSCB byte is stored in the PTS vector table in special purpose memory see Special purpose Memory on page 5 6 Figure 6 9 shows the PTSCB for each PTS mode Unused PTSCB bytes can be used as extra RAM NOTE The PTSCB must be located in the internal register file The location of the first byte of the PTSCB must be aligned on a quad word boundary an address evenly divisible by 8 Because the PTS uses nonextended addressing it cannot operate across page boundaries For example PTSSRC cannot point to a location on page 05 while PTSDST points to page 00 In the 8XC196NP all nonextended data accesses will operate from the page defined by EP REG For PTS routines write to REG to select page 00H see Accessing Data on page 5 23 The 80C196NU forces all
183. BIT is zero output 0 or T2 Gf TBIT is one output 1 Note that although the values of the EPAO output and TBIT are the same in this example these two values are unrelated To establish the initial value of the output set or clear REG x The PWM toggle mode has the advantage of using only one EPA channel However if the wave form edges are close together the PTS may take too long and miss setting up the next edge The PWM remap mode uses two EPA channels to eliminate this problem 6 6 5 2 PWM Remap Mode Example Figure 6 17 shows the PTS control block for PWM remap mode The following example uses two EPA channels and a single timer to generate a PWM waveform in PWM remap mode EPAO as serts the output and 1 deasserts it For each channel an interrupt is generated every T2 pe riod but the comparison times for the channels are offset by the on time T1 see Figure 6 14 on page 6 27 Although TBIT is toggled at the end of every PWM remap mode cycle see Table 6 7 on page 6 26 it plays no role in this mode To generate a PWM waveform follow this procedure 1 Disable the interrupts and the PTS The DI instruction disables all interrupts the DPTS instruction disables the PTS 2 Set up one PTSCB for EPAO and one for EPA1 as shown in Table 6 9 Note that the two blocks are identical except that PTSPTR1 points to EPAO TIME for EPAO and to 1 TIME for EPA1 3 Configure P1 1 to serve as the EPAT output
184. Bus Multiplexing on page 13 10 13 26 intel INTERFACING WITH EXTERNAL MEMORY When selecting infinite wait states be sure to add external hardware to count wait states and re lease READY within a specified period of time Otherwise a defective external device could tie up the address data bus indefinitely NOTE Ready control is valid only for external memory you cannot add wait states when accessing internal ROM Setup and hold timings must be met when using the READY signal to insert wait states into a bus cycle see Table 13 11 and Figures 13 13 through 13 15 Because a decoded valid address is used to generate the READY signal the setup time is specified relative to the address being valid This specification T yyy indicates how much time the external device has to decode the address and assert READY after the address is valid The READY signal must be held valid until the To yx timing specification is met Typically this is a minimum of 0 ns from the time CLKOUT goes low Do not exceed the maximum yy specification or additional unwanted wait states might be added In all cases refer to the datasheets for the current specifications for T yyy and Ter Table 13 11 READY Signal Timing Definitions Symbol Definition Address Valid Input Data Valid Maximum time the memory device has to output valid data after the device outputs a valid address Address Vali
185. C DEST source leftmost word operand into the ST wreg waop destination rightmost operand DEST lt SRC 110000aa waop wreg PSW Flag Settings Z N C V VT ST STB STORE BYTE Stores the value of the source SRC DEST leftmost byte operand into the destination erp breg baop rightmost operand 110001 baop breg PSW Flag Settings Z N C V VT ST SUB SUBTRACT WORDS Subtracts the source DEST SRC 2 operands word operand from the destination word SUB wreg waop operand stores the result in the destination operand and sets the carry flag as the complement of borrow DEST lt DEST SRC 011010aa waop wreg PSW Flag Settings 2 V 5 SUB SUBTRACT WORDS Subtracts the first DEST SRC1 SRC2 8 operands source word operand from the second stores SUB Dwreg Swreg waop the result in the destination operand and sets the carry flag as the complement of borrow 010010aa Swreg Dwreg DEST lt SRC1 SRC2 PSW Flag Settings 2 V VT ST 42 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format SUBB SUBTRACT BYTES Subtracts the source DEST SRC 2 operands byt
186. C196NP and 80C196NU This partition is in external memory external addresses F2080 F2FFFH 83C196NP The REMAP bit CCB1 2 the EA input and the type of instruction extended or nonextended control access to this partition as shown in Table 5 2 Table 5 2 Program Memory Access for the 83 196 REMAP CCB1 2 Pin Instruction Type Memory Location Accessed X Asserted Extended or nonextended External memory F2080 F2FFFH 0 Deasserted Extended or nonextended Internal ROM FF2080 FF2FFFH Extended Internal ROM FF2080 FF2FFFH 1 Deasserted Nonextended External memory 02080 02FFFH FF3000 FFFFFH in external memory external addresses F3000 FFFFFH NOTE We recommend that you write FFH the opcode for the RST instruction to unused program memory locations This causes a device reset if a program unintentionally begins to execute in unused memory 5 5 8XC196NP 80C196NU USER S MANUAL intel 5 2 2 2 Special purpose Memory Special purpose memory resides in locations 2000 207 It contains several reserved memory locations the chip configuration bytes CCBs and vectors for both peripheral transac tion server PTS and standard interrupts Note that the special purpose memory partition of the 80C196NU differs slightly from that of the 8XC196NP Table 5 3 describes the special purpose memory bold type highlights the differences Table 5 3 8XC196NP and 80C196NU
187. C196NU External flash memory FF2080H 83C196NP Internal ROM EA 1 external memory EA 0 FF207FH Special purpose memory 80C196NP and 80C196NU External flash memory FF2000H far constants 83C196NP Internal ROM EA 1 external memory EA 0 FF1FFFH FF0100H External flash memory code or far constants FFOOFFH Reserved FEFFFFH 030000H Unimplemented O2FFFFH 010000H 128 Kbyte external RAM far data OOFFFFH 003000H External RAM near data 002 80C196NP and 80C196NU External RAM 002000H 83C196NP External RAM CCB1 2 0 or remapped internal ROM CCB1 2 1 001FFFH 1 001F00H Internal peripheral special function registers SFRs 001EFFH 001C00H External RAM future SFR expansion 001BFFH 000400H External RAM near data 0003FFH 000100H Upper register file general purpose register RAM 0000FFH 000018H Lower register file general purpose register RAM and stack pointer 00001 7H 000000H Lower register file CPU SFRs 5 30 l ntel MEMORY PARTITIONS 5 6 3 Example 3 Using 1 Mbyte Mode Figure 5 11 shows a system designed for operation in the 1 Mbyte mode In this mode code can execute from any page in the 1 Mbyte memory space The system uses both 8 bit and 16 bit buses and uses the write strobe mode See Chapter 13 Interfacing with External Memory The 32Kx8 RAM stores near data in the upper half of page The 32
188. CLKOUT Note 1 Note 2 Note 1 active active 040 1 040 1 P3 0 50 WK1 1 NP only Note 3 Note 3 Note 4 0 NU only P3 5 1 55 1 WK1 WK1 Note 3 Note 3 Note 4 P3 6 EXTINT2 WK1 WK1 Note 1 Note 1 Note 1 P3 7 WK1 WK1 Note 1 Note 1 Note 1 P4 2 0 PWM2 0 WK1 WK1 Note 1 Note 1 Note 1 D 8 196 80C196NU USER S MANUAL Table B 5 8XC196NP and 80C196NU Pin Status Continued Power During Upon down Multiplexed RESET NP NU Bus Port Pins With pos Inactive Idle and Hold Idle Note 11 Standby NU only P4 3 WK1 WK1 Note 1 Note 1 Note 1 EPORT 3 0 A19 16 WK1 1 Note 5 Note 5 Note 6 Note 8 A15 0 WK1 10270 Note 7 7 HiZ 10270 AD15 0 WK1 040 Note 7 Note 7 HiZ 10270 ALE WKO 0 Note 9 Note 9 WKO Lozo BHE WK1 1 Note 10 Note 10 WK1 LoZ1 EAst HiZ HiZ HiZ HiZ HiZ NP only INST WKO 0 Note 9 Note 9 WKO 040 NMI WKO WKO WKO WKO WKO ONCE MDO MDO MDO MDO MDO PLLEN1 HiZ HiZ HiZ HiZ HiZ NU only PLLEN2 MDO MDO MDO MDO MDO NU only RD WK1 1 Note 10 Note 10 WK1 LoZ1 READY WK1 WK1 WK1 WK1 WK1 RESET 0 WK1 WK1 WK1 WK1 RPD LoZ1 LoZ1 LoZ1 LoZ1 LoZ1 WR WK1 1 Note 10 Note 10 WK1 LoZ1 XTALI m Osc input Oscinput Oscinput Osc in
189. Chapter 4 Programming Considerations provides an overview of the instruction set de scribes general standards and conventions and defines the operand types and addressing modes supported by the MCS 96 microcontroller family For additional information about the instruc tion set see Appendix A Chapter 5 Memory Partitions describes the addressable memory space of the device It describes the memory partitions explains how to use windows to increase the amount of memory that can be accessed with direct addressing and provides examples of memory configurations Chapter 6 Standard and PTS Interrupts describes the interrupt control circuitry priority scheme and timing for standard and peripheral transaction server PTS interrupts It also ex plains interrupt programming and control Chapter 7 I O Ports describes the input output ports and explains how to configure the ports for input output or special functions 1 1 8XC196NP 80C196NU USER S MANUAL intel Chapter 8 Serial I O SIO Port describes the asynchronous synchronous serial I O SIO port and explains how to program it Chapter 9 Pulse width Modulator provides a functional overview of the pulse width mod ulator PWM modules describes how to program them and provides sample circuitry for con verting the PWM outputs to analog signals Chapter 10 Event Processor Array EPA describes the event processor array a t
190. Clock Prescaler These bits control the PWM output period on the three pulse width modulators 2 CLK1 CLKO 0 0 disable clock prescaler 0 1 enable divide by two prescaler PWM output period is 1024 state times 1 X enable divide by four prescaler PWM output period is 2048 state times t This bit was called SLOW PWM in earlier documentation for the 8XC196NP 8 196 80C196NU USER S MANUAL EP DIR intel EP DIR 80C196NU 7 Address Reset State 1FE3H FFH In I O mode each bit of the extended port I O direction DIR register controls the direction of the corresponding pin Clearing a bit configures a pin as a complementary output setting a bit configures a pin as either an input or an open drain output Open drain outputs require external pull ups Any pin that is configured for its extended address function is forced to the complementary output mode except during reset hold idle powerdown and standby Standby mode is available only on the 2 PIN1 PINO Bit Bit Number Mnemonic Function 7 4 Reserved always write as ones 3 0 0 Extended Address Port Pin x Direction This bit configures EPORT x as a complementary output or an input open drain output 0 complementary output 1 input or an open drain output intel REGISTERS EP
191. D AND PTS INTERRUPTS This chapter describes the interrupt control circuitry priority scheme and timing for standard and peripheral transaction server PTS interrupts It discusses the three special interrupts and the four PTS modes two of which are used with the EPA to produce pulse width modulated PWM out puts It also explains interrupt programming and control 6 1 OVERVIEW OF INTERRUPTS The interrupt control circuitry within a microcontroller permits real time events to control pro gram flow When an event generates an interrupt the device suspends the execution of current instructions while it performs some service in response to the interrupt When the interrupt is ser viced program execution resumes at the point where the interrupt occurred An internal periph eral an external signal or an instruction can generate an interrupt request In the simplest case the device receives the request performs the service and returns to the task that was interrupted This microcontroller s flexible interrupt handling system has two main components the pro grammable interrupt controller and the peripheral transaction server PTS The programmable interrupt controller has a hardware priority scheme that can be modified by your software Inter rupts that go through the interrupt controller are serviced by interrupt service routines that you provide The upper and lower interrupt vectors in special purpose memory see Chapter 5 Memory P
192. D1 registers When the vector is taken the hardware clears the pending bit Software can generate an interrupt by setting the corresponding interrupt pending bit 7 0 EPAO RI TI EXTINT1 EXTINTO OVRTM2 OVRTM1 Bit Number Function 7 3 Any set bit indicates that the corresponding interrupt is pending The interrupt bit is 1 0 cleared when processing transfers to the corresponding interrupt vector The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector EPAO EPA Capture Compare Channel 0 FF200EH RI SIO Receive FF200CH TI SIO Transmit FF200AH EXTINT1 FF2008H EXTINTO EXTINTO pin FF2006H OVRTM2 Timer 2 Overflow Underflow FF2002H OVRTM1 Timer 1 Overflow Underflow FF2000H 2 Reserved This bit is undefined C 27 8XC196NP 80C196NU USER S MANUAL intel INT PEND1 INT PEND1 Address 0012H Reset State 00H When hardware detects a pending interrupt it sets the corresponding bit in the interrupt pending INT PEND or INT PEND1 registers When the vector is taken the hardware clears the pending bit Software can generate an interrupt by setting the corresponding interrupt pending bit 7 0 NMI EXTINT3 EXTINT2 OVR2 3 OVRO 1 EPA3 EPA2 EPA1 Bit Number Function 7 0 Any set bit indicates that the corresponding interrupt is pending The interrupt bit is cleared when processing t
193. DBZE LOAD BYTE ZERO EXTENDED Zero DEST SRC extends the value of the source byte operand DBZE wreg baop and loads it into the destination word operand 101011aa baop wreg low byte DEST lt SRC high byte DEST lt 0 PSW Flag Settings Z N C V VT ST LJMP LONG JUMP Adds to the program counter LJMP cadd 11100111 disp low disp high NOTE The displacement disp is sign extended to 24 bits in the 1 Mbyte addressing mode This displace ment may cause the program counter to cross a page boundary A 28 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format MUL MULTIPLY INTEGERS Multiplies the source DEST SRC 2 operands and destination integer operands using MUL Ireg waop signed arithmetic and stores the 32 bit result into the destination long integer operand The sticky bit flag is undefined after the instruction is executed DEST lt DEST x SRC PSW Flag Settings Z N C v VT ST 11111110 011011aa waop Ireg MUL 8 operands MULTIPLY INTEGERS Multiplies the two Source integer operands using signed arithmetic and stores the 32 bit result into the destination long integer operand The Sticky bit flag is undefined after the instruction is executed DEST lt SRC1 x SRC2 PSW Flag Settings 7 VT ST
194. DI EI DPTS EPTS POPA POPF PUSHA and PUSHF Glossary 5 8XC196NP 80C196NU USER S MANUAL intel PSW PTS PTSCB PTS control block PTS cycle PTS interrupt PTS mode PTS routine PTS transfer PTS vector QUAD WORD RALU Glossary 6 Processor status word The high byte of the PSW is the status byte which contains one bit that globally enables or disables servicing of all maskable interrupts one bit that enables or disables the PTS and six Boolean flags that reflect the state of the current program The low byte of the PSW is the INT MASK register A push or pop instruction saves or restores both bytes PSW INT MASK Peripheral transaction server microcoded hardware interrupt processor See PTS control block A block of data required for each PTS interrupt microcode executes the proper PTS routine based on the contents of the PTS control block The microcoded response to a single PTS interrupt request Any maskable interrupt that is assigned to the PTS for interrupt processing A microcoded response that enables the PTS to complete a specific task quickly These tasks include transferring a single byte or word transferring a block of bytes or words and generating PWM outputs The entire microcoded response to multiple PTS interrupt requests The PTS routine is controlled by the contents of the PTS control block The movement of a single byte or word from the source memor
195. DIR register determines the I O direction for each port x pin The register settings for an open drain output or a high impedance input are identical An open drain output configuration requires an external pull up A high impedance input configuration requires that the corresponding bit in Px REG be set This bit selects the Px y direction 0 complementary output output only 1 input or open drain output input output or bidirectional Open drain outputs require external pull ups 7 0 1 3 6 5 4 PIN2 PIN1 PINO 7 0 x 4 PIN3 PIN2 PIN1 PINO Bit Bit Number Mnemonic Function 7 0 PIN7 0 Port x Pin y Direction C 30 Table C 10 Px_DIR Addresses and Reset Values Register Address Reset Value P1_DIR 1FD2H FFH P2_DIR 1FD3H FFH P3_DIR 1FDAH FFH P4_DIR 1FDBH FFH intel REGISTERS Px MODE Px MODE Address Table C 11 x 14 Reset State Each bit of the port x mode Px_MODE register controls whether the corresponding pin functions as a standard I O port pin or as a special function signal 7 0 xz1 3 PIN7 6 PIN5 PIN4 PINS PIN2 PIN1 PINO 7 0 x 4 PIN3 PIN2 PIN1 PINO ra oe Mons Function 7 0 PIN7 0 Port x Pin y Mode This bit determines the mode of the corres
196. DLPD 4key causes the device 11110110 key to enter idle mode 1 to enter powerdown mode KEY 2 to enter standby mode 3 NU only to execute a reset sequence KEY any value other than 1 or 2 NP or 1 2 or 3 NU The bus controller completes any prefetch cycle in progress before the CPU stops or resets if KEY 1 then enter idle else if KEY 2 then enter powerdown else if KEY 3 then enter standby NU only else execute reset PSW Flag Settings Z N C V VT ST KEY 1 or 2 NP or 1 2 or 3 NU KEY any value other than 1 or 2 NP or 1 2 or 3 NU 0 0 0 0 0 0 A 20 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format INC INCREMENT WORD Increments the value of the word operand by 1 DEST lt DEST 1 PSW Flag Settings 2 V VT ST V viv iv11ft10 INC wreg 00000111 wreg INCB INCREMENT BYTE Increments the value of the byte operand by 1 DEST DEST 1 PSW Flag Settings 2 V VT ST Vi ivi I7111 INCB breg 00010111 breg JBC JUMP IF BIT IS CLEAR Tests the specified bit If the bit is set control passes to the next sequential instruction If the bit is clear this instruction adds to the program counte
197. E PTS Enable This bit globally enables or disables the peripheral transaction server PTS The EPTS instruction sets this bit DPTS clears it 1 enable PTS 0 disable PTS 1 Interrupt Disable Global This bit globally enables or disables the servicing of all maskable interrupts The bits in INT MASK and INT 5 individually enable or disable the interrupts The EI instruction sets this bit DI clears it 1 enable interrupt servicing 0 disable interrupt servicing 0 ST Sticky Bit Flag This flag is set to indicate that during a right shift a 1 was shifted into the carry flag and then shifted out It can be used with the carry flag to allow finer resolution in rounding decisions C 35 8 196 80C196NU USER S MANUAL PTSSEL intel PTSSEL Address Reset State 0004H 0000H The PTS select PTSSEL register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt request Setting a bit selects a PTS microcode routine clearing a bit Selects a standard interrupt service routine When PTSCOUNT reaches zero hardware clears the corresponding PTSSEL bit The PTSSEL bit must be set manually to re enable the PTS channel The PTS interrupt vector locations are as follows Bit Mnemonic EXTINT3 EXTINT2 OVR2 31 OVRO 1 EPA3 EPA2 EPA1 EPAO RI EXTINTO
198. E WORD EDAR EPA EPC EPORT ESD external address far constants Glossary 2 The integrated module that selects an external memory device during an external bus cycle The 0 value of a bit or the act of giving it a 0 value See also set The act of making a signal inactive disabled The polarity high or low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To deassert RD is to drive it high to deassert ALE is to drive it low The configuration in which the device uses separate lines for address and data address on A19 0 data on AD15 0 for 16 bit bus or AD7 0 for an 8 bit bus See also multiplexed bus The process of introducing a periodic table Group III or Group V element into a Group IV element e g silicon A Group III impurity e g indium or gallium results in a p type material A Group V impurity e g arsenic or antimony results in an n type material Any 32 bit unit of data An unsigned 32 bit variable with values from 0 through 2321 Extended data address register used by the EPORT Event processor array An integrated peripheral that provides high speed input output capability Extended program counter used by the EPORT Extended addressing port The port that provides the additional address lines to support extended addressing Electrostatic discharge A 20 bit address is presented
199. E y 1 the associated on chip peripheral or off chip component controls the pin The CPU can still write to P1_REG but the pin is unaffected until it is switched back to its standard I O function This feature allows software to configure a pin as standard clear P1 MODE y initialize or overwrite the pin value then configure the pin as a special function signal set P1 MODE y In this way initialization fault recovery exception handling etc can be done without changing the operation of the associated peripheral T1CONTROL 1F90H Timer 1 Control This register enables disables timer 1 controls whether it counts up or down selects the clock source and direction and determines the clock prescaler setting T2CONTROL 1F94H Timer 2 Control This register enables disables timer 2 controls whether it counts up or down selects the clock source and direction and determines the clock prescaler setting TIMER1 1F92H Timer 1 Value This register contains the current value of timer 1 TIMER2 1F96H Timer 2 Value This register contains the current value of timer 2 10 4 intel EVENT PROCESSOR ARRAY EPA 10 3 TIMER COUNTER FUNCTIONAL OVERVIEW The EPA has two 16 bit up down timer counters timer 1 and timer 2 which can be clocked in ternally or externally Each is called a timer if it is clocked internally and a counter if it is clocked externally Figure 10 2 illustrates the timer c
200. EPA interrupts are OVRTM1 OVRTM2 and EPAO INT PEND1 0012H Interrupt Pending 1 Any set bit in this 8 bit register indicates a pending interrupt The five bits associated with EPA interrupts are EPA1 EPA2 EPAS OVRO 1 and OVR2 3 P1 DIR 1FD2H Port 1 Direction Each bit of P1_DIR controls the direction of the corresponding pin Clearing a bit configures a pin as a complementary output setting a bit configures a pin as an input or open drain output Open drain outputs require external pull ups 10 3 8XC196NP 80C196NU USER S MANUAL intel Table 10 2 EPA Control and Status Registers Continued Mnemonic Address Description P1 MODE 1FDOH Port 1 Mode Each bit of P MODE controls whether the corresponding pin functions as a standard l O port pin or as a special function signal Setting a bit configures a pin as a special function signal clearing a bit configures a pin as a standard I O port pin P1 PIN 1FD6H Port 1 Input Each bit of P1 PIN reflects the current state of the corresponding pin regardless of the pin configuration P1 REG 1FD4H Port 1 Data Output For an input set the corresponding P1_REG bit For an output write the data to be driven out by each pin to the corresponding bit of P1_REG When a pin is configured as standard I O P1_MODE y 0 the result of a CPU write to Px_REG is immediately visible on the pin When a pin is configured as a special function signal P1_MOD
201. EPA1 7 0 EPAO RI TI EXTINT1 EXTINTO OVRTM2 OVRTM1 Bit Number Function 15 2 Reserved for compatibility with future devices write zero to this bit 14 8 Setting a bit causes the corresponding interrupt to be handled by a PTS microcode 1 0 routine The PTS interrupt vector locations are as follows Bit Mnemonic Interrupt PTS Vector EXTINT3 EXTINTS FF205CH EXTINT2 EXTINT2 pin FF205AH OVR2 31 EPA Capture Channel 2 or 3 Overrun FF2058H OVRO 1 EPA Capture Channel 0 or 1 Overrun FF2056H 3 2054 2 2 2052 1 1 2050 0 204 RI SIO Receive FF204CH TI SIO Transmit FF204AH EXTINT1 FF2048H EXTINTO EXTINTO pin FF2046H OVRTM2 Timer 2 Overflow Underflow FF2042H OVRTM1 Timer 1 Overflow Underflow FF2040H PTS service is not recommended because the PTS cannot determine the source of shared interrupts Figure 6 4 PTS Select PTSSEL Register 6 5 1 Programming Considerations for Multiplexed Interrupts An overrun on the EPA capture compare channels can generate the multiplexed capture overrun interrupts OVRO 1 and OVR2_3 Write to the EPA_MASK Figure 10 11 on page 10 22 reg ister to enable or disable the multiplexed interrupt sources and the I
202. EPA1 CON and CON must be addressed as words while the others can be addressed as bytes 15 8 x 1 3 EY RM 7 0 TB CE M1 MO RE ROT ON RT 7 0 0 2 1 MO RE ROT ON RT Bit Bit Number Mnemonic Funetion 15 97 Reserved always write as zeros 8t RM Remap Feature The remap feature applies to the compare mode of the EPA1 and EPA3 only When the remap feature of EPA1 is enabled EPA capture compare channel 0 shares output pin EPA1 with EPA capture compare channel 1 When the remap feature of EPA3 is enabled EPA capture compare channel 2 shares output EPA3 with EPA capture compare channel 3 0 remap feature disabled 1 2 remap feature enabled 7 TB Time Base Select Specifies the reference timer 0 timer 1 is the reference timer and timer 2 is the opposite timer 1 timer 2 is the reference timer and timer 1 is the opposite timer A compare event clearing setting or toggling an output pin and or resetting either timer occurs when the reference timer matches the time programmed in the event time register When a capture event falling edge rising edge or an edge change on the EPAx pin occurs the reference timer value is saved in the EPA event time register EPAx TIME 6 CE Compare Enable Determines whether the EPA channel operates in capture or compare mode 0 capture mode 1 compare mode These bits apply to the EPA1 C
203. Effect of PSW Flags or Specified Conditions on Conditional Jump Instructions XV 8XC196NP 80C196NU USER S MANUAL intel Table 4 5 7 8 1 2 4 5 2 C 3 C 5 C 6 C 7 C 8 C 9 C 10 C 11 C 12 C 13 C 14 C 15 C 16 C 17 C 18 C 19 xvi TABLES Page PSW Flag Setting 5 Operand Variables nro sianie eno ACB Instruction ue aee Re RITE E IE Anu beset men eb A 7 Instruction Opcodes ie intended in Rae rip A 47 Instruction Lengths and Hexadecimal Opcodes esee A 53 Instruction Execution Times in State Times eee 60 8XC196NP and 80C196NU Signals Arranged by 1 Description of Columns of Table 3 B 6 Signal Descriptioris 2 3 11 eet ER Ure Ee ee cede B 6 Definition of Status Symbols Seren Le Ree ee tee so ron fe B 13 8XC196NP and 80C196NU Pin Status sesseeeeeeemnn B 13 Modules and Related Registers eene eene C 1 Register Name Address and Reset O72 0x Addresses and Reset 0 4000 5 Ef
204. FFFH is directed to internal ROM FF2000 FF2FFFH if EA is high and to external memory 2000 2 if EA is low In either case data in this area must be accessed with extended instructions With remapping enabled CCB1 2 1 and EA high you can access the contents of 2000 FF2FFFH in two ways in internal ROM FF2000 FF2FFFH using an extended instruction in external memory 002000 002 using a nonextended instruction This makes the far data in FF2000 FF2FFFH accessible as near data With remapping enabled CCB 1 2 1 and EA low you can access the contents of 2000 FF2FFFH in external memory F2000 F2FFFH using an extended instruction An advantage of remapping ROM is that it makes the data in ROM accessible as near data in ex ternal memory page 00H The data can then be accessed more quickly with nonextended instruc tions An advantage of not remapping ROM is that the corresponding area in external memory page 00H is available for storing additional near data 5 22 l ntel MEMORY PARTITIONS 5 5 FETCHING CODE AND DATA IN THE 1 AND 64 KBYTE MODES This section describes how the device fetches instructions and accesses data in the 1 Mbyte and 64 Kbyte modes When the device leaves reset the MODE64 bit CCB1 1 selects the 1 Mbyte or 64 Kbyte mode The mode cannot be changed until the next reset NOTE The 8XC196NP and 80C196NU have two major differences concerning code and data
205. FH 001FFFH Peripheral SFRs 001F00H 001EFFH External Memory pde uture Expansion 001C00H 001BFFH External Memory 000400H 0003FFH Upper Register File FF0100H 000100H FFOOFFH 0000FFH Reserved Lower Register File FF0000H 000000H A2462 03 Figure 5 2 Pages FFH and 00H 5 2 MEMORY PARTITIONS Table 5 1 is a memory map of the 8XC196NP and 80C196NU The remainder of this section de scribes the partitions 8XC196NP 80C196NU USER S MANUAL intel Table 5 1 8XC196NP and 80C196NU Memory Map Hex J Address Description Addressing Modes FFFFFF External device memory or I O connected to address data indiractimdosed extended 000 bus FF2FFF Program memory Note 1 FF2080 After a device reset the first instruction fetch is from FF2080H Indirect indexed extended or F2080H in external memory FF207F FF2000 Special purpose memory Note 1 Indirect indexed extended FF1FFF External device memory or I O connected to address data Indirect indexed extended FF0100 bus FFOOFF FF0000 Reserved Note 2 EN FEFFFF lai i Te m 0 0000 Overlaid memory 0000 00 are reserve ndirect indexed extende OEFFFF External device memory I O connected to address data inatraet indexed extended 010000 bus OOFFFF External device memory or I O connected to address data Indirect indexed extended 003000 bus 002FFF Ex
206. Fetches in the 1 Mbyte Mode seseee emen 5 25 5 5 4 Code Fetches in the 64 Kbyte Mode seem 5 25 5 5 5 Data Fetches in the 1 Mbyte and 64 Kbyte Modes 5 26 5 6 MEMORY CONFIGURATION EXAMPLES D72 f 5 6 1 Example 1 Using the 64 Kbyte Mode seem 5 27 5 6 2 Example 2 64 Kbyte System with Additional Data Storage 5 29 5 6 3 Example 3 Using 1 Mbyte Mode 2 5 31 8XC196NP 80C196NU USER S MANUAL intel CHAPTER 6 STANDARD AND PTS INTERRUPTS 6 1 OVERVIEW OF INTERRUPT S sennecesa aran iipasi revi tenen nennen nen nnns 6 1 6 2 INTERRUPT SIGNALS AND REGISTERS eee emen 6 3 6 3 INTERRUPT SOURCES AND PRIORITIES esee Hem 6 4 6 3 1 Special Interrupts eto tte 6 4 6 3 1 1 Unimplemented Opcode 6 5 6 3 2 Software sei bei neste Feet ev cta ics 6 5 6 32 13 NM i erc e Cre Le re Eee ere IE Perret rue hv a Pape 6 6 6 3 2 External Interrupt PINS rm e ite ee eet ue dade ead 6 6 6 3 3 Multiplexed Interrupt Sources 6 6 6 3 4 End of PTS Interr pts uec cote tc e pee dn i cete re dn e e te 6 6 6 4 INTERRUPT LATENCY ike 6 4 1 Situations that Interrupt Latency A donee 6 7 6 4 2 Calculating Latency 2 4 e
207. For an output write the data to be driven out by each pin to the corresponding bit of Px REG When a pin is configured as standard I O Px MODE y 0 the result of a CPU write to Px REG is immediately visible on the pin When a pin is configured as a special function signal Px MODE y 1 the associated on chip peripheral or off chip component controls the pin The CPU can still write to Px REG but the pin is unaffected until it is switched back to its standard I O function This feature allows software to configure a pin as standard clear MODE initialize or overwrite the pin value then configure the pin as a special function signal set Px MODE y In this way initialization fault recovery exception handling etc can be done without changing the operation of the associated peripheral 12 2 REDUCING POWER CONSUMPTION Each power saving mode conserves power by disabling portions of the internal clock circuitry Figure 12 1 and Figure 12 2 The following paragraphs describe each mode in detail 12 8 8 196 80C196NU USER S MANUAL Disable Clock Input Powerdown F XTAL1 Divide by two XTALI g Circuit Disable Clocks Powerdown XTAL2 Clock Disable Generators Oscillator Powerdown Disable Clocks Idle Powerdown Peripheral Clocks PH1 PH2 JcLkouT CPU Clocks PH1 PH2 161 01 Figure 12 1 12 4 Clock Control During Power saving Modes
208. GREATER THAN Tests both the zero flag and the negative flag If JGT cadd either flag is set control passes to the next sequential instruction If both flags are clear 11010010 disp this instruction adds to the program counter the offset between the end of this instruction NOTE The displacement disp is sign and the target label effecting the jump The extended to 24 bits offset must be in the range of 128 to 127 if N 0 AND Z 0 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JH JUMP IF HIGHER UNSIGNED Tests both the zero flag and the carry flag If either the JH cadd carry flag is clear or the zero flag is set i control passes to the next sequential 11011001 disp instruction If the carry flag is set and the zero flag is clear this instruction adds to the NOTE The displacement disp is sign program counter the offset between the end extended to 24 bits of this instruction and the target label effecting the jump The offset must be in range of 128 to 127 if C 1 AND Z 0 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JLE JUMP IF SIGNED LESS THAN OR EQUAL Tests both the negative flag and the zero flag JLE cadd If both flags are clear control passes to the next instruction If either flag is set 11011010 disp this instruction adds to the program coun
209. IONS This listing shows the disassembled code 2080H C814 PUSH WSR 2082H B14814 LDB WSR 48H 2085H 244 2 0 ADD EOH E2H E4H 2089H B21814 LDB WSR SP 208CH 65020018 ADD SP 02H 2090H FO RET 2091H 814 PUSH WSR 2093H B14814 LDB WSR 48H 2096H AAEAE8E6 ADD E6H E8H EAH 209AH B21814 LDB WSR SP 209DH 65020018 ADD SP 402H 20A1H FO RET The C compiler can also take advantage of this feature if the windows switch is enabled For details see the MCS 96 microcontroller architecture software products in the Development Tools Handbook 5 3 3 Windowing and Addressing Modes Once windowing is enabled the windowed locations can be accessed both through the window using direct addressing and through its actual address using indirect or indexed addressing The lower register file locations that are covered by the window are always accessible by indirect or indexed operations To re enable direct access to the entire lower register file clear bits 6 0 of the window selection register To enable direct access to a particular location in the lower register file you may select a smaller window that does not cover that location When windowing is enabled a direct instruction that uses an address within the lower register file actually accesses the window in the upper register file anindirect or indexed instruction that uses an address within either the lower register
210. Indexed Addressing seen 4 10 4 24 4 Zero indexed Addressing 2 4 10 4 2 4 5 Extended Zero indexed Addressing 2 4 10 4 3 ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS ese 4 11 4 8 1 Direct Addiessing iere Totti teat teeth C ve ade xri dg aad 4 11 4 3 2 Indexed Addressing ceteri 4 11 4 3 3 Extended Addressing s ect et d e ede e UR 4 11 4 4 DESIGN CONSIDERATIONS FOR 1 4 11 4 5 SOFTWARE STANDARDS AND CONVENTIONS eee eme 4 11 intel CONTENTS 4 5 1 Using Registers Je d IP 4 5 2 Addressing 32 bit Operands a 4 5 8 X Addressing 64 bit Operands 2 4 12 4 5 4 Linking SUBOUTINGS sisri itia aoreet in e e ERO tee bera 4 13 4 6 SOFTWARE PROTECTION FEATURES AND GUIDELINES 4 14 CHAPTER 5 MEMORY PARTITIONS 5 1 MEMORY eee ecc eh ec needed 5 2 MEMORY PARTITIONS enpa iet he seid sath aee odi S dede inde 5 8 5 2 1 External Memory isses Pie ERG RTI PN X e C EUR 5 2 2 Program and Spacial p purpose Memory poc SE Re TM DE 5 5 5 2 2 1 Program Memory in Page 5 5 5 2 2 2 Special purpose Memory 5 6 5 2 2
211. Kbyte Mode 1 the MODE64 bit controls whether the device operates in 1 Mbyte or 64 Kbyte mode is loaded with the contents of CCBI at reset When MODE64 is set the device operates in 64 Kbyte mode In this mode the EPC Figure 5 7 on page 5 23 is fixed at FFH which allows instructions to execute from page FFH only Extended jump branch and call instructions do not function in the 64 Kbyte mode 5 25 8XC196NP 80C196NU USER S MANUAL intel Code fetches are from external memory or internal memory depending on the device the mem ory location and the value of the EA input 80C196NU Code executes from page OFH in external memory The 80C196NU has no EA input 80C196NP For devices without internal nonvolatile memory EA must be tied low and code executes only from page in external memory 83C196NP Code in all locations except FF2000 FF2FFFH executes from external memory Instruction fetches from FF2000 FF2FFFH are controlled by the EA input f EA is low code executes from external memory page f EAf is high code executes from internal ROM page FFH 5 5 5 Data Fetches in the 1 Mbyte and 64 Kbyte Modes Data fetches are the same in the 1 Mbyte and 64 Kbyte modes The device can access data in any page Data accesses to page 00H are nonextended Data accesses to any other page are extended NOTE This information on data fetches applies only for EP REG 00H 80C196NP an
212. LD is removed You must enable the bus hold protocol before using this signal see Enabling the Bus hold Protocol on page 13 32 BREQ is multiplexed with P2 3 CLKOUT Clock Output Output of the internal clock generator The CLKOUT frequency is internal operating frequency f has a 50 duty cycle CLKOUT is multiplexed with P2 7 55 0 Chip select Lines 0 5 The active low output CSx is asserted during an external memory cycle when the address to be accessed is in the range programmed for chip select x If the external memory address is outside the range assigned to the six chip selects no chip select output is asserted and the bus configuration defaults to the 55 values Immediately following reset 50 is automatically assigned to the range FF2000 FF20FFH F2000 F20F FH if external 55 0 is multiplexed with P3 5 0 8XC196NP 80C196NU USER S MANUAL intel Table B 3 Signal Descriptions Continued Name Type Description NP only External Access This input determines whether memory accesses to special purpose and program memory partitions FF2000 FF2FFFH are directed to internal or external memory These accesses are directed to internal memory if EA is held high and to external memory if EA is held low For an access to any other memory location the value of EA is irrelevant is not latched and can be switched dynamically during normal operati
213. MANUAL intel SBUF TX SBUF TX Address 1FBAH z Reset State 00H The serial port transmit buffer register contains data that is ready for transmission In modes 1 2 and 3 writing to SBUF TX starts a transmission In mode 0 writing to SBUF TX starts a transmission only if the receiver is disabled SP 0 7 0 Data to Transmit Bit Number Function 7 0 Data to Transmit This register contains a byte of data to be transmitted by the serial port C 40 intel REGISTERS SP SP 18H XXXXH The system s stack pointer SP can point anywhere in an internal or external memory page it must be word aligned and must always be initialized before use The stack pointer is decremented before a PUSH and incremented after a POP so the stack pointer should be initialized to two bytes in 64 Kbyte mode or four bytes in 1 Mbyte mode above the highest stack location If stack operations are not being performed locations 18H and 19H may be used as standard registers 15 8 Stack Pointer high byte 7 0 Stack Pointer low byte 1 Function 15 0 Stack Pointer This register makes up the system s stack pointer C 41 8XC196NP 80C196NU USER S MANUAL intel SP BAUD SP BAUD Address 1FBCH Reset State 0000H The serial port baud rate SP BAUD register selects the serial port baud rate and clock source The most significant bit sel
214. MASK15 MASK14 MASK13 MASK12 MASK11 MASK10 MASK9 MASK8 Bit Bit Function 15 12 Reserved for compatibility with future devices write zeros to these bits 11 0 MASK19 8 Address Mask Bits For a 2 byte address range set the n most significant bits of MASK19 8 where n 20 n 13 8 Figure 13 3 Address Mask ADDRMSK x Register Table 13 5 ADDRMSKx Addresses and Reset Values Register Address Reset Value ADDRMSKO 1F42H XFFFH ADDRMSK1 1 XFFFH ADDRMSK2 1F52H XFFFH ADDRMSK3 1F5AH XFFFH ADDRMSK4 1F62H XFFFH ADDRMSK5 1F6AH XFFFH intel INTERFACING WITH EXTERNAL MEMORY Observe the following restrictions in choosing an address range for a chip select output The addresses in the address range must be contiguous The size of the address range must be 2 bytes where n 8 9 20 This corresponds to block sizes of 256 bytes 512 bytes 1 Mbyte The base address of a 2 byte address range must be on a 2 byte boundary that is the base address must be evenly divisible by 27 For example the base address of 256 Kbyte range must be 00000H 40000H 80000H or C0000H Table 13 6 shows the base addresses for some address range sizes address ranges for different chip selects must not overlap unless their BUSCONx parameters wait states bus width and multiplexing have the same values If BUSCONx
215. MODE EP MODE Address 1FE1H Reset State FFH Each bit of the extended port mode MODE register controls whether the corresponding pin functions as a standard l O port pin or as an extended address signal Setting a bit configures a pin as an extended address signal clearing a bit configures a pin as a standard I O port pin 7 0 2 PIN1 PINO Bit Bit Function Number Mnemonic uneto 7 4 Reserved always write as zeros 3 0 0 Extended Address Port Pin x Mode This bit determines the mode of EPORT x 0 standard port pin 1 extended address signal 8 196 80C196NU USER S MANUAL EP PIN intel EP PIN Address Reset State 1FE7H XXH Each bit of the extended port input EP register reflects the current state of the corresponding pin regardless of the pin configuration 7 0 2 emen Function 7 4 Reserved always write as zeros 3 0 0 Extended Address Port Pin x Input This bit contains the current state of EPORT x intel REGISTERS EP REG EP REG Address 1FE5H Reset State Each bit of the extended port data output REG register contains data to be driven out by the corresponding pin When pin is configured as standard MODE x 0 the result o
216. ND1 0012H The bits in this register are set by hardware to indicate that an interrupt is pending PSW No direct access Processor Status Word This register contains one bit that globally enables or disables servicing of all maskable interrupts and another that enables or disables the PTS These bits are set or cleared by executing the enable interrupts El disable interrupts DI enable PTS EPTS and disable PTS DPTS instructions PTSSEL 0004H 0005H PTS Select Register This register selects either a PTS routine or a standard interrupt Service routine for each of the maskable interrupt requests PTSSRV 0006H 0007H PTS Service Register The bits in this register are set by hardware to request an end of PTS interrupt 6 3 INTERRUPT SOURCES AND PRIORITIES Table 6 3 lists the interrupts sources their default priorities 30 is highest and 0 is lowest and their vector addresses The unimplemented opcode and software trap interrupts are not priori tized they go directly to the interrupt controller for servicing The priority encoder determines the priority of all other pending interrupt requests NMI has the highest priority of all prioritized interrupts PTS interrupts have the next highest priority and standard interrupts have the lowest The priority encoder selects the highest priority pending request and the interrupt controller se lects the corresponding vector location in special purpose memory Th
217. NP 5 2 5 5 5 22 5 25 REMAP bit 5 22 RPD 12 2 B 11 RST instruction 4 14 11 9 11 11 A 3 A 36 A 52 A 59 A 67 RXD 8 2 B 11 and SIO port mode 0 8 4 8 5 and SIO port modes 1 2 and 3 8 6 S Sampled input B 6 SBUF RX C 51 C 54 SBUF TX C 51 C 54 SCALL instruction A 3 A 36 A 47 A 53 A 57 A 64 A 65 Index 9 8 196 80C196NU USER S MANUAL Serial I O port See SIO port Set defined 1 3 SETC instruction 3 A 36 A 52 59 A 67 SFRs and idle mode 12 5 and powerdown mode 12 7 CPU 5 12 table of 5 12 peripheral 5 7 and windows 5 13 table of 5 8 reserved 4 12 5 9 with indirect or indexed operations 4 12 5 9 with read modify write instructions 5 7 Shift instructions A 59 A 66 SHL instruction A 3 A 37 A 47 A 59 A 66 SHLB instruction A 3 A 37 A 47 A 59 A 66 SHLL instruction A 3 A 38 A 47 A 59 SHORT INTEGER defined 4 2 SHR instruction A 3 A 38 A 47 A 59 A 66 SHRA instruction A 3 A 39 A 47 A 59 A 66 SHRAB instruction A 3 A 39 A 47 A 59 A 66 SHRAL instruction A 3 A 40 A 47 A 59 A 66 SHRB instruction A 3 A 40 A 47 A 59 A 66 SHRL instruction A 3 A 41 A 47 A 59 A 66 Signals descriptions B 6 B 12 naming conventions 1 4 Single transfer mode See PTS SIO port 2 11 8 1 9 bit data See mode 2 mode 3 block diagram 8 1 10 2 calculating baud rate 8 12 enabling interrupts 8 13 enabling parity 8 8 framing error 8 14 half duplex consid
218. NT MASKI register to en able or disable the OVRO_1 and OVR2 3 interrupts PTS service is not recommended for multiplexed interrupts because it cannot determine the inter rupt source 8 196 80C196NU USER S MANUAL intel INT MASK Address Reset State 0008H 00H The interrupt mask INT MASK register enables or disables masks individual interrupt requests The El and Dl instructions enable and disable servicing of all maskable interrupts INT MASK is the low byte of the processor status word PSW therefore PUSHF or PUSHA saves this register on the stack and POPF or POPA restores it 7 0 EPAO RI TI EXTINTO OVRTM2 OVRTM1 Bit z Number Function 7 3 Setting a bit enables the corresponding interrupt 1 0 The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector Capture Compare Channel 0 FF200EH RI SIO Receive FF200CH TI SIO Transmit FF200AH EXTINT1 FF2008H EXTINTO EXTINTO pin FF2006H OVRTM2 Timer 2 Overflow Underflow FF2002H OVRTM1 Timer 1 Overflow Underflow FF2000H 2 Reserved for compatibility with future devices write zero to this bit Figure 6 5 Interrupt Mask INT_MASK Register intel STANDARD AND PTS INTERRUPTS INT MASK1 Address 0013H Reset State 00H The interrupt mask 1 INT MASK1 register enables or disables masks individual interrupt requests
219. NU xis 1 2 or 4 depending on the clock mode The internal bus speed of the device is v f Operating period 1 f All AC Timings are referenced to t Tava Address Setup to ALE Low Length of time ADDRESS is valid before ALE falls Use this specification when designing the external latch Tavat Address Setup to RD Low Length of time ADDRESS is valid before RD falls Tavwe Address Setup to WR Low Length of time ADDRESS is valid before WR falls CLKOUT High Period Needed in systems that use CLKOUT as clock for external devices Tc HWL CLKOUT High to WR Low Time between CLKOUT going high and WR going active Tc LCL CLKOUT Cycle Time Normally 2t Tc LLH CLKOUT Falling to ALE Rising Use to derive other timings Minimum time between ALE pulses ALE High Period Use this specification when designing the external latch Tuax Address Hold after ALE Low Length of time ADDRESS is valid after ALE falls Use this specification when designing the external latch ALE Falling to CLKOUT Rising Use to derive other timings Tun ALE Low to RD Low Length of time after ALE falls before RD is asserted Could be needed to ensure proper memory decoding takes place before a device is enabled ALE Low to WR Low Length of time after ALE falls before WR is asserted Could
220. ON SET REFERENCE Table A 8 Instruction Lengths and Hexadecimal Opcodes Arithmetic Group Direct Immediate Note I ieee Mnemonic Length Opcode Length Opcode Length Opcode p Opcode ADD 2 ops 3 64 4 65 3 66 4 5 67 ADD 3 ops 4 44 5 45 4 46 5 6 47 ADDB 2 ops 3 74 3 75 3 76 4 5 77 ADDB 3 ops 4 54 4 55 4 56 5 6 57 ADDC 3 A4 4 A5 3 A6 4 5 7 ADDCB 3 B4 3 B5 3 B6 4 5 B7 CLR 2 01 CLRB 2 11 CMP 3 88 4 89 3 8A 4 5 8B CMPB 3 98 3 99 3 9A 4 5 9B CMPL 3 C5 DEC 2 05 DECB 2 15 EXT 2 06 EXTB 2 16 INC 2 07 INCB 2 17 SUB 2 ops 3 68 4 69 3 6A 4 5 6B SUB 3 ops 4 48 5 49 4 4A 5 6 4B SUBB 2 ops 3 78 3 79 3 7A 4 5 7B SUBB 3 ops 4 58 4 59 4 5A 5 6 5B SUBC 3 A8 4 A9 3 AA 4 5 AB SUBCB 3 B8 3 B9 3 BA 4 5 BB NOTES 1 Indirect normal and indirect autoincrement share the same opcodes as do short and long indexed modes Because word registers always have even addresses the address can be expressed in the upper seven bits the least significant bit determines the addressing mode Indirect normal and short indexed modes make the second byte of the instruction even LSB 0 Indirect autoincrement and long indexed modes make the second byte odd LSB 1 2 For indexed instructions the first column lists instruction lengths as S L where S is the short indexed
221. ON and EPA3 CON registers only C 20 intel REGISTERS EPAx CON EPAx CON Continued Address Table C 8 0 3 Reset State The EPA control EPAx CON registers control the functions of their assigned capture compare channels The registers for EPAO andEPA2 are identical The registers for EPA1 and have an additional bit the remap bit This added bit bit 8 requires an additional byte so EPA1 CON and must be addressed as words while the others can be addressed as bytes 15 8 x 1 3 RM 7 0 TB CE M1 MO RE ROT ON RT 7 0 0 2 M1 MO RE ROT ON RT Bit Bit Function Number Mnemonic 5 4 M1 0 EPA Mode Select In capture mode specifies the type of event that triggers an input capture In compare mode specifies the action that the EPA executes when the reference timer matches the event time Mi 0 Capture Mode Event no capture capture on falling edge capture on rising edge capture on either edge M1 Compare Mode Action 0 0 1 1 0 0 no output 0 1 clear output pin 1 0 Set output pin 1 1 toggle output pin 3 RE Re enable Re enable applies to the compare mode only It allows a compare event to continue to execute each time the event time register EPAx TIME matches the reference timer rather than only upon the first time match 0 compare function is disabled after a single event 1 compare fu
222. ONAL CONVENTIONS AND TERMINOLOGY eem 1 3 1 3 RELATED DOCUMENTS asses Ett eet rt ete re b etd a dete 1 5 1 4 ELECTRONIC SUPPORT SYSTEMS esses emere enne 1 8 1 4 1 5 URGERE IE 1 8 1 4 2 Bulletin Board System BBS een 1 9 1 4 2 1 How to Find MCS 96 Microcontroller Files on the BBS 1 10 1 4 2 2 How to Find ApBUILDER Software and Hypertext Documents on the BBS 1 10 1 4 3 CompuServe Forums and iia levine aie 1 10 1 4 4 World Wide Web et rt tetti rel Late es e erede 1 11 1 5 TECHNICAL SUPPORT iro ere ree rt e ocu dede Pate etd 1 11 1 6 PRODUCT 1 11 2 ARCHITECTURAL OVERVIEW 2 1 TYPIGAL APPLICATIONS t tercie iege rete tet deed tne re 2 1 2 2 DEVIGE FEATURES eee reme PHI EE He 2 3 BLOCK DIAGRAM epe be t ce ph efe sido itr eo 2 2 2 8 1 61548 Gontrol te dete 2 3 2 3 2 Register File c 2 3 2 3 3 Register Arithmetic logic Unit RALU seem O74 2 3 3 1 Code Execution crana eniran Enea 2 4 2 3 8 2 Instruction Format 1275 2 3 4 Memory Controller
223. OP 2 RST 4 SETC 2 SKIP 3 md PTS Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long DPTS 2 EPTS 2 NOTE The column entitled Reg lists the instruction execution times for accesses to the register file or peripheral SFRs The column entitled Mem lists the instruction execution times for accesses to all memory mapped registers I O or memory See Table 5 1 on page 5 4 for address information A 67 intel B Signal Descriptions APPENDIX B SIGNAL DESCRIPTIONS This appendix provides reference information for the pin functions of the 8XC196NP and 80C196NU B 1 FUNCTIONAL GROUPINGS OF SIGNALS Table B 1 lists the signals for the 8XC196NP and 80C196NU grouped by function A diagram of each package that is currently available shows the pin location of each signal NOTE As new packages are supported they will be added to the datasheets first If your package type is not shown in this appendix refer to the latest datasheet to find the pin locations Table B 1 8XC196NP and 80C196NU Signals Arranged by Function Address amp Data Processor Control Input Output Bus Control amp Status A19 0 NP only EPORT3 0 ALE AD15 0 EXTINT3 0 P1 3 0 EPA3 0 BHE WRH NMI P1 4 T1CLK BREQ Power amp Ground ONCE P1 5 T1DIR CLKOU
224. OVRTM2 OVRTM1 PTS service is not recommended because the PTS cannot determine the source of Interrupt EXTINTS pin EXTINT2 pin EPA Capture Channel 2 or 3 Overrun EPA Capture Channel 0 or 1 Overrun EPA Capture Compare Channel 3 EPA Capture Compare Channel 2 EPA Capture Compare Channel 1 EPA Capture Compare Channel 0 SIO Receive SIO Transmit EXTINTO pin Timer 2 Overflow Underflow Timer 1 Overflow Underflow shared interrupts PTS Vector FF205CH FF205AH FF2058H FF2056H FF2054H FF2052H FF2050H FF204EH FF204CH FF204AH FF2048H FF2046H FF2042H FF2040H 15 8 EXTINT3 EXTINT2 OVR2_3 OVRO 1 EPAS3 EPA2 EPA1 7 0 EPAO RI TI EXTINT1 EXTINTO OVRTM2 OVRTM1 7 Function 15 2 Reserved for compatibility with future devices write zero to this bit vu Rae a bit causes the corresponding interrupt to be handled by a PTS microcode routine C 36 intel REGISTERS PTSSRV PTSSRV Address 0006H Reset State 0000H The PTS service PTSSRV register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine When PTSCOUNT reaches zero hardware clears the corre sponding PTSSEL bit and sets the PTSSRV bit which requests the end of PTS interrupt When the end of PTS interrupt is called hardware clears the PTSSRV bit The PTSSEL bit must be set manually to re enable the PTS channel T
225. OVRTM2 from timer 1 and timer 2 These inter rupts are directly mapped into the two 8 bit interrupt pending registers INT PEND and INT PENDI The four separate capture overrun interrupts from EPA3 0 are multiplexed and mapped into two bits in INT PENDI The capture overrun interrupts from EPAO and 1 are multiplexed and mapped into OVRO 1 bit 4 of INT PENDI the capture overrun interrupts from EPA2 and EPA3 are multiplexed and mapped into OVR2 3 bit 5 of INT PENDI To en able the interrupts set the corresponding bits in the the two 8 bit interrupt mask registers INT MASK and INT 5 To enable the individual sources of the capture overrun inter rupts OVRO 1 and OVR2 3 set the corresponding bits in the EPA mask register MASK Chapter 6 Standard and PTS Interrupts discusses the interrupts in greater detail EPA MASK Address 1F9CH Reset State AAH The EPA interrupt mask EPA MASK register enables or disables masks the multiplexed EPA3 0 overrun interrupts OVR3 0 7 0 OVR3 OVR2 OVR1 OVRO Bit Bit Function 7 5 3 1 Reserved for compatibility with future devices write zeros to these bits 6 4 2 0 OVR3 Setting this bit enables the corresponding source as shared overrun OVR2 interrupt source The shared overrun interrupts OVRO 1 and OVR2 3 OVR1 are enabled by setting their interrupt enable bits in th
226. On devices with no internal nonvolatile memory always connect to Vas is not implemented on the 80C196NU HLDA Bus Hold Acknowledge This active low output indicates that the CPU has released the bus as the result of an external device asserting HOLD P2 6 HOLD Bus Hold Request An external device uses this active low input signal to request control of the bus This pin functions as HOLD only if the pin is configured for its special function see Bidirectional Port Pin Configurations on page 7 7 and the bus hold protocol is enabled Setting bit 7 of the window selection register WSR enables the bus hold protocol P2 5 INST Instruction Fetch This active high output signal is valid only during external memory bus cycles When high INST indicates that an instruction is being fetched from external memory The signal remains high during the entire bus cycle of an external instruction fetch INST is low for data accesses including interrupt vector fetches and chip configuration byte reads INST is low during internal memory fetches RD Read Read signal output to external memory RD is asserted only during external memory reads READY Ready Input This active high input signal is used to lengthen external memory cycles for slow memory by generating wait states in addition to the wait states that are generated internally When READY is high CPU operation continues in
227. Powerdown XTAL2 Disable Generators Oscillator Powerdown CPU Clocks PH1 PH2 Disable Clocks Idle Powerdown A3161 01 Figure 2 3 Clock Circuitry 8XC196NP The 80C196NU s clock circuitry Figure 2 4 implements phase locked loop and clock multiplier circuitry which can substantially increase the CPU clock rate while using a lower frequency in put clock The clock circuitry accepts an input clock signal on XTAL provided by an external crystal or oscillator Depending on the values of the PLLEN1 and PLLEN2 pins this frequency is routed either through the phase locked loop and multiplier or directly to the divide by two cir cuit The multiplier circuitry can double or quadruple the input frequency F4 1 before the fre quency f reaches the divide by two circuitry The clock generators accept the divided input frequency f 2 from the divide by two circuit and produce two nonoverlapping internal timing signals PH1 and PH2 These signals are active when high NOTE For brevity this manual uses lowercase to represent the internal clock frequency of both the 8XC196NP and the 80C196NU For the 8XC196NP fis equal to Fy 74 1 For the 80C196NU f is equal to either 1 2 1 OF depending on the clock multiplier mode which is controlled by the PLLEN1 and PLLEN2 input pins 2 7 8XC196NP 80C196NU USER S MANUAL intel Disable PLL Powerdown Phase C
228. Products or Embedded Microcontrollers databook to determine which type of memory is available for a specific device A transistor consisting of one part p type material and two parts n type material A field effect transistor with a p type conducting path Semiconductor material with introduced impurities doping causing it to have an excess of positively charged carriers Program counter A component of the clock generation circuitry The phase locked loop PLL and the two input pins PLLENI and PLLEN2 combine to enable the device to attain its maximum operating frequency with an external clock whose frequency is either equal to one half or one fourth that maximum frequency or with an external oscillator whose frequency is either one half or one fourth that maximum frequency Programmable interrupt controller The module responsible for handling interrupts that are to be serviced by interrupt service routines that you provide Also called simply the interrupt controller See phase locked loop Any maskable interrupt or nonmaskable NMI Two of the nonmaskable interrupts unimplemented opcode and software trap are not prioritized they vector directly to the interrupt service routine when executed A partition of memory where instructions can be stored for fetching and execution An instruction that prevents an interrupt from being acknowledged until after the next instruction executes The protected instructions are
229. R inactive Demultiplexed Mode A19 0 CSx Hold after WR High Minimum time the address will be valid after WR inactive BHE INST Hold after WR High Minimum time these signals will be valid after WR inactive WRit High to ALE High Time between going inactive and next ALE Also used to calculate WR inactive and next Address valid Twrex Data Hold after WR High Length of time after WR rises that the data stays valid on the bus 13 44 INTERFACING WITH EXTERNAL MEMORY Table 13 16 AC Timing Definitions Continued Symbol Definition The 8XC196Nx Meets These Specifications Continued A19 0 CSx Hold after WR High Minimum time the address and chip select output are held after WR inactive WR Low to CLKOUT High Minimum and maximum time between WR being asserted and CLKOUT going high Twice WR Low to CLKOUT Low Minimum and maximum time between WR being asserted and CLKOUT going low WR Low to WR High WR pulse width 13 45 intel Instruction Set Reference APPENDIX A INSTRUCTION SET REFERENCE This appendix provides reference information for the instruction set of the family of MCS 96 microcontrollers It defines the processor status word PSW flags describes each instruction shows the relationships between instructions and PSW flags and shows hexadecimal opcodes instruction lengths and execution times It
230. RESET causes the chip to reset and return to normal operating mode After a device reset the first instruction fetch is from FF2080H or F2080H in external memory For the 80C196NP and 80C196NU the program and special purpose memory locations FF2000 FF2FFFH reside in external memory For the 88C196NP these locations can reside either in external memory or in internal ROM RPD Return from Powerdown Timing pin for the return from powerdown circuit If your application uses powerdown mode connect a capacitor between RPD and Vss if either of the following conditions is true e the internal oscillator is the clock source the phase locked loop PLL circuitry 80C196NU only is enabled see PLLEN2 1 signal description The capacitor causes a delay that enables the oscillator and PLL circuitry to stabilize before the internal CPU and peripheral clocks are enabled The capacitor is not required if your application uses powerdown mode and if both of the following conditions are true e an external clock input is the clock source e the phase locked loop circuitry 80C196NU only is disabled If your application does not use powerdown mode leave this pin unconnected Calculate the value of the capacitor using the formula found on page 12 11 Table 12 2 Operating Mode Control and Status Registers Mnemonic Address Description CCRO 2018H Chip Configuration 0 Register Bit 0 of this register enables a
231. ROL Register on page 10 16 and Timer 2 Control T2CONTROL Register on page 10 17 f is the internal operating frequency See Internal Timing on page 2 7 for details 10 3 1 Cascade Mode Timer 2 Only Timer 2 can be used in cascade mode In this mode the timer 1 overflow output is used as the timer 2 clock input Either the direction control bit of the timer 2 control register or the direction control assigned to timer 1 controls the count direction This method called cascading can pro vide a slow clock for idle mode timeout control or for slow pulse width modulation PWM ap plications see Generating a Low speed PWM Output on page 10 12 10 3 2 Quadrature Clocking Mode Both timer 1 and timer 2 can be used in quadrature clocking mode This mode uses the TxCLK and TxDIR pins as quadrature inputs as shown in Figure 10 3 External quadrature encoded sig nals two signals at the same frequency that differ in phase by 90 are input and the timer incre ments or decrements by one count on each rising edge and each falling edge Because the TXCLK and TxDIR inputs are sampled by the internal phase clocks transitions must be separated by at least two state times for proper operation The count is clocked by PH2 which is PH1 delayed by one half period The sequence of the signal edges and levels controls the count direction Refer to Figure 10 4 and Table 10 3 for sequencing information A typical source of quadrature encoded sig
232. S cu WU URL f ALE N N A19 0 ADISS BC N POO AD7 0 Data Data a AD7 0 Multiplexed ANCUS ELEME NRI EUN ELEM KNEE GUQUE e 17 Nem uf ALE N N c 7 2 Nf 158 a S AD7 0 Data Low Address Low Address AD15 8 High Address High Address A2471 02 Figure 13 12 Timings for Multiplexed and Demultiplexed 8 bit Buses 8XC196NP 13 25 8XC196NP 80C196NU USER S MANUAL intel 13 5 4 Comparison of Multiplexed and Demultiplexed Buses This section compares the timings for multiplexed and demultiplexed buses A 16 bit bus is used for the comparison 8 bit Bus Timings on page 13 24 compares the 8 bit and 16 bit buses In a multiplexed system where AD15 0 carry both address and data bus activities are time com pressed in comparison with a demultiplexed system where the address and data have separate lines 19 0 and AD15 0 The compression is reflected in differences in specifications for the demultiplexed and multiplexed bus Table 13 10 lists several bus specifications and their values for demultiplexed and multiplexed buses The data shows that the demultiplexed bus can accom modate slower memory devices See System Bus AC Timing Specifications on page 13 36 for a complete list of AC timing definitons Table 13 10 Comparison of AC Timings for Demultiplexed and Multiplexed 16 bit Buses
233. SP lt SP 4 SP lt PC PC lt PC 24 bit disp PSW Flag Settings Z N C V VT ST LD LOAD WORD Loads the value of the source DEST SRC word operand into the destination operand LD wreg waop DEST lt SRC PSW Flag Settings Z N C V VT ST 101000aa waop wreg A 27 8 196 80C196NU USER S MANUAL intel Table A 6 Instruction Set Continued the offset between the end of this instruction and the target label effecting the jump The offset must be in the range of 32 768 to 132 767 64 Kbyte mode PC lt PC 16 bit disp 1 Mbyte mode PC lt PC 24 bit disp PSW Flag Settings Z N C V VT ST Mnemonic Operation Instruction Format LDB LOAD BYTE Loads the value of the source DEST SRC byte operand into the destination operand LDB breg baop DEST SRC 101100aa baop breg PSW Flag Settings Z N C V VT ST LDBSE LOAD BYTE SIGN EXTENDED Sign DEST SRC extends the value of the source short LDBSE wreg baop integer operand and loads it into the destination integer operand 101111aa baop wreg low byte DEST lt SRC if DEST 15 1 then high word DEST lt else high word DEST lt 0 end_if PSW Flag Settings Z N C V VT ST L
234. Settings 2 V VT ST Vi ivi I7111 NEGB breg 00010011 breg NOP NO OPERATION Does nothing Control passes to the next sequential instruction PSW Flag Settings 7 VT ST NOP 11111101 31 8 196 80C196NU USER S MANUAL Table A 6 Instruction Set Continued In lel Mnemonic Operation Instruction Format NORML NORMALIZE LONG INTEGER Normalizes the source leftmost long integer operand That is it shifts the operand to the left until its most significant bit is 1 or until it has performed 31 shifts If the most significant bit is still 0 after 31 shifts the instruction stops the process and sets the zero flag The instruction stores the actual number of shifts performed in the destination rightmost operand COUNT lt 0 do while MSB DEST 0 AND COUNT 31 DEST lt DEST x 2 COUNT lt COUNT 1 end_while PSW Flag Settings Z N C V VT ST 0 NORML SRC DEST lreg breg 00001111 breg Ireg NOT COMPLEMENT WORD Complements the value of the word operand replaces each 1 with a 0 and each 0 with a 1 DEST lt NOT DEST PSW Flag Settings Z N C V VT ST 0 04 1 wreg 00000010 wreg NO
235. States 0 0 0 0 1 1 1 0 2 1 1 3 Figure 13 4 Bus Control BUSCONX Register 13 10 intel INTERFACING WITH EXTERNAL MEMORY Table 13 7 BUSCONx Addresses and Reset Values Register Address Reset Value BUSCONO 1F44H 03H BUSCON 1 1F4CH 00H BUSCON2 1F54H 00H BUSCONS 1F5CH 00H BUSCON4 1F64H 00H BUSCON5 1F6CH 00H 13 3 3 Chip select Unit Initial Conditions A chip reset produces the following initial conditions for the chip select unit e ADDRMSKx XFFFH e ADDRCOMO 0F20H This asserts CSO for the 256 byte address range F2000 F20FFH ADDRCOMI ADDRCOMS X000H For the fetch of chip configuration byte 0 BUSCONO is initialized for an 8 bit bus width multiplexed mode and three wait states DEMUX 0 BW16 0 WSO 1 WS1 1 Before the fetch of chip configuration byte 1 CCB1 the values of DEMUX BW16 WSO and WS1 in BUSCONO are loaded from CCBO The external bus is configured according to the new values The first lines of your program should perform two tasks 1 Set the stack pointer 2 Initialize all of the chip select registers ADDRCOMx ADDRMSKx BUSCON x by using the procedure in Initializing the Chip select Registers 13 3 4 Initializing the Chip select Registers When initializing the chip select parameters or modifying them at any time it is important to avoid a condition in which two chip selects outputs have
236. T Voc PLLEN1 NU only P1 6 T2CLK CS5 0 Vss PLLEN2 NU only P1 7 T2DIR HOLD RESET P2 0 TXD HLDA RPD P2 1 RXD INST XTAL1 P2 7 2 RD XTAL2 P3 7 0 READY P4 2 0 PWM2 0 WR WRL 4 3 1 8 196 80C196NU USER S MANUAL 82 DI A16 EPORT O 81 A17 EPORT 1 o Q lt 1 99 AD1 98 AD2 96 95 ADS 94 AD6 93 AD7 92 A Voc 91 B AD8 90 Vss 89 ADO 88 AD10 87 011 86 AD12 85 84 AD14 83 AD15 RESET 1 RD NMI BHE WRH 3 ALE AO INST A1 READY 3 RPD Vss ONCE A2 68 Fl Vss A3 67 M S8XC196NP 66 ass AG 64 9 A7 3 A10 yoo 62 Ait 55 12 Ne View of component as E P3 0 CSO mounted on PC board 58 15 1 51 57 FANG P3 2 CS2 56 Vss P3 3 5 55 EAXTAL1 56 54 EAXTAL2 P3 4 54 Vss P3 5 CS5 P3 6 EXTINT2 3 P2 7 CLKOUT P1 1 EPA1 6 29 P1 2 EPA2 30 P1 3 amp 31 P1 6 T2CLK 35 P1 7 T2DIR E 37 P4 0 PWMO 38 P4 1 PWM1 39 4 2 PWM2 40 P2 0 TXD E 44 P2 1 45 2 2 EXTINTO E 46 P2 3 BREQ 47 P2 5 HOLD 49 P2 6 HLDA 50 P2 4 EXTINT1 48 A2348 03 Figure 1 8XC196NP 100 lead SQFP Package intel SIGNAL DESCRIPTIONS oO EE co Qc x 10 I dio em NW Qooooonoooondaoaadaadaa
237. T1DIR Timer 1 External Direction External direction up down for timer 1 Timer 1 increments when T1DIR is high and decrements when it is low Also used in conjunction with T1CLK for quadrature counting mode T1DIR is multiplexed with P1 5 T2DIR Timer 2 External Direction External direction up down for timer 2 Timer 2 increments when T2DIR is high and decrements when it is low Also used in conjunction with T2CLK for quadrature counting mode T2DIR is multiplexed with P1 7 TXD Transmit Serial Data In serial modes 1 2 and 3 TXD transmits serial port output data In mode 0 it is the serial clock output TXD is multiplexed with P2 0 8XC196NP 80C196NU USER S MANUAL intel Table B 3 Signal Descriptions Continued Name Type Description Voc PWR Digital Supply Voltage Connect each Vec pin to the digital supply voltage Vss GND Digital Circuit Ground Connect each Vss pin to ground through the lowest possible impedance path WR Write This active low output indicates that an external write is occurring This signal is asserted only during external memory writes WRi is multiplexed with WRL t The chip configuration register 0 CCRO determines whether this pin functions as WR WRL CCRO 2 1 selects WR CCRO 2 0 selects WRL4 WRH Write Hight During 16 bit bus cycles this active low output signal is asserted for high byte writes and word writes to external memory
238. TB COMPLEMENT BYTE Complements the value of the byte operand replaces each 1 with a 0 and each 0 with a 1 DEST lt NOT DEST PSW Flag Settings Z N C V VT ST 0 0 NOTB breg 00010010 breg A 32 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format OR LOGICAL OR WORDS ORs the source word operand with the destination word operand and replaces the original destination operand with the result The result has a 1 in each bit position in which either the source or destination operand had a 1 DEST lt DEST OR SRC PSW Flag Settings Z N C V VT ST 0 0 DEST SRC OR wreg waop 100000aa waop wreg ORB LOGICAL OR BYTES ORs the source byte operand with the destination byte operand and replaces the original destination operand with the result The result has a 1 in each bit position in which either the source or destination operand had a 1 DEST lt DEST OR SRC PSW Flag Settings Z N Cy V VT ST 0 DEST SRC ORB breg baop 100100aa baop breg POP POP WORD Pops the word on top of the stack and places it at the destination operand DEST lt SP SP lt SP 2 PSW Flag S
239. The following code shows one way to prevent all interrupts except EXTINT3 priority 14 from interrupting an SIO receive interrupt service routine priority 06 8XC196NP 80C196NU USER S MANUAL intel SERIAL RI ISR CSEG PUSHA Save PSW INT MASK INT MASK1 amp WSR this disables all interrupts LDB INT MASK1 01000000 Enable EXTINT3 only Enable interrupt servicing Service the RI interrupt POPA Restore PSW INT MASK INT 5 1 amp WSR registers RET AT OFF200CH fill in interrupt table DCW LSW SERIAL RI ISR LSW is a compiler directive that means least significant word of vector address END Note that location FF200CH in the interrupt vector table must be loaded with the value of the la bel SERIAL RI ISR before the interrupt request occurs and that the receive interrupt must be enabled for this routine to execute This routine like all interrupt service routines is handled in the following manner 1 6 14 After the hardware detects and prioritizes an interrupt request it generates and executes an interrupt call This pushes the program counter onto the stack and then loads it with the contents of the vector corresponding to the highest priority pending unmasked interrupt The hardware will not allow another interrupt call until after the first instruction of the interrupt service routine is executed The PUSHA instruction saves the contents of the PSW INT MASK INT 5 and
240. U executes the interrupt service routine Otherwise the CPU executes the instruction that immediately follows the command that invoked the power saving mode In idle mode asserting any enabled interrupt causes the device to resume normal operation EXTINTO is multiplexed with P2 2 EXTINT1 is multiplexed with P2 4 EXTINT2 is multiplexed with P3 6 and is multiplexed with P3 7 HLDA Bus Hold Acknowledge This active low output indicates that the CPU has released the bus as the result of an external device asserting HOLD HLDA is multiplexed with P2 6 SIGNAL DESCRIPTIONS Table B 3 Signal Descriptions Continued Name Type Description HOLD Bus Hold Request An external device uses this active low input signal to request control of the bus This pin functions as HOLD only if the pin is configured for its special function see Bidirectional Port Pin Configurations on page 7 7 and the bus hold protocol is enabled Setting bit 7 of the window selection register WSR enables the bus hold protocol HOLD is multiplexed with P2 5 INST Instruction Fetch This active high output signal is valid only during external memory bus cycles When high INST indicates that an instruction is being fetched from external memory The signal remains high during the entire bus cycle of an external instruction fetch INST is low for data accesses including interrupt vector fetche
241. UD VALUE is 0000H when using the internal clock source f and 0001H when using T1CLK In synchronous mode 0 the minimum BAUD VALUE is 0001H for transmissions and 0002H for receptions 15 8 CLKSRC BV14 BV13 BV12 BV11 BV10 BV9 BV8 7 0 BV7 BV6 BV5 4 BV3 BV2 BV1 BVO Bit Bit Function Number Mnemonic 15 CLKSRC Serial Port Clock Source This bit determines whether the serial port is clocked from an internal or an external source 0 signal on the T1CLK pin external source 1 internal operating frequency f 14 0 BV14 0 Baud Rate These bits constitute the BAUD VALUE Use the following equations to determine the BAUD VALUE for a given baud rate Synchronous mode 0 7 f T1CLK BAUD VALUE 1 Baud Rate x 2 Baud Rate Asynchronous modes 1 2 and 3 f T1CLK 1 r my BAUD VALUE Baud Rate x 16 Baud Rate x 8 For mode 0 receptions the BAUD VALUE must be 0002H or greater Otherwise the resulting data in the receive shift register will be incorrect Figure 8 7 Serial Port Baud Rate SP BAUD Register 8XC196NP 80C196NU USER S MANUAL intel CAUTION For mode 0 receptions the BAUD VALUE must be 0002H or greater Otherwise the resulting data in the receive shift register will be incorrect The reason for this restriction is that the receive shift register is clocked from an internal signal ra
242. URAL OVERVIEW 2 3 3 2 Instruction Format 5 96 microcontrollers combine a large set of general purpose registers with a three operand instruction format This format allows a single instruction to specify two source registers and a separate destination register For example the following instruction multiplies two 16 bit vari ables and stores the 32 bit result in a third variable MUL RESULT FACTOR 1 FACTOR 2 multiply FACTOR 1 and FACTOR 2 and store answer in RESULT RESULT FACTOR 1 FACTOR 2 An 80C186 device requires four instructions to accomplish the same operation The following ex ample shows the equivalent code for an 80C186 device MOV AX FACTOR 1 move FACTOR 1 into accumulator AX AX lt FACTOR1 MUL FACTOR 2 multiply FACTOR 2 and AX DX AX lt AX x FACTOR 2 MOV RESULT AX move lower byte into RESULT RESULT lt AX MOV RESULT 2 DX move upper byte into RESULT 2 RESULT 2 lt DX 2 3 A Memory Controller The RALU communicates with all memory except the register file and peripheral SFRs through the memory controller It communicates with the upper register file through the memory control ler except when windowing is used see Chapter 5 Memory Partitions The memory controller contains the prefetch queue the slave program counter slave PC address and data registers and the bus controller The bus controller drives the memory bus which consists of an internal m
243. VRO 1 in INT PEND1 OVR2 and OVR3 are multiplexed to share another interrupt pending bit OVR2 3 in INT PEND1 CON EPA1 CON EPA2 CON EPA3 CON 1F80H 1F84H 1F88H 1F8CH EPAx Capture Compare Control These registers control the functions of the capture compare channels EPA1 CON and CON require an extra byte because they contain additional bit for PWM remap mode These two registers must be addressed as words the others can be addressed as bytes EPAO TIME EPA1 TIME EPA2 TIME TIME 1F82H 1F86H 1F8AH 1F8EH EPAx Capture Compare Time In capture mode these registers contain the captured timer value In compare mode these registers contain the time at which an event is to occur In capture mode these registers are buffered to allow two captures before an overrun occurs However they are not buffered in compare mode INT_MASK 0008H Interrupt Mask Three bits in this 8 bit register OVRTM1 OVRTM2 and EPAO enable and disable mask the three interrupts associated with the corresponding bits in INT PEND register INT MASK1 0013H Interrupt Mask 1 Five bits in this 8 bit register EPA1 EPA2 EPA3 OVRO 1 and OVR2 3 enable and disable mask the five interrupts associated with the corresponding bits in INT_PEND1 register INT PEND 0009H Interrupt Pending Any set bit in this 8 bit register indicates a pending interrupt The three bits associated with
244. Values Register Address Reset Value ACC 00 000CH 00H ACC 02 000 00H 8XC196NP 80C196NU USER S MANUAL intel ACC STAT ACC STAT Address OBH 80C196NU Reset State 00H The accumulator control and status STAT register enables and disables fractional and saturation modes and contains three status flags that indicate the status of the accumulator s contents 80C196NU FME SME STOVF OVF STSAT Bit Bit Number Mnemonic Function 7 FME Fractional Mode Enable Set this bit to enable fractional mode See Table C 4 In this mode the result of a signed multiplication instruction is shifted left by one bit before it is added to the contents of the accumulator For unsigned multiplication this bit is ignored 6 SME Saturation Mode Enable Set this bit to enable saturation mode See Table C 4 In this mode the result of a signed multiplication operation is not allowed to overflow or underflow For unsigned multiplication this bit is ignored 5 3 Reserved for compatibility with future devices write zeros to these bits STOVF Sticky Overflow Flag For unsigned multiplication this bit is set if a carry out of bit 31 occurs Unless saturation mode is enabled this bit is set for signed multiplication to indicate that the sign bit of the accumulator and the sign bit of the addend are equal but the sign bit of the result is the opp
245. W Flag Settings Z N C V VT ST T DIVB DIVIDE SHORT INTEGERS Divides the DEST SRC contents of the destination integer operand DIVB by the contents of the source short integer operand using signed arithmetic It stores the 11111110 100111 wreg quotient into the low order byte of the destination i e the word with the lower address and the remainder into the high order byte The following two statements are performed concurrently low byte DEST lt DEST SRC high byte DEST lt DEST MOD SRC wreg baop PSW Flag Settings Z N C V VT ST ee 7 T 5 8XC196NP 80C196NU USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format DIVU DIVIDE WORDS UNSIGNED Divides the DEST SRC contents of the destination double word DIVU Ireg waop operand by the contents of the source word ising unsigned arithmetic It stores 100011aa waop Ireg the quotient into the low order word i e the word with the lower address of the destination operand and the remainder into the high order word The following two statements are performed concurrently low word DEST lt DEST SRC high word DEST lt DEST MOD SRC PSW Flag Settings Z N C V VT ST mb To DIVUB DIVIDE BYTES UNSIGNED This instruction DEST SRC
246. Y BIT FLAG IS CLEAR Tests the sticky bit flag If the flag is set control JNST cadd passes to the next sequential instruction If the sticky bit flag is clear this instruction adds 11010000 disp to the program counter the offset between the end of this instruction and the target label NOTE The displacement disp is sign effecting the jump The offset must be in extended to 24 bits range of 128 to 127 if ST then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JNV JUMP IF OVERFLOW FLAG IS CLEAR Tests the overflow flag If the flag is set JNV cadd control passes to the next sequential instruction If the overflow flag is clear this 11010101 disp instruction adds to the program counter the offset between the end of this instruction and NOTE The displacement disp is sign the target label effecting the jump The offset extended to 24 bits must be in range of 128 to 127 if V 2 0 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST A 25 8 196 80C196NU USER S MANUAL Table A 6 Instruction Set Continued In lel Mnemonic Operation Instruction Format JNVT JUMP IF OVERFLOW TRAP FLAG IS CLEAR Tests the overflow trap flag If the flag is set this instruction clears the flag and passes control to the next sequential instruction If the overflow
247. a is 1F80H To determine the offset subtract that base address from the address to be accessed 1F82H 1F80H 0002H Add the offset to the base address of the window in the lower register file from Table 5 11 The direct address is 0082H 0002H 0080H 5 18 l ntel MEMORY PARTITIONS 5 3 2 4 Unsupported Locations Windowing Example 8XC196NP Only Assume that you wish to access location IFE7H the PIN register a memory mapped SFR with direct addressing through a 128 byte window This location is in the range of addresses 1FEO 1FFFH that cannot be windowed Although you could set up the window by writing 1FH to the WSR reading this location through the window would return FFH all ones and writing to it would not change the contents However you could directly address the remaining SFRs in the range of IF80 1FDFH 5 3 2 5 Using the Linker Locator to Set Up a Window In this example the linker locator is used to set up a window The linker locator locates the win dow in the upper register file and determines the value to load in the WSR for access to that win dow Please consult the manual provided with the linker locator for details ockckck ck ck kk modi ck ckckckck ck ckckckck kk modl1 module main Main module for linker public functionl extrn WSR Must declare WSR as external wsr equ 14h byte sp equ 18h word oseg varl dsw 1 Allocate variables in an overlayable segment var2 dsw 1 var3 dsw 1
248. a mixed 8 bit and 16 bit system with two flash memories and one SRAM The WRL signal which is generated for all 8 bit writes Table 13 14 is used to write bytes to the SRAM Note that the RD signal is sufficient for sin gle byte reads on a 16 bit bus Both bytes are put onto the data bus and the memory controller discards the unwanted byte 51 50 19 0 AD15 8 8XC196 2439 03 Figure 13 19 A System with 8 bit and 16 bit Buses 13 9 SYSTEM BUS AC TIMING SPECIFICATIONS Refer to the latest datasheet for the AC timings to make sure your system meets specifications The major external bus timing specifications are shown in Figure 13 20 through 13 23 13 36 intel INTERFACING WITH EXTERNAL MEMORY CLKOUT TAVDV i TLLWL TWHLH WR TQVWH TWHOX ago i i noise Cem write 1 12 TRHBX i 1 TWHBX INST Valid INST i TRHAX TWHAX ea LEER a GN TWHSH TRHSH A2367 05 Figure 13 20 Multiplexed System Bus Timing 8XC196NP 13 37 8 196 80C196NU USER S MANUAL CLKOUT ALE RD AD15 0 read WR AD15 0 write BHE INST Tcupv TW TLLAL T Z AVLL
249. able A 9 Instruction Execution Times in State Times Continued Data Mnemonic Extended indirect Normal EBMOVI register register 8 14 per word 16 per interrupt memory register 8 17 per word 16 per interrupt memory memory 8 20 per word 16 per interrupt Mnemonic Indirect BMOV register register 6 8per word memory register 6 11 per word memory memory 6 14 per word BMOVI register register 7 8 per word 14 per interrupt memory register 7 11 per word 14 per interrupt memory memory 7 14 per word 14 per interrupt Extended indirect Mnemonic Direct Immed Extended indexed Normal Autoinc ELD 6 9 8 11 8 11 ELDB 6 9 8 11 8 11 EST 6 9 8 11 8 11 ESTB 6 9 8 11 8 11 Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long Reg Mem Reg Mem Reg Mem Reg Mem LD 4 5 5 8 6 8 6 9 7 10 LDB 4 4 5 8 6 8 6 9 7 10 LDBSE 4 4 5 8 6 8 6 9 7 10 LDBZE 4 4 5 8 6 8 6 9 7 10 ST 4 5 8 6 9 6 9 7 10 STB 4 5 8 6 8 6 9 7 10 XCH 5 8 13 9 14 XCHB 5 8 13 9 14 NOTE The column entitled Reg lists the instruction execution times for accesses to the register file or peripheral SFRs The column entitled Mem lists the instruction execution times for accesses to all memory mapped registers I O or memory See Table 5 1 on page 5 4 for address information A 63
250. address is 00H the results of the multiply are added to the current contents of the accumulator A 30 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format MULUB 2 operands MULTIPLY BYTES UNSIGNED Multiplies the source and destination operands using unsigned arithmetic and stores the word result into the destination operand The sticky bit flag is undefined after the instruction is executed DEST lt DEST x SRC PSW Flag Settings 7 VT ST DEST SRC MULUB wreg baop 011111aa baop wreg MULUB 8 operands MULTIPLY BYTES UNSIGNED Multiplies the two source byte operands using unsigned arithmetic and stores the word result into the destination operand The sticky bit flag is undefined after the instruction is executed DEST lt SRC1 x SRC2 PSW Flag Settings 7 VT ST DEST SRC1 SRC2 MULUB wreg breg baop 010111 breg wreg NEG NEGATE INTEGER Negates the value of the integer operand DEST lt DEST PSW Flag Settings 2 V VT ST wreg 00000011 wreg NEGB NEGATE SHORT INTEGER Negates the value of the short integer operand DEST lt DEST PSW Flag
251. air EPAO and EPA1 or EPA3_CON to pair EPA2 and EPA3 One channel must be configured to set the out put the other to clear it At the set or clear time the PTS reads the old time value from EPAx_TIME adds to it the PWM period constant and returns the new value to EPAx_TIME Set and clear times can be programmed to differ by as little as one timer count resulting in very nar row pulses Once started this method requires no CPU intervention unless you need to change the output frequency The method uses a single timer counter The timer counter is not interrupted during this process so other EPA channels can also use it if they do not reset it To determine the maximum high speed PWM frequency in your system calculate your system s worst case interrupt latency and then double it The worst case interrupt latency is the total la tency of all the interrupts both normal and PTS used in your system Assume a system that uses a pair of remapped EPA channels i e EPAO and 1 or EPA3 and 4 two enabled interrupts and PTS service Also assume that the PTS is initialized and that the duty cycle and frequency are fixed The worst case interrupt latency for a single interrupt system with PTS service is 43 state times see PTS Interrupt Latency on page 6 9 In this mode the maxi mum period equals twice the PTS latency Therefore the execution time for a PWM period equals 86 state times When the input frequency on XTAL is 25 MHz and the p
252. aken 8 jump taken JNE 4 jump not taken 8 jump taken JNH 4 jump not taken 8 jump taken JNST 4 jump not taken 8 jump taken JNV 4 jump not taken 8 jump taken JNVT 4 jump not taken 8 jump taken JST 4 jump not taken 8 jump taken JV 4 jump not taken 8 jump taken JVT 4 jump not taken 8 jump taken Shift Mnemonic Direct NORML 8 1 per shift 9 for 0 shift SHL 6 1 per shift 7 for O shift SHLB 6 1 per shift 7 for O shift SHLL 7 1 per shift 8 for 0 shift SHR 6 1 per shift 7 for O shift SHRA 6 1 per shift 7 for 0 shift SHRAB 6 1 per shift 7 for 0 shift SHRAL 7 1 per shift 8 for 0 shift SHRB 6 1 per shift 7 for 0 shift SHRL 7 1 per shift 8 for 0 shift NOTE The column entitled Reg lists the instruction execution times for accesses to the register file or peripheral SFRs The column entitled Mem lists the instruction execution times for accesses to all memory mapped registers or memory See Table 5 1 on page 5 4 for address information A 66 intel INSTRUCTION SET REFERENCE Table A 9 Instruction Execution Times in State Times Continued Special Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long CLRC 2 CLRVT 2 DI 2 mE EI 2 IDLPD Valid key 12 x PER Invalid key EM 28 N
253. al 1 1 1 RESET 1 RST Instruction IDLPD Invalid Key See the datasheet for minimum and maximum values A2416 01 Figure 11 8 Internal Reset Circuitry 11 6 1 Generating an External Reset To reset the device hold the RESET pin low for at least one state time after the power supply is within tolerance and the oscillator has stabilized When RESET is first asserted the device turns on a pull down transistor Q1 for 16 state times This enables the RESET signal to function as the system reset 8XC196NP 80C196NU USER S MANUAL intel The simplest way to reset the device is to insert a capacitor between the RESET pin and as shown in Figure 11 9 The device has an internal pull up resistor shown in Figure 11 8 RESET should remain asserted for at least one state time after V o and XTALI have stabilized and met the operating conditions specified in the datasheet A capacitor of 4 7 uF or greater should provide sufficient reset time as long as V rises quickly RESET il 8XC196 Device A0276 01 Figure 11 9 Minimum Reset Circuit Other devices in the system may not be reset because the capacitor will keep the voltage above Since RESET is asserted for only 16 state times it may be necessary to lengthen and buffer the system reset pulse Figure 11 10 shows an example of a system reset circuit In this example D2 creates a wired OR gate connection to the reset pin A
254. al Overview for additional information Clearing REGO 0 CLKO disables the prescaler generating a pulse that is 512 state times in length With the prescaler disabled the correct multiplier is 2 Setting CON REGO 0 CLKO enables the PWM s divide by two clock prescaler generating pulse that is 1 024 state times in length With the divide by two clock prescaler enabled the cor rect multiplier is 4 For example assume that CLKO is set and the value you write to the PWMx CONTROL register is 19H 25 decimal To arrive at the appropriate duty cycle you must multiply the value stored in PWMx CONTROL by 4 then divide that result by the total pulse length 1 024 This calculation results in a duty cycle value of approximately 1046 0977 For the 80C196NU setting CON REGO 1 CLK1 enables the divide by four clock prescaler generating a pulse that is 2 048 state times in length With the divide by four prescaler enabled the correct multiplier is 8 When CON REGO 1 is set the divide by four clock prescaler is en abled and CON REGO 0 is ignored 9 4 intel PULSE WIDTH MODULATOR Duty PWM Control Cycle Register Value Output Waveform 0 00H 0 10 19H o JI 90 E6H o T Il U 99 6 FH o T A0119 02 Figure 9 3 PWM Output Waveforms 9 4 PROGRAMMING THE FREQUENCY AND PERIOD The PWM module provides two selectable fixed PWM output frequencies for a specified internal operating frequency f
255. ally EPAx TIME Adds of two values to the location specified by Adds the value in PTSCONST1 to the location PTSPTR1 If TBIT is clear it adds the value in specified by PTSPTR1 PTSCONST1 If TBIT is set it adds the value PTSCONST2 Stores the sum back into the location specified by Stores the sum back into the location specified by PTSPTR1 PTSPTR1 Toggles TBIT Toggles the unused TBIT Figure 6 14 illustrates a generic PWM waveform The length of an entire PWM output pulse is T2 The time the output is is the time the output is off is T2 The formulas for frequency and duty cycle are shown below In most applications the frequency is held constant and the duty cycle is varied to change the average value of the waveform 1 Frequency in Hertz 4 T2 T1 Duty Cycle 100 T2 6 26 intel STANDARD AND PTS INTERRUPTS Output Value 1 on off on off 0 0 Ti T2 T2 T1 time M a o On time T1 Off time T2 T1 0263 02 Figure 6 14 Generic PWM Waveform PWM modes do not use a PISCOUNT register to specify the number of consecutive PTS cycles To stop producing the PWM output first clear the PISSEL x bit to disable PTS service for the interrupt and then use the interrupt service routine to reconfigure the EPA channel 6 6 5 1 PWM Toggle Mode Example Figure 6 15 shows the PTS control block for PWM toggle mode To genera
256. ame Address and Reset Status Continued lel Binary Reset Value rco Register Name ee ua tas SBUF TX Serial Port Transmit Buffer 1FBAH 0000 0000 SP Stack Pointer 0018H XXXX XXXX SP BAUD Serial Port Baud Rate 1FBCH 0000 0000 0000 0000 SP Serial Port Control 1FBBH 0000 0000 SP STATUS Serial Port Status 1FB9H 0000 1011 T1CONTROL Timer 1 Control 1F90H 0000 0000 T2CONTROL Timer 2 Control 1F94H 0000 0000 TIMER1 Timer 1 Value 1F92H 0000 0000 0000 0000 TIMER2 Timer 2 Value 1F96H 0000 0000 0000 0000 WSR Window Selection 0014H 0000 0000 WSR1 NU Window Selection 1 0015H 0000 0000 ZERO REG Zero Register 0000H 0000 0000 0000 0000 intel The 32 bit accumulator register 0x resides at locations OC OFH You can read from or write to the accumulator register as two words at locations OCH and OEH REGISTERS ACC 0x ACC 0x Address Table C 3 X 2 0 2 80C196NU Reset State You can read this register to determine the current value of the accumulator You can write to this register to clear or preload a value into the accumulator 80C196NU 15 8 Accumulator Value word 1 high byte 7 0 ACC 02 Accumulator Value word 1 low byte 15 8 Accumulator Value word 0 high byte 7 0 ACC 00 Accumulator Value word 0 low byte PUN Function 15 0 Accumulator Value Table C 3 ACC 0x Addresses and Reset
257. amples with code Figure 6 12 shows the PTS control block for single transfer mode 6 20 intel STANDARD AND PTS INTERRUPTS PTS Single Transfer Mode Control Block In single transfer mode the PTS control block contains a source and destination address PTSSRC and PTSDST a control register PTSCON and a transfer count PTSCOUNT 7 0 Unused 0 0 0 0 0 0 0 0 7 0 Unused 0 0 0 0 0 0 0 0 15 8 PTSDST HI PTS Destination Address high byte 7 0 PTSDST LO PTS Destination Address low byte 15 8 PTSSRC HI PTS Source Address high byte 7 0 PTSSRC LO PTS Source Address low byte 7 0 PTSCON M2 M1 MO BW su DU SI DI 7 0 PTSCOUNT Consecutive Byte or Word Transfers Register Location Function PTSDST PTSCB 4 PTS Destination Address Write the destination memory location to this register A valid address is any unreserved memory location within page 00H however it must point to an even address if word transfers are selected PTSSRC PTSCB 2 PTS Source Address Write the source memory location to this register A valid address is any unreserved memory location within page 00H however it must point to an even address if word transfers are selected Figure 6 12 PTS Control Block Single Transfer Mode 6 21 8XC196NP 80C196NU USER S MANUAL intel PTS Single Transfer Mode Control Block Conti
258. an read EP PIN at any time to determine the value of a pin When PIN is read the tents of the sample latch are output onto the internal bus Figure 7 3 shows a circuit schematic for a single bit of the EPORT Q1 and Q2 are the strong com plementary drivers for the pin Q1 can source at least 3 mA at Vec 0 7 volts Q2 can sink at least 3 mA at 0 45 volts Consult the datasheet for specifications Resistor provides ESD protection for the pin 7 3 1 1 Reset During reset the falling edge of RESET generates a short pulse that turns on the medium pull up transistor Q3 which remains on for about 300 ns causing the pin to change rapidly to its reset state The active low level of turns on transistor Q4 which weakly holds the pin high Q4 can source approximately 10 WA consult the datasheet for exact specifications When RESET is inactive both and Q4 are off Q1 and Q2 determine output drive 7 3 1 2 Output Enable If RESET HOLD idle or powerdown is asserted the gates that control Q1 and Q2 are dis abled and Q1 and Q2 remain off Otherwise the gates are enabled and complementary or open drain operation is possible 7 3 1 3 Complementary Output Mode For complementary output mode the gates that control Q1 and Q2 must be enabled The Q2 gate is always enabled except when RESET HOLD idle or powerdown is asserted Either clear ing EP DIR selecting complementary mode or setting
259. and LONG INTEGERs are formed by two adjacent 16 bit words in memory The least significant word of a DOUBLE WORD is always in the lower address even when the data is in the stack which means that the most significant word must be pushed into the stack first The address of a 32 bit operand is that of its least significant byte The hardware supports the 32 bit data types as operands in shift operations as dividends of 32 by 16 divide operations and as products of 16 by 16 multiply operations For these operations the 32 bit operand must reside in the lower register file and must be aligned at an address that is evenly divisible by four 4 5 3 Addressing 64 bit Operands The hardware supports the QUAD WORD only as the operand of the EBMOVI instruction For this operation the QUAD WORD variable must reside in the lower register file and must be aligned at an address that is evenly divisible by eight 4 12 intel PROGRAMMING CONSIDERATIONS 4 5 4 Linking Subroutines Parameters are passed to subroutines via the stack Parameters are pushed into the stack from the rightmost parameter to the left The 8 bit parameters are pushed into the stack with the high order byte undefined The 32 bit parameters are pushed onto the stack as two 16 bit values the most significant half of the parameter is pushed into the stack first As an example consider the fol lowing procedure void example procedure char paraml long param2 int param3 Wh
260. apture Comp 1 Time 1F86H 0000 0000 0000 0000 2 2 1F8AH 0000 0000 0000 0000 Capture Comp 3 Time 1F8EH 0000 0000 0000 0000 5 Interrupt Mask 0008H 0000 0000 INT MASK1 Interrupt Mask 1 0013H 0000 0000 INT PEND Interrupt Pending 0009H 0000 0000 INT PEND1 Interrupt Pending 1 0012H 0000 0000 ONES REG Ones Register 0002H 1111 1111 1111 1111 P1 DIR Port 1 I O Direction 1FD2H 1111 1111 P1 MODE Port 1 Mode 1FDOH 0000 0000 P1_PIN Port 1 Pin Input 1FD6H XXXX XXXX P1_REG Port 1 Data Output 1FD4H 1111 1111 P2_DIR Port 2 I O Direction 1FD3H 1111 1111 P2 MODE Port 2 Mode 1FD1H 1000 0000 P2 PIN Port 2 Pin Input 1FD7H XXXX XXXX P2 REG Port 2 Data Output 1FD5H 1111 1111 P3 DIR Port 3 Direction 1FDAH 1111 1111 P3_MODE Port 3 Mode 1FD8H 0000 0001 P3_PIN Port 3 Pin Input 1FDEH XXXX XXXX P3_REG Port 3 Data Output 1FDCH 1111 1111 P4 DIR Port 4 I O Direction 1FDBH 1111 1111 P4 MODE Port 4 Mode 1FD9H 0000 0000 PIN Port 4 Pin Input 1FDFH XXXX XXXX P4 REG Port 4 Data Output 1FDDH 1111 1111 PSW Program Status Word PTSSEL PTS Select 0004H 0000 0000 0000 0000 PTSSRV PTS Service 0006H 0000 0000 0000 0000 PWMO CONTROL PWM 0 Control 1FBOH 0000 0000 PWM1 CONTROL PWM 1 Control 1FB2H 0000 0000 PWM2 CONTROL PWM 2 Control 1FB4H 0000 0000 SBUF RX Serial Port Receive Buffer 1FB8H 0000 0000 C 3 8 196 80C196NU USER S MANUAL In Table C 2 Register N
261. are not directly supported can be easily implemented with two INTEGER operations See the example in DOUBLE WORD Operands on page 4 3 4 18 QUAD WORD Operands QUAD WORD is a 64 bit unsigned variable that can take on values from 0 through 264 1 The architecture directly supports the QUAD WORD operand only as the operand of the EB MOV I instruction For this operation the QUAD WORD variable must reside in the lower reg ister file and must be aligned at an address that is evenly divisible by eight 4 1 9 Converting Operands The instruction set supports conversions between the operand types The LDBZE load byte zero extended instruction converts a BYTE to a WORD CLR clear converts a WORD to a DOUBLE WORD by clearing writing zeros to the upper WORD of the DOUBLE WORD LDBSE load byte sign extended converts a SHORT INTEGER into an INTEGER EXT sign extend converts an INTEGER to a LONG INTEGER 4 1 10 Conditional Jumps The instructions for addition subtraction and comparison do not distinguish between unsigned BYTE WORD and signed SHORT INTEGER INTEGER operands However the condition al jump instructions allow you to treat the results of these operations as signed or unsigned quan tities For example the CMP compare instruction is used to compare both signed and unsigned 16 bit quantities Following a compare operation you can use the JH jump if higher instruction for unsigned operands or the JGT jump if g
262. artitions contain the lower 16 bits of the interrupt service routines addresses The CPU automatically adds FF0000H to the 16 bit vector in special purpose memory to calculate the address of the interrupt service routine and then executes the routine The peripheral transaction server PTS a microcoded hardware interrupt processor provides high speed low overhead in terrupt handling it does not modify the stack or the PSW You can configure most interrupts ex cept NMI trap and unimplemented opcode to be serviced by the PTS instead of the interrupt controller The PTS supports four special microcoded routines that enable it to complete specific tasks in much less time than an equivalent interrupt service routine can It can transfer bytes or words either individually or in blocks between any memory locations in page 00H and can generate pulse width modulated PWM signals PTS interrupts have a higher priority than standard inter rupts and may temporarily suspend interrupt service routines A block of data called the PTS control block PTSCB contains the specific details for each PTS routine see Initializing the PTS Control Blocks on page 6 17 When a PTS interrupt occurs the priority encoder selects the appropriate vector and fetches the PTS control block PTSCB 6 1 8XC196NP 80C196NU USER S MANUAL intel Interrupt Pending or PTSSRV Bit Set NMI Yes Pending No Return Priority Encoder Y
263. asheet for exact specifications is reduced to device leakage Table B 5 on page B 13 lists the values of the pins during powerdown mode If Vc is maintained above the minimum specification the special function registers SFRs and register RAM retain their data 12 5 1 Enabling and Disabling Powerdown Mode Setting the PD bit in the chip configuration register 0 CCRO 0 enables both standby and pow erdown modes Clearing it disables both modes CCRO is loaded from the chip configuration byte CCBO when the device is reset 12 5 2 Entering Powerdown Mode Before entering powerdown complete the following tasks Complete all serial port transmissions or receptions Otherwise when the device exits powerdown the serial port activity will continue where it left off and incorrect data may be transmitted or received Putall other peripherals into an inactive state To allow other devices to control the bus while the microcontroller is in powerdown assert HLDA Do this only if the routines for entering and exiting powerdown do not require access to external memory 12 7 8XC196NP 80C196NU USER S MANUAL intel After completing these tasks execute the IDLPD 2 instruction to enter powerdown mode NOTE To prevent an accidental return to full power hold the external interrupt pins EXTINT low while the device is in powerdown mode 12 5 3 Exiting Powerdown Mode The device will exit powerdown mode when either of
264. ate 92 ORB Indirect 93 ORB Indexed 94 XORB Direct 95 XORB Immediate 96 XORB Indirect A 49 8 196 80C196NU USER S MANUAL Table A 7 Instruction Opcodes Continued Hex Code Instruction Mnemonic 97 XORB Indexed 98 CMPB Direct 99 CMPB Immediate 9A CMPB Indirect 9B CMPB Indexed 9C DIVUB Direct 9D DIVUB Immediate 9E DIVUB Indirect 9F DIVUB Indexed LD Direct A1 LD Immediate A2 LD Indirect LD Indexed A4 ADDC Direct A5 ADDC Immediate A6 ADDC Indirect A7 ADDC Indexed A8 SUBC Direct A9 SUBC Immediate AA SUBC Indirect AB SUBC Indexed AC LDBZE Direct AD LDBZE Immediate AE LDBZE Indirect AF LDBZE Indexed BO LDB Direct B1 LDB Immediate B2 LDB Indirect B3 LDB Indexed B4 ADDCB Direct B5 ADDCB Immediate B6 ADDCB Indirect B7 ADDCB Indexed B8 SUBCB Direct B9 SUBCB Immediate BA SUBCB Indirect BB SUBCB Indexed BC LDBSE Direct BD LDBSE Immediate BE LDBSE Indirect BF LDBSE Indexed A 50 lel INSTRUCTION SET REFERENCE Table A 7 Instruction Opcodes Continued Hex Code Instruction Mnemonic CO ST Direct C1 BMOV C2 ST Indirect C3 ST Indexed C4 STB Direct C5 CMPL C6 STB Indirect C7 STB Indexed C8 PUSH Direct C9 PUSH Immediate CA
265. ate Addressing Immediate addressing mode accepts one immediate value as an operand in the instruction You specify an immediate value by preceding it with a number symbol An instruction can contain only one immediate value the remaining operands must be direct references The following in structions use immediate addressing ADD 340 PUSH 1234H AX lt AX 340 SP lt SP 2 MEM WORD SP 1234H DIVB AX 10 AL AX 10 AH lt AX MOD 10 4 2 3 Indirect Addressing indirect addressing mode accesses an operand by obtaining its address from a WORD regis ter in the lower register file You specify the register containing the indirect address by enclosing it in square brackets 1 The indirect address can refer to any location within the address space including the register file The register that contains the indirect address must be word aligned and the indirect address must conform to the rules for the operand type An instruction can contain only one indirect reference any remaining operands must be direct references The following in structions use indirect addressing 8XC196NP 80C196NU USER S MANUAL intel LD ADDB AL BL CX POP 4 2 3 1 AX BX AX AX lt MEM WORD AL lt BL BYTE CX MEM WORD AX lt MEM WORD SP oP lt lt SP 42 Extended Indirect Addressing Extended load and store instructions can use indirect addressing The
266. ate times The rising edge of the address latch enable ALE indicates that the device is driving an address onto the bus A19 16 and AD15 0 The device presents a valid address before ALE falls In a multiplexed system the ALE signal is used to strobe a transparent latch such as a 74AC373 which captures the address from AD15 0 and holds it while the bus controller puts data onto AD15 0 13 22 intel INTERFACING WITH EXTERNAL MEMORY Demultiplexed CLKOUT ALE A19 0 RD AD15 0 WR Multiplexed CLKOUT ALE A19 16 RD AD15 0 WR AD15 0 X xy a REDE EN TwiwH lt gt Data Address A2461 02 Figure 13 11 Timings for Multiplexed and Demultiplexed 16 bit Buses 8XC196NP 13 23 8XC196NP 80C196NU USER S MANUAL intel 13 5 3 8 bit Bus Timings Figure 13 12 shows idealized 8 bit timings for the 8XC196NP One cycle is required for an 8 bit read or write A 16 bit access requires two cycles The first cycle accesses the lower byte and the second cycle accesses the upper byte Except for requiring an extra cycle to write the bytes sep arately the timings are the same as on the 16 bit bus and the comparison between the multiplexed and demultiplexed cases is also the same The demultiplexed bus can accommodate slower mem ory devices than the multiplexed bus can 13 24 intel INTERFACING WITH EXTERNAL MEMORY Demultiplexed cour VA
267. ays an 8 bit value called PISCON Bits 5 7 select the PTS mode Figure 6 11 The function of bits 0 4 differ for each PTS mode Refer to the sections that describe each mode in detail to see the function of these bits Table 6 4 on page 6 10 lists the cycle execution times for each PTS mode 8 196 80C196NU USER S MANUAL intel Address PTSPCB 1 PTSCON The PTS control PTSCON register selects the PTS mode and sets up control functions for that mode 7 0 M2 M1 MO t 4 4 Bit Bit _ Number Mnemonic Function 7 5 M2 0 PTS Mode These bits select the PTS mode M2 1 0 0 0 0 block transfer 0 0 1 reserved 0 1 0 PWM toggle or remap 0 1 1 reserved 1 0 0 single transfer 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved t The function of this bit depends upon which mode is selected See the PTS control block description in each PTS mode section Figure 6 11 PTS Mode Selection Bits PTSCON Bits 7 5 6 6 3 Single Transfer Mode In single transfer mode an interrupt causes the PTS to transfer a single byte or word selected by the BW bit in PISCON from one memory location to another This mode is typically used with serial I O or synchronous serial I O interrupts It can also be used with the EPA to move captured time values from the event time register to internal RAM for further processing See AP 445 8 196 Peripherals A User s Point of View for application ex
268. be needed to ensure proper memory decoding takes place before a device is enabled 13 43 8XC196NP 80C196NU USER S MANUAL intel Table 13 16 AC Timing Definitions Continued Symbol Definition The 8XC196Nx Meets These Specifications Continued Multiplexed Mode AD15 8 CSx Hold after RD High Minimum time the high byte of the address in 8 bit mode will be valid after RD inactive Demultiplexed Mode A19 0 CSx Hold after RD High Minimum time the address will be valid after RD inactive BHE INST Hold after RD High Minimum time these signals will be valid after RD inactive RD High to ALE Rising Time between RD going inactive and the next ALE Useful in calculating time between RD inactive and next address valid RD High to RD Low Minimum RD inactive time TrHsH A19 0 CSx Hold after RD High Minimum time the address and chip select output are held after RD inactive RD Low to Address Float Used to calculate when the device stops driving address on the bus RD Low to CLKOUT High Maximum time between RD being asserted and CLKOUT going high Trice RD Low to CLKOUT Low Length of time from RD asserted to CLKOUT falling edge RD Low to RD High RD pulse width Multiplexed Mode AD15 8 CSx Hold after WR High Minimum time the high byte of the address 8 bit mode will be valid after W
269. ce timer and timer 1 is the opposite timer A compare event clearing setting or toggling an output pin and or resetting either timer occurs when the reference timer matches the time programmed in the event time register When capture event falling edge rising edge or an edge change on the EPAx pin occurs the reference timer value is saved in the EPA event time register EPAx TIME 6 CE Compare Enable Determines whether the EPA channel operates in capture or compare mode 0 capture mode 1 compare mode These bits apply to the EPA1 CON and CON registers only Figure 10 10 EPA Control EPAx CON Registers 10 19 8XC196NP 80C196NU USER S MANUAL intel EPAx CON Continued Address Table 10 2 on page 10 3 0 3 Reset State 00H The EPA control EPAx CON registers control the functions of their assigned capture compare channels The registers for EPAO andEPA2 are identical The registers for EPA1 and have an additional bit the remap bit This added bit bit 8 requires an additional byte so EPA1 CON and CON must be addressed as words while the others can be addressed as bytes 15 8 x 1 3 E m RM 7 0 TB CE M1 MO RE ROT ON RT 7 0 0 2 1 MO RE ROT ON RT Bit Bit Number Mnemonic Function 5 4 M1 0 EPA Mode Select In capture mode specifies the type of event that triggers an
270. crocode engine which instructs the RALU to perform operations using bytes words or double words from either the 256 byte lower register file or through a win dow that directly accesses the upper register file See Chapter 5 Memory Partitions for more information about the register file and windowing CPU instructions move from the 4 byte for the 8XC196NP or 8 byte for the 80C196NU prefetch queue in the memory controller into the RALU s instruction register The microcode engine decodes the instructions and then generates the sequence of events that cause desired functions to occur 2 3 2 Register File The register file is divided into an upper and a lower file In the lower register file the lowest 24 bytes are allocated to the CPU s special function registers SFRs and the stack pointer while the remainder is available as general purpose register RAM The upper register file contains only general purpose register RAM The register RAM can be accessed as bytes words or double words The RALU accesses the upper and lower register files differently The lower register file is always directly accessible with direct addressing see Addressing Modes on page 4 6 The upper reg ister file is accessible with direct addressing only when windowing is enabled Windowing is a technique that maps blocks of the upper register file into a window in the lower register file See Chapter 5 Memory Partitions for more information about t
271. cseg functionl push wsr Prolog code for wsr ldb wsr WSR Prolog code for wsr add varl var2 var3 Use the variables as registers ldb wsr sp Epilog code for wsr add sp 2 Epilog code for wsr Ket end KKKKKKKK mod2 KKKKKKKKKKKKKK 5 19 8XC196NP 80C196NU USER S MANUAL intel public function2 extrn WSR wsr equ 14h byte sp equ 18h word oseg varl dsw 1 var2 dsw 1 var3 dsw 1 cseg function2 push wsr Prolog code for wsr ldb wsr WSR Prolog code for wsr add varl var2 var3 ldb wsr sp Epilog code for wsr add sp 2 Epilog code for wsr ret end ck ck ck kk kk kk Sk ke Sk Sk S S S A A ko ko The following is an example of a linker invocation to link and locate the modules and to deter mine the proper windowing RL196 MOD1 0BJ MOD2 0BJ registers 100h 03ffh windowsize 32 The above linker controls tell the linker to use registers 0100 03FFH for windowing and to use a window size of 32 bytes These two controls enable windowing The following is the map listing for the resultant output module MODI by default SEGMENT MAP FOR modl MOD1 TYPE BASE LENGTH ALIGNMENT MODULE NAME RESERVED 0000H OO1AH STACK 001AH 0006H WORD KAR GAP EON 0020H 00 OVRLY 0100H 0006H WORD MOD2 OVRLY 0106H 0006H WORD MOD1 Tus EAP SEER 010CH 1F74H CODE 2080H 0011H BYTE MOD2 CODE 2091H 0011H BYTE MOD1 TE GAP CRER 20A2H DF5EH 5 20 l ntel MEMORY PARTIT
272. ctional Ports in Special function Mode Open drain Configuration Complementary Output Output Input Px MODE 1 1 1 1 Px DIR 0 0 1 1 SFDIR 0 0 1 1 SFDATA 0 1 0 1 Note 2 1 Px REG X X X 1 Q1 off on off off Q2 on off on off Note 2 off Px PIN 0 1 X Note 3 high impedance Note 4 NOTES 1 X Don t care If Px_REG is cleared Q2 is on if is set Q2 is off Px PIN contains the current value on the pin During reset and until the first write to Px MODE Q4 is on 2 3 4 intel PORTS 7 2 2 Bidirectional Port Pin Configurations Each bidirectional port pin can be individually configured to operate either as an I O pin or as a pin for a special function signal In the special function configuration the signal is controlled by an on chip peripheral or an off chip component In either configuration two modes are possible complementary output output only high impedance input or open drain output input output or bidirectional To prevent the CMOS inputs from floating the bidirectional port pins are weakly pulled high dur ing and after reset until your software writes to MODE The default values of the control reg isters after reset configure the pins as high impedance inputs with weak pull ups To ensure that the ports are initialized correctly and that the weak pull ups are turned off follow this suggested initialization sequence 1 Wri
273. ctions the REG register provides the page number Data and constants in this page are called near data and near constants NOTE The 8XC196NP allows you to change the value of EP REG to control which memory page a nonextended instruction accesses However software tools require that EP REG be equal to 00H The 80C196NU forces all nonextended data accesses to page 00H You cannot use EP REG to change pages Data outside the page specified by EP REG is called far data To access far data you must use extended instructions For extended instructions the CPU provides the page number From REG 16 bit Data Address Register Nonextended Address 23 16 15 0 From CPU 16 bit Data Address Register Extended Address 23 16 15 0 A2514 01 Figure 5 8 Formation of Extended and Nonextended Addresses The code example below illustrates the use of extended instructions to access data in page 01H EP REG EQU 1FE5H RSEG AT 1 TEMP DSW 1 RESULT DSW 1 CSEG AT OFF2080H Some code SUBB PUSHA save flags disable interrupts LD 1234 EST TEMP 010600H Store temp value in 010600H ADD RESULT TEMP 44000H do something with registers EST RESULT 010602H Store result in 010602H more eld est instructions POPA restore flags and interrupts RET more code gt DONE BR DONE END 5 24 l ntel MEMORY PARTITIONS 5 5 3 Code Fetches in the 1 Mbyte Mode 1 the MODE
274. d The falling edge of RESET turns on transistor which remains on for about 300 ns causing the pin to change rapidly to its reset state The active low level of RESET turns on transistor Q4 which weakly holds the pin high Q4 can source approximately 10 uA consult the datasheet for exact specifications Q4 remains on weakly holding the pin high until your software writes to the Px MODE register NOTE P2 7 is an exception After reset P2 7 carries the CLKOUT signal rather than being held high When CLKOUT is selected it is always a complementary output 7 4 lel PORTS Internal Bus SFDATA Q1 Pin 1500 to 2000 R1 Read Port PH1 Clock Medium Pullup Q3 Any Write to MODE A0238 04 Figure 7 1 Bidirectional Port Structure 7 5 8 196 80C196NU USER S MANUAL Table 7 4 Logic Table for Bidirectional Ports in Mode Configuration Complementary Output gor Input Px MODE 0 0 0 0 Px DIR 0 0 1 1 SFDIR X X X X SFDATA X X X X Px REG 0 1 0 1 Note 2 1 Q1 off on off off Q2 on off on off Note 2 off Px PIN 0 1 X Note 3 high impedance Note 4 NOTES 1 2 3 4 X Don t care If Px REG is cleared Q2 is on if Px REG is set Q2 is off Px PIN contains the current value on the pin During reset and until the first write to Px MODE Q4 is on Table 7 5 Logic Table for Bidire
275. d edge as valid The input frequency at which this occurs depends on the length of the interrupt service routine as well as other factors Unless the interrupt service routine includes a check for overruns this situ ation will remain the same until the device is reset or the EPAx TIME register is read The act of reading EPAx TIME allows the buffered time value to be moved into EPAx TIME This clears the buffer and allows another event to be captured Remember that the act of the transferring the buffer contents to the EPAx TIME register is what actually sets the EPAx interrupt pending bit and generates the interrupt 10 11 8XC196NP 80C196NU USER S MANUAL intel 10 4 1 2 Preventing EPA Overruns Any one of the following methods can be used to prevent or recover from an EPA overrun situa tion Clear EPAx 0 When the overwrite bit EPAx 0 is zero the EPA does not consider the captured edge until the EPAx TIME register is read and the data in the capture buffer is transferred to EPAx TIME This prevents the situation by ignoring new input capture events when both the capture buffer and EPAx TIME contain valid capture times The OVRx pending bit in EPA PEND is set to indicate that an overrun occurred Enable the OVRx interrupt and read the EPAx TIME register within the ISR If this situation occurs the overrun interrupt will be generated The OVRx interrupt will then be acknowledged and its interrupt service
276. d 80C196NU Data accesses to the register file 0000 03FFH and the SFRs 1F00 1FFFH are directed to the internal registers All other data accesses are directed to external memory 83C196NP Data accesses to the register file 0000 03FFH and the SFRs 1F00 1FFFH are directed to the internal registers Accesses to other locations are directed to external memory except as noted below Data accesses to FF2000 FF2FFFH depend on the EA input f EAf is low accesses are to external memory page OFH f EAf is high accesses are to the internal ROM page FFH 5 26 l ntel MEMORY PARTITIONS Data accesses to 002000 002FFFH depend on the REMAP bit and the EA input fremapping is disabled CCB1 2 0 accesses are external e f remapping is enabled CCB1 2 1 accesses depend EA If EA is low accesses are external REMAP is ignored IfEA is high accesses to the internal ROM 5 6 MEMORY CONFIGURATION EXAMPLES This section provides examples of memory configurations for both 64 Kbyte and 1 Mbyte mode Each example consists of a circuit diagram and a memory map that describes how the address space is implemented Chapter 13 Interfacing with External Memory discusses the interface in detail and provides additional examples 5 6 1 Example 1 Using the 64 Kbyte Mode Figure 5 9 shows a system designed for operation in the 64 Kbyte mode Code executes only from page FFH which is implem
277. d Rate Mode 0 Mode 1 2 3 Mode 0 Mode 1 2 3 9600 8515H 80A2H 0 0 15 4800 8A2BH 8144H 0 0 16 2400 9457H 828AH 0 0 1200 A8AFH 8515H 0 0 300 Note 2 9457H Note 2 0 NOTES 1 15 is always set when the internal peripheral clock is selected as the clock source for the baud rate generator 2 For mode 0 operation at 25 MHz the minimum baud rate is 381 47 BAUD VALUE 7FFFH For mode 0 operation at 300 baud the maximum internal clock frequency is 19 6608 MHz BAUD_VALUE 7FFFH C 43 8XC196NP 80C196NU USER S MANUAL intel SP CON SP CON Address 1FBBH Reset State 00H The serial port control SP CON register selects the communications mode and enables or disables the receiver parity checking and nine bit data transmission For the 80C196NU it also enables or disables the divide by two prescaler 7 0 8XC196NP PAR TB8 REN PEN M1 MO 7 0 80C196NU PRS PAR TB8 REN PEN M1 MO Bit Bit Number Mnemonic Function 7 Reserved for compatibility with future devices write zero to this bit 6t PRS Prescale This bit enables the divide by two prescaler 0 disable the prescaler 1 enable the prescaler 5 PAR Parity Selection Bit Selects even or odd parity 0 even parity 1 odd parity 4 TB8 Transmit Ninth Data Bit This is the ninth data bit that will be transmitted in mode 2 or 3 This bit is cleared after each transmission so it must be set be
278. d demultiplexed bus modes A19 16 y o Address Lines 16 19 These address lines provide address bits 16 19 during the entire external memory cycle supporting extended addressing of the 1 Mbyte address space NOTE Internally there are 24 address bits however only 20 address lines A19 0 are bonded out The internal address space is 16 Mbytes 000000 FFFFFFH and the external address space is 1 Mbyte 00000 FFFFFH The device resets to FF2080H in internal ROM or F2080H in external memory A19 16 are multiplexed with EPORT 3 0 AD15 0 y o Address Data Lines The function of these pins depend on the bus size and mode When a bus access is not occurring these pins revert to their I O port function 16 bit Multiplexed Bus Mode AD15 0 drive address bits 0 15 during the first half of the bus cycle and drives or receives data during the second half of the bus cycle 8 bit Multiplexed Bus Mode AD15 8 drive address bits 8 15 during the entire bus cycle AD7 0 drive address bits 0 7 during the first half of the bus cycle and either drive or receive data during the second half of the bus cycle 16 bit Demultiplexed Mode AD15 0 drive or receive data during the entire bus cycle 8 bit Demultiplexed Mode AD7 0 drive or receive data during the entire bus cycle AD15 8 drive the data that is currently on the high byte of the internal bus SIGNAL DESCRIPTIONS Table B 3 Signal Descriptions Continued
279. d the 1 Mbyte and 64 Kbyte operating modes Mbyte refers to the address space defined by the 20 external address lines In 1 Mbyte mode code can execute from almost anywhere in the 1 Mbyte space In 64 Kbyte mode code can execute only from the 64 Kbyte area FF0000 FFFFFFH The 64 Kbyte mode provides compatibility with software written for previous 16 bit MCS9 96 micro controllers In either mode nearly all of the 1 Mbyte address space is available for data storage Other topics covered in this chapter include the following the relationship between the 1 Mbyte address space defined by the 20 external address lines and the 16 Mbyte address space defined by the 24 internal address lines extended and nonextended data accesses awindowing technique for accessing the upper register file and peripheral special function registers SFRs with direct addressing examples of external memory configurations for the 1 Mbyte and 64 Kbyte operating modes amethod for remapping the 4 Kbyte internal ROM 83C196NP only 5 1 MEMORY MAP OVERVIEW instructions can address 16 Mbytes of memory However only 20 of the 24 address lines implemented by external pins A19 0 in demultiplexed mode or A19 16 and AD15 0 in multi plexed mode The lower 16 address data lines AD15 0 are the same as those in all other MCS 96 microcontrollers The four extended address lines A19 16 are provided by the EPORT If for example an internal 24 bit
280. d to READY Setup Maximum time the memory system has to assert READY after the device outputs the address to guarantee that at least one wait state will occur To READY Hold after CLKOUT High If maximum specification is exceeded additional wait states will occur Teivx READY Hold after CLKOUT Low Minimum hold time is always 0 ns If maximum specification is exceeded additional wait states will occur ALE Cycle Time Minimum time between ALE pulses Tnipv RD Low to Input Data Valid Maximum time the memory system has to output valid data after the device asserts RD TRLRH RD Low to RD High RD pulse width Data Valid to WR High Time between data being valid on the bus and WR going inactive Memory devices must meet this specification WR Low to WR High WR pulse width 13 27 8 196 80C196NU USER S MANUAL CLKOUT READY ALE RD AD15 0 read WR AD15 0 write BHE INST A19 16 CSx Tai vx max LH 2 Tana 21 4 2t TAVDV 2t Address Out 2t K Tavwn 2t Data Out Address Out T0013 02 13 28 Figure 13 13 READY Timing Diagram Multiplexed Mode INTERFACING WITH EXTERNAL MEMORY CLKOUT READY ALE RD AD15 0 read WR AD15 0 write BHE INST A19 0 CSx k
281. daao o lt lt lt lt lt gt lt gt lt lt lt lt lt lt lt lt lt gt xt QN XO LO x CO QN O O O O O O CO CO CO CO cO ADO 1 80 Vss NC 2 79 18 EPORT 2 RESET 3 78 19 EPORT 3 WR WRL E15 76 EA RD 0 WRH 1 ALE Voc INST Vss READY A2 m RPD A3 E ONCE A4 S8XC196NP Vss A5 A A6 F3 Vss A7 18 Voc Vss 1 A10 NC View of component as pA P3 0 CSO m 12 1 51 mounted PC board A13 P3 2 CS2 1A14 P3 3 CS3 7 15 SS F Vss P3 4 CS4 E XTAL1 P3 5 CS5 XTAL2 P3 6 EXTINT2 ss NC P2 7 CLKOUT P3 7 EXTINT3 NC P1 0 EPAO P2 6 HLDA Vcc 2 5 HOLD CO t LO 00 O O tr 10 CO C CO CO CO CO CO b MB Mb Raa OOs o gt gt gt wu A Feat Se ae 54455 a r4 ams nz a A2349 03 Figure B 2 8XC196NP 100 lead QFP Package 8 196 80C196NU USER S MANUAL 82 DI A16 EPORT O 81 A17 EPORT 1 o Q lt 1 99 98 AD2 96 95 ADS 94 AD6 93 AD7 92 A Voc 91 B AD8 90 Vss 89 ADO 88 AD10 87 011 86 AD1
282. de with slow memories As shown in Figure 13 24 a delay of 2t occurs in the first bus cycle follow ing a chip select output change and the first write cycle following a read cycle 13 40 lel INTERFACING WITH EXTERNAL MEMORY CLKOUT ALE RD AD15 0 read WR AD15 0 write BHE INST A19 16 CSx 21 TRHLH 2t Tavpv 2t TAVWL 4 2t C en 2 5 C E T0010 02 Figure 13 24 Deferred Bus cycle Mode Timing Diagram 80C196NU 13 41 8 196 80C196NU USER S MANUAL 13 9 2 Explanation of AC Symbols Each symbol consists of two pairs of letters prefixed by for time The characters in a pair indicate a signal and its condition respectively Symbols represent the time between the two sig nal condition points For example is the time between signal L ALE condition L Low intel and signal RD condition L Low Table 13 15 defines the signal and condition codes Table 13 15 AC Timing Symbol Definitions Signals Conditions Ai Address H HOLD S CSx H High B BHE HA HLDA W WRH WRL L Low CLKOUT L ALE X XTAL1 V Valid D Data Q Data Out Y READY X No Longer Valid G Buswidth R RD Z Floating Address bus demultiplexed mode or address data bus multiplexed mode 13 9 3 AC Timing Definitions Table 13 16 define
283. de 1 operation The only difference is that the data consists of 9 bits so 11 bit packages are transmitted and received During a reception the RI flag and the RI interrupt pending bit are set just after the end of the stop bit During a transmission the TI flag and the TI interrupt pending bit are set at the beginning of the stop bit The ninth bit can be used for parity or multiprocessor communications 8 7 8XC196NP 80C196NU USER S MANUAL intel 8 3 2 5 Multiprocessor Communications Modes 2 and 3 are provided for multiprocessor communications In mode 2 the serial port sets the RI interrupt pending bit only when the ninth data bit is set In mode 3 the serial port sets the RI interrupt pending bit regardless of the value of the ninth bit The ninth bit is always set in ad dress frames and always cleared in data frames One way to use these modes for multiprocessor communication is to set the master processor to mode 3 and the slave processors to mode 2 When the master processor wants to transmit a block of data to one of several slaves it sends out an address frame that identifies the target slave Be cause the ninth bit is set an address frame interrupts all slaves Each slave examines the address byte to check whether it is being addressed The addressed slave switches to mode 3 to receive the data frames while the slaves that are not addressed remain in mode 2 and are not interrupted 8 4 PROGRAMMING THE SERIAL PORT To use the
284. de enabled See Table 3 2 Software can clear this flag hardware does not clear it Figure 3 2 Accumulator Control and Status STAT Register 8XC196NP 80C196NU USER S MANUAL intel Table 3 2 Effect of SME and FME Bit Combinations SME FME Description 0 0 Sets the OVF and STOVF flags if the sign bits of the accumulator and the addend the number to be added to the contents of the accumulator are equal but the sign bit of the result is the opposite 0 1 Shifts the addend the number to be added to the contents of the accumulator left by one bit before adding it to the accumulator Sets the OVF and STOVF flags if the sign bits of the accumulator and the addend are equal but the sign bit of the result is the opposite Accumulates a signed integer value up or down to saturation and sets the STSAT flag Positive saturation changes the accumulator value to 7FFFFFFFH negative saturation changes the accumulator value to 80000000H Accumulation proceeds normally after saturation which means that the accumulator value can increase from a negative saturation or decrease from a positive saturation Shifts the addend the number to be added to the contents of the accumulator left by one bit before adding it to the accumulator Accumulates a signed integer value up or down to saturation and sets the STSAT flag Positive saturation changes the accumulator value to 7FFFFFFFH nega
285. des Hex Code Instruction Mnemonic 00 SKIP 01 CLR 02 NOT 03 NEG 04 XCH Direct 05 DEC 06 EXT 07 INC 08 SHR 09 SHL 0A SHRA 0B XCH Indexed 0C SHRL 00 SHLL SHRAL NORML 10 Reserved 11 CLRB 12 NOTB 13 NEGB 14 XCHB Direct 15 DECB 16 EXTB 17 INCB 18 SHRB 19 SHLB 1A SHRAB 1B XCHB Indexed 1C EST Indirect 1D EST Indexed 1E ESTB Indirect 1F ESTB Indexed 20 27 SJMP 28 2F SCALL 30 37 JBC 38 3F JBS 40 AND Direct 3 ops 41 AND Immediate 3 ops 42 AND Indirect 3 ops 43 AND Indexed 3 ops A 47 8 196 80C196NU USER S MANUAL Table A 7 Instruction Opcodes Continued Hex Code Instruction Mnemonic 44 ADD Direct 3 ops 45 ADD Immediate 3 ops 46 ADD Indirect 3 ops 47 ADD Indexed 3 ops 48 SUB Direct 3 ops 49 SUB Immediate 3 ops 4A SUB Indirect 3 ops 4B SUB Indexed 3 ops 4C MULU Direct 3 ops 4D MULU Immediate 3 ops 4E MULU Indirect 3 ops 4F MULU Indexed 3 ops 50 ANDB Direct 3 ops 51 ANDB Immediate 3 ops 52 ANDB Indirect 3 ops 53 ANDB Indexed 3 ops 54 ADDB Direct 3 ops 55 ADDB Immediate 3 ops 56 ADDB Indirect 3 ops 57 ADDB Indexed 3 ops 58 SUBB Direct 3 ops 59 SUBB Immediate 3 ops 5A SUBB Indirect 3
286. divides the contents of the destination word piyvyB operand by the contents of the source byte Seared ano unsigned arithmetic It pn 100111 aa baop wreg the quotient into the low order byte i e the byte with the lower address of the destination operand and the remainder into the high order byte The following two statements are performed concurrently low byte DEST lt DEST SRC high byte DEST lt DEST MOD SRC wreg baop PSW Flag Settings Z N C V VT ST pese DJNZ DECREMENT AND JUMP IF NOT ZERO Decrements the value of the byte operand by DJNZ 1 If the result is 0 control passes to the next sequential instruction If the result is not 0 11100000 breg disp the instruction adds to the program counter the offset between the end of this instruction NOTE The displacement disp is sign and the target label effecting the jump The extended to 24 bits offset must be in the range of 128 to 127 COUNT lt COUNT 1 if COUNT 0 then PC lt PC 8 bit disp end if breg cadd PSW Flag Settings Z N C V VT ST intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format DJNZW DECREMENT AND JUMP IF NOT ZERO WORD Decrements the value of the word by 1 If the result is 0 control pa
287. dress space The following instructions use ex tended indirect addressing with autoincrement ELD AX lt MEM WORD EX lt EX 2 AL lt MEM_BYTE EX lt EX 2 ELDB AL EX 4404 04 4 ee EST EX MEM WORD EX lt AX MEM WORD EX lt MEM WORD EX 2 ESTB AL EX BYTE EX AL BYTE EX lt MEM 2 4 8 intel PROGRAMMING CONSIDERATIONS 4 2 3 4 Indirect Addressing with the Stack Pointer You can also use indirect addressing to access the top of the stack by using the stack pointer as the WORD register in an indirect reference The following instruction uses indirect addressing with the stack pointer PUSH SP duplicate top of stack SP amp SP 2 4 2 4 Indexed Addressing Indexed addressing calculates an address by adding an offset to a base address There are three variations of indexed addressing short indexed long indexed and zero indexed Both short and long indexed addressing are used to access a specific element within a structure Short indexed addressing can access up to 255 byte locations long indexed addressing can access up to 65 535 byte locations and zero indexed addressing can access a single location An instruction can con tain only one indexed reference any remaining operands must be direct references 4 2 4 1 Short indexed Addressing In a short indexed instruction you specify the offset as an 8 bit constant a
288. dressing and they cannot be windowed WARNING The contents or functions of these locations may change with future device revisions in which case a program that relies on one or more of these locations might not function properly l ntel MEMORY PARTITIONS 5 2 4 External Memory Several partitions in pages and FFH and all of pages 01H OEH are assigned to external memory see Table 5 1 Data can be stored in any part of this memory Instructions can be stored in any part of this memory in 1 Mbyte mode but can be stored only in page FFH in 64 Kbyte mode Memory Configuration Examples on page 5 27 contains examples of memory configu rations in the two modes Chapter 13 Interfacing with External Memory describes the external memory interface and shows additional examples of external memory configurations 5 2 2 Program and Special purpose Memory Program memory and special purpose memory occupy a 4 Kbyte memory partition from FF2000 FF2FFFH For the 80C196NP and 80C196NU this partition resides in external memory external addresses 2000 2 For the 83C196NP this partition resides in on chip ROM in page and it can also be mapped to page see Remapping Internal ROM 83C196NP Only on page 5 22 5 2 2 1 Program Memory in Page FFH Three partitions in page FFH can be used for program memory FF0100 FFIFFFH in external memory external addresses F0100 F1FFFH FF2080 FF2FFFH 80
289. e 5 4 Because the areas in the lower register file do not overlap two windows can be in effect at the same time For example you can activate a 128 byte window using WSR and a 64 byte window using WSRI Figure 5 4 These two windows occupy locations 0040 00FFH in the lower register file leav ing locations 001A 003FH for use as general purpose register RAM locations 0018 0019H for the stack pointer or general purpose register RAM and locations 0000 0017H for the CPU SFRs 128 byte Window 128 byte Window WSR 17H WSR 17H 64 byte Window 0340H WSR1 2DH Window in OOFFH WSR Window in Lower Register File 0080H Lower Register File 007FH WSR1 Window in 0040H Lower Register File 003FH 0000H 8XC196NP 80C196NU A3053 02 Figure 5 4 Windowing 5 13 8XC196NP 80C196NU USER S MANUAL intel 5 3 1 Selecting a Window The window selection register Figure 5 5 has two functions The HLDEN bit WSR 7 enables and disables the bus hold protocol see Chapter 13 Interfacing with External Memory it is unrelated to windowing The remaining bits select a window to be mapped into the top of the low er register file Window selection register 1 Figure 5 6 selects a second window to be mapped into the middle of the 80C 196NU s lower register file Table 5 8 provides a quick reference of WSR values for windowing the peripheral SFRs Table 5 9 on page 5 15 lists the WSR values for
290. e 8 4 Serial Port Frames for Mode 1 The transmit and receive functions are controlled by separate shift clocks The transmit shift clock starts when the baud rate generator is initialized The receive shift clock is reset when a start bit high to low transition is received Therefore the transmit clock may not be synchronized with the receive clock although both will be at the same frequency The transmit interrupt TI and receive interrupt RI flags in SP STATUS are setto indicate com pleted operations During a reception both the RI flag and the RI interrupt pending bit are set just before the end of the stop bit During a transmission both the TI flag and the TI interrupt pending bit are set at the beginning of the stop bit The next byte cannot be sent until the stop bit is sent Use caution when connecting more than two devices with the serial port in half duplex i e with one wire for transmit and receive The receiving processor must wait for one bit time after the RI flag is set before starting to transmit Otherwise the transmission could corrupt the stop bit causing a problem for other devices listening on the link 8 6 intel SERIAL 1 0 SIO PORT 8 3 2 2 Mode 2 Mode 2 is the asynchronous ninth bit recognition mode This mode is commonly used with mode 3 for multiprocessor communications Figure 8 5 shows the data frame used in this mode It con sists of a start bit 0 nine data bits LSB first and a stop bit 1
291. e C 18 WSR Settings and Direct Addresses for Windowable SFRs Continued 32 byte Windows 64 byte Windows 128 byte Windows Register Memory 00 0 00 0 0080 00FFH Mnemonic Location z WSR address WSR address WSR Address P4_DIR 1FDBH 7EH OOFBH 3FH 00DBH 1FH 00DBH P4 MODE 1FD9H 7EH 00F9H 00D9H 1FH 00D9H P4 PIN 1FDFH 7EH OOFFH 3FH OODFH 1FH OODFH P4_REG 1FDDH 7EH 00FDH 00DDH 1FH 00DDH PWMO CONTROL 1FBOH 7DH OOFOH 3EH OOFOH 1FH 00BOH PWM1 CONTROL 1FB2H 7DH 00F2H O0F2H 1FH 00B2H PWM2_CONTROL 1FB4H 7DH 00 00F4H 1FH 00B4H SBUF_RX 1FB8H 7DH 00 8 00 8 1 00 8 SBUF TX 1FBAH 7DH 00FAH 3EH OOFAH 1FH 00BAH SP BAUD 1FBCH 7DH 00FCH OOFCH 1FH 00 1FBBH 7DH OOFBH 3EH OOFBH 1FH 00 SP STATUS 1FB9H 7DH 00F9H 00 9 1FH 00B9H T1CONTROL 1F90H 7CH OOFOH 3EH 00DOH 1FH 0090H T2CONTROL 1F94H 7CH 00 00D4H 1FH 0094H TIMER1 1F92H 7CH 00F2H 00D2H 1FH 0092H 2 1 96 7CH OOF6H 3EH 00D6H 1FH 0096H Must be addressed as a word C 51 8 196 80C196NU USER S MANUAL intel WSR1 WSR1 Address 0015H 80C196NU Reset State 00H Window selection 1 WSR1 register selects a 32 or 64 byte segment of the upper register file or peripheral SFRs to be windowed into the middle of the lower register f
292. e and window number See Table 5 8 on page 5 15 or Table 5 9 on page 5 15 Figure 5 6 Window Selection 1 WSR1 Register Table 5 8 Selecting a Window of Peripheral SFRs WSR or WSR1 Value WSR or WSR1 Value WSR Value for Peripheral for 32 byte Window for 64 byte Window 128 byte Window 00E0 00FFH or 0060 007 00C0 00FFH or 0040 007 0080 00FFH EPORT Ports 1 4 PWM SIO 7DH EPA and Timers 7CH 3EH 1FH Chip selects 4 5 7BH Chip selects 0 3 7AH 3DH 1EH t For the 8XC196NP the EPORT SFRs are memory mapped SFRs They must be accessed with indirect indexed or extended addressing they cannot be windowed Table 5 9 Selecting a Window of the Upper Register File Register RAM WSR or WSR1 Value WSR or WSR1 Value WSR Value Locations for 32 byte Window for 64 byte Window for 128 byte Window Hex 00 0 00 or 0060 007 00 0 0 or 0040 007FH 0080 00FFH 03E0 03FF 5FH 03C0 03DF 5EH 2FH 03A0 03BF 5DH 0380 039F 5CH 2 17H 8XC196NP 80C196NU USER S MANUAL intel Table 5 9 Selecting a Window of the Upper Register File Continued Register RAM WSR or WSR1 Value WSR or WSR1 Value WSR Value Locations for 32 byte Window for 64 byte Window for 128 byte Window Hex 00E0 00FFH or 0060 007 00 0 0 or 0040 007FH 0080 0360 037F 5BH 0340
293. e interrupt mask 1 OVRO INT MASK1 register Figure 10 11 EPA Interrupt Mask EPA MASK Register 10 7 DETERMINING EVENT STATUS In compare mode an interrupt pending bit is set each time a match occurs on an enabled event even if the interrupt is specifically masked in the mask register In capture mode an interrupt pending bit is set each time a programmed event is captured and the event time moves from the capture buffer to the EPAx TIME register If the capture buffer is full when an event occurs an overrun interrupt pending bit is set Timer overflows and capture overruns also set interrupt pending bits You can mask the interrupts by clearing bits in EPA MASK Figure 10 11 INT MASK and INT MASKI If an interrupt is masked software can still poll the interrupt pending registers to determine whether an event has occurred 10 22 intel EVENT PROCESSOR ARRAY EPA EPA PEND Address 1F9EH Reset State AAH When hardware detects a pending EPA3 0 overrun interrupt OVR3 0 it sets the corresponding bit in the EPA interrupt pending EPA PEND register OVRO and OVR1 are multiplexed to share one bit OVRO 1 the INT PEND1 register Similarly OVR2 and OVR3 are multiplexed to share another bit OVR2 3 in the INT PEND 1 register 7 0 OVR3 OVR2 OVR1 OVRO Bit Number Function 7 5 3 1 Reserved These bits are undefined 6 4 2 0 Any set bit indicates
294. e of the DEST operand CLR wreg DEST lt 0 00000001 wreg PSW Flag Settings Z N C V VT ST 1 0 0 0 CLRB CLEAR BYTE Clears the value of the DEST operand CLRB breg DEST lt 0 00010001 breg PSW Flag Settings Z N C V 5 1 0 0 CLRC CLEAR CARRY FLAG Clears the carry flag ceo CLRC 11111000 PSW Flag Settings Z N C V VT ST 0 CLRVT CLEAR OVERFLOW TRAP FLAG Clears the overflow trap flag CLRVT VT lt 0 11111100 PSW Flag Settings Z N C V VT ST 0 CMP COMPARE WORDS Subtracts the source DEST SRC word operand from the destination word CMP wreg waop 100010aa waop wreg 8XC196NP 80C196NU USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format CMPB COMPARE BYTES Subtracts the source DEST SRC byte operand from the destination byte CMPB breg bao operand The flags are altered but the A operands remain unaffected If a borrow 10011028 breg occurs the carry flag is cleared otherwise it is set DEST SRC PSW Flag Settings 2 V VT ST CMPL COMPARE LONG Compares the DEST SRC magnitudes of two double word long CMPL Direg Slreg operands The operands are specified using the direct addressing mode The flags are 11000101 5 Dlreg altered but the operands remain unaffected If a borrow occurs the carry flag is cleared o
295. e operand from the destination byte SUBB breg baop operand stores the result in the destination operand and sets the carry flag as the 011110aa baop breg complement of borrow DEST lt DEST SRC PSW Flag Settings Z N V VT ST Vi iviv 7111 SUBB SUBTRACT BYTES Subtracts the first DEST SRC1 SRC2 3 operands source byte operand from the second stores SUBB Dbreg Sbreg baop the result in the destination operand and sets the carry flag as the complement of borrow 010110aa Sbreg Dbreg DEST lt SRC1 SRC2 PSW Flag Settings 2 V VT ST T SUBC SUBTRACT WORDS WITH BORROW DEST SRC Subtracts the source word operand from the SUBC wreg waop destination word operand If the carry flag was clear SUBC subtracts 1 from the result 101010aa waop wreg It stores the result in the destination operand and sets the carry flag as the complement of borrow DEST DEST SRC 1 0 PSW Flag Settings Z N C V VT ST Livi i7 1 SUBCB SUBTRACT BYTES WITH BORROW DEST SRC Subtracts the source byte operand from the SUBCB breg baop destination byte operand If the carry flag was clear SUBCB subtracts 1 from the result It 101110aa baop breg stores the result in the destination operand and sets the carry flag as the complement of b
296. e to match the external system This is accomplished by writing appropriate config uration data into 4 MODE Writing to MODE not only configures the pins but also turns off the transistor that weakly holds the pins high Q4 in Figure 7 1 on page 7 5 For this reason even if port 4 is to be used as it is configured at reset you should still write data into MODE intel PORTS 7 2 5 Design Considerations for External Interrupt Inputs To configure a port pin that serves as an external interrupt input you must set the corresponding bits in the configuration registers Px_DIR Px_MODE and Px_REG However setting the Px_MODE bit causes the device to set the corresponding interrupt pending bit indicating an in terrupt request To configure P2 2 EXTINTO 2 4 P3 6 EXTINT2 and P3 7 EXTINT3 we recommend the following sequence to prevent the false interrupt request 1 Disable interrupts by executing the DI instruction 2 Set the DIR bit 3 Set the Px_MODE bit 4 Set the REG bit 5 Clear the INT PEND and INT PENDI bits 6 Enable interrupts optional by executing the EI instruction 7 3 EPORT The EPORT is a four bit bidirectional memory mapped I O port in the 8XC196NP but a stan dard I O port in the 80C196NU For the 8XC196NP it must be accessed using indirect or indexed addressing and it cannot be windowed For the 80C196NU it can be windowed This port pro vides the address si
297. ect the bank of memory that stores the high odd byte Figure 13 10 on page 13 22 illustrates use of the standard mode in a 16 bit system In this example WR writes words to the 16 bit flash memory To write individual bytes you can use the decoding logic in Figure 13 18 or use the write strobe mode 13 34 intel INTERFACING WITH EXTERNAL MEMORY To write single bytes on a 16 bit bus requires separate low byte and high byte write signals WRL WRH Figure 13 18 shows a sample circuit that combines WR BHE and ad dress bit O AO to produce these signals This additional logic is unnecessary however In the write strobe mode WRL and WRH are available at the device s external pins WRH WHE WRL AO A0104 01 Figure 13 18 Decoding WRL and WRH The write strobe mode eliminates the need to externally decode high byte and low byte write sig nals to external 16 bit memory on a 16 bit bus When the write strobe mode is selected the WR WRL pin operates as WRL and the BHE WRHf pin operates as WRH In the 16 bit bus mode WRL is asserted for all low byte writes even addresses and all word writes and WRH is asserted for all high byte writes odd addresses and all word writes In the 8 bit bus mode WRH and are asserted for both even and odd addresses see Table 13 14 13 35 8XC196NP 80C196NU USER S MANUAL intel Figure 13 19 illustrates the use of the write strobe mode in
298. ects the clock source The lower 15 bits represent BAUD VALUE an unsigned integer that determines the baud rate The maximum BAUD VALUE is 32 767 7FFFH In asynchronous modes 1 2 and 3 the minimum BAUD VALUE is 0000H when using the internal clock source f and 0001H when using T1CLK In synchronous mode 0 the minimum BAUD VALUE is 0001H for transmissions and 0002H for receptions 15 8 CLKSRC BV14 BV13 BV12 BV11 BV10 BV9 BV8 7 0 BV7 BV6 BV5 4 BV3 BV2 BV1 BVO Bit Bit 2 Number Mnemonic Function 15 CLKSRC Serial Port Clock Source This bit determines whether the serial port is clocked from an internal or an external source 0 signal on the T1CLK pin external source 1 2 internal operating frequency f 14 0 BV14 0 Baud Rate These bits constitute the BAUD VALUE Use the following equations to determine the BAUD VALUE for a given baud rate Synchronous mode 0 BAUD VALUE ei r IH Baud Rate x 2 Baud Rate Asynchronous modes 1 2 and 3 f T1CLK BAUD VALUE 1 or D Baud Rate x 16 Baud Rate x 8 For mode 0 receptions the BAUD VALUE must be 0002H or greater Otherwise the resulting data in the receive shift register will be incorrect C 42 intel REGISTERS SP BAUD Table C 16 SP BAUD Values When Using the Internal Clock at 25 MHz SP BAUD Register Value Note 1 96 Error Bau
299. ed If your application does not use powerdown mode leave this pin unconnected Calculate the value of the capacitor using the formula found on page 12 11 PWR Digital Supply Voltage Connect each Vg pin to the digital supply voltage GND Digital Circuit Ground Connect each pin to ground through the lowest possible impedance path 8XC196NP 80C196NU USER S MANUAL intel Table 11 1 Minimum Required Signals Continued Signal Description XTAL1 Input Crystal Resonator or External Clock Input Input to the on chip oscillator internal phase locked loop circuitry 80C196NU and the internal clock generators The internal clock generators provide the peripheral clocks CPU clock and CLKOUT signal When using an external clock source instead of the on chip oscillator connect the clock input to XTAL1 The external clock signal must meet the V specification for XTAL1 see datasheet XTAL2 Inverted Output for the Crystal Resonator Output of the on chip oscillator inverter Leave XTAL2 floating when the design uses a external clock source instead of the on chip oscillator 11 1 1 Unused Inputs For predictable performance it is important to tie unused inputs to Voc or Otherwise they can float to a mid voltage level and draw excessive current Unused interrupt inputs may generate spurious interrupts if left unconnected 11 1 2 I O Port Pin Co
300. ed event occurred When an EPA channel is configured for compare mode write the compare event time to this register C 24 Table C 9 EPAx TIME Addresses and Reset Values Register Address Reset Value EPAO TIME 1F82H 0000H EPA1 TIME 1F86H 0000H EPA2 TIME 1F8AH 0000H TIME 1F8EH 0000H intel REGISTERS INT MASK INT MASK Address 0008H i Reset State 00H The interrupt mask INT MASK register enables or disables masks individual interrupt requests The El and Dl instructions enable and disable servicing of all maskable interrupts INT MASK is the low byte of the processor status word PSW therefore PUSHF or PUSHA saves this register on the stack and POPF or POPA restores it 7 0 EPAO RI TI EXTINT1 EXTINTO OVRTM2 OVRTM1 Bit Number Function 7 3 Setting a bit enables the corresponding interrupt 1 0 The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector 0 FF200EH RI SIO Receive FF200CH TI SIO Transmit FF200AH FF2008H EXTINTO EXTINTO pin FF2006H OVRTM2 Timer 2 Overflow Underflow FF2002H OVRTM1 Timer 1 Overflow Underflow FF2000H 2 Reserved for compatibility with future devices write zero to this bit C 25 8XC196NP 80C196NU USER S MANUAL intel INT MASK1 INT MASK
301. efined 1 5 TICLK 8 2 10 2 B 11 TICONTROL C 51 C 54 intel TIDIR 10 2 B 11 T2CLK 10 2 B 11 T2CONTROL C 51 C 54 T2DIR 10 2 B 11 Technical support 1 11 Terminology 1 3 TIJMP instruction A 2 A 44 A 51 A 57 A 64 Timer counters 2 11 10 5 10 6 and PWM 10 12 10 13 10 14 10 15 cascading 10 6 configuring pins 10 2 count rate 10 6 resolution 10 6 SFRs 10 3 See also EPA TIMERI C 51 C 54 2 C 51 C 54 Timing HLDA 13 30 HOLD 13 30 instruction execution 60 61 internal 2 7 2 9 interrupt latency 6 7 6 10 6 23 PTS cycles 6 10 READY 13 27 SIO port mode 0 8 5 SIO port mode 1 8 6 SIO port mode 2 8 7 SIO port mode 3 8 7 TRAP instruction 6 5 2 A 45 A 52 57 A 64 A 65 TRAP interrupt 6 4 TXD 8 2 B 11 and SIO port mode 0 8 4 U UART 2 11 8 1 Unimplemented opcode interrupt 4 14 6 4 6 5 6 7 Units of measure defined 1 5 Universal asynchronous receiver and transmitter See UART V Vo 11 1 B 12 Vss 11 1 B 12 INDEX Wait states 13 5 13 26 13 30 for CCBO fetch 13 17 Window selection register See WSR WSRI Windows 5 1 5 13 5 21 addressing 5 18 and addressing modes 5 21 base address 5 16 5 18 examples 5 18 5 21 nonwindowable locations 5 19 selecting 5 14 setting up with linker loader 5 19 table of 5 15 5 17 Word accesses and write control signals 13 34 WORD defined 4 3 World Wide Web 1 11 WR 13 5 B 12 afte
302. egister file to anywhere in the address space It operates in extended indirect and extended indexed modes 4 2 ADDRESSING MODES The instruction set uses four basic addressing modes direct immediate indirect with or without autoincrement indexed short long or zero indexed The stack pointer can be used with indirect addressing to access the top of the stack and it can also be used with short indexed addressing to access data within the stack The zero register can be used with long indexed addressing to access any memory location Extended variations of the indirect and indexed modes support the extended load and store in structions An extended load instruction moves a word ELD or a byte ELDB from any location in the address space into the lower register file An extended store instruction moves a word EST or a byte ESTB from the lower register file into any location in the address space An instruction can contain only one immediate indirect or indexed reference any remaining oper ands must be direct references This section describes the addressing modes as they are handled by the hardware An understand ing of these details will help programmers to take full advantage of the architecture The assembly language hides some of the details of how these addressing modes work Assembly Language Addressing Mode Selections on page 4 11 describes how the assembly language handles direct and indexed addressing mode
303. egisters and Chip Configuration Bytes on page 13 14 13 17 8XC196NP 80C196NU USER S MANUAL intel After RESET is deasserted the following pins are initialized The P2 7 CLKOUT pin operates as CLKOUT as during reset Be sure that the CLKOUT signal does not damage external hardware The P3 0 CSO pin operates as CSO which is asserted for the CCB fetches If you plan to use the P3 0 pin as an input it must be reconfigured from its post reset operation as an output The BHE WRH pin operates as BHE The pin operates as WR Bus hold function is disabled internally WSR 7 0 The READY P5 6 pin is active that is the chip responds to external requests for additional wait states The INST pin is low deasserted The AD15 0 pins are active The following port pins are weakly held high P1 7 0 P2 6 P2 4 0 P3 7 1 and P4 7 0 EPORT 3 0 pins are forced high regardless of the state of the EA pin Following reset you should set the stack pointer and initialize the chip select outputs using the procedure in Example of a Chip select Setup on page 13 12 13 5 BUS WIDTH AND MULTIPLEXING The external bus can operate with a 16 bit or 8 bit data bus and with a multiplexed or demulti plexed address data bus Figure 13 8 shows the external bus signals during operation in the four combinations of bus width and multiplexing 18 18 INTERFACING WITH EXTERNAL MEMORY Bus Control 8XC196
304. em the data is on AD15 0 In an 8 bit system the data is on AD7 0 AD15 8 drive the data currently on the high byte of the internal bus In multiplexed mode bottom half of Figure 13 8 and Figure 13 9 both A19 0 and AD15 0 drive the address A19 0 drive the address throughout the entire bus cycle For a 16 bit bus width AD15 0 drive the address for the first half of the bus cycle and drive or receive data during the second half In the 8 bit case AD15 8 drive the address during the entire bus cycle 13 20 intel INTERFACING WITH EXTERNAL MEMORY In multiplexed mode with the full address on the bus for only half of the cycle the external de vice has less time to receive it and to respond As a result for the same bus cycle length 4t a multiplexed system requires a faster external device unless wait states are added to the bus cy cle Although the multiplexed mode has this disadvantage it is useful for compatibility with de vices designed for multiplexed operation In a 16 bit system left side of Figure 13 8 and Figure 13 9 one data word can be transferred over AD15 0 in a single bus cycle In an 8 bit system one data word is transferred as two bytes over AD7 0 in successive bus cycles and AD15 8 drive the upper eight address bits for the entire bus cycle The flexibility of the chip select unit enables you to specify the bus width the number of wait states and a multiplexed or demultiplexed bus for each of the six chip select
305. emonic Function 7 6 1 To guarantee device operation write ones to these bits 5 4 WS1 0 Wait States These two bits control the number of wait states that are used for an external fetch of CCB1 wso WS1 0 0 zero wait states 0 1 one wait state 1 0 two wait states 1 1 three wait states 3 DEMUX Select Demultiplexed Bus Selects the demultiplexed bus mode for an external fetch of CCB1 0 2 multiplexed address and data are multiplexed on AD15 0 1 demultiplexed data only on AD15 0 2 Write control Mode Selects the write control mode which determines the functions of the BHE WRH and WR WRL pins for external bus cycles 0 write strobe mode the BHE WRH pin operates as WRH and the WR WRL pin operates as 1 standard write control mode the BHE WRH pin operates as BHE and the WR WRL pin operates as WR 1 BW16 Buswidth Control Selects the bus width for an external fetch of CCB1 0 8 bit bus 1 16 bit bus 0 PD Powerdown Enable Enables or disables the IDLPD 2 and IDLPD 3 instructions When enabled the IDLPD 2 instruction causes the microcontroller to enter powerdown mode and for the 80C196NU only the IDLPD 3 instruction causes the microcontroller to enter standby mode 0 disable powerdown and standby modes 1 enable powerdown and standby modes If your design uses powerdown or standby mode set this bit when you program the CCBs If it does not clearing this bit
306. emory bus and the ex ternal address data bus The bus controller receives memory access requests from either the RALU or the prefetch queue queue requests always have priority This queue is transparent to the RALU and your software NOTE When using logic analyzer to debug code remember that instructions are preloaded into the prefetch queue and are not necessarily executed immediately after they are fetched When the bus controller receives a request from the queue it fetches the code from the address contained in the slave PC The slave PC increases execution speed because the next instruction byte is available immediately and the processor need not wait for the master PC to send the ad dress to the memory controller If a jump interrupt call or return changes the address sequence the master PC loads the new address into the slave PC then the CPU flushes the queue and con tinues processing 2 5 8XC196NP 80C196NU USER S MANUAL intel The extended program counter EPC is an extension of the slave PC The EPC generates the up per eight address bits for extended code fetches and outputs them on the extended addressing port EPORT Because only four EPORT pins are implemented only the lower four address bits are available See Chapter 5 Memory Partitions for additional information The memory controller includes a chip select unit with six chip select outputs for selecting an ex ternal device during an external bus cycle
307. en this procedure is entered at run time the stack will contain the parameters in the following order param3 low word of param2 high word of param2 undefined paraml return address Stack Pointer If a procedure returns a value to the calling code as opposed to modifying more global variables the result is returned in the temporary storage space TMPREGO in this example starting at is viewed as either an 8 16 32 64 bit variable depending on the type of the procedure The standard calling convention adopted by the C programming language has several key fea tures Procedures can always assume that the eight or sixteen bytes of register file memory starting at ICH can be used as temporary storage within the body of the procedure Code that calls a procedure must assume that the procedure modifies the eight or sixteen bytes of register file memory starting at ICH Code that calls a procedure must assume that the procedure modifies the processor status word PSW condition flags because procedures do not save and restore the PSW Function results from procedures are always returned in the variable TMPREGO The C programming language allows the definition of interrupt procedures which are executed when a predefined interrupt request occurs Interrupt procedures do not conform to the rules of normal procedures Parameters cannot be passed to these procedures and they cannot return re sul
308. ency Input to the State Time Divide by two Circuit 12 5 MHz 160 ns 25 MHz 80 ns 50 MHz 40 ns The following formulas calculate the frequency of PH1 and PH2 the duration of a state time and the duration of a clock period t PH1 in MHz PH2 State Time in us IP 1 Because the device can operate at many frequencies this manual defines time requirements such as instruction execution times in terms of state times rather than specific measurements Datasheets list AC characteristics in terms of clock periods t For the 80C196NU Table 2 3 details the relationships between the input frequency Fs the configuration of PLLENI and PLLEN2 the operating frequency f the clock period t and state times Figure 2 6 illustrates the timing relationships between the input frequency 1 the operating frequency f and CLKOUT signal with each of the three valid PLLENx pin configurations Since the maximum operating frequency is 50 MHz only a 12 5 MHz external clock frequency allows all three clock modes 2 9 8XC196NP 80C196NU USER S MANUAL intel Table 2 3 Relationships Between Input Frequency Clock Multiplier and State Times FyraLi f t Frequency PLLEN2 1 Multiplier Input Frequency to Clock State Time on XTAL1 the Divide by two Circuit Period 50 MHz t 00 1 50 MHz 20 ns 40 ns 00 1 25 MHz 40 ns 80 ns 25 MHz 10 2 50 MHz 20 ns 40 ns 00 1 12 5
309. ent false interrupts first configure the port pins and then clear the interrupt pending registers before glo bally enabling interrupts See Design Considerations for External Interrupt Inputs on page 7 11 The interrupt detection logic can generate an interrupt if a momentary negative glitch occurs while the input pin is held high For this reason interrupt inputs should normally be held low when they are inactive 6 3 3 Multiplexed Interrupt Sources overrun errors for the four capture compare modules are multiplexed into two interrupt pairs OVRO 1 channels 0 and 1 and OVR2 3 channels 2 and 3 Generally PTS interrupt service is not useful for multiplexed interrupts because the PTS cannot readily determine the interrupt source Your interrupt service routine should read the EPA PEND register to determine the source of the interrupt and to ensure that no additional interrupts are pending before executing the return instruction Chapter 10 Event Processor Array EPA discusses the EPA interrupts detail 6 3 4 End of PTS Interrupts When the PTSCOUNT register decrements to zero at the end of a single transfer or block transfer routine hardware clears the corresponding bit in the PTSSEL register which disables PTS service for that interrupt It also sets the corresponding PTSSRV bit requesting an end of PTS interrupt An end of PTS interrupt has the same priority as a corresponding standard interrupt The interrupt c
310. ented by the 64 Kbyte flash memory The 32 Kbyte RAM in the upper half of page OOH stores near data Table 5 12 on page 5 28 lists the memory addresses for this example For memory map details see Table 5 1 on page 5 4 CE Page 00H A15 0 Flash 64Kx8 32Kx8 Code amp Data Data FF0000 008000 OOFFFFH 8XC196NP NU AD7 0 A2474 02 Figure 5 9 A 64 Kbyte System With an 8 bit Bus 80C196NP and 80C196NU The flash memory which implements page FFH holds the special purpose memory FF2000 FF207FH code and far constants 5 27 8XC196NP 80C196NU USER S MANUAL intel 83C196NP only Locations FF2000 FF2FFFH which store code and special purpose memory are implemented by internal ROM Data accesses to locations FF2000 FF2FFFH are directed to the flash memory if EA is low and to internal ROM if EA t is high Locations FF2000 FF2FFFH can be remapped to page by setting the REMAP bit CCB1 2 An access to the remapped area 002000 002FFFH is directed to ROM if EA is high and to external memory if EA is low With remapping enabled REMAP 1 and EA high the far constants in the special purpose memory can be accessed as near constants in page 00H Table 5 12 Memory Map for the System in Figure 5 9 Address Description FFFFFFH FF3000H External flash memory code or far constants FF2FFFH Program memory 80C196NP and 80C19
311. er execution of each line of the example code LDB Px_DIR 00011111B LDB Px_MODE 00000000B LDB Px_REG 10010011B intel PORTS Table 7 8 Port Pin States After Reset and After Example Code Execution Action or Code Resulting Pin States Px7 Px6 5 Px 4 Px3 2 Px 1 Px 0 Reset wk1 wk1 wk1 wk1 wk1 wk1 wk1 wk1 LDB Px_DIR 00011111B 1 1 1 wk1 wk1 wk1 wk1 wk1 LDB Px_MODE 00000000B 1 1 1 HZ1 HZ1 HZ1 HZ1 HZ1 LDB REG 10010011 1 0 0 HZ1 0 0 HZ1 HZ1 t wk1 weakly pulled high HZ1 high impedance actually a 1 with an external pull up 7 2 4 Bidirectional Port Considerations This section outlines special considerations for using the pins of these ports Port 1 Port 2 P2 2 EXTINTO P2 4 EXTINT 1 P2 5 HOLD After reset your software must configure the device to match the external system This is accomplished by writing appropriate config uration data into MODE Writing to MODE not only configures the pins but also turns off the transistor that weakly holds the pins high Q4 in Figure 7 1 on page 7 5 For this reason even if port 1 is to be used as it is configured at reset you should still write data into Pl MODE After reset your software must configure the device to match the external system This is accomplished by writing appropriate config data into P2 MODE Writing to P2 MODE not only
312. er of the following conditions are true e theinternal oscillator is the clock source e the phase locked loop PLL circuitry 80C196NU only is enabled see PLLEN2 1 signal description The capacitor causes a delay that enables the oscillator and PLL circuitry to stabilize before the internal CPU and peripheral clocks are enabled The capacitor is not required if your application uses powerdown mode and if both of the following conditions are true external clock input is the clock source e the phase locked loop circuitry 80C196NU only is disabled If your application does not use powerdown mode leave this pin unconnected Calculate the value of the capacitor using the formula found on page 12 11 RXD y o Receive Serial Data In modes 1 2 and 3 RXD receives serial port input data In mode O it functions as either an input or an open drain output for data RXD is multiplexed with P2 1 T1CLK Timer 1 External Clock External clock for timer 1 Timer 1 increments or decrements on both rising and falling edges of T1CLK Also used in conjunction with T1DIR for quadrature counting mode and External clock for the serial I O baud rate generator input program selectable T1CLK is multiplexed with P1 4 T2CLK Timer 2 External Clock External clock for timer 2 Timer 2 increments or decrements on both rising and falling edges of T2CLK Also used in conjunction with T2DIR for quadrature counting mode T2CLK is multiplexed with P1 6
313. erand into ESTB breg treg the destination rightmost operand m 27 f ext indirect 00011110 treg breg This instruction allows you to move data from the lower register file to anywhere in the 16 Xt indexed 00011111 treg disp low Mbyte address space disp high disp ext breg ext indirect DEST SRC i DEST SRC 24 bit di NOTE For 20 bit addresses the offset extindexed K i must be the range of 524287 PSW Flag Settings 107924288 Z N C V VI ST EXT SIGN EXTEND INTEGER INTO LONG INTEGER Sign extends the low order word ExT of the operand throughout the high order word of the operand if DEST 15 1 then high word DEST lt OFFFFH else high word DEST lt 0 end_if PSW Flag Settings Z N C V VT ST 0 0 00000110 8XC196NP 80C196NU USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format EXTB SIGN EXTEND SHORT INTEGER INTO INTEGER Sign extends the low order byte EXTB ofthe operand throughout the high order byte of the operand 00010110 wreg if DEST 7 1 then high byte DEST else high byte DEST lt 0 end if wreg PSW Flag Settings Z N C V VT ST 0 0 IDLPD IDLE POWERDOWN Depending on the 8 bit value of the KEY operand this instruction I
314. erations 8 6 interrupts 8 5 8 8 8 15 mode 0 8 4 8 5 mode 1 8 5 8 6 mode 2 8 5 8 6 8 7 mode 3 8 5 8 6 8 7 multiprocessor communications 8 7 8 8 overrun error 8 14 programming 8 8 receive interrupt flag 8 15 receiver 8 1 selecting baud rate 8 8 8 12 Index 10 intel SFRs 8 2 signals 8 2 status 8 13 8 15 transmit interrupt TI flag 8 15 transmitter 8 1 See also mode 0 mode 1 mode 2 mode 3 port 2 SJMP instruction A 2 41 A 47 A 53 A 57 64 SKIP instruction 2 41 47 59 67 Software addressing modes 4 11 conventions 4 11 4 13 device reset 11 11 interrupt service routines 6 14 linking subroutines 4 13 protection 4 14 13 32 trap interrupt 6 4 6 5 6 7 SP BAUD C 51 C 54 SP CON 8 9 C 51 C 54 Special instructions A 59 A 67 Special operating modes SFRs 12 2 Special purpose memory 5 2 5 5 5 6 SP STATUS 8 14 C 51 C 54 ST instruction A 2 A 42 A 51 A 56 A 63 Stack instructions A 55 A 62 Stack pointer 5 11 13 11 and subroutine call 5 11 initializing 5 12 Standby mode 12 6 State time defined 2 9 STB instruction A 2 A 42 A 51 A 56 A 63 Sticky bit ST flag 4 5 A 4 A 5 A 25 A 26 SUB instruction A 3 A 42 A 48 A 53 A 60 SUBB instruction 3 A 43 A 48 A 49 A 53 60 SUBC instruction A 3 A 43 50 A 53 60 SUBCB instruction 3 A 43 A 50 A 53 60 Subroutines linking 4 13 nested 5 12 T t d
315. errupts pragma interrupt epa0 interrupt EPAO INT void 0 interrupt unsigned int time_value 10 25 8 196 80C196NU USER S MANUAL In time value 0 time must read to prevent overrun void init timerl tlcontrol COUNT ENABLE COUNT UP CLOCK INTERNAL DIVIDE BY 1 void main void unsigned int time_value Initialize the timers and interrupts before using the EPA init_timerl init epa0 enable Globally enable interrupts while 1 loop forever wait for interrupts to occur 10 8 3 EPA PWM Output Program lel This example C program demonstrates the generation of a PWM signal using the EPA s PWM toggle mode see PWM Modes on page 6 26 and shows how to service the interrupts with the PTS The PWM signal in this example has a 50 duty cycle pragma model EX include 80c196np h define PTS_BLOCK_BASE 0x98 Create typedef template for the PWM_TOGGLE mode control block typedef struct PWM_toggle_ptscb_t unsigned char unused unsigned char ptscon void pts ptr unsigned int constantl unsigned int constant2 PWM toggle ptscb This locates the PTS block mode control block in register ram This control block may be located at any quad word boundary register PWM toggle ptscb PWM toggle CB 3 pragma locate PWM toggle CB 3 PTS BLOCK BASE The PTS vector must contain the address of t
316. ers are located memory mapped address space Memory mapped registers must be accessed with indirect or indexed addressing they cannot be windowed AII ports can provide low speed input output pins or serve alternate functions Table 7 1 provides an overview of the device I O ports The remainder of this chapter describes the ports in more detail and explains how to configure the pins The chapters that cover the associated peripherals discuss using the pins for their special functions Table 7 1 Device Ports Port Bits Type Direction Associated Peripheral s Port 1 8 Standard Bidirectional EPA and timers Port 2 8 Standard Bidirectional SIO interrupts bus control clock gen Port 3 8 Standard Bidirectional Chip select unit interrupts Port 4 4 Standard Bidirectional PWM EPORT 4 bein E NF Bidirectional Extended address lines 7 2 BIDIRECTIONAL PORTS 1 4 bidirectional ports are very similar in both circuitry and configuration ports use Schmitt triggered input buffers for improved noise immunity Table 7 2 lists the bidirectional port pins with their special function signals and associated peripherals 8XC196NP 80C196NU USER S MANUAL intel Table 7 2 Bidirectional Port Pins Port Pin Special function Special function Associated Signal s Signal Type Peripheral P1 0 EPAO yo EPA P1
317. es Highest Priority Interrupt Encoder Highest Priority PTS Interrupt Yes No Reset INT PEND x Bit Reset PTSSRV x Reset INT PEND x Execute 1 PTS Bit Bit Microcoded Decrement PTSCOUNT Pe ce on Stack LJMP to Return ISR Execute Interrupt Service Routine Clear PTSSEL x Bit POP PC from Stack Set PTSSRV x Bit Return Return 0320 02 Figure 6 1 Flow Diagram for PTS and Standard Interrupts 6 2 intel STANDARD AND PTS INTERRUPTS Figure 6 1 illustrates the interrupt processing flow In this flow diagram INT 5 repre sents both the INT MASK and INT 5 registers and INT represents both the INT PEND and INT PENDI registers 6 2 INTERRUPT SIGNALS AND REGISTERS Table 6 1 describes the external interrupt signals and Table 6 2 describes the control and status registers for both the interrupt controller and PTS Table 6 1 Interrupt Signals Port Pin Interrupt Signal Type Description P2 2 P2 4 P3 6 P3 7 EXTINTO l External Interrupts EXTINT1 In normal operating mode a rising edge on EXTINTx sets the EXTINT2 EXTINTx interrupt pending bit EXTINTx is sampled during phase 2 CLKOUT high The minimum high time is one state time In standby and powerdown modes asserting the signal for at least 50 ns causes the device to resume normal operation The interrupt need not be enabled but the pin must be configured
318. es and the number of wait BUSCONS HOCH states inserted into each bus cycle Figure 13 1 illustrates the device s calculation of a chip select output CSx for a given external memory address The 12 most significant bits of the external address are compared XORed bit wise with the 12 least significant bits BASE19 8 of the ADDRCOM register If all of the bits match CSx is asserted Additionally if some bits do not match CSx is still asserted if for each non matching bit in ADDRCOMx the corresponding bit in ADDRMSKx is cleared The 12 least significant bits are named MASK 19 8 for their function in masking bits BASE19 8 External Address ADDRCOMx ADDRMSKx 19 8 7 0 15 1211 0 15 1211 0 bit x CSx A2386 02 Figure 13 1 Calculation of a Chip select Output 13 6 intel INTERFACING WITH EXTERNAL MEMORY 13 3 1 Defining Chip select Address Ranges This section describes the ADDRCOMx and ADDRMSKx registers and how to set them up for a desired address range The ADDRCOMs x register Figure 13 2 and ADDRMS Kx register Fig ure 13 3 control the assertion of each chip select output CSx The BASE19 8 bits in the ADDRCOMXx register determine the base address of the address range The 19 8 bits in the ADDRMSKx register determine the size of the address range x 0 5 ADDRCOMx Address Reset State The address compare ADDRCOMx register specifies the base lowest address of the address
319. es and Reset Values Register Address Reset Value P1 REG 1FD4H FFH P2 REG 1FD5H FFH P3 REG 1FDCH FFH P4 REG 1FDDH FFH C 33 8XC196NP 80C196NU USER S MANUAL intel PSW PSW no direct access The processor status word PSW actually consists of two bytes The high byte is the status word which is described here the low byte is the INT MASK register The status word contains one bit PSW 1 that globally enables or disables servicing of all maskable interrupts one bit PSW 2 that enables or disables the peripheral transaction server PTS and six Boolean flags that reflect the state of a user s program The status word portion of the PSW cannot be accessed directly To access the status word push the value onto the stack PUSHF then pop the value to a register POP test reg The PUSHF and PUSHA instructions save the PSW in the system stack and then clear it POPF and POPA restore it 15 8 2 V VT PSE ST See INT MASK on page C 25 Bit Bit i Function Number Mnemonic uneto 7 Z Zero Flag This flag is set to indicate that the result of an operation was zero For multiple precision calculations the zero flag cannot be set by the instruc tions that use the carry bit from the previous calculation e g ADDC SUBC However these instructions can clear the zero flag This ensures that the zero flag will reflect the result of the entire opera
320. ese operations a DOUBLE WORD variable must reside in the lower register file and must be aligned at an address that is evenly divisible by four The address of a DOUBLE WORD is that of its least significant byte the even byte address The least significant word of the DOUBLE WORD is always in the lower address even when the data is in the stack This means that the most significant word must be pushed into the stack first DOUBLE WORD operations that are not directly supported can be easily implemented with two WORD operations For example the following sequences of 16 bit operations perform a 32 bit addition and a 32 bit subtraction respectively ADD REG1 REG3 2 operand addition ADDC 2 4 SUB REG1 REG3 2 operand subtraction SUBC REG2 REG4 4 3 8XC196NP 80C196NU USER S MANUAL intel 4 1 7 Operands A LONG INTEGER is a 32 bit signed variable that can take on values from 2 147 483 648 231 through 2 147 483 647 2311 The architecture directly supports LONG INTEGER operands only as the operand in shift operations as the dividend in 32 by 16 divide operations and as the product of 16 by 16 multiply operations For these operations a LONG INTEGER variable must reside in the lower register file and must be aligned at an address that is evenly di visible by four The address of a LONG INTEGER is that of its least significant byte the even byte address LONG INTEGER operations that
321. eserved NOTE Using any SFR as a base or index register for indirect or indexed operations can cause unpredictable results because external events can change the contents of SFRs Also because some SFRs are cleared when read consider the implications of using an SFR as an operand in a read modify write instruction e g XORB 5 2 4 Register File The register file is divided into an upper register file and a lower register file Figure 5 3 The upper register file consists of general purpose register RAM The lower register file contains ad ditional general purpose register RAM along with the stack pointer SP and the CPU special function registers SFRs 8 196 80C196NU USER S MANUAL Page 00H General purpose Register RAM Address 0100H 00FFH 0000H Address 03FFH 0100H OOFFH 001AH 0019H 0018H 0017H 0000H A0301 02 Figure 5 3 Register File Memory Map Table 5 6 on page 5 11 lists the register file memory addresses The RALU accesses the lower register file directly without the use of the memory controller It also accesses a windowed loca tion directly see Windowing on page 5 13 Only the upper register file and the peripheral SFRs be windowed Registers in the lower register file and registers being windowed can be accessed with direct addressing NOTE The register file must not contain code An attempt to execute an instruction from a location
322. eset same timer X 1 X X X 0 1 1 Reset opposite timer NOTES bitis not used X bit may be used but has no effect on the described operation These bits cause other oper ations to occur 10 18 intel EVENT PROCESSOR ARRAY EPA EPAx CON Address Table 10 2 on page 10 3 0 3 Reset State 00H The EPA control EPAx CON registers control the functions of their assigned capture compare channels The registers for EPAO andEPA2 are identical The registers for EPA1 and have an additional bit the remap bit This added bit bit 8 requires an additional byte so EPA1 CON and CON must be addressed as words while the others can be addressed as bytes 15 8 1 3 RM 7 0 TB CE M1 MO RE ROT ON RT 7 0 x 0 2 TB CE M1 MO RE ROT ON RT Function 15 97 Reserved always write as zeros gt RM Remap Feature wi remap feature applies to the compare mode of the EPA1 and EPA3 When the remap feature of EPA1 is enabled EPA capture compare channel 0 shares output pin EPA1 with EPA capture compare channel 1 When the remap feature of EPA3 is enabled EPA capture compare channel 2 shares output pin EPA3 with EPA capture compare channel 3 0 remap feature disabled 1 feature enabled 7 TB Time Base Select Specifies the reference timer 0 timer 1 is the reference timer and timer 2 is the opposite timer 1 timer 2 is the referen
323. ettings Z N C V VT ST POP waop 110011 aa waop A 33 8XC196NP 80C196NU USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format POPA POP ALL This instruction is used instead of POPF to support the eight additional POPA interrupts It pops two words off the stack and places the first word into the INT MASK1 WSR register pair and the second word into the PSW INT MASK register pair This instruction increments the SP by 4 Interrupt calls cannot occur immediately following this instruction INT MASK1 WSR lt SP SP lt SP 2 PSW INT_MASK lt SP SP lt lt SP 2 11110101 PSW Flag Settings Z N C V VT ST POP FLAGS Pops the word on top of the stack and places it into the PSW Interrupt POPF calls cannot occur immediately following this instruction 11110011 PSW lt SP SP lt SP 2 PSW Flag Settings Z N C V VT ST PUSH PUSH WORD Pushes the word operand onto the stack PUSH SP lt SP 2 110010aa waop SP lt DEST PSW Flag Settings Z N C V VT ST A 34 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format PUSHA
324. ettings Z N C V VT ST TIJMP TBASE INDEX MASK 11100010 INDEX MASK TBASE NOTE TIJMP multiplies OFFSET by two to provide for word alignment of the jump table A 44 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format TRAP SOFTWARE TRAP This instruction causes an interrupt call that is vectored through TRAP location FF2010H The operation of this instruction is not affected by the state of the 11110111 interrupt enable flag 1 in the PSW Interrupt calls cannot occur immediately following this NOTE This instruction is not supported instruction by assemblers The TRAP 64 Kbyte mode instruction is intended for use by SP lt SP 2 development tools These tools SP lt may not support user application PC lt 2010H of this instruction 1 Mbyte mode SP lt SP 4 SP lt PC PC lt 0 2010 PSW Flag Settings Z N C V VI ST XCH EXCHANGE WORD Exchanges the value of DEST SRC the source word operand with that of the XCH wreg waop destination word operand i 00000100 waop wreg direct DEST lt gt SRC 00001011 waop wreg indexed PSW Flag Settings Z N C V VI ST XCHB EXCHANGE BYTE Exchanges the value of DEST SRC the source byte operand with that of the XCHB breg des
325. exing for all external bus cycles that access address range x 7 0 DEMUX BW16 WS1 WSO Bit Bit Function Number Mnemonic 7 DEMUX Address Data Multiplexing This bit specifies the address data multiplexing on AD15 0 for all external accesses to the address range assigned to chip select output x 0 multiplexed 1 demultiplexed 6 BW16 Bus Width This bit specifies the bus width for all external accesses to the address range assigned to chip select output x 0 8 bits 1 16 bits 5 2 Reserved for compatibility with future devices write zeros to these bits 1 0 WS1 0 Wait States These bits specify the number of wait states for all external accesses to the address range assigned to chip select output x WS1 WSO Wait States 0 0 0 0 1 1 1 0 2 1 1 3 Table C 7 BUSCONx Addresses and Reset Values Register Address Reset Value BUSCONO 1F44H 03H BUSCON 1 1F4CH 00H BUSCON2 1F54H 00H BUSCONS 1F5CH 00H BUSCON4 1F64H 00H BUSCON5 1F6CH 00H intel REGISTERS CCRO CCRO no direct access The chip configuration 0 CCRO register enables or disables powerdown and standby 80C196NU only modes and selects the write control mode It also contains the bus control parameters for fetching chip configuration byte 1 7 0 1 1 WS1 WSO DEMUX BHE BW16 PD Bit Bit Number Mn
326. f a CPU write to EP REG is immediately visible on the pin During nonextended data accesses REG contains the value of the memory page that is to be accessed For compatibility with software tools clear the REG bit for any EPORT pin that is configured as extended address signal MODE x set 80C196NU Only For nonextended data accesses the 80C196NU forces the page address to 00H You cannot change pages by modifying REG 7 2 PINO Bit Bit 4 Number Mnemonic Function 7 4 Reserved always write as zeros 3 0 0 Extended Address Port Pin x Output If EPORT x is to be used as an output write the data that itis to drive out If EPORT x is to be used as an input set this bit For the 8XC196NP if EPORT x is to be used as an address line write the correct value for the memory page to be accessed by nonextended instructions The 80C196NU forces the page address to 00H You cannot change pages by modifying EP REG 8 196 80C196NU USER S MANUAL EPA MASK intel EPA MASK Address Reset State 1F9CH AAH The EPA interrupt mask EPA MASK register enables or disables masks the multiplexed EPA3 0 overrun interrupts OVR3 0 7 0 OVR3 OVR2 OVR1 OVRO Bit Bit 3 Number Mnemonic Function 7 5 3 1 Reserved for compatibility with
327. f the interrupt is enabled the device executes the in terrupt service routine then fetches and executes the instruction following the IDLPD 2 instruc tion If the interrupt is disabled masked the device fetches and executes the instruction following the IDLPD 2 instruction and the pending bit remains set until the interrupt is serviced or software clears the pending bit 12 8 intel SPECIAL OPERATING MODES Internal Powerdown Signal EXTINTx Ev x d NE o Y RPD 2 a aa 9 5 20 159 01 Figure 12 3 Power up and Powerdown Sequence When Using an External Interrupt When using an external interrupt signal to exit powerdown mode we recommend that you con nect the external component shown in Figure 12 4 to the RPD pin The discharging of the capac itor causes a delay that allows the oscillator and phase locked loop circuitry to stabilize before the internal CPU and peripheral clocks are enabled MCS 96 Microcontroller A2389 02 Figure 12 4 External RC Circuit 12 9 8XC196NP 80C196NU USER S MANUAL intel During normal operation before entering powerdown mode an internal pull up holds the RPD pin at Voc When an external interrupt signal is asserted the internal oscillator circuitry is enabled and turns on a weak internal pull down The resistance of the internal pull down should be approximately 10 This weak pull down causes
328. fect of SME and FME Bit Combinations esses C 7 ADDRCOM x Addresses and Reset C 8 ADDRMSKx Addresses and Reset Values sss C 9 BUSCONx Addresses and Reset Values essem 10 EPAx CON Addresses and Reset C 23 EPAx TIME Addresses and Reset C 24 DIR Addresses and Reset nnne C 30 MODE Addresses and Reset C 31 Special function Signals for Ports 1 4 essem 3 PIN Addresses and Reset C 32 REG Addresses and Reset C 33 PWMx CONTROL Addresses and Reset C 38 SP BAUD Values When Using the Internal Clock at 25 2 C 43 TIMERx Addresses and Reset een C 48 WSR Settings and Direct Addresses for Windowable C 49 WSR1 Settings and Direct Addresses for Windowable 5 C 52 intel Guide to This Manual intel CHAPTER 1 GUIDE TO THIS MANUAL This manual describes the 8XC196NP and 80C196NU embedded microcontrollers It is intended for use by both software and hardware designers familiar with the principles of microcontrollers Th
329. fetches The 8KC196NP s prefetch queue is four bytes while the 80C196NU s is eight bytes The 8XC196NP gives higher priority to instruction fetches than to data fetches while the 80C196NU gives higher priority to data accesses than to instruction fetches 5 5 1 Fetching Instructions The 24 bit program counter Figure 5 7 consists of the 8 bit extended program counter EPC concatenated with the 16 bit master program counter PC It holds the address of the next in struction to be fetched The page number of the instruction is in the EPC In 1 Mbyte mode the EPC can have any 8 bit value However only the four LSBs of the EPC are implemented exter nally as EPORT pins A19 16 This means that in the 1 Mbyte mode the device can fetch code from any page in the 1 Mbyte address space and FFH FFH overlays OFH In 64 Kbyte mode the EPC is fixed at which limits program memory to page and EPC PC 23 16 15 0 A2513 03 Figure 5 7 The 24 bit Program Counter 5 5 2 Accessing Data Internally data addresses have 24 bits Figure 5 8 on page 5 24 The lower 16 bits are supplied by the 16 bit data address register The upper 8 bits the page number come from different sourc es for nonextended and extended instructions Operation on page 7 12 describes how the page number is output to the EPORT pins 5 23 8XC196NP 80C196NU USER S MANUAL intel For nonextended instru
330. fore SBUF TX is written When CON is set this bit takes on the even parity value 3 REN Receive Enable Setting this bit enables the receiver function of the RXD pin When this bit is set a high to low transition on the pin starts a reception in mode 1 2 or 3 In mode 0 this bit must be clear for transmission to begin and must be set for reception to begin Clearing this bit stops a reception in progress and inhibits further receptions 2 PEN Parity Enable In modes 1 and 3 setting this bit enables the parity function This bit must be cleared if mode 2 is used When this bit is set TB8 takes the parity value on transmissions With parity enabled STATUS 7 becomes the receive parity error bit 1 0 M1 0 Mode Selection These bits select the communications mode M1 MO 0 0 mode 0 0 1 mode 1 1 0 mode 2 1 1 mode 3 This bit is reserved on the 8XC196NP For compatibility with future devices write zero to this bit C 44 intel REGISTERS SP STATUS SP STATUS Address 1FB9H Reset State OBH The serial port status SP STATUS register contains bits that indicate the status of the serial port 7 0 RPE RB8 TI FE TXE OE Bit Bit Function Number Mnemonic 7 RPE RB8 Received Parity Error Received Bit 8 RPE is set if parity is disabled SP_CON 2 0 and the ninth data bit received is high RB8 is set if parity is enabled SP_CON
331. g a lowercase italic character represents more than one register For example the x in Px REG indicates that the register name refers to any of the port data registers Certain bits are described as reserved bits In illustrations reserved bits are indicated with a dash These bits are not used in this device but they may be used in future implementations To help ensure that a current software design is compatible with future imple mentations reserved bits should be cleared given a value of 0 or left in their default states unless otherwise noted Do not rely on the values of reserved bits consider them undefined Signal names are shown in upper case When several signals share a common name an individual signal is represented by the signal name followed by a number For example the EPA signals are named EPAO EPA1 2 etc Port pins are represented by the port abbre viation a period and the pin number e g P1 0 P1 1 a range of pins is represented by 2 e g P1 4 0 represents five port pins P1 4 P1 3 P1 2 P1 1 P1 0 A pound symbol appended to signal name identifies an active low signal GUIDE TO THIS MANUAL t Lowercase t represents the internal operating period See Internal Timing units of measure A DCV Kbytes kHz Mbytes MHz ms mW ns pF W V uA uF us uw on page 2 7 for details The following abbreviations are used to represent uni
332. g is undefined after the instruction is executed DEST SRC1 x SRC2 11111110 010111aa baop breg wreg PSW Flag Settings Z N C V VT ST 2 MULU MULTIPLY WORDS UNSIGNED Multiplies DEST SRC 2 operands the source and destination word operands MULU waop using unsigned arithmetic and stores the 32 bit result into the destination double word 011011 waop Ireg operand The sticky bit flag is undefined after the instruction is executed DEST lt DEST x SRC PSW Flag Settings Z N C V VT ST MULU MULTIPLY WORDS UNSIGNED Multiplies DEST SRC1 SRC2 3 operands the two source word operands using MULU wreg waop unsigned arithmetic and stores the 32 bit result into the destination double word 010011 waop wreg Ireg operand The sticky bit flag is undefined after the instruction is executed NOTE 8XC196NU only A destination DEST lt SRC1 x SRC2 address in the range 00H 0FH enables the multiply accumulate PSW Flag Settings function When set bit 3 of the destination address causes the 2 NIC LST accumulator to be cleared before the results of the multiply are added to the contents of the accu mulator For example if the desti nation address is 08H the accumulator is cleared and then the results of the multiply are added However if the destination
333. g of the positive and negative whole numbers and zero 16 bit signed variable with values from 2312 through 42 P The 24 bit address that the microcontroller generates See also external address The module responsible for handling interrupts that are to be serviced by interrupt service routines that you provide Also called the programmable interrupt controller The total delay between the time that an interrupt is generated not acknowledged and the time that the device begins executing the interrupt service routine or PTS routine A software routine that you provide to service a standard interrupt See also PTS routine A location in special purpose memory that holds the starting address of an interrupt service routine Glossary 3 8XC196NP 80C196NU USER S MANUAL intel ISR LONG INTEGER LSB MAC maskable interrupts MSB multiplexed bus multiply accumulate n channel FET n type material near constants near data nonmaskable interrupts Glossary 4 See interrupt service routine A 32 bit signed variable with values from o through 42 Least significant bit of a byte or least significant byte of a word See multiply accumulate interrupts except unimplemented opcode software trap and NMI Maskable interrupts can be disabled masked by the individual mask bits in the interrupt mask registers and their servicing can be disabled by the global interrupt enable bit Each
334. ge could not have 4000H as base address for example because 4000H is not on a 32 Kbyte boundary Example of a Chip select Setup on page 13 12 shows another example of setting up the chip select unit 13 3 2 Controlling Wait States Bus Width and Bus Multiplexing For each chip select output address range the bus control register BUSCONx Figure 13 4 de termines the wait states the bus width and the address data multiplexing BUSCONx Address Table 13 7 0 5 Reset State For the address range assigned to chip select x the bus control BUSCON register specifies the number of wait states the bus width and the address data multiplexing for all external bus cycles that access address range x 7 0 DEMUX BW16 WS1 WSO Bit Bit Number Mnemonic Function 7 DEMUX Address Data Multiplexing This bit specifies the address data multiplexing on AD15 0 for all external accesses to the address range assigned to chip select x output 0 multiplexed 1 demultiplexed 6 BW16 Bus Width This bit specifies the bus width for all external accesses to the address range assigned to chip select x output 0 8 bits 1 16 bits 5 2 Reserved for compatibility with future devices write zeros to these bits 1 0 WS1 0 Wait States These bits specify the number of wait states for all external accesses to the address range assigned to chip select x output WS1 WSO Wait
335. gnal Name Type Description 5 Reset A level sensitive reset input to and open drain system reset output from the micro controller Either a falling edge on RESET or an internal reset turns on a pull down transistor connected to the RESET pin for 16 state times In the powerdown standby and idle modes asserting RESET causes the chip to reset and return to normal operating mode After a device reset the first instruction fetch is from FF2080H or F2080H in external memory For the 80C196NP and 80C196NU the program and special purpose memory locations FF2000 FF2FFFH reside in external memory For the 83C196NP these locations can reside either in external memory or in internal ROM RPD Return from Powerdown Timing pin for the return from powerdown circuit If your application uses powerdown mode connect a capacitor between RPD and Vss if either of the following conditions is true e the internal oscillator is the clock source e the phase locked loop PLL circuitry 80C196NU only is enabled see PLLEN2 1 signal description The capacitor causes a delay that enables the oscillator and PLL circuitry to stabilize before the internal CPU and peripheral clocks are enabled The capacitor is not required if your application uses powerdown mode and if both of the following conditions are true an external clock input is the clock source e the phase locked loop circuitry 80C196NU only is disabl
336. gnals necessary to support extended addressing If one or more extended ad dress pins are unnecessary in an application the unused port pins can be used for I O Figure 7 2 shows a block diagram of the EPORT Table 7 9 lists the EPORT pins with their extended address signals Table 7 10 lists the registers that affect the function and indicate the status of EPORT pins Table 7 9 EPORT Pins Port Pin rr eign Signal Type EPORT 0O A16 EPORT 1 A17 EPORT 2 A18 y o EPORT 3 A19 y o 8XC196NP 80C196NU USER S MANUAL intel Table 7 10 EPORT Control and Status Registers Mnemonic Address Description DIR 1FESH EPORT Direction In mode each bit of EP DIR controls the direction of the corre sponding pin Clearing a bit configures a pin as a complementary output setting a bit configures a pin as either an input or an open drain output Open drain outputs require external pull ups Any pin that is configured for its extended address function is forced to the complementary output mode except during reset hold idle powerdown and standby Standby mode is available only on the 80C196NU EP MODE 1FE1H EPORT Mode Each bit of EP MODE controls whether the corresponding pin functions as a standard port pin or as an extended address signal Setting a bit configures a pin as an extended address signal clearing a bit configures a pin as a standard I O port pin
337. gure 3 1 resides at locations Read from or write to the accumulator register as two words at locations and OEH ACC 0x Address x 0 2 80C196NU Reset State 00H The 32 bit accumulator register 0x resides at locations OC OFH You can read from or write to the accumulator register as two words at locations OCH and OEH 80C196NU 15 8 Accumulator Value word 1 high byte 7 0 ACC 02 Accumulator Value word 1 low byte 15 8 Accumulator Value word 0 high byte 7 0 ACC 00 Accumulator Value word 0 low byte Rumba Function 15 0 Accumulator Value You can read this register to determine the current value of the accumulator You can write to this register to clear or preload a value into the accumulator Figure 3 1 Accumulator ACC 0x Register intel ADVANCED MATH FEATURES 3 4 ACCUMULATOR CONTROL AND STATUS REGISTER ACC STAT The STAT register controls the operating mode and reflects the status of the accumulator The mode bits FME and SME are effective only for signed multiplication Table 3 2 describes the 80C196NU s operation with each of the four possible configurations of these bits ACC STAT Address OBH 80C196NU Reset State 00H The accumulator control and status STAT register enables and disables fractional and saturation modes and contains three status flags that indicate the status of the accumulator s
338. hase locked loop is dis abled on the 80C196NU the PWM period is 6 88 us and the maximum PWM frequency is 145 3 kHz 10 14 intel EVENT PROCESSOR ARRAY EPA 10 4 2 4 Generating the Highest speed PWM Output You can generate a highest speed pulse width modulated output with a pair of EPA channels and a dedicated timer counter The first channel toggles the output when the timer value matches EPAx TIME and at some later time the second channel toggles the output again and resets the timer counter This restarts the cycle No interrupts are required resulting in the highest possible speed Software must calculate and load the appropriate EPAx TIME values and load them at the correct time in the cycle in order to change the frequency or duty cycle With this method the resolution of the EPA selected by the TxCONTROL registers see Figure 10 8 on page 10 16 and Figure 10 9 on page 10 17 determines the maximum PWM output fre quency Resolution is the minimum time required between consecutive captures or compares When the input frequency on XTALI is 25 MHz and the phase locked loop is disabled on the 80C196NU a 160 ns resolution results in a maximum PWM of 6 25 MHz 10 5 PROGRAMMING THE EPA AND TIMER COUNTERS This section discusses configuring the port pins for the EPA and the timer counters describes how to program the timers and the capture compare channels and explains how to enable the EPA interrupts 10 5 1 Configuring the EPA
339. he PTS control block pragma pts toggle CB 3 0 3 Sample PTS control block initialization sequence 10 26 intel EVENT PROCESSOR ARRAY EPA void Init PWM toggle PTS3 void disable disable all interrupts disable_pts disable the PTS interrupts PWM_toggle_CB_3 constant2 127 toggle CB 3 constantl 127 PWM toggle CB 3 pts ptr void amp EPAO TIME PWM toggle CB 3 ptscon 0x42 Sample code that could be used to generate a PWM with an EPA channel setbit pl reg 0 1 init output clrbiti pl dir 0x1 to output setbit pl mode 0x1 set special function setbit ptssel 0x8 setbit int mask 0x0 void main void Init PWM toggle PTS3 0 epal con 0x78 toggle timerl compare re enable epal timer 127 tlcontrol 0xC2 enable timer up 1 microsecond 16 MHz enable pts while 1 10 27 intel 1 Minimum Hardware Considerations intel CHAPTER 11 MINIMUM HARDWARE CONSIDERATIONS The 8XC196NP and 80C196NU have several basic requirements for operation within a system This chapter describes options for providing the basic requirements and discusses other hardware considerations 11 1 MINIMUM CONNECTIONS Table 11 1 lists the signals that are required for the device to function and Figure 11 1 shows the connections for a minimum configuration Table 11 1 Minimum Required Signals Si
340. he higher the probability that external noise will affect the clock generator circuitry and cause unreliable operation See the datasheet for required XTALI voltage drive levels and actual specifications External Clock Input XTAL1 Clock Driver 8XC196 Device No Connection XTAL2 t Required if TTL driver is used Not needed if CMOS driver is used A0274 02 Figure 11 5 External Clock Connections Txuxc 0 7 Voc 0 5 V 0 7 Voc 0 5 V L x XTAL1 0 3 0 5 V 0 3 Vc 0 5 V 4 gt XLXL A2119 02 Figure 11 6 External Clock Drive Waveforms At power on the interaction between the internal amplifier and its feedback capacitance i e the Miller effect may cause a load of up to 100 pF at the pin if the signal at XTAL1 is weak such as might be the case during start up of the external oscillator This situation will go away when the XTAL input signal meets the V and V specifications listed in the datasheet If these specifications are met the pin capacitance will not exceed 20 pF 8XC196NP 80C196NU USER S MANUAL intel 11 6 RESETTING THE DEVICE Reset forces the device into a known state As soon as RESET is asserted the I O pins the con trol pins and the registers are driven to their reset states Table B 5 on page B 13 lists the reset states of the pins See Table C 2 on page C 2 for the reset
341. he register file and windowing 2 3 8XC196NP 80C196NU USER S MANUAL intel 2 3 8 Register Arithmetic logic Unit RALU The RALU contains the microcode engine the 16 bit arithmetic logic unit ALU the master pro gram counter PC the processor status word PSW and several registers The registers in the RALU are the instruction register a constants register a bit select register a loop counter and three temporary registers the upper word lower word and second operand registers The 24 bit master program counter PC provides a linear nonsegmented 16 Mbyte memory space Only 20 of the address lines are implemented with external pins so you can physically ad dress only 1 Mbyte For compatibility with earlier devices the PC can be configured as 16 bits wide The master PC contains the address of the next instruction and has a built in incrementer that automatically loads the next sequential address However if a jump interrupt call or return changes the address sequence the ALU loads the appropriate address into the master PC The PSW contains one bit PSW 1 that globally enables or disables servicing of all maskable in terrupts one bit PSW 2 that enables or disables the peripheral transaction server PTS and six Boolean flags that reflect the state of your program Appendix A Instruction Set Reference provides a detailed description of the PSW registers except the 3 bit bit select register and the 6 bit
342. he standard interrupt vector locations are as follows Bit Mnemonic EXTINT3 EXTINT2 OVR2 3t OVRO 1 2 1 EPAO RI TI EXTINT1 EXTINTO OVRTM2 OVRTM1 Interrupt Pin EXTINT2 Pin EPA Capture Channel 2 or 3 Overrun EPA Capture Channel 0 or 1 Overrun EPA Capture Compare Channel 3 EPA Capture Compare Channel 2 EPA Capture Compare Channel 1 EPA Capture Compare Channel 0 SIO Receive SIO Transmit EXTINTO pin Timer 2 Overflow Underflow Timer 1 Overflow Underflow PTS service is not recommended for multiplexed interrupts This bit is cleared when both corresponding interrupt pending bits are cleared in EPA PEND 15 S EXTINT3 EXTINT2 OVR2_3 OVRO 1 EPAS3 EPA2 EPA1 7 0 EPAO RI TI EXTINT1 EXTINTO OVRTM1 OVRTM2 MULA Function 15 2 Reserved These bits are undefined 14 3 A bit is set by hardware to request an end of PTS interrupt for the corresponding interrupt 1 0 through its standard interrupt vector Standard Vector FF203CH FF203AH FF2038H FF2036H FF2034H FF2032H FF2030H FF200EH FF200CH FF200AH FF2008H FF2006H FF2002H FF2000H C 37 8XC196NP 80C196NU USER S MANUAL intel PWMx CONTROL PWMx CONTROL Address Table C 15 x 0 2 Reset State The PWM control PWMx_CONTROL register determines the duty cycle of the PWM xchannel A zero loaded into this register causes the PWM to output a low continuously 0 duty cycle An
343. heral transaction server PTS The programmable interrupt con troller has a hardware priority scheme that can be modified by your software Interrupts that go through the interrupt controller are serviced by interrupt service routines that you provide The peripheral transaction server PTS a microcoded hardware interrupt processor provides high speed low overhead interrupt handling You can configure most interrupts except NMI trap and unimplemented opcode to be serviced by the PTS instead of the interrupt controller PTS can transfer bytes or words either individually or in blocks between any memory loca tions and can generate pulse width modulated PWM signals PTS interrupts have a higher pri ority than standard interrupts and may temporarily suspend interrupt service routines See Chapter 6 Standard and PTS Interrupts for more information 2 6 intel ARCHITECTURAL OVERVIEW 2 4 INTERNAL TIMING The clock circuitry of the 8XC196NP Figure 2 3 is identical to that of earlier MCS 96 micro controllers It receives an input clock signal on XTAL provided by an external crystal or clock and divides the frequency by two The clock generators accept the divided input frequency from the divide by two circuit and produce two nonoverlapping internal timing signals PH1 and PH2 These signals are active when high Disable Clock Input Powerdown FxraLi XTAL1 J Divide by two Circuit Disable Clocks
344. hese bits specify the PTS mode M2 1 0 0 1 0 PWM TMOD Remap Mode Select 0 PWM remap mode TBIT Toggle Bit Initial Value Defines the initial value of TBIT 1 selects initial value as one 0 selects initial value as zero NOTE PWM remap mode the TBIT value is not used PTSCONST I is always added to the PTSPTR1 value However the unused TBIT still toggles at the end of each PWM remap cycle Reading this bit returns the current value of TBIT Figure 6 17 PTS Control Block PWM Remap Mode Continued Figure 6 18 shows the EPA and PTS operations for this example The first timer match occurs at time 0 for EPAO which asserts the output and generates an interrupt PWM Remap Cycle 1 The PTS adds 2 to EPAO TIME and toggles TBIT The output remains asserted until the second timer match occurs at for EPA1 which deasserts the output and generates an interrupt PWM Remap Cycle 2 The PTS adds T2 to 1 TIME and toggles the TBIT Alternating EPAO and interrupts continue with EPAO asserting the output and deas serting it 6 35 8XC196NP 80C196NU USER S MANUAL intel Start If EPAO set the output If EPA1 clear the output PTS Cycle If EPAO EPAO TIME EPAO TIME T2 If EPA1 EPA1 TIME EPA1 TIME T2 Toggle TBIT TBIT is not used A2553 01 Figure 6 18 EPA and PTS Operations for the PWM Remap Mode Examp
345. hrough 4 294 967 295 register file that is evenly divisible by four Note 2 LONG INTEGER 32 Yes 231 through 231 1 An address in the lower Note 1 2 147 483 648 through register file that is evenly 2 147 483 647 divisible by four Note 2 QUAD WORD 64 No 0 through 264 1 An address in the lower Note 3 register file that is evenly divisible by eight NOTES 1 The 32 bit variables are supported only as the operand in shift operations as the dividend in 32 by 16 divide operations and as the product of 16 by 16 multiply operations 2 For consistency with third party software you should adopt the C programming conventions for addressing 32 bit operands For more information refer to page 4 11 3 QUAD WORD variables are supported only as the operand for the EBMOVI instruction 8XC196NP 80C196NU USER S MANUAL intel Table 4 2 lists the equivalent operand type names for both C programming and assembly lan guage Table 4 2 Equivalent Operand Types for Assembly and C Programming Languages Operand Types Assembly Language Equivalent C Programming Language Equivalent BYTE BYTE unsigned char SHORT INTEGER BYTE char WORD WORD unsigned int INTEGER WORD int DOUBLE WORD LONG unsigned long LONG INTEGER LONG long QUAD WORD 4 1 1 BIT Operands A BIT is a single bit variable that can have the Boolean values true and false The architec ture requires that BITs be addre
346. ile below any window selected by the WSR 7 0 80C196NU W6 W5 WA W3 W2 W1 WO Bit Bit Function Number Mnemonic Reserved always write as zero 6 0 W6 0 Window Selection These bits specify the window size and window number See Table 5 8 on page 5 15 or Table 5 9 on page 5 15 Table C 19 WSR1 Settings and Direct Addresses for Windowable SFRs 32 byte Windows 64 byte Windows Register Memory 0060 007FH 0040 007FH Mnemonic Location 5 WSR agaress WSR1 address ADDRCOMO 1F40H 7AH 0060H 3DH 0040H ADDRCOM1 1F48H 7AH 0068H 3DH 0048H ADDRCOM2 1F50H 7AH 0070H 3DH 0050H ADDRCOM3 1F58H 7AH 0078H 3DH 0058H ADDRCOM4 1F60H 7BH 0060H 3DH 0060H ADDRCOM5 1F68H 7BH 0068H 3DH 0068H ADDRMSKO 1F42H 7AH 0062H 3DH 0042H ADDRMSK1 1F4AH 7AH 006 3DH 004AH ADDRMSK2 1F52H 7AH 0072H 3DH 0052H ADDRMSK3 1F5AH 7AH 007AH 3DH 005AH ADDRMSK4 1F62H 7BH 0062H 3DH 0062H ADDRMSK5 1F6AH 7BH 006AH 3DH 006 BUSCONO 1F44H 7AH 0064H 3DH 0044H BUSCON1 1F4CH 7AH 006CH 3DH 004CH BUSCON2 1F54H 7AH 0074H 3DH 0054H BUSCONS 1F5CH 7AH 007CH 3DH 005CH BUSCON4 1F64H 7BH 0064H 3DH 0064H Must be addressed as a word C 52 intel REGISTERS WSR1 Table C 19 WSR1 Settings and Direct Addresses for Windowable SFRs Continued
347. im er counter based high speed input output unit It describes the timer counters and explains how to program the EPA and how to use the EPA to produce pulse width modulated PWM outputs Chapter 11 Minimum Hardware Considerations describes options for providing the ba sic requirements for device operation within a system discusses other hardware considerations and describes device reset options Chapter 12 Special Operating Modes provides an overview of the idle powerdown standby and on circuit emulation ONCE modes and describes how to enter and exit each mode Chapter 13 Interfacing with External Memory lists the external memory signals and de scribes the registers that control the external memory interface It discusses the chip selects mul tiplexed and demultiplexed bus modes bus width and memory configurations the bus hold protocol write control modes and internal wait states and ready control Finally it provides tim ing information for the system bus Appendix Instruction Set Reference provides reference information for the instruction set It describes each instruction defines the processor status word PSW flags shows the rela tionships between instructions and PSW flags and lists hexadecimal opcodes instruction lengths and execution times For additional information about the instruction set see Chapter 4 Programming Considerations Appendix B Signal Descriptions
348. in the register file causes the memory controller to fetch the instruction from external memory 5 10 l ntel MEMORY PARTITIONS Table 5 6 Register File Memory Addresses Address M 2 Range Description Addressing Modes O3FFH 0100 General purpose register RAM upper register file Indirect indexed windowed direct OOFFH z m 001 General purpose register RAM lower register file Direct indirect indexed 0019H Stack poi SP fil Di indi 0018H tack pointer SP lower register file irect indirect indexe 0017H mot 0000H CPU special function registers SFRs lower register file Direct indirect indexed 5 2 4 1 General purpose Register RAM The lower register file contains general purpose register RAM The stack pointer locations can also be used as general purpose register RAM when stack operations are not being performed The RALU can access this memory directly using direct addressing The upper register file also contains general purpose register RAM The RALU normally uses indirect or indexed addressing to access the RAM in the upper register file Windowing enables the RALU to use direct addressing to access this memory See Chapter 4 Programming Con siderations for a discussion of addressing modes Windowing provides fast context switching of interrupt tasks and faster program execution See Windowing on page 5 13
349. includes the following tables Table 1 on page 2 is a map of the opcodes Table 2 on page 4 defines the processor status word PSW flags Table A 3 on page A 5 shows the effect of the PSW flags or a specified register bit on conditional jump instructions Table 4 on page 5 defines the symbols used in Table A 6 Table A 5 on page A 6 defines the variables used in Table A 6 to represent instruction operands Table A 6 beginning on page A 7 lists the instructions alphabetically describes each of them and shows the effect of each instruction on the PSW flags Table 7 beginning on page 47 lists the instruction opcodes in hexadecimal order along with the corresponding instruction mnemonics Table A 8 on page A 53 lists instruction lengths and opcodes for each applicable addressing mode Table 9 on page A 60 lists instruction execution times expressed in state times NOTE The symbol prefixes an immediate value in immediate addressing mode Chapter 4 Programming Considerations describes the operand types and addressing modes A 1 8XC196NP 80C196NU USER S MANUAL intel Table A 1 Opcode Map Left Half Opcode 0 1 2 x3 x4 x5 x6 x7 ox SKIP CLR NOT NEG XCH DEC EXT INC di Ay CLRB NOTB NEGB XCHB DECB EXTB INCB di SJMP ay JBC bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 AND ADD
350. instruction length and L is the long indexed instruction length 3 Forthe SCALL and SJMP instructions the three least significant bits of the opcode are concatenated with the eight bits to form an 11 bit 2 s complement offset A 53 8 196 80C196NU USER S MANUAL intel Table A 8 Instruction Lengths and Hexadecimal Opcodes Continued Arithmetic Group II Direct Immediate Note 1 eee Mnemonic Length Opcode Length Opcode Length Opcode p dd Opcode DIV 4 FE 8C 5 FE8D 4 FE 8E 5 6 FE 8F DIVB 4 FE 9C 4 FE 9D 4 FE 9E 5 6 FE 9F DIVU 3 8C 4 8D 3 8E 4 5 8F DIVUB 3 9C 3 9D 3 9E 4 5 9F MUL 2 ops 4 FE eC 5 FE 6D 4 FE 6E 5 6 FE 6 MUL 3 ops 5 FE 4C 6 FE4D 5 FE 4E 6 7 FE 4F MULB 2 ops 4 FE 7C 4 FE 7D 4 FE 7E 5 6 FE 7F MULB 3 ops 5 FE 5C 5 FE5D 5 FE 5E 6 7 FE 5F MULU 2 ops 3 6 4 6D 3 6E 4 5 6F MULU 3 ops 4 4C 5 4D 4 4E 5 6 4F MULUB 2 ops 3 7C 3 7D 3 7E 4 5 MULUB 3 ops 4 5C 4 5D 4 5E 5 6 5F Logical Direct Immediate Note f NO A Mnemonic Length Opcode Length Opcode Length Opcode zr ah Opcode AND 2 ops 3 60 4 61 3 62 4 5 63 AND 3 ops 4 40 5 41 4 42 5 6 43 ANDB 2 ops 3 70 3 71 3 72 4 5 73 ANDB 3 ops 4 50 4 51 4 52 5 6 53 NEG 2 03 NEGB 2 13 NOT 2 02 NOTB 2 12 OR 3 80 4 81 3 82 4 5 83 ORB 3 90 3 91 3 92 4 5
351. ir I O function during those modes See Figure 11 7 on page 11 8 and Table B 5 on page B 13 for additional information 7 3 3 2 REG Settings for Pins Configured as Extended address Signals Nonextended data accesses go to the address contained in EP REG Therefore if you configure EP REG to point to the desired address you can use nonextended addressing modes to access the extended address space However we recommend that you clear the REG bits for any EPORT pins configured as extended address signals in order to maintain compatibility with soft ware development tools NOTE If any pins are configured as extended address signals and their corresponding REG bits are set nonextended operations will still access the register file and standard SFRs However all other nonextended accesses including those to internal RAM and internal nonvolatile memory will be directed off chip to the page address in EP REG The 8XC196NP allows you to change the value of EP REG to control which memory page a nonextended instruction accesses However software tools require that EP REG be equal to 00H The 80C196NU forces all nonextended data accesses to page 00H You cannot use EP REG to change pages 7 3 3 3 EPORT Status During Instruction Execution When using the EPORT to address memory outside page 00H keep these points in mind 1 During extended accesses the upper four bits of the address lower four bits of the EPC are sent
352. ir reset values Executing this instruction causes the RESET pin to be pulled low for 16 state times SFR lt Reset Status Pin Reset Status PSW lt 0 EPC PC FF2080H PSW Flag Settings V 5 0 0 0 0 0 0 RST 11111111 SCALL SHORT CALL Pushes the contents of the program counter the return address onto the stack then adds to the program counter the offset between the end of this instruction and the target label effecting the call The offset must be in the range of 1024 to 1023 64 Kbyte mode SP lt SP 2 SP lt PC PC lt PCG 11 bit disp 1 Mbyte mode SP lt SP 4 SP lt PC PC PC 11 bit disp PSW Flag Settings Z N C V VT ST SCALL cadd 00101 disp low NOTE The displacement disp is sign extended to 16 bits in the 64 Kbyte addressing mode and to 24 bits in the 1 Mbyte addressing mode This displacement may cause the program counter to cross a page boundary in 1 Mbyte mode SETC SET CARRY FLAG Sets the carry flag lt 1 PSW Flag Settings Z N C V VT ST 1 SETC 11111001 A 36 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format SHL SHIFT WORD LEFT Shifts the destination word operand to the left as many times a
353. is a capture event In the output mode the EPA monitors a timer until its value matches that of a stored time value When a match occurs the EPA triggers an output event which can set clear or toggle an output pin This is a compare event Both capture and compare events can initiate interrupts which can be serviced by either the interrupt controller or the PTS 2 11 8XC196NP 80C196NU USER S MANUAL intel Timer 1 and timer 2 are both 16 bit up down timer counters that can be clocked internally or ex ternally Each timer counter is called a timer if it is clocked internally and a counter if itis clocked externally See Chapter 10 Event Processor Array EPA for additional information on the EPA and timer counters 2 5 4 Pulse width Modulator PWM The output waveform from each PWM channel is a variable duty cycle pulse with a programma ble frequency that occurs every 256 or 512 state times for the 8XC196NP or every 256 512 or 1024 state times for the 80C196NU as programmed Several types of motors require a PWM waveform for most efficient operation When filtered the PWM waveform produces a DC level that can change in 256 steps by varying the duty cycle See Chapter 9 Pulse width Modulator for more information 2 6 SPECIAL OPERATING MODES In addition to the normal execution mode the device operates in several special purpose modes Idle and powerdown modes conserve power when the device is inactive An additional
354. is chapter describes what you ll find in this manual lists other documents that may be useful and explains how to access the support services we provide to help you complete your design 1 4 MANUAL CONTENTS This manual contains several chapters and appendixes a glossary and an index This chapter Chapter 1 provides an overview of the manual This section summarizes the contents of the re maining chapters and appendixes The remainder of this chapter describes notational conventions and terminology used throughout the manual provides references to related documentation de scribes customer support services and explains how to access information and assistance Chapter 2 Architectural Overview provides an overview of the device hardware It de scribes the core internal timing internal peripherals and special operating modes Chapter 3 Advanced Math Features describes the advanced mathematical features of the 80C196NU The 80C196NU is the first member of the MCS 96 microcontroller family to in corporate enhanced 16 bit multiplication instructions for performing multiply accumulate oper ations and a dedicated 32 bit accumulator register for storing the results of these operations The accumulator and the enhanced instructions combine to decrease the amount of time required to perform multiply accumulate operations The instructions and accumulator support signed and unsigned integers as well as signed fractional data
355. is vector contains the start ing base address of the corresponding PTS control block PTSCB or interrupt service routine PTSCBs must be located on a quad word boundary in the internal register file Interrupt service routines must begin execution in page FFH but can jump anywhere after the initial vector is tak en 6 3 1 Special Interrupts This microcontroller has three special interrupt sources that are always enabled unimplemented opcode software trap and NMI These interrupts are not affected by the EI enable interrupts and DI disable interrupts instructions and they cannot be masked of these interrupts are serviced by the interrupt controller they cannot be assigned to the PTS Of these three only NMI goes through the transition detector and priority encoder The other two special interrupts go di rectly to the interrupt controller for servicing Be aware that these interrupts are often assigned to special functions in development tools intel STANDARD AND PTS INTERRUPTS Table 6 3 Interrupt Sources Vectors and Priorities Interr ntroller 19 PTS Service Interrupt Source Mnemonic o 5 gt o 5 gt 3 5 E E 5 2 gt 2 gt Nonmaskable Interrupt NMI INT15 FF203EH 30 Pin EXTINT3 INT14 FF203CH 14 PTS14 FF205CH 29 EXTINT2 Pin EXTINT2 INT13 FF203AH 13 PTS13 FF205AH 28 ES det 229 2 OVR2 3
356. ister PWMx CONTROL x 0 1 or 2 controls the duty cycle the pulsewidth stated as a percentage of the period of the corresponding PWM output Each control register con tains an 8 bit value that is loaded into a buffer when the 8 bit counter rolls over from FFH to 00H The comparators compare the contents of the buffers to the counter value Since the value written to the control register is buffered you can write a new 8 bit value to PVMx CONTROL at any time However the comparators do not recognize the new value until the counter has expired the remainder of the current 8 bit count The new value is used during the next PWM output period The counter continually increments until it rolls over to 00H at which time the PWM output is driven high and the contents of the control registers are loaded into the buffers The PWM output remains high until the counter value matches the value in the buffer at which time the output is pulled low When the counter resets again i e when an overflow occurs the output is switched high Loading PVMx CONTROL with forces the output to remain low Figure 9 3 shows typical PWM output waveforms PWM can generate a duty cycle ranging in length from 0 to 99 6 of the pulse To deter mine the desired duty cycle measurement you must apply a multiplier 2 4 or 8 to the PWMx CONTROL value to compensate for the divided input frequency from the divide by two circuitry See Chapter 2 Architectur
357. istics of the three chip select outputs and the corresponding contents of BUSCONx 13 12 intel INTERFACING WITH EXTERNAL MEMORY Flash 256Kx16 50 52 22 D15 0 D7 0 0 WS 0 WS 80000 FFFFFH 7 000 7 82510 2 0 UART 8XC196 A19 0 A17 0 A12 0 AD15 0 D7 0 3 WS CE 01 00 01 A2433 03 Figure 13 5 Example System for Setting Up Chip select Outputs Table 13 8 BUSCONx Registers for the Example System Chip Contents of select Multiplexing Bus Width Wait States BUSCONx Output 0 Demultiplexed 16 bits 0 COH 1 Demultiplexed 8 bits 3 83H 2 Demultiplexed 8 bits 0 80H The location and size of an address range are specified by the ADDRCOMx register and the ADDRMS Kx register see Figure 13 2 and Figure 13 3 The 8 Kbyte SRAM is assigned to ad dress range 7E000 7FFFFH and uses chip select output 2 The 12 most significant bits of the base address 7E000H are written to the BASE1 9 8 bits in the ADDRCOM2 register which then contains 07 The address range for 52 is 8 Kbytes 213 bytes n 13 The number of bits to be set in MASK19 8 of ADDRMSK2 is 20 n 7 After the 7 most significant bits of MASK 19 8 are set ADDRMSKQ 2 contains OFEOH Results for CSO and 1 are found similarly see Table 13 9 13 13 8 196 80C196NU USER S MANUAL Table 13 9 Results for the Chip select Example intel
358. it WORDS must be aligned at even byte boundaries in the address space The least significant byte of the WORD is in the even byte address and the most significant byte is in the next higher odd address The address of a WORD is that of its least significant byte the even byte address WORD operations to odd addresses are not guaranteed to operate in a consistent manner 4 1 5 INTEGER Operands An INTEGER is a 16 bit signed variable that can take on values from 32 768 215 through 32 767 4255 1 Arithmetic operations that generate results outside the range of an INTEGER set the overflow flags in the processor status word PSW The numeric result is the same as the result of the equivalent operation on WORD variables INTEGERs must be aligned at even byte boundaries in the address space The least significant byte of the INTEGER is in the even byte address and the most significant byte is in the next high er odd address The address of an INTEGER is that of its least significant byte the even byte address INTEGER operations to odd addresses are not guaranteed to operate in a consistent manner 4 1 66 DOUBLE WORD Operands A DOUBLE WORD is an unsigned 32 bit variable that can take on values from 0 through 4 294 967 295 232 1 The architecture directly supports DOUBLE WORD operands only as the operand in shift operations as the dividend in 32 by 16 divide operations and as the product of 16 by 16 multiply operations For th
359. l 2 EPA2 Interrupt m 0 gt g Capture Compare Channel 3 Interrupt 2352 02 Figure 10 1 EPA Block Diagram 10 2 EPA AND TIMER COUNTER SIGNALS AND REGISTERS Table 10 1 describes the EPA and timer counter input and output signals Each signal is multi plexed with a port pin as shown in the first column Table 10 2 briefly describes the registers for the EPA capture compare channels and timer counters Table 10 1 EPA and Timer Counter Signals PortPin EPA Signal s TRE Description P1 3 0 0 VO High speed input output for capture compare channels 0 3 P1 4 T1CLK External clock source for timer 1 P1 5 T1DIR External direction control for timer 1 P1 6 T2CLK External clock source for timer 2 P1 7 T2DIR External direction control for timer 2 10 2 intel EVENT PROCESSOR ARRAY EPA Table 10 2 EPA Control and Status Registers Mnemonic Address Description EPA MASK 1F9CH EPA Mask Four bits OVRO OVR1 OVR2 and OVR3 in this 8 bit register enable and disable mask the individual capture overrun interrupt Sources associated with capture compare channels EPA3 0 EPA PEND 1F9EH EPA Pending Four bits OVRO OVR1 OVR2 and OVR3 in this 8 bit register indicate an overrun status for the associated capture compare channels 0 OVRO and OVR1 are multiplexed to share one interrupt pending bit O
360. l clock generator Because the device can operate at many frequencies this manual defines time requirements in terms of state times rather than in specific units of time Lowercase t represents the period of the internal clock For the NP t is the reciprocal of Where Fy44 1 is the input frequency on XTAL 1 For the 80C196NU which employs a phased lock loop with clock multiplier circuitry t is the reciprocal of either 2E 44 4 OF 4F xray The multiplier depends on the clock mode which is controlled by the PLLEN1 and PLLEN2 input pins Figure 2 4 on page 2 8 illustrates the clock circuitry of the 80C196NU Universal asynchronous receiver and transmitter A part of the serial I O port See watchdog timer Any 16 bit unit of data An unsigned 16 bit variable with values from 0 through 21821 A method for converting data a larger format by filling the upper bit positions with zeros intel Index intel defined 1 3 1 1 Mbyte mode 5 1 fetching code 5 23 5 25 fetching data 5 26 incrementing SP 5 11 memory configuration example 5 31 64 Kbyte mode 5 1 5 5 fetching code 5 23 5 25 fetching data 5 26 incrementing SP 5 11 memory configuration example 5 27 5 29 A A15 0 B 6 19 0 5 1 13 2 13 20 for CCBO fetch 13 17 19 16 7 11 B 6 See also EPORT Accumulator ACC Ox register 3 4 STAT register 3 5 operating modes fractional mode 3
361. ld feature and ignores any new requests until the bit is set again Sometimes it is important to prevent another device from taking control of the bus while a block of code is executing One way to protect a code segment is to clear WSR 7 and then execute a JBC instruction to check the status of the HLDA signal The JBC instruction prevents the RALU from executing the protected block until current hold requests are serviced and the hold feature is disabled This is illustrated in the following code DI Disable interrupts to prevent code interruption PUSH WSR Disable hold requests and LDB WSR 1FH window Port 2 WAIT JBC P2 PIN 6 WAIT Check the HLDA signal If set add protected instruction here POP WSR Enable hold requests EI Enable interrupts 13 7 3 Hold Latency When an external device asserts HOLD the 8XC196Nx finishes the current bus cycle and then asserts HLDA The time it takes the device to assert HLDA after the external device asserts HOLD is called hold latency see Figure 13 16 on page 13 31 Table 13 13 lists the maximum hold latency for each type of bus cycle 13 32 intel INTERFACING WITH EXTERNAL MEMORY Table 13 13 Maximum Hold Latency Maximum Hold Latency Bus Cycle Type state times Internal execution or idle mode 1 5 16 bit external execution 2 5 1 per wait state 8 bit external execution 2 5 4 2 per wait state 13 7 4 Regaining Bus Control While HOLD i
362. le You can change the duty cycle by changing the time that the output is high and keeping the period constant After a timer match occurs for EPA1 when the output falls schedule the next EPA1 match for T2 DT where DT is the time to be added to the on time Thereafter schedule the next match for T2 You can do this by replacing one EPA 1 PTS interrupt with a normal interrupt clear PTSSEL 8 Have the interrupt service routine add T2 DT to TIME and set PTSSEL 8 to re enable PTS service for EPA1 This adjustment changes the duty cycle without affecting the period By using two EPA channels in the PWM remap mode you can generate duty cycles closer to 096 and 10096 than is possible with PWM toggle mode For further information about generating PWM waveforms with the EPA see Operating in Compare Mode on page 10 12 6 36 intel I O Ports intel CHAPTER 7 PORTS I O ports provide a mechanism to transfer information between the device and the surrounding system circuitry They can read system status monitor system operation output device status configure system options generate control signals provide serial communication and so on Their usefulness in an application is limited only by the number of I O pins available and the imagination of the engineer 7 1 1 0 PORTS OVERVIEW Standard I O port registers are located in the SFR address space and they can be windowed Mem ory mapped I O port regist
363. les timer 1 enables timer 6 UD Up Down This bit determines the timer counting direction in selected modes see mode bits M2 0 0 count down 1 count up 5 8 M2 0 EPA Clock Direction Mode Bits These bits determine the timer clocking source and direction control source M2 1 0 ClockSource Direction Source 0 0 0 f 4 UD bit TT CONTROL 6 X 0 1 T1CLK UD bit T1CONTROL 6 0 1 0 f 4 T1DIR pin 0 1 1 T1CLK pint T1DIR pin 1 1 1 quadrature clocking using T1CLK and T1DIR If an external clock is selected the timer counts on both the rising and falling edges of the clock 2 0 P2 0 EPA Clock Prescaler Bits These bits determine the clock prescaler value P2 P1 Prescaler Divisor Resolution 0 0 0 divide by 1 disabled 160 ns 0 0 1 divide by 2 320 ns 0 1 0 divide by 4 640 ns 0 1l 1 divide by 8 1 28 us 1 0 0 divide by 16 2 56 us 1 0 1 divide by 32 5 12 us 1 1 0 divide by 64 10 24 us 1 1 1 divide by 128 NU only 20 48 us Atf 25 MHz Use the formula on page 10 6 to calculate the resolution at other frequencies Figure 10 8 Timer 1 Control TI CONTROL Register 10 16 intel EVENT PROCESSOR ARRAY EPA T2CONTROL Address 1F94H Reset State 00H The timer 2 control T2CONTROL register determines the clock source counting direction and count rate for timer 2 7 0 CE UD M2 M1 MO P2 P1 PO Bit Bit Function Number Mnemonic
364. ls the function of its assigned capture compare channel The reg isters for EPAO and EPA2 are identical The registers for and have an additional bit the remap bit RM which is used to enable and disable remapping for high speed PWM gener ation see Generating a High speed PWM Output on page 10 14 This added bit bit 8 re quires an additional byte so EPA1_CON CON must be addressed as words while the others can be addressed as bytes To program a compare event write to EPAx CON Figure 10 10 to configure the EPA cap ture compare channel and then load the event time into EPAx TIME To program a capture event you need only write to EPAx CON Table 10 5 shows the effects of various combinations of EPAx CON bit settings Table 10 5 Example Control Register Settings and EPA Operations Capture Mode MODE ROT ON RT 3 7 6 5 3 2 1 0 Operation X 0 0 0 0 0 None X 0 0 1 0 X X Capture on falling edges X 0 1 0 0 X X Capture on rising edges X 0 1 1 0 X X Capture on both edges X 0 X 1 0 1 X Reset opposite timer X 0 1 X 0 1 X Reset opposite timer Compare Mode MODE RE ROT ON RT 7 6 5 4 3 2 1 0 Operation X 1 010 X 0 0 None X 1 0 1 X 0 X X Clear output pin X 1 1 0 X 0 X X Set output pin X 1 1 1 X 0 X X Toggle output pin X 1 X X X 0 0 1 R
365. lso contains the bus control parameters for fetching chip configuration byte 1 7 0 1 1 WS1 WSO DEMUX BHE BW16 PD Bit Bit Number Mnemonic Function 7 6 1 To guarantee device operation write ones to these bits 5 4 WS1 0 Wait States These two bits control the number of wait states that are used for an external fetch of CCB1 wso WS1 0 0 zero wait states 0 1 one wait state 1 0 two wait states 1 1 three wait states 3 DEMUX Select Demultiplexed Bus Selects the demultiplexed bus mode for an external fetch of CCB1 0 2 multiplexed address and data are multiplexed on AD15 0 1 demultiplexed data only on AD15 0 2 Write control Mode Selects the write control mode which determines the functions of the BHE WRH and WR WRL pins for external bus cycles 0 write strobe mode the BHE WRH pin operates as WRH and the WR WRL pin operates as WRL 1 standard write control mode the BHE WRH pin operates as BHE and the WR WRL pin operates as WR 1 BW16 Buswidth Control Selects the bus width for an external fetch of CCB1 0 8 bit bus 1 16 bit bus 0 PD Powerdown Enable Enables or disables the IDLPD 2 and IDLPD 8 instructions When enabled the IDLPD 2 instruction causes the microcontroller to enter powerdown mode and for the 80C196NU only the IDLPD 3 instruction causes the microcontroller to enter standby mode 0 disable powerdown and
366. m for Setting Up Chip select oe iue AG en eee 13 13 Chip Configuration 0 CCRO Register ripe ene ae ee el intel Figure 13 7 13 8 13 9 13 10 13 11 13 12 13 13 13 14 13 15 13 16 13 17 13 18 13 19 13 20 13 21 13 22 13 23 13 24 B 1 B 2 B 3 B 4 CONTENTS FIGURES Page Chip Configuration 1 CCR1 19 16 Multiplexing and Bus Width Options sem 13 19 Bus Activity for Four Types of Buses 13 20 16 bit External Devices in Demultiplexed Mode 13 22 Timings for Multiplexed and Demultiplexed 16 bit Buses 8XC196NP 13 23 Timings for Multiplexed and Demultiplexed 8 bit Buses 8XC196NP 13 25 READY Timing Diagram Multiplexed Mode see 13 28 READY Timing Diagram Demultiplexed Mode 8XC196NP 13 29 READY Timing Diagram Demultiplexed Mode 80C196NU 13 30 TIMING siete ttn oreet nre egre e PLE 13 81 Write control Signal eene eene 13 34 Decoding WRL and WRERBR nece tree pee rtr ete eene cp ad pcs 13 35 A System with 8 bit and 16 bit 8 1 13 36 Multiplexed System Bus Timing 8 196 13 37 Multiplexed System Bus Timing 80C196NU
367. mit FF200AH EXTINT1 pin FF2008H EXTINTO EXTINTO pin FF2006H OVRTM2 Timer 2 Overflow Underflow FF2002H OVRTM1 Timer 1 Overflow Underflow FF2000H 2 Reserved This bit is undefined Figure 6 7 Interrupt Pending INT_PEND Register intel STANDARD AND PTS INTERRUPTS INT PEND1 Address 0012H Reset State 00H When hardware detects a pending interrupt it sets the corresponding bit in the interrupt pending INT PEND or INT PEND1 registers When the vector is taken the hardware clears the pending bit Software can generate an interrupt by setting the corresponding interrupt pending bit 7 0 NMI EXTINT3 EXTINT2 OVR2 3 OVRO 1 EPA3 EPA2 EPA1 Bit Number Function 7 0 Any set bit indicates that the corresponding interrupt is pending The interrupt bit is cleared when processing transfers to the corresponding interrupt vector The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector NMI Nonmaskable Interrupt FF203EH pin FF203CH EXTINT2 EXTINT2 pin FF203AH OVR2_3 EPA Capture Channel 2 or 3 Overrun FF2038H OVRO 1 EPA Capture Channel 0 or 1 Overrun FF2036H EPAS3 EPA Capture Compare Channel 3 FF2034H EPA2 EPA Capture Compare Channel 2 FF2032H EPA1 EPA Capture Compare Channel 1 FF2030H An overrun on the EPA capture compare channels can generate the multiplexed capture overrun interrupts The EPA MASK and EP
368. mplemented opcode interrupt prevents other interrupt requests from being acknowledged until after the next instruction is executed 6 3 1 2 Software Trap The TRAP instruction opcode F7H causes an interrupt call that is vectored through location FF2010H The TRAP instruction provides a single instruction interrupt that is useful when de bugging software or generating software interrupts The TRAP instruction prevents other inter rupt requests from being acknowledged until after the next instruction is executed 8XC196NP 80C196NU USER S MANUAL intel 6 3 1 3 NMI The external NMI pin generates a nonmaskable interrupt for implementation of critical interrupt routines NMI has the highest priority of all the prioritized interrupts It is passed directly from the transition detector to the priority encoder and it vectors indirectly through location FF203EH The NMI pin is sampled during phase 2 CLKOUT high and is latched internally Because inter rupts are edge triggered only one interrupt is generated even if the pin is held high If your sys tem does not use the NMI interrupt connect the NMI pin to Vg to prevent spurious interrupts 6 3 2 External Interrupt Pins The external interrupt pins are multiplexed with port pins as follows EXTINTO P2 2 2 4 EXTINT2 P3 6 and EXTINT3 P3 7 Writing to a bit in the Px register also sets the corresponding external interrupt bit in the interrupt pending register To prev
369. munications mode and enables or disables the receiver parity checking and nine bit data transmission For the 80C196NU it also enables or disables the divide by two prescaler 7 0 8XC196NP PAR TB8 REN PEN M1 MO 7 0 80C196NU PRS PAR TB8 REN PEN M1 MO Tk e sende Funetion 7 Reserved for compatibility with future devices write zero to this bit 6t PRS Prescale This bit enables the divide by two prescaler 0 disable the prescaler 1 enable the prescaler 5 PAR Parity Selection Bit Selects even or odd parity 0 even parity 1 odd parity 4 TB8 Transmit Ninth Data Bit This is the ninth data bit that will be transmitted in mode 2 or 3 This bit is cleared after each transmission so it must be set before SBUF TX is written When CON is set this bit takes on the even parity value 3 REN Receive Enable Setting this bit enables the receiver function of the RXD pin When this bit is set a high to low transition on the pin starts a reception in mode 1 2 or 3 In mode 0 this bit must be clear for transmission to begin and must be set for reception to begin Clearing this bit stops a reception in progress and inhibits further receptions 2 PEN Parity Enable In modes 1 and 3 setting this bit enables the parity function This bit must be cleared if mode 2 is used When this bit is set TB8 takes the parity value on transmissions With parity enabled SP STATUS 7 bec
370. n EPAx TIME the current timer value is loaded into the buffer and held there After the CPU reads the EPAx TIME register the contents of the capture buffer are automatically transferred into EPAx TIME and the EPA interrupt pending bit is set 10 9 8XC196NP 80C196NU USER S MANUAL intel Event Occurs at EPA Pin Capture Buffer EPA Interrupt Pending Bit Set EPAx TIME Read out Time Value A2458 02 Figure 10 6 EPA Simplified Input capture Structure If a third event occurs before the CPU reads the event time register the overwrite bit EPAx 0 determines how the EPA will handle the event If the bit is clear the EPA ignores the third event If the bit is set the third event time overwrites the second event time in the capture buffer Both situations set the overrun interrupt pending bit and if the interrupt is enabled they generate an overrun interrupt Table 10 4 summarizes the possible actions when a valid event oc curs NOTE In order for an event to be captured the signal must be stable for at least two state times both before and after the transition occurs Figure 10 7 Event 1 Y 2 State 2 State Times Times Event 2 f 2 State 2 State Times Times A3130 01 Figure 10 7 Valid EPA Input Events 10 10 intel EVENT PROCESSOR ARRAY EPA Table 10 4 Action Taken when a Valid Edge Occurs Status of EPA CON
371. n drain output input output or bidirectional Open drain outputs require external pull ups P1_MODE 1FDOH Port x Mode P2 MODE 1FC9H Each bit of Px MODE controls whether the corresponding pin ES MOBE functions as Standard I O port pin or as a special function signal 0 standard port pin 1 special function signal P1 PIN 1FD6H Port x Input P2 PIN Each bit of PIN reflects the current state of the corresponding BEEN pin regardless of the pin configuration P1 REG 1FD4H Port x Data Output For an input set the corresponding Px REG bit P4 REG 1FDDH For an output write the data to be driven out by each pin to the A corresponding bit of Px REG When a pin is configured as standard Px MODE y 0 the result of a CPU write to REG is immediately visible on the pin When a pin is configured as a special function signal Px MODE y 1 the associated on chip peripheral or off chip component controls the pin The CPU can still write to Px REG but the pin is unaffected until it is switched back to its standard function This feature allows software to configure a pin as standard I O clear MODE initialize or overwrite the pin value then configure the as a special function signal set MODE y In this way initial ization fault recovery exception handling etc can be done without changing the operation of the associated peripheral
372. n internal reset system power up or SWI closing will generate the system reset signal RESET SW1 8XC196 Device System reset signal to external circuitry Notes 1 D1 provides a faster cycle time for repetitive power on resets 2 Optional pull up for faster recovery 0277 02 Figure 11 10 Example System Reset Circuit 11 10 intel MINIMUM HARDWARE CONSIDERATIONS 11 6 2 Issuing the Reset RST Instruction The RST instruction opcode FFH resets the device by pulling RESET low for 16 state times It also clears the processor status word PSW sets the extended and master program counters EPC PC to FF2080H and resets the special function registers SFRs See Table C 2 on page C 2 for the reset values of the SFRs 11 6 3 Issuing an Illegal IDLPD Key Operand The device resets itself if an illegal key operand is used with the idle powerdown IDLPD com mand The legal keys are 1 for idle mode 2 for powerdown mode and 3 for standby mode NU only If any other value is used the device executes a reset sequence See Appendix A for a description of the IDLPD command 11 11 intel 12 Special Operating Modes intel CHAPTER 12 SPECIAL OPERATING MODES The 8XC196NP and 80C196NU provide the following power saving modes idle standby 80C196NU only and powerdown They also provide an on circuit emulation ONCE mode that electrically isolates the device from the other sy
373. nals is a shaft angle decoder shown in Figure 10 3 Its output signals X and Y are input to TxCLK and TxDIR which in turn output signals X_internal and Y_internal These signals are used in Figure 10 4 and Table 10 3 to describe the direction of the shaft 10 6 intel EVENT PROCESSOR ARRAY EPA 8XC196 Device PH2 PH1 X internal Optical Reader Y internal A0268 02 Figure 10 3 Quadrature Mode Interface Table 10 3 Quadrature Mode Truth Table US DC T e State DIE Cu Count Direction T 0 Increment L 1 Increment 0 2 Increment 1 T Increment J 0 Decrement 1 Decrement 0 T Decrement 1 Decrement 10 7 8XC196NP 80C196NU USER S MANUAL intel CLKOUT TxDIR COUNT x A0269 02 Figure 10 4 Quadrature Mode Timing and Count 10 4 EPA CHANNEL FUNCTIONAL OVERVIEW The EPA has four programmable capture compare channels that can perform the following tasks capture the current timer value when a specified transition occurs on the EPA pin clear set or toggle the EPA pin when the timer value matches the programmed value in the event time register generate an interrupt when a capture or compare event occurs generate an interrupt when a capture overrun occurs reset its own base timer in compare mode reset the opposite timer in both compare and capture mode Each EPA channel ha
374. nction always enabled 2 Reserved always write as zero These bits apply to the EPA1 CON and EPA3 CON registers only C 21 8XC196NP 80C196NU USER S MANUAL intel EPAx CON EPAx CON Continued Address Table C 8 0 3 Reset State The EPA control EPAx CON registers control the functions of their assigned capture compare channels The registers for EPAO andEPA2 are identical The registers for EPA1 and have an additional bit the remap bit This added bit bit 8 requires an additional byte so EPA1 CON and must be addressed as words while the others can be addressed as bytes 15 8 x 1 3 RM 7 0 TB CE M1 MO RE ROT ON RT 7 0 0 2 M1 MO RE ROT ON RT Bit Bit Function Number Mnemonic 1 ROT Reset Opposite Timer Controls different functions for capture and compare modes In Capture Mode 0 causes no action 1 resets the opposite timer In Compare Mode Selects the timer that is to be reset if the RT bit is set 0 selects the reference timer for possible reset 1 selects the opposite timer for possible reset The TB bit bit 7 selects which is the reference timer and which is the opposite timer 0 ON RT Overwrite New Reset Timer The ON RT bit functions as overwrite new in capture mode and reset timer in compare mode In Capture Mode ON An overrun error is generated when an input cap
375. nd PH2 frequency 2 9 PWM duty cycle 6 26 PWM frequency 6 26 state time 2 9 FPAL 96 4 5 Frequency f 2 9 2 9 H Handbooks ordering 1 6 Hardware addressing modes 4 6 intel device considerations 11 1 11 11 device reset 11 8 11 9 11 10 11 11 interrupt processor 2 6 6 1 minimum configuration 11 1 NMI considerations 6 6 noise protection 11 4 reset instruction 4 14 SIO port considerations 8 6 HLDA 13 4 13 30 B 8 HLDEN bit 5 14 13 32 Hold latency See bus hold protocol HOLD 13 4 13 30 B 9 considerations 7 9 Hypertext manuals and datasheets downloading 1 10 I O ports after reset 13 18 Idle mode 2 12 12 5 12 6 12 7 entering 12 6 exiting 12 6 12 7 timeout control 10 6 IDLPD instruction A 2 A 20 A 52 A 59 A 67 IDLPD 1 12 6 IDLPD 2 12 8 IDLPD 3 12 6 illegal operand 11 9 11 11 Immediate addressing 4 7 INC instruction A 2 A 21 A 47 A 53 A 60 INCB instruction A 2 A 21 A 47 A 53 A 60 Indexed addressing 4 11 and register RAM 5 11 and windows 5 21 Indirect addressing 4 7 and register RAM 5 11 with autoincrement 4 8 Input pins level sensitive B 6 sampled B 6 INST 13 4 B 9 after reset 13 18 Instruction fetch reset location 5 2 See also 1 Mbyte mode 64 Kbyte mode Instruction set 4 1 additions 4 5 4 6 INDEX and PSW flags A 5 code execution 2 4 2 5 conventions 1 3 differences 4 5 execution times 60 61 lengths 53
376. nd disables standby and powerdown mode INT MASK 0008H Interrupt Mask Bits 3 and 4 of this register enable and disable mask the external interrupts EXTINTO and EXTINT1 12 2 intel SPECIAL OPERATING MODES Table 12 2 Operating Mode Control and Status Registers Continued Mnemonic Address Description INT MASK1 0013H Interrupt Mask 1 Bits 5 and 6 of this register enable and disable mask the external interrupts EXTINT2 and EXTINT3 INT PEND 0009H Interrupt Pending Bits 3 and 4 of this register are set to indicate a pending external interrupt EXTINTO and EXTINT1 INT PEND1 0012H Interrupt Pending 1 Bits 5 and 6 of this register are set to indicate a pending external interrupt EXTINT2 and P2 DIR 1FD3H Port x Direction P3_DIR 1FDAH Each bit of Px DIR controls the direction of the corresponding pin Clearing a bit configures a pin as a complementary output setting a bit configures a pin as an input or open drain output Open drain outputs require external pull ups P2 MODE 1FD1H Port x Mode P3 MODE 1FD8H Each bit of Px_MODE controls whether the corresponding pin functions as a standard I O port pin or as a special function signal Setting a bit configures a pin as a special function signal clearing a bit configures a pin as a standard port pin P2 REG 1FD5H Port x Data Output P3 REG 1FDCH For an input set the corresponding Px REG bit
377. nd the base address as an indirect address register a WORD The following instructions use short indexed addressing LD AX 12H BX lt MEM WORD BX 12H MULB AX BL 3 CX AX BL XMEM BYTE CX 3 The instruction LD AX 12H B X loads AX with the contents of the memory location that resides at address BX 12H That is the instruction adds the constant 12 the offset to the contents of BX the base address then loads AX with the contents of the resulting address For example if BX contains 1000H then AX is loaded with the contents of location 1012H Short indexed address ing is typically used to access elements in a structure where BX contains the base address of the structure and the constant 12H in this example is the offset of a specific element in a structure You can also use the stack pointer in a short indexed instruction to access a particular location within the stack as shown in the following instruction LD AX 2 SP 4 2 4 2 Long indexed Addressing In a long indexed instruction you specify the base address as a 16 bit variable and the offset as an indirect address register a WORD The following instructions use long indexed addressing LD AX TABLE BX AX lt MEM WORD TABLE BX AND AX BX TABLE CX AX lt BX AND MEM WORD TABLE CX 8XC196NP 80C196NU USER S MANUAL intel ST AX TABLE BX MEM WORD TABLE BX lt AX ADDB AL BL LOOKUP CX AL lt BL MEM BYTE LOOKUP CX The instruction LD AX
378. ndexed instruction length and L is the long indexed instruction length 3 Forthe SCALL and SJMP instructions the three least significant bits of the opcode are concatenated with the eight bits to form an 11 bit 2 s complement offset A 59 8 196 80C196NU USER S MANUAL In lel Table A 9 lists instructions alphabetically within groups along with their execution times ex pressed in state times Table A 9 Instruction Execution Times in State Times Arithmetic Group 1 Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long Reg Mem Reg Mem Reg Mem Reg ADD 2 ops 4 5 6 8 7 9 6 8 7 9 ADD 3 ops 5 6 7 10 8 11 7 10 8 11 ADDB 2 ops 4 4 6 8 7 9 6 8 7 9 ADDB 3 ops 5 5 7 10 8 11 7 10 8 11 ADDC 4 5 6 8 7 9 6 8 7 9 ADDCB 4 4 6 8 7 9 6 8 7 9 CLR 3 CLRB 3 CMP 4 5 6 8 7 9 6 8 9 CMPB 4 4 6 8 7 9 6 8 9 CMPL 7 DEC 3 DECB 3 EXT 4 EXTB 4 INC 3 INCB 3 SUB 2 ops 4 5 6 8 7 9 6 8 7 9 SUB 3 ops 5 6 7 10 8 11 7 10 8 11 SUBB 2 ops 4 4 6 8 7 9 6 8 7 9 SUBB 3 ops 5 5 7 10 8 11 7 10 8 11 SUBC 4 5 6 8 7 9 6 8 7 9 SUBCB 4 4 6 8 7 9 6 8 7 9 NOTE The column entitled Reg lists the instruction execution times for accesses to the register file or peripheral SFRs The column entitled
379. ne of three ways 0 2 or nothing Each of the following load instructions loads AX with the contents of the variable THISVAR LD AX THISVAR 0 LD AX THISVAR ZERO REG LD AX THISVAR The following instructions also use zero indexed addressing ADD AX 1234H ZERO REG AX lt AX MEM WORD 1234H POP 5678H ZERO REG MEM WORD 5678H lt MEM WORD SP gt SB ESP 2 4 2 4 5 Extended Zero indexed Addressing The extended instructions can also use zero indexed addressing The only difference is that you specify the address as a 24 bit constant or variable The following extended instruction uses zero indexed addressing ZERO REG acts as a 32 bit fixed source of the constant zero for an extended indexed reference AX 23456H ZERO REG AX lt MEM WORD 23456H intel PROGRAMMING CONSIDERATIONS 4 3 ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS assembly language simplifies the choice of addressing modes Use these features wherever possible 4 31 Direct Addressing The assembly language chooses between direct and zero indexed addressing depending on the memory location of the operand Simply refer to the operand by its symbolic name If the operand is in the lower register file the assembly language chooses a direct reference If the operand is elsewhere in memory it chooses a zero indexed reference 4 3 2 Indexed Addressing The assembly language chooses between short indexed and long indexed
380. next return address moves to the top of the stack 8XC196NP 80C196NU USER S MANUAL Your program must load a word aligned even address into the stack pointer Select an address that is two bytes for 64 Kbyte mode or four bytes for 1 Mbyte mode greater than the desired starting address because the CPU automatically decrements the stack pointer before it pushes the first byte of the return address onto the stack Remember that the stack grows downward so allow sufficient room for the maximum number of stack entries The stack must be located in page 00H in either the internal register file or external RAM The stack can be used most efficiently when it is located in the upper register file The following example initializes the top of the upper register file as the stack LD SP 400 Load stack pointer 5 2 4 3 CPU Special function Registers SFRs Locations 0000 001 7H in the lower register file are the CPU SFRs Table 5 7 lists the CPU SFRs for the 8XC196NP and the 80C196NU and highlights those that are unique to the 80C196NU Appendix C describes the CPU SFRs Table 5 7 CPU SFRs 8XC196NP CPU SFRs 80C196NU CPU SFRs Address High Odd Byte Low Even Byte Address High Odd Byte Low Even Byte 0016H Reserved Reserved 0016H Reserved Reserved 0014H Reserved WSR 0014H WSR1 WSR 0012H MASK1 INT PEND1 0012H INT MASK1 INT PEND1 0010H Reserved Rese
381. ng mode Be sure to thoroughly consider the issues such as different access times for internal and external memory before using this dynamic switching capability On devices with no internal nonvolatile memory always connect EA to Vas is not implemented on the 80C196NU 0 VO Event Processor Array EPA Input Output pins These are the high speed input output pins for the EPA capture compare channels For high speed PWM applications the outputs of two EPA channels either EPAO and EPA1 or EPA2 and EPA3 can be remapped to produce a PWM waveform on a shared output pin see Generating a High speed PWM Output on page 10 14 EPA3 0 are multiplexed with P1 3 0 EPORT 3 0 y o Extended Addressing Port On the 8XC196NP this is 4 bit bidirectional memory mapped port On the 8XC196NU this is 4 bit bidirectional standard I O port EPORT 3 0 are multiplexed with A19 16 EXTINT3 0 External Interrupts In normal operating mode a rising edge on EXTINTx sets the EXTINTx interrupt pending bit EXTINTx is sampled during phase 2 CLKOUT high The minimum high time is one state time In standby and powerdown modes asserting the EXTINT x signal for at least 50 ns causes the device to resume normal operation The interrupt need not be enabled but the pin must be configured as a special function input see Bidirectional Port Pin Configurations on page 7 7 If the EXTINT x interrupt is enabled the CP
382. nnections Chapter 7 1 Ports contains information about initializing and configuring the ports Table 11 2 lists the sections with page numbers that contain the information for each port Table 11 2 Port Configuration Guide Port Where to Find Configuration Information Ports 1 4 Bidirectional Port Pin Configurations on page 7 7 and Bidirectional Port Considerations on page 7 9 EPORT Configuring EPORT Pins on page 7 17 MINIMUM HARDWARE CONSIDERATIONS Note 3 22 uF Notes 1 See the datasheet for the oscillator frequency range Fogc and the crystal manufacturer s datasheet for recommended load capacitors 2 The number of Vcc and Vss pins varies with package type see datasheet Be sure to connect all Vcc pins to the supply voltage and all Vss pins to ground 3 Connect the capacitor to RPD when using powerdown mode and the internal oscillator or phase locked loop NU only circuitry Otherwise RPD may float 4 No connection is required XTAL2 XTAL1 Voc RESET Note 2 NP Onl 4 7 uF Vss y T Hi 8XC196 Device READY BHE PLLEN1 NU Only RD Bus Control WB Note 4 INST ALE PLLEN2 NU Only A2415 02 Figure 11 1 Minimum Hardware Connections 8XC196NP 80C196NU USER S MANUAL intel 11 2 APPLYING AND REMOVING POWER When power is first applied to the device must remain continuously low for at least one state time afte
383. nquishes control by driving HOLD high In response the 8 196 deasserts HLDA and resumes control of the bus 13 31 8XC196NP 80C196NU USER S MANUAL intel If the 8XC196Nx has a pending external bus cycle while it is in hold another device has control of the bus it asserts BREQ to request control of the bus After the external device responds by releasing HOLD the 8 196 exits hold and then deasserts BREQ and HLDA 13 7 1 Enabling the Bus hold Protocol To use the bus hold protocol you must configure P2 3 BREQ P2 5 HOLD and P2 6 HLDA to operate as special function signals BREQ and HLDA are active low outputs HOLD is an active low input You must also set the hold enable bit HLDEN in the window selection register WSR 7 to en able the bus hold protocol Once the bus hold protocol has been selected the port functions of P2 3 P2 5 and P2 6 cannot be selected without resetting the device During the time that the pins are configured to operate as special function signals their special function values can be read from the P2 PIN x bits However the hold function can be dynamically enabled and disabled as described in Disabling the Bus hold Protocol 13 7 2 Disabling the Bus hold Protocol To disable hold requests clear WSR 7 The 8XC196Nx does not take control of the bus immedi ately after HLDEN is cleared Instead it waits for the current hold request to finish and then dis ables the bus ho
384. nterrupt A 3 A 52 EI instruction 6 10 A 3 17 A 52 59 67 EJMP instruction 4 5 A 2 A 17 A 52 A 57 A 64 ELD instruction 4 5 A 3 A 18 A 52 A 56 A 63 ELDB instruction 4 5 A 3 A 18 A 52 A 56 63 2 11 10 1 10 27 5 10 11 block diagram 10 2 capture data overruns 10 21 C 22 capture compare modules 10 8 programming 10 18 choosing capture or compare mode 10 19 C 20 compare modules programming 10 18 configuring pins 10 2 controlling the clock source and direction 10 16 10 17 C 46 C 47 determining event status 10 22 enabling a timer counter 10 16 10 17 C 46 C 47 enabling remapping for PWM 10 19 C 20 re enabling the compare event 10 20 C 21 resetting the timer in compare mode 10 21 C 22 Index 3 8 196 80C196NU USER S MANUAL resetting the timers 10 21 C 22 selecting the capture compare event 10 20 C 21 selecting the time base 10 19 C 20 selecting up or down counting 10 16 10 17 C 46 C 47 signals 10 2 using for PWM 6 26 6 32 See also port 1 port 6 PWM timer counters 0 CON 50 C 53 EPAO TIME C 50 C 53 1 CON 10 19 C 20 50 C 53 1 TIME C 50 53 EPA2 CON C 50 C 53 EPA2 TIME C 50 C 53 EPA3 0 B 8 EPA3 CON 10 19 C 20 C 50 C 53 EPA3 TIME C 50 C 53 EPA MASK C 50 C 53 EPA PEND C 50 C 53 EPAx CON 10 3 settings and operations 10 18 EPAx TIME 10 3 EPC 2 6 5 23 5 25 7 13 EPORT 2 6 2 11
385. nterrupt Set Cleared Pending Bit Latency Time Response Time 34 ssStieTimes 1 64 Kbyte or 1 Mbyte Mode 0262 02 Figure 6 3 PTS Interrupt Response Time 6 9 8XC196NP 80C196NU USER S MANUAL intel Table 6 4 Execution Times for PTS Cycles PTS Mode Execution Time in State Times Single transfer mode register register 18 per byte or word transfer 1 memory register 21 per byte or word transfer 1 memory memory 24 per byte or word transfer 1 Block transfer mode register register 13 7 per byte or word transfer 1 minimum memory registert 16 7 per byte or word transfer 1 minimum memory memory 19 7 per byte or word transfer 1 minimum PWM remap mode 15 PWM toggle mode 15 Register indicates an access to the register file or peripheral SFR Memory indicates an access to a memory mapped register or memory See Table 5 1 on page 5 4 for address information 6 5 PROGRAMMING THE INTERRUPTS The PTS select register PTSSEL selects either PTS service or a standard software interrupt ser vice routine for each of the maskable interrupt requests see Figure 6 4 The interrupt mask reg isters INT MASK and INT MASKI enable or disable mask individual interrupts see Figures 6 5 and 6 6 With the exception of the nonmaskable interrupt NMI bit INT MASKI 7 setting a bit enables the corresponding interrupt source and clearing a bit dis ables the source
386. nterrupt mask register see Table 8 2 on page 8 2 and execute the EI instruction to globally enable servicing of interrupts See Chapter 6 Standard and PTS Interrupts for more information about interrupts 8 4 5 Determining Serial Port Status You can read the SP STATUS register Figure 8 8 to determine the status of the serial port Reading SP STATUS clears all bits except TXE For this reason we recommend that you copy the contents of the SP STATUS register into a shadow register and then execute bit test instruc tions such as JBC and JBS on the shadow register Otherwise executing a bit test instruction clears the flags so any subsequent bit test instructions will return false values You can also read the interrupt pending register see Table 8 2 on page 8 2 to determine the status of the serial port interrupts 8 13 8XC196NP 80C196NU USER S MANUAL intel SP STATUS Address 1FB9H Reset State OBH The serial port status SP_STATUS register contains bits that indicate the status of the serial port 7 0 RPE RB8 RI TI Bit Bit i Number Mnemonic Function 7 RPE RB8 Received Parity Error Received Bit 8 is set if parity is disabled SP CON 2 0 and the ninth data bit received is high RB8 is set if parity is enabled CON 2 1 and a parity error occurred Reading STATUS clears this bit 6 RI Receive Interrupt This bi
387. nued Register Location Function PTSCON PTSCB 1 PTS Control Bits M2 0 PTS Mode M2 1 0 1 0 0 single transfer mode BW Byte Word Transfer 0 word transfer 1 byte transfer SU Update PTSSRC 0 reload original PTS source address after each byte or word transfer 1 retain current PTS source address after each byte or word transfer DU Update PTSDST 0 reload original PTS destination address after each byte or word transfer 1 retain current PTS destination address after each byte or word transfer Slt PTSSRC Autoincrement 0 do not increment the contents of PTSSRC after each byte or word transfer 1 increment the contents of PTSSRC after each byte or word transfer Dif PTSDST Autoincrement 0 do not increment the contents of PTSDST after each byte or word transfer 1 increment the contents of PTSDST after each byte or word transfer PTSCOUNT PTSCB 0 Consecutive Word or Byte Transfers Defines the number of words or bytes that will be transferred during the single transfer routine Each word or byte transfer is one PTS cycle Maximum value is 255 The DU DI bits and SU SI bits are paired in single transfer mode Each pair must be set or cleared together However the two pairs DU DI and SU SI need not be equal Figure 6 12 PTS Control Block Single Transfer Mode Continued The PTSCB in Table 6 5 defines nine PTS cycles Each cycle moves a single word from locati
388. ollers handbook order number 270646 Table 1 4 MCS 96 Microcontroller Datasheets Automotive Title and Description Order Number 87C196CA 87C196CB 20 MHz Advanced 16 Bit CHMOS Microcontroller with 272405 Integrated CAN 2 0 87C196JT 20 MHz Advanced 16 Bit CHMOS Microcontroller 272529 87C196JV 20 MHz Advanced 16 Bit CHMOS Microcontroller 272580 87 196 87C196JVAJT 87C196JR JQ Advanced 16 Bit CHMOS 270827 Microcontroller 1 87C196KT 87C196KS Advanced 16 Bit CHMOS Microcontroller 270999 87C196KT KS 20 MHz Advanced 16 Bit CHMOS Microcontroller 272513 Included in Automotive Products handbook order number 231792 1 7 8XC196NP 80C196NU USER S MANUAL intel Table 1 5 MCS 96 Microcontroller Quick References Title and Description Order Number 8XC196KR Quick Reference includes the JQ JR KR 272113 8XC196KT Quick Reference 272269 8XC196MC Quick Reference 272114 8XC196NP Quick Reference 272466 8 196 Quick Reference 272270 1 4 ELECTRONIC SUPPORT SYSTEMS Intel s FaxBack service and application BBS provide up to date technical information We also maintain several forums on CompuServe and offer a variety of information on the World Wide Web These systems are available 24 hours a day 7 days a week providing technical information whenever you need it 1 4 4 FaxBack Service FaxBack is an on demand publishing system that sends documents
389. omes the receive parity error bit This bit is reserved on the 8XC196NP For compatibility with future devices write zero to this bit Figure 8 6 Serial Port Control SP CON Register 8 196 80C196NU USER S MANUAL intel SP CON Continued Address Reset State The serial port control SP CON register selects the communications mode and enables or disables the receiver parity checking and nine bit data transmission For the 80C196NU it also enables or disables the divide by two prescaler 1FBBH 00H 7 0 8XC196NP PAR TB8 REN PEN M1 MO 7 0 80C196NU PRS PAR TB8 REN PEN M1 MO Bit Bit Number Mnemonic Function 1 0 M1 0 Mode Selection These bits select the communications mode M1 MO 0 0 mode 0 0 1 mode 1 1 0 mode 2 1 1 mode 3 This bit is reserved on the 8XC196NP For compatibility with future devices write zero to this bit Figure 8 6 Serial Port Control SP CON Register Continued intel SERIAL 1 0 SIO PORT SP BAUD Address 1FBCH Reset State 0000H The serial port baud rate SP BAUD register selects the serial port baud rate and clock source The most significant bit selects the clock source The lower 15 bits represent BAUD VALUE an unsigned integer that determines the baud rate The maximum BAUD VALUE is 32 767 7FFFH In asynchronous modes 1 2 and 3 the minimum BA
390. omparator Phase locked Oscillator Disable Clock Input Powerdown Disable Oscillator Powerdown Phase locked Loop Clock Multiplier Divide by two Circuit Disable Clocks PLLEN1 Standby Powerdown Generators CPU Clocks PH1 PH2 Disable Clocks Idle Standby Powerdown A3063 02 Figure 2 4 Clock Circuitry 80C196NU For both the 8XC196NP and 80C196NU the rising edges of PH and PH2 generate CLKOUT Figure 2 5 The clock circuitry routes separate internal clock signals to the CPU and the periph erals to provide flexibility in power management Reducing Power Consumption on page 12 3 describes the power management modes It also outputs the CLKOUT signal on the CLKOUT pin Because of the complex logic in the clock circuitry the signal on the CLKOUT pin is a de layed version of the internal CLKOUT signal This delay varies with temperature and voltage 2 8 intel ARCHITECTURAL OVERVIEW 7 lt i gt i a m 1 State Time gt lt 1 State Time gt PHI _ PH2 i CLKOUT Phase 1 Phase 2 Phase 2 0805 01 Figure 2 5 Internal Clock Phases The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state Table 2 2 lists state time durations at various frequencies Table 2 2 State Times at Various Frequencies f Frequ
391. on 20H to an external memory location The PTS transfers the first word to location 6000H Then it increments and updates the destination address and decrements the PISCOUNT register it does not increment the source address When the second cycle begins the PTS moves a second word from location 20H to location 6002H When PTSCOUNT equals zero the PTS will have filled locations 6000 600FH and an end of PTS interrupt is generated 6 22 intel STANDARD AND PTS INTERRUPTS Table 6 5 Single Transfer Mode PTSCB Unused Unused PTSDST HI 60H PTSDST LO 00H PTSSRC HI 00H PTSSRC LO 20H PTSCON 85H Mode 100 BW 0 SI SU 0 DI DU 1 PTSCOUNT 09H 6 6 4 Block Transfer Mode In block transfer mode an interrupt causes the PTS to move a block of bytes or words from one memory location to another See AP 445 8 196 Peripherals A User s Point of View for ap plication examples with code Figure 6 13 shows the PTS control block for block transfer modes In this mode each PTS cycle consists of the transfer of an entire block of bytes or words Because a PTS cycle cannot be interrupted the block transfer mode can create long interrupt latency The worst case latency could be as high as 500 states if you assume a block transfer of 32 words from one external memory location to another using an 8 bit bus with no wait states See Table 6 4 on page 6 10 for execution times of
392. only difference is that the register containing the indirect address must be a word aligned 24 bit register to allow access to the entire 1 Mbyte address space The following instructions use extended indirect addressing ELD AX EX AX lt MEM WORD EX ELDB AL EX AL lt MEM BYTE EX EST EX MEM WORD EX lt AX ESTB AL EX MEM BYTE EX lt AL 4 2 3 2 Indirect Addressing with Autoincrement You can choose to automatically increment the indirect address after the current access You spec ify autoincrementing by adding a plus sign 4 to the end of the indirect reference In this case the instruction automatically increments the indirect address by one if the destination is an 8 bit register or by two if it is a 16 bit register When your code is assembled the assembler automat ically sets the least significant bit of the indirect address register The following instructions use indirect addressing with autoincrement LD AX BX lt MEM WORD BX lt BX 2 ADDB AL BL CX AL lt BL MEM_BYTE CX p CX CX 4 1 PUSH AX SE MEM WORD SP MEM WORD AX AX lt AX 2 4 2 3 3 Extended Indirect Addressing with Autoincrement The extended load and store instructions can also use indirect addressing with autoincrement The only difference is that the register containing the indirect address must be a word aligned 24 bit register to allow access to the entire 1 Mbyte ad
393. ontroller processes it with an interrupt service routine that is stored in the memory location pointed to by the standard interrupt vector For example the PTS services the SIO transmit inter 6 6 intel STANDARD AND PTS INTERRUPTS rupt if PTSSEL 5 is set The interrupt vectors through FF204AH but the corresponding end of PTS interrupt vectors through FF200AH the standard SIO transmit interrupt vector When the end of PTS interrupt vectors to the interrupt service routine hardware clears the PTSSRV bit The end of PTS interrupt service routine should reinitialize the PTSCB if required and set the appro priate PTSSEL bit to re enable PTS interrupt service 6 4 INTERRUPT LATENCY Interrupt latency is the total delay between the time that the interrupt request is generated not acknowledged and the time that the device begins executing either the standard interrupt service routine or the PTS interrupt service routine A delay occurs between the time that the interrupt request is detected and the time that it is acknowledged An interrupt request is acknowledged when the current instruction finishes executing If the interrupt request occurs during one of the last four state times of the instruction it may not be acknowledged until after the next instruction finishes This additional delay occurs because instructions are prefetched and prepared a few state times before they are executed Thus the maximum delay between interrupt request and ac
394. open drain output or a high impedance input are identical An open drain output configuration requires an external pull up A high impedance input configuration requires that the corre sponding bit in PA REG be set This port has a higher drive capability than the other ports in order to support PWM high drive output requirements P4 MODE 1FD9H Port 4 Mode Each bit in this register determines whether the corre sponding pin functions as a standard I O port pin or is used for a special function signal P4 PIN 1FDFH Port 4 Pin State P4 PIN contains the current state of each port pin regardless of the pin mode setting P4 REG 1FDDH Port 4 Output Data P4 REG contains data to be driven out by the respective pins When a port pin is configured as an input the corre sponding bit in REG must be set 9 3 PWM OPERATION For the 8XC196NP REGO 0 CLKO controls the PWM output frequency by enabling or disabling the divide by two clock prescaler Enabling the prescaler causes the 8 bit counter to in crement once every two state times disabling it causes the counter to increment once every state time 8XC196NP 80C196NU USER S MANUAL intel For the 80C196NU two bits control the PWM output frequency REGO 0 CLKO and CON REGO 1 CLK1 The two bits control the PWM output frequency by enabling or disabling the divide by two or divide by four clock prescaler Each control reg
395. ops 5B SUBB Indexed 3 ops 5C MULUB Direct 3 ops 5D MULUB Immediate 3 ops 5E MULUB Indirect 3 ops 5F MULUB Indexed 3 ops 60 AND Direct 2 ops 61 AND Immediate 2 ops 62 AND Indirect 2 ops 63 AND Indexed 2 ops 64 ADD Direct 2 ops 65 ADD Immediate 2 ops 66 ADD Indirect 2 ops 67 ADD Indexed 2 ops 68 SUB Direct 2 ops 69 SUB Immediate 2 ops 6A SUB Indirect 2 ops 6B SUB Indexed 2 ops 6C MULU Direct 2 ops A 48 lel Table A 7 Instruction Opcodes Continued INSTRUCTION SET REFERENCE Hex Code Instruction Mnemonic 6D MULU Immediate 2 ops 6E MULU Indirect 2 ops 6F MULU Indexed 2 ops 70 ANDB Direct 2 ops 71 ANDB Immediate 2 ops 72 ANDB Indirect 2 ops 73 ANDB Indexed 2 ops 74 ADDB Direct 2 ops 75 ADDB Immediate 2 ops 76 ADDB Indirect 2 ops 77 ADDB Indexed 2 ops 78 SUBB Direct 2 ops 79 SUBB Immediate 2 ops 7A SUBB Indirect 2 ops 7B SUBB Indexed 2 ops 7 MULUB Direct 2 ops 7D MULUB Immediate 2 ops 7E MULUB Indirect 2 ops 7F MULUB Indexed 2 ops 80 OR Direct 81 OR Immediate 82 OR Indirect 83 OR Indexed 84 XOR Direct 85 XOR Immediate 86 XOR Indirect 87 XOR Indexed 88 CMP Direct 89 CMP Immediate 8A CMP Indirect 8B CMP Indexed 8C DIVU Direct 8E DIVU Indirect 8F DIVU Indexed 90 ORB Direct 91 ORB Immedi
396. orrow DEST DEST SRC 1 0 PSW Flag Settings Z N C V VT ST Livii 7 1 43 8 196 80C196NU USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format TIJMP TABLE INDIRECT JUMP Causes execution to continue at an address selected from a table of addresses The first word register TBASE contains the 16 bit address of the beginning of the jump table TBASE can be located in RAM up to FEH without windowing or above FFH with windowing The jump table itself can be placed at any nonreserved memory location on a word boundary in page FFH The second word register INDEX contains the 16 bit address that points to a register containing a 7 bit value This value is used to calculate the offset into the jump table Like TBASE INDEX can be located in RAM up to FEH without windowing or above FFH with windowing Note that the 16 bit address contained in INDEX is absolute it disregards any windowing that may be in effect when the TIJMP instruction is executed The byte operand MASK is 7 bit immediate data to mask INDEX MASK is ANDed with INDEX to determine the offset OFFSET OFFSET is multiplied by two then added to the base address TBASE to determine the destination address DEST X in page FFH INDEX AND MASK OFFSET 2 x OFFSET TBASE DEST X PC lt DEST X PSW Flag S
397. ose register RAM with direct addressing through a 32 byte window Table 5 10 on page 5 17 shows that you need to write 4AH to the window selection register It also shows that the base address of the 32 byte memory area is 0140H To determine the offset subtract that base ad dress from the address to be accessed 014BH 0140H 000BH Add the offset to the base ad dress of the window in the lower register file from Table 5 11 The direct address is 000BH 00 for a WSR window or 006BH 000BH 0060H for a WSR1 window 5 3 2 2 64 byte Windowing Example Assume that you wish to access the SFR at location 1F8CH with direct addressing through a 64 byte window Table 5 10 on page 5 17 shows that you need to write 3EH to the window selection register It also shows that the base address of the 64 byte memory area is 1F80H To determine the offset subtract that base address from the address to be accessed 1F8CH 1F80H 000 Add the offset to the base address of the window in the lower register file from Table 5 11 The direct address is 000CH 0 for a WSR window or 004CH 000CH 0040H for a WSRI window 5 3 2 3 128 byte Windowing Example Assume that you wish to access the SFR at location 1F82H with direct addressing through a 128 byte window Table 5 11 on page 5 18 shows that you need to write 1FH to the window selection register It also shows that the base address of the 128 byte memory are
398. osite See Table C 4 Software can clear this flag hardware does not clear it 1 OVF Overflow Flag This bit indicates that an overflow occurred during the preceding accumu lation See Table C 4 This flag is dynamic it can change after each accumulation 0 STSAT Sticky Saturation Flag This bit indicates that a saturation has occurred during accumulation with saturation mode enabled See Table C 4 Software can clear this flag hardware does not clear it intel REGISTERS ACC STAT Table C 4 Effect of SME and FME Bit Combinations SME FME Description 0 0 Sets the OVF and STOVF flags if the sign bits of the accumulator and the addend the number to be added to the contents of the accumulator are equal but the sign bit of the result is the opposite 0 1 Shifts the addend the number to be added to the contents of the accumulator left by one bit before adding it to the accumulator Sets the OVF and STOVF flags if the sign bits of the accumulator and the addend are equal but the sign bit of the result is the opposite 1 0 Accumulates a signed integer value up or down to saturation and sets the STSAT flag Positive saturation changes the accumulator value to 7FFFFFFFH negative saturation changes the accumulator value to 80000000H Accumulation proceeds normally after saturation which means that the accumulator value can increase from a negative saturation or decrease from a
399. ou must still write to Px REG to initialize the pin For a bidirectional pin to function as an input either special function or port pin you must set Px REG 7 7 8 196 80C196NU USER S MANUAL Table 7 6 Control Register Values for Each Configuration intel Desired Pin Configuration Configuration Register Settings Standard Signal DIR REG Complementary output driving 0 0 0 0 Complementary output driving 1 0 0 1 Open drain output strongly driving 0 1 0 0 Open drain output high impedance 1 0 1 Input 1 0 1 Special function signal DIR REG Complementary output output value controlled by peripheral 0 1 X Open drain output output value controlled by peripheral 1 1 X Input 1 1 1 During reset and until the first write to Px MODE the pins are weakly held high 7 2 3 Bidirectional Port Pin Configuration Example Assume that you wish to configure the pins of a bidirectional port as shown in Table 7 7 Table 7 7 Port Configuration Example Port Pin s Configuration Data Px 0 Px 1 high impedance input high impedance Px 2 Px 3 open drain output 0 4 open drain output 1 assuming external pull up Px 5 Px 6 complementary output 0 Px 7 complementary output 1 To do so you could use the following example code segment Table 7 8 shows the state of each pin after reset and aft
400. ounter structure T2CONTROL 2 0 3 T2CLK Y Timer 2 14 Prescaler Quadrature Count Module Timer 1 Overflow OVRTM Interrupt T2CONTROL 6 Quadrature Direction Direction T1CONTROL 2 0 T1CONTROL 6 Timer 1 TicLk Prescaler 4 Module Quadrature Count OVRTM T1DIR Interrupt T1CONTROL 6 Direction Quadrature Direction Disable prescaler if quadrature clocking is selected A0250 02 Figure 10 2 EPA Timer Counters 10 5 8XC196NP 80C196NU USER S MANUAL intel The timer counters can be used as time bases for input captures output compares and pro grammed interrupts software timers When a counter increments from FFFEH to FFFFH or dec rements from 0001H to 0000H the counter overflow interrupt pending bit is set This bit can optionally cause an interrupt The clock source direction control source count direction and res olution of the input capture or output compare are all programmable see Programming the Tim ers on page 10 15 The maximum count rate is one half the internal clock rate or f 4 see Internal Timing on page 2 7 This provides a minimum resolution for an input capture or out put compare of 160 ns at f 25 MHz for 8XC196NP and 80 ns at f 50 MHz for the 80C196NU 4x prescaler divisor resolution f where prescaler divisor is the clock prescaler divisor from the registers see Timer 1 Control T1 CONT
401. overflow occurs and the overflow OVF flag is set Saturation mode prevents an underflow or overflow of the accumulated value In saturation mode the accumulator s value is changed to for a positive saturation or 80000000H for a negative saturation and the sticky sat uration STSAT flag is set The following two examples illustrate the contents of the accumulator as a result of positive and negative saturation respectively 7FFFFFFFH 0111 1111 1111 1111 1111 1111 1111 1111 231 1 42147483647 80000000H 1000 0000 0000 0000 0000 0000 0000 0000 2147483648 intel ADVANCED MATH FEATURES 3 2 2 Fractional Mode A signed fractional contains an imaginary decimal point between the sign bit the MSB and the adjacent bit These examples illustrate the representation of 32 bit signed fractional numbers 0 111 1111 1111 1111 1111 1111 1111 1111 214 499041 2147483648 0 000 0000 0000 0000 0000 0000 0000 0000 0 1 111 1111 1111 1111 1111 1111 1111 1111 NONU AM 2147483648 1 000 0000 0000 0000 0000 0000 0000 0000 1 Fractional mode shifts the result of a multiplication instruction left by one bit before writing the result to the accumulator This left shift eliminates the extra sign bit when both operands are signed leaving a correctly signed result and the correct decimal placement 8XC196NP 80C196NU USER S MANUAL intel 3 3 ACCUMULATOR REGISTER ACC 0x 32 bit accumulator register Fi
402. overlapping address ranges and different bus parameter values wait states bus width and multiplexing Accessing a location in such an overlapping address range can cause unpredictable results 13 11 8XC196NP 80C196NU USER S MANUAL intel Use the following sequence to initialize the chip select registers after reset l Initialize chip select output 0 11 Clear ADDRMSKO 12 Write to ADDRCOMO to establish the desired base address 1 3 Write to ADDRMSKO to establish the desired address range 1 4 Write the desired bus parameter values to BUSCONO 2 While executing in the address range defined in step 1 for chip select output 0 use the following sequence to initialize chip select outputs 1 5 Begin with x 1 21 Load ADDRMSKx with OFFFH 2 2 Write to ADDRCOM 5 to establish the desired base address 2 3 Write to ADDRMSK to establish the desired address range 2 4 Write the desired bus parameter values to BUSCONx 2 5 Repeat steps 2 1 2 4 for x 2 5 13 3 5 Example of a Chip select Setup This section shows an example of setting up the chip select unit and provides details of the chip select output calculation This example shows how to set up the chip select registers for the sys tem shown in Figure 13 5 For each address range the BUSCONx register see Figure 13 4 spec ifies the address data multiplexing bit 7 the bus width bit 6 and the number of wait states bits 1 0 Table 13 8 lists the character
403. per Register File 0 03COH 5EH 2FH 0 5DH 0380H 5CH 2EH 17H 0360H 5BH 0340H 5AH 2DH 0320H 59H 0300H 58H 2CH 16H 02 57 02 0 56 2BH 02A0H 55H 0280H 54H 2AH 15H 0260H 53H 0240H 52H 29H 0220H 51H 0200H 50H 28H 14H 01E0H 4FH 01COH 4EH 27H 01A0H 4DH 0180H 4CH 26H 13H 0160H 4BH 0140H 4AH 25H 0120H 49H 0100H 48H 24H 12H t For the 8XC196NP locations 1FE0 1FFFH contain memory mapped SFRs that cannot be windowed Reading these locations through a window returns FFH writing these locations through a window has no effect For the 80C196NU these locations are not memory mapped they can be windowed 8 196 80C196NU USER S MANUAL intel Table 5 11 Windowed Base Addresses Window Size WSR Windowed Base Address Base Address in Lower Register File WSR1 Windowed Base Address Base Address in Lower Register File 80C196NU Only 32 byte OOEOH 0060H 64 byte 00COH 0040H 128 byte 0080H Appendix C includes a table of the windowable SFRs with the window selection register values and direct addresses for each window size The following examples explain how to determine the WSR value and direct address for any windowable location An additional example shows how to set up a window by using the linker locator 5 3 2 1 32 byte Windowing Example Assume that you wish to access location 014BH a location in the upper register file used for gen eral purp
404. per four address lines 19 16 are implemented by the EPORT Table 13 1 shows how the external address depends on the number of EPORT lines used to address the external device Table 13 1 Example of Internal and External Addresses EPORT Lines Connected tothe Internal Address Device pins External Device A16 XF2080H F2080H 12080H A17 16 xF2080H F2080H 32080H A18 16 xF2080H F2080H 72080H A19 16 xF2080H F2080H F2080H 13 1 8 196 80C196NU USER S MANUAL 13 2 EXTERNAL MEMORY INTERFACE SIGNALS intel Table 13 2 describes the external memory interface signals For some signals the pin has an al ternate function shown in the Multiplexed With column In some cases the alternate function is a port signal e g P2 7 Chapter 7 I O Ports describes how to configure a pin for its I O port function and for its special function In other cases the signal description includes instructions for selecting the alternate function Table 13 2 External Memory Interface Signals Name Type Description Multiplexed With A15 0 yo System Address Bus These address lines provide address bits 15 0 during the entire external memory cycle during both multiplexed and demultiplexed bus modes A19 16 Address Lines 16 19 These address lines provide address bits 16 19 during the entire external memory cycle supporting extended addressing of the 1 Mbyte address
405. perating conditions Table B 4 defines the symbols used to rep resent the pin status Refer to the DC Characteristics table in the datasheet for actual specifica tions for Vor Vy and Table B 4 Definition of Status Symbols Symbol Definition Symbol Definition 0 Voltage less than or equal to Vo Vi MDO Medium pull down 1 Voltage greater than or equal to Voy Vin MD1 Medium pull up HiZ High impedance WKO Weak pull down 1070 Low impedance strongly driven low WK1 Weak pull up LoZ1 Low impedance strongly driven high ODIO Open drain I O Table B 5 8XC196NP and 80C196NU Pin Status Power Multiplexed During RESETE Port Pins with RESET Inactive Hold Idle cle Note 11 Standby NU only P1 3 0 EPA3 0 WK1 WK1 Note 1 Note 1 Note 1 P1 4 T1CLK WK1 WK1 Note 1 Note 1 Note 1 P1 5 T1DIR WK1 WK1 Note 1 Note 1 Note 1 P1 6 T2CLK WK1 WK1 Note 1 Note 1 Note 1 P1 7 T2DIR WK1 WK1 Note 1 Note 1 Note 1 P2 0 TXD WK1 WK1 Note 1 Note 1 Note 1 P2 1 RXD WK1 WK1 Note 1 Note 1 Note 1 2 2 EXTINTO WK1 WK1 Note 1 Note 1 Note 1 2 3 BREQ WK1 WK1 Note 1 Note 1 Note 1 P2 4 EXTINT1 WK1 WK1 Note 1 Note 1 Note 1 P2 5 HOLD WK1 WK1 Note 1 Note 1 Force 0 P2 6 HLDA WK1 WK1 Note 1 Note 1 0 P2 7 CLKOUT CLKOUT
406. ponding port pin 0 standard port pin 1 special function signal Table C 12 lists the special function signals for each pin Table C 11 Px MODE Addresses and Reset Values Register Address Reset Value P1 MODE 1FDOH 00H P2 MODE 1FD1H 80H P3 MODE 1FD8H 01H P4 MODE 1FD9H 00H Table C 12 Special function Signals for Ports 1 4 Port 1 Port 2 Port 3 Port 4 Special Special Special Special Pin function Pin function Pin function Pin function Signal Signal Signal Signal P1 0 EPAO P2 0 TXD P3 0 50 4 0 PWMO P1 1 EPA1 P2 1 RXD P3 1 CS1 P4 1 PWM1 P1 2 EPA2 P2 2 EXTINTO P3 2 CS2 P4 2 PWM2 P1 3 EPA3 P2 3 BREQ P3 3 CS3 P4 3 P1 4 2 4 P3 4 CS4 P1 5 T1DIR P2 5 HOLD P3 5 CS5 P1 6 T2CLK P2 6 HLDA P3 6 EXTINT2 P1 7 T2DIR P2 7 CLKOUT P3 7 EXTINT3 C 31 8 196 80C196NU USER S MANUAL intel Px PIN Px PIN Address Table C 13 x 1 4 Reset State Each bit of the port x pin input Px_PIN register reflects the current state of the corresponding pin regardless of the pin configuration 7 0 x 1 3 PIN7 6 5 PIN4 PINS PIN2 PIN1 PINO 7 0 4 2 PINO Bit Number Bit Function Mnemonic 7 0 PIN7 0 Port x Pin y Input Value This bit contains the current state of Px y C 32 Table C 13 Px_PIN Addresses and Reset Values Register Addres
407. positive saturation 1 1 Shifts the addend the number to be added to the contents of the accumulator left by one bit before adding it to the accumulator Accumulates a signed integer value up or down to saturation and sets the STSAT flag Positive saturation changes the accumulator value to 7FFFFFFFH negative saturation changes the accumulator value to 80000000H Accumu lation proceeds normally after saturation which means that the accumulator value can increase from a negative saturation or decrease from a positive saturation 8 196 80C196NU USER S MANUAL intel ADDRCOMx ADDRCOMx Address Table C 5 x 0 5 Reset State The address compare ADDRCOMx register specifies the base lowest address of the address range The base address of a 2 byte address range must be on 2 byte boundary 15 8 BASE19 BASE18 BASE17 BASE16 7 0 BASE15 BASE14 BASE13 BASE12 BASE11 BASE10 BASE9 BASE8 Function 15 12 Reserved for compatibility with future devices write zeros to these bits 11 0 5 19 8 Base Address Bits These bits are the 12 most significant bits of the base address of the address range assigned to chip select x Table C 5 ADDRCOMx Addresses and Reset Values Register Address Reset Value ADDRCOMO 1F40H OF20H ADDRCOM1 1F48H X000H ADDRCOM2 1F50H X000H ADDRCOM3 1F58H X000H ADDRCOM4 1F
408. power saving mode In idle mode asserting any enabled interrupt causes the device to resume normal operation On circuit Emulation Holding ONCE high during the rising edge of RESET places the device into on circuit emulation ONCE mode This mode puts all pins into a high impedance state thereby isolating the device from other components in the system The value of ONCE is latched when the RESET pin goes inactive While the device is in ONCE mode you can debug the system using a clip on emulator To exit ONCE mode reset the device by pulling the RESET signal low To prevent accidental entry into ONCE mode connect the ONCE pin to Va 12 1 8XC196NP 80C196NU USER S MANUAL intel Table 12 1 Operating Mode Control Signals Continued Signal Port Pin Description PLLEN2 1 Phase Lock Loop 1 and 2 Enable 80C196NU These input pins are used to enable the on chip clock multiplier only feature and select either the doubled or quadrupled clock speed CAUTION If PLLEN1 is held low while PLLEN2 is held high the device will enter into an unsupported test mode RESET VO Reset A level sensitive reset input to and open drain system reset output from the microcontroller Either a falling edge on RESET or an internal reset turns on a pull down transistor connected to the RESET pin for 16 state times In the powerdown standby and idle modes asserting
409. preg A pointer register Must be aligned on an address that is evenly divisible by 4 The value must be in the range of 00 FCH Sbreg A byte register in the lower register file that serves as the source of the instruction operation Slreg A 32 bit register in the lower register file that serves as the source of the instruction operation Must be aligned on an address that is evenly divisible by 4 The value must be in the range of 00 FCH Swreg A word register in the lower register file that serves as the source of the instruction operation Must be aligned on an address that is evenly divisible by 2 The value must be in the range of 00 treg A 24 bit register in the lower register file Must be aligned on an address that is evenly divisible by 4 The value must be in the range of 00 FCH waop A word operand that is addressed by any addressing mode w2 reg A double word register in the lower register file Must be aligned on an address that is evenly divisible by 4 The value must be in the range of 00 FCH Although w2 reg is similar to reg there is a distinction w2 reg consists of two halves each containing a 16 bit address reg is indivisible and contains a 32 bit number wreg A word register in the lower register file When it could be unclear whether this variable refers to a source or a destination register it is prefixed with an S or a D Must be aligned on an address that is evenly divisible by 2 The value must be in the range
410. provides reference information for the device pins in cluding descriptions of the pin functions reset status of the I O and control pins and package pin assignments Appendix C Registers provides a compilation of all device special function registers SFRs arranged alphabetically by register mnemonic It also includes tables that list the win dowed direct addresses for all SFRs in each possible window Glossary defines terms with special meaning used throughout this manual Index lists key topics with page number references 1 2 intel GUIDE TO THIS MANUAL 1 2 NOTATIONAL CONVENTIONS AND TERMINOLOGY The following notations and terminology are used throughout this manual The Glossary defines other terms with special meanings addresses assert and deassert clear and set instructions The pound symbol has either of two meanings depending on the context When used with a signal name the symbol means that the signal is active low When used in an instruction the symbol prefixes an immediate value in immediate addressing mode In this manual both internal and external addresses use the number of hexadecimal digits that correspond with the number of available address lines For example the highest possible internal address is shown as FFFFFFH while the highest possible external address is shown as FFFFFH When writing code use the appropriate address conventions for the software tool you are u
411. ptional for the 8XC196NP but is not available for the 80C196NU The second character of the device name indicates the presence and type of nonvolatile memory 80C196NP none 83C196NP ROM 2 Register RAM amounts include the 24 bytes allocated to core special function registers SFRs and the stack pointer 3 I O pins include address data and bus control pins and 32 I O port pins 2 3 BLOCK DIAGRAM Figure 2 1 shows the major blocks within the device The core of the device Figure 2 2 consists of the central processing unit CPU and memory controller The CPU contains the register file and the register arithmetic logic unit RALU The CPU connects to both the memory controller and an interrupt controller via a 16 bit internal bus An extension of this bus connects the CPU to the internal peripheral modules In addition an 8 bit internal bus transfers instruction bytes from the memory controller to the instruction register in the RALU Optional Interrupt Core p Clock and PTS Power Mgmt A2801 01 Figure 2 1 8 196 and 80C196NU Block Diagram 2 2 intel ARCHITECTURAL OVERVIEW Memory Controller Register File RALU Microcode Engine Prefetch Queue Slave PC Register ALU Address Register RAM Master PC Data Register CPU SFRs Registers Bus Controller A2797 01 Figure 2 2 Block Diagram of the Core 2 3 4 CPU Control The CPU is controlled by the mi
412. put P2 MODE 1FC9H Port 2 Mode This register selects either the general purpose input output function or the peripheral function for each pin of port 2 Set P2 MODE 1 0 to configure TXD P2 0 and RXD P2 1 for the SIO port P2 PIN 1FCFH Port 2 Pin State Two bits of this register contain the values of the TXD P2 0 and RXD P2 1 pins Read P2 PIN to determine the current value of the pins P2 REG 1FCDH Port 2 Output Data This register holds data to be driven out on the pins of port 2 Set P2 REG 1 for the RXD P2 1 pin Write the desired output data for the TXD P2 0 pin to P2 REG O SBUF RX 1FB8H Serial Port Receive Buffer This register contains data received from the serial port SBUF TX 1FBAH Serial Port Transmit Buffer This register contains data that is ready for transmission In modes 1 2 and 3 writing to TX starts a transmission In mode 0 writing to SBUF starts a transmission only if the receiver is disabled SP CON 3 0 SP BAUD 1FBCH 1FBDH Serial Port Baud Rate This register selects the serial port baud rate and clock source The most significant bit selects the clock source The lower 15 bits represent the BAUD VALUE an unsigned integer that determines the baud rate SP CON 1FBBH Serial Port Control This register selects the communications mode and enables or disables the receiver parity checking and ninth bit data transmis sions The TB8 bit is cleared after each transmission 8XC196NP 80C19
413. put E 58 2 HiZ HiZ HiZ pul HiZ XTAL2 Osc output Osc output Osc HiZ Osc LoZ0 1 LoZ0 1 output output 1040 1 1020 1 NOTE 1 If Px MODE y 0 then port is as programmed If MODE y 1 then as specified by the associ ated peripheral 2 fP2 MODE 7 0 then port is as programmed If P2 MODE 7 1 then 1 3 Used as chip select If HLDA 0 then WK1 If HLDA 1 then LoZ1 Used as port then port is as programmed 4 Used as chip select WK1 Used as port then port is as programmed 5 When used as extended address If HLDA 1 then 0 If HLDA 0 then HiZ When used as EPORT then port value 6 When used as extended address then When used as EPORT then port value 7 f HLDA 1 then LoZO If HLDA 0 then HiZ 8 When used as extended address then previous address When used as EPORT then port value 9 If HLDA 1 then Lozo If HLDA 0 then WKO 10 If HLDA 1 then LoZ1 If HLDA 0 then WK1 11 The values in this column are valid until user code configures the specific signal i e until Px MODE is written intel Registers APPENDIX C REGISTERS This appendix provides reference information about the device registers Table C 1 lists the mod ules and major components of the device with their related configuration and status registers Ta ble C 2 lists the registers arranged alphabetically by mnemonic along with their names addresses and reset values Following the
414. r reset 13 18 during bus hold 13 30 See also write control signals WRH 13 3 13 5 13 33 13 35 B 12 See also write control signals Write strobe mode example 13 36 Write control modes 13 1 13 33 13 36 byte writes and word writes 13 35 standard 13 33 Write control signals 13 33 13 34 decoding logic 13 34 WRL 13 5 13 33 13 35 B 12 See also write control signals WSO and 51 13 11 13 26 WSR 5 14 13 32 WSRI 5 12 5 13 5 15 5 18 X X defined 1 5 x defined 1 4 XCH instruction A 2 A 3 A 45 A 47 A 56 63 instruction 2 A 3 45 47 56 63 instruction 2 46 49 54 A 61 XORB instruction 2 46 A 49 50 A 54 61 XTALI 11 2 B 12 and Miller effect 11 7 Index 11 8 196 80C196NU USER S MANUAL and SIO baud rate 8 12 8 13 hardware connections 11 6 11 7 XTAL2 11 2 B 12 hardware connections 11 6 11 7 Y y defined 1 4 2 Zero 7 flag 4 5 A 22 A 23 A 24 A 25 C 34 Index 12 lel
415. r the offset between the end of this instruction and the target label effecting the jump The offset must be in the range of 128 to 127 if specified bit 0 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JBC breg bitno cadd 00110606 breg disp NOTE The displacement disp is sign extended to 24 bits JBS JUMP IF BIT IS SET Tests the specified bit If the bit is clear control passes to the next sequential instruction If the bit is set this instruction adds to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in the range of 128 to 127 if specified bit 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JBS breg bitno cadd 00111bbb breg disp NOTE The displacement disp is sign extended to 24 bits A 21 8XC196NP 80C196NU USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format JC JUMP IF CARRY FLAG IS SET Tests the carry flag If the carry flag is clear control JC cadd passes to the next sequential instruction If the carry flag is set this instruction adds to 11011011 disp the program counter the offset between the end of this instruction and the target label NOTE The displacement disp is sign effecting the jump
416. r the power supply is within tolerance and the oscillator clock has stabilized oth erwise operation might be unpredictable Similarly when powering down a system should be brought low before Vec is removed otherwise an inadvertent write to an external lo cation might occur Carefully evaluate the possible effect of power up and power down sequenc es on a system 11 3 NOISE PROTECTION TIPS The fast rise and fall times of high speed CMOS logic often produce noise spikes on the power supply lines and outputs To minimize noise it is important to follow good design and board lay out techniques We recommend liberal use of decoupling capacitors and transient absorbers Add 0 01 uF bypass capacitors between o and each Vg pin to reduce noise Figure 11 2 Place the capacitors as close to the device as possible Use the shortest possible path to connect lines to ground and each other 8XC196 Device Digital Ground Plane 5V Return Power Source t Use 0 01 uF bypass capacitors for maximum decoupling A3069 01 Figure 11 2 Power and Return Connections 11 4 intel MINIMUM HARDWARE CONSIDERATIONS Multilayer printed circuit boards with separate V and ground planes also help to minimize noise For more information on noise protection refer to AP 125 Designing Microcontroller Sys tems for Noisy Environments and AP 711 EMI Design Techniques for Microcontrollers in Auto motive Applica
417. ral Components 296467 Comprehensive information on Intel s peripheral components including datasheets application notes and technical briefs Flash Memory 2 volume set 210830 A collection of datasheets and application notes devoted to techniques and information to help design semiconductor memory into an application or system Packaging 240800 Detailed information on the manufacturing applications and attributes of a variety of semiconductor packages Development Tools Handbook 272326 Information on third party hardware and software tools that support Intel s embedded microcontrollers Included in handbook set order number 231003 Table 1 2 Application Notes Application Briefs and Article Reprints Title Order Number AB 71 Using the SIO on the 8XC196MH application brief 272594 AP 125 Design Microcontroller Systems for Electrically Noisy Environments ttt 210313 AP 155 Oscillators for Microcontrollers 230659 AR 375 Motor Controllers Take the Single Chip Route article reprint 270056 AP 406 MCS 96 Analog Acquisition Primer 111 270365 Included in Automotive Products handbook order number 231792 tt Included in Embedded Applications handbook order number 270648 ttt Included in Automotive Products and Embedded Applications handbooks 1 6 intel GUIDE TO THIS MANUAL Table 1 2 Application Notes Application Briefs and Article Reprints Continued
418. ransfers to the corresponding interrupt vector The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector NMI Nonmaskable Interrupt FF203EH pin FF203CH EXTINT2 EXTINT2 FF203AH OVR2 3 EPA Capture Channel 2 or 3 Overrun FF2038H OVRO 11 EPA Capture Channel 0 or 1 Overrun FF2036H EPAS3 EPA Capture Compare Channel 3 FF2034H EPA2 EPA Capture Compare Channel 2 FF2032H EPA1 EPA Capture Compare Channel 1 FF2030H An overrun on the EPA capture compare channels can generate the multiplexed capture overrun interrupts The EPA MASK and EPA PEND registers decode these multiplexed interrupts Write to EPA MASK to enable the interrupt sources read EPA PEND to determine which source caused the interrupt C 28 intel REGISTERS ONES REG ONES REG Address E Reset State The two byte ones register ONES is always equal to FFFFH It is useful as a fixed source of all ones for comparison operations 02H FFFFH 15 One high byte 0 One low byte Function 15 0 One These bits are always equal to FFFFH C 29 8 196 80C196NU USER S MANUAL intel Px DIR Px DIR Address Table C 10 1 4 Reset State Each pin of port x can operate in any of the standard modes of operation complementary output open drain output or high impedance input The port x I O direction
419. re DTE Pages FFH and ett tp ve o oe I betta ee 5 3 Register File Memory 5 10 WindoWlrig n Dt Penes ete 5 13 Window Selection WSR 5 14 Window Selection 1 WSR1 5 15 The 24 bit Program Counter i 9503 Formation of Extended and Nonextended Addresses 93024 A 64 Kbyte System With an 8 bit 8 5 27 A 64 Kbyte System with Additional Data Storage 5 29 Example System Using the 1 Mbyte eme 5 31 Flow Diagram for PTS and Standard Interrupts 6 2 Standard Interrupt Response 6 9 PTS Interrupt Response 9 PTS Select PTSSEL Register eese O71 1 Interrupt Mask INT MASK 6 12 Interrupt Mask 1 INT MASK1 eme 6 13 Interrupt Pending INT PEND em 6 16 Interrupt Pending 1 INT PEND1 6 17 PTS Control Blocks rete ege tegi ER dates Itb e te
420. re tools require that REG be equal to 00H The 80C196NU forces all nonextended data accesses to page 00H You cannot use EP REG to change pages After a HOLD request the 80C196NU s chip select channels become inactive before the 80C196NU asserts HLDA In demultiplexed mode the 80C196NU s RD and WR signals are asserted one clock period 1t earlier than on the 80C196NP intel Advanced Math Features intel CHAPTER 3 ADVANCED MATH FEATURES The 80C196NU is the first member of the MCS 96 microcontroller family to incorporate en hanced 16 bit multiplication instructions for performing multiply accumulate operations and a dedicated 32 bit accumulator register for storing the results of these operations The accumulator and the enhanced instructions combine to decrease the amount of time required to perform mul tiply accumulate operations The instructions and accumulator support signed and unsigned inte gers as well as signed fractional data This chapter describes the 80C196NU s advanced mathematical features 3 4 ENHANCED MULTIPLICATION INSTRUCTIONS The 16 bit multiplication instructions MULU and MUL that exist for all MCS 96 microcontrol lers have been enhanced for the 80C196NU The MULU instruction supports unsigned integers while the MUL instruction supports signed integers and signed fractionals When you execute a 16 bit multiplication instruction with a destination address that is OFH or below the 80C196NU au
421. reater than instruction for signed operands 4 4 intel PROGRAMMING CONSIDERATIONS 4 1 11 Floating Point Operations The hardware does not directly support operations on REAL floating point variables Those op erations are supported by floating point libraries from third party tool vendors See the Develop ment Tools Handbook The performance of these operations is significantly improved by the NORML instruction and by the sticky bit ST flag in the processor status word PSW The NORML instruction normalizes a 32 bit variable the sticky bit ST flag can be used in conjunc tion with the carry C flag to achieve finer resolution in rounding 4 1 12 Extended Instructions This section briefly describes the instructions that have been added to enable code execution and data access anywhere in the 1 Mbyte address space NOTE In 1 Mbyte mode ECALL LCALL and SCALL always push two words onto the stack therefore a RET must always pop two words from the stack Because of the extra push and pop operations interrupt routines and subroutines take slightly longer to execute in 1 Mbyte mode than in 64 Kbyte mode EBMOVI Extended interruptable block move Moves a block of word data from one memory location to another This instruction allows you to move blocks of up to 64K words between any two locations in the address space It uses two 24 bit autoincrementing pointers and a 16 bit counter EBR Extended branch This instruction is
422. rect Mnemonic Direct Immed Extended indexed Normal Autoinc ECALL 1 Mbyte mode 22 Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long LCALL 1 Mbyte mode 22 18 64 Kbyte mode 13 RET 1 Mbyte mode a 64 Kbyte mode 274 SCALL 18 1 Mbyte mode 13 64 Kbyte mode TRAP 1 Mbyte mode 25 64 Kbyte mode 18 NOTE The column entitled Reg lists the instruction execution times for accesses to the register file or peripheral SFRs The column entitled Mem lists the instruction execution times for accesses to all memory mapped registers I O or memory See Table 5 1 on page 5 4 for address information A 65 8 196 80C196NU USER S MANUAL Table A 9 Instruction Execution Times in State Times Continued In lel Conditional Jump Mnemonic Short Indexed DJNZ 5 jump not taken 9 jump taken DJNZW 6 jump not taken 10 jump taken JBC 5 jump not taken 9 jump taken JBS 5 jump not taken 9 jump taken JC 4 jump not taken 8 jump taken JE 4 jump not taken 8 jump taken JGE 4 jump not taken 8 jump taken JGT 4 jump not taken 8 jump taken JH 4 jump not taken 8 jump taken JLE 4 jump not taken 8 jump taken JLT 4 jump not taken 8 jump taken JNC 4 jump not t
423. registers have different parameter values and an address in their overlapping region is accessed the results are unpredictable See Example of a Chip select Setup on page 13 12 for a chip select initialization procedure that avoids this difficulty Table 13 6 Base Addresses for Several Sizes of the Address Range Address Range Size 1 Mbyte 512 Kbyte 256 Kbyte 512 bytes 256 bytes 00000H 00000H 00000H 00000H 00000H 80000H 40000H 00200H 00100H 80000H 00400H 00200H C0000H 00600H 00300H Addresses FFEOOH FFDOOH FFFOOH For an address range satisfying these restrictions set up ADDRCOMx and ADDRMSKx reg isters as follows Place the 12 most significant bits of the base address into bits BASE19 8 in the ADDRCOMXx register Figure 13 2 For an address range of 2 bytes set the n most significant bits of MASK19 8 in the ADDRMS Kx register Figure 13 3 where n 20 n For example assume that chip select output x is to be assigned to a 32 Kbyte address range with base address E0000H The address range size is 32 x 1024 215 and n 20 15 5 To set up the registers write the 12 most significant bits of E0000H to BASE19 8 the ADDRCOM reg ister and set the 5 most significant bits of MASK19 8 in the ADDRMSKx register ADDRCOMx 0E00H ADDRMSKx OF80H 13 9 8XC196NP 80 196 USER S MANUAL intel Note that the 32 Kbyte address ran
424. requency equals 25 MHZ the desired period of the output waveform is either 20 48 us 512 state times if the divide by two prescaler is disabled or 40 96 us 1 024 state times if the prescaler is enabled If PVMx CONTROL equals 8AH 138 decimal the pulsewidth is held high for 11 04 us and low for 9 44 us of the total 20 48 us pe riod resulting in a duty cycle of approximately 5496 If the prescaler is enabled the same values would produce a period of 40 96 us with the pulsewidth being held high for 22 08 us and low for 18 88 us for the same duty cycle approximately 54 9 5 2 Enabling the PWM Outputs Each PWM output is multiplexed with a port pin so you must configure it as a special function output signal before using the PWM function To do so follow this sequence 1 Clear the corresponding bit of P4_DIR see Table 9 5 2 Set the corresponding bit of P4_MODE see Table 9 5 3 Set or clear the corresponding bit of P4_REG see Table 9 5 Table 9 5 shows the alternate port function along with the register setting that selects the PWM output instead of the port function Table 9 5 PWM Output Alternate Functions PWM Output Alternate Port Function PWM Output Enabled When PWMO P4 0 P4 DIR 0 0 PA MODE 0 1 PA REG X PWM1 P4 1 P4 DIR 1 0 PA MODE 1 1 P4_REG X 2 P4 2 P4 DIR2 0 PA MODE2 1 PA REG X 9 5 3 Generating Analog Outputs The PWM modules can generate a rectang
425. ressing port and chip select unit enable these microcontrollers to handle larger more complex programs and to access more external memory at a faster rate than could earlier MCS 96 microcontrollers The 8XC196NP and 80C196NU are pin compatible and have identical cores However the 80C196NU can operate at twice the frequency of the 83XC196NP The 80C196NU also employs an accumulator and enhanced multiplication instructions to support multiply accumulate opera tions The 80C196NU is the first MCS 96 microcontroller with this capability This chapter pro vides a high level overview of the architecture 2 1 TYPICAL APPLICATIONS MCS 96 microcontrollers are typically used for high speed event control systems Commercial applications include modems motor control systems printers photocopiers air conditioner con trol systems disk drives and medical instruments Automotive customers use MCS 96 microcon trollers in engine control systems airbags suspension systems and antilock braking systems ABS 2 1 8XC196NP 80C196NU USER S MANUAL intel 2 2 DEVICE FEATURES Table 2 1 lists the features of the 8XC196NP and 80C196NU Table 2 1 Features of the 8XC196NP and 80C196NU Register Chip External Device Pins PS select Interrupt Note 2 Pins Pins 8XC196NP 100 4K 1024 64 4 1 3 6 4 80C196NU 100 0 1024 64 4 1 3 6 4 NOTES 1 Nonvolatile memory is o
426. rogramming the Captuie Comiiare Channels oa 10 6 ENABLING THE EPA 10 22 10 7 DETERMINING EVENT STATUS ern ine ere ote e deer eroe rere 10 22 10 7 1 Using Software to Service the Multiplexed Overrun Interrupts 10 23 10 8 PROGRAMMING EXAMPLES FOR EPA CHANNELS 10 24 10 8 1 EPA Compare Event Program 10 24 10 8 2 EPA Capture Event Program seem 10 25 10 8 3 EPA PWM Qutput Program 3 rere rater Ped eed 10 26 CHAPTER 11 MINIMUM HARDWARE CONSIDERATIONS 11 1 MINIMUM 5 11 1 Tidal Unused Inputs uses ie elena 11 2 11 1 2 Pin Connections casein aida nid eee 11 2 11 2 APPLYING AND REMOVING 00 11 4 11 3 NOISE PROTECTION rennen nnns 11 4 11 4 THE ON CHIP OSCILLATOR 11 5 11 5 USING AN EXTERNAL CLOCK SOURCE eee 11 7 11 6 RESETTING THE DEVICE i rere rere tae d 128 11 6 1 Generating an External Reset 2 11 9 11 6 2 Issuing the Reset RST Instruction IY 11 6 3 Issuing an Illegal IDLPD Key Operand 11 11
427. rom external memory should be tied low Ifthe CCBs are stored in external ROM chip select output 0 0 should be connected to that device Chip select output 0 is initialized for the address range 2000 20 which in cludes the CCB locations Following the CCB fetches the device fetches the instruction at FF2080H The device uses the following bus control parameters for the CCBO fetch Bus multiplexing DEMUX multiplexed Bus width BW16 8 bits Wait states WSO WS1 3 wait states The READY pin is active for the CCBO and fetches and can be used to insert additional wait states see Wait States Ready Control on page 13 26 CCBO can be fetched over a 16 bit bus even though BW16 defaults to 8 bits for the CCBO fetch upper address lines A19 8 and AD15 8 are strongly driven during the CCBO fetch because an 8 bit bus is assumed Therefore if you have a 16 bit data bus write the value 20H to FF2019H to avoid contention on AD15 8 Lines A19 0 are driven in the multiplexed mode You can access the memory using A19 0 and use AD15 0 for data only itself contains bits that specify DEMUX BW16 WSO and WS1 These values are used to control the 1 fetch and following the fetch they are stored in the chip select output 0 bus control register BUSCONO see Chip select Unit Initial Conditions on page 13 11 The bits in CCBO and 1 are described in Chip Configuration R
428. rre sponding PTSSEL bit and sets the PTSSRV bit which requests the end of PTS interrupt When the end of PTS interrupt is called hardware clears the PTSSRV bit The PTSSEL bit must be set manually to re enable the PTS channel 15 8 EXTINT3 EXTINT2 OVR2 3 OVRO 1 EPA3 EPA2 EPA1 7 0 EPAO RI TI EXTINT1 EXTINTO OVRTM1 OVRTM2 Bit Number Function 15 2 Reserved These bits are undefined 14 3 A bit is set by hardware to request an end of PTS interrupt for the corresponding interrupt 1 0 through its standard interrupt vector The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector EXTINT3 Pin FF203CH EXTINT2 EXTINT2 Pin FF203AH OVR2 3 EPA Capture Channel 2 or 3 Overrun FF2038H OVRO 11 EPA Capture Channel 0 or 1 Overrun FF2036H Capture Compare Channel 3 FF2034H EPA2 EPA Capture Compare Channel 2 FF2032H EPA1 EPA Capture Compare Channel 1 FF2030H EPAO EPA Capture Compare Channel 0 FF200EH RI SIO Receive FF200CH TI SIO Transmit FF200AH EXTINT1 FF2008H EXTINTO EXTINTO pin FF2006H OVRTM2 Timer 2 Overflow Underflow FF2002H OVRTM1 Timer 1 Overflow Underflow FF2000H PTS service is not recommended for multiplexed interrupts This bit is cleared when both corresponding interrupt pending bits are cleared in EPA_PEND Figure 6 10 PTS Service PTSSRV Register 6 6 2 Selecting the PTS Mode The second byte of each PTSCB is alw
429. rt 3 This is an 8 bit bidirectional standard 1 port Port is multiplexed as follows P3 0 CSO P3 1 CS1 P3 2 CS2 P3 3 CS3 P3 4 CS4 P3 5 CS5 P3 6 EXTINT2 and 7 P4 3 0 Vo Port 4 This is 4 bit bidirectional standard port with high current drive capability Port 4 is multiplexed as follows P4 0 PWMO P4 1 PWM 1 and P4 2 PWMe P4 3 is not multiplexed 8XC196NP 80C196NU USER S MANUAL intel Table B 3 Signal Descriptions Continued Name Type Description NU PLLEN2 1 only Phase locked Loop 1 and 2 Enable These input pins are used to enable the on chip clock multiplier feature and select either the doubled or quadrupled clock speed as follows PLLEN1 PLLEN2 Mode 0 0 standard mode clock multiplier circuitry disabled Internal clock equals the XTAL1 input frequency 1 Reserved d 0 doubled mode clock multiplier circuitry enabled Internal clock is twice the XTAL1 input frequency 1 1 quadrupled mode clock multiplier circuitry enabled Internal clock is four times the XTAL1 input frequency This reserved combination causes the device to enter an unsupported test mode PWM2 0 Pulse Width Modulator Outputs These are PWM output pins with high current drive capability The duty cycle and frequency pulse widths are programmable PWM2 0 are multiplexed with P4 2 0 RD Read Read signal output to external memory
430. rupt TI flag indicates whether a data byte has finished transmitting These flags also set the corresponding bits in the interrupt pending register A reception or transmission sets the RI or TI flag in SP STATUS and the corresponding interrupt pending bit However a soft ware write to the RI or TI flag SP STATUS has no effect on the interrupt pending bits and does not cause an interrupt Similarly reading SP STATUS clears the RI and TI flags but does not clear the corresponding interrupt pending bits The RI and TI flags in the SP STATUS and the corresponding interrupt pending bits can be set even if the RI and TI interrupts are masked The transmitter empty bit is set if SBUF_TX and its buffer are empty and ready to accept up to two bytes is cleared as soon as a byte is written to SBUF TX One byte may be written if TI alone is set By definition if TXE has just been set a transmission has completed and TI is set The received parity error RPE flag or the received bit 8 RB8 flag applies for parity enabled or disabled respectively If parity is enabled is set if a parity error is detected If parity is dis abled RBS is the ninth data bit received in modes 2 and 3 intel Pulse width Modulator intel CHAPTER 9 PULSE WIDTH MODULATOR The pulse width modulator PWM module has three output pins each of which can output a PWM signal with a fixed frequency and a variable duty cycle These outputs
431. rved 0010H Reserved Reserved 000 Reserved Reserved OOOEH 031 021 000 Reserved Reserved 000CHf 011 001 000 Reserved Reserved 000AH STATt Reserved 0008H PEND INT MASK 0008H PEND INT MASK 0006H PTSSRV H PTSSRV L 0006H PTSSRV PTSSRV L 0004H PTSSEL PTSSEL L 0004H PTSSEL PTSSEL L 0002H ONES REG ONES REG L 0002H REG H ONES REG L 0000H ZERO REG H ZERO REG L 0000H ZERO REG H ZERO REG L These SFRs are unique to the 80C196NU t Must be addressed as a word 5 12 l ntel MEMORY PARTITIONS 5 3 WINDOWING Windowing expands the amount of memory that is accessible with direct addressing Direct ad dressing can access the lower register file with short fast executing instructions With window ing direct addressing can also access the upper register file and peripheral SFRs Windowing maps a segment of higher memory the upper register file or peripheral SFRs into the lower register file The 8XC196NP has a single window selection register while the 80C196NU has two The first WSR is the same in both devices WSR selects a 32 64 or 128 byte segment of higher memory to be windowed into the top of the lower register file space The second WSRI is unique to the 80C196NU WSRI selects a 32 or 64 byte segment of high er memory to be windowed into the middle of the lower register file Figur
432. s The examples in this section assume that temporary registers are defined as shown in this segment of assembly code and described in Table 4 3 Oseg at lich AX DSW 1 BX DSW 1 Cx DSW 1 DX DSW 1 EX DSL 1 4 6 intel PROGRAMMING CONSIDERATIONS Table 4 3 Definition of Temporary Registers Temporary Register Description AX word aligned 16 bit register AH is the high byte of AX and AL is the low byte BX word aligned 16 bit register BH is the high byte of BX and BL is the low byte CX word aligned 16 bit register CH is the high byte of CX and CL is the low byte DX word aligned 16 bit register DH is the high byte of DX and DL is the low byte EX double word aligned 24 bit register 4 21 Direct Addressing Direct addressing directly accesses a location in the 256 byte lower register file without involv ing the memory controller Windowing allows you to remap other sections of memory into the lower register file for direct access see Chapter 5 Memory Partitions for details You specify the registers as operands within the instruction The register addresses must conform to the align ment rules for the operand type Depending on the instruction up to three registers can take part in a calculation The following instructions use direct addressing AX lt CX AL lt BL CL AX lt AX X BX CL c eL c ADD ADDB AL BL CL MUL INCB CL 0 4 4 2 2 Immedi
433. s 7 10 operation 7 1 7 3 overview 7 1 SFRs 7 3 Port 4 considerations 7 10 operation 7 1 7 3 7 10 overview 7 1 SFRs 7 3 Port serial See SIO port Ports general purpose I O 2 11 Index 7 8XC196NP 80C196NU USER S MANUAL Power consumption reducing 2 12 12 7 Powerdown mode 2 12 12 7 12 12 circuitry external 12 11 controlling 13 15 disabling 12 6 12 7 enabling 12 7 entering 12 6 12 7 exiting 12 8 12 11 with EXTINT 12 8 12 12 with RESET 12 8 Prefetch queue 2 5 5 23 Priority encoder 6 4 Priority instruction fetch versus data fetch 5 23 Processor status word See PSW Product information ordering 1 6 Program counter See PC Program memory 5 2 5 5 5 25 PSW 2 4 4 13 6 12 C 25 flags and instructions A 5 PTS 2 4 2 6 6 1 and EPA 6 26 6 36 block transfer mode 6 23 control block See cycle execution time 6 10 cycle defined 6 23 instructions A 59 A 67 interrupt latency 6 9 interrupt processing flow 6 2 PWM modes 6 26 6 36 PWM remap mode 6 32 PWM toggle mode 6 27 10 13 10 14 10 15 routine defined 6 1 single transfer mode 6 20 vectors memory locations 5 6 5 7 See also PWM PTSCB 6 1 6 4 6 7 6 18 6 23 memory locations 5 7 PTSSEL 6 7 6 10 6 18 PTSSRV 6 7 6 18 Pulse width modulator See PWM PUSH instruction A 3 A 34 A 51 A 55 A 62 PUSHA instruction A 2 A 35 A 52 A 55 A 62 PUSHF instruction 2 A 35 A 52 A 55 A 62 PWM 6 2
434. s specified by the count operand The count may be specified either as an immediate value in the range of 0 to 15 OFH inclusive or as the content of any register 10H OFFH with a value in the range of 0 to 31 1FH inclusive The right bits of the result are filled with zeros The last bit shifted out is saved in the carry flag Temp lt COUNT do while Temp 0 C lt High order bit of DEST DEST lt DEST x 2 Temp lt Temp 1 end while PSW Flag Settings 2 V VT ST SHL wreg count 00001001 count wreg or SHL wreg breg 00001001 breg wreg SHLB SHIFT BYTE LEFT Shifts the destination byte operand to the left as many times as specified by the count operand The count may be specified either as an immediate value in the range of 0 to 15 OFH inclusive or as the content of any register 10H OFFH with a value in the range of 0 to 31 1FH inclusive The right bits of the result are filled with zeros The last bit shifted out is saved in the carry flag Temp lt COUNT do while Temp 0 lt High order bit of DEST DEST lt DEST x 2 Temp lt Temp 1 end while PSW Flag Settings 2 V 5 11 SHLB breg count 00011001 count breg or SHLB breg breg 00011001 breg breg A 37 8 196 80C196NU USER S MANUAL intel Table A
435. s 01H and 02H Table 5 13 lists the memory address es For memory map details see Table 5 1 on page 5 4 80C196NP and 80C196NU The flash memory which implements page FFH holds the special purpose memory FF2000 FF207FH code and far constants 83C196NP only Locations FF2000 FF2FFFH which store code and special purpose memory are implemented by internal ROM Data accesses to locations FF2000 FF2FFFH are directed to the flash memory if EA is low and to internal ROM if EA t is high Locations FF2000 FF2FFFH can be remapped to page by setting the REMAP bit CCB1 2 An access to the remapped area 002000 002FFFH is directed to ROM if EA is high and to external memory if EA is low With remapping enabled REMAP 1 and high the far constants in the special purpose memory can be accessed as near constants in page 00H Page FFH 00 Pages 01 02H A16 0 A15 0 A15 0 A16 0 Flash RAM RAM 64Kx8 64Kx8 128Kx8 Code amp Data Data Data 0000 000000 010000 OOFFFFH 02FFFFH 7 0 8XC196NP NU WE A2475 02 Figure 5 10 A 64 Kbyte System with Additional Data Storage 5 29 8XC196NP 80C196NU USER S MANUAL intel Table 5 13 Memory Map for the System in Figure 5 10 Address Description FFFFFFH FF3000H External flash memory code or far constants FF2FFFH Program memory 80C196NP and 80
436. s Mode eem e 7 16 Configuration Register Settings for EPORT Pins 7 17 Serial Port Signals die cte egre inte ener gne C cbe cine del 8 2 Serial Port Control and Status 8 2 SP BAUD Values When Using the Internal Clock at 25 2 8 12 SP BAUD Values When Using the Internal Clock at 50 MHz 80C196NU Only 8 13 PWM Sigrials eite pet E depo 9 2 PWM Control and Status eene 9 3 PWM Output Frequencies 8XC196NP sese enne PWM Output Frequencies 80 196 0 9 6 PWM Output Alternate nennen eene 9 9 EPA and Timer Counter emen 10 2 EPA Control and Status Registers 10 3 Quadrature Mode Truth Table esses 10 7 Action Taken when a Valid Edge 10 11 Example Control Register Settings and EPA 10 18 Minimum Required 11 1 O Port Configuration Quide orti re e tec d i Re ntes 11 2 Operating Mode Control em eee 12 1 Operating Mode Control and Status Registers sse 12 2 80C196NU Clock MOdes
437. s Reset Value P1_PIN 1FD6H XXH P2_PIN 1FD7H XXH P3_PIN 1FDEH XXH P4 PIN 1FDFH XXH intel REGISTERS Px REG Px REG Address Table C 14 1 4 Reset State For an input set the corresponding port x data ouput Px REG register bit For an output write the data to be driven out by each pin to the corresponding bit of Px REG When a pin is configured as standard I O MODE y 0 the result of a CPU write to REG is immediately visible on the pin When a pin is configured as a special function signal Px MODE y 1 the associated on chip peripheral or off chip component controls the pin The CPU can still write to Px REG but the pin is unaffected until it is switched back to its standard function This feature allows software to configure a pin as standard clear Px MODE y initialize or overwrite the pin value then configure the pin as a special function signal set Px MODE y In this way initialization fault recovery exception handling etc can be done without changing the operation of the associated peripheral 7 0 1 3 PIN7 PING PIN5 PIN4 2 PINO 7 0 x 4 2 PINO Bit Number Bit Function Mnemonic 7 0 7 0 Port x Pin y Output To use Px y for output write the desired output data to this bit To use Px y for input set this bit Table C 14 Px REG Address
438. s a control register EPAx CON capture compare channel an event time register EPAx TIME capture compare channel and a timer input Figure 10 5 The control register selects the timer the mode and either the event to be captured or the event that is to occur The event time register holds the captured timer value in capture mode and the event time in com pare mode See Programming the Capture Compare Channels on page 10 18 for configuration information 10 8 intel EVENT PROCESSOR ARRAY EPA Timer Counter Unit TIMER1 External clocking TxCLK with up to 6 bit prescaler Quadrature clocking through TxCLK and TxDIR Clock on TIMER2 Internal clocking with up to 6 bit prescaler TIMER1 overflow EPA Capture Compare Overrun Channel x EPAx to Mode Selection t EPA1 and 3 only If enabled for EPA1 EPAO shares the EPA1 pin If enabled for 2 shares the pin A0270 02 Figure 10 5 A Single EPA Capture Compare Channel 10 4 1 Operating in Capture Mode In capture mode when a valid event occurs on the pin the value of the selected timer is captured into a buffer The timer value is then transferred from the buffer to the EPAx TIME register which sets the EPA interrupt pending bit as shown in Figure 10 6 If enabled an interrupt is gen erated If a second event occurs before the CPU reads the first timer value i
439. s and Chip Configuration Bytes on page 13 14 de scribes the CCBs and CCRs 5 2 3 Peripheral Special function Registers SFRs Locations 1F00 1FFFH provide access to the peripheral SFRs see Table 5 5 Locations in this range that are omitted from the table are reserved The peripheral SFRs are I O control registers they are physically located in the on chip peripherals Peripheral SFRs can be windowed and they can be addressed either as words or bytes except as noted in the table 5 7 8 196 80C196NU USER S MANUAL Table 5 5 Peripheral SFRs intel Reserved Locations EPORT SFRs Address High Odd Byte Low Even Byte Address High Odd Byte Low Even Byte 1FEEH Reserved Reserved THFE6H PIN Reserved 1FECH Reserved Reserved THFEAH REG Reserved 1FEAH Reserved Reserved TH FE2H DIR Reserved 1FE8H Reserved Reserved THFEOH EP MODE Reserved Ports 1 4 SFRs Serial and PWM SFRs Address High Odd Byte Low Even Byte Address High Odd Byte Low Even Byte 1FDEH PIN P3 PIN 1FBEH Reserved Reserved 1FDCH P4 REG P3 REG 1FBCH SP BAUD SP BAUD L 1FDAH P4 DIR P3 DIR 1FBAH SP CON SBUF TX 1FD8H P4 MODE P3 MODE 1FB8H SP STATUS SBUF RX 1FD6H P2 PIN P1 PIN 1FB6H Reserved CON REGO 1FD4H P2 REG P1 REG 1FB4H Reserved PWM2 CONTROL 1FD2H P
440. s and chip configuration byte reads INST is low during internal memory fetches NMI Nonmaskable Interrupt In normal operating mode a rising edge on NMI generates a nonmaskable interrupt NMI has the highest priority of all prioritized interrupts Assert NMI for greater than one state time to guarantee that it is recognized ONCE On circuit Emulation Holding ONCE high during the rising edge of RESET places the device into on circuit emulation ONCE mode This mode puts all pins into a high impedance state thereby isolating the device from other components in the system The value of ONCE is latched when the RESET pin goes inactive While the device is in ONCE mode you can debug the system using a clip on emulator To exit ONCE mode reset the device by pulling the RESET signal low To prevent accidental entry into ONCE mode connect the ONCE pin to Vas P1 7 0 Vo Port 1 This is a standard bidirectional port that is multiplexed with individually selectable special function signals Port 1 is multiplexed as follows P1 0 EPAO P1 1 EPA1 P1 2 EPA2 1 P1 4 T1CLK P1 5 T1DIR P1 6 T2CLK and P1 7 T2DIR P2 7 0 Vo Port 2 This is a standard bidirectional port that is multiplexed with individually selectable special function signals Port 2 is multiplexed as follows P2 0 TXD P2 1 RXD P2 2 EXTINTO P2 3 BREQ P2 4 EXTINT1 P2 5 HOLD P2 6 HLDA and P2 7 CLKOUT P3 7 0 Vo Po
441. s asserted the 8XC196Nx continues executing code until it needs to access the external bus If executing from internal memory it continues until it needs to perform an external memory cycle If executing from external memory it continues executing until the queue is emp ty or until it needs to perform an external data cycle As soon as it needs to access the external bus the 8XC196Nx asserts BREQ and waits for the external device to deassert HOLD After asserting BREQ the 8XC196Nx cannot respond to any interrupt requests including NMI until the external device deasserts HOLD One state time after HOLD goes high the 8XC196Nx deasserts HLDA and with no delay resumes control of the bus If the 8XC196Nx is reset while in hold bus contention can occur For example a CPU only de vice would try to fetch the chip configuration byte from external memory after was brought high Bus contention would occur because both the external device and the 8XC196Nx would attempt to access memory One solution is to use the RESET signal as the system reset then all bus masters including the 8XC196Nx are reset at once Chapter 11 Minimum Hard ware Considerations shows system reset circuit examples 13 8 WRITE CONTROL MODES The device has two write control modes the standard mode which uses the WR and BHE sig nals and the write strobe mode which uses the WRL and WRH signals Otherwise the two modes are identical The modes are
442. s set to indicate that the result of an operation is negative The flag is correct even if an overflow occurs For all shift operations and the NORML instruction the flag is set to equal the most significant bit of the result even if the shift count is zero ST The sticky bit flag is set to indicate that during a right shift a 1 has been shifted into the carry flag and then shifted out This bit is undefined after a multiply operation The sticky bit flag can be used with the carry flag to allow finer resolution in rounding decisions See the description of the carry C flag for details V The overflow flag is set to indicate that the result of an operation is too large to be represented correctly in the available space For shift operations the flag is set if the most significant bit of the operand changes during the shift For divide operations the quotient is stored in the low order half of the destination operand and the remainder is stored in the high order half The overflow flag is set if the quotient is outside the range for the low order half of the destination operand Chapter 4 Programming Considerations defines the operands and possible values for each Instruction Quotient Stored in V Flag Set if Quotient is DIVB Short Integer lt 128 or gt 127 lt 81H or gt 7FH DIV Integer lt 32768 or gt 32767 lt 8001H or gt 7FFFH DIVUB Byte 255 FFH DIVU Word 65535 FFFFH VT The overflo
443. s the AC timing specifications that the memory system must meet and those that the device will provide Table 13 16 AC Timing Definitions Symbol Definition The External Memory System Must Meet These Specifications Address Valid to Input Data Valid Maximum time the memory device has to output valid data after the device outputs a valid address Toupy CLKOUT High to Input Data Valid Maximum time the memory system has to output valid data after CLKOUT rises CLKOUT Low to Input Data Valid Maximum time the memory system has to output valid data after CLKOUT falls Data Valid to WR High Time between data being valid on the bus and WR going inactive Tnupz RD High to Input Data Float Time after RD is inactive until the memory system must float the bus If this timing is not met bus contention will occur RD Low Input Data Valid Maximum time the memory system has to output valid data after the device asserts RD CS x Valid Input Data Valid Maximum time the memory device has to output valid data after the device outputs a valid chip select output 18 42 INTERFACING WITH EXTERNAL MEMORY Table 13 16 AC Timing Definitions Continued Definition The 8XC196Nx Meets These Specifications Operating frequency Frequency of the signal input on the XTAL1 pin times the clock multiplier x For the 8XC196NP xis always 1 for the 80C196
444. s the transmit interrupt clearing the bit disables masks the interrupt Setting the RI bit enables the receive interrupt clearing the bit disables masks the interrupt INT_PEND 0012H Interrupt Pending When set the TI bit indicates a pending transmit interrupt When set the RI bit indicates a pending receive interrupt P1 DIR 1FD2H Port 1 Direction This register selects the direction of each port 1 pin To use as the input clock to the baud rate generator clear P1 DIR 4 P1 MODE 1FDOH Port 1 Mode This register selects either the general purpose input output function or the peripheral function for each pin of port 1 To use T1CLK as the clock source for the baud rate generator set MODE 4 to configure T1CLK P1 4 for the SIO port intel SERIAL SIO PORT Table 8 2 Serial Port Control and Status Registers Continued Mnemonic Address Description P1 PIN 1FD6H Port 1 Pin State If you are using T1CLK P1 4 as the clock source for the baud rate generator you can read P1 PIN 4 to determine the current value of T1CLK P1 REG 1FD4H Port 1 Output Data To use T1CLK as the clock source for the baud rate generator set P1_REG 4 P2_DIR 1FCBH Port 2 Direction This register selects the direction of each port 2 pin Clear P2_DIR 1 to configure RXD P2 1 as a high impedance input open drain output and set P2_DIR 0 to configure TXD P2 0 as a comple mentary out
445. se 13 2 13 3 THE GHIP SELEGT ien pe p e Ces 13 5 13 3 1 Defining Chip select Address Ranges seem 13 7 13 3 2 Controlling Wait States Bus Width and Bus Multiplexing 13 10 13 3 3 Chip select Unit Initial Conditions emm 13 11 13 3 4 Initializing the Chip select Registers seed 1 13 3 5 Example of a Chip select Setup 2 13 12 13 4 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES ness 13 14 13 5 BUS WIDTH AND 12113 18 13 5 1 A 16 bit Example System 13 21 13 5 2 gt 16 bit Bus TIMINGS uer eee ERR 13 22 13 5 3 8 bit BUS TIMINGS iint eer terre dae E edd e 13 24 13 5 4 Comparison of Multiplexed and Demultiplexed Buses 13 26 13 66 WAIT STATES READY 13 26 19 7 BUS HOED PROTOCOL 4 Rd ERR 13 30 13 7 1 Enabling the Bus hold Protocol 2 eem 13 32 13 7 2 Disabling the Bus hold 13 32 13 7 3 Hold Eatenoy 13 32 13 7 4 Regaining Bus 13 33 13 8 WRITE CONTROL 2 004404 1 2 0000 entente enne eren nnne nint 13 33 13 9 SYSTEM BUS TIMING
446. selection register WSR1 Unlike the 80C196NP the 80C196NU s EPORT special function registers are located in SFR address space rather than in memory mapped space so they can be windowed for direct access The 80C196NU has an 8 byte prefetch queue while the 80C196NP has a 4 byte prefetch queue In the 80C196NU data accesses have a higher priority than instruction queue fetches In the 80C 196NP the opposite is true instruction fetches have the highest priority The 80C196NU s serial I O port has a divide by 2 prescaler controlled by the SP CON register The 80C196NU s EPA has an additional prescaler option divide by 128 controlled by the timer control register Tx CONTROL 2 13 8XC 2 14 196NP 80C196NU USER S MANUAL intel The 80C196NU s PWM has an additional prescaler option divide by 4 controlled by the PWM control register CON REGO When operating with a demultiplexed bus the 80C196NU can add an automatic delay in the first cycle following a chip select change or in a write cycle that follows a read This mode called deferred mode extends the following timing specifications by two clock periods 2t Taare Ting Toug The 80C196NU has an additional power saving mode standby IDLPD 3 The 8XC196NP allows you to change the value of EP REG to control which memory page a nonextended instruction accesses However softwa
447. sing In general assemblers require a zero preceding an alphabetic hexadecimal character and an H following any hexadecimal value so FFFFFFH must be written as OFFFFFFH ANSI compilers require a zero plus an preceding a hexadecimal value so FFFFFFH must be written as Consult the manual for your assembler or compiler to determine its specific requirements The terms assert and deassert refer to the act of making a signal active enabled and inactive disabled respectively The active polarity low or high is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To assert is to drive it low to assert ALE is to drive it high to deassert RD is to drive it high to deassert ALE is to drive it low The terms clear and set refer to the value of a bit or the act of giving it a value If a bit is clear its value is 0 clearing a bit gives it a 0 value If a bit is set its value is 1 setting a bit gives it a 1 value Lowercase f represents the internal operating frequency See Internal Timing on page 2 7 for details Instruction mnemonics are shown in upper case to avoid confusion In general you may use either upper case or lower case when programming Consult the manual for your assembler or compiler to determine its specific requirements 1 3 8XC196NP 80C196NU USER S MANUAL intel italics
448. sion Z N C V VI ST 0 v SHRB LOGICAL RIGHT SHIFT BYTE Shifts the destination byte operand to the right as many SHRB breg count times as specified by the count operand The j count may be specified either as an 00011000 count breg immediate value in the range of 0 to 15 or inclusive or as the content of any SHRB breg breg 00011000 breg breg NOTES This instruction clears the Sticky bit flag at the beginning of the instruction If at any time during the shift a 1 is shifted into the carry flag and another shift cycle occurs the instruc tion sets the sticky bit flag In this operation DEST 2 rep resents unsigned division A 40 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format SHRL LOGICAL RIGHT SHIFT DOUBLE WORD Shifts the destination double word operand to SHRL Ireg count the right as many times as specified by the count operand The count may be specified 00001100 count Ireg either as an immediate value in the range of 0 or to 15 OFH inclusive or as the content of SHRL Ireg breg any register 10H OFFH with a value in the range of 0 to 31 1FH inclusive The left bits 00001100 breg Ireg of the result are filled with zeros The last bit shifted out is saved in the carry flag NOTES This instruction
449. sion the system asks you to register with the system operator by entering your name and location The system operator will set up your access account within 24 hours At that time you can access the files on the BBS NOTE If you encounter any difficulty accessing the high speed modem try the dedicated 2400 baud modem Use these modem settings 2400 N 8 1 8XC196NP 80C196NU USER S MANUAL intel 1 4 2 1 How to Find MCS 96 Microcontroller Files on the BBS Application notes utilities and product literature are available from the BBS To access the files complete these steps 1 EnterF from the BBS Main menu The BBS displays the Intel Apps Files menu 2 L and press Enter The BBS displays the list of areas and prompts for the area number 3 12 and press Enter to select MCS 96 Family The BBS displays a list of subject areas including general and product specific subjects 4 the number that corresponds to the subject of interest and press Enter to list the latest files 5 the file numbers to select the files you wish to download for example 1 6 for files 1 and 6 or 3 7 for files 3 4 5 6 and 7 and press Enter The BBS displays the approx imate time required to download the files you have selected and gives you the option to download them 1 4 2 2 How to Find ApBUILDER Software and Hypertext Documents on the BBS The latest ApBUILDER files and hypertext manuals and
450. space NOTE Internally there 24 address bits however only 20 address lines A19 0 are bonded out The internal address space is 16 Mbytes 000000 FFFFFFH and the external address space is 1 Mbyte 00000 The device resets to FF2080H in internal ROM or F2080H in external memory EPORT 3 0 AD15 0 yo Address Data Lines The function of these pins depend on the bus size and mode When bus access is not occurring these pins revert to their I O port function 16 bit Multiplexed Bus Mode AD15 0 drive address bits 0 15 during the first half of the bus cycle and drive or receive data during the second half of the bus cycle 8 bit Multiplexed Bus Mode AD15 8 drive address bits 8 15 during the entire bus cycle AD7 0 drive address bits 0 7 during the first half of the bus cycle and either drive or receive data during the second half of the bus cycle 16 bit Demultiplexed Mode AD15 0 drive or receive data during the entire bus cycle 8 bit Demultiplexed Mode AD7 0 drive or receive data during the entire bus cycle AD15 8 drive the data that is currently on the high byte of the internal bus 13 2 INTERFACING WITH EXTERNAL MEMORY Table 13 2 External Memory Interface Signals Continued Name Type Description Multiplexed With ALE Address Latch Enable This active high output signal is asserted only during external memory cycles ALE signals the
451. ssed as components of BYTEs or WORDs It does not support the direct addressing of BITs 4 1 2 BYTE Operands A BYTE is an unsigned 8 bit variable that can take on values from 0 through 255 28 1 Arith metic and relational operators can be applied to BYTE operands but the result must be interpret ed in modulo 256 arithmetic Logical operations on BYTEs are applied bitwise Bits within BYTEs are labeled from 0 to 7 bit 0 is the least significant bit There are no alignment restric tions for BYTEs so they may be placed anywhere in the address space 4 1 SHORT INTEGER Operands SHORT INTEGER is 8 bit signed variable that can take on values from 128 27 through 127 427 1 Arithmetic operations that generate results outside the range of a SHORT INTE GER set the overflow flags in the processor status word PSW The numeric result is the same as the result of the equivalent operation on BYTE variables There are no alignment restrictions SHORT INTEGERs so they may be placed anywhere in the address space 4 2 intel PROGRAMMING CONSIDERATIONS 41 4 WORD Operands A WORD is an unsigned 16 bit variable that can take on values from 0 through 65 535 216 1 Arithmetic and relational operators can be applied to WORD operands but the result must be in terpreted in modulo 65536 arithmetic Logical operations on WORDS are applied bitwise Bits within are labeled from 0 to 15 bit 0 is the least significant b
452. sses to the next sequential instruction If the result is not 0 the instruction adds to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in the range of 1 28 to 127 COUNT lt COUNT 1 if COUNT 0 then PC lt PC 8 bit disp end if PSW Flag Settings Z N C V VT ST DJNZW wreg cadd 11100001 wreg disp NOTE The displacement disp is sign extended to 24 bits DPTS DISABLE PERIPHERAL TRANSACTION SERVER PTS Disables the peripheral transaction server PTS PTS Disable PSW 2 0 PSW Flag Settings Z N C V VT ST DPTS 11101100 8 196 80C196NU USER S MANUAL intel Table A 6 Instruction Set Continued EBR shares its opcode E3 with the BR instruction To differentiate between the two the compiler sets the least significant bit of the EBR instruction For example EBR 50 becomes E351 when compiled PC lt DEST PSW Flag Settings Z N C V VT ST Mnemonic Operation Instruction Format EBMOVI EXTENDED INTERRUPTABLE BLOCK PTRS CNTREG MOVE Moves a block of word data from one EBMOVI prt2_reg wreg memory location to another This instruction allows you to move blocks of up to 64K words 11100100 wreg
453. start of an external bus cycle and indicates that valid address information is available on the system address data bus A19 16 and AD15 0 for a multiplexed bus A19 0 for a demultiplexed bus ALE differs from ADV in that it does not remain active during the entire bus cycle An external latch can use this signal to demultiplex address bits 0 15 from the address data bus in multiplexed mode Byte High Enable During 16 bit bus cycles this active low output signal is asserted for word reads and writes and high byte reads and writes to external memory indicates that valid data is being transferred over the upper half of the system data bus Use BHE in conjunction with AO to determine which memory byte is being transferred over the System bus 0 0 0 0 1 high byte only 1 0 low byte only The chip configuration register 0 CCRO determines whether this pin functions as or WRH CCRO 2 1 selects BHE CCRO 2 0 selects WRH Byte s Accessed both bytes P5 5 WRH BREQ Bus Request This active low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle The device can assert BREQ at the same time as or after it asserts HLDA Once it is asserted BREQ remains asserted until HOLD is removed You must enable the bus hold protocol before using this signal see Enabling the Bus hold Protocol on page 13 32 P2 3
454. stem components This chapter describes each mode and explains how to enter and exit each Refer to Appendix A for descriptions of the instructions discussed in this chapter to Appendix B for descriptions of signal status during each mode and to Appendix C for details about the registers 12 4 SPECIAL OPERATING MODE SIGNALS AND REGISTERS Table 12 1 lists the signals and Table 12 2 lists the registers that are mentioned in this chapter Table 12 1 Operating Mode Control Signals Signal Port Pin Name Type Description P2 7 CLKOUT Clock Output Output of the internal clock generator The CLKOUT frequency is 1 2 the internal operating frequency f CLKOUT has a 50 duty cycle CLKOUT is multiplexed with P2 7 P3 7 External Interrupts P3 6 2 In normal operating mode a rising edge on sets the 52 Eine EXTINTx interrupt pending bit EXTINTx is sampled during phase 2 CLKOUT high The minimum high time is one state time In standby and powerdown modes asserting the EXTINTx signal for at least 50 ns causes the device to resume normal operation The interrupt need not be enabled but the pin must be configured as a special function input see Bidirectional Port Pin Configurations on page 7 7 If the EXTINTx interrupt is enabled the CPU executes the interrupt service routine Otherwise the CPU executes the instruction that immediately follows the command that invoked the
455. stem s worst case interrupt latency and worst case interrupt service ex ecution time and then add them together The worst case interrupt latency is the total latency of all the interrupts both normal and PTS used in your system The worst case interrupt service execution time is the total execution time of all interrupt service routines and PTS cycles Assume a system with a single EPA channel a single enabled interrupt and PTS service Also assume that the PTS is initialized and that the duty cycle and frequency are fixed The worst case interrupt latency for a single interrupt system with PTS service is 43 state times see PTS Inter rupt Latency on page 6 9 The PTS cycle execution time in PWM toggle mode is 15 state times Table 6 4 on page 6 10 Therefore a single capture compare channel can be updated every 58 state times 43 15 Each PWM period requires two updates one setting and one clearing so the execution time for a PWM period equals 116 state times When the input frequency on XTALI is 25 MHz and the phase locked loop is disabled on the 80C196NU the PWM period is 9 27 us and the maximum PWM frequency is 107 8 KHz 10 4 2 3 Generating a High speed PWM Output You can generate a high speed pulse width modulated output with a pair of EPA channels and the PTS set up in PWM remap mode PWM Remap Mode Example on page 6 32 describes how to configure the EPA and PTS The remap bit bit 8 must be set in to p
456. stination addresses are calculated using the indirect with autoin crement addressing mode A long register PTRS addresses the source and destination pointers which are stored in adjacent word registers The source pointer SRCPTR is the low word and the destination pointer DSTPTR is the high word of PTRS A word register CNTREG specifies the number of transfers The blocks of data can be located anywhere in page 00H of register RAM but should not overlap Because the source SRCPTR and destination DSTPTR pointers are 16 bits wide this instruction uses nonextended data moves It cannot operate across page boundaries For example SRCPTR cannot point to a location on page 05 while DSTPTR points to page 00 SRCPTR and DSTPTR will operate from the page defined by REG EP REG should be set to 00H to select page 00H see Accessing Data on page 5 23 The 80C196NU forces REG to 00H COUNT lt CNTREG LOOP SRCPTR PTRS DSTPTR lt PTRS 2 DSTPTR lt SRCPTR PTRS lt SRCPTR 2 PTRS 2 DSTPTR 2 COUNT lt COUNT 1 if COUNT 0 then go to LOOP PSW Flag Settings 7 VT ST PTRS CNTREG BMOV wreg 11000001 wreg Ireg NOTE The pointers are autoincre mented during this instruction However CNTREG is not decre mented Therefore it is easy to unintentionally create a long uninterruptible operation with the BMOV
457. struction 2 5 26 A 51 58 66 JST instruction A 3 5 A 26 A 51 A 58 66 Jump instructions A 64 conditional A 5 A 58 A 66 unconditional A 57 JV instruction A 3 5 A 26 A 51 A 58 A 66 JVT instruction A 3 A 5 A 27 A 51 A 58 A 66 L Latency See bus hold protocol interrupts LCALL instruction A 3 A 27 A 52 A 57 A 65 LD instruction A 2 A 27 A 50 A 56 A 63 LDB instruction A 2 A 28 A 50 A 56 A 63 LDBSE instruction A 3 A 28 A 50 A 56 A 63 LDBZE instruction A 3 A 28 A 50 A 56 A 63 Level sensitive input B 6 Literature 1 11 LJMP instruction 2 A 28 A 52 A 57 A 64 Logical instructions A 54 A 61 LONG INTEGER defined 4 4 Lookup tables software protection 4 14 Manual contents summary 1 1 Manuals online 1 10 Math features 3 1 3 6 Measurements defined 1 5 Memory bus 2 5 Memory configuration examples 5 27 5 32 Memory controller 2 3 2 5 Memory map 5 3 Example of 1 Mbyte mode 5 32 Example of 64 Kbyte mode 5 28 5 30 Memory external 13 1 13 45 interface signals 13 2 Memory reserved 5 6 5 7 Microcode engine 2 3 Index 6 Miller effect 11 7 Mode 0 SIO 8 4 8 5 Mode 1 SIO 8 5 8 6 Mode 2 SIO 8 5 8 7 8 8 Mode 3 SIO 8 5 8 7 8 8 MODE64 bit 5 23 MUL instruction 3 1 A 29 52 54 A 61 MULB instruction A 29 A 30 A 52 A 54 A 61 Multiplication instructions multiply accumulate example code 3
458. t is set when the last data bit is sampled Reading SP STATUS clears this bit This bit need not be clear for the serial port to receive data 5 TI Transmit Interrupt This bit is set at the beginning of the stop bit transmission Reading SP STATUS clears this bit 4 FE Framing Error This bit is set if a stop bitis not found within the appropriate period of time Reading SP STATUS clears this bit 3 TXE SBUF TX Empty This bit is set if the transmit buffer is empty and ready to accept up to two bytes It is cleared when a byte is written to SBUF TX 2 OE Overrun Error This bit is set if data in the receive shift register is loaded into SBUF RX before the previous bit is read Reading STATUS clears this bit 1 0 Reserved These bits are undefined Figure 8 8 Serial Port Status SP STATUS Register The receiver checks for a valid stop bit Unless a stop bit is found within the appropriate time the framing error FE bit in the SP STATUS register is set When the stop bit is detected the data in the receive shift register is loaded into SBUF and the receive interrupt RI flag is set If this happens before the previous byte in SBUF_RX is read the overrun error OE bit is set SBUF RX always contains the latest byte received itis never a combination of the last two bytes intel SERIAL 1 0 SIO PORT The receive interrupt RI flag indicates whether an incoming data byte has been received The transmit inter
459. t tools catalog Systems catalog Multimedia catalog Multibus and iRMX software catalog and BBS file listings Microprocessor PCI and peripheral catalog Quality and reliability and change notification catalog oe er nw PF we Im iAL Intel Architecture Labs technology catalog 1 4 2 Bulletin Board System BBS The bulletin board system BBS lets you download files to your computer The application BBS has the latest ApBUILDER software hypertext manuals and datasheets software drivers firm ware upgrades application notes and utilities and quality and reliability data 916 356 3600 U S Canada Japan Asia Pacific up to 19 2 Kbaud 916 356 7209 U S Canada Japan Asia Pacific 2400 baud only 44 0 1793 496340 Europe The toll free BBS available in the U S and Canada offers lists of documents available from FaxBack a master list of files available from the application BBS and a BBS user s guide The BBS file listing is also available from FaxBack catalog number 6 see page 1 8 for phone num bers and a description of the FaxBack service 1 800 897 2536 U S and Canada only Any customer with a modem and computer can access the BBS The system provides automatic configuration support for 1200 through 19200 baud modems Typical modem settings are 14400 baud no parity 8 data bits and 1 stop bit 14400 N 8 1 To access the BBS just dial the telephone number and respond to the system prompts During your first ses
460. te a PWM waveform using PWM toggle mode EPAO complete the following procedure This example uses the values stored in CSTOREI and CSTORE2 to control the frequency and duty cycle of a PWM 1 Disable the interrupts and the PTS The DI instruction disables all standard interrupts the DPTS instruction disables the PTS 2 Store the on time value T1 in CSTOREI 3 Store the off time value T2 T1 in CSTORE2 4 Setupthe PTSCB as shown in Table 6 8 Load PTSCON with 43H selects PWM toggle mode initial TBIT value 1 Set up PTSPTRI to point to EPAO TIME the EPAO event time register Load PTSCONSTI with the on time value from CSTOREI Load PTSCONST with the off time value T2 from CSTORE2 6 27 8XC196NP 80C196NU USER S MANUAL intel Table 6 8 PWM Toggle Mode PTSCB PTSCONST HI T T1 HI PTSCONST LO T T1 LO PTSCONST1 HI T1 HI PTSCONST1 LO T1 LO HI 1FH PTSPTR1 LO 82H PTSCON 43H Mode 010 TMOD 1 TBIT 1 Unused Configure 1 0 to serve as the EPAO output Clear P1_DIR 0 selects output Set MODE O selects the EPAO special function signal Set P1 REG O0 initializes the output to 1 Set up EPAO Load 0 CON with 0078H timer 1 compare toggle output pin re enable Load EPAO TIME with the value in PISCONST1 selects as first event time
461. te times for external stack usage or 71 state times for internal stack usage Therefore a single capture compare channel 0 3 can be updated every 125 state times assuming internal stack usage 54 71 Each PWM period requires two updates one setting and one clearing so the execution time for a PWM pe riod equals 250 state times When the input frequency on XTAL 1 is 25 MHz and the phase locked loop is disabled on the 80C196NU the PWM period is 20 us and the maximum PWM frequency is 50 kHz 10 4 2 2 Generating a Medium speed PWM Output You can generate a medium speed pulse width modulated output with a single EPA channel and the PTS set up in PWM toggle mode PWM Toggle Mode Example on page 6 27 describes how to configure the EPA and PTS Once started this method requires no CPU intervention unless you need to change the output frequency The method uses a single timer counter The timer counter is not interrupted during this process so other EPA channels can also use it if they do not reset it 10 13 8XC196NP 80C196NU USER S MANUAL intel The maximum output frequency depends upon the total interrupt latency and interrupt service ex ecution time As additional EPA channels and the other functions of the microcontroller are used the maximum PWM frequency decreases because the total interrupt latency and interrupt service execution time increases To determine the maximum medium speed PWM frequency in your system calculate your sy
462. te to DIR to establish the individual pins as either inputs or outputs Outputs will drive the data that you specify in step 3 For a complementary output clear its Px DIR bit For a high impedance input or an open drain output set its Px DIR bit Open drain outputs require external pull ups 2 Write to Px MODE to select either I O or special function mode Writing to MODE regardless of the value written turns off the weak pull ups Even if the entire port is to be used as I O its default configuration after reset you must write to Pc MODE to ensure that the weak pull ups are turned off For a standard I O pin clear its Px MODE bit In this mode the pin is driven as defined in steps 1 and 3 For a special function signal set its Px MODE bit In this mode the associated peripheral controls the pin 3 Write to Px REG For output pins defined in step 1 write the data that is to be driven by the pins to the corresponding Px REG bits For special function outputs the value is immaterial because the peripheral controls the pin However you must still write to Px REG to initialize the pin For input pins defined in step 1 set the corresponding Px REG bits Table 7 6 lists the control register values for each possible configuration For special function outputs the Px REG value is irrelevant don t care because the associated peripheral controls the pin in special function mode However y
463. ter the offset between the end of this instruction NOTE The displacement disp is sign and the target label effecting the jump The extended to 24 bits offset must be in the range of 128 to 127 if N 2 1 ORZ 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST A 23 8XC196NP 80C196NU USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format JLT JUMP IF SIGNED LESS THAN Tests the negative flag If the flag is clear control JLT cadd passes to the next sequential instruction If the negative flag is set this instruction adds 11011110 disp to the program counter the offset between the end of this instruction and the target label NOTE The displacement disp is sign effecting the jump The offset must be in the extended to 24 bits range of 128 to 127 if N 2 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JNC JUMP IF CARRY FLAG IS CLEAR Tests the carry flag If the flag is set control passes JNC cadd the next sequential instruction If the carry flag is clear this instruction adds to the 11010011 disp program counter the offset between the end of this instruction and the target label NOTE The displacement disp is sign effecting the jump The offset must be in the extended to 24 bits range of 128 to 127
464. ter file and the special function regis ters SFRs while page FFH contains special purpose memory chip configuration bytes and in terrupt vectors and program memory The device fetches its first instruction from location FF2080H Addresses in page FFH exist only in the internal 24 bit address space The implementation of page FFH in the 83C196NP differs from that in the 80C196NP and 80C196NU For the 83C196NP locations FF2000 FF2FFFH are implemented by 4 Kbytes of in ternal ROM and the remainder of page 000 is implemented by external memory in page OFH For the 80C196NP and the 80C196NU which have no internal ROM all of page FFH is implemented by external memory in page OFH NOTE Because the device has 24 bits of address internally all programs must be written as though the device uses all 24 bits The device resets from page FFH so all code must originate from this page Use the assembler directive cseg at OFExxxxH This is true even if the code is actually stored in external memory 5 2 l ntel MEMORY PARTITIONS Page FFH Page 00H FFFFFFH OOFFFFH External Memory External Memory FF3000H _ Cid _ ___ 003000H FF2FFFH 002FFFH Program Memory 80C196NP NU 80C196NP NU External External Memory 83C196NP ROM 83C196NP FF2080H External Memory if FF207FH 1 2 0 Special Purpose Memory A Copy of 80C196NP NU External Page FFH if 83C196NP ROM CCB1 2 1 FF2000H 10 002000H FF1FF
465. ternal device memory or I O connected to address data 002000 bus Note 3 Indirect indexed extended 001FFF 001F00 Indirect indexed extended Peripheral SFRs Note 4 Windowed direct 001EFF External device memory or I O connected to address data 001C00 bus future SFR expansion Note 5 Indirect indexed extended 001 External device memory or I O connected to address data 000400 bus Indirect indexed extended 0003FF Upper register file register RAM Indirect indexed 000100 windowed direct 0000FF 000000 Lower register file register RAM stack pointer CPU SFRs Direct indirect indexed NOTES 1 For the 80C196NP and 80C196NU the program and special purpose memory locations FF2000 FF2FFFH reside in external memory For the 83C196NP these locations can reside either in exter nal memory or in internal ROM Do not use these locations except to initialize them Except as otherwise noted initialize unused program memory locations and reserved memory locations to FFH For the 80C196NP and 80C196NU locations 002000 002FFFH reside in external memory For the 83C196NP locations 002000 002 can be external memory CCB1 2 0 or a copy of program and special purpose memory stored in the internal ROM CCB1 2 1 For the 8XC196NP locations 1FEO 1FFFH contain memory mapped SFRs They must be accessed with indirect indexed or extended ad
466. tes the instruction that follows the IDLPD 1 instruction NOTE To prevent an accidental return to full power hold the external interrupt pins low while the device is in idle mode 12 4 STANDBY MODE 80C196NU ONLY In standby mode the device s power consumption decreases to approximately 1096 of normal consumption Internal logic holds the CPU and peripheral clocks at logic zero which causes the CPU to stop executing instructions the system bus control signals to become inactive and the peripherals to turn off The phase locked loop PLL circuitry and the on chip oscillator continue to operate Table B 5 on page 13 lists the values of the pins during standby mode 12 4 4 Enabling and Disabling Standby Mode Setting the PD bit in the chip configuration register 0 CCRO 0 enables both standby and pow erdown modes Clearing it disables both modes CCRO is loaded from the chip configuration byte CCBO when the device is reset 12 4 2 Entering Standby Mode Before entering standby mode complete the following tasks Complete all serial port transmissions or receptions Otherwise when the device exits standby the serial port activity will continue where it left off and incorrect data may be transmitted or received Putall other peripherals into an inactive state After completing these tasks execute the IDLPD 3 instruction to enter standby mode NOTE To prevent an accidental return to full power hold
467. the external capacitor C to begin dis charging at a typical rate of 200 LA When the RPD pin voltage drops below the threshold voltage about 2 5 V for 5 V operation and 1 6 V for 3 V operation the internal phase clocks are enabled and the device resumes code execution At this time a Schmitt triggered detection circuit prompted by the switching voltage levels strongly drives a logic one quickly pulling the RPD pin back up to Vcc see recovery time in Fig ure 12 5 The time constant RC follows an exponential charging curve However since there is no external resistor on the RPD pin the time constant goes to zero and the recovery time is instantaneous t t lt 1 1 0 where Vo Charging capacitor voltage 12 5 3 3 Selecting C With the resistance of the discharge path designed into the silicon via the internal pull down the selection of an external capacitor C can be critical Ideally you want to select a component that will produce a sufficient discharge time to permit the internal oscillator circuitry to stabilize Be cause many factors can influence the discharge time requirement you should always fully char acterize your design under worst case conditions to verify proper operation 12 10 lel SPECIAL OPERATING MODES A 3 RPD Volts 2 Discharge Code Execution Resumes 2 4 6 8 10 12 14 16 18 20 22 Time ms Voc 5V
468. the external memory interface include ready control for inserting additional wait states a bus hold protocol that enables external devices to take con trol of the bus and two write control modes for writing words and bytes to memory These fea tures provide a great deal of flexibility when interfacing with external memory devices In addition to describing the signals and registers related to external memory this chapter discuss es the process of fetching the chip configuration bytes and configuring the external bus It also provides examples of external memory configurations and chip select setup 13 1 INTERNAL AND EXTERNAL ADDRESSES The address that external devices see is different from the address that the device generates inter nally Internally the device has 24 address lines but only the lower 20 address lines A19 0 are implemented with external pins The absence of the upper four address bits at the external pins causes different internal addresses to have the same external address For example the internal addresses FF2080H 7F2080H and 0 2080 all appear at the 20 external pins as F2080H The upper nibble of the internal address has no effect on the external address The address seen by an external device also depends on the number of address lines that the ex ternal system uses If the address on the external pins A19 0 is F2080H and only A17 0 are con nected to the external device the external device sees 32080H The up
469. the reset state Holding the ONCE signal high during the rising edge of causes the device to enter ONCE mode The ONCE signal is latched when RESET goes inactive Internally the ONCE pin is tied to a medium strength pull down To prevent accidental entry into ONCE mode connect the ONCE pin to Vss Exit ONCE mode by asserting the RESET signal Normal operations resume when RESET goes high 12 7 RESERVED TEST MODES 80C196NU ONLY For the 80C196NU only holding PLLENI low while PLLEN2 is held high causes the device to enter an unsupported test mode Table 12 3 shows the proper PLLEN1 PLLEN2 connections for valid clock modes 12 12 intel SPECIAL OPERATING MODES Table 12 3 80C196NU Clock Modes PLLEN2 PLLEN1 Mode 0 0 Clock multiplier circuitry disabled 0 1 Reserved CAUTION This combination causes the device to enter an unsupported test mode 1 0 Doubled clock doubling circuitry enabled Internal clock is twice the XTAL1 input Quadrupled clock quadrupling circuitry enabled Internal clock is four times the XTAL1 input 12 13 intel 13 Interfacing with External Memory intel CHAPTER 13 INTERFACING WITH EXTERNAL MEMORY device can interface with a variety of external memory devices Six chip selects can be indi vidually programmed for bus width the number of wait states and a multiplexed or demulti plexed address data bus Other features of
470. the status word which is described here the low byte is the INT MASK register The status word contains one bit PSW 1 that globally enables or disables servicing of all maskable interrupts one bit PSW 2 that enables or disables the peripheral transaction server PTS and six Boolean flags that reflect the state of a user s program The status word portion of the PSW cannot be accessed directly To access the status word push the value onto the stack PUSHF then pop the value to a register POP test reg The PUSHF and PUSHA instructions save the PSW in the system stack and then clear it POPF and POPA restore it 15 8 2 V VT PSE ST See INT MASK on page C 25 Bit Bit Function Number Mnemonic 4 VT Overflow trap Flag This flag is set when the overflow flag is set but it is cleared only by the CLRVT JVT and JNVT instructions This allows testing for a possible overflow at the end of a sequence of related arithmetic operations which is generally more efficient than testing the overflow flag after each operation 3 C Carry Flag This flag is set to indicate an arithmetic carry or the last bit shifted out of an operand It is cleared if a subtraction operation generates a borrow Normally the result is rounded up if the carry flag is set The sticky bit flag allows a finer resolution in the rounding decision See the PSW flag descriptions in Appendix A for details 2 PS
471. ther than the signal on TXD Although these two signals are normally synchronized the internal signal generates one clock before the first pulse transmitted by TXD and this first clock signal is not synchronized with TXD This clock signal causes the receive shift register to shift in whatever data is present on the RXD pin This data is treated as the least significant bit LSB of the reception The reception then continues in the normal synchronous manner but the data received is shifted left by one bit because of the false LSB The seventh data bit transmitted is received as the most significant bit MSB and the transmitted MSB is never shifted into the receive shift register Using the internal peripheral clock at 25 MHz the maximum baud rate is 4 17 Mbaud for mode 0 receptions and 6 25 Mbaud for mode 0 transmissions The maximum baud rate for modes 1 2 and3 is 1 56 Mbaud for both receptions and transmissions For the 80C196NU using the internal peripheral clock at 50 MHz the maximum baud rates are doubled 12 5 Mbaud for mode 0 trans missions 8 33 Mbaud for mode 0 receptions and 3 13 Mbaud for modes 1 2 and 3 Table 8 3 shows the SP BAUD values for common baud rates when using a 25 MHz internal clock These values also apply to the 80C196NU at 50 MHz with the prescaler enabled Table 8 3 shows the BAUD value for 9600 baud when using a 50 MHz clock input with the prescaler disabled Because of rounding the BAUD VALUE formula is
472. therwise it is set DEST SRC PSW Flag Settings Z N C V VT ST 1 DEC DECREMENT WORD Decrements the value DEST of the operand by one DEC wreg DEST lt DEST 1 00000101 wreg PSW Flag Settings Z N C vVv VTI ST DECB DECREMENT BYTE Decrements the value DEST of the operand by one DECB breg DEST lt DEST 1 00010101 breg PSW Flag Settings Z NC vV VTI ST ae eed e intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format DI DISABLE INTERRUPTS Disables interrupts Interrupt calls cannot occur after DI his instruction 11111010 Interrupt Enable PSW 1 lt 0 PSW Flag Settings Z N C V VT ST DIV DIVIDE INTEGERS Divides the contents of DEST SRC the destination long integer Fiol by DIV Ireg waop contents of the source integer word operand using signed arithmetic It stores the quotient 11111110 100011 waop into the low order word of the destination i e the word with the lower address and the remainder into the high order word The following two statements are performed concurrently low word DEST lt DEST SRC high word DEST lt DEST MOD SRC PS
473. tination byte operand DEST lt gt SRC PSW Flag Settings Z N C V VT ST 00010100 baop breg direct 00011011 baop breg indexed A 45 8 196 80C196NU USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format XOR LOGICAL EXCLUSIVE OR WORDS XORs DEST SRC the source word operand with the destination yor wreg waop word operand and stores the result in the destination operand The result has ones in 100001 waop wreg the bit positions in which either operand but not both had a 1 and zeros in all other bit positions DEST lt DEST SRC PSW Flag Settings Z N C V VT ST 0 0 XORB LOGICAL EXCLUSIVE OR BYTES XORs DEST SRC the source byte operand with the destination XORB breg baop byte operand and stores the result in the destination operand The result has ones in the bit positions in which either operand but not both had a 1 and zeros in all other bit positions DEST lt DEST SRC PSW Flag Settings Z N C V VT ST 0 0 100101aa baop breg Table A 7 lists the instruction opcodes in hexadecimal order along with the corresponding in struction mnemonics A 46 lel INSTRUCTION SET REFERENCE Table A 7 Instruction Opco
474. tion not just the last calculation For example if the result of adding together the lower words of two double words is zero the zero flag would be set When the upper words are added together using the ADDC instruction the flag remains set if the result is zero and is cleared if the result is not zero 6 N Negative Flag This flag is set to indicate that the result of an operation is negative The flag is correct even if an overflow occurs For all shift operations and the NORML instruction the flag is set to equal the most significant bit of the result even if the shift count is zero 5 V Overflow Flag This flag is set to indicate that the result of an operation is too large to be represented correctly in the available space For shift operations SHL SHLB and SHLL the flag is set if the most significant bit of the operand changes during the shift For divide operations the quotient is stored in the low order half of the destination operand and the remainder is stored in the high order half The overflow flag is set if the quotient is outside the range for the low order half of the destination operand Chapter 4 Programming Considerations defines the operands and possible values for each See the PSW flag descriptions in Appendix A for details C 34 intel REGISTERS PSW PSW Continued no direct access The processor status word PSW actually consists of two bytes The high byte is
475. tion are disconnected from the pins so a floating pin will not cause increased power consumption Open drain outputs require an external pull up resistor Inputs must be driven or pulled high or low they must not be allowed to float 7 19 intel Serial I O SIO Port intel CHAPTER 8 SERIAL SIO PORT A serial input output SIO port provides a means for the system to communicate with external devices This device has a serial I O SIO port that shares pins with port 2 This chapter describes the SIO port and explains how to configure it Chapter 7 I O Ports explains how to configure the port pins for their special functions Refer to Appendix B for details about the signals dis cussed in this chapter 81 SERIAL I O SIO PORT FUNCTIONAL OVERVIEW serial I O port Figure 8 1 is an asynchronous synchronous port that includes a universal asynchronous receiver and transmitter UART The UART has one synchronous mode mode 0 and three asynchronous modes modes 1 2 and 3 for both transmission and reception Internal Data Bus SBUF RX Receive Shift Register A _JRXD SBUF_TX Control Logic SP_STATUS Transmit Shift Register at Ho Baud Rate zs 1 Generator SP BAUD A3070 02 TI Interrupts RI Internal Clock Signal Note The prescale circuitry is unique to the 80C196NU Figure 8 1 SIO Block Diagram The serial port
476. tion within page 00H Figure 6 15 PTS Control Block PWM Toggle Mode 6 29 8XC196NP 80C196NU USER S MANUAL intel PTS PWM Toggle Mode Control Block Continued Register Location Function PTSCON PTSCB 1 PTS Control Bits M2 0 PTS Mode These bits specify the PTS mode M2 M1 MO 0 1 0 PWM TMOD Toggle Mode Select 1 PWM toggle mode TBIT Toggle Bit Initial Value Defines the initial value of TBIT 0 selects initial value as zero 1 selects initial value as one The TBIT value determines whether PTSCONST1 or PTSCONST2 is added to the PTSPTR1 value 0 PTSCONST1 is added to PTSPTR1 1 PTSCONST2 is added to PTSPTR1 Reading this bit returns the current value of TBIT which is toggled by hardware at the end of each PWM toggle cycle Figure 6 15 PTS Control Block PWM Toggle Mode Continued Figure 6 16 is a flow diagram of the EPA and PTS operations for this example Operation begins when the timer is enabled at time in Figure 6 14 on page 6 27 by the write to TICONTROL The first timer match occurs at time T1 The EPA toggles the output pin to zero and generates an interrupt to initiate the first PTS cycle PWM Toggle Cycle 1 Because TBIT is initialized to one the PTS adds the off time value T2 to EPAO_TIME and toggles TBIT to zero The second timer match occurs at time T2 the end of one complete PWM pulse The EPA tog
477. tions 11 4 THE ON CHIP OSCILLATOR CIRCUITRY The on chip oscillator circuit Figure 11 3 consists of a crystal controlled positive reactance os cillator In this application the crystal operates in a parallel resonance mode The feedback resis tor Rf consists of paralleled n channel and p channel FETs controlled by the internal powerdown signal In powerdown mode Rf acts as an open and the output drivers are disabled which disables the oscillator Both the XTAL1 and XTAL2 pins have built in electrostatic discharge ESD pro tection NOTE For the 80C196NU although the maximum external clock input frequency is 50 MEZ the maximum oscillator input frequency is limited to 25 MHz To internal circuitry Voc XTAL2 Output XTAL1 Input Oscillator Enable from powerdown circuitry A0076 03 Figure 11 3 On chip Oscillator Circuit 8XC196NP 80C196NU USER S MANUAL intel Figure 11 4 shows the connections between the external crystal and the device When designing an external oscillator circuit consider the effects of parasitic board capacitance extended oper ating temperatures and crystal specifications Consult the manufacturer s datasheet for perfor mance specifications and required capacitor values With high quality components 20 pF load capacitors C are usually adequate for frequencies above 1 MHz Noise spikes on the XTAL1 or XTAL2 pin can cause a miscount in the internal clock generating
478. tive saturation changes the accumulator value to 80000000H Accumu lation proceeds normally after saturation which means that the accumulator value can increase from a negative saturation or decrease from a positive saturation intel Programming Considerations intel CHAPTER 4 PROGRAMMING CONSIDERATIONS This section provides an overview of the instruction set of the MCS9 96 microcontrollers and of fers guidelines for program development For detailed information see Appendix A 41 OVERVIEW OF THE INSTRUCTION SET about specific instructions The instruction set supports a variety of operand types likely to be useful in control applications see Table 4 1 NOTE The operand type variables are shown in all capitals to avoid confusion For example a BYTE is an unsigned 8 bit variable in an instruction while a byte is any 8 bit unit of data either signed or unsigned Table 4 1 Operand Type Definitions No of Addressing Operand Type Bits Signed Possible Values Restrictions BIT 1 No True 1 or False 0 As components of bytes BYTE 8 No 0 through 28 1 0 through 255 None SHORT INTEGER 8 Yes 27 through 27 1 None 7128 through 127 WORD 16 No 0 through 216 1 Even byte address 0 through 65 535 INTEGER 16 Yes 215 through 215 1 Even byte address 732 768 through 32 767 DOUBLE WORD 32 No 0 through 232 1 An address in the lower Note 1 0 t
479. to the EPORT EPORT pins configured for the extended address function EP MODE x set output this address 2 During nonextended accesses EPORT pins configured for the extended address function EP MODE x set output the value contained in EP REG 7 18 intel PORTS 3 Any nonextended or direct instruction that accesses the register file or the windowable SFRs is always directed internally to these areas regardless of the page from which code is executing This effectively maps the register file and windowable SFRs into every page Extended instructions can access the mapped over areas of each page as shown in the following code example EST 1 01001CH 0 reg 1CH stored at memory location 01001CH 7 3 3 4 Design Considerations At the end of EPORT bus activity and during periods of internal bus activity EPORT pins con tinue to drive the last data address that was output If these lines are being used to enable external memory that memory will remain enabled until a different page is accessed During the CCB fetch all EPORT lines are strongly driven high Designers should ensure that this does not conflict with external systems that are outputting signals to the EPORT When EPORT pins are floated during idle powerdown or hold the external system must provide circuitry to prevent CMOS inputs on external devices from floating During powerdown the EPORT input buffers on pins configured for their extended address func
480. tomatically stores the result in the accumulator If bit 3 of the destination address is set address 08H 09H OFH the 80C196NU clears the accumulator before it stores the result of the current instruction If bit 3 of the destination address is clear address 00H 01H 07H it adds the result of the current instruction to the existing contents of the accumulator This simple example illustrates the results of consecutive multiply accumulate instructions The results of the first three instructions are automatically added together in the accumulator while the last instruction clears the accumulator before the result is stored register 1 register 3 10 decimal 0AH register 2 30 decimal 1EH register 4 20 decimal 14H 40 decimal 28H 200 decimal 1400 decimal 2200 decimal 600 decimal mul 00H register l register 2 10 20 200 Accumulator mul 00H register 3 register 4 30 40 1200 Accumulator mul 00H register 2 register 4 20 40 800 Accumulator mul 08H register_2 register_3 20 30 600 Accumulator Table 3 1 compares the instructions required to perform a multiply accumulate operation for the 8XC196NP and those required for the 80C196NU The 8XC196NP requires four instructions while the 80C196NU requires only one to accomplish the same operation The four 8 196 instructions take a total of 32 state times to execute while the single 80C196NU instruction takes only 16 state times In addition the 80C19
481. transmit receive modes meaning that they can transmit and receive data simultaneously Mode 1 is the standard 8 bit asynchronous mode used for nor mal serial communications Modes 2 and 3 are 9 bit asynchronous modes typically used for in terprocessor communications see Multiprocessor Communications on page 8 8 In mode 2 the serial port sets an interrupt pending bit only if the ninth data bit is set In mode 3 the serial port always sets an interrupt pending bit upon completion of a data transmission or reception 8 5 8XC196NP 80C196NU USER S MANUAL intel When the serial port is configured for mode 1 2 or 3 writing to SBUF TX causes the serial port to start transmitting data New data placed in TX is transmitted only after the stop bit of the previous data has been sent falling edge on the RXD input causes the serial port to begin receiving data if RXD is enabled Disabling RXD stops a reception in progress and inhibits fur ther receptions See Programming the Control Register on page 8 8 8 3 2 1 Mode 1 Mode 1 is the standard asynchronous communications mode The data frame used in this mode Figure 8 4 consists of ten bits a start bit 0 eight data bits LSB first and a stop bit 1 If parity is enabled a parity bit is sent instead of the eighth data bit and parity is checked on recep tion 8 Bits of Data or 7 Bits of Data with Parity Bit k 10 Bit Frame A0245 02 Figur
482. ts Since interrupt procedures can execute essentially at any time they must save and restore both the PSW and TMPREGO 4 13 8XC196NP 80C196NU USER S MANUAL intel 4 6 SOFTWARE PROTECTION FEATURES AND GUIDELINES The device has several features to assist in recovering from hardware and software errors The unimplemented opcode interrupt provides protection from executing unimplemented opcodes The hardware reset instruction RST can cause a reset if the program counter goes out of bounds The RST instruction opcode is FFH so the processor will reset itself if it tries to fetch an instruc tion from unprogrammed locations in nonvolatile memory or from bus lines that have been pulled high We recommend that you fill unused areas of code with NOPs and periodic jumps to an error rou tine or RST instruction This is particularly important in the code surrounding lookup tables since accidentally executing from lookup tables will cause undesired results Wherever space allows surround each table with seven NOPs because the longest device instruction has seven bytes and a RST or a jump to an error routine Since RST is a one byte instruction the NOPs are unneces sary if RSTs are used instead of jumps to an error routine This will help to ensure a speedy re covery from a software error intel Memory Partitions intel CHAPTER 5 MEMORY PARTITIONS This chapter describes the organization of the address space its major partitions an
483. ts of measure amps amperes direct current volts kilobytes kilohertz kilo ohms milliamps milliamperes megabytes megahertz milliseconds milliwatts nanoseconds picofarads watts volts microamps microamperes microfarads microseconds microwatts Uppercase X no italics represents an unknown value or an irrelevant don t care state or condition The value may be either binary or hexadecimal depending on the context For example 2XAFH hex indicates that bits 11 8 are unknown 10XXB binary indicates that the two least significant bits are unknown 1 3 RELATED DOCUMENTS The tables in this section list additional documents that you may find useful in designing systems incorporating MCS 96 microcontrollers These are not comprehensive lists but are a representa tive sample of relevant documents For a complete list of available printed documents please or der the literature catalog order number 210621 To order documents please call the Intel literature center for your area telephone numbers are listed on page 1 11 Intel s ApBUILDER software hypertext manuals and datasheets and electronic versions of ap plication notes and code examples are also available from the BBS see Bulletin Board System BBS on page 1 9 New information is available first from FaxBack and the BBS Refer to Electronic Support Systems on page 1 8 for details 1 5 8XC196NP 80C196NU USER S MANUAL intel Table 1
484. ture occurs while the event time register EPAx TIME and its buffer are both full When an overrun occurs the ON bit determines whether old data is overwritten or new data is ignored 0 ignores new data 1 overwrites old data in the buffer In Compare Mode RT 0 disables the reset function 1 resets the ROT selected timer These bits apply to the EPA1 CON and EPA3 CON registers only 22 lel Table C 8 EPAx CON Addresses and Reset Values Register Address Reset Value EPAO0 CON 1F80H 00H EPA1 CON 1F84H 0000H EPA2 CON 1F88H 00H EPA3 CON 1F8CH 0000H REGISTERS EPAx CON C 23 8 196 80C196NU USER S MANUAL intel EPAx TIME EPAx TIME Address Table C 9 xz 0 3 Reset State The EPA time EPAx TIME registers are the event time registers for the EPA channels In capture mode the value of the reference timer is captured in EPAx TIME when an input transition occurs Each event time register is buffered allowing the storage of two capture events at once In compare mode the EPA triggers a compare event when the reference timer matches the value in EPAx TIME EPAx TIME is not buffered for compare mode 15 8 EPA Timer Value high byte 7 0 EPA Timer Value low byte ca Function 15 0 EPA Time Value When an EPA channel is configured for capture mode this register contains the value of the reference timer when the specifi
485. ular pulse train that varies in duty cycle and period Filtering this output will create a smooth analog signal To make a signal swing over the desired analog range first buffer the signal and then filter it with either a simple RC network or an active filter Figure 9 6 is a block diagram of the type of circuit needed to create the smooth analog sig nal 9 9 8XC196NP 80C196NU USER S MANUAL intel 8XC196 Buffer Filter Power Device to Make Passive Amp Output Swing or Analog PWM Active Optional Output Optional A2391 01 Figure 9 6 D A Buffer Block Diagram Figure 9 7 shows a sample circuit used for low output currents less than 100 WA Consider tem perature and power supply drift when selecting components for the external D A circuitry With proper components a highly accurate 8 bit D A converter can be made using the PWM Analog Output 8XC1 96 74 Device Buffer L Consider both ripple and response time requirements when selecting R and C A2390 02 Figure 9 7 PWM to Analog Conversion Circuitry 9 10 intel 10 Event Processor Array EPA intel CHAPTER 10 EVENT PROCESSOR ARRAY EPA Control applications often require high speed event control For example the controller may need to periodically generate pulse width modulated outputs or an interrupt In another application the controller may monitor an input signal to determine the status of an
486. ur Notice that the preamble and exit code for this routine does not save or restore register RAM The interrupt service routine is assumed to allocate its own private set of registers from the lower register file The general purpose register RAM in the lower register file makes this quite practi cal In addition the RAM in the upper register file is available via windowing see Windowing on page 5 13 6 5 3 Determining the Source of an Interrupt When the transition detector detects an interrupt it sets the corresponding bit in the INT PEND or INT PENDI register Figures 6 7 and 6 8 This bit is set even if the individual interrupt is disabled masked The pending bit is cleared when the program vectors to the interrupt service routine INT PEND and INT PENDI can be read to determine which interrupts are pending They can also be modified written either to clear pending interrupts or to generate interrupts under software control However we recommend the use of the read modify write instructions such as AND and OR to modify these registers ANDB INT PEND 11111110B Clears the OVRTM1 pending bit ORB PEND 00000001B Sets the OVRTM1 pending bit Other methods could result in a partial interrupt cycle For example an interrupt could occur dur ing an instruction sequence that loads the contents of the interrupt pending register into a tempo rary register modifies the contents of the temporary register and then
487. ure 9 2 PWM Block Diagram 80C196NU Only 9 2 PWM SIGNALS AND REGISTERS Table 9 1 describes the PWM s signals and Table 9 2 briefly describes the control and status reg isters Table 9 1 PWM Signals Port Pin Signal Si cena Description P4 0 PWMO Pulse width modulator 0 output with high drive capability P4 1 PWM1 Pulse width modulator 1 output with high drive capability P4 2 PWM2 Pulse width modulator 2 output with high drive capability intel PULSE WIDTH MODULATOR Table 9 2 PWM Control and Status Registers Mnemonic Address Description CON REGO 1FB6H PWM Control Register This register controls the clock prescaler Bit 0 CLKO controls the output period of the PWM channels by enabling or disabling the divide by two clock prescaler 8 196 only Bits 0 and 1 CLKO CLK1 control the output period of the PWM channels by enabling or disabling the divide by two or divide by four clock prescaler B0C196NU only PWMO CONTROL PWM1 CONTROL PWM2 CONTROL 1FBOH 1FB2H 1FB4H PWM Duty Cycle This register controls the PWM duty cycle A zero loaded into this register causes the PWM to output a low continu ously 0 duty cycle An FFH in this register causes the PWM to have its maximum duty cycle 99 6 duty cycle P4 DIR 1FDBH Port 4 Direction The P4 DIR register determines the I O mode for each port 4 pin The register settings for an
488. w trap flag is set when the overflow flag is set but it is cleared only by the CLRVT JVT and JNVT instructions This allows testing for a possible overflow at the end of a sequence of related arithmetic operations which is generally more efficient than testing the overflow flag after each operation 2 The zero flag is set to indicate that the result of an operation was zero For multiple precision calculations the zero flag cannot be set by the instructions that use the carry bit from the previous calculation e g ADDC SUBC However these instructions can clear the zero flag This ensures that the zero flag will reflect the result of the entire operation not just the last calculation For example if the result of adding together the lower words of two double words is zero the zero flag would be set When the upper words are added together using the ADDC instruction the flag remains set if the result is zero and is cleared if the result is not zero intel INSTRUCTION SET REFERENCE Table A 3 shows the effect of the PSW flags or a specified condition on conditional jump instruc tions Table A 4 defines the symbols used in Table A 6 to show the effect of each instruction on the PSW flags Table A 3 Effect of PSW Flags or Specified Conditions on Conditional Jump Instructions Instruction Jumps to Destination if
489. windowing the upper register file WSR Address 0014H Reset State 00H The window selection register WSR has two functions One bit enables and disables the bus hold protocol The remaining bits select windows Windows map sections of RAM into the top of the lower register file in 32 64 or 128 byte increments PUSHA saves this register on the stack and POPA restores it 7 0 HLDEN W6 W5 WA w3 W2 W1 WO Bit Bit Number Mnemonic Function 7 HLDEN HOLD HLDA Protocol Enable This bit enables and disables the bus hold protocol see Chapter 13 Interfacing with External Memory It has no effect on windowing 1 enable 0 disable 6 0 W6 0 Window Selection These bits specify the window size and window number See Table 5 8 on page 5 15 or Table 5 9 on page 5 15 Figure 5 5 Window Selection WSR Register intel MEMORY PARTITIONS WSR1 80C196NU Address Reset State Window selection 1 WSR1 register selects a 32 or 64 byte segment of the upper register file or peripheral SFRs to be windowed into the middle of the lower register file below any window selected 0015H 00H by the WSR 7 0 80C196NU W6 W5 WA W3 W2 W1 WO Bit Bit Number Mnemonic Function Reserved always write as zero 6 0 W6 0 Window Selection These bits specify the window siz
490. writes the contents of the temporary register back into the interrupt pending register If the interrupt occurs during one of the last four states of the second instruction it will not be acknowledged until after the completion of the third instruction Because the third instruction overwrites the contents of the interrupt pend ing register the jump to the interrupt vector will not occur An overrun on the EPA capture compare channels can generate the multiplexed capture overrun interrupts OVRO 1 and OVR2 3 Read the PEND register to determine the source of the interrupt request Figure 10 12 on page 10 23 8 196 80C196NU USER S MANUAL intel INT PEND Address Reset State 0009H 00H When hardware detects a pending interrupt it sets the corresponding bit in the interrupt pending INT PEND or INT PEND1 registers When the vector is taken the hardware clears the pending bit Software can generate an interrupt by setting the corresponding interrupt pending bit 7 0 EPAO RI TI EXTINT1 EXTINTO OVRTM2 OVRTM1 Bit Number Function 7 3 Any set bit indicates that the corresponding interrupt is pending The interrupt bit is 1 0 cleared when processing transfers to the corresponding interrupt vector The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector EPAO EPA Capture Compare Channel 0 FF200EH RI SIO Receive FF200CH TI SIO Trans
491. y location to the destination memory location A location in special purpose memory that holds the starting address of a PTS control block An unsigned 64 bit variable with values from 0 through 29 1 The QUAD WORD variable is supported only as the operand for the EBMOVI instruction Register arithmetic logic unit A part of the CPU that consists of the ALU the PSW the master PC the microcode engine a loop counter and six registers intel reserved memory sampled inputs saturation mode set SFR SHORT INTEGER sign extension sink current source current SP special interrupt GLOSSARY A memory location that is reserved for factory use or for future expansion Do not use a reserved memory location except to initialize it with FFH All input pins with the exception of RESET are sampled inputs The input pin is sampled one state time before the read buffer is enabled Sampling occurs during PHI while CLKOUT is low and resolves the value high or low of the pin before it is presented to the internal bus If the pin value changes during the sample time the new value may or may not be recorded during the read RESET is a level sensitive input EXTINTx is normally a sampled input however the powerdown circuitry uses EXTINTx as a level sensitive input during powerdown mode Saturation occurs when the result of two positive numbers generates a negative sign bit or the result of two negative numbers
492. ycle Mode 80C196NU Only on page 13 40 0 deferred bus cycle mode disabled 1 deferred bus cycle mode enabled 4 3 1 To guarantee device operation write ones to these bits ait REMAP Internal ROM Mapping Controls the internal ROM mapping 0 ROM maps to FF2000 FF2FFFH only 1 ROM maps to FF2000 FF2FFFH and 002000 002FFFH 1 MODE64 Addressing Mode Selects 64 Kbyte or 1 Mbyte addressing 0 selects 1 Mbyte addressing 1 selects 64 Kbyte addressing 0 Reserved for compatibility with future devices write zero to this bit The CCRs are loaded with the contents of the chip configuration bytes CCBs after a device reset The CCBs reside in nonvolatile memory at addresses FF2018H CCBO and FF201AH CCB1 tt Bit 5 is reserved on the 8XC196NP device and bit 2 is reserved the 80C196NU device For compatibility with future devices write zeros to these bits Figure 13 7 Chip Configuration 1 CCR1 Register Upon leaving the reset state the device is configured for normal operation This section describes the state of the chip following reset and summarizes the steps in the configuration process 18 16 intel INTERFACING WITH EXTERNAL MEMORY Following reset the chip automatically fetches the two chip configuration bytes e 83C196NP only The CCB fetches are from external memory if EA s 0 and from internal ROM if EA 1 80C196NP and 80C196NU only The CCB fetches are f

8XC196NP, 80C196NU Microcontroller User`s Manual

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