MC10P5010 User Manual V1.3
Contents
1. Shanghai Sinasun Micvaetectranics Ca Ltd page 16 of 22 485 sinesun we mcr MC10P5010 User Manual V1 3 9 3 AC Electrical Characteristics VDD 3V 4 040 4 035 4 030 4 025 4 020 4 015 4 010 T 25 C Characteristics Symbol Pin Condition Min Typ Max External Oscillator Frequency Fe 325K 8M Hz T 25C Fret 1 4 1 MHz VDD 3V Internal RC Frequency a z T 20C 70 C Fo 2 4 2 MHz VDD 1 8 3 6V VDD 3V Built in RC fosc vs Temperature 4 005 4 000 3 995 3 990 3 985 3 980 3 3 3 3 fIHRC MHz 3 975 3 970 3 965 960 4 040 4 035 4 030 4 025 4 020 4 015 4 010 4 005 fIHRC CMHz 3 995 3 990 3 985 3 980 3 975 3 970 3 965 3 960 20 30 Temperature C 40 Temperature 27 C Built in RC fosc vs VDD 70 1 80 1 90 2 00 2 10 2 20 2 30 2 40 2 50 2 60 2 70 2 80 2 90 3 00 3 10 3 20 3 30 3 40 3 50 3 60 VDD V Shanghai Sinosun Microelectronics Ca Ltd page 17 of 22 sinssun FR M9 EEF MC10P5010 User Manual V1 3 10 Typical Application Schematics SOP20 Internal RC Oscillator A Nd ten O Teken i Notel The decoupling capacitor C2 should not be omitted C2 must be positioned as close as possible to the IC pins The distance should not be larger than 5cm Note2 If the cu2. Osc Freq Capacitance of Cx SMH Omitted 15 typical oscillator frequency and ee Zz mi l E P recommended capacitance value of T 4MHz Omitted 15p 30p De pe Cx ne See pie Note Considering the different 455KHz 100p 300p chatactetistics of different types of oscillatot the capacitance value listed are merely suggested Please select the capacitor cautiously according to the chatactetistic of crystal or ceramic oscillator 3 2 Internal High accuracy RC The frequency of MC10P5010 s RC oscillator is 4MHz While selecting internal RC mode PCO and PC1 can be used as GPIO Special Note To make oscillating accurately and stably it is necessaty to connect a capacitor whose capacitance is larger than 10uF between VDD and GND and let the distance from the capacitor to the chip as short as possible less than 5cm 4 GPIO MC10P5010 has 16 general purpose input output GPIO ports PA7 PAO PB7 PB2 PCI PCO and one input ports PBO Each GPIO is controlled by the corresponding Data Register bit PA PB and PC and Direction Register bit DDRA DDRB and DDRC When a GPIO excluding PC1 and PCO is used as input port it can select internal pull up 25Kohm resistor or not through setting the register KBIM or PBP PBP3 and PBP2 in MCR The following figure shows the structure of GPIO Direction Reg Bit DBUS Shanghai Sinosun Microelectronics Ca Ltd page 7 of 22 sinssun RI MF MC10P5010 User
3. 0 PAn s keyboard interrupt function is disabled 1 PAn s keyboard interrupt function is enabled configuring PAn to input mode and connects internal 25Kohm pull up resistor automatically 05 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O DDRB DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 KBEBO R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 BIT O KBEBO PBO keyboard interrupt function enable bit 0 PBO s keyboard interrupt function is disabled 1 PBO s keyboard interrupt funct by PBPO in OPBIT ion is enabled pull up resistor of PBO is controlled 0C Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O MCR KBIE KBIC PBP PBP3 PBP2 OUTC FCAE R W RAN R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 BIT 7 KBIE Keyboard interrupt enable bit 0 Keyboard interrupts master is disabled 1 Keyboard interrupts master is enabled BIT 6 KBIC Keyboard interrupt clear bit Writing a pos clears the keyboard interrupt latch Writing a This bit always reads as zero 7 3 Timer Interrupt The timer interrupt TMI requirement is relative with two factors qe has no effect 1 Timer interrupt mask bit TIM While TIM 1 the timer interrupt is masked otherwise the timer interrupt is enabled 2 Timer interrupt flag bit TIF When the counter of timer decrements to zero TIF will be set which means TMI
4. with carrier 1 0 0 L 1 0 1 H without catrier 1 1 0 L Shanghai Sinosun Micraetectianics Ca Ltd page 11 of 22 485 sinesun p ql ns MC10P5010 User Manual V1 3 1 1 1 H with carrier The carrier wave of IROUT is generated based on the system clock 1 2 frequency of oscillator frequency FC 2 0 in OPBIT is used to configure the ratio as the following table OSC IROUT FC 2 0 Ratio to Fsys Frequency Carrier Frequency Hz Hz 000 6 445K 37 91K 001 36 4M 55 56K 010 50 4M 40 00K 011 53 4M 37 74K 100 56 4M 35 71K 101 61 4M 32 78K 110 64 4M 31 25K 111 74 4M 27 03K Here are the relative registers of IROUT 0C Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O MCR KBIE KBIC PBP PBP3 PBP2 OUTC FCAE R W R W R W z R W R W R W R W R W Initial Value 0 0 gt 0 0 0 0 0 BIT 1 OUTC IROUT logic control bit 0 IROUT outputs logic 0 1 IROUT outputs logic 1 BIT 0 FCAE Carrier wave output enable bit 0 IROUT outputs without carrier wave 1 IROUT outputs with carrier wave 7 Interrupt 7 1 General Description The interrupts of MC10P5010 are keyboard interrupt KBI timer interrupt TMI and software interrupt SWI KBI and TMI can be masked by I bit which is in CPU status control register CCR but SWI cannot be masked Furthermore SWI is also an instruct For details about SWI please refer to the datasheet H
5. 3 PBP3 PB3 O Eh 0 PB3 s 25Kohm pull up is disconnected 1 PB3 s 25Kohm pull up is connected the port must be configured to input BIT 2 PBP2 PB2LFLijy 0 PB2 s 25Kohm pull up is disconnected 1 PB2 s 25Kohm pull up is connected the port must be configured to input Note PBO s pull up resistor is controlled by PBPO in OPBIT 0D Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O PC E PC1 PCO R W RAN RAN Initial Value 0 0 BIT 1 0 PCn PC Data register n 1 0 0E Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O DDRC DDRC1 DDRCO R W gt R W R W Initial Value 0 0 BIT 1 0 DDRCn PC Direction register n 1 0 0 Configured to input 1 Configured to output 5 Timer The timer of MC10P5010 contains a single 8 bit software programmable count down counter with 7 bit software selectable prescaler The counter may be preset under software control and decrements towards zero When the counter decrements to zero the timer interrupt flag TIF bit in TCR is set Once the timer interrupt flag is set an interrupt is generated to CPU only if TIM bit in TCR and I bit in CCR are cleared For more information about interrupt please refer to SARI RRA AVR The timer counts the system clock through prescaler continuously The contents of the counter TDR may be re
6. Manual V1 3 The function of data register and direction register is listed below R W DDR Function W 0 The port is in input mode Data is written into the output data latch W 1 The port is in output mode Data is written into the output latch and output to the port R 0 The port is in input mode The state of port is read R 1 The port is in output mode The output data latch is read PAs can be used as keyboard interrupt input Each PAs can be configured by corresponding bit of KBIM When KBEn 1 n 0 to 7 PAn is configured as keyboard interrupt input meanwhile the pull up resistor is connected For detail information about keyboard interrupt please refer to When PB2 PB7 is configured as input internal pull up resistor can be selected The pull up of PB2 is controlled by PBP2 in MCR PB3 s is controlled by PBP3 and PB4 PB7 s are all controlled by PBP PBO is used as high voltage input when programming OTP Normally it is used as an input and has a selectable internal pull up resistor and can be configured as keyboard interrupt input controlled by KBEBO in DDRB Refer to 7 2 PC1 and PCO can be used as GPIO when internal RC mode is selected Here are the relative registers of GPIO 00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bi
7. data register to determine which port triggers the interrupt The keyboard interrupt circuit diagram is shown below KBE 7 0 KBEBO DDRA 7 0 PA PBO Data bit Trigger Singnal from other ports KBI requirement to CPU L Port The keyboard interrupt KBI requirement is relative with three factors 1 KBIE in MCR KBIE is enable bit of KBI While KBIE 1 KBI function is enabled While KBIE 0 KBI function is disabled 2 KBE 7 0 corresponding to PA 7 0 and KBEBO corresponding to PBO While KBEn 1 KBEBO 1 the KBI function of PAn PBO is enabled otherwise KBI function is disabled 3 The state of PA7 PAO and PBO When the state of the pin changes from high level to low the KBI interrupt is triggered So KBI is low level triggered interrupt Shanghai Sinosun Microelectronics Ca Ltd page 13 of 22 sinssun RI ERF MC10P5010 User Manual V1 3 KBIC in MCR is relative to KBI response After the processor responds the KBI interrupt KBIC bit should be written to qe interrupt will be responded endlessly Here are the relative registers of KBI otherwise the KBI requirement will be latched which means the 0B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 KBIM KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBEO R W R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 BIT 7 0 KBEn PA keyboard interrupt function enable bit n 7 0
8. CO5 Instruction Set The process of interrupt response is lt While interrupt request occurring CPU pushes all the relative registers 5 bytes altogether to the system stack set I bit to 1 and mask all the other interrupts Differently from system reset hardware interrupt does not terminate current instruction execution but suspends itself until current instruction finished Shanghai Sinasun Micvaetectranics Ca Ltd page 12 of 22 FERIIS fri cB MC10P5010 User Manual V1 3 sinssun lt gt While responding interrupt firstly CPU fetches the entrance address of the interrupt service subroutine from the corresponding interrupt vector then jumps to the subroutine and executes Each interrupts service subroutine needs an RTI instruct When executing RTI CPU pops all status registers from the system stack and executes the instruct exactly after the interrupt happened The interrupt vectors are shown bellow The priority is decreased from bottom to top in the list Vector Address Interrupt 1FF0 1FF1 Resetved 1FF2 1FF3 Reserved 1FF4 1FE5 KBI 1FF6 1FF7 TMI 1FF8 1FF9 Reserved 1FFA 1FFB Resetved 1FFC 1FFD SWI 1 FFE 1 FFF RESET 7 2 Keyboard Interrupt PAO PA7 and PBO can be used as keyboard interrupt inputs All the keyboard interrupt inputs use a single interrupt requirement port and a single interrupt vector The processor must read from GPIO s
9. MC10P5010 User Manual The Original User Manual s Name MC10P01 8 Bit MCU designed by SinoMCU 2014 3 24 Note Should there be any inconsistencies between Chinese and English version the Chinese version shall prevail sinssun Be I9 faX EB F E ERE dk YF AIR D 9 Shanghai SinoSun Microelectronics Co Ltd gt A 0 O0 A 10 11 sInssun ERD frd B F MC10P5010 User Manual V1 3 Contents Introduce CELO 5i aa qub AAA A AA SERE ETE E RENE REF REEE EE EE Ken 3 Lil Product Peatur s 2 el A Cure AA ANUS Iu URS NS ns 3 1 2 Block Diagram atas dived beate ia did dsd dio Sob Mod o pd ae Dr db added beh 4 lc3 Pin ASSTeNMent armen A A EPI ED E E cep Ee 4 1 4 Pan Description asss ii 5 CPi i ce seeds race A mna partur eu tarta trous NN 5 Zl Xnstr etron SEL annen ern AA wid acne ie Dita aen 5 2 24 Address Spa66 i eeu A A neee d edidi cud e dee 5 2 9 Program Memory ROM soria ardennen ada draden iuda pcdcs cess 5 2 4 User Data Memory RAM beu oe es remm E e one Ru enei ee ee ee er ele EC ER It 5 2 5 Configuration Bit OPBIT ven eee OER 5 2 6 Control Registers cesses ah c RER 6 System Clock AR GR TERR 6 3 1 External Oscillator o oooooomomormomo GR 7 3 2 Internal High accuracy RC i i aaa arn B AR aa ts 7 Ce EF Lees 7 DE MA 9 TROUT Port ER EAE eee 11 A IA A AA 12 7 1 General Description MEE O eee 12 1 2 Keyboard Interrupt SEE eN eee
10. RA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRAO 0000 0000 05 DDRB R W DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 KBEBO 0000 00 0 08 TDR RIW TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDRO uuuu uuuu 09 TCR RW TIF TIM PRER PR2 PR1 PRO 01 0100 0B KBIM R W KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBEO 0000 0000 0C MCR R W KBIE KBIC PBP PBP3 PBP2 OUTC FCAE 00 0 0000 0D PC RW PC1 PCO 00 0E DDRC R W DDRC1 DDRCO 00 Note means the bit is not defined u means the initial value is indefinite 3 System Clock The signal Fosc is generated by external crystal or ceramic oscillator or internal high accuracy RC oscillator The primary system clock Fsys is 1 2 frequency division of the signal Fosc Shanghai Sinasun Micvaetectranics Ca Ltd page 6 of 22 485 sinesun L muB MC10P5010 User Manual V1 3 3 1 External Oscillator Crystal or ceramic oscillator is connected as following diagram when the external oscillator mode is selected The oscillating frequency must be in the range of 325KHz to 8MHz The capacitor Cx is usually required When selecting 3 5MHz or higher frequency oscillator Cx can be omitted It is strongly recommended to make the crystal or ceramic oscillator as near as possible to OSCI and OSCO pin because of oscillating starting and stability The following table lists some
11. ad at any time without disturbing the count If writing TDR the counter will count from the new value Shanghai Sinasun Micvaetectranics Ca Ltd page 9 of 22 sinssun RI ERF MC10P5010 User Manual V1 3 The prescaler is a 7 bit divider which can get division ratio of 1 2 4 8 16 32 64 or 128 PR2 PRI and PRO of TCR are programmed to choose the appropriate prescaler output which is used as the 8 bit counter clock input The processor cannot write into or read from the prescaler however The timer block diagram is shown below Here are the relative registers of Timer Overflow Detect Interrupt Control TCR TIF TIM sa a its contents can be cleared to all zeros by writing the PRER in the TCR 08 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDRO R W R W R W R W R W R W R W R W R W Initial Value u u u u u u u u BIT 7 0 TDR 7 0 TDR is a read write register which contains the current value of 8 bit count down timer 09 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCH TIF TIM PRER PR2 PR1 PRO R W R W R W R W R W R W R W Initial Value 0 1 0 1 0 0 BIT 7 TIF Timer interrupt flag 0 The timer has not reached a count of zero 1 The timer has reached a count of zero Writing a 0 clears TIF Writing a 1 has no effect BIT 6 TIM Timer
12. current limiting resistor R1 should not be omitted Note3 The capacitor C1 could be omitted normally Shanghai Sinosun Microelectronics Ca Ltd page 19 of 22 485 sinesun e REF 11 Dimension of Package SOP20 300mil MC10P5010 User Manual V1 3 SP a Min Typical Max Min Typical Max A 394 420 10 01 10 67 B 290 300 7 37 7 62 C 14 20 0 36 0 51 C 495 512 57 13 00 D 92 104 2 34 2 64 E 50 1 27 F 4 0 10 G 32 38 0 81 0 97 H 12 0 10 0 30 n 0 8 o 8 Shanghai Sinosun Micraetectianics Ca Ltd page 20 of 22 sinssun ARS MC10P5010 User Manual V1 3 SOP16 150mil emos Un mil l Ume mm Min Typical Max Min Typical Max A 238 244 6 05 6 20 B 150 157 3 80 4 00 C 14 19 0 36 0 48 C 386 398 9 80 10 10 D 53 62 1 35 1 57 E 50 27 F 4 0 10 G 22 32 0 56 0 82 H 4 12 0 10 0 30 a o 8 0 8 Shanghai Sinosun Microelectronics Ca Ltd page 21 of 22 sing3sun e REEF MC10P5010 User Manual V1 3 12 REVISION HISTORY REV Date Description 1 0 2011 08 05 First edition issued 1 3 2014 03 24 The user manual s name MC10P01 changed to MC10P5010 Shanghai Sinasun Micvaetectranics Ca Ltd page 22 of 22
13. ee 13 7 3 Timer Interrupt T E eee eee 14 System Operation MEERN 7 MEE eee eee eee II 15 8 1 STOP Mod BA eee ee 15 8 2 WAIT Modem eee 15 Elected Sp amp eniimilkat ion ereen eee eee eeen 16 O AO e Mammie eee eee eee ee ee eee 16 9 2 DCWUBEkrical Characteristics eee eee eee ee 16 OC Pllectrical Characteristics eeen eeen eneen 17 Ty Application Schematics eee RR RR eee eee eee eee 18 IuNeusron of Package suus er dea tah A ng vald MEAD Oh Weds ebde 20 Shanghai Sinosun Micraetectianics Ca Ltd page 2 of 22 485 sinesun Ll ns MC10P5010 User Manual V1 3 MC10P5010 User Manual 1 Introduction MC10P5010 is a high performance 8 bit Microcontroller It has internal high accuracy RC oscillator circuit and infrared emission diode driving circuit It provides perfect solution for the remote control of TV DVD STB etc 1 1 Product Features 8 bit CPU with CISC structure compatible with HC05 1K 8 bits OTP ROM 32 bytes RAM including stack 8 bit timer 9 channels keyboard interrupt KBI 4992925 Infrared remote control code output IROUT which has 8 types carrier frequency selectable and can drive infrared emission diode directly lt gt Two types of oscillating mode External crystal or ceramic oscillator with frequency from 325KHz to 4MHz Internal high accuracy 4MHz RC oscillator Frequency deviation less than 1 CONDITION 3 0V 25 C Low power di
14. interrupt mask 0 Timer interrupt is not masked enabled 1 Timer interrupt is masked disabled BIT 3 PRER Prescaler reset bit Shanghai Sinosun Microelectronics Ca Ltd page 10 of 22 485 sinesun L muB MC10P5010 User Manual V1 3 Writing a 1 to PRER will reset prescaler to zero This bit always reads as zero BIT 2 0 PR 2 0 Prescaler division ratio selection The following table lists the value of PR 2 0 and the corresponding division ratio PR2 PR1 PRO Division Ratio 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 6 IROUT Port IROUT has ability to sink large current It can drive infrared emission diode directly IROUT outputs remote control signal with carrier wave whose duty ratio is 1 3 The frequency of IROUT has 8 types of selection controlled by FC 2 0 in OPBIT IRPO of OPBIT controls positive or negative logic of IROUT signal The IROUT control logic is shown below Carrier Wave System Signal Clock FCAE oe TROUT OUTC gt FCAE in MCR controls whether carrier wave is valid or not OUTC in MCR controls the logic of IROUT If FCAE or OUTC is zero the prescaler will be cleared to zero which guaranteed the first cycle of ROUT is entire The following is the truth table of IRPO OUTC FCAE and IROUT IRPO FCAE OUTC TROUT 0 0 0 H 0 0 1 L without carrier 0 1 0 H 0 1 1 L
15. is triggered TIF could not be cleared automatically so it must be cleared by software For more information about the function of TMI and TIF please refer to S Sim KAAS H Wo Shanghai Sinasun Micvaetectranics Ca Ltd page 14 of 22 485 sinesun L muB MC10P5010 User Manual V1 3 8 System Operation Modes MC10P5010 has two low power modes STOP mode and WAIT mode 8 1 STOP Mode The instruct STOP makes MCU enter STOP mode which has several effects bellow lt gt System primary oscillator stops amp Clear I bit in CCR and enable interrupt lt gt Data stored in RAM will be maintained lt gt All states of GPIO remain System primary oscillator stops lt gt All the internal operation stops If one of the following things happens MCU will exit from STOP mode lt gt KBI request occurs lt gt Any type of system reset occurs While MCU works under STOP mode almost all the operations terminate so the power dissipation is very low 8 2 WAIT Mode The instruct WAIT makes MCU enter WAIT mode which has several effects bellow lt gt CPU clock stops CPU process and internal bus activities terminate Clear I bit in CCR and enable interrupt Data stored in RAM will be maintained All states of GPIO remain lt gt All states of registers remain If one of the following things happens CPU clock will restarts and MCU will exit from WAIT lt gt gt gt mode lt gt Any type of interrup
16. ll up resistor selectable keyboard interrupt can be triggered 2 CPU 2 1 Instruction Set MC10P5010 uses HCO5 compatible instruction set For detail information about instruction set please refer to the datasheet HCO5 Instruction Set provided by Sinosun Note Instruct MUL jis not available 2 2 Address Space 0000 000F Control Register 0010 00DF Reserved 00E0 00FF RAM including Stack 0100 1BFF Reserved 1C00 1FFF OTP ROM 2 3 Program Memory ROM Program memory of MC10P5010 which is used to store instructions is an OTP ROM with size of IK bytes The highest address 1FF0 1FFF area of program memory is reset interrupt vector area 8 FUR URSRSISI RIS 2 4 Uset Data Memory RAM User data memory of MC10P5010 has 32 bytes which are shared with stack For more information about stack please refer to the datasheet HCO5 Instruction Set 2 5 Configuration Bit OPBIT Configuration Bit OPBIT is a special bit of OTP It is used as configuring system functions OPBIT is set while programming OTP ROM data with special programmer designed by Sinosun MC10P5010 s OPBIT is defined as follows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OPBIT ENCR PBPO IRPO RCEN FC2 FC1 FCO Shanghai Sinasun Micvaetectranics Ca Ltd page 5 of 22 485 sinesun L muB MC10P5010 User Manual V1 3 BIT 7 ENCR Program memory protection bit 0 Protec
17. rrent of the infrared emission diode D1 is particularly latge the current limiting resistor R1 should not be omitted Note3 The capacitor C1 could be omitted normally SOP20 External Crystal Ceramic Oscillator ENT PO pao PAL paz Pao PA3 PAS PAS Note1 The decoupling capacitor C2 should not be omitted C2 must be positioned as close as possible to the IC pins The distance should not be larger than 5cm Note2 If the current of the infrared emission diode D1 is particularly latge the current limiting resistor R1 should not be omitted Note3 The capacitor C1 could be omitted normally Shanghai Sinosun Microelectronics Ca Ltd page 18 of 22 a singsun Der MC10P5010 User Manual V1 3 SOP16 Internal RC Oscillator 104 j 47uF 16V PB Note1 The decoupling capacitor C2 should not be omitted C2 must be positioned as close as possible to the IC pins The distance should not be larger than 5cm Note2 If the current of the infrared emission diode D1 s particularly large the current limiting resistor R1 should not be omitted Note3 The capacitor C1 could be omitted normally SOP16 External Crystal Ceramic Oscillator Notel The decoupling capacitor C2 should not be omitted C2 must be positioned as close as possible to the IC pins The distance should not be larger than 5cm Note2 If the cutrent of the infrared emission diode D1 is particularly large the
18. ssipation idle current less than 1uAQ3V lt gt Data stored in RAM can be maintained for more than 24 hours CONDITION supply voltage is higher than 0 7V lt gt Serial programming interface circuit lt gt Protecting program memory data Operating voltage range 2 0 5 5V External oscillating mode 1 8 5 5V Internal oscillating mode lt gt Package type SOP20 300mil SOP16 150mil Shanghai Sinosun Microelectronics Ca Ltd page 3 of 22 485 sinesun we muB 1 2 Block Diagram IROUT 1 3 Pin Assignment GND OSCI PCO OSCO PC1 PAO PAL PA2 VPP PBO PA3 PA4 PA5 GND OSCI PCO OSCO PC1 PAO PA1 PA2 VPP PBO PA3 MC10P5010 User Manual V1 3 P 7 0 VDD IROUT PB7 PB6 PB5 PB4 PB3 PB2 PA7 PA6 00 JO 0 WN EE m o SOP20 300mi I SOP16 150mi 1 Shanghai Sinosun Microelectronics Ca Ltd page 4 of 22 485 sinesun L muB MC10P5010 User Manual V1 3 1 4 Pin Description Name Direction Function Description OSCI PCO I O External Oscillator GPIO while configured as internal RC mode OSCO PC1 I O External Oscillator GPIO while configured as internal RC mode GND P Ground VDD P Source Programming high voltage input GPIO pull up tesistot selectable keyboard interrupt can VPP PBO 1 gr g high voltage inpu pul up y P be triggered PB2 PB7 I O GPIO pull up resistor selectable PAO PA7 I O GPIO pu
19. t O PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PAO R W R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 BIT 7 0 PAn PA Data register n 7 0 04 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O DDRA DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRAO R W R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 BIT 7 0 DDRAn PA Direction register n 7 0 0 Configured to input 1 Configured to output 01 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O PB PB7 PB6 PB5 PB4 PB3 PB2 PBO R W R W R W R W R W R W R W R Initial Value 0 0 0 0 0 0 5 0 BIT 7 2 PBn PB Data register n 7 2 BIT 0 PBO PBO Data bit it is read only bit because PBO is always input 05 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DDRB DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 KBEBO R W RAN RAN RAN RAN RAN RAN RAN Initial Value 0 0 0 0 0 0 0 BIT 7 2 DDRBn PB Direction register n 7 2 Shanghai Sinasun Micvaetectranics Ca Ltd page 8 of 22 RI ERF 485 sinesun w MC10P5010 User Manual V1 3 0 Configured to input l Configured to output 0C Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MCR KBIE KBIC PBP PBP3 PBP2 OUTC FCAE R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 PBP PB7 PB4 pull up selection 0 PB7 PB4 s 25Kohm pull up is disconnected 1 PB7 PB4 s 25Kohm pull up is connected the port must be configured to input BIT 4 BIT
20. t request occur lt gt Any type of system reset occurs While MCU works under WAIT mode activities of CPU stop but the system primary oscillator still works so the power dissipation is lower than under normal mode Shanghai Sinosun Micraetectianics Ca Ltd page 15 of 22 SINSsun 9 Electrical Specification 9 1 Absolute Rating FERIIS fri cB MC10P5010 User Manual V1 3 Rating Symbol Value Unit Supply Voltage VDD 0 3 6 5 V Input Voltage VIN VSS 0 3 VDD 0 3 V Operating Temperature TA 4085 Storage Temperature Tstg 65 150 9 2 DC Electrical Characteristics VDD 3V T 25C Characteristics Symbol Pin Condition Min Typ Max Unit i External Oscillating 2 0 5 5 V Operating Voltage VDD Internal Oscillating 1 8 5 25 V Input Leakage Current V leak All input ports VIN VDD 0 iai uA Input High Voltage Vin All input ports 0 7VDD VDD V Input Low Voltage Vi All input ports 0 0 2VDD V PA7 PAO Pull up Resistance Ru 10 25 50 Kohm PB7 PB2 Pull up Resistance Ro PBO 30 50 80 Kohm PA7 PAO PB7 PB2 Output High Current Ton Von 2 7V 3 5 mA PC1 PCO IROUT PA7 PAO Output Low Current Ton PB7 PB2 V 0 3V 10 14 mA PC1 PCO Output Low Curtent Lo IROUT Va 1 5V 300 400 mA VDD 3V Idle Supply Current la VDD 0 1 1 uA in STOP mode VDD 3V Dynamic Supply Current lac VDD 3 mA no load LVR Voltage Vive T 20C 70C 1 15 1 4 1 65 V
21. tion is enabled 1 Protection is disabled BIT 5 PBPO PBO pull up enable bit 0 PBO 50Kohm pull up resistor is disabled 1 PBO 50Kohm pull up resistor is enabled BIT 4 IRPO IROUT logic selection 0 IROUT outputs negative logic 1 IROUT outputs positive logic BIT 3 RCEN Internal RC External OSC selection 0 External OSC mode 1 Internal RC mode BIT 2 0 FC 2 0 Carrier wave frequency selection 000 Carrier frequency is 1 6 of system frequency about 38KHz Fosc 455KHz 001 Carrier frequency is 1 36 of system frequency about 56KHz Fosc 4MHz 010 Carrier frequency is 1 50 of system frequency about 40KHz Fosc 4MHz 011 Carrier frequency is 1 53 of system frequency about 38KHz Fosc 4MHz 100 Carrier frequency is 1 56 of system frequency about 36KHz Fosc 4MHz system frequency about 33KHz Fosc 4MHz system frequency about 31 5KHz Fosc 4MHz system frequency about 27KHz Fosc 4MHz 101 Carrier frequency is 1 61 110 Carrier frequency is 1 64 111 Carrier frequency is 1 74 2 6 Control Registers All the registers of MC10P5010 are listed below Detail functions of these registers are described in the following contents Address Name R W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit 1 Bit 0 202618 00 PA R W PA7 PA6 PA5 PA4 PA3 PA2 PA1 PAO 0000 0000 01 PB RW PB7 PB6 PB5 PB4 PB3 PB2 PBO 0000 00 0 04 DDRA R W DD
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