MF644 User`s Manual
Contents
1. MF 644 MULTIFUNCTION I O DEVICE USER S MANUAL HUMUSOFT COPYRIGHT 2014 by HUMUSOFT s r o All rights reserved No part of this publication may be reproduced or distributed in any form or by any means or stored in a database or retrieval system without the prior written consent of HUMUSOFT 5 Limited Warranty HUMUSOFT s r o disclaims all liability for any direct or indirect damages caused by use or misuse of the MF 644 device or this documentation HUMUSOFT is a registered trademark of HUMUSOFT s r o Other brand and product names are trademarks or registered trademarks of their respective holders Printed in Czech Republic Table of Contents 1 Introduction 1 1 General Description 2 Features LIST entree ene 1 3 Specifications 1 3 1 A D 1 3 2 D A 1 3 3 Digital 1 3 4 Digital Outputs 1 3 5 Quadrature Encoder Inputs 1 3 6 Counters Timers 2 Installation 2 1 Hardware Installation 2 2 Software Installation on Windows 3 Programming Guide 3 1 Register daca ene Gate dere 3 2 Register Description 3 3 A D Converter vespere m RU PIER D A Converters oc sexe et er a 32. bits BADRO PCI Express chipset interrupts status 512 32 memory mapped bits special functions BADRI A D D A digital O 128 16 32 memory mapped BADR2 Counter timer chip 128 32 memory mapped Table 1 Base Address Regions PCI Express chipset PEX8311 and counter timer chip are located in 32 bit regions and should be accessed by 32 bit instructions BADR1 containing analog I O has 16 bit architecture and registers are naturally 16 bit wide but 32 bit access to this area is allowed as well under certain conditions 32 bit access is broken into two 16 bit cycles on the MF 644 internal bus This allows increasing throughput by accessing two consecutive internal 16 bit registers by single cycle Therefore two D A channels can be written or two A D channels can be read at once which increases speed of data transfers almost twice In BADRI do not use 32 bit access to other registers than ADDATA and DAO DAT Programming Guide Address Read BADRO 0x68 INTCSR 4 o N w gt O lt o B lt lt Address Read BADR1 0x00 ADDATA A D data BADR1 0x02 ADDATA A D data mirror BADR1 0x04 ADDATA A D data mirror BADR1 0x06 ADDATA A D data mirror BADR1 0x08 ADDATA A D data mirror BADRI 0x0A ADDATA A D data mirror BADRI 0x0C ADDATA A D data mirror BADRI 0x0E ADDATA A D data mirror BADR1 0x10 DIN Digital input BADR1 0x20 ADSTART A D SW trigger BADR1 0x22
3. BADR1 0x24 BADR1 0x26 BADR1 0x28 BADR1 0x2A BADR1 0x2C BADR1 0x2E o o w gt O Z lt o B lt lt r 6 INTCSR ADCTRL A D control Address Read BADR2 0x00 CTROSTATUS BADR2 0x04 CTRO BADR2 0x08 BADR2 0x10 CTRISTATUS BADR2 0x14 BADR2 0x18 BADR2 0x20 CTR2STATUS BADR2 0x24 CTR2 BADR2 0x28 BADR2 0x30 CTR3STATUS BADR2 0x34 CTR3 BADR2 0x38 BADR2 0x40 CTR4STATUS BADR2 0x44 CTR4 BADR2 0x48 BADR2 0x60 BADR2 0x68 GPIOC BADR2 0x6C IRCSTATUS BADR2 0x70 IRCO BADR2 0x74 BADR2 0x78 IRC2 BADR2 0x7C IRC3 RB gt G N lt B lt E Programming Guide 17 Programming Guide 3 2 Register Description INTCSR BADRO0 0x68 Interrupt Control Status Description Default R W Reserved 3 1 0 0 Internal PCI Wire Interrupt Enable 1 enables internal PCI Wire interrupts INTA Reserved Local Interrupt Input Enable 1 enables Local interrupt input LINTi assertion to assert the internal PCI Wire interrupt INTA Used in conjunction with Internal PCI Wire Interrupt Enable bit INTCSR 8 Deasserting LINTi also clears the interrupt Reserved Local Interrupt Input Active 1 indicates the Local interrupt input LINTi is active 0 3116 1 16 Reserved 0x0F01 Table 5 INTCSR Interrupt Control Status Register Format Programming
4. 5 Digital 3 6 Quadrature Encoder 3 7 Tim r Counter erc ep ves e 4 I O Signals 4 1 Output Connector Signal Description Table of Contents Introduction Introduction 1 Introduction 1 1 General Description The MF 644 multifunction I O device is designed for the need of connecting PC compatible computers to real world signals The MF 644 contains 8 channel fast 14 bit A D converter with simultaneous sample hold circuit 8 independent 14 bit D A converters 8 bit digital input port and 8 bit digital output port 4 quadrature encoder inputs with single ended or differential interface and 5 timers counters The device is designed for standard data acquisition and control applications and optimized for use with Real Time Windows Target for Simulink amp The MF 644 features fully 32 bit architecture for fast throughput 1 2 Features List The MF 644 offers following features 32 bit architecture 14 bit A D converter with simultaneous sample amp hold circuit conversion time 1 6 us for single channel 3 7 us for 8 channels 8 channel single ended fault protected input multiplexer input range 10 internal clock amp voltage reference 8 D A converters with 14 bit resolution and 10V output range 4 guadrature encoder inputs with single ended or differential interface Introduction software selectable digital input n
5. CTROMODE BADR2 0x00 Counter 0 Mode CTRIMODE BADR2 0x10 Counter 1 Mode CTR2MODE BADR2 0x20 Counter 2 Mode CTR3MODE BADR2 0x30 Counter 3 Mode CTR4MODE BADR2 0x40 Counter 4 Mode Bit Description Default E Count Direction 1 counts up 0 counts down i Repetition If 0 counter stops after terminal count If 1 counter reloads after terminal count and starts new cycle Load Toggle If 0 counter always reloads from register A on LP terminal count If 1 counter reloads alternately from A register or from B register depending on output toggle status Output Toggle If 0 counter output pin is connected to terminal count If 1 counter output is connected to output toggle which is inverted on every terminal count Output Control Controls output value and polarity 00 direct output 01 inverted output 10 force output low 11 force output high Trigger source Controls counter hardware trigger source 00 trigger disabled 01 trigger by counter input TxIN 10 trigger by counter n 1 output 11 trigger by counter n 1 output Trigger type Controls counter hardware trigger edge 00 trigger disabled 01 trigger by rising edge of trigger signal 10 trigger by falling edge of trigger signal 11 trigger by either edge of trigger signal Retrigger If 0 retrigger is disabled and counter can be triggered only when stopped If 1 counter can be retriggered when running Programming Guide Gate source Control
6. Guide ADCTRL BADR1 0x00 A D Control Bit Description Default 0 select 1 enables chanel 0 channel scan list CHI select 1 enables chanel 1 in channel scan list CH2 select 1 enables chanel 2 in channel scan list 3 CH3 select 1 enables chanel 3 in channel scan list 4 select 1 enables chanel 4 in channel scan list CHS select 1 enables chanel 5 in channel scan list CH6 select 1 enables chanel 6 in channel scan list CH7 select 1 enables chanel 7 in channel scan list Reserved 0x00 Table 6 ADCTRL A D Control Register Format 19 Programming Guide ADDATA BADR1 0x00 A D Data R Description A D Data Reads data from A D Data is valid after EOLC bit in GPIOC goes low Data from channels selected in ADCTRL register are available in FIFO lower number channels first 15 14 Reserved N A Table 7 ADDATA A D DATA Register Format Note ADDATA register has 7 mirror registers located from BADR1 0x02 to BADRI1 0x0E This arrangement remaps FIFO to linear address space and allows reading consecutive values from A D FIFO by 32 bit instructions DIN BADR1 0x10 Digital Input R Bit Deseription Default Digital input 7 0 Reads digital input port Reserved N A Table 8 DIN Digital Input Register Format DOUT BADR1 0x10 Digital Output Bit Description Default Digital output 7 0 Writes to digital output port H Reserved N A
7. and Signal Processing Controller Device type Other devices Manufacturer Unknown Location PCI bus 14 device 4 function 0 Device status The drivers for this device are not installed Code 28 There is no driver selected for the device information set or element To find a driverforthis device click Update Driver Click on Update Driver button 11 Hardware Installation How do you want to search for driver software gt Search automatically for updated driver software Windows will search your computer and the Internet for the latest driver software for your device unless you ve disabled this feature in your device installation B Browse my computer for driver software Locate and install driver software manually Click on Browse my computer for driver software button Browse for driver software on your computer Search for driver software in this location CAHUDAOLIB V Include subfolders Let me pick from a list of device drivers on my computer This list will show installed driver software compatible with the device and all driver software in the same category as the device When prompted for driver location type path to driver files or select driver 12 Hardware Installation location using Browse button and click Nexr Would you like to install this device software Publisher Humusoft s r o Name Humusoft Data Acquisition Devices Always tru
8. from Load A or Load B register CTRIRESET Writing 1 resets counter 1 CTRIRESET Writing 1 resets counter 1 1 resets counter 1 CTRITSET Writing 1 sets counter 1 output toggle register CTRITRESET Writing 1 resets counter output toggle register 12 CTR2START Writing starts counter 2 za CTR2STOP Writing 1 stops counter 2 CTR2LOAD Writing 1 loads counter 2 from Load A or Load B register 15 CTR2RESET Writing 1 resets counter 2 0 18 CTR3START Writing starts counter 3 0 19 CTR3STOP Writing 1 stops counter 3 0 5d CTR3LOAD Writing 1 loads counter 3 from Load A or Load B register CTR3RESET Writing 1 resets counter 3 Programming Guide 22 CTR3TSET Writing 1 sets counter 3 output toggle register 0 CTR3TRESET Writing 1 resets counter 3 output toggle register CTRASTART Writing 1 starts counter 4 CTR4STOP Writing 1 stops counter 4 jE CTR4LOAD Writing 1 loads counter 4 from Load A or 6 Load register 27 CTR4RESET Writing 1 resets counter 4 0 CTRATSET Writing 1 sets counter 4 output toggle register 29 CTR4TRESET Writing 1 resets counter 4 output toggle register Table 17 CTRXCTRL Common Counter Control Register Format Note Bits 29 0 are active by writing 1 Writing 0 to these bits is not necessary and has no action asigned 26 Programming Guide GPIOC BADR2 0x68 General Purpose I O Control it Description Default F
9. high 0 active low Connected to external trigger Table 18 GPIOC General Purpose I O Control Register Format Note Interrupts depends on INTCSR register at BADRO 0x68 28 Programming Guide IRCCTRL BADR2 0x6C IRC Conrol Register it Description Default 4 IRCOMODE Selects IRCO counter operation 00 IRC 4 edge detection 01 bidirectional counter rising edge 10 bidirectional counter falling edge 11 bidirectional counter either edge IRCOCOUNT count control 00 IRCO count enabled 01 IRCO count disabled 10 count enabled if 10 input is 0 11 IRCO count enabled if 10 input is 1 IRCORESET IRCO reset control 000 IRCO reset disabled 001 IRCO reset 010 IRCO reset if IO is 0 011 IRCO reset if IO is 1 100 IRCO reset by rising edge of 10 101 IRCO reset by falling edge of 10 110 IRCO reset by either edge of IO 111 Reserved IRCOFILTER IRCO digital filter control 1 enables digital filter on IRCO inputs 0 disables filtering 11 10 IRCICOUNT IRCI count control See IRCOCOUNT 0 14 12 IRCIRESET reset control See IRCORESET 0 IRCIFILTER IRCI digital filter control 1 enables digital filter on IRC1 inputs 0 disables filtering 17 16 IRC2MODE Selects IRC2 counter operation See i IRCOMODE 19 18 IRC2COUNT IRC2 count control See IRCOCOUNT 0 IRC2RESET IRC2 reset control See IRCORESET 29 Programming Guide IRC2FILTER IRC2 digital fi
10. register Each A D channel has one bit in ADCTRL Setting this bit includes the channel in conversion scan list Conversion can be initiated by a read operation from ADSTART register by timer counter 4 or by external trigger Once the conversion is started selected channels are simultaneously sampled and converted When the conversion of all selected channels is complete EOLC bit 17 in GPIOC register is set low which means that converted data is available in output FIFO and can be read from ADDATA register EOLC remains low until next conversion is started Starting new conversion resets FIFO A D conversion can be triggered also by timer 4 output or by external trigger input according to setting of ADTRIGSRC bit 30 in CTRAMODE register These signals can also generate interrupt according to setting of CTRAINTSRC bit 31 in CTR4MODE register 31 Programming Guide A D converter has fixed input range 10V and uses two s complement binary coding A D converter zero offset can be adjusted by R23 A D gain can be adjusted by R25 Ox3FFF Digital Value Analog Voltage 0 0012 V 0x2000 10 0000 V Ox1 FFF 9 9988 V 0x0000 0 0000 V Table 22 A D Inputs Coding 3 4 D A Converters D A converters are accessed through eight data input latch registers DAO DA7 D A converter outputs are initially connected GPIOC register is set to 1 This bit can be used from D A converters Data from D A input to gro
11. to approve connected Thunderbolt device on some platforms Hardware Installation The following Thunderbolt device chain has been plugged in and one or more devices require your permission to connect to this system Select the devices you wish to connect Sonnet Technologies Inc Echo ExpressC 4 Always Connect M Note Selecting Do Not Connect will prevent that device and all devices further down the chain from being used on the system Select Always Connect and click on OK button This figure serves only as an example It can look different on your platform Once the device has been approved open the Device Manager In the Other devices group there is a new PCI Data Acquisition and signal Processing Controller device Hardware Installation mitis Rs 4 4 Computer gt 484 Computer gt Disk drives gt 88 Display adapters gt 8 DVD CD ROM drives b Human Interface Devices gt lt lt IDE ATA ATAPI controllers pcm Keyboards b A Mice and other pointing devices D Monitors p ij Multifunction adapters p amp Network adapters 4 jo Other devices ig PCI Data Acquisition and Signal Processing Controller gt 2 Ports COM amp LPT p Processors b Sound video and game controllers p 484 System devices p 9 Universal Serial Bus controllers Double click on this new found device The Properties window will open 10 Hardware Installation n PCI Data Acquisition
12. 0 Data Counter 1 Data Counter 2 Data Counter 3 Data Counter 4 Data ARR A Description Default Counter Data Reads current contents of counter uw Table 14 CTRx Counter Data Register Format CTR0A BADR2 0x04 Counter 0 Load A W CTRIA BADR2 0x14 Counter 1 Load A W CTR2A BADR2 0x24 Counter 2 Load A W CTR3A BADR2 0x34 Counter 3 Load A W CTR4A BADR2 0x44 Counter 4 Load A W Description Default Counter Load A Counter load register A Table 15 Counter Load Register Format CTROB BADR2 0x08 Counter 0 Load B W CTR1B BADR2 0x18 Counter 1 Load B W CTR2B BADR2 0x28 Counter 2 Load B W CTR3B BADR2 0x38 Counter 3 Load B W Bit Description Default Counter Load B Counter load register Table 16 CTRxB Counter Load B Register Format Note Counter 4 does not have Load B register and is always being loaded from Load A register 24 Programming Guide CTRXCTRL BADRISEEGU 3 Counter Conrol Register Bit Description Default 5 E CTROSTART Writing starts counter 0 CTROSTOP Writing 1 stops counter 0 CTROLOAD Writing 1 loads counter 0 from Load A or Load B register CTRORESET Writing 1 resets counter 0 CTROTSET Writing 1 sets counter 0 output toggle register NEC CTROTRESET Writing 1 resets counter 0 output toggle register CTRISTART Writing 1 starts counter 1 CTRISTOP Writing 1 stops counter 1 CTRILOAD Writing 1 loads counter 1
13. Firmware ID Read only DINT Status 1 indicates interrupt active 0 indicates not active Read only ADINT Enable 1 enables A D interrupt 0 disables A D interrupt ADINT Select Edge 1 indicates edge triggered 0 indicates level triggered interrupt ADINT Polarity 1 active high 0 active low Connected to EOLC of A D converter should be set to active low for normal operation CTRAINT Status 1 indicates interrupt active 0 indicates interrupt not active CTR4INT Enable 1 enables counter 4 interrupt 0 disables counter 4 interrupt CTRAINT Select Edge indicates edge triggered 0 indicates level triggered interrupt CTRAINT Polarity active high 0 active low Connected to counter 4 output EOLC Reads EOLC end of last conversion bit of A D 17 converter Active low 0 when all channels converted 1 0 during A D conversion 22 18 Reserved 0 LDAC Load D A converters active low Writing 0 makes D A latches transparent 1 holds D A outputs Can be used for simultaneous update of analog outputs EXTINT Status 1 indicates interrupt active 0 indicates interrupt not active Read only EXTINT Enable 1 enables counter 4 interrupt 0 disables external trigger interrupt DACEN 1 enables D A outputs 0 forces OV to all D A 27 Programming Guide EXTINT Select Edge 1 indicates edge triggered 0 indicates level triggered interrupt EXTINT Polarity active
14. RIG IRCIA 27 ry 28 T IRCIB IRC1I 11 F 30 TOIN IRCII 31 TOOUT IRC2A 13 1 32 IRC2A 33 TIOUT IRC2B 15 al 34 2 IRC2B 35 T20UT IRC2I 17 ma o je 36 en o 18 T30UT 19 r 25 X2 Connector Pin Assignement 37 Contact Address Contact address HUMUSOFT s r o Pob e n 20 186 00 Praha 8 Czech Republic tel 420 2 84011730 tel fax 420 2 84011740 E mail info humusoft com Homepage http www humusoft com 38
15. Table 9 DOUT Digital Output Register Format ADSTART BADR1 0x20 A D Conversion Start Bit Description Default A D Conversion Start Reading this register triggers A D ell conversion for all channels selected in ADCTRL Table 10 ADSTART A D Conversion Start Register Format 20 Programming Guide DAO BADR1 0x20 D A Converter 0 W BADR1 0x22 D A Converter 1 W DA2 BADR1 0x24 D A Converter 2 W DA3 BADR1 0x26 D A Converter 3 W DA4 BADR1 0x28 D A Converter 4 W DAS BADR1 0x2A D A Converter 5 W DA6 BADR1 0x2C D A Converter 6 W DA7 BADR1 0x2E D A Converter 7 W Description Default DAx D A converter channel n data 0x3FFF Reserved N A Table 11 DAx D A Converter Data Register Format Note D A converter outputs are updated only if LDAC bit in GPIOC registrer is set low bit 23 at BADR2 0x68 0 Otherwise D A outputs are keeping old values and data written to DAn registers are kept until LDAC goes low LDAC bit can be used for simultaneous update of D A outputs CTROSTATUS BADR2 0x00 Counter 0 Status CTRISTATUS BADR2 0x10 Counter 1 Status CTR2STATUS BADR2 0x20 Counter 2 Status CTR3STATUS BADR2 0x30 Counter 3 Status CTR4STATUS BADR2 0x40 Counter 4 Status Description Default EM Counter Running 1 if counter is running 0 if stopped 1 Counter Output Reads counter toggle output 0 Table 12 CTRxSTATUS Counter Status Register Format 21 Programming Guide
16. case of single ended encoder outputs use signal inputs and leave inputs disconnected If differential encoder outputs are used connect both and inputs of the MF 644 to encoder outputs In both cases connect encoder signal ground to GND on X2 connector of the MF 644 Each IRC channel has one 32 bit data register IRCO IRC3 Control and status 33 Programming Guide registers IRCCTRL and IRCSTATUS common for all IRC channels Each IRC counter can be switched to bidirectional counter mode In such case A is clock input and B controls direction 1 up 0 down In IRC and counter modes counter reset can be controlled by I input 3 7 Timer Counter The MF 644 contains 5 timers counters with 50 MHz clock The first four timers are accessible through external connector X2 while the fifth timer can generate device interrupt or trigger A D conversion or can be used as a clock source for other timers or for similar internal functions TxIN pin on I O connector can serve either as clock gate or trigger input depending on configuration Inputs and outputs are TTL compatible Schmitt triggers are at all inputs to improve noise immunity Counters are implemented in programmable gate array chip offering wide range of operation modes allowing up down binary counting internal or external clock and gate sources prescaling one shot continuous outputs software external triggering programmable gate and outpu
17. ll outputs at Logic 1 Introduction 1 3 5 Ouadrature Encoder Inputs Number of axes Resolution Counter modes Index input Inputs Input noise filter Input freguency 4 independent 32 bits guadrature X4 or up down counter programmable differential with Schmitt triggers digital programmable 0 3 us max 2 5 MHz 1 3 6 Counters Timers Counter chip Number of channels Resolution Clock frequency Counter modes Triggering Clock source Inputs Outputs custom 5 4 of them available on I O connector one used for A D triggering and interrupt 32 bits 50 MHZ up down binary software external internal prescalers external TTL Schmitt triggers TTL Hardware Installation 2 Installation 2 1 Hardware Installation The MF 644 multifunction I O device is connected to computer through Thunderbolt interface It can be connected into any free Thunderbolt port Follow the steps outlined below Find empty Thunderbolt connector in your computer Use supplied Thunderbolt cable to connect 644 device to your computer Check the status of green LED diode which is placed next to the MF 644 Thunderbolt connector If the LED is on the MF 644 is powered and ready to use 2 2 Software Installation on Windows Once you have connected the MF 644 device to your computer you can install Windows driver Follow the steps outlined below It may be necessary
18. lter control 1 enables digital filter on IRC2 inputs 0 disables filtering IRC3MODE Selects IRC3 counter operation See IRCOMODE 2726 26 IRC3COUNT IRC3 count control See IRCOCOUNT IRC3 count control IRC3COUNT IRC3 count control See IRCOCOUNT IRCOCOUNT IRC3RESET IRC3 reset control See IRCORESET 31 IRC3FILTER IRC3 digital filter control 1 enables digital filter on IRC3 inputs 0 disables filtering Table 19 IRCCTRL IRC Control Register Format Note Digital filter on IRC inputs is a low pass filter improving noise immunity The filter also decreases maximum input frequency and signal changes shorter than 320 ns are ignored IRCSTATUS BADR2 0x6C IRC Status Register R Bit Description Default ELEM IRCOINDEX Reads 10 input Reserved N A 8 IRCIINDEX Reads II input 1 EET IRC2INDEX Reads I3 input 23 17 Reserved 24 IRC3INDEX Reads I3 input 1 Table 20 IRCSTATUS IRC Status Register Format 30 Programming Guide IRCO BADR2 0x70 0 Data Register IRCI BADR2 0x74 IRCI Data Register R IRC2 BADR2 0x78 IRC2 Data Register IRC3 BADR2 0x7C IRC3 Data Register Description Default IRCx Reads data from IRC counter Table 21 IRCx IRCx Data Register Format 3 3 A D Converter A D converter is controlled through ADDATA ADCTRL ADSTART and GPIOC registers Before starting a conversion it is necessary to configure channels which will be converted by ADCTRL
19. oise filter 0 3 us guadrature input freguency up to 2 5 MHz software selectable index pulse operation 4 channel 32 timer counter with 20 ns resolution 8 bit TTL compatible digital input port 8 bit TTL compatible digital output port interrupt reguires one Thunderbolt connector Thunderbolt endpoint device powered from Thunderbolt interface 1 3 Specifications 1 3 1 A D Converter Resolution Number of channels Sample hold circuit Conversion time FIFO Input ranges Input protection Input impedance 14 bits 8 single ended simultaneous sampling of all channels 1 6 us single channel 1 9 us 2 channels 2 5 us 4 channels 3 7 us 8 channels 8 entries one conversion cycle 10V 18V gt 10 Ohm Introduction 1 3 2 D A Converter Resolution Number of channels Settling time Slew Rate Short output circuit current Resistive Load Capacitive Load DC output impedance Differential nonlinearity 14 bit 8 max 31 us full scale swing 1 2 LSB 10 V us 15 mA min 5 kOhm max 50 pF max 0 5 Ohm 1 LSB 1 3 3 Digital Inputs Number of bits 8 Input signal levels TTL Logic 0 0 8 V max Logic 1 2 0 V min 1 3 4 Digital Outputs Number of bits 8 Output signal levels TTL Logic 0 Logic 1 0 5 V max 25 mA sink 50 mA total load for all outputs at Logic 0 2 0 V min 25 mA source 50 mA total load for a
20. s counter hardware gate source 00 gate set high 01 counter gated by counter input TxIN 10 counter gated by counter 1 output 11 counter gated by counter n 1 output Gate polarity Selects value of gate input which disables counting If set to 0 low level of gate signal disables counting If set to 1 high level of gate signal disables counting Clock source Selects counter clock source 0000 50 MHz internal clock 0001 10 MHz internal clock 0010 1 MHz internal clock 0011 100 kHz internal clock 0100 reserved 0101 counter input TxIN rising edge 0110 counter input TxIN falling edge 0111 counter input TxIN either edge 1000 reserved 1001 counter n 1 output rising edge 1010 counter n 1 output falling edge 1011 counter n 1 output either edge 1100 reserved 1101 counter n 1 output rising edge 1110 counter n 1 output falling edge 1111 counter n 1 output either edge ADTRIGSRC A D trigger source 0 triggers by falling edge of external trigger input 1 triggers by falling edge of counter 4 output Implemented in CTRAMODE register only CTR4INTSRC Interrupt signal source 0 interrupts by falling edge of external trigger input 1 interrupts by falling edge of counter 4 output Implemented in CTRAMODE register only 23 Programming Guide Table 13 CTRxMODE Counter Mode Register Format CTRO CTR2 CTR3 CTR4 BADR2 0x04 BADR2 0x14 BADR2 0x24 BADR2 0x34 BADR2 0x44 Counter
21. st software from Humusoft s r o Install You should only install driver software from publishers you trust How I decide which device software is safe to install Click on Install button in Windows Security window Windows has successfully updated your driver software Windows has finished installing the driver software for this device m Humusoft MF644 13 Hardware Installation Click on Close button To complete the installation process of the MF 644 multifunction I O device you have to reconnect the device disconnect the Thunderbolt cable from your computer and connect it back after a while r EB S 19 2 RS 4 34 Computer gt 4M Computer Data Acquisition Devices gt a Disk drives gt k Display adapters b DVD CD ROM drives p 85 Human Interface Devices gt C IDE ATA ATAPI controllers pm Keyboards D JA Mice and other pointing devices gt Ai Monitors gt Multifunction adapters gt EP Network adapters p 197 Ports COM amp LPT D Processors gt j Sound video and game controllers gt iil System devices p Universal Serial Bus controllers Device Manager after successful driver installation 14 Programming Guide 3 Programming Guide 3 1 Register Map The MF 644 uses Vendor ID 0x186C and Device ID 0x0644 Registers of the MF 644 device are located in 3 memory mapped regions Region Function Size Width bytes
22. t polarities pulse counting freguency measurement pulse generation including PWM programmable clock source 34 Signals 4 I O Signals 4 1 Output Connector Signal Description The MF 644 multifunction I O device is equipped with two on board 37 pin D type female connectors X1 and X2 For pin assignment refer to Tables 24 and 25 TB 640 Terminal Board can be connected to both connectors AD0 AD7 DA0 DA7 DINO DIN7 DOUTO DOUT7 IRCO IRC3 TOIN T3IN TOOUT T3OUT TRIG 5V AGND GND Analog inputs Analog outputs TTL compatible digital inputs TTL compatible digital outputs Quadrature encoder A B and Index inputs Timer counter gate and clock inputs Timer counter outputs A D converter external trigger input 5V 0 2A power supply Analog ground Digital ground 35 I O Signals 20 DAO AD2 75 22 DA2 AD4 I 24 DA4 AD6 7 i eo 26 AD7 8 27 AGND 28 V 29 GND DA7 11 OS 30 DOUTO DINO 12 31 DOUTI DINI 13 CES 32 DOUT2 DIN2 14 33 DOUT3 DIN3 15 34 DOUT4 DIN4 16 35 DOUTS DINS 17 pw Je 36 2 18 DOUT7 19 rm 24 X1 Connector Pin Assignement 36 Signals 20 IRC3A IRCOA IRCOB baa 22 IRC3B IRCOB 23 IRC3B IRCOI 24 IRC3I IRCOI 25 IRC3I 26 T
23. und until DACEN bit 26 in to disconnecting all analog outputs latch registers are passed to D A converters only if LDAC bit 23 in GPIOC register is 0 If this bit is set to 1 data remains just in input latches without being written to D A converters Then if LDAC is set to 0 all D A outputs are update registers d simultaneously from input latch Output voltage ranges of D A converters are 4 used After power on or hardware reset the converter positive range can be adjusted by adjusted by R8 32 ELOV and straight binary coding is output voltage is set to OV D A RS while negative range can be Programming Guide Digital Value Analog Voltage 0x3FFF 9 9988 V 0x2000 0 0000 V Ox1 FFF 0 0012 V 0x0000 10 0000 V Table 23 D A Outputs Coding 3 5 Digital The MF 644 contains one 8 bit digital input port and one 8 bit digital output port Digital input port can be accessed directly by read from DIN register Inputs are TTL compatible Digital output port can be accessed by byte or word write to DOUT register Outputs are TTL compatible After power on or hardware reset digital outputs are set to 0 3 6 Ouadrature Encoder Inputs The MF 644 contains four guadrature encoder inputs with single ended or differential interface and index inputs Inputs are differential TTL compatible with Schmitt triggers The MF 644 can be used either with single ended or differential encoder outputs In
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