Using DMACII (Chained Transfer)
Contents
1. Typical operation of a chain transfer in cases where the INTO interrupt is used as the cause of DMACII 1 When initialized MOD COUNT SADR DADR CADRO CADR1 MOD COUNT SADR DADR CADRO CADR1 2 When first DMACII request INTO interrupt occurs After a DMACII transfer the COUNT value is decremented by 1 Furthermore if the source of transfer and the destination of transfer are variable the SADR and DADR values are incremented by 1 for 8 bit transfers or incremented by 2 for 16 bit transfers 2000h 2001h transfer 2800h 3000h 3001h At the start of a DMACII index located at the address 0400h determines the operation of the transfer performed 2000h the DMACII 2001h DMACII transfer 2800h 3000h 3001h EEh XXh 3800h INTO interrupt vector 28th entry of a relocatable vector table 3 When second DMACII request INTO interrupt occurs MOD COUNT SADR DADR CADRO CADR1 MOD COUNT SADR DADR CADRO CADR1 j DMACII transfer 2000h 2001h 2800h 3000h 3001h 3800h 22h FFn EER xx osoon 4 The above applies to the following settings SIZE bit 1 8 bits transfer INTO interrupt vector 28th entry of a relocatable vector table UPDS bit 1 transfer source direction forward address UPDD bit 0 transfer destination direction fixed address 3800h INTO i2. ingle transfer Yi Burst Transfer single ANSE Burst transfer Interrupts not used Yes End of Transfer Interrupt ue Interrupts used 3 2 DMAC II Index When chain transfers are used the DMACII index has 4 bytes of CADR1 CADRO chain transfer addresses added The total number of bytes that comprise the DMACII index is 12 unless end of transfer interrupt is used Be sureto create as many DMACII indices as the number of times a chain transfer is to be performed TheDMAC II index must be located on the RAM area Beginning address of DMACII index BASE BASE 2 Transfer mode Transfer counter BASE 4 Transfer source address BASE 6 Transfer destination address BASE 8 BASE 10 Chained transfer address Figure 2 DMAC II Index REJ05B0640 0100 Rev 1 00 May 2005 Page 3 of 11 434 NE SAS M320 80 Series Using DMACII Chained Transfer 3 3 DMAC II Transfer The interrupt requests from all peripheral functions whose ILVL2 ILVLO bits in the interrupt control register have been set to 111b constitute the cause of requests to DMAC II In this application note the INTO interrupt is used for the cause of DMAC II request 3 4 Setting Up the Relocatable Vector Table Therelocatable vector tables must be located on the RAM area During a chain transfer when COUNT transfer counter reaches 0 the peripheral function interrupt vector that constitutes the cause of a DMACII request changes to the CADR1 CADRO value of the D
3. 00000b MULT Multiple Transfer Select Bit 0 Multiple transfer not used 5 Transfer count COUNT b15 bo Set the number of times transferred REJ05B0640 0100 Rev 1 00 May 2005 Page 5 of 11 RENESAS M320 80 Series Using DMACII Chained Transfer 6 Transfer source address SADR b15 b0 16 bits Set the source address of transfer 7 Transfer destination address DADR b15 bo 16 bits Set the destination address of transfer When COUNT reaches 0 the peripheral 8 Chained transfer address CADR function interrupt vector that constitutes the b31 b0 cause of a DMACII request changes to the CADR value Set the beginning address of the DMACII index to which the transfer is chained 9 RLVL register b7 b0 O0000NNE RLVL2to RLVLO Stop Wait Mode Exit Minimum Interrupt Priority Level Control Bit FSIT High Speed Interrupt Set Bit Set to 0 DMAC II and high speed interrupts cannot be Nothing is assigned 9 3 used at the same time Set to 0 DMAII DMAC II Select Bit Set to 1 s Nothing is assigned Set to 00b 10 Interrupt Control Register set all interrupt request registers for the interrupts to be used as the cause of DMAC II requests ILVL2 to ILVLO Interrupt Priority Level Select Bit Set to 111b Set the priority level of the interrupt used as IR Interrupt Request Bit ne cause of DMAC II re
4. MACII index REJ05B0640 01 00 Rev 1 00 May 2005 Page 4 of 11 RENESAS M320 80 Series Using DMACII Chained Transfer 3 5 Register Setting To enable the operation defined in Section 3 Detailed description the following register settings must be taken place step by step For detail configuration of each register please refer to M32C 80 Series HARDWARE MANUAL 1 Interrupt disable Set flag to O 2 Create a relocatable vector table Create a relocatable vector table in the RAM 3 Interrupt table register Set the beginning address of the relocatable vector table located in the RAM 4 Transfer mode MOD b15 b8 b7 bo For 4 through 8 create as many DMACII indices as the 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 number of times a chain transfer is to be performed SIZE Transfer Unit Select Bit 0 8 bits 1 16 bits IMM Transfer Data Select Bit 0 Immediate data 1 Memory UPDS Transfer Source Direction Select Bit 0 Fixed address 1 Forward address UPDD Transfer Destination Direction Select Bit 0 Fixed address 1 Forward address OPER Calculation Transfer Function Select Bit 0 Not used BRST Burst Transfer Select Bit 0 Single transfer INTE End of Transfer Interrupt Select Bit 0 Interrupt not used CHAIN Chained Transfer Select Bit 1 Use chained transfer Nothing is assigned Set to 00
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6. Transfer Destination Fixed Calculation Transfer None Burst Transfer Single Interrupt None uf Chained Transfer Have ZS Multiple Transfer None x dm index 0 count 5 number of transfer 5 dm index 0 sadr datal Source of transfer beginning address of the data array dm index 0 dadr amp destl Destination of transfer destl dm index 0 cadr amp dm index 1 REJ05B0640 01 00 Rev 1 00 May 2005 Page 7 of 11 434 NE SAS M32C 80 Series Using DMACII Chained Transfer dm index 1 mod mod word 0x0006 Transfer Unit 8bit Transfer Data Memory Transfer Source Forward Transfer Destination Fixed Calculation Transfer None Burst Transfer Single Interrupt None a Chained Transfer None f Multiple Transfer None dm index 1 count 5 number of transfer 5 dm index 1 sadr data2 Source of transfer beginning address of the data array dm index 1 dadr amp dest2 Destination of transfer dest2 dm index 1 cadr amp dm index 0 Set the interrupt used for DMAC II rlvl 0x20 Interrupt priority level 7 is used for DMAC II transfers intOic 0x07 INTO interrupt level 7 used for DMACII while 1 4 2 Relocatable Vector Tables Section vector ROMDATA variable vector table org VECTOR ADR lword dummy int BRK software int 0 lword dummy int lwo
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8. ar medical aerospace nuclear or undersea repeater use The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials If these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of Japan and or the country of destination is prohibited Please contact Renesas Technology Corporation for further details on these materials or the products contained therein REJ05B0640 0100 Rev 1 00 May 2005 Page 11 of 11
9. ave any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 434 NESAS APPLICATION NOTE M32C 80 Series Using DMACII Chained Transfer 1 Abstract This application note describes how to use DMACII in chained transfer 2 Introduction The explanation of this issue is applied to the following condition Applicable MCU M32C 80 Series This program can also be used when operating other microcomputers within the M 16C family provided they have DMACII function However some functions may have been modified Refer to the User s Manual for details Use functions covered in this Application Note only after careful evaluation 3 Detailed description The following explains an example use of DMACII transfer for the case where each time an interrupt request which has had its priority level set to 7 occurs data is transferred from memory to memory by a DMACII transfer and when a specified number of transfers has finished the transfer mode transfer count source of transfer address and destination of transfer address are changed Figure 1 shows a typical operation of a chained transfer mode REJ05B0640 0100 Rev 1 00 May 2005 Page 1 of 11 434 NESAS M32C 80 Series Using DMACII Chained Transfer
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13. nterrupt vector 28th entry 0400h of a relocatable vector table 4 When third DMACII request INTO interrupt occurs 400h When COUNT reached 0 the interrupt vector value for the cause of a DMACII transfer is rewritten to the value of CADR1 CADRO 800h 0086h MOD DADR CADRO 0000h CADR1 SADR 2000n Ti 2001h i DMACII transfer The DMACII index located at the address 800h determines the operation of the transfer performed 3800h FFh INTO interrupt vector 28th entry of a relocatable vector table OPER bit 0 without calculation transfer BRST bit 0 single transfer NTE bit 0 interrupt no used Figure 1 Typical Operation of a DMACII Chained Transfer Mode REJ05B0640 01 00 Rev 1 00 May 2005 Page 2 of 11 434 NE SAS M320 80 Series Using DMACII Chained Transfer 3 1 DMAC II Transfer Mode This application note example offers functions of chained transfer mode shown in Table 1 Table 1 Selectable Functions in Chained Transfer Mode Item Definition Selection T fer Block 8 bits Yes ransfer Bloc 16 bits Transfer Data EAIA dale Data in memory Yes Source Direction Fixed address Forward address Yes Fi r Yi Destination Direction Ked Address Forward address Calculation Transfer Without Calculation Transfer Yes Function Function With Calculation Transfer Function
14. on Select Bit har oper 1 Calculation Transfer Function Select Bit 1 1 CX Q 0c CE GGA Q jon w K brsti Burst Transfer Select Bit har inte End of Transfer Interrupt Select Bit har chain 1 Chained Transfer Select Bit har reserve 7 char mult 1 Multiple Transfer Select Bit mod_bit unsigned short mod_word mod unsigned short count Transfer count unsigned char near sadr Transfer source address char near dadr Transfer destination address struct DMACII_INDEX far cadr Chained transfer address jdm index 2 long ram vect 64 Relocatable vector table Transfer data array static unsigned char near datal 5 0x11 0x22 0x33 0x44 0x55 static unsigned char near data2 5 0xff 0xee 0xdd 0xcc 0xbb Transfer destination memory xy unsigned char near dest1 unsigned char near dest2 define S VECTOR unsigned long O0xfefd00 Relocatable vector address ORK IK RIK ke kk kc ke ke ke ke ke ke kk ke ke ke ke e e main Ey ORK IK ke kk ke kk ko ke ko ke ke ke ke kk ke kei ke ee e k void main void asm fclr it Ns Interrupt disable memcpy ram vect S VECTOR 64 4 Copy relocatable vector to RAM asm ldc 4 ram vect intb Set relocatable vector to RAM DMACII setting dm index 0 mod mod word 0x0086 Transfer Unit 8bit Transfer Data Memory Transfer Source Forward
15. quest to 7 Set to 0 POL Polarity Switch Bit INTOIC to INT5IC 0 Selects falling edge or L 1 Selects rising edge or H LVS Level Sensitive Edge Sensitive Switch Bit INTOIC to INTSIC 0 Edge sensitive 1 Level sensitive The POL and LVS bits are accommodated in the INTOIC Nothing is assigned INTSIC registers In other interrupt request registers set it Set to 00b Dx REJ05B0640 01 00 Rev 1 00 May 2005 Page 6 of 11 434 NE SAS M320 80 Series Using DMACII Chained Transfer 4 Example of a Sample Program 4 1 C language source KK I KR e RI KK Ck kk RR IR RRA IR IRA A IR II ARIA III IA ke kk ko k k kk ke k k FILENAME rej05b0640 src c Ner 1 00 FUNCTION DMACII Chained transfer KK II KK kk Ck I kCkCk kk kk kk KC Kk Ck kk kk kk k k Kk Ck kk k k kk k ke kk Ck kk k ke k k kc ko k k ke kk kc ke kk kkk k ke ek ke kk f ORK IK ko kk kc ke kk kc ke kk ke ke ke ke ke ke ke ke ke e e include file RK IKK kk kk kk kk kk ke ke kk ke kei ke ee ek include lt stdio h gt include lt string h gt include sfr32c83 h ORK IK RR ke kk kc IK ke ke ke ke ke ke ke I e e DMACII f ORK IKK kk kk kk ko ke kk ke kk kk ke ke ke ke ee e struct DMACII INDEX union struct char size 1 Transfer Unit Select Bit har imm 1 Transfer Data Select Bit har upds l Transfer Source Direction Select Bit har updd l Transfer Destination Directi
16. rd dummy int H lword dummy int 7 lword dummy int lword dummy int lword dummy int H lword dummy int H lword dummy int DMAO software int 8 P Omission r lword dummy int INT5 software int 26 lword dummy int INT4 software int 27 lword dummy int INT3 software int 28 lword dummy int INT2 software int 29 lword dummy int INT1 software int 30 glb dm index lword dm index INTO software int 31 lword dummy int TIMER B5 software int 32 r Omission rd r REJ05B0640 0100 Rev 1 00 May 2005 Page 8 of 11 RENESAS M320 80 Series Using DMACII Chained Transfer 5 Reference Renesas Technology Corporation Home Page http www renesas com E mail Support E mail csc renesas com Hardware Manual M 32C 80 Group Hardware M anual Use the latest version on the home page http www renesas com TECHNICAL UPDATE TECHNICAL NEWS Use the latest information on the home page http www renesas com REJ05B0640 01 00 Rev 1 00 May 2005 Page 9 of 11 434 NE SAS REVISION HISTORY M32C 80 Series Using DMACII Chained Transfer Rev Date Description Summary 1 00 2005 05 20 Page First edition issued REJ05B0640 01 00 Rev 1 00 May 2005 Page 10 of 11 434 NE SAS M320 80 Series Using DMACII Chained Transfer Keep safety first in your circuit designs Renesas Technology Corporation puts the maxi
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