FPGA Tools HOWTO - Connectivity Lab
Contents
1. Figure 28 Adding an existing file to the project Step 16 Next Left click on the next to the Compiler Options and Double click Linker Script We use a linker script to tell the compiler the linker technically where to put the software in memory The generate linker script dialog shows many different sections of the program and where they will be put in memory You don t have to understand what these sections mean just understand that they represent where parts of the program are stored in memory 7 Refer to figure 29 for the memory options THE BOOT PARTITIONS SHOULD BE LEFT IN BRAM 7 Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 Generate Linker Script Sections View Heap and Stack View Section Size bytes Memory Section Size bytes Memory text 0x00000404 DDR_SDRAM_6 Heap 0 1000 DDR_SDRAM_6 v odata 000000014 DDR_SDRAM_6 Stack 0x1000 DDR_SDRAM_I sdata2 0x00000000 DDR_SDRAM_6 sbss2 000000000 DDR_SDRAM_6 v data 000000118 DDR_SDRAM_6 fixup 0x00000000 DDR_SDRAM_6 sdata 0x0000000C DDR_SDRAM_6 Y Meran View sbss 000000008 DDR_SDRAM_6 v Memory Start Address Length bss 000002028 DDR_SDRAM_ IS DDR_SDRAM_64M 000000000 65536K boot0 000000010 plb_bram_if_cnth v plb_bram_if_cntl_1 OxFFFFOOOO 64K Add Section Delete Section Boot and Yector Sections Section Address Memory2. 19 Select the LEDs Step 8 Select 64 KB for the BRAM Make sure that you select a BRAM PPC will NOT work without BRAM 7 Click Next to Proceed to Software Setup Step 9 Reconfigure the software setup to match figure 20 Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 Base System Builder Software Setup Devices to use as standard input standard output and boot memory STDIN RS232_Uart STDOUT AS232_Uart v Boot Memory pib_brarn_if_critl_1 Sample application selection Select the sample C application that you would like to have generated Each application will imclude a linker script Memory test Illustrate system allveness and perform a basic read write test to each memory in your system Peripheral selftest Perform a simple self test for each peripheral in your system Below are other software applications found for your board In order to select an application please ensure your system satiety the requirements See More Details ML403 Cypress USB Application Figure 20 Deselect the Memory test and the Peripheral selftest Step 10 Click Generate to get the code and Finish to open the project in XPS Figure 21 shows the result Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007
3. for the specited frequency Processor configuration Debug IF Reset polarity CPU debug user pins only CPU debug and trace pins No debug On chip memory UCM Use BRAM Data lnstructior MONE w Cache setup Enable For optimal performance enable burst andor cacheline on memory Enable floating point unit FPL 2 Figure 18 Configuring the PPC Step 7 Refer to figures 19 configuring the first set of IO interfaces Select DDR_SDRAM_32M for set 2 but for the next two deselect everything Basically you deselect everything but the LED interface the UART Universal Asynchronous Receiver Transmitter you need the UART for console debugging and the DDR SDRAM Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 Base System Builder Configure IO Interfaces 1 of 4 The following external memor and I0 devices were found on your board ling Virtex 4 MLO Evaluation Plathorm Revision 1 Please select the IO devices which you would like to use IO devices RS232_Uart l Ferpheral OPE UARTLITE J Baudrate bits per seconds S600 wt Data bits m we Parity NONE Ww Use interrupt v LEDs_4Bii Peripheral OPE GPIO na Use interrupt v LEDs_Positi COsmlons Peripheral OPE GPIO w Use interrupt Push Buttons Position d i Data Sheet Figure
4. http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 Step 13 We need to create space for our file in the project To do this double click on Add Software Application Project under the Applications in the Project Information Area Refer to figure 27 Name your project led_blink and select OK Xilinx Platform Studio C Documents and Settings Administrator Desktop files_to_be_synced Ahmads fh File Edit View Project Hardware Software Device Configuration Debug Simulation Window Help OP AGI a Poa Fe BMI AYRE teh SP imee ANS EEJ ZEEE AAAAN Project Information Area eee i 56 Type par h fc Project Applications IP Catalog O 57 iol Projects 56 Program par jam Add Software Application Project 59 W WF Default ppc405 0 bootloop 60 ol high 61 lt Lnuputdir gt lt design gt be lt desiqgn gt ncd Gg lt Lnputdir gt lt design gt 64 END Program par 65 66 67 Options for Post 5a 69 Type tree h f 70 71 Program post par Ta e 3 73 o lt desiqn gt twr 74 xml lt design gt tw gt 75 tsi lt design gt tsi 76 lt cinputdir gt lt desigqr TY lt inputdir gt lt desigr 73 END Program post_ 4 Platform Studio m System Assemt Figure 27 Adding our LED blink to the project By default our program will be initialized in BRAM This means the code will be st
5. pop up J ModelSim SE 6 2a File Edit View Compile Simulate Add Transcript Tools Layout Window Help amp amp amp is tes 100 ps gt OPS aD Contains 2 XOX PB y Kew ni Bee amp RIAR FERIT ERENT Bal wave default clock enable reset E count Haf counter_3bit_testbench gf testcounter zi enable IMPLICIT WIRE reset 21 z reset IMPLICIT WIRE enable 20 z count H IMPLICIT WIRE clock 19 INITIALHIO ALWAYSHI5 FINITIALH24 AE Transcript R Top level modules counter 3bit testbench Figure 3 The wave window has been added to ModelSim Step 5 Now run the simulation Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 ModelSim gt run 500ns I am showing only the wave window in figure 4 ge wave default clock enable eset BA count Now FOOOUO ps Cursor 7 gg wave Figure 4 The wave window with our simulation results The wave window is not zoomed to the correct resolution First click in the wave RAAB window to make the zoom toolbar active Next click on the Zoom Full a icon Figure 5 is the result Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley Spring 2007 gt clock enable SF reset B
6. A programming tools is a long approximately 2 days and error prone process You are better off having them installed by an expert if you are new to FPGA programming In any case you should work through the tutorial below on a computer 1 Functional Simulation of Verilog Code using ModelSim ModelSim is a powerful simulator from Mentor Graphics for simulating Verilog code The best reference to learn ModelSim is the ModelSim User s Manual which you can download from Mentor Graphics website after registering for free Consider the simple Verilog code snippet below that implements a 3 bit counter You are encouraged to make a new folder for the counter and its test bench module counter_3bit clock enable reset count input clock reset input enable output 2 0 count reg 2 0 count always posedge clock or posedge reset begin if enable Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 begin if reset count lt 3 b0 else if count 3 b111 count lt 3 b0 else count lt count 1 end end endmodule The code above is hopefully straightforward to understand The code snippet below shows a testbench for the 3 bit counter timescale 1 ns 1 ps define HalfCycle 5 define Cycle HalfCycle 2 module counter _3bit_testbench reg clock enable reset wire 2 0 count setup clock initial
7. Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 FPGA TOOLS HOW TO Bharathwaj Bart Simpson Muthuswamy Connectivity Lab 264M Cory Hall Department of EECS University of California Berkeley mbharat eecs berkeley edu This document serves as a tutorial for using the myriad of software tools used to program an FPGA Describing the complete functionality of an FPGA is beyond the scope of this document an excellent reference is 1 The language that we use to program an FPGA is Verilog Describing Verilog in detail is also beyond the scope of this document Although you could use the examples in this report to understand the basic ideas behind Verilog I would suggest consulting a reference like 2 In addition you need an FPGA hardware platform for implementing your design As stated earlier we use the ML403 for testing some of our designs This tutorial assumes the implementation platform is the ML403 You should be able to adopt the steps below for any platform shoot me an email if you are stuck and I will try to help I will also assume that you have a good text editor I use Crimson Editor Verilog simulator we use ModelSim 6 2a FPGA programming environment we use Xilinx ISE 9 1 and a Power PC Programming toolkit we use Xilinx EDK 9 1 You can also program an FPGA using Simulink from Mathworks you need System Generator for DSP we use version 9 1 Please note installing FPG
8. K examples projects here Figure 16 EDK 9 1 startup screen showing the base system builder Step 1 I highly recommend using the Base System Builder to build the project skeleton Select Uk to build a new project Step 2 Create a new directory for the project called LED_blink_ml403_ppc as shown in Figure 17 Create New XPS Project using BSB Wizard New project Project file C Documents and Settings Administrator Desktop files_to_be_synced amp hmadStuff LED_blink_ML403_ppe spstem xrnpl Advanced options optional F1 for help Set Project Peripheral Repositories Figure 17 A new project created using the base system builder wizard Step 3 In the Base System Builder Welcome Screen select Create a New Design Step 4 Next select the board vendor as Xilinx and Board name as the ML403 Evaluation Platform Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 Step 5 Select PowerPC as your processor the MicroBlaze is a soft core Pay careful attention to the block diagram in this box Step 6 Make sure all the clock frequencies are 100 MHz refer to figure 18 Base System Builder Configure PowerPC PowerPo System wide settings Reference clock Processor clock frequency frequency 100 00 MHz 100 00 s MHz 100 00 MHz Bus clock frequency Ensure that your board ts configured
9. Sim gt vlog v Note vlog 1901 OptionFile C Modeltech_6 2a vlog opt not found Ignored Model Technology ModelSim SE vlog 6 2a Compiler 2006 06 Jun 16 2006 Compiling module counter_3bit Compiling module counter_3bit_testbench Top level modules counter_3bit_testbench Step 3 Start the simulation ModelSim gt vsim work counter_3bit_testbench vsim work counter_3bit_testbench Loading work counter_3bit_testbench Loading work counter_3bit Warning vsim 3009 TSCALE Module counter_3bit does not have a timescale directive in effect but previous modules do Region counter_3bit_testbench testcounter Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 Figure 2 will pop up fed ModelSim SE 6 2a File Edit Yiew Compile Simulate Add Transcript Tools Layout Window Help counter_3bit_testbench af testcounter enable MPLICIT WIRE reset 21 z eset D H IMPLICIT WIRE enable 20 Gm fs count IMPLICIT WIRE clock 19 INITIALHHO HALWAYSHIS D FINITIALH24 3 Transcript Compiling module counter_3bit_testbencH H H Tan laval madi ilas Figure 2 ModelSim all ready to simulate Now we need to add what waveforms that we want to see I usually add all waveforms Step 4 Add waveforms ModelSim gt add wave Figure 3 should
10. Xilinx Platform Studio C Documents and Settings Administrator Desktop files_to_be_synced AhmadStuff _ED_blink_ML403_ppc system xmp fast_runtime opt E File Edit view Project Hardware Software Device Configuration Debug Simulation Window Help E OF AS OMT OeaX Ane N RAL BeANS NP HR Bec anO E SE AAAA MS Project Information Area 62 lt design gt ncd Output placed and routed NCD Project Applications IP Catalog 63 lt inputdir gt lt design gt pcef Input physical constraints file SSS 64 END Program par Software Projects 65 i JAdd Software Application Project 66 RA Default ppc405_0_bootloop 67 Options for Post Par Trace 6 69 Type tree h for a detailed list of tree command line options oH TA Program post_par_ tree 72 e 3 Produce error report limited to 3 items per constraint 73 o lt design gt twr Output trace report file 74 xml lt design gt twx Output XML version of the timing report 7S tsi lt design gt tsi Produce Timing Specification Interaction report 76 lt inputdir gt lt design gt ncd Input placed and routed ned 77 lt inputdir gt lt design gt pcef Physical constraints file 78 END Program post_par_trcee 79 80 61 lt Platform Studio th System Assembly View Block Diagram 2 fast_runtime opt system uct Generating Block Diagram C Documents and Settings Administrator Desktop files to be synced AhmadStuff LED blink ML403_pp
11. aan OxFFFFFFFC plb_bram_ if cntl1 ELF file used to populate section information C 4LED_Blink_ml403_ppc led_blink executable elf Output Linker Script led_blink_linker_script td C Cee Figure 29 Linker options Step 17 Before we build the program we will disable optimizations because they can make debugging difficult Double click on Project led_blink and find the Optimization tab Change the Optimization Level to No Optimization Also make sure that in the Debug Options section the Create symbols for debugging checkbox is selected 7 Step 18 Select Software and then select Build All User Applications in the menu bar Step 19 Left click Debug in the menu bar and Select Launch XMD Figure 30 will pop Part Name Hatti H System GE H565909S AGF32AP HieS A93 RC4UFRI2 AF6HRHFS xe 5144x1 PowerPC465 Processor Configuration Ax26611436 A gt ABABA Ho of PO Breakpoints Ho of Read AddreData Watchpoints 1 Ho of Write Addr Data Watchpoints 1 User Defined Address Map to access Special PowerPC Features using AMD I Cache D 7 HxYAHHJFFF I Cache A gt 7 HRB466H Hx FBR TEFF D Cache A gt 78 ABABA Hx 7BHBSF EF Ax 8 AB4608 Ax 7BHR TE FF A gt 8 HB4608 Hx PB ANAF FF A gt FHA 460H Hx FARR TE FF Connected to ppc target id H Starting GDE server for ppc target Cid H at TCP port no 1234 Figure 30 XMD is up and running Connectivity Lab http connectivitylab eecs berkel
12. ce driver documentation remember that th layer 0 API can be found in the drivers x ariver _ 4 header file while the layer 1 API can be found in the drivers x lt odriver h header file Figure 24 Select Links underlined above Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 Step 12 e Left click on Driver API links Driver API Links Building Block Components Common Figure 25 The Driver API links gives you a list of all the APIs Step 12 f Scroll down the API list and select GPIO version 2 01a refer to figure 27 gpio 2 01 0 Ma a ou a D 0 Figure 26 Select 2 01a for GPIO This will give you the API description for GPIO The program code for blinking the LED is given below include xgpio h include xparameters h include xcache_ h include xtime_ h int main void XGpio gp_ out int 0 int j 0 XGpio_Initialize amp gp out XPAR_LEDS 4BIT_DEVICE_1ID XGpio_SetDataDirection amp gp_out 1 0x00 while 1 j j 1 256 write the value of to the LED s XGpio_DiscreteWrite amp gp_out 1 j software delay loop for pause for i 0 i lt 400000 i Create a new directory called code in your project and create a new file with the text above You can name the file anything you want I have ledApp c Connectivity Lab
13. clock 1 b0 you need to do this since clock is of type reg and by the Verilog standard reg types start with x value unless explicitly set always HalfCycle clock clock setup UUT Unit Under Test counter_3bit testcounter clock clock enable enable reset reset count count initial begin apply some test stimulus enable 1 b1 reset 1 b1 Cycle 3 reset 1 b0 Cycle 5 reset 1 b1 Cycle reset 1 b0 end endmodule We will use ModelSim to simulate the code above Start ModelSim by double clicking M ModelSim SE 1 za on the icon Figure 1 should pop up Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS http www eecs berkeley edu University of California Berkeley Spring 2007 N ModelSim SE 6 2a File Edit view Compile Simulate Add Library Tools Layout Window Help w work unavailable Library AIM Library c Modeltech_6 2a modelsim_lib abel aim AIM_VER Library c Modeltech_6 2a modelsim_lib abel_ver ain CPLD Library c Modeltech_6 2a modelsim_lib cpld CPLD_VER Library c Modeltech_6 2a modelsim_lib cpld_ver PLS Library c Modeltech_6 2a modelsim_lib abel pls SIMPRIM Library c Modeltech_6 2a modelsim_lib simprim SIMPRIMS_VER Library c Modeltech_6 2a modelsim_lib simprims_vel UNISOOO_YER Library c Modeltech_6 2a modelsim_lib uni3000_ver UNISIM Library c Modeltech_6 2a modelsim_lib uni
14. cs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 E New Project Wizard Device Properties Select the Device and Design Flow for the Project Property Name lt Product Category Family Device Fackage Speed 4 a5 D Synthesis Tool fol MHDLAYerlog Simulator Modelsim SE Verilog Top Level Source Type Prefered Language Verilog Enable Enhanced Design Summary Enable Message Filtering bjb Display Incremental Messages Figure 9 Device properties for the ML403 Step 5 Click ERE twice so that you can add an existing source Click Add Source to add the Counter 3bit v file Do not add the testbench Step 6 Accept the default project settings Click F click OK if you get the File Added Successfully box You should see figure 10 Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 EE Xilinx ISE C Documents and Settings AdministratorDesktop iles_to_be_synced AhmadStuffisample_code Counters WML403_Counter ML403_Counter ise Design Summary x File Edit view Project Source Process Window Help _ f l _ A Pere e T fORB EG S 488X 4a YIP LX SP AAS E Oh iA R 2 Ow MH coosnst ViVi a EEEE x E FPGA Design Summary ML403_COUNTER Project Status Sources Sources for Synthesis Implemen
15. e blkdiagram system html Generated system svg Block diagram generated Copied C EDK data xflow bitgen ut to ete directory Warning Error CAPS NUM SCRL Ln 78 Col 2 Z Adobe Acrobat fm 3 Windows Ex Gi FPGA SDR_Tec Berkeley EECS G untitled Paint a Xilinx Platform 5 Figure 21 XPS is ready to go Step 11 The careful reader would have noticed a difference between Figure 21 and their XPS window I have opened two files fast_runtime opt and system ucf To get to these files click on the Project in the Project Information Area and then double click on the two files The system ucf file is similar to the one we created in the ISE project The fast_runtime opt is more interesting When I compiled the project for the first time I always get an error from the Post Place and Route program unexpected termination halting Since this error message is not very informative I decided to comment out the post place and route program Lo and behold My program compiled and worked on the board However I don t know the implications of commenting out the Post Place and Route program I have contacted Xilinx still waiting for a response Please email me 1f you have an explanation or you found an alternate solution But for the time being make sure you comment out the Post Place and Route program in fast_runtime opt Step 12 The next step is to create the LED source code Again the idea is we write a C pr
16. e count O00 CTS ST Mow FOOO00 ps 499401 ps kal Figure 5 The wave window showing more details You can use the other zoom icons to get a nicer picture Try to get figure the wave window to look like figure 6 You can also use the cursor icons A it Ay to place cursor s on the wave window so that you can measure properties like the rise time etc zE gt clock enable gt reset C EC A CODD CO Ce a E e E E iE Now BOO ps E Yon Ee pel wave Co eeeeseseseseseseses i i i i a a yDRN Figure 6 Wave window with an active cursor and showing more functionality of the counter 2 Implementation of your code on an FPGA Using Xilinx ISE to simplify the steps We will implement the counter created in section a on the ML403 board The tool we will use is Xilinx ISE Implementation of a design on an FPGA mainly consists of the Connectivity Lab Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 following steps Synthesis Translation Generating a Program File and Download the program file onto the FPGA We won t go into a lot of detail s on the steps above just an idea of how to use the ISE An important note the ISE is a GUI Graphical User Interface That is it is just an interface to command line tools Therefore when there are errors in any stage of the ISE you should look at the output dumps from each step They will t
17. ell you a lot about what is going on Lets get started yr lt u Step 1 Double click on the Xilinx ISE icon WESS on your desktop to start the tool Figure 7 shows up File Edit Yiew Project Source Process Window Help DAHA SiG BX be ViPHPXKS BIASES ODA io mcr WV IRE SMA A No project is open File gt Open Project or File gt New Project E Sources pj Snapshots f Libraries No flow available Figure 7 Xilinx ISE startup screen Step 2 Click on File gt New Project to start the New Project Wizard shown in figure 8 Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 E New Project Wizard Create New Project Si EJ Enter a Name and Location for the Project Project Name Froject Location r esktop tiles_to_be_syncedAhmadstuthDinkporsyin al Select the Type of Top Level Source for the Project Top Level Source Type HEL Figure 8 ISE New Project Wizard Step 3 Create a new project named ML403_Counter in the same directory as your Mest gt Verilog source files Leave source as HDL Click to continue Step 4 The Device Properties window will pop up Configure it to match the chip on the ML403 board see figure 9 If you have the board just look at the chip This will give you all the information you need Connectivity Lab http connectivitylab ee
18. ey edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 Step 20 Type dow led_blink executable elf and type con to execute the program The LEDs should blink slowly 4 System Generator for DSP Programming FPGAs using Simulink Xilinx s User s Guide for System Generator 6 is the best reference for learning how to use System Generator It is a free download 16 MB 5 References l http www fpga4fun com last accessed 05 17 07 Advanced Digital Design with the Verilog HDL Cuiletti Michael D Xilinx Design Series 2003 Xilinx Synthesis Technology XST User Guide pp 5 10 5 12 Online last accessed 05 18 07 http toolbox xilinx com docsan xilinx5 pdf docs xst xst pdf ML401 ML402 ML403 Evaluation Platform Online last accessed 05 18 07 http www xilinx com bvdocs userguides ug080 pdf Embedded Systems Tools User s Manual Online last accessed 05 22 07 http www xilinx com ise embedded est_rm pdf Xilinx System Generator User s Guide Online last accessed 05 23 07 http www xilinx com support sw_manuals sysgen_ug pdf Introduction to Xilinx Platform Studio Iowa State University Online last accessed 05 23 07 http class ece 1astate edu cpre488 Labs Lab_1 CPRE488 LABOlI1 pdf 6 Acknowledgements First off many thanks to Prof Ahmad Bahai for find the funding and letting me work on this project Prof Pravin Varai
19. http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 PPC hardcore 0 0 dd r SLAVES OF plb Step 1 Implement hardware rat Step 2 Design software Figure 15 The concept behind implementing a design on the PPC The PPC already exists on the FX core We will just implement various hardware in the FPGA fabric on the FX core and then write software in C to glue the hardware to the PPC For more details refer to 5 Double click on the MEt Xilinx Platform Studio XPS icon to start EDK 9 1 Figure 16 should pop up Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 s Xilinx Platform Studio no project opened Platform Studio File Edit View Project Hardware Software Device Configuration Debug Simulation Window Help DP RS tO MP tae Ze BM AMS se Rim ANGE ABEM m a x Project Information Area Project Applications IP Catalog a cl eine aw Select desired text for more information Documentation Examples Tech Tips Starting your project O a X 4 i Software Development Hardware Development w Xilinx Platform Studio Create new or open existing project BS Em Blank XPS project em Open a recent project Browse for More Projects Browse installed ED
20. it is un necessary to specify timing if you specify a global clock For further information on timing constraints please refer to 3 Step 9 Now add the UCF file you created in step 8 to your project Right click the xc4vfx 12 10ff668 under sources and select Add Source as shown in figure 11 ma ciyf 2 1 0HBGE jefe Counter_Sbit i Mew Source Add Source Add Copy of Source El Open Set as Top Module Use SmartGuide Mew Partition Delete Partition Partition Properties Partition Force H Remove Sources Pai Snaps Move to Library SSeS Toggle Paths a DT Properties TESSE Figure 11 Adding the UCF Step 10 Left click the counter_3bit Counter_3bit v under the Sources window as shown in figure 12 The Processes dialog box will change to reflect the implementation steps Double click on the Generate Programming File ISE will start the synthesis process Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 C OUNCES E ounces for i Sunthesisyl mplementation ka ML403_Counter El ga wedi 2 100668 E counter _ abt uct counter abit uct Br Sources fai Snapshots I Libraries Processes for counter Sbit P Add Existing Source PM Create New Source B Vien Design Summary ee Design Utilities ES F User Constraints 40 Synthesize ST 4 Impleme
21. nt Design F Generate Programming File i Update Bitstream with Processor Data u Analyze Design Using Chipscope Figure 12 Double click on Generate Programming File to start bitstream generation Step 11 If all goes well ISE should be done in about a minute on a dual core 2 GHz machine The next step is to actually download your design to the FPGA Connect your JTAG cable to the ML403 refer to 4 via the FPGA amp CPU Debug port Power on your ML403 and connect your JTAG cable to your computer Step 12 Left Click on and double click on the Configure Device MPACT option Figure 13 pops up Leave the defaults click 1 Figure 14 pops up Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 ES iMPACT Welcome to iMPACT Sls Please select an action fram the list below Configure devices using Boundary Scan JTAG O Prepare a PROM File O Prepare a System ACE File Prepare a Boundary Scan File SWF Configure devices using Slave Seral mode lt Back f Finish Figure 13 Selecting the cable type Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 Step 13 You can skip configuration of the xccace xcf32p and the xc95144xl All you are going to configure is the FX chip S
22. o click F45 till you get to the FX chip qe A nn ma TF ge ae Oe RY Sources x Sa Boundary Scan Sul SlaveSerial Sal SelectMAP 38 Desktop Configuration 23 Direct SPI Configuration E SystemA CE E xoca xc95144xl PROM File Formatter lt f fil tile po I Sources g8 Snapshots f Libraries Configuration Modes Assign New Configuration File Processes x D Ost _ngo msgs File name File type All Design Files mpm bsd v None Enable Programming of SPI Flash Device Attached to this FPGA Enable Programming of BPI Flash Device Attached to this FPGA Figure 14 Getting ready to download the bit file Step 14 Select the counter_3bit bit file Just select OK in the ensuing dialog box you are not going to add any other files Now right click on the xc4vfx12 left click program and select OK That s it You should see the LEDs light up on the board 3 Embedded Power PC Programming using Xilinx EDK NOTE DO NOT CREATE THIS PROJECT IN A DIRECTORY WITH SPACES IF YOU DO THE PROJECT WILL NOT COMPILE THE REASON IS XILINX TOOLS USE Cygwin CALLS SINCE THEY ARE UNIX BASED THEY WILL NOT HANDLE SPACES In the previous section you learned how to program the FPGA using ISE and HDL In this section you will look at how to program the Power PC PPC core on the Xilinx FX chips The basic concept behind programming the FX chip is shown in figure 15 Connectivity Lab
23. ogram to interface to the LEDs through the GPIO bus Finding the various libraries required to program the PPC requires a little bit of mouse clicking Step 12 a Left click on Help EDK Online Documentation Step 12 b Left click on IP Reference refer to figure 22 Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 EDK Home Page Tools IP Reference Processor Reference Guides Figure 22 Select IP Reference underlined above Step 12 c Left click on Driver Reference Guide refer to figure 23 Xilinx EDK IP Documentation Processor IP Catalog gt Describes the usage ofthe On chip Peripheral Bus OP and the IBM Processor Local Bus PLB used in Xilinx FPGAs gt Provides the design specifications for all the processor IP provided with the EDK Driver Reference Guide Xilinx provides full featured device drivers for its Processor IP cores The Figure 23 Select Driver Reference Guide underlined above Step 12 d Left click on Links refer to figure 24 Xilinx Processor IP Library Xilinx Device Drivers Introduction Xilinx provides full featured device drivers for its Processor IF cores The device driver architecture is described in the Device Driver Programmer Guide Links to the Application Programming Interface API documentation for each device driver are provided below When referencing specific devi
24. ored in FPGA memory Make sure the bootloop program is initialized to BRAM This keeps the processor in a known state after we load the hardware the UART interface the SDRAM interface and GPIO Bus and before we load the software our LED blink program Right click on Default ppc405_0_bootloop and make sure that Mark to Initialize BRAMS is selected Step 14 Now the hardware portion of our project is configured we need to download it to our FPGA board Click on Device Configuration in the menu bar and then Download Bitstream Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 Once the FPGA is configured the DONE LED above the Compact Flash card on the ML403 will light up Now you will download our software onto the board Step 15 First add our source file Right click on Sources and select Add Existing File Refer to figure 28 Project Information Area ee Project Applications IP Catalog Software Projects je Jd Software Application Project AP Default ppc405 OL bootloop Project led_blink Processor poc405_ 0 Executable C Documents and Settings 4dministrator Desktophles_to_be_synced4hmadStutfisample_codeSLED Blink_ml403_ Compiler Options Add Existing Files WdministratorsDesktop iles to be synced 4hmadStuffyeample codeXLED Blink ml403_ppc co H Add Mew File
25. sim UNISIMS_ VER Library c Modeltech_6 2a modelsim_lib unisims_ver ILINXCORELIB Library c Modeltech_6 2a modelsim_lib xilinsCoreLit ILINXCORELIB_ Library c Modeltech_6 2a modelsim_lib ilinxCoreLit sv_std Library MODEL_TECH s _std vital2000 Library MODEL_TECH vital2000 ieee Library MODEL_TECH ieee Hi modelsim_lib Library MODEL_TECH modelsim_lib Esl I std Library MODEL_TECH std i std_developerskit Library MODEL_TECH std_developerskit H spnopsys Library MODEL TECH synopsys Md Ct E JM Library KE Transcript E 7 THIS WARK PANTAING TRANF SFPRET ANN Figure 1 The ModelSim startup screen A note on the Workspace window in figure 1 you see a lot of libraries related to Xilinx products You need these libraries if you are to use any of Xilinx s parts like RAM units synthesized from Xilinx CoreGen in your code You won t need these parts for the 3bit counter Here are the steps to simulate your model What you type is in bold italics ModelSim output is in 0 point italics Step 1 cd to your project directory by typing the command in the Transcript window ModelSim gt cd sample_code counters Step 2 One way to use ModelSim is to create a library and add your modules to it For other methods refer to the ModelSim User s Guide ModelSim gt vlib work ModelSim gt vmap work work Modifying C Modeltech_6 2a win32 modelsim ini Step 2 Compile the code Model
26. t 32 b0 if our 32 bit counter reaches 5e7 then 0 5 seconds have elapsed the input clock is at 100 MHz 1e8 Hz always posedge clock or posedge reset begin if reset fast_100MHz_count lt 32 h0 else if fast_100MHz_count 32 h2FAF080 begin fast_100MHz_count lt 32 h0 slow_1Hz_clock slow_1Hz_ clock end else fast_100MHz_ count lt fast_100MHz_ count 1 end always posedge slow_1Hz_clock or posedge reset begin if reset count lt 3 b0 else if count 3 b111 count lt 3 b0 else count lt count 1 end endmodule In the code snippet above I have done two things First I specified which pins on the FPGA the ports of the top level module map to In order to find this information refer to your board s User s Guide In the case of the ML403 refer to 4 Next I slowed down the clock to 1 Hz using a 32 bit counter Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 Step 8 Next let us specify a UCF Create a file named counter_3bit ucf in the same directory as your project Enter the following using a text editor NET clock LOC AE14 NET reset LOC E7 NET count lt 0 gt LOC G6 NET count lt 1 gt LOC A11 NET count lt 2 gt LOC A12 Save the file There are actually two types of constraints placement and timing However for most designs
27. tation Design Overview Project File ML 403_Counterise Cunent State o S ML403_Counter Summary S EF xc4vix1 2 1 0668 C 10B Properties Module Name counter_3bit i twos OOO O W e counter _3bit Counter_3bit v D1 Timing Constraints nod 2 1 D668 Warming O Clock Report Ta ra Errors and Wamings ML403_COUNTER Partition Summary A Synthesis Messages No partition information was found i Detailed Reports O Place and Route Messages Tinting Messages Status Generated Errors Wamings Q Bitgen Messages Synthesis Report All Current Messages Translation Report Detailed Reports Map Report kisii doau tee beri eee ae ea ores H Map Report Static Timing Report Processes for counter_3bit O Place and Route Report eine M Add Existing Source pO Static Timing Report m Create New Source Bitgen Report View Design Summary Es p Design Utilities E y User Constraints H E Synthesize XST L H P Implement Design Project Properties E E Generate Programming File Enable Enhanced Design Summary Update Bitstream with Processor Data O Enable Message Filtering a Analyze Design Using Chipscope O Display Incremental Messsages Enhanced Design Summary Contents Show Partition Data O Show Errors O Show Warnings O Show Failing Constraints O Show Clock Report Figure 10 ISE project has been created Now there are two steps that you need
28. to do before you can build your code First you need to tell the design tools what is your top level module is This is the module that starts executing once you download code to the board Second you need to tie the input and outputs from your code to actual FPGA pins There are two ways to do this using a User Constraints File UCF or XCF Xilinx Constraints File or directly specifying the pin locations in your top level module 3 I will use a UCF for the pin locations refer to 3 for directly specifying the constraints in your top level module Step 7 Now converting counter_3bit to a top level module is pretty easy you just have to specify the pin locations in the code Double click on the counter_3bit in the Sources dialog box refer to figure 10 and modify the code as shown below Connectivity Lab http connectivitylab eecs berkeley edu Department of EECS University of California Berkeley http www eecs berkeley edu Spring 2007 module counter_3bit clock goes to FPGA pin AE14 SYSCLK 100 MHz reset goes to FPGA pin E7 GPIO Switch North counto will go to FPGA pin G5 GPIO LED 0 counti will go to FPGA pin A6 GPIO LED 1 count2 will go to FPGA pin A11 GPIO LED 2 a count input clock reset output 2 0 count reg 2 0 count we need to slow down the clock or we can t distinguish the count reg slow_1Hz_clock reg 31 0 fast_100MHz_ count initial slow_1Hz_clock 1 b0 initial fast_ 1OOMHz_coun
29. ya Dr Carl Chun Ali Djabbari and Dr Wei Ma from National Semiconductor have been very helpful and continue to help me in this project Raffi Selvian debugged one of the very first incarnations of our installation Ian Tan helped me countless times with FPGA tips Sophie Maryam and Prashanth provided valuable feedback Last but not the least Ferenc Kovac for mentoring me and helping us with the ML403 and tool setups Connectivity Lab http connectivitylab eecs berkeley edu
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