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sysIO Usage Guidelines for Lattice Devices

1. isp5000VG ispXPGA ispGDX2 ispXPLD isp5000B LVDSIN Yes Yes Yes LVDSOUT Yes Yes LVDSTRI Yes Yes LVDSIO Yes Yes Se BLVDSIN Yes Yes BLVDSOUT Yes Yes BLVDSTRI Yes Yes BLVDSIO Yes LVPECLIN Yes Yes Yes Yes LVPECLOUT Yes Yes Yes LVPECLTRI Yes Yes Yes LVPECLIO 1 Clock input pins only Table 56 Available Macros When the Differential I Os are Used with sysHSI Block ispXPGA ispGDX2 LVDSIN Yes Yes LVDSOUT Yes Yes LVDSTRI Yes Yes LVDSIO BLVDSIN Yes BLVDSOUT Yes BLVDSTRI Yes BLVDSIO LVPECLIN LVPECLOUT LVPECLTRI LVPECLIO Technical Support Assistance Hotline e mail Internet 1 800 LATTICE North America 1 503 268 8001 Outside North America techsupport latticesemi com www latticesemi com 48
2. Parameter Symbol Parameter Description Min Typ Max Veco I O Supply Voltage 3 0 3 3 3 6 VREF Input Reference Voltage 1 3 1 5 1 7 External Termination Voltage Vv 1 3 1 5 1 7 g VTT VREF Vin Input High Voltage VREF 0 2 Veco 0 3 Vu Input Low Voltage 0 3 Vrer 0 2 Vou Output High Voltage Vrer 0 4 VoL Output Low Voltage Vrer 0 4 lou Output Current at Voy 8mA lot Output Current at VoL 8mA CTT3 Termination Driving device Receiving device l Va 1 5V 10 C 50 ohm I pad pad sa Z 50 ohm i mbe cL Vor Vier GND 24 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices CTT25 The following tables describe the features supported by a Lattice device when the syslO interfaces are in 2 5V CTT Center Tap Terminated mode and the key specifications described in JEDEC Standard JESD8 4 Table 29 CTT25 Features List Feature Value External Termination Required Yes Bus Maintenance Control OFF Slew Rate Control FAST Drive Strength Control No Open Drain Option No Table 30 CTT25 DC Characteristics Parameter Symbol Parameter Description Min Typ Max Veco I O Supply Voltage 2 3 2 5 2 7 VREF Input Reference Voltage 1 3 1 5 1 7 VIT a Voltage 13 15 17 Vin Input High Voltage Vrer 0 2 Vcco 0 3 Vu Input Low Voltage 0 3 _ Vrer 0 2 VoH Output High Voltage Vrer 0 4 V
3. Parameter Symbol Parameter Description Min Typ Max Veco I O Supply Voltage 3 0 3 3 3 6 VREF Input Reference Voltage Sen na VIT External Termination Voltage FE VoH Output High Voltage IOH 0 9Vcco _ _ VoL Output Low Voltage IOL 0 1Vcco Vin Input High Voltage 0 5Veco Note 1 Vu Input Low Voltage 0 3 0 3Vcco 1 Viy max value varies by device Please refer to the appendices for device specific Vu MAX values 2 In this specification Vcco refers to the Voco of the driving device It is assumed that Vcc of the receiving device tracks Vcco Some devices use absolute values 17 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices PCIX The following tables describe the features supported by a Lattice device when the syslO interfaces are in 3 3V PCIX mode and the key specifications described in the PCIX Addendum to the PCI Local Bus Specification Revi sion 1 0 Table 15 PCIX Features List Feature Value External Termination Required No Bus Maintenance Control UP Slew Rate Control FAST Drive Strength Control OH IOL Set according to the PCIX Specification Open Drain Option No Table 16 PCIX DC Characteristics Parameter Symbol Parameter Description Min Typ Max Veco I O Supply Voltage 3 0 3 3 3 6 VREF Input Reference Voltage VIT External Termination Voltage Vou Output High Voltage IOH 0 9Vcco
4. Feature Value External Termination Required Yes Bus Maintenance Control OFF Slew Rate Control FAST Drive Strength Control No Open Drain Option No Table 26 SSTL2_Il DC Characteristics Parameter Symbol Parameter Description Min Typ Max Veco UO Supply Voltage 2 3 2 5 2 7 Input Reference Voltage V 1 15 1 25 1 35 REF VREF 0 5Vcco External Termination Voltage V 1 15 1 25 1 35 TI VIT VREF Vin Input High Voltage VREF 0 18 Veco 0 3 Vu Input Low Voltage 0 3 Vper 0 18 VoH Output High Voltage Veco 0 43 VoL Output Low Voltage 0 35 loH Output Current at Voy 15 2mA loL Output Current at VoL 15 2mA SSTL2_II Termination Driving device Receiving device Va 0 5V ogg a ii Veco SP 50 ohm 50 ohm A pad 25 ohm pad DAMW Z 50 ohm lt CJ SR Ver Vir GND i 23 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices CTT33 The following tables describe the features supported by a Lattice device when the syslO interfaces are in 3 3V CTT Center Tap Terminated mode and the key specifications described in JEDEC Standard JESD8 4 Table 27 CTT3 Features List Feature Value External Termination Required Yes Bus Maintenance Control OFF Slew Rate Control FAST Drive Strength Control No Open Drain Option No Table 28 CTT3 DC Characteristics
5. The second type of interface implemented is the terminated single ended interface standard This group of inter faces includes different versions of SSTL and HSTL interfaces along with CTT GTL Usage of one of these partic ular I O interfaces requires the use of an additional Vpgp signal At the system level a termination voltage V77 is also required Typically an output will be terminated to V77 at the receiving end of the transmission line it is driving The final types of interfaces implemented are the differential standards LVDS Bus LVDS BLVDS and LVPECL Table 1 lists all the syslO standards supported for all the Lattice device families and Table 2 lists the Veco VREF and V77 requirements for each of the syslO standards supported www latticesemi com 1 tn1000_09 1 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Table 1 syslO Standards Supported for the Lattice Family of Devices syslO Standard ispMACH 5000VG ispMACH 5000B ispXPLD 5000MX ispGDX2 ispXPGA LVTTL Yes Yes Yes Yes Yes LVCMOS 3 3 Yes Yes Yes Yes Yes LVCMOS 2 5 Yes Yes Yes Yes Yes LVCMOS 1 8 Yes Yes Yes Yes Yes PCI Yes Yes Yes Yes Yes PCIX Yes Yes AGP 1X Yes Yes Yes Yes Yes SSTL3 Class Il Yes Yes Yes Yes Yes SSTL2 Class Il Yes Yes Yes Yes Yes CTT3 Yes Yes Yes Yes CTT2 Yes Yes Yes Yes HSTL Class Yes Yes Yes Yes Yes HSTL Class III Yes Yes Yes Yes Yes HSTL C
6. VoL Output Low Voltage IOL Se 0 1Vcco Vin Input High Voltage 0 5Veco Note 1 Vi Input Low Voltage 0 3 0 35Vcco 1 Vi max value varies by device Please refer to the appendices for device specific Vu MAX values device specific Vu values 2 In this specification Voco refers to the Veco of the driving device It is assumed that Vcc of the receiving device tracks Voco Some devices use absolute values 18 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices AGP_1X The following tables describe the features supported by a Lattice device when the syslO interfaces are in 3 3V AGP 1X mode and the key specifications described in the Accelerated Graphics Port Interface Specification Revi sion 2 0 from Intel Corporation This specification closely mirrors the 3 3V PCI specification in many respects The differences are in the AC drive strength and the timing specifications Table 17 AGP1X Features List Feature Value External Termination Required No Bus Maintenance Control OFF Slew Rate Control FAST Drive Strength Control OH IOL Set according to the AGP 1X Specification Open Drain Option No Table 18 AGP1X DC Characteristics Parameter Symbol Parameter Description Min Typ Max Veco I O Supply Voltage 3 0 3 3 3 6 VREF Input Reference Voltage E SC VIT External Termination Voltage VoH Output High Voltage IOH 0 9Vcco VoL Output Low Vol
7. attice syslO Usage Guidelines aaee22 Semiconductor i j 122223 gemiconduc for Lattice Devices October 2005 Technical Note TN1000 Introduction The newer Lattice device families give the user the ability to easily interface with other devices by using advanced system I O standards This capability is referred to as sysIO Standard This application note describes the syslO standards that are available and how they can be implemented using Lattice s design software Over the past several years many factors have played heavily into the new development of I O switching standards The greatest factor has been the need to move signals around a board faster and with less noise The second greatest factor has been the development of more advanced process technologies that operate at lower and lower supply voltages To support the performance and supply voltage requirements at a system level Lattice supports syslO standards with its ispMACH 5000VG ispMACH 5000B ispXPLDTM 5000MX ispGDX2 and ispXPGATM families syslO Standards There are three classes of I O interface standards that are implemented in Lattice s programmable devices The first is the unterminated single ended interface This group of interfaces is the most common in use today in semi conductor devices It includes the LVTTL standard along with the 1 8V 2 5V and 3 3V LVCMOS interface stan dards Additionally PCI PCIX and AGP 1X are all subsets of this type of interface
8. D a o Q o S S VREF5 3 7 VREF2 GCLK GCLK CE lt 0 gt CE lt 3 gt 10 lt 192 223 gt 10 lt 32 63 gt o tai VCCO6 x x vCCco1 E E D D a o Q Q S S VREF6 E 3 VREF1 GCLK GCLK CE lt 1 gt CE lt 2 gt syslO Bank 7 syslO Bank 0 A QUA G i D E e Ww d GND V8 H e w 3 Q w aljo w GND A O x o Vv O a E F o Q 2 z o Q 2 o Differential Clock Inputs As shown in Figure 13 there are two clock pins on each side of an ispGDX2 device These clock pins can be con figured to meet one of the single ended interface standards Additionally they can be configured to interface with differential LVDS or LVPECL signals As shown in Figure 14 when differential signaling is selected GCLKO or GCLK8 will be the positive input to the comparator while GCLK1 or GCLK2 will be the negative input to the compar ator 46 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Figure 14 Clock Pairs for Differential Signaling GCLKO GCLK2 CLKO CLK2 GCLK1 GCLK3 Control Pin Interfaces The test and programming pins TCK TMS TDI TDO and TOE are independent of the banks These pins are LVC MOS only and are driven by Vcco pin from the adjacent bank The 1149 1 TAP pins TCK TMS TDI and TDO have their own supply pin Vecs Global Output Enable Pins GOEO GOE1 GOE2 GOE3 The global Output Enable pins support the same syslO
9. Figure 8 Clock Pairs for Differential Signaling GCLKo gt lt _ GCLK3 CLKO CLK3 GCLK1 _ _ _ _ GCLK2 Each global Clock input is associated with the adjacent bank of I O cells If a reference voltage is required for a Clock input it is obtained from the associated bank In this way CLKO gets Ver from bank 0 CLK1 gets Vpep from bank 1 and so on This is the reason that the Clock inputs are located at the bank boundaries as shown previously in figure 3 This scheme allows the Clock inputs to support syslO standards without requiring separate Ver pins Control Pin Interfaces The test and programming pins TCK TMS TDI TDO and TOE are independent of the banks The TOE pin uses the core supply level Vcc to set the input threshold and output drive levels and is compatible to the LVCMOS 3 3 interface standard That supply pin must be set to be compatible with one of the three LVCMOS interface stan dards Global Output Enable Pins GOEO GOE1 The global Output Enable pins support the same syslO interface standards as the user I O pins If an external ref erence voltage is required GOEO and GOE1 get this Vref from bank 2 Global Reset Pin The global Reset pin supports the same syslO interface standards as the user I O pins If an external reference voltage is required gets this Vrep from bank 2 40 Lattice Semiconductor Device Specific syslO Features syslO Usage Guidelines
10. I2 I NODE P_OUT OUT _P N OUT OUT_N LVDSTRI I3 I NODE OE OE P OUT OUT Pi N OUT OUT N LVDSIO I4 I NODEO OE OE O NODE1l P_IO IO P N_ IO IO N VHDL Il LVDSIN port map P_IN gt IN P N_IN gt IN N O gt NODE 12 LVDSOUT port map I gt NODE P_OUT gt OUT P N OUT gt OUT N 13 LVDSTRI port map I gt NODE P_OUT gt OUT P OE gt OE N OUT gt OUT N I4 LVDSIO Port map I gt NODEO OE gt OE O gt NODE1 P_IO gt IO P N_ IO gt IO N ABEL Il LVDSIN P_IN N_IN NODE I2 LVDSOUT NODE P_OUT N_ OUT I3 LVDSTRI NODE OE P_OUT N_OUT I4 LVDSIO NODEO OE NODE1 P_I0 N IO 10 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices VHDL Syntax attribute IO TYPES string attribute IO TYPES of PinName signal is Type DriveCurrent Example library ieee use ieee std logic 1164 all entity iovhdl is port md in std logic vector 1 downto 0 Din in std logic vector 4 downto 0 Clk0 in std logic Clk1 in std logic Clk2 in std logic Clk3 in std logic portA out std logic vector 4 downto 0 portB out std logic vector 4 downto 0 portC out std logic vector 4 downto 0 portD out std logic vector 4 downto 0 porte out std logic vector 4 downto 0 Attribute declaration ATTRIBUTE IO TYPES string IO types for I O pins ATTRIBUTE IO TYPES OF md SIGNAL IS PCI PIN ATTRIBU
11. commonly used on devices that do not have the syslO feature will be ignored if it is used in an ABEL source file Instead the attribute LAT IOTYPES should be used with the LVCMOS33 OD LVCMOS25 OD or LVCMOS18_OD properties to implement an open drain output or I O While it is possible to specify the bank it is recommended that the software be allowed to specify this To do this a should be used for Bank No otherwise Bank_No will be a value that can be obtained from the device data sheet If a pin has been assigned to an I O and the Bank_No conflicts with that pin assignment the fitter will produce an error To use the default drive strength for an I O a should be used in the Drive_Current area A full description of the standards and possible values for those standards is given in the descriptions of each of the syslO standards Bus maintenance and output slew rate selection is achieved using the LAT_PULL and LAT_SLEW attributes respectively syslO Usage with Verilog and VHDL Synplify and Precision RTL Synthesis support these syslO standards in VHDL and in Verilog with attribute pass ing much the same as pin locations pull ups and slew rates are already controlled A list of the attributes with the possible values for those attributes is shown in Table 3 below A full description of the standards and the attributes associated with each standard is given in the descriptions of each of the syslO standards Lattice Semiconducto
12. for Lattice Devices Appendix E ispGDX2 ispGDX2 syslO Banking Scheme Each ispGDX2 device is separated into eight independent groups of I Os and inputs called banks The device has been designed such that there is a maximum of eight syslO standard interfaces per ground The average DC cur rent drawn by I Os between adjacent bank GND connections or between the last GND in an I O bank and the end of the I O bank shall not exceed n 8mA Where n is the number of I Os between bank GND connections or between the last GND in a bank and the end of a bank Figure 13 shows the banking scheme for the ispGDX2 256 family of devices The banks in the ispGDX2 device are numbered from zero to seven as are the Vcco and Ver inputs for that bank In each bank there will be a single Veer pin and multiple Voco pins In addition each I O has configurable drive strength weak pull up weak pull down or a buskeeper latch Table 53 lists the syslO standards with the typical values for Voco VREF and VIT Figure 13 ispGDX2 256 Banking Scheme A A ps A Qa A Zil y S E it x er GND n B Q u IREI w o Q w O w GND T O w H o Ed O a E le gt gt a O A gt gt O syslO Bank 4 syslO Bank 3 10 lt 160 191 gt 10 lt 64 95 gt N N VCCO5 x x VCCO2 D
13. for Lattice Devices The two tables below lists the drive strength and the Vj characteristics for the LVCMOS syslO standards Also keep in mind that the internal pull ups and buskeeper latches for the IO pins are connected to the core Vcc voltage and not the bank Veco for this device Table 47 LVCMOS Features and DC Characteristics Standard Drive Strength mA LVCMOS33 20 16 12 8 5 4 LVCMOS25 16 12 8 5 4 LVCMOS18 12 8 5 4 1 Defaults are in bold Table 48 LVCMOS Features and DC Characteristics Parameter Value LVCMOS33 Viy MAX 3 6V LVCMOS25 Vu MAX 3 6V LVCMOS18 Mu MAX 3 6V 41 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Appendix C ispXPLD 5000MX 5000MX syslO Banking Scheme Each ispXPLD 5000MX device is separated into four independent groups of I Os and inputs called banks The device has been designed such that there is a maximum of 12 syslO standards per ground The average DC cur rent drawn by I Os between adjacent bank GND connections or between the last GND in an I O bank and the end of the I O bank shall not exceed n 8mA Where n is the number of I Os between bank GND connections or between the last GND in a bank and the end of a bank Figure 9 shows the banking scheme for the ispXPLD family of devices The banks in the ispXPLD 5000MX device are numbered from zero to three as are the Vcco and Vrer inputs for that bank In each bank ther
14. in Vop between H and L 27 mV Vos Output Voltage Offset 1 1 1 3 1 5 V AVos Change in Vos between H and L 27 mV IOSD Output Short Circuit Current 36 65 mA Notes 1 All the values are specified for Rr 270hm and C 10pF 2 See Table 2 for device specific capability 32 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices BLVDS Termination There are two types of BLVDS drivers the termination schemes at the driver side are similar as in LVDS termina tion The standard BLVDS drivers are current sourcing 10mA standard BLVDS drivers and are available for general syslO usage or SERDES usage See Table 1 for device specific support Standard i BLVDS Driver i d For certain devices a resistor pack is required at the BLVDS driver side as shown The BLVDS drivers with resistor pack are not supported for SERDES usage See Table 1 for device specific support I BLVDS Driver I with Resistor Pack j 80Q I 800 33 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices BLVDS Multi drop Application Single Termination I VILYY Double Termination n I H E d vy vavy 34 Lattice Semiconductor LVPECL syslO Usage Guidelines for Lattice Devices The following tables describe the features supported by a Lattice device when the syslO interfaces are in differen tial LVPECL mo
15. in Vos between H and L 50 mV losp Output Short Circuit Current 24 mA Notes 1 All the values are specified for Ry 1000hm and C 5pF 2 See Table 2 for device specific capability 30 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices LVDS Termination The following examples show how termination is accomplished when using the LVDS transmitter and receiver To extract the advantages high speed data throughput low EMI power reduction offered by LVDS care must be taken while designing high speed differential boards Since the LVDS signals switch at a very fast rate less than a nanosecond this means almost every single interconnect will act as a transmission line Lattice LVDS drivers are current sourcing standard LVDS drivers Refer to Table 1 for device specific support Standard LVDS Driver I LVDS Receiver I In certain devices LVDS drivers are supported with a resistor pack as shown Table 1 specifies the device and con figuration I I LVDS Driver i i with Resistor Pack i 3009 i LVDS pad NN l Receiver I i pad 3000 AN A few key points to keep in mind while designing a PC board using LVDS are shown here Matching the differential impedance is very important even for short interconnects Discontinuities in differ ential impedance will create reflections which will degrade the signal and show up as common mode noise Minimize skew between the condu
16. interface standards as the user I O pins If an external ref erence voltage is required GOEO gets this Vacr from bank 7 GOE1 from bank 4 GOE2 from bank 3 and GOE3 from bank 0 Global Reset Pin The global Reset pin supports the same syslO interface standards as the user I O pins If an external reference voltage is required gets this Vpep from bank 4 Device Specific syslO Features The two tables below list the drive strength and the Vu characteristics for the LVCMOS syslO standards Also keep in mind that the internal pull ups and buskeeper latches for the IO pins are connected to the bank Vcco for this device Table 53 LVCMOS Features and DC Characteristics Standard Drive Strength mA LVCMOS33 20 16 12 8 5 4 LVCMOS25 16 12 8 5 4 LVCMOS18 12 8 5 33 4 1 Defaults are bolded Table 54 LVCMOS Features and DC Characteristics Parameter Value LVCMOS33 Vu MAX 3 6V LVCMOS25 Vi MAX 3 6V LVCMOS18 Vu MAX 3 6V 47 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Appendix F Differential syslO Availability by Device Family Available Macros by Differential Standard and Device Table 55 illustrates available macros by differential standard and device when the differential I Os are used without sysHSI Block Table 56 illustrates macros with sysHSI Block Table 55 Available Macros When the Differential I Os are Used Without sysHSI Block
17. reduce the problem The first is to divide the higher current outputs or I Os more evenly among the device ground pins Doing this reduces the amount of current any single ground pin will have to sink A second method is to use the programmable current drive option available on the unterminated syslO standards Also for signals that do not have as much capacitive loading and for signals that do not switch as fast the current drive can be significantly reduced syslO Interface Selection and Configuration Lattice provides support for the syslO standards through the design source files and in the Constraint Editor CPLD or Preference Editor FPGA inside the design tools A designer can attach syslO properties to their ABEL VHDL or Verilog source files which will be passed through to the fitter software If the designer is using schematics properties are added to the input output and I O ports syslO Usage With ABEL ABEL supports the syslO standards by declaring an attribute in the ABEL source code property for that attribute and listing the pins that are associated with that property When using any of these attributes the expression LIBRARY lattice must be included in the ABEL source file An I O is specified to be a specific I O type using the expression LAT IOTYPES Signal name Type Bank No Drive Current A list of the attributes and possible values for those attributes is given below in Table 3 The OPENDRAIN attribute
18. 0 portB reg 4 0 portc reg 4 0 portD reg 4 0 portE IO types for I O pins pragma attribute md IO_TYPES PCI PIN pragma attribute portA IO TYPES PCI PIN pragma attribute portB IO TYPES LVCMOS33 PIN 20 pragma pragma pragma attribute attribute attribute porte portD porte IO_TYPES IO_TYPES IO_TYPES IO types for Clock pins pragma attribute Clk0 IO TYPES LVDS PIN 0 NONE pragma attribute Clk2 IO TYPES LVPECL D PIN 1 NONE CTT33 PIN LVCMOS25_OD PIN 8 LVDS PIN Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Differential syslO Macro Instantiation in HDLs Differential Signaling Usage Model Lattice devices support LVDS BLVDS and LVPECL differential I Os This section discusses the software usage of these differential standards syslO LVDS BLVDS and LVPECL are implemented in two ways e The user can define the p side of the differential pair in the design source and then set the IO_TYPES attribute to LVDS BLVDS or LVPECL By setting the IO_TYPES attribute to one of these differential I O types the software will automatically define the n side of the differential pair Furthermore the user can assign the IO_TYPES attribute in the Constraint Editor without modifying the design source e The user can also implement the LVDSIN BLVDSIN LVPECLIN LVDSOUT BLVDSOUT LVPECLOUT LVDSTRI BLVDSTRI LVPECLTRI LVDSIO and BLVDSIO macros
19. CLKO CLK3 GCLK1 GCLK2 Control Pin Interfaces The test and programming pins TCK TMS TDI TDO and TOE are independent of the banks The TOE pin uses the core supply level Vcc to set the input threshold and output drive levels and will be compatible to the LVCMOS interface standard associated with that core supply level The 1149 1 TAP pins TCK TMS TDI and TDO have their own supply pin Vcc Global Output Enable Pins GOE0 GOE1 The global Output Enable pins support the same syslO interface standards as the user I O pins If an external ref erence voltage is required GOEO and GOE1 get this Vpep from bank 2 Global Reset Pin The global Reset pin supports the same syslO interface standards as the user I O pins If an external reference voltage is required gets this Vgep from bank 2 Device specific syslO Features The two tables below lists the drive strength and the Vu characteristics for the LVCMOS syslO standards Also keep in mind that the internal pull ups and buskeeper latches for the I O pins are connected to the bank Veco for this device Table 49 LVCMOS Features and DC Characteristics Standard Drive Strength mA LVCMOS33 20 16 12 8 5 4 LVCMOS25 16 12 8 5 4 LVCMOS18 12 8 5 4 1 Defaults are bolded Table 50 LVCMOS Features and DC Characteristics Parameter Value LVCMOS33 Vu MAX 3 6V LVCMOS25 Vu MAX 3 6V LVCMOS18 Vu MAX 3 6V 43 Lattice Semicond
20. Description Min Typ Max Veco I O Supply Voltage ve ariana oe ze Va e a E Voltage 1 35 1 5 1 65 Vin Input High Voltage Vper 0 2 Vu Input Low Voltage Vrer 0 2 Vou Output High Voltage VoL Output Low Voltage 0 6 loH Output Current at Voy _ lot Output Current at VoL 36mA 29 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices LVDS The following tables describe the features supported by a Lattice device when syslO interfaces are in LVDS mode The LVDS interface is specified in IEEE Standard 1596 3 SCI LVDS and ANSI TIA EIA 644 These specifications are electrically similar but the data transfer rates are different Table 39 LVDS Features List Feature Value External Termination Required Yes Bus Maintenance Control OFF Slew Rate Control N A Drive Strength Control N A Open Drain Option N A Table 40 LVDS DC Characteristics Parameter Symbol Parameter Description Min Typ Max Units A 2 3 2 5 2 7 V Veco I O Supply Voltage 30 Se 36 y Vicm Input Common Mode Voltage 0 2 1 8 V Vrun Differential Input Threshold 100 mV Vin Input Voltage 0 2 4 V Vou Output High Voltage 1 38 1 6 V VoL Output Low Voltage 0 9 1 03 V Von Output Voltage Differential 250 350 450 mV AVop Change in Vop between H and L 50 mV Vos Output Voltage Offset 1 125 1 25 1 375 V AVos Change
21. EC Standard JESD8 7 Table 9 LVCMOS18 Features List Feature Value External Termination Required No Bus Maintenance Control UP DOWN LATCH OFF Slew Rate Control SLOW or FAST Drive Strength Control 4mA 5 33mA 8mA 12mA Open Drain Option LVCMOS18_OD 1 Refer to the Appendix for device specific values The items in bold are the default values Refer to Appendices for default drive strength values Table 10 LVCMOS18 DC Characteristics Parameter Symbol Parameter Description Min Typ Max Veco I O Supply Voltage 1 65 1 8 1 95 VREF Input Reference Voltage i VIT External Termination Voltage VoH Output High Voltage Veco 0 4 VoL Output Low Voltage 0 4 Vin Input High Voltage 0 65Vcco Note 1 Vu Input Low Voltage 0 3 0 35Veco 1 Vip max value varies by device Please refer to the appendices for device specific Vu MAX values 2 In this specification Vcco refers to the Veco of the driving device It is assumed that Voc of the receiving device tracks Veco Some devices have absolute values eg 0 65 1 65 1 07 Vj amp 0 35 1 95 0 68 Vil 15 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices LVTTL The following tables describe the features supported by a Lattice device when the syslO interfaces are in LVTTL mode and the key specifications described in JEDEC Standard
22. JESD8B Table 11 LVTTL Features List Feature Value External Termination Required No Bus Maintenance Control UP DOWN LATCH OFF Slew Rate Control SLOW or FAST Drive Strength Control IOH IOL 20MA Open Drain Option No 1 Refer to the Appendix for device specific values The items in bold are the default values Refer to Appendices for default drive strength values Table 12 LVTTL DC Characteristics Parameter Symbol Parameter Description Min Typ Max Veco I O Supply Voltage 3 0 3 3 3 6 VREF Input Reference Voltage VIT External Termination Voltage VoH Output High Voltage lop 2 4 VoL Output Low Voltage lo 0 4 Vin Input High Voltage 2 Note 1 Vu Input Low Voltage 0 3 _ 0 8 1 Vi max value varies by device Please refer to the appendices for device specific Vu MAX values Lattice Semiconductor syslO Usage Guidelines for Lattice Devices PCI The following tables describe the features supported by a Lattice device when the syslO interfaces are in 3 3V PCI mode and the key specifications described in the PCI Local Bus Specification Revision 2 2 Table 13 PCI Features List Feature Value External Termination Required No Bus Maintenance Control UP Slew Rate Control FAST Drive Strength Control lo4 lot Set according to the PCI Specification Open Drain Option No Table 14 PCI DC Characteristics
23. MACH 5000B device are numbered from zero to three as are the Voco and Voer inputs for that bank In each bank there will be a single Vper pin and multiple Vcco pins In addition each I O has configurable drive strength weak pull up weak pull down or a buskeeper latch Table 2 lists the syslO standards with the typical values for Veco Vref and VT Figure 7 isp MACH 5000B Banking Scheme lt lt GND Bank 0 I Os Bank 3 I Os Veco Veco Bank 0 Bank 3 10s syslO Bank 0 syslO Bank 3 i GCLKO GCLK3 GCLKO GCLK1 eee AN EE l GCLK3 GCLK2 Differential Pair i Differential Pair GCLK1 i GCLK2 SEN syslO Bank 1 i syslO Bank 2 si Veco Vecora lt i GOEO lt OGND D Bank 1 I Os GOE1 Bank 2 I Os fu eidis ES RESETB D 39 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Differential Clock Inputs As shown in Figure 3 there are two clock pins on each side of an isp MACH 5000B device These clock pins can be configured to meet one of the single ended interface standards that all of the inputs and I Os support Additionally two clock together to interface with differential LVDS or LVPECL signals As shown in Figure 4 when differential signaling is selected GCLKO or GCLK8 will be the positive input to the comparator while GCLK1 or GCLK2 will be the negative input to the comparator
24. TE IO TYPES OF portA SIGNAL IS PCI PIN ATTRIBUTE IO TYPES OF portB SIGNAL IS LVCMOS33 PIN 20 ATTRIBUTE IO TYPES OF portC SIGNAL IS CTT33 PIN ATTRIBUTE IO TYPES OF portD SIGNAL IS LVCMOS25 OD PIN 8 ATTRIBUTE IO TYPES OF portE SIGNAL IS LVDS PIN IO types for Clock pins ATTRIBUTE IO TYPES OF Clk0 SIGNAL IS LVDS PIN 0 NONE ATTRIBUTE IO TYPES OF Clkl SIGNAL IS LVPECL_S PIN 1 NONE ATTRIBUTE IO TYPES OF Clk2 SIGNAL IS LVPECL_D PIN 1 NONE D F D T end 11 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices syslO Usage with Schematic Capture The syslO standards are supported in schematics in much the same way as regular I Os The symbol attributes for the input output and I O buffers in the generic library include three additional attributes called IO_TYPES Drive and Diff_Pair The IO_Standard attribute can be set to any of the I O standards given in Table 2 The Diff_Pair attribute is used for differential I O standards It is assigned to the p side differential signal and set to the name of the n side differential signal If the Diff_Pair attribute is not set the software will automatically reserve the I O pair of the p side differential signal and back annotate the n side as signal name_n The Drive attribute sets the drive strength of the output and bi directional signals The values for the DRIVE attribute are found in
25. attice Semiconductor syslO Usage Guidelines for Lattice Devices LVCMOS25 LVCMOS25_OD The following tables describe the features supported by a Lattice device when the syslO interfaces are in 2 5V LVCMOS mode and the key specifications described in JEDEC Standard JESD8 5 Table 7 LVCMOS25 Features List Feature Value External Termination Required No Bus Maintenance Control UP DOWN LATCH OFF Slew Rate Control SLOW or FAST Drive Strength Control 4mA 5 33mA 8mA 12mA 16mA Open Drain Option LVCMOS25_OD 1 Refer to the Appendix for device specific values The items in bold are the default values Refer to Appendices for default drive strength values Table 8 LVCMOS25 DC Characteristics Parameter Symbol Parameter Description Min Typ Max Veco UO Supply Voltage 2 3 2 5 2 7 VREF Input Reference Voltage VIT External Termination Voltage Vou Output High Voltage lop Veco 0 4 VoL Output Low Voltage Ig E 0 4 Vin Input High Voltage 1 7 Note 1 Vu Input Low Voltage 0 3 0 7 1 Vi max value varies by device Please refer to the appendices for device specific Vu MAX values Lattice Semiconductor LVCMOS18 LVCMOS18_OD The following tables describe the features supported by a Lattice device when the syslO interfaces are in 1 8V syslO Usage Guidelines for Lattice Devices LVCMOS mode and the key specifications described in JED
26. cco o D x sysHSIO sysHSl9 x VREF E E VREF kd ki Q o BKo_Ioo 2 g St a sysHSI1 sysHSI8 S DS to t o BK0_IO61 BK5_IO61 GCLKO sysHSl2 sysHSI7 GCLK4 GCLK1 GCLK5 o PLL a a PLL V PLLo 3 3 VPLLI GPLLO PLL z o PLL GPLLI T GCLK2 PLL PLL GCLK6 GCLK3 GCLK7 PLL PLL BK1_100 to sysHSI3 sysHSI6 S BK1_l061 7 x E E oO kd ki VREF bel S sysHSl4 sysHSI5 S Vcco syslO Bank 2 syslO Bank 3 BK2_1O0 mp BK3_100 O H Ne x u W GND 8 E 0 to 8 D to GND A BK2_1061 x BK3_1061 44 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Differential Clock Inputs As shown in Figure 11 there are four clock pins one for each PLL on each side of the ispXPGA device These clock pins can be configured to meet one of single ended interface standards that all of the inputs and I Os Addi tionally they can be configured to interface with single ended LVPECL signals or two clock pins can be paired together to interface with differential LVDS or LVPECL signals As shown in Figure 12 when differential signaling is selected GCLKO and GCLK2 will be the positive input to the comparator while GCLK1 and GCLK3 will be the neg ative input to the comparator and GCLK4 and GCLK6 will be the positive input to the comparator while GCLK5 and GCLK7 will be the negative input to the comparator Figure 12 Clock Pairs for Differential Signali
27. ce voltage is required GOEO and GOE1 get this Ver from bank 2 Global Reset Pin The global Reset pin supports the same 14 interface standards as the user I O pins If an external reference volt age is required gets this Vaer from bank 2 37 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Device Specific syslO Features The two tables below lists the drive strength and the Vj characteristics for the LVCMOS syslO standards Also keep in mind that the internal pull ups and buskeeper latches for the IO pins are connected to the bank Vcco volt age and not the core Vcc for this device Table 45 LVCMOS Features and DC Characteristics Standard Drive Strength MA LVCMOS33 20 16 12 8 5 4 LVCMOS25 16 12 8 5 4 LVCMOS18 12 8 5 4 1 Defaults are in bold Table 46 LVCMOS Features and DC Characteristics Parameter Value LVCMOS33 Mu MAX 5 5V LVCMOS25 Mu MAX 3 6V LVCMOS18 Mu MAX 3 6V 38 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Appendix B ispMACH 5000B ispMACH 5000B syslO Banking Scheme The ispMACH 5000B devices are divided into four independent groups of I Os and inputs called bank The device has been designed such that there is a maximum of 14 syslO standard interfaces per ground with each ground capable of sinking 96mA of current Figure 3 shows the banking scheme for the isoMACH 5000B family of devices The banks in an isp
28. cifications described in JEDEC Standard JESD8 6 Table 35 HSTL_IV Features List Feature Value External Termination Required Yes Bus Maintenance Control OFF Slew Rate Control FAST Drive Strength Control No Open Drain Option No Table 36 HSTL_IV DC Characteristics Parameter Symbol Parameter Description Min Typ Max Veco UO Supply Voltage 1 4 1 5 1 6 Input Reference Voltage V 0 90 TT Vrer 0 5Vcco External Termination Voltage V V DE VTT VREF c9 Vu Input High Voltage Veer 0 1 Vu Input Low Voltage Ver 0 1 Vou Output High Voltage Veco 0 4 VoL Output Low Voltage 0 4 loH Output Current at Voy 8mA lot Output Current at VoL 48mA n HSTL_IV Termination Driving device Receiving device Vit Veco Vit Veco Voo 50 ohm 50 ohm he pad i pad A CD Z 50 ohm be LD Veer Vi GND HSTL_IV vsd 28 Lattice Semiconductor GTL The following tables describe the features supported by Lattice devices when the syslO interfaces are in the GTL model Table 37 GTL Features List syslO Usage Guidelines for Lattice Devices Feature Value External Termination Required Yes Bus Maintenance Control OFF Slew Rate Control FAST Drive Strength Control No Open Drain Option Yes Table 38 GTL DC Characteristics Parameter Symbol Parameter
29. ctors within a differential pair Use bypass capacitors at each package and make sure that each power and ground trace is wide and short with multiple vias to minimize inductance to the power planes Use multiple PCB board layers with dedicated planes for Vcc and Ground Avoid crosstalk between CMOS TTL signals and LVDS signals by designing the two signals on different lay ers of the board 31 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices BLVDS The following tables describe the features supported by a Lattice device when the syslO interfaces are in BLVDS mode BLVDS is used in bussed multi drop and multi point applications over backplanes or cables BLVDS boosts output drive current to 10mA to drive a heavily loaded bus Table 41 BLVDS Features List Feature Value External Termination Required Yes Bus Maintenance Control OFF Slew Rate Control N A Drive Strength Control N A Open Drain Option N A Table 42 BLVDS DC Characteristics Parameter Symbol Parameter Description Min Typ Max Units gt 2 3 2 5 2 7 V Veco I O Supply Voltage 30 33 36 V Vicm Input Common Mode Voltage 0 2 1 8 V Vrun Differential Input Threshold 100 mV ViN Input Voltage for Vip or Vin 0 2 4 V Vou Output High Voltage for Vop or Von 1 4 1 8 V VoL Output Low Voltage for Vop or Von 0 95 1 1 V Von Output Voltage Differential 240 300 460 mV AVop Change
30. de and the key specifications Table 43 LVPECL Features List Feature Value External Termination Required Yes Bus Maintenance Control OFF Slew Rate Control N A Drive Strength Control N A Open Drain Option N A Table 44 LVPECL DC Input Characteristics Parameter Symbol Parameter Description Min Typ Max Units Veco I O Supply Voltage 3 0 3 3 3 6 V Vicm Input Common Mode Voltage 0 2 1 8 V Vrun Differential Input Threshold 0 3 V VoH Output High Voltage 1 70 2 41 V VoL Output Low Voltage 0 96 1 57 V LVPECL Termination The following is an example of how termination is accomplished when using a differential LVPECL receiver When the LVPECL driver is either bi CMOS or bipolar in nature the termination will be two 509 resistors to V77 rather than a single 1009 across the differential inputs If Vyr is not available Thevenin s equivalent circuit may be used for the termination BI CMOS or Bipolar LVPECL Driver syslO LVPECL I I Driver l 1002 I pad MN I Ci l e pad 2 100Q MN I Bourns CAT16PC 4F12 35 LVPECL Receiver LVPECL Receiver ee ee Stee Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Appendix A ispMACH 5000VG ispMACH 5000VG sysl0O Banking Scheme Each ispMACH 5000VG device is separated into four independent groups of I Os and inputs called banks The device has been designed such that there i
31. e will be a single Veer pin and multiple Veco pins In addition each I O has configurable drive strength weak pull up weak pull down or a buskeeper latch Table 2 lists the syslO standards with the typical values for Voco VREF and VIT Figure 9 ispXPLD 5000MX Banking Scheme lt i lt GND f F Bank 0 I Os Bank 3 I Os Vecoio Veco Bank 0 Bank 3 VOs syslO Bank 0 syslO Bank 3 de GCLKO GCLK3 GCLKO GCLK1 el nn Dil Ji GCLK3 GCLK2 Differential Pair i Differential Pair GCLK1 GCLK2 Bank 1 Bank 2 S syslO Bank 1 syslO Bank 2 lo Veco Veco GND uf Bank 1 I Os In In Bank 2 I Os E GND Differential Clock Inputs As shown in Figure 9 there are two clock pins one for each PLL on each side of the ispXPLD 5000MX device These clock pins can be configured to meet one of the single ended interface standards that all of the inputs and I Os Additionally two clock pins can be paired together to interface with differential LVDS or LVPECL signals As shown in Figure 10 when differential signaling is selected GCLKO or GCLK3 will be the positive input to the comparator while GCLK1 or GCLK2 will be the negative input to the comparator 42 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Figure 10 Clock Pairs for Differential Signaling GCLKO GCLK3
32. er Vi GND HSTL_l vsd 26 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices HSTL_III The following tables describe the features supported by a Lattice device when the syslO interfaces are in HSTL Class III mode and the key specifications described in JEDEC Standard JESD8 6 Table 33 HSTL_III Features List Feature Value External Termination Required Yes Bus Maintenance Control OFF Slew Rate Control FAST Drive Strength Control No Open Drain Option No Table 34 HSTL_III DC Characteristics Parameter Symbol Parameter Description Min Typ Max Veco UO Supply Voltage 1 4 1 5 1 6 Input Reference Voltage V 0 90 REF Vrer 0 5Vcco External Termination Voltage V V DE VIT VREF c9 Vu Input High Voltage Vrer 0 1 z Vit Input Low Voltage Vrer 0 1 Vou Output High Voltage Veco 0 4 VoL Output Low Voltage 0 4 loH Output Current at Voy 8mA loL Output Current at VoL 24mA HSTL_III Termination Driving device Receiving device Vir Veco Voco T i 50 ohm i A pad i pad A lt gt Z 50 ohm i gt H Vee 0 9V GND E HSTL_IIl vsd 27 Lattice Semiconductor HSTL_IV The following tables describe the features supported by a Lattice device when the syslO interfaces are in HSTL syslO Usage Guidelines for Lattice Devices Class IV mode and the key spe
33. in the design source By using the macro the user has the ability to simulate and view both sides of the differential pair in the design source LVDS BLVDS and LVPECL IO_TYPES Usage with HDL Synplify and Precision RTL Synthesis support syslO LVDS and BLVDS using attribute passing and the IO_TYPES attribute with VHDL and Verilog much the same as pin locations pull ups and slew rates are already controlled Similarly ABEL HDL passes properties to the place and route tools as they are currently used Below are examples of how each HDL supports syslO LVDS using the IO_TYPES attribute Verilog with Synplify synthesis IO TYPES LVDS Verilog with Precision RTL Synthesis pragma attribute PinName IO TYPES LVDS VHDL ATTRIBUTE IO TYPES string ATTRIBUTE IO TYPES OF PinName SIGNAL IS LVDS ABEL LVDS BLVDS LVPECL Macro Definition Like the IO_TYPES attribute the n side of the macro does not have to be connected leaving only the p side to be simulated Below are macro symbols of differential syslO Figure 1 LVDSIN BLVDSIN and LVPECLIN Macro Symbol Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Figure 2 LVDSOUT BLVDSOUT and LVPECLOUT Macro Symbol P_OUT N OUT Figure 3 LVDSTRI BLVDSTRI and LVPECLTRI Macro Symbol OE P_OUT Il N_OUT Figure 4 LVDSIO and BLVDSIO Macro Symbol OE I Pot 0 NIO O LVDS BLVDS and LVPECL Macro Usage with HDL Syn
34. ination Driving device Receiving device Va 0 45V ee I Yoo R 50 ohm sE pad 25 ohm pad CD Z 50 ohm Hib WA l E Ver Vir GNDIO sstl3_l vsd 20 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices SSTL3_II The following tables describe the features supported by a Lattice device when the syslO interfaces are in 3 3V SSTL Class Il mode and the key specifications described in JEDEC Standard JESD8 8 Table 21 SSTL3_II Features List Feature Value External Termination Required Yes Bus Maintenance Control OFF Slew Rate Control FAST Drive Strength Control No Open Drain Option No Table 22 SSTL3_II DC Characteristics Parameter Symbol Parameter Description Min Typ Max Veco UO Supply Voltage 3 0 3 3 3 6 Input Reference Voltage V 1 3 1 5 1 7 REE Vrer 0 45Vcco External Termination Voltage V 1 3 1 5 1 7 DE Vit VREF ViH Input High Voltage VREF 0 2 Veco 0 3 Vit Input Low Voltage 0 3 Vrer 0 2 Vou Output High Voltage Veco 0 9 VoL Output Low Voltage 0 5 loH Output Current at Voy 16mA lot Output Current at VoL 16mA SSTL3_II Termination Driving device Receiving device V 0 45Voco Vir 0 45Vecq Voo 50 ohm 50 ohm d pad 25 ohm pad A MN Z 50 ohm J dd il Vi Vier GND sstl3_Il vsd 21 Lattice Semiconductor syslO Usage Guidelines for Lat
35. lass IV Yes Yes GTL Yes Yes Yes Yes Yes LVPECL Yes Yes Yes Yes Yes LVDS Yes Yes Yes Yes Yes BLVDS Yes Yes Only available on the CLOCK inputs Outputs require external resistor network Non sysHSI mode outputs require external resistor network Support for outputs in non sysHSI mode only outputs require an external resistor network Software setting for PCIX is the same as PCI OD P GO A Table 2 sysIO Standards with the Typical Values for Veco VREF and Vrr syslO Standard Veco VREF VIT LVTTL 3 3V LVCMOS 3 3 3 3V LVCMOS 2 5 2 5V LVCMOS 1 8 1 8V POA T aay dare PCIX 3 3V AGP 1X 3 3V SSTL3 Class II 3 3V 1 5V 1 5V SSTL2 Class II 2 5V 1 25V 1 25V CTT3 3 3V 1 5V 1 5V CTT2 2 5V 1 5V 1 5V HSTL Class 1 5V 0 75V 0 75V HSTL Class III 1 5V 0 9V 1 5V HSTL Class IV 1 5V 0 9V 1 5V GTL 1 0V 1 5V LVPECL 3 3V WS e di lU e BLVDS 2 5V 3 3V Gg 1 ispXPGA supports 2 5V only Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Bus Maintenance Selections The Lattice devices supporting syslO interfaces allow designers to choose between having a weak pull up resistor a weak pull down resistor a bus friendly latch or nothing on every I O and input with the exception of TCK TMS TDI TDO and TOE For additional information o
36. le to implement a subset of the supported standards based on the Veco and Ver chosen The dedicated input and global clock pin configurations are also set based on the bank levels for Veco and Vor I O pins can be configured to be inputs outputs or bi directional I Os When an I O is configured as an input pin its assignment to a given bank will only be a function of Vor as inputs are independent of Veco The Vr_r levels for the terminated syslO standards are given in Table 1 There are no two terminated input standards that have the same Vper level As a result only one of the terminated standards can be implemented in a given bank for inputs and I Os If the syslO standard selected is one of the non terminated interfaces then that input can be placed in any bank When an I O is configured as an output pin its assignment to a bank is determined by the Vcco of that bank When an I O is configured as a bi directional I O pin using a terminated syslO standard both Vaer and Vcco are required In this instance other pins configured as I Os or inputs will have to be compatible with Vor and outputs will have to be compatible with Veco syslO Standard Descriptions The following are the descriptions of each of the standards that can be implemented with a Lattice syslO Stan dards The descriptions include information about the electrical characteristics of the interface standard along with the different properties that apply to the interface and accep
37. lock pins LAT IOTYPES C1k0 LVDS 0 LAT IOTYPES Clk2 LVPECL D 2 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Verilog with Synplify Syntax PinType PinName synthesis IO TYPES Type DriveCurrent Example module vlogio md Din C1k0 C1k1 C1k2 C1k3 portA portB portC portD portE IO types for Clock pins input C1k0 synthesis IO TYPES LVDS PIN input Clk2 synthesis IO TYPES LVPECL D PIN input C1k3 will take the default type LVCMOS33 IO types for I O pins input 1 0 md synthesis IO TYPES PCI PIN input 4 0 Din output 4 0 portA synthesis IO TYPES PCI PIN output 4 0 portB synthesis IO TYPES LVCMOS33 PIN 20 output 4 0 portC synthesis IO TYPES CTT33 PIN output 4 0 portD synthesis IO TYPES LVCMOS25 OD PIN 8 output 4 0 portE synthesis IO TYPES LVDS PIN reg 4 0 portA reg 4 0 portB reg 4 0 portc reg 4 0 portD reg 4 0 portE Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Verilog with Precision RTL Synthesis Syntax pragma attribute PinName IO TYPES Type DriveCurrent Example module vlogio md Din C1k0 C1k1 C1k2 C1k3 portA portB portC portD portE input 1 0 md input 4 0 Din input C1k0 C1k1 C1k2 C1k3 output 4 0 portA output 4 0 portB output 4 0 portc output 4 0 portD output 4 0 portE reg 4 0 portA reg 4
38. lock pins can be paired together to interface with differential LVDS or LVPECL signals As shown in Figure 2 when differential signaling is selected GCLKO or GCLK3 will be the positive input to the comparator while GCLK1 or GCLK2 will be the negative input to the comparator Figure 6 Clock Pairs for Differential Signaling GCLKo CO lt _ GCLK3 CLKO CLK3 GCLK1 gt GCLK2 Each global clock input is associated with the adjacent bank of I O cells If a reference voltage is required for a clock input it is obtained from the associated bank In this way CLKO gets Vref from bank 0 CLK1 gets Vrer from bank 1 and so on This is the reason that the clock inputs are located at the bank boundaries as shown previously in figure 1 This scheme allows the clock inputs to support syslO standards without requiring separate Voer pins Control Pin Interfaces The test and programming pins TCK TMS TDI TDO and TOE are independent of the banks The TOE pin uses the core supply level Voc to set the input threshold and output drive levels and is compatible to the LVCMOS 3 3 interface standard The 1149 1 TAP pins TCK TMS TDI and TDO have their own supply pin Vccy That supply pin must be set to be compatible with one of the three LVCMOS interface standards Global Output Enable Pins GOE0 GOE1 The global Output Enable pins support the same 14 interface standards as the user I O pins If an external refer en
39. n drain out put Veco is not required because there is no internal pull up circuitry used with the possible exception of the bus maintenance circuit Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Design Guidelines for Simultaneously Switching Outputs Anytime multiple outputs switch ground bounce concerns must be taken into account Ground bounce is the result of a high amount of current changing in the inductance of the ground pins bond wires and ground plane of the device When this happens the voltage level of the internal ground will differ from the voltage level of the external ground which will effectively change the level of the output signals Additionally the internal logic may also be affected by this phenomenon because the difference between ground and the supply voltage inside the device may be incorrect for a short period Lattice devices have been designed such that there is a certain maximum amount current that each bank can sink This current varies according to the device chosen Refer to the corresponding Appendix for detailed information Additionally the ground pins for each bank are independent from those in other banks to improve noise isolation due to several I Os switching simultaneously The voltage level difference between grounds in different banks or between a bank and the core ground should be no more than 200mV If the warning is generated there are a couple of simple steps that can be taken to
40. n the drive capabilities of each of the bus maintenance options refer to the device data sheets The TMS TDI TDO and TOE pins have weak pull up circuits while the TCK pin has nothing The default selection when using an unterminated I O interface standard is a weak pull up resistor When using one of the terminated I O standards on a given I O or input pin the software will disable bus maintenance circuitry because the terminated I O standards will always use specific termination resistors external to the device The same is true for clock inputs that have been paired together for differential signaling as the differential inputs are usually terminated to each other The Vcc Or Veco depending on the device sources both the pull up resistor and the bus friendly latch If an input pin is configured to meet an I O standard that has a Vu greater than the source voltage of the pull up resistor or bus friendly latch it is recommended that either an external pull up resistor be used or the bus maintenance circuit be configured to be a pull down resistor syslO Options for Unterminated Interface Standards Several additional features are available when selecting either the LVTTL or one of the LVCMOS interface stan dards These features include programmable slew rate programmable output drive strength and open drain capa bility A full description of each of the syslO interface options is listed in the descriptions of the individual syslO interface
41. ng GCLKO gt lt GCL CLKI CLK2 GCLK1 gt H J GCLK3 GCLK4 gt lt _ GCLK6 o CLK3 CLK4 GCLK5 _ J I J GCLK7 Control Pin Interfaces The test and programming pins TCK TMS TDI TDO TOE and CFG0 are independent of the banks The TOE pin uses the core supply level Vcc to set the input threshold and output drive levels and will be compatible to the LVC MOS interface standard associated with that core supply level The 1149 1 TAP pins TCK TMS TDI and TDO have their own supply pin Vecu Global Reset Pin The global Reset pin supports the same syslO interface standards as the user I O pins If an external reference voltage is required gets this Vag from Bank 3 Device Specific syslO Features The two tables below lists the drive strength and the Vj characteristics for the LVCMOS syslO standards Also keep in mind that the internal pull ups and buskeeper latches for the IO pins are connected to the bank Veco for this device Table 51 LVCMOS Features and DC Characteristics Standard Drive Strength MA LVCMOS33 20 16 12 8 5 33 4 LVCMOS25 16 12 8 5 33 4 LVCMOS18 12 8 5 33 4 1 Defaults are bolded Table 52 LVCMOS Features and DC Characteristics Parameter Value LVCMOS33 Vu MAX 3 6V LVCMOS25 Viy MAX 3 6V LVCMOS18 Vu MAX 3 6V 45 Lattice Semiconductor syslO Usage Guidelines
42. oL Output Low Voltage _ Vrer 0 4 lou Output Current at Voy 8mA _ _ lot Output Current at VoL 8mA CTT25 Termination Driving device Receiving device V 1 5V 10 Voo 50 ohm I pad pad sa Z 50 ohm i mbe cL Vor Vier GND 25 Lattice Semiconductor HSTL_ The following tables describe the features supported by a Lattice device when the syslO interfaces are in HSTL Class mode and the key specifications described in JEDEC Standard JESD8 6 Table 31 HSTL_I Features List syslO Usage Guidelines for Lattice Devices Feature Value External Termination Required Yes Bus Maintenance Control OFF Slew Rate Control FAST Drive Strength Control No Open Drain Option No Table 32 HSTL_I DC Characteristics Parameter Symbol Parameter Description Min Typ Max Veco UO Supply Voltage 1 4 1 5 1 6 Input Reference Voltage V 0 68 0 75 0 90 hai Vrer 0 5Voco External Termination Voltage Vv 0 5V TT Vrt VREF cco Vin Input High Voltage Vrer 0 1 Vit Input Low Voltage Voer 0 1 Vou Output High Voltage Veco 0 4 VoL Output Low Voltage E 0 4 loH Output Current at Voy 8mA lot Output Current at VoL 8mA _ HSTL_I Termination Driving device Receiving device Vrr 0SVoco Voco T i 50 ohm i A pad i pad A lt gt Z 50 ohm i be LD Vo
43. r syslO Usage Guidelines for Lattice Devices Table 3 VHDL Verilog syslO Attributes Attribute Name Possible Values IO_TYPES LVCMOS33 LVCMOS33_OD LVTTL PCI AGP_1X LVCMOS25 LVCMOS25_0D LVCMOS18 LVCMOS18_OD SSTL3_I SSTL3_II SSTL2_I SSTL2_II CTT33 CTT25 HSTL_I HSTL_III HSTL_IV GTL LVDS BusLVDS LVPECL BANK_NO 0 1 2 3 4 5 6 7 DRIVE 4 5 8 12 16 20 NONE PULL UP DOWN LATCH OFF SLEW FAST SLOW Below are examples of ABEL VHDL and Verilog code that demonstrate usage of syslO attributes Additional infor mation on constraint usage is found in the help files and usage documentation for the design software ABEL MODULE abel io library lattice mdl md0 pin Din4 Din0 pin C1k3 C1k0 pin port19 port0 pin istype reg IO Types for input pins LAT IOTYPES md0 PCI LAT IOTYPES mdl PCIX IO Types for output pins LAT IOTYPES port2 AGP_1X LAT _IOTYPES port3 SSTL3_I LAT IOTYPES port5 SSTL2 I LAT IOTYPES port7 HSTL I LAT _IOTYPES port8 HSTL_III LAT _IOTYPES port9 HSTL_IV LAT _IOTYPES portl0 CTT3 LAT _IOTYPES portll LVTTL LAT _IOTYPES port12 LVCMOS33 20 LAT _IOTYPES port13 LVCMOS33_0D LAT IOTYPES port14 LVCMOS25_0D 8 LAT IOTYPES port15 LVCMOS18 5 LAT IOTYPES port16 LVCMOS18_0D 4 LAT IOTYPES port17 LVDS LAT IOTYPES port18 BLVDS IO types for c
44. s a maximum of 14 syslO standard interfaces per ground with each ground capable of sinking 96mA of current Figure 1 shows the banking scheme for the ispMACH 5000VG family of devices The banks in an ispMACH 5000VG device are numbered from zero to three as are the Vcco and Ver inputs for that bank In each bank there will be a single Veer pin and multiple Veco pins In addition each I O has configurable drive strength weak pull up weak pull down or a buskeeper latch Table 2 lists the syslO standards with the typical values for Veco Vref and VT Figure 5 isp MACH 5000VG Banking Scheme lt i lt GND Bank 0 I Os Bank 3 I Os Vecoio Veco Bank 0 Bank 3 VOs syslO Bank 0 syslO Bank 3 Os GCLKO GCLK3 GCLKO GCLK1 EE Ee EE JI GCLK3 GCLK2 Differential Pair i Differential Pair GCLK1 d GCLK2 Bank 1 Bank 2 pa syslO Bank 1 i syslO Bank 2 Ges Veco Veco 5 GOEO lt GND m Bank 1 I Os GOE1 Bank 2 I Os fu eidis E i RESETB D 36 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Differential Clock Inputs As shown in Figure 1 there are two clock pins on each side of an ispMACH 5000VG device These clock pins can be configured to meet one of the fourteen single ended interface standards that all of the inputs and I Os support Additionally two c
45. standards Programmable Slew Rate To assist the user with noise at the system level a programmable slew rate option has been added to every I O pin Signals that require high performance should use the FAST slew rate option Care should be taken to properly ter minate the signal by using a series termination resistor so that transmission line effects and reflections do not cause problems Signals that are not as critical should be set to SLOW slew rate The default slew rate setting in the design software for all signals is FAST The slew rates for the individual devices will be found in the device data sheets Programmable Output Drive Strength Another method that can be used to control noise and power consumption issues is to control the output drive strength The sink or source capability varies by the device family chosen Refer to the appropriate Appendix for the family relevant information Having this capability can allow for better impedance matching and improved perfor mance for signals that are heavily loaded with capacitance The output drive strength levels are provided in the descriptions of each of the individual syslO interface standards and represent the minimum drive strength settings Open Drain I O Configuration All I Os and outputs can be configured to be open drain for use on busses that can only be driven to logic high either by another device or by using an external pull up resistor When an I O is configured to be an ope
46. table values for each property Additionally for termi nated I O standards circuit examples will be given to demonstrate typical termination techniques Any device specific information like drive strength V 4 Voy values etc are listed in the respective appendices Lattice Semiconductor syslO Usage Guidelines for Lattice Devices LVCMOS33 LVCMOS33_OD The following tables describe the features supported by a Lattice device when the syslO interfaces are in 3 3V LVCMOS mode and the key specifications described in JEDEC Standard JESD8B Table 5 LVCMOS33 Features List Feature Value External Termination Required No Bus Maintenance Control UP DOWN LATCH OFF Slew Rate Control SLOW or FAST Drive Strength Control loH lot ORO 8mA 12mA 16mA 20mA 24m Open Drain Option LVCMOS33_OD 1 Refer to the Appendix for device specific values The items in bold are the default values Refer to Appendices for default drive strength values Table 6 LVCMOS33 DC Characteristics Parameter Symbol Parameter Description Min Typ Max Veco UO Supply Voltage 3 0 3 3 3 6 VREF Input Reference Voltage VIT External Termination Voltage Vou Output High Voltage IOH 2 4 VoL Output Low Voltage IOL 0 4 Vin Input High Voltage 2 Note 1 Vu Input Low Voltage 0 3 0 8 1 Mu max value varies by device Please refer to the appendices for device specific Vu MAX values L
47. tage IOL 0 1Vcco Vin Input High Voltage 0 5Vceco Note 1 Vu Input Low Voltage 0 3 0 3Vcco 1 Vi max value varies by device Please refer to the appendices for device specific Vu MAX values device specific VIH values 2 In this specification Vcco refers to the Voco of the driving device It is assumed that Vcc of the receiv ing device tracks Vcco Some devices use absolute values Lattice Semiconductor syslO Usage Guidelines for Lattice Devices SSTL3_I The following tables describe the features supported by a Lattice device when the syslO interfaces are in 3 3V SSTL Class mode and the key specifications described in JEDEC Standard JESD8 8 Table 19 SSTL3_I Features List Feature Value External Termination Required Yes Bus Maintenance Control OFF Slew Rate Control FAST Drive Strength Control No Open Drain Option No Table 20 SSTL3_1 DC Characteristics Parameter Symbol Parameter Description Min Typ Max Veco I O Supply Voltage 3 0 3 3 3 6 Input Reference Voltage V 1 3 1 5 1 7 REF Vrer 0 45Vcco External Termination Voltage V 1 3 1 5 1 7 Vit VREF Vin Input High Voltage VREF 0 2 Veco 0 3 Vit Input Low Voltage 0 3 Voer 0 2 VoH Output High Voltage Vcco 1 1 VoL Output Low Voltage 0 7 loH Output Current at Voy 8mA _ _ lot Output Current at VoL 8mA E SSTL3_I Term
48. the descriptions for the standards that support this capability Boundary Scan Test with syslO interface Boundary scan test of a board or system is often performed before device programming to ensure proper connec tivity Device programming times are usually greater than two seconds per device and are based on the speed of the test equipment and the configuration of the programming chain Boards with long programming chains will nat urally take longer to program consuming precious board test time and resources By doing the connectivity testing before programming board test time can be minimized when an error is discovered and prevents possible conten tion issues as a result of the programmable devices being programmed and becoming active To allow for testing a board before fully programming a device devices with the syslO capability have also been designed with a Quick syslO configuration capability that allows for the configuration of the I Os without affecting the logic in the device Only the physical nature of the I Os is affected This capability is provided through Lattice s ispVM System programming software please refer to the isoVM System User Manual for more information syslO Banking Scheme Each device is separated into independent groups of I Os and inputs called banks The number of banks is device dependent see individual device appendix for more details Each bank has its own resources for GND Veco and Veer and will be ab
49. thesis tools such as Synplify and Precision RTL Synthesis black box the VHDL and Verilog instantiations and pass them through an EDIF netlist to the Lattice software The Lattice software converts the black box into the physical representation of the syslO LVDS buffers within the device using the macros defined above Unlike other HDLs ABEL requires special additions to support differential macro functionality the Lattice design tools provide direct support for ABEL and have been modified to support differential macro functionality Below are VHDL Verilog and ABEL examples of instantiating these modules in the source code Table 1 lists the acronyms that apply to the syntax Table 4 syslO Differential VO Acronyms Acronym Definition P_IN The p side of the DIFFERENTIAL I O input N_IN The n side of the DIFFERENTIAL I O input O The output of the DIFFERENTIAL WO input or bi directional buffer I The input of the DIFFERENTIAL I O output or bi directional buffer P_OUT The p side of the DIFFERENTIAL I O output N_OUT The n side of the DIFFERENTIAL I O output OE The output enable of the DIFFERENTIAL I O output or bi directional buffer P_IO The p side of the DIFFERENTIAL I O bi directional signal N_IO The n side of the DIFFERENTIAL I O bi directional signal Lattice Semiconductor syslO Usage Guidelines for Lattice Devices Verilog LVDSIN Il P_IN IN P N IN IN N O NODE LVDSOUT
50. tice Devices SSTL2_1 The following tables describe the features supported by a Lattice device when the syslO interfaces are in 2 5V SSTL Class mode and the key specifications described in JEDEC Standard JESD8 9 Table 23 SSTL2 Features List Feature Value External Termination Required Yes Bus Maintenance Control OFF Slew Rate Control FAST Drive Strength Control No Open Drain Option No Table 24 SSTL2_ DC Characteristics Parameter Symbol Parameter Description Min Typ Max Veco UO Supply Voltage 2 3 2 5 2 7 Input Reference Voltage V 1 15 1 25 1 35 REE Veer 0 5Voco External Termination Voltage V 1 15 1 25 1 35 m Vit VREF Vin Input High Voltage VREF 0 18 Veco 0 3 Vu Input Low Voltage 0 3 Vrer 0 18 VoH Output High Voltage Veco 0 62 _ VoL Output Low Voltage 0 54 loH Output Current at Voy 7 6mA loL Output Current at VoL 7 6MA SSTL2_I Termination Driving device Receiving device V 0 5V ego I Voo i 50 ohm d pad 25 ohm pad ot Maer Vi GND 22 Lattice Semiconductor syslO Usage Guidelines for Lattice Devices SSTL2_Il The following tables describe the features supported by a Lattice device when the syslO interfaces are in 2 5V SSTL Class Il mode and the key specifications described in JEDEC Standard JESD8 9 Table 25 SSTL2_ Il Features List
51. uctor syslO Usage Guidelines for Lattice Devices Appendix D ispXPGA ispXPGA syslO Banking Scheme Each ispXPGA device is separated into eight independent groups of I Os and inputs called banks The device has been designed such that there is a maximum of 12 syslO standards per ground The average DC current drawn by I Os between adjacent bank GND connections or between the last GND in an I O bank and the end of the I O bank shall not exceed n 8mA Where n is the number of I Os between bank GND connections or between the last GND in a bank and the end of a bank Figure 11 shows the banking scheme for the ispXPGA family of devices The banks in a ispXPGA device are numbered from zero to seven as are the Voco and Vper inputs for that bank In each bank there will be a single Vrep pin and multiple Veco pins In addition each I O has configurable drive strength weak pull up weak pull down or a buskeeper latch Table 2 lists the syslO standards with the typical values for Voco VREF and VIT Figure 11 ispXPGA Banking Scheme BK7_100 BK6_100 Q Q GND e i o sE to S i to GND da BK7_1061 BK6_1061 syslO Bank 7 syslO Bank 6 Vcco V

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