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ModelSim Designer Tutorial

1. al Package List LIBRARY ieee USE ieee std lodic 1164 all USE ieee std logic arith all Declarations Ports 3 bit address bus addr IN std logic vector 2 DOWNTO clk IN std logic 10 MHz clock cs IN std logie chip select 8 bit data in bus from cpu data in IN std logic vector 7 DOWNTO nrw IN std logic read write l rst IN std logic reset sin IN std logie serial input 8 bit data out bus to cpu data out OUT std logic vector 7 DOWNTO 0 int OUT std logic interrupt 1 sout OUT std logic serial output M ki INSS WSS SSG NEE ER Symbol B 2 A Ll l 2 8 ON SIE AS A 2 05 OH Ready 2 Figure 11 An HDL view of uart_top Wart top struct vhd ID C0 J M n OF Tu p PH 12 13 14 15 15 17 18 VHDL Entity NART uart top syubol Created s by darronn UNENOWN at 10 57 21 14 09 2004 Generated by Mentor Graphics Model im Designer TH LIBRARY ieee USE ieee std logic 1164 11 USE ieee std logic arith all ENTITY uart top IS PORTi S bit address bus addr IM std logic vector iz BOWNTO 0 clk IM std logic 10 MHz clock cs IN std logic chip select n PRE 2 View Side Data pane a Right click in the Design tab and select Show Side Data Figure 12 Increase the size of the Workspace if necessary The Side Data pane
2. Figure 58 Viewing the memories tab in the Main window workspace Viewing a memory wore Memories can be viewed via the ModelSim GUI Wars space 1 Memory instance ram 1 mem 4095 Of ram tb spram2 mem 0 2047 tam tb spram3 mem 0 65535 4036 2045 65536 a Select View gt Debug Windows gt Memory The Memories tab opens in the Workspace pane Figure 58 and lists the memories in the current design context ram_tb with the range depth and width of each memory b VHDL The radix for enumerated types is Symbolic To change the radix to binary for the purposes of this lesson type the following command at the vsim prompt VSIM gt radix bin c Double click the ram_tb spram I mem instance in the memories list to view its contents A mem tab is created in the MDI frame to display the memory contents The data are all X 0 in VHDL since you have not yet simulated the design The first column blue hex characters lists the addresses Figure 59 and the remaining columns show the data values d In the Memories tab of the Workspace double click instance ram tb spram2 mem This creates a new tab in the MDI frame called mem 1 that contains the addresses and data for the spram2 instance Each time you double click a new memory instance in the Workspace a new tab is created for that instance in the MDI frame ModelSim Designer Tutorial El Aram tb spramd mem 0 3 db am tb d
3. You should see blue vertical lines and numbers defining an area to zoom in Figure 52 c Select View gt Zoom gt Zoom Last The waveform pane returns to the previous display range d Click the Zoom In 2x icon a few times e Inthe waveform pane click and drag up and to the right You should see a blue line and numbers defining an area to zoom out Figure 53 f Select View gt Zoom gt Zoom Full Zooming the waveform display T 75 Figure 52 Zooming in with the mouse pointer wave default NE R x File Edit wiew Insert Format Tools Window ftest_counterclk 0 4 counter reset 0 FE est counter count 00110010 How 1000 ns Cursor 1 Ins 4 KE D ns ta 1 us How 1 us Delta 2 1b Figure 53 Zooming out with the mouse pointer wave default M N o xi File Edit View Insert Format Tools Window 4 fest counter clk 0 uc counter reset 0 E test_counter count 00110010 m sl 1 Z 1 T How 1000 ns Cursor 1 ns E Hi KT WO 250 ns to 357 ns Mow 1 us Delta 2 ModelSim Designer Tutorial T 76 Lesson 5 Viewing simulations in the Wave window Usi ng cursors in the Wave wi ndow Figure 54 Working with a single cursor in the Wave window wave defaut EN riz File Edit Insert Format Tools Window Cursors mark simulation time in the Wave window When ModelSim first draws the Wave window it places one cursor at time zero Clicking any
4. xa an FANDEN oQEmpRULPEKCEUSUFXaE ak ModelSim Designer application note Using ModelSim Designer m your design flow ModelSim Designer datasheet Design Creation to Realization Select Jumpstart to x Dont show this dialog again Ss Mods nol Jumpstart M Figure 3 The uart project 2 FA Workspace Project CMS Designer lv Library 5 Designer address de Block 4 epu interfaceBlock serial inter Black 5 status_reqgis Block 2 tester Black mit rev c Block clock divider Component Component Component Component Component ge Package Navigating the ModelSim interface The window you are now looking at is called the ModelSim Main window It is composed of a number of panes and sub windows that display various types of information about your design simulation or debugging session You can also access other tools from the Main window that display in stand alone windows e g block diagram editor Dataflow window List window The following table describes some of the key parts of the Main window Window pane Description This pane comprises multiple tabs that contain various sorts of information about the current project or design Once a design is loaded additional tabs will appear See Workspace GR 21 in the ModelSim GUI amp Editor Reference for more information Workspace The Transcript pane provides a
5. S m Advanced Verification and Debugging Designer Tutorial Version 6 0a Published October 12 2004 T 2 This document is for information and instruction purposes Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice and the reader should in all cases consult Mentor Graphics to determine whether any changes have been made The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL INDIRECT SPECIAL OR CONSEQUENTIAL DAMAGES WHATSOEVER INCLUDING BUT NOT LIMITED TO LOST PROFITS ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES RESTRICTED RIGHTS LEGEND 03 97 U S Government Restricted Rights The SOFTWARE and documentation have been developed entirely at private expense and are commercial computer software p
6. none alarm end_count stop 1 none entry point standby none none end_count exit point Transitions for Verilog Origin State Destination State Priority none Condition none Actions suspended counting 1 stop none counting suspended 2 stop none counting alarm ZETO none standby counting start none standby alarm ZETO none alarm end count stop none entry point standby none none end_count exit point none none Creating a hierarchical state machine T 65 Your diagram should look similar to the one shown below 1 ebarem 1 kokk 1 ek arem T beep Item T Click the button to save the state diagram Although it is displayed in a separate tab a child hierarchical diagram is a partial view of a state machine and the parent and child diagrams are saved as a single design unit view GraphTutor Control fsm sm ModelSim Designer Tutorial T 66 Lesson 4 Creating state diagrams Editing state machine properties Figure 47 Changing signal status State Machine Properties VAN 3 x There are anumber of properties associated with a state machine that can be edited using the State Machine Properties dialog box Dutput Local sign Type Scope Hide unneeded labels Click
7. Portions or all of certain Software may contain code for experimental testing and evaluation Beta Code which may not be used without Mentor Graphics explicit authorization Upon Mentor Graphics authorization Mentor Graphics grants to you a temporary nontransferable nonexclusive license for experimental use to test and evaluate the Beta Code without charge for a limited period of time specified by Mentor Graphics This grant and your use T 109 ModelSim Designer Tutorial T 110 License Agreement of the Beta Code shall not be construed as marketing or offering to sell a license to the Beta Code which Mentor Graphics may choose not to release commercially in any form If Mentor Graphics authorizes you to use the Beta Code you agree to evaluate and test the Beta Code under normal conditions as directed by Mentor Graphics You will contact Mentor Graphics periodically during your use of the Beta Code to discuss any malfunctions or suggested improvements Upon completion of your evaluation and testing you will send to Mentor Graphics a written evaluation of the Beta Code including its strengths weaknesses and recommended improvements You agree that any written evaluations and all inventions product improvements modifications or developments that Mentor Graphics conceived or made during or subsequent to this Agreement including those based partly or wholly on your feedback will be the exclusive property of Mentor Graphics Mentor Gra
8. WLF files datasets and virtuals UM 147 pathname efault ftest_ringbuf ring_INST txc ftest_ringbuf ring_INST clock test ringbuf ring INST reset ftest_ringbuf ring_INST test ringbuf ring INST outstr ftest_ringbuf ring_INST block test rinabuf ring INST block test rinabuf rinq INST block test rinabuf rina INST block test ringbuf ring INST block ftest_ringbuf ring_INST block ftest_ringbuf ring_INST block ftest_ringbuf ring_INST block test_ringbuf ring_INST block test ringbuf ring INST block ftest_ringbuf ring_INST block ftest_ringbuf ring_INST block value B false false true true false 1 100001001 100001001 sto 100001001 sto 0701701710100 001101110100117 1 Figure 50 The Wave window and its many panes waveform iol xi x i EL ER EN 9 1100 7100000101 100000110 1100000111 100001000 100001001 1000 _ 1100 4100000101 100000110 41000007171 100001000 100007007 1000 _ 100 100000101 100000170 100000111 100001000 100091001 1000 _ zi Now 500000 ns 462300 ns 70 ns B 483000ns imis 24 451988 ns to 463241 ns Now 500 us Delta 2 cursor name cursor value cursor N ModelSim Designer Tutorial Loading a project and design For the examples in this lesson we have used the project named example that you
9. text Figure 55 b Type A and press Enter The cursor name changes to A 3 Jump the cursor to the next or previous transition a Click signal count in the pathname pane a Click the Find Next Transition icon on the Wave window toolbar The cursor jumps to the next transition on the currently selected signal b Click the Find Previous Transition icon on the Wave window toolbar The cursor jumps to the previous transition on the currently selected signal Working with multiple cursors 1 Add a second cursor a Click the Add Cursor icon on the Wave window toolbar b Right click the name of the new cursor and delete the text Type B and press Enter d Drag cursor B and watch the interval measurement change dynamically Figure 56 Using cursors in the Wave window T 77 Figure 55 Renaming a cursor wave default R x File Edik View Insert Format Tools Window 4 test counter clk 1 4 test counter reset Fi test counter count 00010011 Mow 1000 nz Cursor 1 372 ns m B 4 FE 177 ns to 448 ns Now 1 us Delta 2 P Bile 1111 eS SS Se Se ee i 2a Figure 56 Interval measurement between two cursors wave default b 7 Bl x File Edit View Insert Format Tools Window 2 test_counter clk 2 counter reset 70 FE test counter count 00001110 3 11 0 How 1000 ns 281 ns B B di 199 ns Ji 177 n
10. v Add C Modeltech6 0a_deexamples counter vhd counter hd C Modeltech6 0a_de examples tcounter vhd tcounter vhd Add All gt gt Liemeun SS Remove lt lt Remove All Click here to save these filenames to a text file filelist Save Use absolute pathnames for filelist k ci b lt Back Next gt Cancel 2 ModelSim Designer Tutorial T 34 Lesson 2 Working with ModelSim Designer A counter and its testbench appear in the Design tab Figure 19 ModelSim Designer Tutorial Figure 19 Counter and testbench imported into the project S Workspace M Workspace E Ea E AE o Type Path Filename PEE example Project 5 Designer work Library 5 Designer PM Mew dE counter Component ug test counter Component Lesson wrap up This concludes this lesson At this point you are ready to explore the design editor and debugging tools that comprise ModelSim Designer Design editor lessons Lesson 3 Creating block diagrams Lesson 4 Creating state diagrams Debugging tool lessons Lesson 5 Viewing simulations in the Wave window Lesson 6 Viewing and initializing memories Lesson 7 Simulating with Code Coverage Lesson wrap up T 35 ModelSim Designer Tutorial T 36 Lesson 2 Working with ModelSim Designer ModelSim Designer Tutorial Lesson 3 Creating block diagrams Topics The following topics are covered in this lesson Intro
11. Declarations Set i i Wait State State Signal Names Module Declarations in the case of Verilog label on the state diagram __ Settings ad Crea ans and vvill be included as architecture declarations module declarations in c rose ees the case of Verilog when is generated the state machine s gnals status is displayed as well ModelSim Designer Tutorial T 68 Lesson 4 Creating state diagrams 5 Click the button to save the state diagram Figure 49 The finished state diagram Your state machine should now look similar to the one shown in Figure 49 Architecture Declarations Signals Status Constant MOUGHTS std_logic_weetor D DDDODODO SILHAL SCOPE DEFAULT RESET STATUS beep TT m m REL rlrar TT it Package List hold Our r P WE LIBRARY ieee load OUT COME USE ieee std logic 1164 ali USE ieee std logic arith all ModelSim Designer Tutorial Simulate the control block Even though the block diagram isn t complete you won t define the counter block in this exercise you can still simulate the control block for demonstration purposes Load the control block From the state diagram editor select Simulation Start b Select Yes when prompted to enable data capture and show animation ModelSim compiles and loads the control block Notice too that a number of new toolbar buttons for controlling the simulation show up at the
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13. Switch to the Source window Du DU ee mm cL red X indicates that a statement in that line has not been ES C 5 0 Tutarial examples cov executed zero hits repeat 40000 begin green E indicates a line that has been excluded from code for loop loop 2000 coverage statistics posedge clk ctrli h5j posedge clk wt wdi hl 0 haal posedge clk wt wdi hz hbb posedge clk wt blkEi h30 hcc posedge clk rd vdi hl posedge clk rd wdi hz i posedge clk rd wdi h3 j iposedge clk rd wdi h3li posedge clk rd wdi h3 i posedge 1 rd wdi h331i posedge clk ill op iposedge clk nop red XT or indicates that a true or false branch respectively of a conditional statement has not been executed fal fel fel fel fel fel fel fe der fa 2 ral end 100 Fstop ModelSim Designer Tutorial Hover your mouse pointer over a line of code with a green checkmark The icons change to numbers that indicate how many times the statements and branches in that line were executed Figure 86 In this case line 24 was executed 1562 times Select Tools gt Code Coverage gt Show coverage numbers The icons are replaced by execution counts on every line An ellipsis is displayed whenever there are multiple statements on the line Hover the mouse pointer over a statement to see the count for that statement Select Tools gt Code Coverage gt Hide coverage numbers to return
14. a block or embedded block and dragging one of its resize handles If necessary you can drag text elements such as the signal name using the left mouse button b Add a signal from block U 0 to the embedded block eb2 and another signal from a point on sig2 terminating on the embedded block eb2 c Add a signal from the embedded block eb2 terminating in space on the right side of your diagram Notice that an output port is added when you double click at the end of the last signal and its declaration is added to the list of ports on the diagram d Choose Bus with Port and use the button to add a bus from a source on the left side of your diagram with its destination on the upper ModelSim Designer Tutorial Figure 27 Toolbar buttons for adding signals and ports Add a signal Add a signal with a port Add a bus Add a bus with a port Add a bus with a ripper embedded block eb A default input port is automatically created at the beginning of the bus e Add another bus starting from this bus and terminating on instance U Notice how both bus segments have the same default name dbus0 The full declaration showing the default bus type and bounds std_logic_vector 15 DOWNTO 0 is added to the list of ports f Adda bus dbus from 1 to U_I This internal diagram signal is shown with the default bounds 5 0 shown in abbreviated format on the net add two buses dbus2 and dbus3 from U_ termina
15. and signal names T 47 Figure 34 Block diagram with updated names Declarations Package List Parts 06 LIBRARY ieee 7752277 4 std logic vector 3 DOWNTO 0 USE ieee std logic arith all start std logic stop std logic alarm std logic high std logic vector 3 DOWNTO 0 low std logic vector 3 DOWNTO 0 Diagram Signals SIGNAL beep std logic SIGNAL clear std logic SIGNAL dat in std logic vector 3 DOWNTO 0 SIGNAL hold std logic SIGNAL load std logic SIGNAL zero std logic stat MK O i i low stop M O ES GraphTutor GraphTutor reset M Control Counter Uu U 1 high control bundle O Ten n reset start stop alarm ModelSim Designer Tutorial T 48 Lesson 3 Creating block diagrams Add 1 ng anem bedded HH D L text view Figure 35 The Create Embedded View dialog bedded vi E In this section you will enter HDL code to define the functionality of the OR 2 E block on the diagram Create a new view for Embedded Black R1 2 Ma View 1 Open a new view for the OR block Right click the block and select Open gt New View Figure 35 b Leave the type of view set to Text and then click OK Object Properties An embedded HDL text view containing default text is displayed on the block diagram adjacent to the embedded block Blocks Embedded Bl
16. been toggled during execution Design files for this lesson The sample design for this lesson consists of a finite state machine which controls a behavioral memory The testbench test_sm provides stimulus The ModelSim installation comes with Verilog and VHDL versions of this design The files are located in the following directories Verilog lt install_dir gt modeltech examples coverage verilog VHDL lt install_dir gt modeltech examples coverage vhdl This lesson uses the Verilog version in the examples If you have a VHDL license use the VHDL version instead When necessary we distinguish between the Verilog and VHDL versions of the design Related reading ModelSim User s Manual Chapter 12 Measuring code coverage UM 239 ModelSim Designer Tutorial Compiling the design Enabling Code Coverage is a two step process first you compile the files and identify which coverage statistics you want second you load the design and tell ModelSim to produce those statistics 1 Start ModelSim if necessary If the Welcome to ModelSim dialog appears click Close Create a new project Select File gt New gt Project Enter the following in the New Project dialog Type coverage for the Project Name e Enter any suitable path Type coverage for the Default Library Click OK Import files d Select File gt Import gt HDL Browse to one of the directories described under Design files for th
17. bottom of the state diagram editor window The function of these buttons is defined in detail in Chapter 9 Simulator cross probing and state diagram animation in the ModelSim Designer GUI amp Interface Reference Simulate the control block T 69 ModelSim Designer Tutorial T 70 Lesson 4 Creating state diagrams Lesson wrap up This concludes this lesson Before continuing we need to close the simulation we just started 1 From the Main window select Simulate gt End Simulation Click Yes ModelSim Designer Tutorial Lesson 5 Viewing simulations in the Wave window Topics The following topics are covered in this lesson Introduction Related reading Loading a project and design Adding objects to the Wave window Using cursors in the Wave window Working with a single cursor Working with multiple cursors Saving the window format Lesson wrap up T 72 T 72 T 73 T 74 T 76 T 76 T 77 T 79 T 80 T 71 ModelSim Designer Tutorial T 72 Lesson 5 Viewing simulations in the Wave window Introduction The Wave window allows you to view the results of your simulation as HDL waveforms and their values The Wave window is divided into a number of window panes Figure 50 All window panes in the Wave window can be resized by clicking and dragging the bar between any two panes Related reading ModelSim GUI Reference Wave window GR 169 ModelSim User s Manual Chapter 8
18. di di di Ji di di di di di di di HHH didi dl dl di di d di di 4i di di di di di 4i 4i 4i di di HHH di di dl dL di di di di di 4i di di Jb Gl JL dL d di dl dL di di di 4i di 4i di di Tb Gl LL didi dl dL TC GL OL GL di di dl dL di di di di di 4i di di dk di di di di 4i xt di dk 4i di di di Ai Ai di Ai Jk J Ji di dk d JR dk 4i di di di Ai Ai di HHH dk di di di di Ai xn di S mulate the design a Click the run all icon in the Main window b Click the mem tab of the MDI frame to bring the ram_tb spraml mem instance to the foreground Figure 60 VHDL In the Transcript pane you will see NUMERIC STD warnings that can be ignored and an assertion failure that is functioning to stop the simulation The simulation itself has not failed Let s change the address radix and the number of words per line for instance ram tb spraml mem a Right click anywhere in the mem tab and select Properties The Properties dialog box opens Figure 61 b For the Address Radix select Decimal c Select Words per line and type 1 in the field d Click OK You can see the results of the settings in Figure 62 00000000 00000006 0000000 00000012 000000138 0000001 00000024 0000002 0
19. i Filename reloc mem Browse Fill Type Fill Data Value In Increment Decrement skip Random word s Cancel Figure 70 Overwritten values in memory instance es ram_tb sprams mem 246 00000000000000000010010000011110 247 00000000000000000010010000011111 240 00000000000000000010010000100000 249 00000000000000000010010000100001 250 00000000000000000010010000100010 251 00000000000000000000000000000000 252 00000000000000000000000000000001 253 00000000000000000000000000000010 254 00000000000000000000000000000011 255 00000000000000000000000000000100 256 000000000000000000000000000002101 257 00000000000000000000000000000110 220 00000000000000000000000000000111 259 00000000000000000000000000002000 ace LI Interactive debugging commands The memory panes can also be used interactively for a variety of debugging purposes The features described in this section are useful for this purpose 1 Open a memory instance and change its display characteristics a Double click instance ram_tb dpraml mem in the Memories tab b Right click in the mem tab and select Properties c Change the Data Radix to Hexadecimal d Select Words per line and enter 2 e Click OK 2 Initialize a range of memory addresses from a fill pattern a Right click in the data column of the mem tab and select Change to open the Change Memo
20. it 5 appears the same the next time you invoke the tool See Main window GR 20 in the ModelSim GUI amp Editor Reference for more information Brass C MS Desi Library C MS_ Desi 2 0 e Menus are context sensitive The menu items that are available and how certain menu items behave depend on which pane or window is active For example if the Design tab in the Workspace is active and you choose Edit from the menu bar the Clear command is disabled However if you click in the Transcript pane and ibrar esign 44 choose Edit the Clear command is enabled The active is denoted by a blue title bar Transcript Note Loading HDS Project file from user preferences CMS_DesignerModeltech6 0_de_betaspT esamples shdl uart hdp gt Let us try a few things ModelSir 1 Zoom and undock panes a Click the zoom icon on the Workspace Figure 5 Figure 6 Zoomed Workspace pane The pane fills the entirety of the Main window Figure 6 Unzoom A MlModelSim Designer PLUS 6 0 Beta 2 b Click the unzoom icon the Workspace File Edit View Format Compile Simulate Add Tools Window Help c Click the undock icon on the Transcript z si 51 X Ba A x ME Corn Z 8 amp Q t fes The Transcript becomes a stand alone window PDT Path Filename Na uart Project C MS Designer Mode d Click the dock icon on the Transcript UART Library C MS_Designer Mode e Click the close button on the Works
21. multiple times The best plan is to play around a bit watch the gray outlines and see what happens when you drop panes in various places ModelSim Design Loaded ko oo TTS 2 You won t have to do this very often Once you have a layout you like it will be saved when you exit ModelSim Selecting Window gt Initial Layout is the easiest way to rectify an undesired layout d Hover your mouse pointer on the border between two panes so it becomes a double headed arrow 1 e Click and drag left and right or up and down to resize the pane f Select Window Initial Layout ModelSim Designer Tutorial T 26 Lesson 2 Working with ModelSim Designer 3 View stand alone windows a C Select View Debug Windows List The List window displays results from a simulation run in tabular format See List window GR 113 in the ModelSim GUI amp Editor Reference for more information Select View Debug Windows Dataflow The Dataflow window allows you to explore the physical connectivity of your design See Dataflow window GR 98 in the ModelSim GUI amp Editor Reference for more information D Note Many of the options listed under Debug Windows display only when a simulation is loaded Close the List and Dataflow windows 4 Observe context sensitivity of menu commands Click anywhere in the Design tab of the Workspace Select the Edit menu and notice that the Clear command is disable
22. seqv w flle 22 21 35 455 PB ara u file 30 27 90 000 EEE View Source re 10 3 90 000 mmm Save List fila na 7 30 361 DRE Coverage Reports Ezclude Selected File Coverage Copy Clear Coverage Data Properties ModelSim Designer Tutorial T 106 Lesson 7 Simulating with Code Coverage Creating Code Coverage reports You can create reports on the coverage statistics using either the menus or by entering commands in the Transcript pane The reports are output to a text file regardless of which method you use To create coverage reports via the menus do one of the following select Tools gt Code Coverage gt Reports from the Main window menu right click any object in the sim or Files tab of the Workspace and select Code Coverage gt Coverage Reports right click any object in the Instance Coverage pane and select Code coverage reports from the context menu 1 Create a report on all instances a Select Tools Coverage Reports from the Main window toolbar This opens the Coverage Report dialog Figure 89 b Make sure Report on all instances and No Filtering are selected and then click OK ModelSim creates a file report txt in the current directory and displays the report in Notepad c Close Notepad when you are done looking at the report 2 Create a summary report on all design files from the Transcript pane a Type coverage report file cover txt at the VSIM gt prompt b Type notepad
23. sm pe Timer Component 4 E ModelSim Designer Tutorial T 58 Lesson 4 Creating state diagrams Ed iti ng the states and transitions Figure 44 The Object Properties dialog for states 1 Edit the state names and actions l Bez T a Switch back to the State Diagram b Select the start state s0 in Figure 42 on page page T 56 and click the 2260 zi button to display the States tab of the State Machine Object Properties dialog box Figure 44 Outgoing transitions for this state The States tab allows you to enter aname and actions text for one or more Sue CASE selected states on a state diagram You can also change the visibility of IV Implicit loopback r Actions state actions and change the state to a start state or a hierarchical state F Visbie when a single state is selected um s ModelSim Designer Tutorial Editing the states and transitions T 59 Edit the remaining state names and actions State names and actions for VHDL Use the dialog and the table of state names and actions at the right to edit the states on the diagram Old Name Actions The Expression Builder dialog box is automatically displayed when you start s0 hold lt 1 to enter the actions The expression builder can be used to choose from lists clear lt 1 of the available port or local signal names operators and example values beep lt 0 Th
24. the cursor is over a transition the source state and the destination state are named even if the states are outside the current window ModelSim Designer Tutorial Figure 41 The blank child state diagram Untitled csm State Diagram D E pul o x Die 50 View Haram Add Come Aule A A ORES Widow Hep 0015 0 P cm amp x Es co dalmriz l5 8 z uj BA RR A E am 6 a orten d z n sir Feen mu zr vvl duru R summer nop sor S ywar mw un Pre Actions Figure 42 New states and transitions condition condition condition Click the button to save the state diagram Switch to the Design tab in the Workspace The Design tab was updated to display the Control design unit The Control design unit is shown as a block in the Design tab because its interface is defined by the connections on its parent block diagram The Timer design unit is shown as a component because it has no parent block diagram and its interface is defined by a symbol If you expand the Control design unit you will see that it contains a State Diagram view Figure 43 Creating a state machine T 57 Figure 43 The Design tab showing the Control block and state machine view Z Workspace PE Iaraph Tutor Project 5 Designer Mi GraphTutor Library CMS Designer tdi CN New FE Lety sm StateD laqram teicantral Tsm
25. versions of the example design The files are located in the following directories Verilog install dir modeltech examples memory verilog VHDL install dirs modeltech examples memory vhdl This lesson uses the Verilog version for the exercises If you have a VHDL license use the VHDL version instead Related reading ModelSim GUI amp Editor Reference Memory windows GR 131 ModelSim Command Reference mem display CR 140 mem load CR 143 mem save CR 146 radix CR 175 commands ModelSim Designer Tutorial Compiling and loading the design 1 Start ModelSim if necessary If the Welcome to ModelSim dialog appears click Close Create a new project Select File gt New gt Project Enter the following in the New Project dialog Type memory for the Project Name e Enter any suitable path Type memory for the Default Library Click OK Import files Select File gt Import gt HDL b Browse to one of the directories described under Design files for this lesson T 82 on the previous page c Click Remove All if necessary to remove any files listed from a previous import d Import all of the HDL files Load the design a the Design tab click the icon next to the memory library b Right click zam fb and select Flow gt Simulate c Click OK Compiling and loading the design T 83 ModelSim Designer Tutorial T 84 Lesson 6 Viewing and initializing memories
26. 00000 30 00000036 000000362 00000042 00000048 nnd xj Hexadecimal Decimal Line Wrap A a M_ E P Ta mi meri 00101000 00101110 00110100 00111010 01000000 01000110 01001100 01010010 01011000 01011110 01100100 01101010 01110000 710707777111 l l l l llll ll l l lll ll 01000001 01000111 01001101 l l ll l ll l 01011111 01100101 01101011 01110001 7177131 E E NE NE C Fit in window words per Line i Data Radis Symbolic Hexadecimal l l l 00110000 ll ll 00111100 O1000010 01001000 01001110 01010100 l ll l 01100000 lln ll ll ll lll l a 1 1 1 1 r 7 Figure 61 Changing the address radix Properties Address Radix Binary Octal Decimal Unsigned Lancel xi l l ll ll l 00110111 00111101 01000011 01001001 01001111 01010101 01011011 01100001 01100111 01101101 01110011 Ya 1 1 1 Fr 1 Viewing a memory Figure 60 Memory display updates with simulation l ll 00110010 00111000 00111110 01000100 01001010 01010000 l l ll 01011100 01100010 01101000 01101110 01110100 7107771770077 nm l ll l ll ll lll l 00111111 01000101 l l ll l l l 01010111 01011101 01100011 01101001 01101111 01110101 1077773505711 T 85 ModelSim Design
27. 15 Synthesize the design ModelSim Designer interfaces smoothly with a variety of downstream synthesis tools ModelSim compiled the necessary vendor libraries when you first invoked the tool so in many cases you can just select the top level of the design click the synthesis button configure the synthesis tool Precision Synthesis Settings 5 mi x General Setup User Script Setup Technology Device zarz 0004575 Speed Grade 4 T Design Frequency MHz H Add l Pads Use safe FSM Retiming Output Formats v EDIF VHDL Verilog Fun Options M Compile Produce Script File For Batch Run M Sunthesize M Lauch Synthesis Run Integrated Place and Route Netlist Format f vHDL Verilog Overarite implementation folder Defaults and then click OK to invoke the synthesis tool in batch mode ModelSim Designer Tutorial T 16 Lesson 1 ModelSim Designer overview Place and route the design Place and route works similarly to synthesis in ModelSim Designer Select the top level of the design click the Place and Route Icon Xilinx Place and Route Settings Select Syries Reat C Apps Modekechb D diiringi han a IC Apps H odakechi 0 de exsmples vhdusit ls ual tap utir Samaulsson Model User Conshanis Fie Modele VHDL Browse P ogsammrg Fis Formats Ellon Level Creste Binary Configuestion File s Standard C Medium Create ASLI
28. 2 55 test sm Line 74 Ell ist sy pragma Er Lines 25 29 Statement Line 25 Line 25 Line 27 Line 29 Instance Coverage E F x w nsance Desimuunit Desig unit ype Stmtcount Stmthits Stmtmisses Stmt Stmt graph dj test sm sram beh sram Module 10 J 1 30 gi test sm sm seq sm D sm Module 30 2 3 30 EEE d test sm sm 5600 sm 560 Module 22 21 355 Hest sm Module test sm Loading and running the design T 99 click the Dock Undock Pane button in the header bar top right To redock the pane click the Dock Undock Pane button again We will look at these panes more closely in the next exercise For complete details on each pane see Code coverage panes GR 86 ModelSim Designer Tutorial T 100 Lesson 7 Simulating with Code Coverage Viewing statistics in the Main window Let s take a look at the data in these various panes 1 View statistics in the Workspace pane a Select the sim tab in the Workspace and scroll to the right Coverage statistics are shown for each object in the design b Select the Files tab in the Workspace and scroll to the right Each file in the design shows summary statistics for statements branches conditions and expressions c Click the right mouse button on a
29. Configuration Fite C High Place amp Route Fun Mode M Lauch PER Fiom ModelSim Degra F Produce Seni File For Balch hun k 4 then click to run place and route The post place and route netlist and the SDF file are both linked into the project automatically ModelSim Designer Tutorial Run post place and route simulation T 17 Run post place and route simulation With the place and route finished you can run a gate level simulation with timing All of the required files are in place in the project so just click the simulate icon to load the design Again you can use ModelSim s debugging tools to investigate any problems ModelSim Designer Tutorial T 18 Lesson 1 ModelSim Designer overview ModelSim Designer Tutorial Lesson 2 Working with ModelSim Designer Topics The following topics are covered in this lesson Introduction Related reading Starting up Designer Navigating the ModelSim interface Managing designs with the Design tab Simulating the design Creating projects and importing files Lesson wrap up T 20 T 20 T 21 T 23 T 27 T 30 T 33 T 35 T 19 ModelSim Designer Tutorial T 20 Lesson 2 Working with ModelSim Designer Introduction In this lesson we will introduce you to the primary components of the ModelSim Designer interface You will do the following e Open an existing project and browse the design in the Workspace Design tab e Open exist
30. E Le Now 1 ms Delta 2 sim test sm Figure 81 Statement statistics in the Missed Coverage pane e vernlag test sm v ES madeltech examples coverag 5515000 z reg rst clE 13 wire 31 0 out wire dat 20 wire 3 0 addr el reql3l loop 22 y m m 77 23 task nop v 24 8 5 into 14 50000 28 0 op wor T i 25 endtasE 26 27 the ctrl op 7 25 task ctrl z9 input 7 0 data 30 begin X 51 5 into 4 b l 28 b ctrl X 3z B posedge clk 33 5 into data 34 end x 38 endtask 36 7 k n EE ip nurum Dr SLM es a EEE EN N N TEE IS El EZ View statistics in the Details pane a Select the Toggle tab in the Missed Coverage pane If the Toggle tab isn t visible you can do one of two things 1 widen the pane by clicking and dragging on the pane border 2 if your mouse has a middle button click and drag the tabs with the middle mouse button Select any object in the Toggle tab to see details in the Details pane Figure 82 View instance coverage statistics The Instance Coverage pane displays coverage statistics for each instance in a flat non hierarchical view Figure 83 Select any instance in the Instance Coverage pane to see its source code displayed in the Source window Viewing statistics in the Main window T 101 Figure 82 Details pane showing toggle coverage statistics Details k xl
31. Instance tezt zm Signal into Node count 32 0 76 1 46 Toggle Coverage 34 55 0 1 Coverage 67 19 Full Coverage 67 15 2 Coverage 67 19 Figure 83 The Instance Coverage pane Ins Coverage BBE Simt X _ Stmt graph Branch graph 1 Tj 3 gn 1 13 843 m ModelSim Designer Tutorial T 102 Lesson 7 Simulating with Code Coverage Viewing statistics in the Source window Figure 84 Selecting a line in the Missed Coverage pane Missed Coverage EMKE In the previous section you saw that the Source window and the Main window Missed Statements coverage panes are linked You can select objects in the Main window panes to Hw test_sm v view the underlying source code in the Source window Furthermore the Source 18 5 window contains statistics of its own 13 into 407 endt ask dc into 4 bOOO1 28 bO 1 View coverage statistics for test sm in the Source window Make sure test sm is selected in the sim tab of the Workspace tposedge clk dc into data b Inthe Statement tab of the Missed Coverage pane expand test sm v if necessary and select any line Figure 84 endt as The Source window opens in the MDI frame with the line you selected highlighted Figure 85 repeat 1b 126 nop 125 100 128 Fstop The table below describes the various icons al Icon Description Seren green checkmark indicates a statement that has been executed
32. O MENTOR GRAPHICS OR B MODIFICATION OR REPLACEMENT OF SOFTWARE THAT DOES NOT MEET THIS LIMITED WARRANTY PROVIDED YOU HAVE OTHERWISE COMPLIED WITH THIS AGREEMENT MENTOR GRAPHICS MAKES NO WARRANTIES WITH RESPECT TO A SERVICES B SOFTWARE WHICH IS LICENSED TO YOU FOR A LIMITED TERM OR LICENSED AT NO COST OR C EXPERIMENTAL BETA CODE ALL OF WHICH ARE PROVIDED AS IS ModelSim Designer Tutorial 5 2 THE WARRANTIES SET FORTH IN THIS SECTION 5 ARE EXCLUSIVE NEITHER MENTOR GRAPHICS NOR ITS LICENSORS MAKE ANY OTHER WARRANTIES EXPRESS IMPLIED OR STATUTORY WITH RESPECT TO SOFTWARE OR OTHER MATERIAL PROVIDED UNDER THIS AGREEMENT MENTOR GRAPHICS AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND NON INFRINGEMENT OF INTELLECTUAL PROPERTY LIMITATION OF LIABILITY EXCEPT WHERE THIS EXCLUSION OR RESTRICTION OF LIABILITY WOULD BE VOID OR INEFFECTIVE UNDER APPLICABLE LAW IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS BE LIABLE FOR INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES INCLUDING LOST PROFITS OR SAVINGS WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY EVEN IF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS LIABILITY UNDER THIS AGREEMENT EXCEED THE AMOUNT PAID BY YOU FOR THE SOFTWARE OR SERVICE GIVING RISE TO THE CLAIM IN THE CASE WHERE NO AMOUNT WAS PAID
33. VHDL package list and labels for global actions concurrent statements architecture declarations signals status process declarations and state register statements If you are working with Verilog the diagram includes text objects for the default compiler directives list and labels for global actions concurrent statements module declarations signals status and state register statements Adding states and transitions 1 Click the button and add five states on your state diagram The states are added with default names 50 s1 52 53 and 54 Notice that the first state you add is assumed to be the start state and is drawn in green with a double outline The other states are drawn in cyan with a single outline 2 Click the button to add transitions between the states as shown in Figure 42 The transitions are added with default conditions which will be edited later in this tutorial Notice that when you add more than one transition leaving a state the transition priority is indicated by a priority number associated with the transition arc The priorities are initially assigned in the order that you add the transitions but can be re assigned later if necessary If you add a transition in the wrong direction you can easily change its direction by selecting Diagram gt Reverse Direction Note that a popup description known as an object tip is displayed when the arrow or hand cursor is stationary over an object In particular when
34. chine editor e Text editor Waveform editor for stimulus creation Creating a design includes three main steps Create a project 2 Create design units 3 Create a testbench Create a project Projects serve as containers for all the design files and information associated with your design Projects may include design data user data such as project documentation downstream data for external tools and compiler and simulation configuration information Create design units You can use any of the editors to begin building your design or you can import design elements from external libraries Create a testbench You ll often want to create a testbench to exercise your design You can write a testbench from scratch using the Source window or you can create a graphical testbench by using the waveform editor Create the design T 13 ModelSim Designer Tutorial T 14 Lesson 1 ModelSim Designer overview Simulate the design When you have created all the design units and a testbench you compile the design and then load the top level into the simulator You can drive the simulation from the Main window or directly from the block diagram or state machine editors If you get the results you expect your next step is typically to synthesize the design If you don t get the results you expect you can use ModelSim s suite of debugging tools to troubleshoot and correct the design ModelSim Designer Tutorial Synthesize the design T
35. ck diagram editor window Figure 24 d Click the View All button to view the entire diagram The block diagram is a blank sheet except for a background grid a package list with the standard IEEE libraries std logic 1164 and std logic arith and empty text fields with labels for Declarations Ports and Diagram Signals The diagram also shows page boundaries for the default printer and a copy of the default title block Edit the title block A title block is automatically added to all new diagrams if the Add Title Blocks in new diagrams option is set in your diagram preferences The title block incorporates internal variables which automatically enter the current project name your login name and the current date Internal variables are also used to enter the logical pathname for the design This path is initially shown as lt TBD gt lt TBD gt lt TBD gt but the internal variables are converted to show the library design unit and view name when you save the diagram a Click twice on company name in the title block to display a popup edit box and replace the default text by the name of your company b Click twice on enter diagram title here and enter a title such as Top Level Timer Block Diagram c Click twice on enter comments here and enter Created by your name on lt date gt d With the title block selected select File gt Save Title Block and click Yes to confirm ModelSim Designer Tutorial Figur
36. command line interface and serves as an activity log including status and error messages See Transcript GR 22 in the ModelSim GUI amp Editor Reference for more information Transcript The Multiple Document Interface MDI frame holds windows for which there can be multiple instances These include Source editor windows Wave windows and Memory content windows See Multiple document interface MDI frame GR 23 in the ModelSim GUI amp Editor Reference for more information MDI frame Navigating the ModelSim interface T 23 Figure 4 The ModelSim Designer Main window el Modelsim Designer PLUS 6 0a File Edit View Format Compile Simulate Add Tools Window Help 4099 Project Library H7 Note Loading HDS Project file from user preferences CMS DesignersMadeltechb l de betgzpl esamplessvhaluart hdp Hu 50 VVorkspace Transcript MDI frame ModelSim Designer Tutorial T 24 Lesson 2 Working with ModelSim Designer Here are a few important points to keep in mind about the ModelSim interface Figure 5 Pane control icons Windows panes can be resized moved zoomed undocked etc and the changes Zoom Undock Close are persistent You have a number of options for re sizing re positioning undocking xj Modelsim Designer PLUS 6 03 redocking and generally modifying the physical characteristics of windows ces Ss ae and panes When you exit ModelSim the current layout is saved so that
37. cover txt at the VSIM prompt to view the report c Close Notepad when you are done reviewing the report ModelSim Designer Tutorial Figure 89 The Coverage Report dialog E l xi E Coverage Report Report on all files Report on all instances Report on a specific instance Instance Name Browse Report on a source file File Mame Browse Coverage Type v Statement Coverage Expression Coverage Branch Coverage Toggle Coverage Condition Coverage Extended Toggle Coverage Other Options Filter Zero Coverage Only Ma Filtering Include Line Details Filter Above Percent Coverage Totals Only Filter Below Percent Disable Source Annotation Percent 75 Recursive write XML Format Report Pathname Irepatt tat Browse Append to file Lesson wrap up T 107 Lesson wrap up This concludes this lesson Before continuing we need to end the current simulation Type quit sim at the VSIM gt prompt ModelSim Designer Tutorial T 108 Lesson 7 Simulating with Code Coverage ModelSim Designer Tutorial End User License Agreement IMPORTANT USE OF THIS SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS CAREFULLY READ THIS LICENSE AGREEMENT BEFORE USING THE SOFTWARE This license is a legal Agreement concerning the use of Software between you the end user either individually or as an authorized representative of the company acquiri
38. created in Lesson 2 Working with ModelSim Designer 1 If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close 2 Load the project Click somewhere in the Design tab of the Workspace b Select File gt Open and open example hdp This project file is located in the directory you specified in Creating projects and importing files T 33 in Lesson 2 Working with ModelSim Designer 3 Load the design Click the icon next to the work library b Right click fest counter and select Flow gt Simulate c Click OK to load the testbench ModelSim loads the design and adds sim and Files tabs to the Workspace Loading a project and design T 73 ModelSim Designer Tutorial T 74 Lesson 5 Viewing simulations in the Wave window Adding objects to the Wave window ModelSim offers several methods for adding objects to the Wave window In this exercise you will try different methods 1 Add objects from the Objects a Select an item in the Objects pane of the Main window right click and then select Add to Wave Signals in Region ModelSim adds several signals to the Wave window Undock the Wave window By default ModelSim opens Wave windows as a tab in the MDI frame of the Main window You can change the default via the Preferences d
39. ction ModelSim Designer is a design creation simulation and debugging tool for VHDL Verilog and mixed language designs ES Modelsim Designer PLUS 6 0 Beta 2 File Edit View Format Compile Simulate Add Tools Window Help B 100 ns E El EW ER as Contains 5 al Eo Gane e Na wave default 3 uart data out uart tb clk 0 testerjrtl int el b i Sout ea U YE i i uari top 2 uart tb data in 11011010 01011010 M tertio temtio duart tb data nut MN std logic arith logi E Auart tb int W std logic 1184 M I 2 at bine B standard data_in uart_thyrst hth rst uart EST sin tester top current st int clk al read data glow 55 55 Transcript WSIM T3 run 1 ms Failure Uart Testing Complete Time 20700 ns Iteration Process dart tb il tester File 5 Desianer Maodeltechb U de betazpl examples vhdl LIA amp RT hdl tester rtl v hd Break at CMS DesignerModeltech6 0_de_betazp examples hd UT hdltester rth hd line 257 hu 1 xn um Now 20 700 ns Delta simuat thi Limited Visibility Region This lesson provides a brief overview of the ModelSim Designer environment and the basic Designer flow Related reading ModelSim User s Manual Chapter 2 Getting started with ModelSim Designer UM 1 ModelSim Designer Tutorial Basic ModelSim Designer flow T 11 Basic ModelSim Designer flow The following diagram
40. d Click in the Transcript and select Edit gt Clear This command applies to the Transcript pane but not the Workspace pane Click back in the Design tab of the Workspace and select File Open Notice that the Open dialog filters to show project files Now click in the MDI frame and select File Open Notice that the Open dialog filters to show HDL file types instead ModelSim Designer Tutorial Managing designs with the Design tab The Design tab serves as the central access point for all objects in your design This includes design units and their different views graphical textual supporting design data SDF files etc and other related files e g documentation scripts etc The Design tab is organized hierarchically When you expand items you see different views of the design unit The icons in the Design tab communicate a variety of information For more details see Design tab icon descriptions UM 33 in the ModelSim User s Manual Open different views a Expand the uart_top component so you can see all of the views Figure 8 b Double click uart_top struct bd to open a block diagram view Figure 9 c From the block diagram editor select File gt Close Window Managing designs with the Design tab T 27 Figure 8 Different views of uart top Z Workspace 5 n 1 Work space 2 F3 Fi Alan lie NN clock divider Component control ope Component Component Component Com
41. d OR beep 57 MEE HERE GNIS D Created on 01 June 2004 itle Top Level Block Diagram GraphTutor Timer struct by Noah on 01 Jun 2004 ModelSim Designer Tutorial Creating a new project For this lesson you will create a new project 1 Start ModelSim if necessary a Use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close 2 Create a new project Select File New Project b m New Project dialog type GraphTutor for the Project Name and Default Library Figure 21 c Click OK The Design tab in the Workspace pane show the new project and library Figure 22 Figure 21 Creating the GraphTutor project Fal Project E xl Mew Project Project M ame Graph utor Project Path EAM 5 Dezgner Modeltechb de Browse Default Library Graph utod Creating a new project T 39 Figure 22 The new project and library in the Workspace pane Z Workspace 5 GraphTutor Project GraphTutor Library Las Hew 25 ModelSim Designer Tutorial T 40 Lesson 3 Creating block diagrams Creating a new block diagram Use the File Creation wizard to create a new block diagram a Inthe Workspace under the GraphTutor library double click the New icon This opens the File Creation Wizard Figure 23 b Select the appropriate language if necessary c Double click Block Diagram under Graphical Views This opens a new blo
42. decimal Start JU End 4035 File Format Verilog Hex Verilog Binary MTI Address Had z No addresses Compress Data Radix Hexadecimal Symbolic Decimal Binary ctal Decimal Unsigned Hexadecimal Browse Filename data mem mem Lancel Initializing a memory In ModelSim it is possible to initialize a memory using one of three methods from a saved memory file from a fill pattern or from both First let s initialize a memory from a file only You will use one you saved previously data_mem mem View instance ram_tb spram3 mem a Double click the ram_tb spram3 mem instance in the Memories tab This will open a new tab mem 2 in the MDI frame to display the contents of ram tb spram3 mem Scan these contents so you can identify changes once the initialization is complete Right click and select Properties to bring up the Properties dialog Change the Address Radix to Decimal and click OK 2 Initialize spram3 from a file a b C Right click anywhere in the data column and select Load to bring up the Load Memory dialog box Figure 67 The default Load Type is File Only Type data mem mem in the Filename field Click OK The addresses in instance ram_tb spram3 mem are updated with the data from data mem mem Figure 68 nk Figure 68 Initialized memory from file and fill pattern Initializing a memory Figure 67 Load Memo
43. dit the signal and bus names Alternatively you can use a dialog box that allows you to edit the properties for a selected object By default edits to signal and bus nets are applied only to the connected nets but you can choose to apply the changes to the entire diagram or to propagate changes to all occurrences of the net in the hierarchy of the design a Select Diagram gt Signals gt Scope for Changes gt Entire Net in Diagram b Select Edit gt Object Properties Notice that the port declarations are listed at the top of the dialog box and the other internal diagram signals at the bottom Figure 33 Input ports are listed before the output ports otherwise the declarations are listed in alphanumeric order You can choose one or more existing declarations in the dialog box and enter new values for any of the declaration fields For example click dbus1 dbus2 and dbus3 while holding the Ctrl key then enter a new index constraint with bounds 3 DOWNTO 0 3 0 for Vector Bounds in Verilog to update all three buses while all other fields remain AS_JS Editing block and signal names T 45 Figure 32 Editing block and symbol names directly on the diagram 9 37 c ov msl 3 3 3 sm sm osmos s sm s s GraphTuter thlock wi PERSE oo Tigb siy sige Figure 33 The Object Properties dialog 4 Object Properties x Blacks Embedded Blacks Components Generics Declaration
44. duction Related 05 Creating a new project Creating a new block diagram Adding blocks Adding ports and N Adding a bundle and a global connector Saving the block diagram Editing block and signal names Adding an embedded HDL text view Adding a panel Lesson wrap up T 38 T 38 T 39 T 40 T 41 T 42 T 43 T 44 T 45 T 48 T 50 T 51 T 37 ModelSim Designer Tutorial T 38 Lesson 3 Creating block diagrams Int rod u ct j on Figure 20 A completed block diagram a ss is oo si 77 TPP In this lesson you will create part of a simple timer using block diagrams Oe haw RE em embedded text views and state machines ar sub say dl ie A 700222 stars std Logs 000000 Co igb 1 8td logic vector 3 DOWNTO 0 eg 599 5d pose SOS 0B OR ee oe means X std logic vector 3 DOWNTO 0 Related reading 2 esistono minar o beep std_logic USEieee std logic 1164 al 000 SIGNAL clear std logic 000 USieee std_logicarthal l l SIGNAL dat in std_togic_vector 3 DOUNTO 0 ModelSim Graphical Interface and Editor Reference Chapter 2 Introduction Re ee ee ee ee ci SIGNAL zero std lodic 22222020000 to graphical editors and Chapter 4 Block diagram editor R 7 ro 0 77 stat MO stop BO reset control_bundie reset start stop alarm Fort Jalarm lt hol
45. e Use your mouse and the Ctrl Language VHDL a 2c or lt Shift gt keys to select from the listed libraries vw xilins T 21 At this point ModelSim Designer compiles the selected vendor libraries This may take some time L silinzcorelib ModelSim Designer Tutorial T 22 Lesson 2 Working with ModelSim Designer By default ModelSim displays a Welcome dialog upon invocation that is similar to the one shown in Figure 2 3 Click Close ModelSim Designer requires that you have a project open Consequently it will always open a project upon start up The first time you invoke the tool it will open the example uart project that ships with the product In subsequent invocations it will re open whichever project was open when you last exited the tool Assuming that you are invoking the tool for the first time or that you have never opened another project you should see the uart project in the Design tab Figure 3 If you don t see this project open it by clicking in the Design tab and selecting File gt Open The project is located at install dir examples language uart hdp where language is VHDL or Verilog the examples in this section use the VHDL version ModelSim Designer Tutorial Figure 2 The Welcome dialog v IMPORTANT Information B x Model m 50 designe Welcome to ModelSim Designer 6 0a Qa up Introducting ModelSim Designer m Ga iz conj q DE
46. e 23 The File Creation Wizard File Creation Wizard Specify File Type NM x Specify what kind of file you wish to create using which template File Types Template Files Cy Graphical Views lt No Template gt Interface f Symbol 15 Block Diagram State Diagram Cy VHDL Views m Entity 1c EE Architecture 12 Combined E Package Header 15 Package Body 12 Configuration Cy Verilog Views iz Module Z Include Greate a template Properties VHDL C Verilog 1b Finish Cancel Figure 24 A new block diagram Untitled Elnzle Diagram xj Fin Edi ew HDL Disgem Compie Simulate Add Options Windom Help a e mi d c eec we SP Ar Ax 1d IR A v en SauaiN L u 9 o nDimdz Package List Deck aine Porte LEE inne siri ingie 1154 ni Diagram Signals LISE mes tio kegi arih al ale zz 1129 HEHE 2194 m Le Adding blocks button or select Add gt Block to add two blocks on the diagram Figure 25 Notice that the blocks are added with the default library lt library gt the default name block and unique instance names U and U 7 gt Note The Add Block command normally auto repeats until you select another command or terminate the repeating command by using the right mouse button or Esc key However you can change the behavior of the toolbar buttons by setting the Activate once only preference in th
47. e Expression Builder dialog box can be explicitly displayed at any time by selecting Edit gt Expression Builder no actions The syntax for state actions is automatically checked and any errors reported hold lt 1 on entry VHDL and Verilog statements must be terminated by a semicolon hold lt 1 character Line breaks and spaces can be used for clarity and will be preserved on the diagram hold lt 1 load lt You can also edit the state name or actions by direct text editing on the diagram or copy a state and paste its state actions into another state by choosing Paste Special gt Paste State Actions from the popup menu State names and actions for Verilog Old Name New Name Actions sO flush hold 1 clear 1 load 0 no actions hold 1 clear 0 load 0 hold 1 clear 0 load 0 hold 1 clear 0 load 1 ModelSim Designer Tutorial T 60 Lesson 4 Creating state diagrams Editing the transitions 1 Edit the flush state transitions a Select the two transitions entering the state flush by dragging the cursor across them b Click the button to display the Transitions tab of the State Machine Object Properties dialog box c Replace the default condition by the new condition stop 1 stop in Verilog and click Apply to add this condition to both of the selected transitions 2 Editthe rest of the transitions Use the
48. e General tab of the Main Settings dialog box You can also use the Ctrl key with any toolbar button to toggle the repeat mode For example when Remain active is set lt Ctrl gt the Add Block button adds a single block Use the El button to add two embedded blocks on your block diagram Figure 26 Notice that the embedded blocks are added with unique default names eb and eb2 and numbers and 2 The view describing a block must be saved as a uniquely named design unit in a library directory However the view describing an embedded block is saved as part of the parent block diagram and does not impose hierarchy when HDL is generated for your design The name of an embedded block must be unique on the diagram and is used as a label in the generated HDL The blocks U 0 and U 7 will be used to define a child state machine and block diagram views The embedded blocks eb and eb2 will be defined by concurrent assignment statements on the top level block diagram Creating a new block diagram T 41 Figure 25 Two blocks added to the diagram 5 V T n n mnn nem LIBRARY bee Ports USE Bee sti ge Tisiali 7 Diagram signal 0 USE kee st kg arial 0000000000 x Ibrary library lt bloch bloch uo u 1 Figure 26 Two embedded blocks added to the diagram 5 nnm LIBRARY bee USE kee st kgb liGbal 00000 USE bee st bgi anah 00000 library my m QU XX d
49. e extended toggle coverage enabled ModelSim Designer Tutorial Excluding lines and files from coverage statistics ModelSim allows you to exclude lines and files from code coverage statistics You can set exclusions with the GUI with a text file called an exclusion filter file or with pragmas in your source code Pragmas are statements that instruct ModelSim to not collect statistics for the bracketed code See Excluding objects from coverage UM 253 for more details on exclusion filter files and pragmas Exclude a line via the Missed Coverage pane a Right click a line in the Missed Coverage pane and select Exclude Selection You can also exclude the selection for the current instance only by selecting Exclude Selection For Instance lt inst_name gt 2 Exclude an entire file a In the Files tab of the Workspace locate sm v or sm vhd if you are using the VHDL example b Right click the file name and select Coverage gt Exclude Selected File Figure 88 The file is added to the Current Exclusions pane 3 Cancel the exclusion of sm v a Right click sm v in the Current Exclusions pane and select Cancel Selected Exclusions Excluding lines and files from coverage statistics T 105 Figure 88 Excluding an entire file via the GUI Workspace sm seqv em beh sram v test sm v l T Filerame Fullpath Twpe Stmt Count Hits Stmt Graph sm
50. en you save a block diagram ModelSim Designer Tutorial Figure 30 Saving the block diagram Save As Design Unit View B 17 xi Library Design Unit Yen GraphT utor Timer struct ola Graph utor lt default hds package library reno package library Figure 31 The Timer component and views in the Design tab S Workspace Nm Type Path Filename ard GraphT utor Project 5 Designer Mad GraphT utar Library 5 Designer Mad PM Meu Component BlackDiagram L n symbol Symbol timer struct bd timer symbol sb Editing block and signal names You now have a completed top level block diagram for the Timer design However the blocks and signals have default names 1 Edit block names directly on the diagram a Click on the text block in the lower block on the left instance U_O in the picture and notice the small handles which indicate that the text object is selected Click again and notice that the text is now highlighted and can be directly overwritten If you click again the cursor changes to an I beam which allows you to move the cursor in the text and edit individual characters Enter the new name Control and click outside the text to complete the edit b Repeat this procedure to change the name of block instance U_ to Counter embedded block eb to DtoB and embedded block eb2 to ORI Figure 32 2 Edit signal names via a dialog Direct text editing can also be used to e
51. er Tutorial T 86 Lesson 6 Viewing and initializing memories Navigating within the memory Figure 62 Memory window new address radix and line length You can navigate to specific memory address locations or to locations containing ER ram_tb spraml mem particular data patterns First you will go to a specific address 00101001 00101010 00101011 00101100 00101101 00101110 00101111 00110000 00110001 ll l 00110011 00110100 7351317 17731 61131 1 Use Goto to find a specific address a Right click anywhere in address column and select Goto Figure 63 The Goto dialog box opens in the data pane l 2 3 d 5 amp Y a b Type 30 in the dialog box c Click OK bb e O to The requested address appears in the top line of the window ra J El en E mem mem T ram t amp v Figure 63 The Goto dialog box na 2 Par 1 mer 00101000 00101001 00101010 00101011 00101100 4 Goto Memory l ll l Goto Address 00101110 00101111 30 00110000 00110001 00110010 Cancel ll ll 00110100 cou gc m nk oh Oo R RE EN 7351317 17731 1 m mem 1a ModelSim Designer Tutorial Edit the address location directly To quickly move to a particular address do the following a Double click any address in the address column b Enter any desired address Figure 64 c Press Enter on
52. er of this Agreement shall be entitled to recover in addition to other relief reasonable attorneys fees and expenses Rev 040401 Part Number 221417 T 113 ModelSim Designer Tutorial T 114 License Agreement ModelSim Designer Tutorial Index A add wave command T 74 B block diagrams creating T 37 T 53 C Code Coverage excluding lines and files T 105 reports T 106 Source window T 102 coverage report command T 106 cursors Wave window T 76 D documentation T 7 F format saving for Wave window T 79 M manuals T 7 memories changing values T 91 initializing T 89 viewing T 81 memory contents saving to a file T 88 Memory window T 81 P projects opening T 21 R rad x command T 84 S simulation basic flow overview T 11 T time measuring in Wave window T 76 toggle statistics Signals window T 104 W Wave window T 71 adding items to T 74 cursors T 76 measuring time with cursors T 76 saving format T 79 zooming T 75 T 115 ModelSim Designer Tutorial T 116 Index Z zooming Wave window T 75 ModelSim Designer Tutorial
53. fill pattern a Right click in the data column of the mem 2 tab and select Load to bring up the Load Memory dialog box Figure 69 b For Load Type select Both File and Data c For Address Range select Addresses and enter 0 as the Start address and 300 as the End address This means that you will be loading the file from 0 to 300 However the reloc mem file contains only 251 addresses of data Addresses 251 to 300 will be loaded with the fill data you specify next d For File Load enter reloc mem in the Filename field e For Data Load select a Fill Type of Increment f In the Fill Data field set the seed value of 0 for the incrementing data g Click OK h View the data near address 250 by double clicking on any address in the Address column and entering 250 You can see the specified range of addresses overwritten with the new data Also you can see the incrementing data beginning at address 251 Figure 70 Now before you leave this section go ahead and clear the instances already being viewed 4 Right click somewhere in the mem 2 pane and select Close All ModelSim Designer Tutorial Figure 69 Loading a relocatable memory file Load Memory fe S A eE A EL tbfspramoimem 3 C Load Type Address Range b File Only C AIl Data Only Addresses in decimal Both File and D ata Start End 1500 3d File Load File Format Werlog Hex 3e Yerilog Binary MTI
54. ftware was obtained pursuant to DFARS 227 7202 3 a or as set forth in subparagraphs c 1 and 2 of the Commercial Computer Software Restricted Rights clause at FAR 52 227 19 as applicable Contractor manufacturer is Mentor Graphics Corporation 8005 SW Boeckman Road Wilsonville Oregon 97070 7777 USA THIRD PARTY BENEFICIARY For any Software under this Agreement licensed by Mentor Graphics from Microsoft or other licensors Microsoft or the applicable licensor is a third party beneficiary of this Agreement with the right to enforce the obligations set forth herein AUDIT RIGHTS With reasonable prior notice Mentor Graphics shall have the right to audit during your normal business hours all records and accounts as may contain information regarding your compliance with the terms of this Agreement Mentor Graphics shall keep in confidence all information gained as a result of any audit Mentor Graphics shall only use or disclose such information as necessary to enforce its rights under this Agreement CONTROLLING LAW AND JURISDICTION THIS AGREEMENT SHALL BE GOVERNED BY AND CONSTRUED UNDER THE LAWS OF THE STATE OF OREGON USA IF YOU ARE LOCATED IN NORTH OR SOUTH AMERICA AND THE LAWS OF IRELAND IF YOU ARE LOCATED OUTSIDE OF NORTH AND SOUTH AMERICA All disputes ModelSim Designer Tutorial 16 17 arising out of or in relation to this Agreement shall be submitted to the exclusive jurisdiction of Dublin Ireland when the laws of Ireland ap
55. ghlight the data for the addresses 0x0000000c 0x0000000e as shown in Figure 74 Right click the highlighted data and select Change This brings up the Change dialog box Figure 75 Note that the Addresses field is already populated with the range you highlighted Select Value as the Fill Type Enter the data values into the Fill Data field as follow 34 35 36 Click OK The data in the address locations change to the values you entered Figure 76 4 Edit data in place To edit only one value at a time do the following Double click any value in the Data column Enter the desired value and press Enter When you are finished editing all values press the Enter key on your keyboard to exit the editing mode If you needed to cancel the edit function press the Esc key on your keyboard ModelSim Designer Tutorial Figure 74 Changing contents by highlighting ram tb dprami merm 00000000 00000002 00000004 00000005 00000005 0000000 0000000 0000000 ut pcs mU v V Figure 75 Entering data to change Change Memory x Instance Name fram_thfdpram mern Address Range 00600 Fill Type r All b Value es Increment Decrement Start 0000000 End 10 00000006 i Random FllData 20 ki 1 i 124 fo 26 D word s Cancel Apply Figure 76 Changed contents for specified addresses fram_tb dpramifmem naadgaogaagpugu 00000002 00000004 uuu
56. gnals that have not toggled Instance Coverage Displays statement branch condition expression and toggle coverage Statistics for each instance in a flat non hierarchical view Details Shows details of missed coverage such as truth tables or toggle details Another coverage related pane is the Current Exclusions pane Select View gt Code Coverage gt Current Exclusions to display that pane e Current Exclusions Lists all files and lines that are excluded from coverage statistics see Excluding lines and files from coverage statistics T 105 for more information These panes can be re sized rearranged and undocked to make the data more easily viewable To resize a pane click and drag on the top or bottom border To move a pane click and drag on the double line to the right of the pane name To undock a pane you can select it then drag it out of the Main window or you can ModelSim Designer Tutorial Figure 78 Coverage columns in the Main window Workspace Conc Files Figure 79 Coverage panes Missed Coverage Missed Statements Ls Hy test sm v X 25 c X 25 into 4 h l zZ8 h l Instance test zm zram Signal dat r X PE E Re CIE Nude count 32 X 27 5 X 27 into data 0 12525 23 endtask 51 12453 Toggle Coverage 255 X 128 100 0 1 Coverage 62 55 X stop Current Exclusions SFull Coverage 62 53 sm v entire file X Z Coverage 6
57. he Default Library c Click OK The Design tab in the Workspace shows the new project and library 2 Import example files a Select File gt Import gt HDL This starts the HDL Import Wizard b Make sure Specify HDL files is selected in the first dialog and click Next c Click the Browse button and navigate to lt install_dir gt examples gt Figure 18 VHDL Select counter vhd and tcounter vhd and click Add Verilog Select counter v and tcounter v and click Add d Click Next e Select work under the Libraries list and click Next f Click Finish Creating projects and importing files T 33 Figure 17 Creating a new project Fal Project E loj x Hew Project Project Hame example Project Path 5 DesignerModeltech6 0 de En Browse Default Library work Lancel Figure 15 HDL Import Wizard HDL Import Wizard Specify HDL Source Files Files to import should be added to the Files to mport list below They will be analyzed in the order they appear First locate a source directory the files contained in the specified directory will be listed in the left hand column Then use the Add gt gt and lt lt Remove buttons to create the list of files to convert in the right hand column Directory C Modeltech6 0a_de examples Browse Files of type All Files v Search Sub Directories Files in Directory Files to Import counter
58. hnotes dropdown on www model com support ModelSim Designer Tutorial T 8 Introduction Before you begin Preparation for some of the lessons leaves certain details up to you You will decide the best way to create directories copy files and execute programs within your operating system When you are operating the simulator within ModelSim s GUI the interface is consistent for all platforms Example designs ModelSim comes with Verilog and VHDL versions of the designs used in these lessons This allows you to do the tutorial regardless of which license type you have Though we have tried to minimize the differences between the Verilog and VHDL versions we could not do so in all cases In cases where the designs differ e g line numbers or syntax you will find language specific instructions Follow the instructions that are appropriate for the language that you are using ModelSim Designer Tutorial Lesson 1 ModelSim Designer overview Topics The following topics are covered in this chapter Introduction Basic ModelSim Designer flow Set vendor tools and default language Create the design Create a project Create design units Create a testbench Simulate the design Synthesize the design Place and route the design Run post place and route simulation T 10 T 11 T 12 T 13 T 13 T 13 T 13 T 14 T 15 T 16 T 17 ModelSim Designer Tutorial T 10 Lesson 1 ModelSim Designer overview Introdu
59. ial Editing state machine properties T 67 The dialog box also allows you to change the suffix or prefix used for Figure 48 The HDL Generation properties internal registered or clocked signal names For this tutorial suffixes are State Machine Properties E E x used with the default values _int and _cld Architecture Declarations Generation Statement Blocks Signals Status Process Declarations Machine Clock 4 Edit HDL generation properties Synchronous Asynchronous Name Prop Delay qe Faling 1 Condition Select the Generation tab Figure 48 sl HDL Style Heri b Set the following for Clock lf GneHot Case Mode No Reset Synchronous Asynchronous 3 Processes C 2 Processes Name Name clk me l El Level High Condition e Edge Falling State Variable Auto Generate Type Add Pragma c Set the following for Reset eee m ae eee vA e Mode Asynchronous valud to output port Enable H Provide Enable v Priority Above Reset M Name reset More ptions are d w Generate interrupts as overrides e ya no r Level High Register state actions on next state Level Low Sandi 1 4 Click OK Default State Assignment Animation Recovery State Sellinas Instrument HDL for animation The constant declaration is added below the Architecture
60. ialog Tools gt Edit Preferences See ModelSim GUI preferences GR 546 in the ModelSim GUI amp Interface Reference for more information a Click the undock icon on the Wave pane Figure 51 The Wave pane becomes a standalone un docked window Add objects using drag and drop You can drag an object to the Wave window from many other windows and panes e g Workspace Objects and Locals a Inthe Wave window select Edit gt Select All and then Edit gt Delete b Dragan instance from the sim tab of the Main window to the Wave window ModelSim adds the objects for that instance to the Wave window c Drag a signal from the Objects pane to the Wave window d Inthe Wave window select Edit gt Select All and then Edit gt Delete Add objects using a command a Type add wave at the VSIM gt prompt ModelSim adds all objects from the current region b Run the simulation for awhile so you can see waveforms ModelSim Designer Tutorial Figure 51 A Wave window docked in the Main window E wave default 4 counter cik x 4 est counter reset x Fi test counter count sxxexxzx sul ave Zooming the waveform display Zooming lets you change the display range in the waveform pane There are numerous methods for zooming the display 1 Zoom the display using various techniques a Click the Zoom Mode icon on the Wave window toolbar b Inthe waveform pane click and drag down and to the right
61. ices this document is not written to support that goal ModelSim Designer Tutorial Where to find our documentation T 7 Where to find our documentation ModelSim documentation is available from our website at www model com support or in the following formats and locations Document Format How to get it ModelSim Installation amp Licensing Guide paper shipped with ModelSim PDF select Help gt Documentation also available from the Support page of our web site www model com ModelSim Quick Guide command and feature quick reference paper shipped with ModelSim PDF select Help gt Documentation also available from the Support page of our web site www model com ModelSim Tutorial PDF HTML select Help gt Documentation also available from the Support page of our web site www model com ModelSim User s Manual PDF HTML select Help gt Documentation ModelSim Command Reference PDF HTML select Help gt Documentation ModelSim GUI amp Editor Reference PDF HTML select Help gt Documentation Command Help ASCII type help command name at the prompt in the Transcript pane Error message help ASCII type verror lt msgNum gt at the Transcript or shell prompt Tcl Man Pages Tcl manual HTML select Help gt Tcl Man Pages or find contents htm in modeltech docs tcl_help_html Technotes HTML select Tec
62. igure 37 ModelSim Designer Tutorial T 50 Lesson 3 Creating block diagrams Adding q panel Figure 38 The updated block diagram 7 A panel can be useful to outline areas of a diagram For example you can use a 500000 E etd 0 o ux x uu Ulu xo x o o xo vv ECT METRE NS SE s t std l panel to outline a vievv used for simulation or animation EEE rswdee 0007 stop std logic alarm std logic high std logic C DOWNTO nn high stdTlogic vector 3 DOUTE 0 gt 1 Click the E1 button Package List nn Diagram Signals E DEMNM D LIBRARY ieee SIGNAL beep std logic USE ieee std logic 1164 all m 5 8 u SIGNAL clear std_logic USEieeesti lop I AL aan 1 std clone vector 3 Dom 0 2 Click and drag a panel that encloses the graphical objects on your diagram L SIGNAL zero std logice 6 The panel is added with the default name Panel0 DAMI RE arten eg ms o fee de Os ee k 3 Click the button to save your work Your block diagram should look s milar to the one shown in Figure 38 7 5055 control bundle reset start stop Fort 2 alarm lt hold OR beep i Created on 01 June 2004 Tile Top Level Block Diagram Path GraphTutorTimerstruct 0 Edited by Noah on 01 Jun 2004 ModelSim Designer Tutorial Lesson wrap up 51 Lesson wrap up This concludes this lesson In the next lesso
63. igure 45 The new child state diagram Figure 46 States and transitions added to the diagram 3 Edit the states a Use the State tab of the Object Properties dialog and the tables at the right to edit the states Creating a hierarchical state machine T 63 State names and actions for VHDL Old Name New Name Actions sO standby hold lt 1 sl alarm hold lt 1 clear lt 1 beep lt 1 counting none suspended hold lt 1 end_count hold lt 1 clear lt 1 State names and actions for Verilog Old Name New Name Actions sO standby hold 1 clear 0 load 0 hold 1 clear 1 load 0 beep 1 counting hold 0 clear 0 load 0 suspended hold 1 clear 0 load 0 end_count hold 1 clear 1 load 0 ModelSim Designer Tutorial T 64 Lesson 4 Creating state diagrams A Edit the transitions a Use the Transitions tab of the Object Properties dialog and the tables at the right to edit the transitions ModelSim Designer Tutorial Transitions for VHDL Origin State Destination State Priority Condition Actions suspended counting 1 stop 0 none counting suspended 2 stop 1 none counting alarm zero none standby counting start 1 none standby alarm zero
64. imulation dialog already has the correct design unit specified The dialog appears in case there are other settings you need to modify to run the simulation See Start Simulation dialog GR 58 in the ModelSim GUI amp Editor Reference for more details on this dialog b Click OK ModelSim Designer Tutorial Figure 13 Simulating the top level of the design FA Workspace Workspace anme Type aid uart Project Library aN New cpu_interfaceBlock serial interf Black 4 status regis Block tester Black mit rcv c Block address_de Component w clock divider Component w control_ope Component EH EEE pe testbench Component E ENS Sper EI MB uart_top Refresh Rename 4 Cut Copy O Delete Show Side Data Hide Side Data Expand Collapse Toggle Top Marker Graphical Test Bench Import Gate Level Properties Path Filer C MS Desi CMS Desi 10 x za Compile R Technology Selection n z Synthesis lins Place amp Haute Simulating the design T 31 2 Add items to a Wave window Figure 14 Adding objects from the current region to a Wave window a Sim tab of the Workspace right click uart_tb and select Add gt Te Workspace Add to Wave Figure 14 This adds objects from the current region to a Wave window that is displayed in the Main window MDI frame Figure 15 Vie
65. includes three categories of information Side Data category Description Design Data non HDL files that are required for the design e g substitute synthesized design unit SDF files etc User Data any design related files that you want to collect in one spot e g scripts design documentation etc Downstream Data files that are required for specific downstream tools Managing designs with the Design tab T 29 Figure 12 Side Data for the UART design S Workspace Workspace Project 3 D esignD ata Library MS Pw New d synthesis address de Block B Mew 4 epu interfaceBlock J constraints serial interf Block C Mew aL status reqis Block epu interface ctr 4 tester Block E epu interface sdc amp m t rev c Block User Data clock divider Component M Mew control ope Cormponent Downstream Data WE testbench Component a L eanarda 2 ModelSim Designer Tutorial T 30 Lesson 2 Working with ModelSim Designer Simulating the design To simulate the sample UART design we will load the top level which is uart_tb Load the design a Right click uart tb and select Flow gt Simulate Figure 13 ModelSim automatically compiles any source files that haven t already been compiled or that have changed since the last simulation Once all files are compiled ModelSim opens the Start Simulation dialog The Start S
66. ing block diagrams state machines and HDL text files from the Design tab Load a design with the Start Simulation dialog e Add waves to the wave window and run the design In later lessons you will practice using some of the individual tools such as the block diagram editor and Dataflow window Related reading ModelSim User s Manual Chapter 3 Projects and design management UM 23 ModelSim Designer Tutorial Starting up Designer Start ModelSim Designer a Use the ModelSim Designer icon in Windows If you see a Welcome window appear click Close 2 Specify your vendor tools and default language The first time you invoke ModelSim Designer you are prompted to identify your vendor tools and which libraries you want to compile Figure 1 Starting up Designer Figure 1 The Tool Set Up dialog Z Tool Set Up amp Library Compiler E X Tool Setup This iz the first time that you have run M delbim Designer Please select from the list which tools to use by default FPGA Vendor iin 2a Synthesis Tool Precision RT 7j 2b FPGA Libraries a Select FPGA vendor The Following vendor tools have been auto b 1 hesi 1 detected The simulation libraries that have been Select your Synt esis tool automatically selected will be compiled Use the hift keys and the right mouse button to Select the language change selection of libraries d Select the libraries you want to compil
67. is lesson T 96 on the previous page Click Remove All if necessary to remove any files listed from a previous import Import all of the HDL files 4 Enable coverage statistics Select Compile gt Compile Options and move to the Coverage tab Select Statement Branch Condition and 0 1 Toggle coverage statistics Figure 77 Click OK Compiling the design T 97 Figure 77 Selecting coverage types in the Compiler Options dialog Compiler Options m xi VHDL Verilog Coverage 5 ystemC 414 H Enable Statement Coverage M Enable Branch Coverage M Enable Condition Coverage Enable Expression Coverage MW Enable 0 1 Toggle Coverage Enable 0144 2 Toggle Coverage Cancel Apply ModelSim Designer Tutorial T 98 Lesson 7 Simulating with Code Coverage Loading and running the design 1 Load the design a On the Design tab click the icon next to the coverage library b Right click fest sm and select Flow gt Simulate c Click the Others tab and check Enable Code Coverage d Click OK 2 Run the simulation e Type run 1 ms at the VSIM gt prompt When you load a design with Code Coverage enabled ModelSim adds several columns to the Files and sim tabs in the Workspace Figure 78 ModelSim also displays three Code Coverage panes in the Main window Figure 79 e Missed Coverage Displays the selected file s un executed statements branches conditions and expressions and si
68. is redrawn as a hierarchical state with a triple outline and darker fill color Double click the count hierarchical state to create the new hierarchical child state diagram A new child state diagram is opened as a tabbed window initialized with a default state sO connected to an entry point and exit point by transitions with default conditions Figure 45 Notice that the name of the hierarchical state count is included in the window title GraphTutor Control fsm csm count This convention shows that the child diagram is a partial view of the parent diagram 2 Add states and transitions to the diagram Select the exit point and select Diagram gt Change to gt State While the new state is selected drag with the right mouse button and release the mouse button with the ghosted state to the left and below the first state Use the Copy Here option from the popup menu to make a copy of the state at the cursor position Repeat this procedure to add two more states on the diagram This method for adding objects can be useful when you want to add an object with the same or similar properties and attributes to an existing object Use the button to add a new exit point and the button to connect transitions between the states as shown in Figure 46 Note You can add route points by clicking at several points between states to create a smooth arc as shown in the picture between states 52 and 53 ModelSim Designer Tutorial F
69. logic none none Diagram Signals Old Name Type Constraint Bounds dbus 1 sig sigl sig2 sig3 sig4 std_logic_vector std_logic std_logic std_logic std_logic std_logic index none none none none none 3 DOWNTO 0 none none none none none All occurrences of each signal name including the bundle contents should be automatically updated on the diagram when you confirm the dialog box If any nets are not updated check that you have set the scope for changes to Entire Net in Diagram as described on the previous page ModelSim Designer Tutorial Select the bundle name and use direct text editing or the Bundles tab of the Object Properties dialog box to change the bundle name to control_bundle Your block diagram should look s milar to the one shown in Figure 34 3 Save the diagram a Click the EI button You have previously saved the diagram so you are not prompted for library and design unit names However you have changed the signal names connected to input and output ports and the diagram will be inconsistent with the symbol that was automatically created by the previous save You are prompted whether to update the symbol Click Yes to confirm the save You are prompted whether to update instances of the component where used For this tutorial the Timer is a newly created component and is not used elsewhere Click No Editing block
70. ly terminate upon notice if you exceed the scope of license granted or otherwise fail to comply with the provisions of Sections 1 2 or 4 For any other material breach under this Agreement Mentor Graphics may terminate this Agreement upon 30 days written notice if you are in material breach and fail to cure such breach within the 30 day notice period If Software was provided for limited term use this Agreement will automatically expire at the end of the authorized term Upon any termination or expiration you agree to cease all use of Software and return it to Mentor Graphics or certify deletion and destruction of Software including all copies to Mentor Graphics reasonable satisfaction EXPORT Software is subject to regulation by local laws and United States government agencies which prohibit export or diversion of certain products information about the products and direct products of the products to certain countries and certain persons You agree that you will not export any Software or direct product of Software in any manner without first obtaining all necessary approval from appropriate local and United States government agencies RESTRICTED RIGHTS NOTICE Software was developed entirely at private expense and is commercial computer software provided with RESTRICTED RIGHTS Use duplication or disclosure by the U S Government or a U S Government subcontractor is subject to the restrictions set forth in the license agreement under which So
71. m a Right click the Control block and select Open As gt New View This opens the Open Down Create New View wizard Figure 39 b Select State Diagram and click Next The library and design unit fields are dimmed because they are copied automatically from the library and design unit of the parent diagram The view name defaults to fsm sm for a state machine Figure 40 c Click Finish A new state diagram GraphTutor Control fsm csm is created as a child view of the Control block Note that a default state machine name csm is appended to the design unit and view names in the diagram title Do not change this name Creating a state machine T 55 Figure 39 The Open Down Create New View dialog Open Down Create New View Specify Type E x Specify what kind of file you wish to create using which template File Types Template Files Template Graphical Views Rd Block Diaqram v State Diagram El VHDL Views E Architecture Combined Figure 40 Second page of the wizard Open Down Create New View Specify View Name E El Creating document State Diagram File Specification Library raphTutr 0 vi Design Unit oto ef View name lsm sm ModelSim Designer Tutorial T 56 Lesson 4 Creating state diagrams The state diagram is a blank sheet with page boundaries set for the default printer Figure 41 If you are working with VHDL the diagram includes text objects for the default
72. n you will create a state diagram to define the Control block ModelSim Designer Tutorial T 52 Lesson 3 Creating block diagrams ModelSim Designer Tutorial Lesson 4 Creating state diagrams Topics The following topics are covered in this lesson Introduction Related reading Creating a state machine Adding states and transitions Editing the states and transitions Editing the transitions Creating a hierarchical state machine Editing state machine properties S mulate the control block Lesson wrap up T 54 T 54 T 55 T 56 T 58 T 60 T 62 T 66 T 69 T 70 T 53 ModelSim Designer Tutorial T 54 Lesson 4 Creating state diagrams Introduction In this lesson you will create a graphical state machine to describe the Control block in the block diagram you created in the last lesson You must complete Chapter Lesson 3 Creating block diagrams to proceed with this lesson Related reading ModelSim Graphical Interface and Editor Reference Chapter 2 Introduction to graphical editors Chapter 7 State machines and Chapter 8 State diagram editor ModelSim Designer Tutorial Creating a state machine If you just finished the previous lesson you should already have the block diagram open If not open the GraphTutor project if necessary and open the Timer block diagram by double clicking it in the Design tab of the Workspace 1 Use the Open Down wizard to create a new state diagra
73. nals o SIGHAL dbus dbuz library library zblack black gt uu L 1 Figure 29 A bundle and a global connector sinf HP 2 sig H P M age bundieO 5199 ModelSim Designer Tutorial T 44 Lesson 3 Creating block diagrams Saving the block diagram Notice the asterisk character in the header of the block diagram editor window This indicates that the diagram has been edited since it was last saved 1 Save the diagram a b C d Click the button The Save As dialog box allows you to choose from the currently mapped libraries and specify the design unit and design unit view names Figure 30 Select GraphTutor under Library Type Timer for the Design Unit name Click OK The view name and file extension when you save graphical diagrams defaults as follows struct bd block diagram fsm sm state diagram symbol sb symbol If you omit the suffix it is added automatically The default leaf names can be changed by setting preferences However you should not change the extension bd sm sb or the design data file will not be recognized and cannot be reopened 2 View the saved design unit Switch to the Main window and view the Design tab of the Workspace Expand the Timer component The Timer component has two views the block diagram view and a symbol view Figure 31 Symbol views are created automatically wh
74. ng the license and Mentor Graphics Corporation and Mentor Graphics Ireland Limited acting directly or through their subsidiaries or authorized distributors collectively Mentor Graphics USE OF SOFTWARE INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH IN THIS AGREEMENT If you do not agree to these terms and conditions promptly return or if received electronically certify destruction of Software and all accompanying items within five days after receipt of Software and receive a full refund of any license fee paid END USER LICENSE AGREEMENT GRANT OF LICENSE The software programs you are installing downloading or have acquired with this Agreement including any updates modifications revisions copies documentation and design data Software are copyrighted trade secret and confidential information of Mentor Graphics or its licensors who maintain exclusive title to all Software and retain all rights not expressly granted by this Agreement Mentor Graphics grants to you subject to payment of appropriate license fees a nontransferable nonexclusive license to use Software solely a in machine readable object code form b for your internal business purposes and c on the computer hardware or at the site for which an applicable license fee is paid or as authorized by Mentor Graphics A site is restricted to a one half mile 800 meter radius Mentor Graphics standard policies and pr
75. ny column name and select an object from the list Figure 80 Whichever column you selected is hidden To redisplay the column right click again and select that column name The status of which columns are displayed or hidden is persistent between invocations of ModelSim 2 View statistics in the Missed Coverage pane a Select different files from the Files tab of the Workspace The Missed Coverage pane updates to show statistics for the selected file Figure 81 b Select any entry in the Statement tab to display that line in the Source window ModelSim Designer Tutorial Figure 80 Right click a column heading to hide or show columns Workspace Stmt Graph Branch Count 83 75 3036 DD 22 21 35455 HEEL 1 30 27 30 000 pm 2 10 3 30 000 7 El E Transcript 999755 outof t t ci 999495 outof 000000 999555 outof 000000 999615 outof 000000 499675 outof OO0000cd 499735 outof 000000 333751 illegal ap received 999795 outof 000000 H H H H H H H H I c p Rranrh Hits EZ amp amp amp Eee zz zz zz zz Fullpath Type Stmt Count Stmt Hits Stmt amp Stmt Graph Branch Count Branch Hits Branch Branch Graph Condition Court Condition Hits Condition Condition Graph Expression Court Expression Hits Expression A Expression Graph Branch Ea Ei X Conc Branch Graph 657 1 200 ET s
76. ocks Components Generics Declarations Frames Text Signals Bundles Number of selected Comments 1 Bounding Box 2 Modify the HDL code v Resize to Fit Text a Select the text re display the Object Properties dialog box if necessary Text Position Top 7 using the button and choose the Text tab 7 Medi b Check Resize to fit text 5 OR1 2 c Modify the VHDL code so it reads as follows Figure 36 SE RS Er OR1 2 alarm lt hold OR beep If you are working in Verilog the code will look like this ORL 2 assign alarm hold beep d Click OK The modified HDL text is checked for syntax errors and applied to the diagram EINE ModelSim Designer Tutorial Adding an embedded HDL text view T 49 Modify the block shape Figure 37 The modified OR block The functional blocks on the diagram are shown by default as simple rectangular shapes However it is sometimes useful to use logic notation when a block has a specific logical function For example in this block diagram the OR embedded block represents a logical OR function a Right click the OR block and select Shape gt Autoshapes b Select Or in the dialog and click OK c Right click the ORI block and select Object Properties alarm hold OR beep d On the Embedded Blocks tab uncheck Show Ports when connected to hide the port arrow heads e Click OK The ORI embedded block should now look similar to the one shown in F
77. ograms which vary depending on Software license fees paid or service plan purchased apply to the following and are subject to change a relocation of Software b use of Software which may be limited for example to execution of a single session by a single user on the authorized hardware or for a restricted period of time such limitations may be communicated and technically implemented through the use of authorization codes or similar devices c support services provided including eligibility to receive telephone support updates modifications and revisions Current standard policies and programs are available upon request ESD SOFTWARE If you purchased a license to use embedded software development ESD Software Mentor Graphics grants to you a nontransferable nonexclusive license to reproduce and distribute executable files created using ESD compilers including the ESD run time libraries distributed with ESD C and C compiler Software that are linked into a composite program as an integral part of your compiled computer program provided that you distribute these files only in conjunction with your compiled computer program Mentor Graphics does NOT grant you any right to duplicate or incorporate copies of Mentor Graphics real time operating systems or other ESD Software except those explicitly granted in this section into your products without first signing a separate agreement with Mentor Graphics for such purpose BETA CODE
78. pace f Select View gt Workspace to re open the Workspace No Design Loaded Ru 7U7TU V U U U1MUU UU UUU U UUU ModelSim Designer Tutorial Navigating the ModelSim interface T 25 2 Move and resize panes Figure 7 Panes rearranged in the Main window a Hover your mouse pointer on top of the Transcript title bar so it becomes Te ModelSim Designer PLUS 6 0 Beta 2 a four headed arrow File Edit View Format Compile Simulate Add Tools Window Help b Click and drag the Transcript up and to the right until you see a gray HE Project A a LIART Lib ote Loading Preferences outline on the right hand side of the MDI frame 7 Note Loading Preferences fram C Documents and 5 ettinggsmcarnes s Application Data Modelaim Design When you let go of the mouse button the Transcript is moved and the ne ae 1 1 ets MDI frame and Workspace panes shift to the left Figure 7 M IR SER UNE s from C Documents and Settings m C Select Window Initial Layout cames pplication Data Madelsim Designershds_bteamv2004 1 a hds _team_prefs H The layout returns to its original setting H Note Loading HDS Project file fro m user preferences CMS Designe Important Moving panes can get confusing and you may not always Modeltech6 0_de_beta2p1 exam les vehdlhuart hd obtain the results you expect The general rule is as follows any pane ey can be split vertically or horizontally
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81. ponent BlackDiagram tap struct bd 1b L Generated uar top struct v hd Symbol uart top symbol sb P testhenchT estBench UAR T hda th data uart tep testbe File Edit View HDL Diagram Compile Simulate Add Options Window Help PEE UE BS 57 Cu CRE VOCUM data out 8 Less Pe VENTES int_en CORREDOR en UART BU ser if select 1 0 EH clk div en addr flags clear flags 0 2 0 enable_write start_xmit ser if data 7 0 div data int enable xmit clk enable rev clk data_in data_in sin ModelSim Designer Tutorial T 28 Lesson 2 Working with ModelSim Designer Double click uart_top symbol sb to open a symbol and interface view Figure 10 Click the Interface tab Select File gt Close Window If ModelSim prompts you to save changes click No Double click uart_top_struct vhd or uart_top_struct v if you are using the Verilog version of the design to open the HDL generated from the block diagram Figure 11 The file opens in a Source editor in the MDI frame of the Main window ModelSim Designer Tutorial Figure 10 A symbol view of uart_top UART uart top symbol Symbol m ni xi File Edit view HDL Diagram Add Options Window Help B e Slt Es j c Allo l z ul 1111 Ill gt Be R AM gt r e n d amp e
82. praml mem 0 15 n n n n 00000006 0000000 00000012 00000013 0000001 00000024 0000002 000000 30 00000036 00000032 00000042 00000048 A o 0 Figure 59 The mem tab in the MDI pane shows instance ram tb spram1 mem ram b spraml nem di di d di 4i 4i di di di di di di di 4i di di RRRRRTRES di di di di di 4i di di di 4i di di 4i 4i di di Jb Gl LL didi dl dL di di d di di 4i di di di dk Ji Ji di dk d JR di 4i di di di Ai xn di i 3L JL Ji dl dL GL JR dk 4i di di di Ai oe di di dk J Ji di dk ZR JR Y L TL TL nn xn iL dk 4i di di di Ai 3i di di 4i di di di 4i oe di i Jk zh Jk di di oZ ZR di 4i 4i di di Ji oe iL di 4i 4i di di Ji Xi iL i dk Zh Jk di di ae ZR di 4i 4i di di Ji 3i 2i 4 16 Files Memories Ji di dk di di di di di Ji di dk di di di di di Ji di di di di di di di MXMKLALAIML Ji di dk di di
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84. rovided with restricted rights Use duplication or disclosure by the U S Government or a U S Government subcontractor is subject to the restrictions set forth in the license agreement provided with the software pursuant to DFARS 227 7202 3 a or as set forth in subparagraph c 1 and 2 of the Commercial Computer Software Restricted Rights clause at FAR 52 227 19 as applicable ModelSim Designer Tutorial Table of Contents OT 7 1 5 Lesson 1 ModelSim Designer overview 1 9 Lesson 2 VVorking vvith ModelSim Designer 1 19 Lesson 3 Creating block diagrams 1 37 Lesson 4 Creating state diagrams T 53 Lesson 5 Viewing simulations in the Wave window T 71 Lesson 6 Viewing and initializing memories T 81 Lesson 7 Simulating with Code Coverage T 95 A 7 1 115 T 3 ModelSim Designer Tutorial T 4 ModelSim Designer Tutorial Introduction Topics The following topics are covered in this chapter Assumptions Before you begin Example designs T 6 T 8 T 8 ModelSim Designer Tutorial T 6 Introduction Assumptions We assume that you are familiar with the use of your operating system We also assume that you have a working knowledge of VHDL and or Verilog Although ModelSim is an excellent tool to use while learning HDL concepts and pract
85. ry dialog Figure 72 b Click the Addresses radio button and enter the start address as 0x00000006 and the end address as 0x00000009 The Ox hex notation is optional c Select Random as the Fill Type d Enter as the Fill Data setting the seed for the Random pattern e Click OK The data in the specified range are replaced with a generated random fill pattern Figure 73 Interactive debugging commands T 91 Figure 71 Original memory contents BS ram tb dpram 1 mem n n nn c 03 00000002 Ya ib 00000004 te 14 00000006 1 1f 00000008 20 21 0000000 0000000 za 25 0000000 26 27 hfram_tbv Emen Figure 72 Changing memory contents for a range of addresses Change Memory x Instance Marne ng ram thidprani mem 2b Address Range SASA Fill Ca Value is Addresses Inerement 1 r D t Start 0 00000008 0x00000009 5 ie Random 2c FllData Skip il F word s 2d OK Cancel Apply Figure 73 Random contents of a range of addresses fram_tb dprami mem 00000000 00000002 00000004 00000006 00000008 0000000 00000002 0000000 Go ModelSim Designer Tutorial T 92 Lesson 6 Viewing and initializing memories 3 Change contents by highlighting You can also change data by highlighting them in the Address Data pane a C d e Hi
86. ry dialog box Load Memory x Instance Mame ram Hb spram3 mem Load Type Address Range AJ Addresses lin decimal Start o End 65535 File Only C Data Only C Both File and Data File Load File Format Veriloq Hex Verilog Binary MTI Filename data mem mem Browse Data Load 2b Fill Type Value C Increment Fill Data Decrement skip o wordia C Random E am tb spram3 mem a 00000000000000000000000000101000 1 SO000000000000000000000000101001 e 00O000000000000000000000000101010 3 OO000000000000000000000000101011 4 o0000000000000000000000000101100 5 o0000000000000000000000000101101 OOo000000000000000000000000101110 7 00000000000000000000000000101111 2 00000000000000000000000000110000 3 00000000000000000000000000110001 10 0000000000000000000000000110010 11 OSo000000000000000000000000110011 12 00000000000000000000000000110100 Um nl 4 mem mem emdby memg 89 ModelSim Designer Tutorial T 90 Lesson 6 Viewing and initializing memories In this next step you will experiment with loading from both a file and a fill pattern You will initialize spram3 with the 250 addresses of data you saved previously into the relocatable file reloc mem You will also initialize 50 additional address entries with a fill pattern 3 Load the ram_tb spram3 mem instance with a relocatable memory pattern reloc mem and a
87. s Frames Text signals Bundles dbus0 std logic vector 15 DOWNTO sig6 std logic sig std logic sig8 std logic sig3 std logic dbus2 std logic vector 15 DOWNTO 0 dbus3 std logic vector 15 DOWNTO 0 5100 std logic dbus1 std logic vector 15 DOWNTO 0 5100 std logic 5101 std logic sig2 std logic sig3 std logic sig4 std logic Declaration Name abuso Global Net Type td logic vector bd More gt gt Constraint Index C Range C None Bounds 15 DOWNTO fo User Declarations v Align in Columns ModelSim Designer Tutorial T 46 Lesson 3 Creating block diagrams Click Apply to accept the changes Notice that all occurrences on the diagram are updated including the declarations list signals buses and bundle contents and that the lists of port and signal declarations are sorted alphanumerically when the changes are applied to the diagram Use the dialog box to update the port and signal declarations as shown in the following tables For Verilog designs use a type of wire for all ports and signals Ports Old Name New Name Type Constraint Bounds dbus0 d std_logic_vector index 9 DOWNTO 0 sig6 Start std_logic none none sig7 stop std_logic none none sig8 reset std_logic none none sig9 clk std_logic none none dbus2 low std_logic_vector index 3 DOWNTO 0 dbus3 high std_logic_vector index 3 DOWNTO 0 sig5 alarm std_
88. s to 448 ns Mow 1 us Delta 2 1d ModelSim Designer Tutorial T 78 Lesson 5 Viewing simulations in the Wave window 2 Lock cursor B a Right click cursor B in the cursor pane and select Lock B The cursor color changes to red and you can no longer drag the cursor Figure 57 3 Delete cursor B a Right click cursor B and select Delete B ModelSim Designer Tutorial Figure 57 A locked cursor in the Wave window wave default E File Edit View Insert Format Tools Window QAB 2 test_counter clk 1 4 counter reset 0 El counter count 00001010 LI I SS TH I I I I IT 1000 ns 281 ns 199 ns 21 DE Sie 175 ns to 475 ns Now 1 us Delta 2 4 A 4 1 Saving the window format If you close the Wave window any configurations you made to the window e g s gnals added cursors set etc are discarded However you can use the Save Format command to capture the current Wave window display and signal preferences to a DO file You open the DO file later to recreate the Wave window as it appeared when the file was created Format files are design specific use them only with the design you were simulating when they were created 1 Save a format file a Select File Save Format b Leave the file name set to wave do and click Save c Close the Wave window 2 Load a format file a Inthe Main window select View gt Debug Windo
89. shows the six basic steps for working with ModelSim Designer ModelSim Designer Tutorial T 12 Lesson 1 ModelSim Designer overview Set vendor tools and default language The first time you start ModelSim Designer it prompts you to set an FPGA Vendor Synthesis tool and default language It also scans your system to see if t can find existing vendor tools If it finds any it sets the FPGA Vendor and Synthesis tool to match Z Tool Set Up 8 Library Compiler E xj Tool Setup This iz the first time that you have run M delbim Designer Please select from the list which tools to use by default Vendor iin Synthesis Tool Precision ATL FPGA Libraries The Following vendor tools have been auto detected The simulation libraries that have been automatically selected will be compiled Use the hift keys and the right mouse button to change s lection of libraries Language VHDL v xilins 1 xilinscarelib Once you click OK ModelSim compiles the specified vendor libraries You can compile additional libraries later on by selecting Tools FPGA Library Compiler ModelSim Designer gives you the option of setting different target vendor technologies on a per design unit basis ModelSim Designer Tutorial Create the design ModelSim Designer includes graphical and textual editors to facilitate design creation These editors include Block diagram editor e State ma
90. tables at the right to edit the remaining transitions Use the table that matches the language you are using gt Note The NOUGHTS text string is the name of a constant which will be declared as a state machine property later in this tutorial 3 Click the button to save the state diagram ModelSim Designer Tutorial Transitions for VHDL Destination Priority Condition flush 1 stop 1 flush 3 stop 1 count start 1 load_u d NOUGHTS load_u d NOUGHTS load_t none getkey Transitions for Verilog d ZNOUGHTS Origin Destination Priority Condition count flush 1 stop getkey flush 3 stop getkey count 1 start getkey load_u 2 d NOUGHTS flush load_u 1 d NOUGHTS load_u load_t 1 none load_t getkey 1 d NOUGHTS Your state machine should now look similar to the one shown below haldzz 1 cla aram 0 Jd NOUGSHTS haldzz 1 laadzz 1 Jd NOUGSHTS d NOLUGHTS yid zz Editing the states and transitions T 61 ModelSim Designer Tutorial T 62 Lesson 4 Creating state diagrams Creating a hierarchical state machine In this exercise we will create a child state machine that defines the functionality of the count state 1 Create the child state diagram a Select the count state and select Diagram gt Change To gt Hierarchical State The count state
91. ted with default output ports on the right of the diagram Your diagram should look similar to the one shown in Figure 28 Adding a bundle and a global connector 1 Add the bundle a Use the button to add three signals on the left side of your diagram Notice that a default input port is created at the source of each signal but a dangling net connector is drawn when you double click at the end of each signal b Select the three signals by dragging a selection box around them with the mouse and use the button to connect a bundle containing these signals to block instance U 0 as shown in Figure 29 Notice that the bundle has the default name bundleO and the three selected signals are automatically included in the bundle with their names listed under the bundle name 2 Add the global connector a Use the button to add a global connector on your diagram below the bundle b Use the button to add a signal betvveen the global connector and a default input port This will be a clock signal which is implicitly connected to every block on the diagram Creating a new block diagram T 43 Figure 28 The block diagram with ports and signals Package o Declarations 0 0 0 HBRARY ieee i USE ieee std logic 1165 all N Pills 51 g z man wiege ped legit sector ON USE ieee std logic arith all eo o c 5 cC c dbi 263 E t or l5 gy 2 20 5777 Diagram Sig
92. the csm tab to move back to the parent state machine b Select Diagram State Machine Properties This dialog is described in detail under Setting state machine properties GR 472 in the ModelSim Designer GUI amp Interface Reference C Select the Statement Blocks tab and uncheck Visible for Global Actions Concurrent Statements and State Register Statements There are no global actions concurrent statements or state register statements required in this design so you are hiding the labels for these objects on the state diagram d Ifyou are using VHDL select the Process Declarations tab and uncheck Visible There are no process declarations required in this design 2 Define the NOUGATS constant Suffix Prefix for internal signals Update a VHDL Select the Architecture Declarations tab and enter the C Prefix Suffix Ee following declaration for the 10 bit constant VOUGHTS in the free Registered Sufi im ClockedSuffi eig ERN R IsiDIe format entry box Constant NOUGHTS std logic vector 0000000000 o Came Amy Verilog Select the Module Declarations tab and enter the following declaration for the 10 bit constant VOUGHTS in the free format entry box parameter NOUGHTS 10 b0 3 Edit signal status b Select the Signals Status tab c Change signal beep status to Registered Figure 47 Notice that the Reset value field is automatically updated to 0 ModelSim Designer Tutor
93. thout Mentor Graphics prior written consent and payment of Mentor Graphics then current applicable transfer charges Any attempted transfer without Mentor Graphics prior written consent shall be a material breach of this Agreement and may at Mentor Graphics option result in the immediate termination of the Agreement and licenses granted under this Agreement The terms of this Agreement including without limitation the licensing and assignment provisions shall be binding upon your heirs successors in interest and assigns The provisions of this section 4 shall survive the termination or expiration of this Agreement 5 LIMITED WARRANTY 5 1 Mentor Graphics warrants that during the warranty period Software when properly installed will substantially conform to the functional specifications set forth in the applicable user manual Mentor Graphics does not warrant that Software will meet your requirements or that operation of Software will be uninterrupted or error free The warranty period is 90 days starting on the 15th day after delivery or upon installation whichever first occurs You must notify Mentor Graphics in writing of any nonconformity within the warranty period This warranty shall not be valid if Software has been subject to misuse unauthorized modification or installation MENTOR GRAPHICS ENTIRE LIABILITY AND YOUR EXCLUSIVE REMEDY SHALL BE AT MENTOR GRAPHICS OPTION EITHER A REFUND OF THE PRICE PAID UPON RETURN OF SOFTWARE T
94. to icon display Viewing statistics in the Source window T 103 Figure 86 Coverage numbers shown by hovering the mouse pointer L madeltech examples coverage verlag test sm v reg rst clk wire 31 0 out wire dat wire 3 0 addr reg 31 0 loop nop tasE nop f 5 into ff op wore endtask the ctrl op task ctrl input 7 0 data heqin 5 into 4 h l z6 h y ctrl posedge clk 5 into data end endtazk th test sm v 44 ModelSim Designer Tutorial T 104 Lesson 7 Simulating with Code Coverage Viewing togg le statistics in the Objects Figure 87 Toggle coverage columns in the Source window pa n e T bjects A Toggle coverage counts each time a logic node transitions from one state to n 2 5 another Earlter in the lesson you enabled tvvo state toggle coverage 0 gt 1 and 1 nn 5 pus gt 0 with the cover t argument Alternatively you can enable six state toggle e edt coverage using the cover x argument See Toggle coverage UM 249 for more 12596 1249 y E n information 305271 15531 View toggle data in the Objects pane of the Main window Select fest sm in the sim tab of the Main window 3372 3373 100 b Ifthe Objects pane isn t open already select View gt Debug Windows gt 4699 4689 100 Objects c Scroll to the right and you will see the various toggle coverage columns Figure 87 The blank columns show data when you hav
95. to bring up the Save Memory dialog box Figure 66 c For the Address Radix select Decimal d For the Data Radix select Binary e Type data_mem mem into the Filename field f Click OK You can view the saved file in any editor Memory pattern files can be saved as relocatable files simply by leaving out the address information Relocatable memory files can be loaded anywhere in a memory because no addresses are specified 2 Save a relocatable memory pattern file a Select the mem 1 tab in the MDI pane to see the data for the ram_tb spram2 mem instance b Right click in the mem 1 tab to open a popup menu and select Properties In the Properties dialog set the Address Radix to Decimal and the Data Radix to Binary Click OK to accept the changes and close the dialog d Select File Save to bring up the Save Memory dialog box e Specify a Start address of 0 and End address of 250 f For Address Radix select Decimal and for Data Radix select Binary Click No addresses to create a memory pattern that you can use to relocate somewhere else in the memory or in another memory h Enter the file name as reloc mem then click OK to save the memory contents and close the dialog You will use this file for initialization 1n the next section ModelSim Designer Tutorial Figure 66 Save Memory dialog box X Instance Name ram Ib spram1 rem Address Range AJ C Addresses lin
96. uunun 00000006 00000003 0000000 0000000 FJ Emn BEA NISUS Lesson Wrap up T 93 Lesson Wrap up This concludes this lesson Before continuing we need to end the current simulation 1 Select Simulate gt End Simulation Click Yes ModelSim Designer Tutorial T 94 Lesson 6 Viewing and initializing memories ModelSim Designer Tutorial Lesson 7 Simulating with Code Coverage Topics The following topics are covered in this lesson Introduction E Design files for this lesson Related reading Compiling the design Loading and running the design Viewing statistics in the Main window Viewing statistics in the Source window Viewing toggle statistics in the Objects pane Excluding lines and files from coverage statistics Creating Code Coverage reports Lesson wrap up gt Note The functionality described in this tutorial requires a coverage license feature in your ModelSim license file Please contact your Mentor Graphics sales representative if you currently do not have such a feature T 96 T 96 T 96 T 97 T 98 T 100 T 102 T 104 T 105 T 105 T 107 T 95 ModelSim Designer Tutorial T 96 Lesson 7 Simulating with Code Coverage Introduction ModelSim Code Coverage gives you graphical and report file feedback on which executable statements branches conditions and expressions in your source code have been executed It also measures bits of logic that have
97. w Declaration tester rtl Architecture Open Diagram uart top str Architecture View Inistantiation auo Pack age E E J ASO 1 Add to Dataflow J Copy Add ta List Find Log Expand Selected Collapse Selected Expand All Collapse All Save List Code Coverage End Simulation ave default UULU fUart_thy clk E ruat tb cs 9 ruat tb data in uart_tb data aut Uart_tby irit E uart tbrr L FER ES uart_tbs sin Uns Cursor 1 3 a b Hclock_divider_r hd zulwave 414 ModelSim Designer Tutorial T 32 Lesson 2 Working with ModelSim Designer 3 Run the simulation Figure 16 Waveforms in the Wave window Click in the Transcript pane wave default b Type run 1000 and press enter Jua 000 Waves draw in the Wave window Figure 16 iW ular You will explore additional features of the Wave window in a later 2 Auar lesson TE uar fiat 1 4 Quit the simulation uar 1 a Select Simulate End Simulation Click Yes JOO ns Ons s Es moe ModelSim Designer Tutorial Creating projects and importing files In this exercise you will create a new project and then import some existing HDL files Create the new project Select File New Project b Enter the following in the New Project dialog Figure 17 e Type example for the Project Name e Enter any suitable path Type work for t
98. where in the waveform pane brings that cursor to the mouse location You can also add additional cursors name lock and delete cursors use cursors to measure time intervals and use cursors to find transitions ENT Position the cursor by clicking and dragging a Click the Select Mode icon on the Wave window toolbar flestcounter reset 0 l VVorking vvith a single cursor EE test counter count 100010011 LLLA C C E A XL A A T TTT A b Click anywhere in the waveform pane Cursor 1 372 ns A cursor is inserted at the time where you clicked Figure 54 177 ns ta 448 ns Now 1 us Delta 2 c Drag the cursor and observe the value pane Hari 1000 ns The signal values change as you move the cursor This is perhaps the easiest way to examine the value of a signal at a particular time d Inthe waveform pane drag the cursor to the right of a transition with the mouse positioned over a waveform The cursor snaps to the transition Cursors snap to a waveform edge if you click or drag a cursor to within ten pixels of a waveform edge You can set the snap distance in the Window Preferences dialog select Tools Window Preferences e Inthecursor pane drag the cursor to the right of a transition Figure 54 The cursor doesn t snap to a transition if you drag in the cursor pane ModelSim Designer Tutorial 2 Rename the cursor a Right click Cursor 1 in the cursor name pane and select and delete the
99. ws gt Wave All signals and cursor s that you had set are gone b Inthe Wave window select File gt Open gt Format c Select wave do and click Open ModelSim restores the window to its previous state d Closethe Wave window when you are finished by selecting File gt Close Saving the window format T 79 ModelSim Designer Tutorial T 80 Lesson 5 Viewing simulations in the Wave window Lesson wrap up This concludes this lesson Before continuing we need to end the current s mulation 1 Select Simulate gt End Simulation Click Yes ModelSim Designer Tutorial Lesson 6 Viewing and initializing memories Topics The following topics are covered in this lesson Introduction Related reading Compiling and loading the design Viewing a memory Navigating within the memory Saving memory contents to a file Initializing a memory Interactive debugging commands Lesson Wrap up T 82 T 82 T 83 T 84 T 86 T 88 T 89 T 91 T 93 T 81 ModelSim Designer Tutorial T 82 Lesson 6 Viewing and initializing memories Introduction In this lesson you will learn how to view and initialize memories in ModelSim ModelSim defines and lists as memories any of the following reg wire and std logic arrays nteger arrays e Single dimensional arrays of VHDL enumerated types other than std logic Design files for this lesson The ModelSim installation comes with Verilog and VHDL
100. y ie M library io mo sr ow 08 block m 5277 un 557 U 1 P ox 4 os ModelSim Designer Tutorial T 42 Lesson 3 Creating block diagrams Adding ports and signals You can use the buttons shown at the right to add signal and bus nets on a block diagram Figure 27 S gnals or buses can be added between any existing connectable items on the diagram or left unconnected by double clicking to terminate the net with an open net connector However you can use the vi pulldovvn on the buttons to change the default setting and terminate with a default port or ripper Notice that the toolbar button changes to shovv the current setting VVhen the or button is selected a port is automatically added at an unconnected source or destination end point When the button is selected a ripper is used if the end point is over an existing bus or bundle 1 Add several ports and signals a Choose Signal with Port and use the button to connect three signals originating from the block on the left instance U On the picture to the block on the right instance U_ and one signal returning from U Ito U_O The signals are added with unique names sig0 sigl sig2 and sig3 and the default type std logic Notice how the full declarations for these diagram signals are automatically added to the list of Declarations on the diagram gt Note Allow one or more grid lines between each port or signal You can resize objects by selecting
101. your keyboard The pane scrolls to that address Now let s find a particular data entry a Right click anywhere in the data column and select Find The Find in dialog box opens Figure 65 b Type 11111010 in the Find data field and click Find Next The data scrolls to the first occurrence of that address Click Find Next a few more times to search through the list c Click Close to close the dialog box Viewing a memory T 87 Figure 64 Edit the address directly m E p a m1 mem 30 01000110 31 l lll 32 01001000 33 l l l 34 01001010 35 l l ll 36 01001100 37 01001101 100 lil ulll0 Db 01001111 39 40 01010000 ud 01010001 42 l l l MT 7 mi mem Figure 65 Find in searching for data value ram b spraml mem 10000100 l gn in MS E 1 5 7 Find in ram Eb sprami mem Find data 1 1111010 Find Next Replace with Replace all Find backwards Example Find Patterns 1234 101 011 057 hfa38 Close ModelSim Designer Tutorial T 88 Lesson 6 Viewing and initializing memories Saving memory contents to a file You can save memory contents to a file that can be loaded at some later point in simulation Save a memory pattern from the ram_tb spram I mem instance to a file Make sure ram_tb spram1 mem is open and selected in the MDI frame a b Select File gt Save

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