NEX-SA1100/SA1110 Manual
Contents
1. Pad TLA SA1100 SA1100 Channel Signal Name Pin 15 Q3 Gnd Gnd A13 03 nCAS3 125 B12 E3 7 D31 46 B10 E3 6 D30 42 A12 E3 5 D29 36 A10 E3 4 D28 32 B9 E3 3 D27 24 B7 E3 2 D26 20 9 1 025 14 7 0 024 10 2 7 023 45 4 2 6 022 41 2 5 021 35 4 2 4 020 31 B3 E2 3 D19 23 2 2 D18 19 A3 E2 1 D17 13 Al E2 0 D16 9 Probe Connection 2 Doc Rev 1 10 APPENDIX 1110 Mictor Wiring NOTES numbers for the 256 pin Mini Ball Grid Array packages Blank entries in the SA1110 Pin and Signal columns denote unused TLA inputs that can be wired to any user signal Please refer to the manual from Tektronix for the P6434 High Density probes for important information on designing the necessary connectors into a target system Tek AMP TLA SA1110 SA1110 Tek AMP TLA SA1110 SA1110 Mictor Channel Signal Pin Mictor Channel Signal Pin Pin Pin Pin Pin nRESET_OUT 15 14 Mictor Group Tek AMP TLA SA1110 SA1110 Tek AMP TLA SA1110 SA1110 Mictor Mictor Channel Signal Pin Mictor Mictor Channel Signal Pin 4 Pin Pin Pin Pin SDCLKO DQM3 DQM2 nSDCS3 nSDCS2 nSDCS1 nSDCSO nOE nWE nSDCAS nSDRAS Mictor Group C SAIIXX MN XXX 26 Doc Rev 1 10 APPENDIX 1110 Mictor Wiring TLA SA1110 SA1110 Tek AMP TL2. 812 637 DQM3 K13 Bio cro C36 DQM2 5 12 15 412 css 115 cia 34 14 nSDCS3 115 87 2 7 eo nSDCS2 114 ao 1 A49 nSDCS1 113 LAT 7 30 nSDCSO K16 Be cos 2 05 1 44 coa 1 4 83 co3 1 83 ca 15 1 C02 3 622 nWE MI3 __ 7621 nSDCAS L16 c29 nSDRAS M14 Probe Connection C0 C1 Probe Connection C2 C3 Pad TLA SA1110 SA1110 Pad TLA SA1110 SA1110 Signal Name Channel Signal Name Pin 15 00 13 00 812 D37 D31 M1 0 03 6 230 12 12 D3 5 D29 K3 Al0 03 4 D28 1 9 03 3 027 4 7 03 2 026 G3 A9 D3 1 D25 F3 7 23 0 024 02 7 023 2 4 02 6 022 13 02 5 021 2 4 D2 4 D20 J2 B3 D2 3 D19 GI 02 2 D18 G4 A3 D2 1 D17 El Al D2 0 D16 DI Probe Connection D0 D1 Probe Connection D2 D3 SAIIXX MN XXX 29 Doc Rev 1 10 APPENDIX Necessary Signals for Clocking To properly acquire SA 1100 bus activity in Bus Cycle Clocking mode see Section 5 0 for further information on this mode the following signals must be provided OUT nRASO 3 and nCAS0 3 If Bus Cycle Clocking does not work move to the Ac
3. EE AL 600 ___ ___ __ Probe Connection C0 C1 Pad TLA SA1100 Channel Pin AIS CK Gnd 5 1100 Signal Probe Connection D0 D1 SAIIXX MN XXX Pad TLA SA1100 SA1100 Channel Signal Name Pin 15 13 CK3 nRAS3 121 12 C3 7 B10 C3 6 A12 C3 5 A10 C3 4 B9 C3 3 B7 C3 2 A9 C3 1 7 C3 0 B6 22 7 3 133 4 2 6 nCS2 134 A6 C2 5 nCS1 135 A4 C2 4 50 136 B3 C2 3 nOE 118 2 2 117 2 1 nRASI 123 1 2 0 nRASO 124 Probe Connection C2 C3 Pad TLA SA1100 SA1100 Channel Signal Name Pin 15 00 13 0 nCASO 128 B12 D3 7 B10 D3 6 12 03 5 10 03 4 9 3 3 7 03 2 9 03 1 7 03 0 2 7 Do Not Use DNU B4 D2 6 Do Not Use DNU A6 D2 5 Do Not Use DNU AA D2 4 Do Not Use DNU B3 D2 3 Do Not Use DNU Bl D2 2 Do Not Use DNU A3 02 1 Do Not Use DNU 1 02 0 Do Not Use DNU Probe Connection D2 D3 Doc Rev 1 10 TLA SA1100 SA1100 Channel Signal Name Pin 2 DES BIO 6 40 BEEBE 90 n 19 12 GBED ADB 0 Lei tor py 8 B4 Boe 59 1 Eoo 7 Probe Connection E0 E1 SAIIXX MN XXX
4. r0 TUCRegister TUCR Test Control Register LDR rl Bit31Mask Bit 31 Mask LDR 13 r0 Get current TUCR contents ORR 15 13 11 Set Bit 31 true 1 STR r5 r0 Write TUCR to set Bit 31 END SAIIXX MN XXX 32 Doc Rev 1 10 APPENDIX Clocking Considerations Because of timing differences between versions of StrongARM SA 1100 micro and also due to design of the target it may be necessary to adjust the sample point of some of the acquisition groups for ensure proper data acquisition The TLA600 700 Logic Analyzer cards require a 2ns stable data window to guarantee data acquisition and by default this window is defined as 2ns Setup Ons Hold for all groups relative to the RCLK OUT clock edge However this Setup and Hold value can be adjusted on a group by group basis to meet the target s timing requirements This is done by moving to the LA card s Setup window and clicking on the More button next to the right of the Clocking field A window similar to that shown in Figure 4 will appear In this example the Address DRAMA ddr Control and RASAddr groups have been left at the Support Package Defaults selection which is defined as 2ns Setup Ons Hold The Data group has been adjusted to 115 Setup Ins Hold When using a TLA running V3 0 software these adjustments are made by left clicking on the Setup Hold Window field and then choosing the desired Setup value from the menu field The process may be slightly different when u
5. Immediate post indexed Register post indexed Scaled register post indexed Addressing Mode 3 Immediate offset Register offset Immediate pre indexed Register pre indexed Immediate post indexed Register post indexed Addressing Mode 4 Increment after Increment before Decrement after Decrement before Addressing Mode 5 Immediate offset Immediate pre indexed Immediate post indexed 7 5 SA 1100 Instructions Supported ADC lt cond gt S Rd Rn lt shifter_operand gt ADD lt cond gt S Rd Rn lt shifter_operand gt AND lt cond gt S Rd Rn lt shifter_operand gt B L lt cond gt lt target address gt BIC lt cond gt S Rd Rn lt shifter_operand gt BX lt cond gt Rm CDP lt cond gt p lt cp gt opcode 1 CRd CRn CRm opcode 2 CMN lt cond gt Rn shifter operand CMP lt cond gt Rn shifter operand EOR cond 5 Rd Rn shifter gt LDC lt gt lt num CRd addressing mode LDM cond addressing mode Rn registers LDM 1 LDM lt gt addressing mode Rn lt registers gt LDM 2 SAIIXX MN XXX 18 Doc Rev 1 10 LDM LDR LDR LDR LDR LDR LDR LDR MCR MLA MOV MRC MRS MRS MSR MSR MSR MSR MUL MVN ORR RSB RSC SBC SMLAL SMULL STC STM STM STR STR STR STR STR SUB SWI SWP SWP TEQ TST UMLAL UMULL SAIIXX MN XXX lt
6. addressing mode lt cond gt T Rd post indexed addressing mode cond lt S gt Rd Rn shifter operand cond 24 bit immediate cond Rd Rm Rn lt cond gt B Rd Rm Rn cond Rn shifter operand cond Rn shifter operand cond S RdLo RdHi Rm Rs cond S RdLo RdHi Rm Rs 19 1 10 8 0 CONTROL GROUP SYMBOL TABLES The use of Symbol Tables when displaying state data and defining a trigger enables the user to quickly determine the type of bus cycle that occurred or is desired Symbol tables for the Control group SA1100 Ctrl NEX Brutus Table 4 and SA1110 Ctrl Table 5 have been provided to quickly show the type of bus transaction acquired when viewing data in Listing display This same symbol table can be used in the Trigger area of the TLA to easily define the sort of bus cycle that is to be triggered on Pattern TLA600 700 Symbols Meaning 01 READ FETCH Read or Fetch Cycle 10 WRITE Write Cycle Table 4 NEX SA1100 NEX Brutus Control Symbol Table Signals from left to right nWE Pattern TLA600 700 Symbols Meaning READ FETCH Read or Fetch Cycle WRITE Write Cycle RAS CYCLE RAS Address Cycle CAS CYCLE CAS Address Cycle REFRESH Memory Refresh Cycle Table 5 NEX SA1110 Control Symbol Table Signals from left to right 5 5 nSDCAS nOE nWE SAIIXX MN XXX 20 Doc Rev 1 10 APPENDIX 110
7. D 29 L PCLK A 22 nRESET OUT VDDX2 VDDXI VSSX VDDX3 VSSX VSSX VDDX2 ROMSEL 2161 1200 21 0141 1201 TESTCLK D 22 LDD2 TMS D 30 LDD3 TCK D 7 1004 TDI D 15 LDD5 TDO D 23 LDD6 nTRST D 31 LDD7 BATT FAULT VDD VDDXI VSSX VSS VSSX VDDX1 VDDX2 L_LCLK VDD_FAULT VSSX L_FCLK PWR_EN GP 27 nPOE SFRM_C GP 26 nPWE SCLK_C SAIIXX MN XXX 34 Doc Rev 1 10 APPENDIX I StrongARM SA 1110 Pinout This table shows the pinout for the 256 pin mini BGA package 57 16 A 21 vs 157 me arn gt gt gt gt 5 ule D gt nTRST gt E BATT FAULT VSSX VDDXI VDD FAULT PWR EN SFRM C 224 SCLK C Q uv N 55 lt 5 8 2519 a Q19 o e Bla oo w gt gt xis lalala alu lt 8 gt gt s 21515 gt Un e 0 al d L L L K K E VDDXI UDC UDC RXD 1 TXD 1 GPI 5 RXD 2 GP 4 TXD_2 GP 3 RXD_3 TXD_3 VSSX VDDXI jue TEXTAL PEXTAL PXTAL VDDP SS nRESET nRESET 2 lt 21 SAIIXX MN XXX Doc Rev 1 10 APPENDIX J Support About Nexus Technology Inc NEXUS TECHNOLOGY Established in 1991 Nexus Technology Inc is dedicated to developing ma
8. do ee iet ash be ac adeptes i dos 15 Figure 3 Disassembly Display Filter 10 Mark Opcode WIDdONe ve b le wa aching dy 17 Figure Setup Hold scd itae een ends 33 TABLE OF TABLES Table 1 1100 TLA600 700 Channel eene eene ennt 8 Table 2 SA 1110 TLA600 700 Channel Grouping seen enne ennemi 9 Table 3 Brutus TLA600 700 Channel Grouping 4 eee deese neto een nnne 10 Table 4 NEX SA1100 NEX Brutus Control Symbol 20 Table 5 1110 Control Symbol 20 SAIIXX MN XXX 4 1 10 1 0 OVERVIEW 1 1 General Information The 5 11 disassembly software support provides disassembly of acquired StrongARM SA 1100 or SA 1110 bus cycles using a TLA600 700 series logic analyzer For SA 1100 support a 136 channel acquisition module is required for SA 1110 support a 102 channel acquisition system is required In both cases a 100 TLA acquisition card is sufficient unless the core clock frequency is expected to approach or exceed 200MHz The NEX SA11XX support is software only Please see Section 3 0 Connecting to an SA 11XX Target for information on probing The NEX SA11XX provides full instruction decoding of ARM though Architecture v4 Thumb instructions are not supported at this time
9. 1 10 APPENDIX NEX SA1100 P6860 Compression Pinout NOTES The pin numbers are identical for the 208 pin Quad Flat Pack and 256 pin Mini Ball Grid Array packages Blank entries in the SA1100 Pin and Signal columns denote unused TLA inputs that can be wired to any user signal For further information on the P6860 Connectorless probe compression footprint please refer to the P6810 P6860 and P6880 Logic Analyzer Probes Instruction Manual Tektronix part number 071 1059 00 Pad TLA SA1100 Signal Name Probe Connection A0 A1 SAIIXX MN XXX N SA1100 Pin L B9 211115 Bo 7 7 163 TLA SA1100 SA1100 Channel Signal Pin Name 15 13 nRESET OUT 192 B12 7 10 A3 6 A12 A3 5 A10 4 9 A3 3 B7 A3 2 9 1 25 137 7 A3 0 24 138 2 7 23 139 4 2 6 22 140 2 5 21 143 4 2 4 20 144 B3 A2 3 A19 145 2 2 18 146 2 1 17 147 1 2 0 16 148 Probe Connection A2 A3 Doc Rev 1 10 TLA Channel SA1100 Signal Name SA1100 Pin BAE BIO cio AI CES BNT ECEE 12 01 1 LATI OB a ___ c t en 0 0 0 o LAGE COS 22 cos 17022224 12
10. 10
11. 12 CASlines All 10 CASAddr7 CASAddr6 Selects CAS Addr5 CASAddr4 CAS Addr3 CASAddr2 OUT 52 CAS Addr1 nRESET_OUT 192 CAS Addr0 DRAM DRAM AO Table 1 SA 1100 TLA600 700 Channel Grouping SAIIXX MN XXX 8 Doc Rev 1 10 Signal SA1110 TLA700 Group Signal SA1110 TLA700 Name Pad input Name Name BGA Pin input Address Hex DRAMAddr Control nSDRAS Sym nSDCAS nOE nWE SDCLKO Pl nRESET_OUT C7 Table 2 SA 1110 TLA600 700 Channel Grouping SAIIXX MN XXX 9 Doc Rev 1 10 Signal TLA600 700 Group Signal TLA 600 700 Name input Name Name input Address Hex DRAMAddr CASAddr9 CASAddr8 A19 A18 A17 A16 15 Control A14 Sym WEf A13 RASlines LA_RAS3 12 RAS2f RAS 1 10 RASOf CASAddr7 CASlines LA_CAS3 CAS Addr6 52 CAS Addr5 51 CAS Addr4 LA_CASO CASAddr3 Selects LA_CS3 CAS Addr2 LA_CS2 CAS Addr1 CS14 5 44 0 LA 50 DRAM OUT DRAM AO Table 3 Brutus TLA600 700 Channel Grouping SAIIXX MN XXX 10 Doc Rev 1 10 4 0 CONFIGURING THE SUPPORT The SA 1100 microprocessor supports the use of DRAM for code execution memory However because DRAM is accessed by Row and Column address cycles it becomes more difficult to translate those two cycles into a physical address equivalent which is necessary for tracking the flow of program code The DRAMAddr group for Brutus support is
12. 124 FFFFF555 WRITE 1 888 000 us 000 1 16 008060 0000 124 ANDEQ R12 RO R4 LSR 2 FLUSH 1 1 994 500 us OOOBD 17 00 128 AAAAAAAB WRITE 2 121 000 us 000 1 18 0080 1 01000 MOV R1 RO RO 2 227 500 us 00080 19 0080 0 E28FOFO5 ADD RO R15 05 gt gt 30 2 353 500 us 00080 20 0080 4 2 479 500 us 00080 21 1 2844001 gt gt 77777777 Bl 605 500 05 00080 22 0081 E1AOCOOD m R12 Ro R13 2 731 500 us 00081 UU c 200 US QUU c 24 0081 4 9200800 STMDB R13 Ris Rid 12 2 983 500 us 00081 25 0081 8 E24CBO14 SUB R11 Riz 14 3 321 500 us 00081 26 0081 150000 CMPS RO R13 R10 3 875 000 us 00081 27 008200 4BFFFFDD BLMI 0 0000817 4 107 500 us 00082 28 008204 E24DDO3C SUB R13 R13 3 gt gt 0 4 339 000 us 00082 29 008208 E28B0008 ADD RO R11 08 gt gt 0 4 464 000 us 000827 an P131 4 584 us vo 4 b For Help press F1 Tektronix Figure 2 A1100 Disassembly SAIIXX MN XXX 15 Doc Rev 1 10 The other column of interest is the Mnemonics column where SA 1100 disassembly information is displayed As mentioned previously it is possible to filter the SA 1100 instructions that are displayed This is done via selections made in the Disassembly tab of the Properties window see Figure 3 By def
13. Note that three different supports are included One NEX SA1100 is to be used with generic SA 1100 designs A second NEX SA1110 is for use with an SA 1110 target The third NEX BRUTUS is to be used with the Intel SA 1100 Evaluation Board code named Brutus All versions shall be referred to as NEX SA11XX support except when particular distinctions need to be pointed out In practice the only differences between the NEX SA1100 support and the NEX SA1110 support is that the NEX SA1100 and NEX Brutus supports work with DRAM memory and the NEX SA1110 support works with SDRAM memory This manual assumes that the user is familiar with the SA 1100 1110 processor specification and the Tektronix TLA600 700 Logic Analyzer It is also expected that the user is familiar with Windows 95 and or Windows 98 The TLA600 700 Application must also be at V1 1 or later for the NEX SA11XX support to work properly 2 0 SOFTWARE INSTALLATION Three 31 2 diskettes have been included with the NEX SA11XX disassembly product one for generic SA 1100 support another for SA 1110 support and the third specifically developed for the Intel Brutus SA 1100 development board The NEX SA11XX software is loaded in the same method as other Windows programs Place the desired Install disk in the floppy drive of the TLA600 700 Select Control Panel and run Add Remove Programs choose Install Next then Finish Add Remove will then run SETUP EXE on the floppy and instal
14. OUT C1 0 Delta 1 1 T 2 Mag Address Mag DRAMAddr Mag Data Mag Control Mag L DEH Mag WEH Mag L RAS3H Mag 52 Mag 51 Mag Mag L CAS3H Mag LA CA52H Mag L 518 Mag L 508 Mag Selects Mag LA CS3tt Mag Mag Address Mag DRAMAdd Mag Mag Mag LA DES _ Mag LA WEB LA RAS3H Mag LA RAS2H LA RASTH Mag LA Mag LA CAS3H Mag LA CAS2 Mag LA CASTH Mag LA CASO Mag Selects Mag LA CS3H For Help press F1 Data Tektronix Figure 1 A1100 MagniVu Display on TLA600 700 SAIIXX MN XXX 13 Doc Rev 1 10 7 0 USING THE DISASSEMBLY SOFTWARE 7 1 General Information The NEX SA1100 support software acquires and decodes StrongARM SA 1100 bus activity and displays the information as assembly language mnemonics machine code see Figure 2 This permits the tracing of code execution for debug purposes It is possible to filter the data display cycle types of interest to the software engineer Figure 3 The user can choose to display the acquired data in Hardware Software Control Flow or Subroutine modes A major feature of the 1100 software 15 its ability to intelligently acquire bus cycle information By taking advantage of the data clocking power built in to the Tektronix Logic Analyzers the SA1100 software is able to acquire only the valid SA 1100
15. already configured to properly reconstruct the physical address from Row and Column information The DRAMAddr group in the SA 1100 support is configured by default for the largest memory configuration possible 16Mb Some of the bits presently in this group may need to be deleted to reflect a given target Refer to Section 10 3 Dynamic Interface Operation of the 5 1100 Microprocessor Technical Reference Manual for information on how the DRAMAddr group should be configured for a specific target Note During testing it appeared as if the complete proper physical address is placed on the Address bus during the Row Address cycle However the SA 1100 documentation doesn t appear to mention this and there was concern that this functionality may not be present in later versions of the micro so it was decided ignore this and instead create the DRAMAddr group to handle physical memory addresses 5 0 CLOCK SELECTION 5 1 SA 1100 and Brutus 5 1 1 General Information There is one clocking option available when using the NEX SA1100 and NEX Brutus support packages The selections for this option are explained in detail below As previously mentioned these supports are designed to work with DRAM targets only Please use the NEX SA1110 support for SDRAM targets The clocking mode is selected by moving to the System window clicking on Setup for the appropriate LA card then clicking on More a button to the right of the Clocking field Choose the desire
16. grayed out Inserts the contents of the Clipboard Go To Moves the display to the item of interest Properties Edits the current Listing Display properties Smaller Font Decreases the displayed font size Larger Font Increases the displayed font size Search Backward Moves to a previous data match Define Search Define data to be matched Search Forward Moves to the next data match Mark Opcode Permits placing an opcode mark SAIIXX MN XXX 14 1 10 The format or display properties of each displayed column can be changed by putting the mouse cursor on the heading of the column clicking the left mouse button to select that column clicking the right mouse button to bring up the editing dialog then selecting Properties The column to be modified can also be selected by clicking on the Column tab selecting the column of interest in the Column field then making any desired modifications to that display column The modification or selections possible will vary from column to column Two display columns of particular interest are the Timestamp and Mnemonics columns Timestamp shows a time value associated with the acquisition By default Timestamp shows the time from System Trigger Clicking on the From window in the Timestamp Reference field shows all available selections Absolute from when the Logic Analyzer was started Previous the time from the present sequence to the previous displayed one and three selecti
17. 0 Mictor Wiring NOTES pin numbers are identical for 208 pin Quad Flat Pack and 256 pin Mini Ball Grid Array packages Blank entries in the SA1100 Pin and Signal columns denote unused TLA inputs that can be wired to any user signal Please refer to the manual from Tektronix for the P6434 High Density probes for important information on designing the necessary connectors into a target system Tek AMP TLA SA1100 SA1100 Tek AMP TLA SA1100 SA1100 Mictor Mictor Channel Signal Pin Mictor Mictor Signal Pin Pin Pin Pin Pin 1 nRESET OUT 192 Mictor Group A Tek AMP TLA SA1100 SA110 Tek AMP TLA SA1100 SA1100 Mictor Mictor Channel Signal 0 Mictor Mictor Channel Signal Pin Pin Pin Pin Pin Pin nCAS1 Mictor Group C SAIIXX MN XXX 2 Doc Rev 1 10 APPENDIX A 1100 Mictor Wiring TLA SA1100 SA1100 Tek AMP TLA SA1100 SA1100 Mictor Mictor Channel Signal Pin Mictor Mictor Channel Signal Pin Pin Pin Pin Pin nCASO nRAS2 Do Not Use Do Not Use Do Not Use Do Not Use Do Not Use Do Not Use Do Not Use Do Not Use Do Not Use Do Not Use Do Not Use Do Not Use Do Not Use Do Not Use Do Not Use Do Not Use Mictor Group D Tek AMP TLA SA1100 SA1100 Tek AMP TLA SA1100 SA1100 Mictor Mictor Channel Signal Mictor Channel Signal Pin Pin Pin Pin Pin Mictor Group E SAIIXX MN XXX 22 Doc Rev
18. A SA1110 SA1110 Mictor Mictor Channel Signal Pin Mictor Mictor Channel Signal Pin Pin Pin Pin Pin Mictor Group D SAIIXX MN XXX 27 Doc Rev 1 10 APPENDIX D NEX SA1110 P6860 Compression Pinout NOTES The pin numbers are for the 256 pin Mini Ball Grid Array packages Blank entries in the SA1110 Pin and Signal columns denote unused TLA inputs that can be wired to any user signal For further information on the P6860 Connectorless probe compression footprint please refer to the 6810 P6860 and P6880 Logic Analyzer Probes Instruction Manual Tektronix part number 071 1059 00 Pad B9 AM Bo 7 7 SAIIXX MN XXX TLA SA1110 SA1110 Channel Signal Pin Name Probe Connection A0 A1 Pad TLA 5 1110 SA1110 Channel Signal Pin Name 15 CKO Gnd Gnd 13 12 10 A3 6 A12 A3 5 A10 4 9 A3 3 B7 A3 2 9 1 25 16 A7 A3 0 24 G13 B6 2 7 23 F13 B4 A2 6 A22 F15 A6 A2 5 21 16 4 2 4 20 F14 B3 A2 3 A19 E15 2 2 18 D16 A3 A2 1 A17 14 1 2 0 16 015 Probe Connection 2 3 Doc Rev 1 10 TLA SA1110 SA1110 Pad TLA SA1110 SA1110 Channel Signal Name Pin Channel Signal Name Pin 15 CK3 Gnd Gnd 1 SDCLKO 2
19. NEXUS TECHNOLOGY 5 StrongARM Disassembly Software Users Manual Including these Software Support packages BRUTUS 5 1100 5 1110 Copyright 2008 Nexus Technology Inc rights reserved Contents of this publication may not be reproduced in any form without the written permission of Nexus Technology Inc Brand and product names used throughout this manual are the trademarks of their respective holders SAIIXX MN XXX 1 1 10 Warranty Terms License Agreement For warranty terms refer to the Terms and Conditions of Sale document that was included in the product shipment The Software License Agreement is displayed during installation A hardcopy of that agreement may be obtained from Nexus Technology Nexus Technology products to which this manual refers are subject to the Terms and Conditions of Sale document and the Software License Agreement as appropriate Compliance with WEEE and RoHS Directives This product is subject to European Union regulations on Waste Electrical and Electronics Equipment Return to Nexus Technology for recycle at end of life Costs associated with the return to Nexus Technology are the responsibility of the sender SAIIXX MN XXX N Doc Rev 1 10 TABLE CONTENTS OVERVIEW etae EN 2 LA General Information 5 20 SOFTWARE INS TAU Eis Gu
20. Supported eese 17 7 5 1100 Instructions Supported 18 8 0 CONTROL GROUP SYMBOL TABLES 20 APPENDIX A NEX SAT100 Mictor Wiring 21 APPENDIX NEX SA1100 Mictor Wiring 22 APPENDIX B 1100 P6860 Compression 23 APPENDIX C NEX SA1110 Mictor WIEIES decida Y poe oe Gs 26 APPENDIX C NEX SA1110 Mictor Wiring 27 APPENDIX D NEX SA1110 P6860 Compression 1 28 APPENDIX E Necessary Signals for 30 APPENDIX 5 5 aea cn eds RH PA HR HER Ee e 31 APPENDIX G Clocking 1 33 APPENDIX StrongARM 1100 4 4 34 APPENDIX StrongARM 8 2222 35 APPENDIX J SUDDOEL 36 APPENDIX K 37 1 10 SAIIXX MN XXX TABLE FIGURES Figure 1 5 1100 MagniVu Display on TLA600 700 essen nennen enne 13 Figure 25 S ATIOO Disassembly postato
21. ault 3 or 4 SDCLK cycles Selecting the incorrect value will result in invalid data acquisition during Read or Fetch cycles Read Burst Length This field must be set to the length of Burst Read Cycles that the target is using Valid values are 1 default 4 or 8 cycles The proper value must be set or improper Read and Fetch data acquisition will result SAIIXX MN XXX 12 Doc Rev 1 10 6 0 VIEWING DATA 6 Viewing Timing Data on the TLA600 700 By default the TLA600 700 will display an acquisition in the Disassembly mode However the same data can be displayed in Timing form by adding a Waveform Display window This is done by clicking on the Window pull down selecting New Data Window clicking on Waveform Window Type then choosing the Data Source Two choices are presented SA1100 and SA1100 MagniVu The first will show the exact same data same acquisition mode as that shown in the Disassembly window except in Timing format The second selection SA1100 MagniVu will show all of the channels 2GHz MagniVu mode so that edge relationships can be examined at the module s trigger point With either selection all channels can be viewed by scrolling down the window Refer to the TLA600 700 System User s Manual for additional information on formatting the Waveform display cg _ Status Idle 258 aale os _ pet C1 5 ns C2 5 ns Delta Time 100ns Mag RCLK
22. ault the display is in Hardware mode where all bus cycles are displayed Memory Reads Memory Writes Instructions etc Other choices are Software only executed instructions are displayed Control Flow display of instructions affecting code flow such as Jumps Branches etc and Subroutine only instructions such as Calls Returns etc are displayed Note that when data is suppressed in this fashion that Timestamp information in Previous form will be updated to show the time between displayed cycles About Data Listing Window Column Marks Disassembly Demo Brutus z Show Hardware Disassemble Across Gaps Hardware Software Control Flow Subroutine Figure 3 Disassembly Display Filter Window 7 3 Help The Disassembler s Confused or Using Mark Opcode Because the SA 1100 does not have a signal to denote an opcode fetch it is difficult to distinguish between a Read cycle and an Opcode Fetch The disassembly software does the best it can to figure this out but it assumes that every Read from contiguous memory cycles is a Fetch and this may not always be the case When this happens the user can Mark an Opcode a Sample or Cycle in the List display to help the disassembler re synchronize To do this the user first moves the mouse cursor to the cycle that is to be marked Click on the right mouse button to bring up the menu selections then click on Mark Opcod
23. bus cycles and ignore Idle and Wait states This means that the user is able to make optimum use of the acquisition card s memory and see more microprocessor bus cycles For debug purposes the user also has the ability to override this function and acquire data on every RCLK edge to permit the user to see all of the bus traffic including the Idle and Wait states See Section 5 2 Clocking Options for further information Every stored cycle bus or clock edge depending upon clocking selection has a timestamp value stored with it This time information accurate to 500ps in the TLA600 700 series permits precise measurements of microprocessor bus activity Because of the design of Tektronix Logic Analyzers there is no need to worry about trading off acquisition memory depth when making these measurements as the timestamp memory is separate from the acquisition memory 7 2 Disassembly Using the TLA600 700 The TLA600 700 since it is a Windows program has the same type of user interface as other Windows based applications In the Disassembly Listing window a tool bar at the top of the window contains buttons that allow the user to modify the display These buttons from left to right perform the following functions Add Column Adds a column to the display Add Mark Adds a user mark to the display Cut may be grayed out Cuts the selection to the Clipboard Copy may be grayed out Copies the selection to the Clipboard Paste may be
24. d The SA1100 and Brutus supports require that this clock signal be enabled Sample code to enable this signal and disable the internal data and instruction caches is provided in Appendix C Sample Source Code 3 3 Intel Brutus Evaluation Board The Intel Brutus evaluation board has Mictor connectors placed on it for easy access to the SA 1100 signals However in order for out Brutus support package to function properly several signals must be moved by using a Nexus Technology NEX HDSWIZ adapter for the C Group Mictor The HD SWIZ must be modified as follows The Target end of the HD SWIZ is considered to be the connector that plugs into the Mictor on the Brutus target The TLA end of the HD SWIZ is the connector and latch housing mounted on the larger PC board that receives the P6434 probe from the TLA Cut the PC board traces for Pins 3 18 19 and 36 Connect the following Target pin 7 to TLA pin 19 Target pin 9 to TLA pin 3 Target pin 11 to TLA pin 36 Target pin 6 to TLA pin 18 SAIIXX MN XXX 6 Doc Rev 1 10 Then TLA P6434s should be connected to Brutus board as follows A Group Mictor to J11 E Group Mictor to J12 C Group Mictor to J13 using the HD SWIZ SAIIXX MN XXX 7 Doc Rev 1 10 Signal SA1100 TLA700 Group Signal SA1100 TLA700 Name Pin input Name Name Pin input Address Hex DRAMAddr CASAddr10 CASAddr9 CASAddr8 A21 A20 A19 A18 Control 118 A17 Sym 117 A16 RASlines Al5 14 13
25. d mode in the Clocking Select field NOTE Depending upon the speed of the SA 1100 micro and the design of the target it may be necessary to adjust the Setup amp Hold times for some of the NEX SA1100 data groups to ensure proper data acquisition Please refer to Appendix C Clocking Considerations for further details 5 1 2 Clocking Options Explanation Clocking Mode Bus Cycle Clocking is the default clocking selection In this mode the software monitors the OUT nRASO 3 and 50 3 signals to permit the acquisition of SA 1100 bus cycles only Wait and Idle states will be ignored offering the best use of your acquisition memory Refer to Appendix B for more information on how bus cycle data is acquired With Every Edge of RCLK data will be acquired on every edge of the RCLK signal The disassembly software will try to filter and display these cycles accordingly but incorrect decoding may occur because of the SAIIXX MN XXX 11 Doc Rev 1 10 numerous duplicated cycles This clocking mode shows all bus cycles including any Wait or idle states Since no clocking qualification is done only the RCLK signal is needed 5 2 SA 1110 5 2 1 General Information There are three clocking select fields available when using the NEX SA1110 support package Each is explained in detail below As previously mentioned the NEX SA1110 support is designed to work with SDRAM targets only Please use the NEX SA1100 support for DRAM ta
26. e Another window will appear see Figure 4 which permits selecting the type of cycle that is to be marked Opcode Fetch Memory Read etc Select the desired cycle and then click on Okay To remove an existing Mark select Undo Mark and then click on OK SAIIXX MN XXX 16 Doc Rev 1 10 Select Mark Opcode Extension Flush Memory Read Undo Mark Cancel Apply Figure 4 Mark Opcode Window 7 4 Instruction Decoding Addressing Modes Supported The following lists the particular StrongARM feature sets that the NEX SA1100 disassembler packages supports IMPORTANT The Thumb instruction set is not supported at this time Architecture v4 Level Instructions and Addressing modes Load data read cycle detection LDM and LDC multiple load read cycle detection Branch Prefetch Instruction flush detection Mark Opcode support All five addressing modes Addressing Mode 1 Shifter operands Immediate Register Logical shift left by immediate Logical shift left by register Logical shift right by immediate Logical shift right by register Arithmetic shift right by immediate Arithmetic shift right by register SA11XX MN XXX 17 Doc Rev 1 10 Rotate right by immediate Rotate right by register Rotate right with extend Addressing Mode 2 Immediate offset Register offset Scaled register offset Immediate pre indexed Register pre indexed Scaled register pre indexed
27. gt addressing mode Rn registers and cond Rd addressing mode lt cond gt B Rd addressing mode cond Rd post indexed addressing mode lt cond gt H Rd addressing mode lt cond gt SB Rd addressing mode cond SH Rd addressing mode lt cond gt T Rd post indexed addressing mode cond p lt cp gt opcode 1 Rd CRn CRm opcode 2 cond S Rd Rm Rs Rn cond S Rd shifter gt cond lt gt opcode 1 Rd CRn CRm opcode 2 cond Rd CPSR cond Rd SPSR cond Rd CPSR f 32bit immediate cond Rd CPSR fields Rm cond Rd SPSR f 32bit immediate cond Rd SPSR fields Rm cond S Rd Rm Rs lt cond gt lt S gt Rd shifter operand cond S Rd Rn shifter gt cond 15 Rd Rn shifter operand cond S Rd Rn shifter gt cond Rd Rn shifter gt cond S RdLo RdHi Rm Rs cond S RdLo Rm Rs cond p cp num addressing mode cond addressing mode Rn registers STM 1 cond addressing mode Rn lt registers gt STM Q cond Rd addressing mode cond Rd addressing mode cond Rd post indexed addressing mode lt cond gt H Rd
28. l the Selected support in its proper place on the hard disk To load the support into the TLA600 700 first select the desired Logic Analyzer card in the Setup screen select Load Support Package from the File pull down then choose SA1100 SA1110 or Brutus and click on Okay SAIIXX MN XXX 5 Doc Rev 1 10 3 0 CONNECTING AN SA 11XX TARGET 3 1 General Information It is recommended that the user add Mictor connectors to their target for the interface to the TLA600 700 using Tektronix P6434 high density probes as we are unaware of a clip to permit acquiring the signals directly from the micro Table 1 shows the wiring and Channel Grouping required for 1100 support Table 2 shows the same information but for NEX SA1110 support IMPORTANT Specific wiring must be followed when routing the microprocessor signals to Mictor connectors if NEX SA1100 or NEX SA1110 support is going to be used Appendix A SA1100 to Mictor Connector Wiring shows the connections required for the SA1100 Appendix B SA1110 to Mictor Connector Wiring shows the wiring required for the SA1110 3 2 SA 1100 and GP26 The SA 1100 microprocessor does not offer by default a clock signal that can be used by a Logic Analyzer to acquire bus information synchronously which makes disassembly support difficult if not impossible However there is an option to use one of the General Purpose I O pins GP26 to provide a clock that runs at 1 the core clock spee
29. les ids 2 3 0 CONNECTING AN SA 11XX TARGET 6 3 1 General 6 52 SAT add a ER 6 3 3 Intel Brutus Evaluation Board 4 ee ectetur edi deed reb as ioca 6 Z0 CONFIGURING THE SUPPORT on piedi pipes epist diede qiu tasty feto uiid 11 SPE O T O N G orte ex ied 11 SALTO and enin om oM c x 11 T General Informati n issa 11 5 1 2 Clocking Options Explanation 11 12 5 21 General Informiationi iot estet edere te ai da pcd 12 5 2 2 Clocking Options ExplangtlOn coo rs e ce dot qi kite eph Pedal eg aede UE Ue 12 6 0 VIEWING DATA 13 6 1 Viewing Timing Data on 600 700 13 7 0 USING THE DISASSEMBLY SOFTWARE 14 General nes ea 14 7 2 Disassembly Using 14 7 3 Help Disassembler s Confused or Using Mark 16 7 4 Instruction Decoding Addressing Modes
30. lr save working registers MOV v3 sp save stack pointer must enter supervisor mode to disable caches SAIIXX MN XXX 3 Doc Rev 1 10 angel_SWIreason_EnterSVC Enter SVC mode SWI SWI Angel Returns EnterUSR routine in rO MRC p15 0 r4 cl c0 0 read the control register BIC r4 r4 amp Enablelcache turn off Icache BIC r4 r4 EnableDcache turn off Dcache BIC 14 r4 EnableWB pl5 0 r4 cl c0 0 write the control register now back to user mode MOV sp v3 restore stack pointer LDMFD vl v3 lr restore registers now we must flush the icache we flush both because nothing of significance to the user has happened so far we want all data reads to show up and we just restored all the registers from the stack which may have been cached MOV 14 0 p185 0 14 c7 c7 0 LDR GPIODirect GPIO Direction Register LDR rl GPIOAItFunc GAFR GPIO Alternate Function Register LDR r2 RclkMask GPIO26 rclk Mask Bit We must set GPIO Direction and GPIO Alternate Function Registers Bit 26 on to enable OUT LDR 13 10 Get current contents 14 rl Getcurrent GAFR contents ORR 15 13 12 Set Bit 26 true 1 STR r5 10 Write to set Bit 26 as an Output ORR 15 14 2 Set Bit 26 true 1 STR r5 r1 Write GAFR Bit 26 for OUT We must also set Bit 31 of TUCR to output clock
31. ons that permit time to be displayed from different reference points System Trigger Cursor 1 Current Position and Cursor 2 Current Position Selecting the desired mode with the mouse and then clicking the left mouse button will make the selection the present Timestamp display mode e 815 we do Ea eden y 4 20 Delta Time 252ns Brutus Brutus Brutus 3 ample DRAMAddr Data Mnemonics Timestamp Addre 0 0080 4 E3A04000 MOV R4 00 gt gt 0 00080 VISEZ 41941016 P 0060 2 0080 1 01000 R1 FLUSH 251 000 ns 00080 3 59 1 LDR R12 R15 01 0 00008000 376 500 ns 00080 4 OOBDBO 89 0003 LDMIA R12 1 0 0000 124 502 500 ns 00080 5 OOBDDO 0000 124 DATA READ 628 500 ns OOOBD 6 0086084 11100 1 TSTS RO Ri R1 5 1 754 500 ns OOOBD 00 124 55555555 DATA READ 880 500 ns 000 1 8 0086068 1802060 MOVS R2 RO RO RRX 1 007 000 us OOOBD 9 00 128 55555555 DATA READ 1 133 000 us 000 1 10 OOBDBC EOA11001 ADC R1 R1 RI 1 259 500 us OOOBD 11 OOBDCO 0222600 EOR R2 R2 LSL 12 1 385 000 us OOOBD 12 OOBDC4 EO220A22 EOR RO R2 R2 LSR 20 1 511 000 us OOOBD 13 OOBDC8 8800003 STMIA R12 1 1 636 500 us OOOBD 14 OOBDCC 1 MOV R15 RO 14 1 762 000 us OOOBD 15 00
32. rgets The necessary clocking mode selections are made by moving to the System window clicking on Setup for the appropriate LA card then clicking on More a button to the right of the Clocking field Choose the desired mode in each Clocking Select field NOTE Depending upon the speed of the SA 1110 micro and the design of the target it may be necessary to adjust the Setup amp Hold times for some of the NEX SA1110 data groups to ensure proper data acquisition Please refer to Appendix C Clocking Considerations for further details 5 2 2 Clocking Options Explanation Clocking Mode This is set to Bus Cycle Clocking by default In this mode the software monitors the SDCLKO nRAS nCAS and nWE signals to permit the acquisition of valid SA 1110 bus cycles only Wait and Idle states will be ignored offering the best use of your acquisition memory Refer to Appendix C for more information on how bus cycle data is acquired Selecting Rising Edge of SDCLKO will acquire data on every rising edge of the SDCLKO signal The disassembly software will try to filter and display these cycles accordingly but incorrect decoding may occur because of the numerous duplicated cycles This clocking mode shows all bus cycles including any Wait or idle states Since no clocking qualification is done only SDCLKO signal is needed CAS Latency This field should be set to the proper value of the CAS latency for Read cycles Valid selections are 2 def
33. rketing and supporting Bus Analysis applications for Tektronix Logic Analyzers We can be reached at Nexus Technology Inc 78 Northeastern Blvd 2 Nashua 03062 877 595 8116 877 595 8118 Website http www nexustechnology com Support Contact Information Technical Support techsupport nexustechnology com General Information support nexustechnology com Quote Requests quotes nexustechnology com We will try to respond within one business day If Problems Are Found Document the problem and e mail the information to us If at all possible please forward a Saved System Setup with acquired data that shows the problem Do not send a text listing alone as that does not contain enough data for analysis To prevent corruption during the mailing process it is strongly suggested that the Setup be zipped before transmission SAIIXX MN XXX 36 Doc Rev 1 10 APPENDIX References Tektronix TLA600 700 System User s Manual Tektronix TLA600 700 Module User s Manual Tektronix P6434 Mass Termination Probe Instruction Manual Advanced RISC Machines Architectural Reference Manual Edited by Dave Jaggar Document Number ARM DD1 01008 ISBN 0 13 736299 4 Copyright Advanced RISC Machines Ltd ARM 1996 Prentice Hall New York NY Intel SA 1100 Microprocessor Technical Reference Manual September 1998 Order Number 278088 001 Intel SA 1110 Advanced Developer s Manual March 1999 SAIIXX MN XXX 37 Doc Rev 1
34. sing earlier versions of TLA software 54 1100 Eval Board Brutus Clocking Clocking Mode Bus Cycle Clocking Group Setup Hold Window Address Support Package Default DRAMAdd Support Package Default Data Control Support Package Default RASAddr Support Package Default Hep Figure 5 Setup amp Hold Adjustment The same concerns exist for the SA 1110 micro and designs using it The data groups that may need to be adjusted are the Address DRAMAddr Data and Control groups SAIIXX MN XXX Doc Rev 1 10 APPENDIX H StrongARM 1100 Pinout This table shows the pinouts for 208 pin Quad Flat Pack and 256 mini BGA packages Pat Pur Spa Pin n Signal Pin rin Signal Pin Pin Signal Pin Pin Signal RXD_C 25 nPIOR TXD C GP 24 nPIOW VDDX2 GP 23 VSSX VSSX GP 22 VDDX2 VDD VDDXI VSS VSS VSSX VDD 21 PSKTSEL 2181 GP 20 nlIOIS16 D 16 GP 19 nPWAIT D 24 GP 18 nPREG 17 2 0091 16 nPCE1 D 17 GP 15 nWE D 25 GP 14 nOE VDDX2 VDDXI VSSX VSSX VSSX VDDX2 D 2 GP 13 nRAS 3 D 10 GP 12 nRAS 2 D 18 GP 11 nRAS 1 D 26 GP 10 nRAS 0 D 3 GP 9 nCAS 3 D 11 GP 8 nCAS 2 D 19 GP 7 nCAS 1 D 27 GP 6 nCAS 0 VDD VDDXI VSSX VSS VSSX VDDX2 VDDX2 VDD VSS VSSX VSS VDD D 4 GP 5 nCS 3 D 12 GP 4 nCS 2 D 20 GP 3 nCS 1 D 28 GP 2 nCS 0 D 5 25 D 13 0 24 D 21 L_BIAS 23 nRESET
35. tivity Indicator window of TLA and observe that all of these signals are toggling When using the NEX SA1100 support in Every Edge of RCLK mode the only signal that is required is RCLK OUT and this signal must show activity in the Activity Indicator window of the TLA SAIIXX MN XXX 30 Doc Rev 1 10 APPENDIX SAMPLE SOURCE CODE As previously mentioned it is necessary to define the GP26 signal as an external clock source for micro data to be acquired synchronously by the Logic Analyzer It is also strongly recommended that both the instruction and data caches be disabled to permit the Analyzer to better track the flow of the codeand we have provided some examples to do this The code is available on the TLA s hard disk in one of the following folders depending upon which support was loaded C Program Files 700 Supports Brutus C Program Files TLA 700NSupports 1100 with the filename NewWavelnit s The code is also listed below turns on external disables both icache and dcache GPIODirect EQU 0x90040004 GPIOAItFunc EQU 0 9004001 RclkMask EQU 0x04000000 TUCRegister EQU 0 90030008 Bit31Mask EQU 0x80000000 EnableDcache EQU 0x4 EnableWB EQU 0x8 EQU 0 1000 FlushCacheOPC2 EQU 0x0 FlushCacheCRm EQU 0x7 SWI Angel EQU 0x123456 angel SWlIreason EnterSVC EQU 0x17 AREA Random codel CODE READONLY EXPORT NewWavelnit NewWavelnit STMFD vl v3
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