NAR-2090 User`s Manual
Contents
1. 1 LD8_RxF2P00 i LD8_RxF1_Bit 7 5 4 P 111 1 2 5 LD8 RxFO Bit 2 0 P 010 H LD8_RxF2P00 1 LD8_RxF1PF3 Hf 2 6 LD8_RxFO_Bit 2 0 P 011 1 LD8_RxF2P00 Hf LD8_RxF1_Bit 1 0 P 11 Hf 2 7 LD8 RxFO Bit 2 0 P 000 1 LD8_RxF2P00 Hf LD8_RxF1_Bit7P1 i GPIOBASE 00 Bit7PO Must be enabled and write 0 to the GPIO pin GPO17 1 Step3 R W GPIO data bits from GPIO data port BP WDT 5 0 GPO51 50 47 46 45 44 LOADJ GPO34 BY WDT CLEARJ GPO35 BY WDT DISABLE GPO41 BY WDT STATUS GPI42 BY MODE STATUS GPI43 SET TO NORMALT GPO37 SET TO BYPASSJ GPO40 SYSWDT 5 0 GPO15 14 13 12 11 10 SYSWDT CLEARJ GPO32 SYSWDT DISABLET GPO30 SYSWDT STATUS GPB1 lt lt How to access SuperIO configuration Register gt gt 1 config VT1211 Index Port to access superlO config register 002eh Enter VT1211 extended mode to access CR Configuartion Register I config VT1211 P87 ll config VT1211 P87 Exit VT1211 extended mode to access CR config VT1211 Paa Il lt lt lt lt lt How to Set to Normal Mode 55555 GPIOBASE 01 Bit7P1 Delay 15us GPIOBASE 01 _Bit7P0 Delay 15us GPIOBASE 01 Bit7P1 Delay 4 ms _ H L H pusle NAR 2090 User s Manual 26 For First High duration around 15us is enough For low duration2. GPIOBASE 02 Bit 11 lt lt lt lt lt How to Read BP WDT status 55555 Read BP WDT status bit Normal WDT not expired this bit returns 1 If BP WDT expires then this bit will be changed to 0 Once BP WDT expires this bit will keep 0 When a power off on or writing to WDT clear bit H L H pulse with 15us NAR 2090 User s Manual 27 then BP WDT will be set to 1 again BP_Group I H BP WDT status bit GPIOBASE 02 _Bit2 BP WDT clear bit GPIOBASE 01 BitS H L H pulse l SYSWDT programming guide is similar with BP WDT Enable Refresh SYSWDT Disable SYSWDT and read SYSWDT_SYS If SYSWDT expires then PPAP 2020 will be reset immediately 11 SYSWDT is implemented on ZR2 and later PCBA include stdlib h include conio h include stdio h include dos h for delayO and sleep0 pragma inline for inline asm Global constant Start define GPIOLX_OFFSET 0x00 The offset value from GPIOBASE define GPIO3X OFFSET 0x01 The offset value from GPIOBASE define GPIO4X_OFFSET 0x02 The offset value from GPIOBASE define GPIOSX_OFFSET 0x03 The offset value from GPIOBASE define GPIO6X_OFFSET 0x04 The offset v
3. after turning on or rebooting the computer press lt Del gt key immediately to enter BIOS setup program If you want to enter Setup but fail to respond before the message disappears please restart the system either by first turning it off and followed by turning it on COLD START or simply press the RESET button WARM START press lt Ctrl gt lt Alt gt and lt Delete gt keys simultaneously will do too Unless you press the keys at the right time the system will not boot an error message will display and you will be asked to do it again When no setting is stored in BIOS or the setting is missing a message Press lt F1 gt to run Setup will appear Then press lt F1 gt to run Setup or resume HIFLEX BIOS Setup You can use the keyboard to choose among options or modify the system parameters to match the options with your system The table shown on next page will show you all of keystroke functions in BIOS Setup NAR 2090 User s Manual 19 Keys to navigate within Setup menu Key Function Move to the previous item Move to the next item Move to the item on the left menu bar Move to the item on the right menu bar Enter the item you desired Increase the numeric value or make changes Decrease the numeric value or make changes Increase the numeric value or make changes Decrease the numeric value or make changes Main Menu Quit and not save changes into CMOS Status Page Setup Menu and Option Page Setu
4. al char inportb config_VT1211 1 10x20 outportb config VT1211 0x25 outportb co eek Rist nfig VT1211 1 al char define the Multiplexed pins end Select IO direction and Non inverse GPO17 34 35 37 40 41 44 45 46 47 50 51 GPI42 43 outportb config VT1211 0x07 outportb config VT1211 1 GPIO_LDN point to LDN of GPIO outportb config VT1211 0x30 al char inportb config VT1211 1 10x01 outportb config VT1211 0x30 outportb config VT1211 1 al char enable GPIO Get GPIOBASE High byte lt LD8 Rx60 Low byte lt LD8 Rx61 outportb config VT1211 0x60 E a _char inportb config VT1211 1 GPIOBASE al char GPIOBASE GPIOBASE lt lt 0x08 High byte of GPIOBASE outportb config VT1211 0x61 al char inportb config VT1211 1 Low byte of GPIOBASE GPIOBASE GPIOBASE al char Get the GPIOBASE init GPO34 35 37 direction and polarity outportb config VT1211 OxF0 Select GPIO port 3 al char inportb config VT1211 1 amp OxF9 I 0x01 Bit 2 1 0 P 001 outportb config VT1211 OxFO point to GPIO30 37 outportb config VT1211 1 al char outportb config VT1211 0xF2 Non inverse outportb config VT1211 1 0x00 outportb con fig VT1211 0xF1 Il al char inportb config VT1211 1 10xBO 1 output direc
5. printf n n This BP group test OK _ Will go on the test of next BP group n printf n n Toggle the BLACK switch then press any key to continue the test of next BP getcheQ P2020_GPIO_TESTO printf Win 2 RJ45 Twist pairs test OK _ Will go on the test of the rest 2 pairs n printf n n Toggle the Blue or Red switch then press any key to continue the test getcheQ P2020 GPIO TESTO printf min BYPASS EXTERNAL LOOPBACK TEST OKAY Press any key to return to main menu getche goto Main menu end of Selection C pp Main Menu Selection lt D gt I else if i 0x44 II G 0x64 printf n BP WDT status bit will be checked first printiCn Then BP WDT enabled and expired in 1 second printiCn Finally Reset the status bit to 1 n WDT_disableQ Get BP WDT status bit first GPI42 should be 1 al char inportb GPIOBASE GPIO4X OFFSET amp 0x04 if al char 0x04 goto go on test D NAR 2090 User s Manual 42 printf 1n Current BP_WDT status bit is WOW C i e BP_WDT has expired Y n printf n Continue the test VYV continue Others Quit and Return to DOS j getcheQ if j Y ll j y goto continue_the_test_D printf n n Error 03 BY WDT has expired before the test Quit and Return to DOS n n outportb config VT1211 0xaa exit config mode exit 1 continue_the_test_D Will reset BP_WDT to no
6. IO delay0 outportb GPIOBASE GPIO3X OFFSET al char PO low pulse fixdelay 15us0 al char inportb GPIOBASE GPIO3X OFFSET 1 0x20 NAR 2090 User s Manual 30 IO_delayO outportb GPIOBASE GPIO3X OFFSET al char P1 Second high pulse fixdelay 15us0 CLEARJ BP WDT STS HLHO void CLEARJ SYS WDT STS HLHO Global Variable GPIOBASE needs to be known first Global constant adopted Called function IO_delayQ fixdelay 15us0 unsigned char al_char II CLEAR H_L_H pulse al char inportb GPIOBASE GPIO3X OFFSET 0x04 GP32 CLEARJ IO_delayQ outportb GPIOBASE GPIO3X OFFSET al char P1 First high pulse fixdelay 15us0 al char inportb GPIOBASE GPIO3X OFFSET amp OxFB IO delay0 outportb GPIOBASE GPIO3X OFFSET al char PO low pulse fixdelay 15us0 al char inportb GPIOBASE GPIO3X OFFSET 0x04 IO_delayO outportb GPIOBASE GPIO3X OFFSET al char P1 Second high pulse fixdelay 15us0 CLEAR SYS WDT STS HLHO unsigned char WDT REFRESH 1K unsigned int ax twd unsigned int ax idle ms Global Variable GPIOBASE needs to be known first Global constant adopted Called function IO delay WDT disableQ fixdelay_15usO LOADJ_HLHO inline asm Retuned ESC return Ox1b Normal 1000 times refresh return 0x00 unsigned char al
7. Function 1 2 Short Normal Operation 2 3 Short Clear CMOS Contents J10 Reset to default function Function 1 2 Short RESET TO DEFAULT 1 2 Open Normal mode Connector Function Remark J1 J5 LAN LED J7 CPU FAN connector J8 IDE connector Jo 5V amp 12V power connector J10 RESET TO DEFAULT J13 SYS FAN connector J14 8 bit GPO LED connector J15 HDD LED Power LED J17 By pass LED J18 VGA connector J19 COM2 connector J21 J24 RJ45 connector J26 J27 USB connector J30 COM 1 connector J31 PICMG 1 0 connector NAR 2090 User s Manual 14 vm Pin Assignments of Connectors SW1 System reset Signal Description Signal Description PIN No Signal Description vme Sd HSYNC SPCLK NAR 2090 User s Manual 15 J21 J22 J23 J24 J25 Ethernet5 RJ 45 J19 Serial port 2x5 shrouded interface connector connector COM2 PIN No Signal Description PIN No Signal Description DCD Data carrier detect DSR Data set ready LAN_MDO LAN_MDO TC1 RXD Receive data RTS Request to send 102 TXD Transmit data LAN_MD1 CTS Clear to send LAN_MD1 DTR Data terminal ready NC 4 aT ACTIVER RI Ring indicator LINK GND Ground LINK100 NC Not connected 3 3V Ground Ground J8 IDE1 2x20 shrouded connector PIN No Signal Description PIN No Signal Description Reset IDE DRQO Ground Ground Host data 7 Host IOW
8. Hardware E Advanced Restore Defaults ceee NAR 2090 User s Manual 5 Turn on the power of NAR 2090 after following screen was shown port HyperTerminal BEE File Edit View Call Transfer Help Connected 0 00 15 Auto detect Auto detect SCA OLL CAPS NUM KA Captur Z 6 You can then see the boot up information of NAR 2090 When message Hit lt DEL gt if you want to run Setup appear during POST after turning on or rebooting the computer press lt Tab gt key immediately to enter BIOS setup program 7 This is the end of this section If the terminal did not port correctly please check the previous steps 2 14 BIOS Setup Information NAR 2090 is equipped with the Award BIOS within Flash ROM The BIOS has a built in setup program that allows users to modify the basic system configuration easily This type of information is stored in CMOS RAM so that it still retains during power off periods When system is turned on NAR 2090 communicates with peripheral devices and checks its hardware resources against the configuration information stored in the CMOS memory Whenever an error is detected or the CMOS parameters need to be initially defined the diagnostic program will prompt the user to enter the Setup program Some errors are significant enough to abort the start up zo Entering Setup When you see the message Hit lt DEL gt if you want to run Setup
9. Host data 15 Chip select 1 Ground Activity NAR 2090 User s Manual 16 J30 Serial port D SUB9 connector COM1 PIN No Signal Description Data Carrier Detect DCD Receive Data RXD Transmit Data TXD Data Terminal Ready DTR Ground GND Data Set Ready DSR Request to Send RTS Clear to Send CTS Ring Indicator RI J26 J27 Dual USB port connector Signal Description PIN No Signal Description Ground USBDO USBD1 USBD1 5V NAR 2090 User s Manual 17 2 13 Use a Client Computer es Connection Description New Connection Enter a name and choose an icon for the connection Connection Using Hyper Terminal If users use a headless NAR 2090 which has no mouse keyboard and VGA output connected to it the console may be used to communicate with NAR 2090 To access NAR 2090 via the console Hyper Terminal is one of the choices Follow the steps below for the setup Execute HyperTerminal under C Program Files Accessories HyperTerminal 2 Enter a name to create new dial ER D port Enter details for the phone number that you want to dial Country code Area code United States of America 1 y Phone number Connect using Direct to Com COM1 Properties Port Settings 3 For the connection settings make it Direct to COM1 Connect To 21 x Bits per second Data bits a Parity Stop bits H n Flow control
10. al char Set bypass0 if al char 0x00 goto next normal test auto printf n n Error 06 Set to Bypass test failed n outportb config VT1211 0xaa exit config mode exit 1 next_normal_test_auto WDT_disableQ delay 800 al char Set_normal if al char 0x00 goto next bypass test auto printf n n Error 07 Set to Normal test failed n outportb config VT1211 Oxaa exit config mode exit 1 next_bypass_test_auto WDT_disableQ delay 800 printf n n Start BP WDT refresh testing n Sub_menu_display 0x55 1 al_char WDT_REFRESH_1K 1 989 if al char 0x1b goto Main menu ESC return 3 WDT_REFRESH_1K 2 1978 if al char 0x1b goto Main menu ESC return E WDT REFRESH 1K 4 3956 if al char 0x1b goto Main menu ESC return a WDT_REFRESH_1K 8 7912 if al char Ox1b goto Main menu ESC return 7 WDT REFRESH 1K 14 13461 if al char 0x1b goto Main menu ESC return z WDT_REFRESH_1K 20 19231 if al char 0x1b goto Main menu ESC return WDT_REFRESH_1K 26 25000 if al char Ox1b goto Main menu ESC return WDT REFRESH 1K 30 28846 if al char 0x1b goto Main menu ESC return Sub menu display 0x55 9 al char WDT REFRESH 1K 34 32692 if al char 0x1b goto Main menu ESC return Su
11. pass if no failed SGPO61 Write O to SGPI6O SGPI60 0 if yes pass if no failed t4 SGPO53 Write 1 to SGPI52 SGPI52 1 if yes pass if no failed SGPO55 Write 1 to SGPI54 SGPI54 1 if yes pass if no failed SGPO57 Write 1 to SGPI56 SGPI56 1 if yes pass if no failed SGPO61 Write 1 to SGPI60 SGPI60 1 if yes pass if no failed GPIO Direction setting for tl and t2 test items outportb config VT1211 CRFO al char inportb config_VT1211 1 amp OxFB I 0x03 Bit 2 1 0 P 011 outportb config VT1211 CRFO point to GPIO50 57 outportb config VT1211 1 al char outportb config VT1211 CRF1 al char inportb config VT1211 1 amp 0x57 I 0x54 SGPO52 54 56 outportb config VT1211 CRF1 11 SGPI53 55 57 outportb config VT1211 1 al char outportb config VT1211 CRF2 Non Inversed GPIO CRF2P00 a outportb config_VT1211 1 Non_inversed_byte outportb config VT1211 CRFO al char inportb config_VT1211 1 amp OxFC I 0x04 Bit 2 1 0 P 100 outportb config VT1211 CRFO point to GPIO60 67 outportb config _VT1211 1 al char outportb config VT1211 CRF1 al char inportb config VT1211 1 amp OxFD I 0x01 SGPO60 outportb config VT1211 CRF1 SGPI61 outportb config _VT1211 1 al char outportb config VT12
12. 0x08 Check Bypass status GP43 if al 1 0x00 return 0x00 low 0 normal else return OxBB end of UC Set normal unsigned char Set bypass0 Global Variable GPIOBASE needs to be known first Global constant adopted Called function IO_delayQ fixdelay 15us0 test okay return 0x00 I Test failed return OxBB unsigned char al 2 al_2 inportb GPIOBASE GPIO4X OFFSET I 0x01 GP40 Set bypass IO_delayO outportb GPIOBASE GPIO4X OFFSET al 2 P1 First high pulse fixdelay 15us0 al 2 inportb GPIOBASE GPIO4X OFFSET amp OxFE IO_delayO outportb GPIOBASE GPIO4X_OFFSET al_2 PO low pulse fixdelay 15us0 1 2 inportb GPIOBASE GPIO4X OFFSET 1 0x01 O_delayQ outportb GPIOBASE GPIO4X OFFSET al 2 P1 Second high pulse delay 10 delay 10 ms p al_2 inportb GPIOBASE GPIO4X OFFSET amp 0x08 Check Bypass status GP43 if al 2 0x08 return 0x00 high 1 bypass else return OxBB end of UC Set bypass0 unsigned char Sub_menu_display unsigned char al_WDT_type char al_sel Global Variable struct t and d adopted al WDT type 0x55 gt BP WDT OxAA gt SYS WDT unsigned int i for i 0 i lt 26 i printf n NAR 2090 User s Manual 34 I system cls Need DOS system command com exist if al_WDT_type 0x55 printf n Refresh BP_W
13. 15us is enough For second High duration it needs at least 4 ms to operate the mechanical relay contacts lt lt lt lt lt How to Set to Bypass Mode gt gt gt gt gt GPIOBASE 02 Bit0P1 Delay 15us GPIOBASE 02 _BitOPO Delay 15us GPIOBASE 02 Bit0P1 Delay 4 ms _ H L H pusle For First High duration around 15us is enough For low duration 15us is enough For second High duration it needs at least 4 ms to release the mechanical relay contacts II lt lt lt lt lt How to Read BP mode 55555 Read BP status bit 0 gt Normal mode 1 gt Bypass mode GPIOBASE 02 _Bit3 Il lt lt lt lt lt How to Enable Refresh BP WDT gt gt gt gt gt Set Twd First GPIOBASE 03 Bit 1 0 gt BP WDT 5 4 GPIOBASE 02 Bit 7 4 gt BP WDT 3 0 BP WDT 5 0 000001b 111111b 1 63 seconds options available Delay 15us Make a H L H pulse for load signal GPIOBASE 01 Bit4P1 Delay 15us GPIOBASE 01 _Bit4P0 Delay 15us GPIOBASE 01 Bit4P1 Delay 15us H L H pusle For High duration around 15us is enough For low duration 15us is enough Il lt lt lt lt lt How to Disable BP WDT gt gt gt gt gt Make a H L H pulse with 15us width for disabling BP WDT
14. 2 20 Fig 2 21 Fix the Metal Spacers 14mm Fig 2 22 Fix the riser card bracket Fig 2 23 NAR 2090 User s Manual 9 2 10 Default Reset cable amp Status cable 1 insert HDD status cable 2 Insert Power status cable 3 insert Default Reset cable Fig 2 24 Pin header location Fig 2 25 Power LED and Default reset pin header NAR 2090 User s Manual 10 Model Main Processor BIOS Main Memory L2 Cache Memory Chipset SATA Interface PCI IDE Interface Serial Ports USB Interface Auxiliary I O Interfaces Power Input On board Ethernet Hardware Monitor Environmental Requirements Dimension 2 11 Product Specifications NAR 2090 VIA C7 processors FSB 400 533Mhz Award system BIOS with 512KB flash ROM to support DMI PnP APM function Up to 1024MB 1 8V DDR2 128KB 32 way built in C7 CPU module VIA 8237R Two SATA DMA133 Storage One 40 Pin for DMA 33 66 100 IDE Storage Support two high speed 16550 compatible UARTs with 16 byte T R FIFOs Support two USB2 0 ports for high speed I O peripheral devices System reset switch power okay LED Ethernet activity LED Ethernet speed LED general purpose LED alert LED and HDD LED interface Support one AC Adaptor with Adaptor input power requirement Input 100 240V Output 15V 4A Five RealTek 8100C 10BASE T 100BASE TX Fast Ethernet controller with RJ 45 interface Five Rea
15. 2 3 The Chassis The system is integrated in a customized chassis Fig 2 1 Fig 2 2 On the front panel you will find the Power LED Hard Disk LED and LAN LED The back panel has Five LAN ports and a COM port Fig 2 1 Front view of the Chassis Fig 2 2 Back view of the Chassis Fo 24 OpentheChassis 1 Take off the four screws three at the rear side and two at the right left side and remove the top lead Fig 2 3 Fig 2 3 Take off two screws 2 The top lead Fig 2 4 can be removed from the base stand Fig 2 5 Fig 2 4 The top lead Fig 2 5 The base stand 2 5 Install or Remove a SODIMM Follow these steps to upgrade or remove RAM module NAR 2090 User s Manual 1 Install the system memory by pulling the socket s arm and pressing it into the slot gently Fig 2 6 2 7 Fig 2 6 The memory slot Fig 2 7 Install SODIMM 2 By pulling the arms the SODIMM can eject itself Fig 2 8 Fig 2 8 Eject a SODIMM module NAR 2090 User s Manual 5 2 6 Remove and Install Battery 1 Press the metal clip back to eject the button battery Fig 2 9 2 Replace it with a new one by pressing the battery with fingertip to restore the battery Fig 2 10 EN Ms Fig 2 9 Eject the battery Fig 2 10 Restore the battery 2 7 Install Compact Flash The system has an internal drive bay for one Compact Fla
16. al WDT type 0x55 printf n n Your choice for BY WDT refresh test lt _ gt b b else printf nin Your choice for SYS WDT refresh test lt _ gt b b return 0x00 all display 1 if al WDT type 0x55 printf n n Auto testing BP WDT Current choice lt c gt n n al sel else printf n n Auto testing SYS_WDT Current choice lt c gt n n al sel return 0x01 end of Sub_menu_display c al_sel ass void P2020_GPIO_TESTO unsigned char al char al charl Test ing way Use PPAP 2020 ZR2 GPIO 8 bi direction pins from Super IO VT1211 Initialization for VT1211 must be done first in MainQ tl SGPO52 Write O to SGPIS3 SGPI53 0 if yes pass if no failed SGPO54 Write O to SGPI55 SGPI55 O if yes pass if no failed SGPO56 Write 0 to SGPIS7 SGPIS7 0 if yes pass if no failed SGPO60 Write O to SGPI61 SGPI61 0 if yes pass if no failed 12 SGPO52 Write 1 to SGPIS3 SGPI53 1 if yes pass if no failed SGPO54 Write 1 to SGPISS SGPIS5 1 if yes pass if no failed SGPO56 Write 1 to SGPIS7 SGPIS7 1 if yes pass if no failed SGPO60 Write 1 to SGPI61 SGPI61 1 if yes pass if no failed t3 SGPO53 Write O to SGPI52 SGPI52 0 if yes pass if no failed SGPO55 Write O to SGPIS4 SGPI54 O if yes pass if no failed NAR 2090 User s Manual 35 SGPO57 Write O to SGPI56 SGPI56 0 if yes
17. chips It contains VIA CN700 and VIA VT823R to support VIA C7 processor DDR2 SODIMM USB 2 0 port communication Ultra DMA 100 IDE Master and SATA storage The on board super VIA VT8237R supports two UARTs and hardware monitoring PPAP 2020 has built in onboard VIA C7 processor EBGA package Eden C7 533 or 400MHz system bus for cost effective and high performance application The VIA CN700 provides a completely integrated solution for the system controller and data path components in a VIA processor system It provides optimized 64 bit DDR2 interface The VIA VT8237R provides a highly integrated multifunction for the best industry applications It supports up to for Ultra ATA 33 66 100 IDE master interface Universal Serial Bus USB2 0 controllers Full duplex high performance 150MB s Dual Channel SATA interface NAR 2090 User s Manual 52 All detailed operating relations are shown in Fig 3 2 PPAP 2020 System Block Diagram VIA EDEN CPU ESP 3000 4000 5000 6000 VIA C3 733 800 10 VIA CLE266 A J VT8623 f MINI DDR DIMM MINI PCI SLOT PCI SLOT ADERI r Y 15 Jl Jl 1 na ma J 4 gt T Y Primary Sounth Bridge f ONE 44 PHAR nh A L ren Connect VT8235 Secondary Realtek Realtek basaan Reaktek DET CF sto een chee a 7 8100C 8100 832 8100c 8100 832 8100C18100 532 8100C 8100 S3 SAM CF walectable LPC VO LPC INTERFACE WINBOND USB 2 0 mn Ph ee X2 r IE 1 Jl paz
18. inportb GPIOBASE GPIO4X OFFSET 1 0x02 IO delay0 outportb GPIOBASE GPIO4X OFFSET al 3 P1 Second high pulse fixdelay 15us0 end of WDT_disableQ void SYSWDT_disableQ Global Variable GPIOBASE needs to be known first Global constant adopted Called function IO_delayQ fixdelay 15us0 unsigned char al 3 al_3 inportb GPIOBASE GPIO3X_OFFSET 10x01 GP30 WDT disable IO delay0 outportb GPIOBASE GPIO3X OFFSET al 3 P1 First high pulse fixdelay 15us0 al 3 inportb GPIOBASE GPIO3X OFFSET amp OxFE IO_delayO outportb GPIOBASE GPIO3X_OFFSET al_3 PO low pulse fixdelay_15usQ al 3 inportb GPIOBASE GPIO3X_OFFSET I 0x01 IO delay0 outportb GPIOBASE GPIO3X OFFSET al 3 P1 Second high pulse fixdelay 15us0 end of SYSWDT disable void LOADJ_HLHO Global Variable GPIOBASE needs to be known first Global constant adopted NAR 2090 User s Manual 29 Called function IO_delayQ fixdelay 15us0 unsigned char al_char LOADJ H_L_H pulse al char inportb GPIOBASE GPIO3X_OFFSET I 0x10 GP34 LOAD IO_delayQ outportb GPIOBASE GPIO3X OFFSET al char P1 First high pulse fixdelay 15us0 al char inportb GPIOBASE GPIO3X OFFSET amp OxEF IO_delayO outportb GPIOBASE GPIO3X OFFSET al char PO low pulse fixdelay_15
19. lt Enter gt to certify it Follow command keys in CMOS Setup table to change Date Time Drive type and Boot Sector Virus Protection Status Screen Shot Phoenix Award BIOS CMOS Setup Utility Standard CMOS Setup Utility Date mm dd yy Wed Jan 05 2005 Time hh mm ss 16 51 13 IDE Primary Master None IDE Primary Slave None IDE Secondary Master None IDE Secondary Slave None Video EGA VGA Base Memory 640K Extended Memory 95232K Total Memory 96256K ESC Quit 1 gt Select Item F1 Help Shift F2 Change Color PU PD Modify NAR 2090 User s Manual 21 Menu Selections Options Description me automatically changes when you set the date EGA VGA CGA 40CGA 80MONO Select the default video device Display the amount of conventional memory detected during boot up Display the amount of extended memory detected during boot up Display the total memory available in the system Yh Advance BIOS Features This section allows user to configure your system for basic operation Users will be able to select the system s default speed boot up sequence keyboard operation shadowing and security Screen Shot Phoenix Award BIOS CMOS Setup Utility Advanced BIOS Features ESC Quit TILE gt Select Item F1 Help Shift F2 Color F5 Old Values F6 Load BIOS Default F7 Load Setup Default PU PD Modify Un Internal Cache External Cache These two categories speed up
20. memory access However it depends on CPU chipset design NAR 2090 User s Manual 22 R J I op Enabled Enable cache Disabled Disable cache Quick Power On Self Test This category speeds up Power On Self Test POST after you power up the computer If it is set to Enable BIOS will shorten or skip some check items during POST Enabled Enable quick POST Disabled Normal POST Boot Up NumLock Status Select power on state for NumLock The choice Enabled Disabled Gate A20 Option This entry allows user to select how the gate A20 is handled The gate A20 is a device used to address memory over 1 Mbytes Originally the gate A20 was handled via a pin on the keyboard But now though keyboards still provide this support it is more common and much faster for the system chipset to provide support for gate A20 Typematic Rate Setting Keystrokes repeat at a rate determined by the keyboard controller When enabled the typematic rate and typematic delay can be selected The choice Enabled Disabled Typematic Rate Chars Sec Set the how many number of times a second to repeat a keystroke when a key is holding down The choice 6 8 10 12 15 20 24 and 30 Typematic Delay Msec NAR 2090 User s Manual 23 Set the delay time after the key is held down before it begins to repeat the keystroke The choice 250 500 750 and 1000 ny Security Option Select whether the password is required every
21. outportb GPIOBASE GPIOSX OFFSET al char al char inportb GPIOBASE GPIO6X OFFSET 0x02 SGPO61P 1 IO delay outportb GPIOBASE GPIO6X OFFSET al char fixdelay_15us0 al char inportb GPIOBASE GPIO5X OFFSET amp 0x54 Mask SGPI52 54 56 al charl inportb GPIOBASE GPIO6X OFFSET amp 0x01 Mask SGPI60 al char al char al charl if al char 0x55 goto gpio done al charl 0x04 Test4 failed gpio_test_failed outportb config VT1211 0xaa exit config mode printf n n Error 0C PPAP 2020 GPIO test failed for External loopback t X gt 0x X n al charl al char exit gpio done end of P2020 GPIO TESTO Ip e MAIN Program po unsigned char main 0 unsigned int i j k unsigned char al_char j First define the Multiplexed pins start outportb config VT1211 0x87 enter config mode outportb config VT1211 0x87 fixdelay 15us0 CR24Bit7 P1 Define the multiplexed pin pin121 as GPIO17 CR24_PFF Define the multiplexed pin pin121 as GPIO17 10 outportb config VT1211 0x24 al char inportb config_VT1211 1 1 0x80 al char inportb config VT1211 1 OxFF NAR 2090 User s Manual 38 outportb config VT1211 0x24 outportb config VT1211 1 al char CR23Bit5 PI Define the multiplexed pins pin66 97 as GPIO pins outportb config VT1211 0x25
22. time the system boots or only when you enter setup The system will not boot and access to Setup will be denied if the correct password is not entered at the prompt The system will boot and access to Setup will be denied if the correct password is not entered at the prompt Note To disable security select PASSWORD SETTING at Main Menu and then user will be asked to enter password Do not type anything and simply press lt Enter gt it will disable security Once the security is disabled the system will boot up and user can enter Setup freely Yi OS Select for DRAM gt 64MB Select the operating system that is running with more than 64MB of RAM on the system The choice Non OS2 OS2 Console Redirection Set the UNIX Console redirect to the terminal from COM1 The choice Enabled Disabled Um Baud Rate Set the RS 232 baud rate speed The choice 9600 19200 38400 57600 and 115200 Advanced Chipset Features This section allows user to configure your system for AT clock DRAM timings NAR 2090 User s Manual 24 Integrated Peripherals Yi Onboard LAN BootROM This function decide whether invoke the boot ROM of the onboard Realtek LAN chip Disable Disabled this function Default value Enable Enabled this function Default value 2 15 Reset to Default Sample Code information Portwell Confidential Portwell Intellectual Property All rights reserved I First release 07 2
23. 0 P 011 outportb config VT1211 CRFO II point to GPIO50 57 outportb config _VT1211 1 al char outportb config VT1211 CRF1 al char inportb config VT1211 1 amp OxAB I OxA8 SGPI52 54 56 outportb config _VT1211 CRF1 11 SGPO53 55 57 outportb config VT1211 1 al char outportb config VT1211 CRFO al char inportb config VT1211 1 amp OxFC I 0x04 Bit 2 1 0 P 100 outportb config VT1211 CRFO point to GPIO60 67 outportb config _VT1211 1 al char outportb config VT1211 CRF1 al char inportb config VT1211 1 amp OxFE I 0x02 SGPI60 outportb config VT1211 CRF1 SGPO61 outportb config _VT1211 1 al char al char inportb GPIOBASE GPIOSX OFFSET amp 0x57 SGPO53 55 57 P 000 IO delay0 outportb GPIOBASE GPIOSX OFFSET al char al char inportb GPIOBASE GPIO6X_OFFSET amp OxFD SGPO61P 0 IO delay outportb GPIOBASE GPIO6X OFFSET al char fixdelay_15us0 al char inportb GPIOBASE GPIOSX OFFSET amp 0x54 Mask SGPI52 54 56 al charl inportb GPIOBASE GPIO6X OFFSET amp 0x01 Mask SGPI60 al char al char al charl if al char 0x00 goto gp ok 3 al char 0x03 goto gpio_test_failed NAR 2090 User s Manual 37 gp ok 3 al char inportb GPIOBASE GPIOSX OFFSET 1 0xA8 SGPO53 55 57 P 111 IO delay0
24. 000 TIMES DISABLE SYS WDT n printf lt F gt Enable SYS WDT VW This will reset system after 1 second n printf lt G gt SYS WDT AUTO Refresh TEST VX Run all sub items in lt E gt Wa printf lt 3 gt EXIT Ao printf Your choice lt _ gt b b i getcheQ printf gt n 11 Main Menu Selection lt 3 gt if i 0x33 printf n n Test Item lt 3 gt Return to DOS Mn outportb config VT1211 0xaa exit config mode exit 0 11 Main Menu Selection lt B gt else if G 0x42 Il G 0x62 al char Set bypass0 if al_char 0x00 goto next_return_to_dos printf n n Error 02 V Set to Bypass test failed n outportb config VT1211 0xaa exit config mode NAR 2090 User s Manual 41 exit 1 next return to dos printf min Test Item lt B gt Return to DOS n outportb config VT1211 0xaa exit config mode exit 0 end of selection B I Main Menu Selection lt C gt pp RUN BP EXT LOOPBACK by connecting P2020 ZR2 GPIO amp an ext test fixture else if G 0x43 II G 0x63 VT1211 Super IO GP52 57 60 61 are used for PPAP 2020 GPIO Set bypass0 P2020 GPIO TESTQ printf min 2 RJ45 Twist pairs test OK _ Will go on the test of the rest 2 pairs n printf n n Toggle the Blue or Red switch then press any key to continue the test getcheQ P2020_GPIO_TESTO
25. 11 CRF2 Non Inversed GPIO CRF2P00 outportb config VT1211 1 Non inversed byte al char inportb GPIOBASE GPIOSX OFFSET amp OxAB SGPO52 54 56 P 000 IO delay0 outportb GPIOBASE GPIOSX OFFSET al char al char inportb GPIOBASE GPIO6X OFFSET amp OxFE SGPO60P 0 IO delay0 outportb GPIOBASE GPIO6X OFFSET al char fixdelay 15us0 al char inportb GPIOBASE GPIOSX OFFSET amp OxA8 Mask SGPI53 55 57 al charl inportb GPIOBASE GPIO6X OFFSET amp 0x02 Mask SGPI61 al char al char al charl if al char 0x00 goto gp ok 1 al char 0x01 goto gpio_test_failed al char inportb GPIOBASE GPIOSX OFFSET I 0x54 SGPO52 54 56 P 111 NAR 2090 User s Manual 36 1O_delayQ outportb GPIOBASE GPIOSX OFFSET al_char al char inportb GPIOBASE GPIO6X OFFSET I 0x01 SGPO60P 1 1O_delayQ outportb GPIOBASE GPIO6X_OFFSET al_char fixdelay 15us0 al char inportb GPIOBASE GPIOSX OFFSET amp OxA8 Mask SGPI53 55 57 al charl inportb GPIOBASE GPIO6X OFFSET amp 0x02 Mask SGPI61 al char al char al charl if al char 0xAA goto gp ok 2 al charl 0x02 goto gpio_test_failed GPIO Direction setting for t3 and t4 test items gp ok 2 outportb config _VT1211 CRFO al char inportb config_VT1211 1 amp OxFB I 0x03 Bit 2 1
26. 4 al 5 unsigned int i j al 4 ax twd Truncate high word Twd load into WDT 5 0 GP51 50 47 46 45 44 first al 5 inportb GPIOBASE GPIOSX OFFSET amp OxFC al 5 al 51 al4554 IO delay0 outportb GPIOBASE GPIOSX_OFFSET al 5 write GP51 50 al 5 inportb GPIOBASE GPIO4X_OFFSET amp OxOF al_5 al_5 al4 lt lt 4 IO_delayO outportb GPIOBASE GPIO4X_OFFSET al_5 write GP47 46 45 44 for 1 1 1 lt 1000 1 LOADJ HLHO fort j 1 j lt 80 j printf b printf Enable or Refresh BP WDT d times at i Get time and Date gettime amp t printf 02d 02d 02d 02d t ti hour t ti min t ti sec t ti hund NAR 2090 User s Manual 31 getdate amp d printf d d d Refreshing d da mon d da day d da year for j 1 j lt 80 printf b if i 1 delay 6 else fixdelay 15us0 if ax_idle_ms 1 delay ax_idle_ms else if i 1 delay ax_idle_ms 6 else delay ax_idle_ms al 5 inportb GPIOBASE GPIO4X OFESET amp 0x08 Check Bypass status GP43 if al 5 0x00 goto okay loop low 0 normal else printiCnin Error 01 Refresh BP_WDT 1000 times gt Failed Check CPLD or H W Circuit Na outportb config VT1211 0xaa exit config mode exit 1 okay_loop asm movah 6 check Esc key pressed asm mov dl 0ffh asm int2lh Call DOS function call as
27. 5 2006 2020BP00 EXE for ZR1 PCBA By Frank Hsu Second release 09 08 2006 2020BP01 EXE for ZR2 and later PCBA Modified by Frank Hsu Add SYSWDT support SYSWDT has the similar programming algorithm with BP WDT TAT Program 2020BP01 CPP I Descript BY PASS test program for PPAP 2020 Designer Frank Hsu Language Borland C 5 02 I OS MS DOS Win98 only Upddate 09082006 Release TAT Programming guide Step Define the GPIO pins for Bypass features 1 1 SIOCFG Rx24 bit7P1 1 2 SIOCFG Rx25 bitSP1 1 Step2 Point to Logic Device LD number8 for GPIO and init these GPIO pins LD8 RxFO Port Selection Bit 2 0 000 gt Portl GP10 17 001 gt Port3 GP30 37 010 gt Port4 GP40 47 011 gt Port5 GP50 57 100 gt Port6 GP60 67 LD8_RxFl Pin direction l output O input LD9_RxF2 Pin Polarity O Normal not inverted 1 inverted 2 1 SIOCFG_Rx07P08 2 2 LD8 Rx30 Bit0P1 2 3 Get GPIOBASE GPIOBASE is composed from LD8_Rx60 High byte and _Rx61 Low byte Address Offset 00 from GPIOBASE is for GPIO port pins NAR 2090 User s Manual 25 rama Address Offset 01 from GPIOBASE is for GPIO port3 pins Address Offset 02 from GPIOBASE is for GPIO port4 pins Address Offset 03 from GPIOBASE is for GPIO port5 pins 2 4 LD8_RxFO_Bit 2 0 P 001
28. DT 1000 times seconds seconds gt Twd Refresh interval n else printf n Refresh SYS WDT 1000 times seconds seconds gt Twd Refresh interval n printf n lt 1 gt 1 second 0 989 second lt A gt 38 seconds 36 538 seconds printf n lt 2 gt 2 seconds 1 978 seconds lt B gt 42 seconds 40 385 seconds printf n lt 3 gt 4 seconds 3 956 seconds lt C gt 46 seconds 44 231 seconds printf n lt 4 gt 8 seconds 7 912 seconds xD gt 50 seconds 48 077 seconds printf In lt 5 gt 14 seconds 13 461 seconds lt E gt 54 seconds 51 923 seconds printf n lt 6 gt 20 seconds 19 231 seconds lt F gt 56 seconds 53 846 seconds printf n lt 7 gt 26 seconds 25 000 seconds lt G gt 58 seconds 55 769 seconds printf n lt 8 gt 30 seconds 28 846 seconds lt H gt 60 seconds 57 692 seconds printf n lt 9 gt 34 seconds 32 692 seconds lt I gt 62 seconds 59 615 seconds printf nn lt Q gt RETURN TO MAIN MENU Ts Get time and Date gettime amp t printf 2d 02d 02d 02d t ti hour t ti min t ti sec t ti hund getdate amp d printf d d d n d da_mon d da day d da year printf n lt lt lt lt lt lt OTHER CHOICE WILL NOT DELAY gt gt gt gt gt gt n printf n PRESS Esc KEY TO STOP REFRESHING BP WDT DISABLE BP_WDT n if al sel K goto all display 1 if
29. E GPIO3X OFFSET amp 0x01 Check Bypass status GP31 if al 5 0x01 goto SYSWDT okay loop High 1 normal else printf win Error 0B Refresh WDT 1000 times gt Failed Check CPLD or H W Circuit n outportb config VT1211 0xaa exit config mode exit 1 SYSWDT_okay_loop asm mov ah 6 check Esc key pressed asm mov dl Offh asm int2lh Call DOS function call asm cmp al lbh asm je SYSWDT_esc_return if Esc pressed goto esc return for i loop SYSWDT_disable return 0x00 SYSWDT esc return SYSWDT_disableQ return Ox1b end of uc WDT RFSH 1K ui ui unsigned char Set normal0 Global Variable GPIOBASE needs to be known first Global constant adopted Called function IO_delayQ fixdelay 15us0 test okay return 0x00 I Test failed return OxBB unsigned char al 1 al 1 inportb GPIOBASE GPIO3X OFFSET 0x80 GP37 Set normal NAR 2090 User s Manual 33 1O_delayQ outportb GPIOBASE GPIO3X_OFFSET al 1 P1 First high pulse fixdelay_15usQ al 1 inportb GPIOBASE GPIO3X OFFSET amp Ox7F IO delay outportb GPIOBASE GPIO3X OFFSET al 1 PO low pulse fixdelay_15us0 al I inportb GPIOBASE GPIO3X OFFSET 10x80 IO_delayO outportb GPIOBASE GPIO3X OFFSET al 1 PI Second high pulse delay 10 delay 10 ms al 1 inportb GPIOBASE GPIO4X OFFSET amp
30. NAR 2090 Series Communications Appliance User s Manual Revision 01 0 Portwell Inc 3F No 92 Sec 1 Nei Hu Rd Taipei 114 Taiwan R O C an Headquarter 886 2 2799 2020 FAX 886 2 2799 1010 Cosme http www portwell com tw EMAIL ISO 9001 INFO MAIL PORTWELL COM TW Table of Contents Ghapter1 Introduclon aaa ni GARA 2 1 1 About TINS Manta Goch a a oa na AE 2 1 2 Manual Organization ana NBA nba eons aminan ied acd eee aa 2 1 3 Technical Support IRONMAN Orcadas o pa iden 2 Chapter 2 Get Started isis 3 2 1 Included FANT a A AA A AAA 3 2 2 Before YOU BEGNA TS 3 2 3 THE CNASSIS a A PAA PN RAAT 4 2 4 Open GSE Ne 4 2 5 install or Remove a SODIMM surnet A A A B onsa 4 27 EGON PSN AGS 6 2 8 naako NATAL ee 7 29 Add neser card MO Systemi merienenn nii iiair portene 9 2 10 Default Reset cable amp Status Caba naaa ta A aga 10 219 Product Specifications AKA KA ARA BAN BAKE 11 2 12 Hardware Configuration Sean aata pinka la ti 12 213 Use BN AA PA HAN ERA 18 2 15 Reset to Default Sample Code informati0N ooooooccccinnnccnnnnnnccnnconanccnnnnnarccnnnnnrrcn nn nn nnrc nn nan nn 25 Chapter 3 Operation GUIAE worm anses 51 aa Be Guide OF PPAP 2020 senka ET 51 e ARPA oteren eu se tore eiieeii 52 NAR 2090 User s Manual 1 Chapter 1 Introduction 1 1 About This Manual This manual describes all required information for setting up and using the NAR 2090 All mentioned below applies to the whole system unless speci
31. T amp OxC1 I 0x41 IO_delayO outportb GPIOBASE GPIO1X OFFSET al char write GP15 10 SYSWDT_LOADJ_HLHO II LOADJ_HLHO for testing only printf win This test will reset system after 1 second 1n otherwise test failed sleep 3 printf n n ERRORWA Test failed of system WDT enabling n outportb config_VT1211 Oxaa exit config mode exit 1 end of ifG f Main Menu Selection lt G gt else if 1 G Il i g AUTO test system WDT CLEARJ_SYS_WDT_STS_HLHO NAR 2090 User s Manual 48 printf mn Start SYS WDT refresh testing n Sub menu display OxAA 1 al_char WDT_RFSH_1K 1 989 if al char 0x1b goto Main menu ESC return Sub menu display OxAA 2 al char WDT RFSH 1K 2 1978 if al char 0x1b goto Main menu ESC return Sub menu display OxAA 3 al char WDT RFSH 1K 4 3956 if al char 0x1b goto Main menu ESC return Sub menu display OxAA 4 al char WDT RFSH 1K 8 7912 if al char 0x1b goto Main menu ESC return Sub menu display OxAA 5 al char WDT_RFSH_1K 14 13461 if al char 0x1b goto Main menu ESC return Sub menu display OxAA 6 al char WDT_RFSH_1K 20 19231 if al char 0x1b goto Main menu ESC return Sub menu display OxAA 7 al char WDT RFSH 1K 26 25000 if al char 0x1b goto Main menu ESC return Sub m
32. ally stated NAR 2090 provides the essential components for delivering optimal performance and functionality in the value communications appliance market segment This manual should familiarize you with NAR 2090 operations and functions NAR 2090 family has one two or five on board Ethernet ports to serve communication appliances such as Firewall which needs more Ethernet ports to connect external network internet demilitarized zone and internal network NAR 2090 features Versatile networking and I O capabilities 1 4 or 5 Ethernet ports One COM ports One miniPCI slot Onboard 256MB RAM Up to 512 Mbytes or 1Gbytes of DDR2 memory 1 2 Manual Organization The manual describes how to configure your NAR 2090 system to meet various operating requirements It is divided into three chapters with each chapter addressing a basic concept and operation of this whole system Chapter 1 Introduction This section briefly talks about how this document is organized It includes some guidelines for users who do not want to read through everything but still helps you find what you need Chapter 2 Hardware Configuration Setting and Installation This chapter shows how the hardware is put together including detailed information It shows the definitions and locations of Jumpers and Connectors that you can easily configure your system Descriptions on how to properly mount the main memory are also included to help you get a safe installatio
33. alue from GPIOBASE define config VT1211 0x2E Hardware strapping define GPIO LDN 0x08 GPIO LDN 0x08 define portb 0x61 define refresh status Ox10 define CRFO OxFO define CRF1 OxF1 define CRP2 OxF2 define Non inversed byte 0x00 8 GPIO pins not inversed Global constant End Global Variable Start unsigned int GPIOBASE struct time t struct date d char VER DATE 2020BP00 exe V1 00 07 25 2006 First release char VER DATE 2020BP01 exe V1 00 09 08 2006 Second release Global Variable end void IO_delayQ nportb 0x80 inportb 0x80 m void fixdelay 15us 0 NAR 2090 User s Manual 28 delay 15 us unsigned char char_ah char_al char_ah inportb portb amp refresh_status fixdelay_loop char al inportb portb amp refresh status if char ah char al goto fixdelay loop end of fixdelay 15us void WDT_disableQ Global Variable GPIOBASE needs to be known first Global constant adopted Called function IO_delayQ fixdelay 15us0 unsigned char al 3 al_3 inportb GPIOBASE GPIO4X_OFFSET 1 0x02 GP41 WDT_disable IO delay0 outportb GPIOBASE GPIO4X OFFSET al 3 P1 First high pulse fixdelay 15us0 al 3 inportb GPIOBASE GPIO4X OFFSET amp OxFD IO_delayO outportb GPIOBASE GPIO4X_OFFSET al_3 PO low pulse fixdelay 15us0 al 3
34. b menu display 0x55 a al char WDT REFRESH 1K 8 36533 if al char 0x1b goto Main menu ESC return Sub menu display 0x55 b al char WDT REFRESH 1K 42 40385 if al char 0x1b goto Main menu ESC return NAR 2090 User s Manual 44 Sub_menu_display 0x55 c al_char WDT_REFRESH_1K 46 44231 if al char 0x1b goto Main menu ESC return Sub menu display 0x55 d WDT REFRESH 1K 50 48077 char 0x1b goto Main menu ESC return Sub menu display 0x55 e WDT REFRESH 1K 54 51923 if al char 0x1b goto Main menu ESC return Sub menu display 0x55 f WDT REFRESH 1K 56 53846 if al char Ox1b goto Main menu ESC return Sub menu display 0x55 g al char WDT REFRESH 1K 58 55769 har 0x1b goto Main menu ESC return an a AS TE o cl if ali Sub menu display 0x55 h al char WDT REFRESH 1K 60 57692 if al char 0x1b goto Main menu ESC return Sub menu display 0x55 1 WDT REFRESH 1K 62 59615 if al char Ox1b goto Main menu ESC return Q printf n in BP WDT AUTO TEST gt PASS _ Press any key to continue getche goto Main_menu Main Menu Selection lt 1 gt I else if i 0x31 retrigger 100 times Sub_Menu Sub men
35. eak case 0x42 al char WDT RESH 1K 42 40385 break case 0x62 al_char WDT RESH 1K 42 40385 break case 0x43 al char WDT_RFSH_1K 46 44231 break case 0x63 al char WDT_RFSH_1K 46 44231 break case 0x44 al char WDT RFSH 1K 50 48077 break case 0x64 al char WDT_RFSH_1K 50 48077 break case 0x45 al_char WDT_RFSH_1K 54 51923 break case 0x65 al char WDT_RFSH_1K 54 51923 break case 0x46 al_char WDT_RFSH_1K 56 53846 break case 0x66 al char WDT_RFSH_1K 56 53846 break case 0x47 al char WDT_RFSH_1K 58 55769 break NAR 2090 User s Manual 47 case 0x67 al char WDT_RFSH_1K 58 55769 break case 0x48 al char WDT_RFSH_1K 60 57692 break case 0x68 al char WDT RFSH 1K 60 57692 break case 0x49 al_char WDT_RFSH_1K 62 59615 break case 0x69 al_char WDT_RFSH_1K 62 59615 break default al_char WDT RESH IK 1 1 break end of switch if al char Ox1b goto Main menu ESC return VY printf n n Refresh SYS WDT 1000 times gt PASS Press any key to do more tests getcheQ goto SYSWDT_Sub_Menu end of if G e Main Menu Selection lt F gt else if 1 F Il i f Enable System WDT and Let WDT expire will reset system System WDT Twd load into SWDT 5 0 GP15 10 first al char inportb GPIOBASE GPIO1X OFFSE
36. enu display OxAA 8 WDT RFSH 1K 30 28846 if al char 0x1b goto Main menu ESC return Sub menu display OxAA 9 WDT RFSH 1K 34 32692 if al char 0x1b goto Main menu ESC return Sub menu display OxAA a WDT RFSH 1K 38 36538 if al char 0x1b goto Main menu ESC return Sub menu display OxAA b WDT RFSH 1K 42 40385 if al char 0x1b goto Main menu ESC return Sub menu display OxAA c WDT_RFSH_1K 46 44231 if al char 0x1b goto Main menu ESC return Sub menu display OxAA d WDT RESH 1K 50 48077 if al char 0x1b goto Main menu ESC return Sub menu display OxAA e WDT RFSH 1K 54 51923 if al char 0x1b goto Main menu ESC return Sub menu display OxAA f WDT RESH 1K 56 53846 if al char Ox1b goto Main menu ESC return Sub menu display OxAA g al char WDT RFSH 1K 58 55769 if al char 0x1b goto Main menu ESC return Sub menu display OxAA h al char WDT RFSH 1K 60 57692 if al char 0x1b goto Main menu ESC return Sub menu display OxAA 15 al char WDT RFSH 1K 62 59615 if al char 0x1b goto Main menu ESC return E lo Il E 8 Wy o ll o ll ne pr
37. gement policies can be applied respectively to individual network to achieve the highest security level The target market segment is communication appliance including Virtual Private Network Load Balancing Quality of Service Intrusion Detection Virus Detection Firewall and Voice Over IP This PPAP 2020 system board is eligible with VIA Eden processor EBGA package Eden Esp8000 and On board 256Mb or higher DDRAM The enhanced on board PCI IDE interface supports 1 drive up to PIO mode 4 timing and Ultra DMA 100 synchronous mode feature The on board super I O chipset integrates two serial ports driven by two high performance 16550C compatible UARTs to provide 16 byte send receive FIFOs Besides the two Universal Serial Bus ports provide high speed data communication between peripherals and PC The on board flash ROM is used to make the BIOS update easier The high precision Real Time Clock Calendar is built to support Y2K for accurate scheduling and storing configuration information All of these features make PPAP 2020 excellent in stand alone applications If any of these items is damaged or missing please contact your vendor and save all packing materials for future replacement and maintenance NAR 2090 User s Manual 51 3 2 System Architecture The following illustration of block diagram will show you how PPAP 2020 gives you a highly integrated system solution The most up to date system architecture of PPAP 2011 includes two main
38. intf n n SYS WDT AUTO TEST gt PASS A A Press any key to continue getche NAR 2090 User s Manual 49 goto Main_menu End of ifG g Main Menu Selection lt 2 gt I else if i 0x32 printf n n Set BYPASS amp NORMAL Modes testing gt Sound of Relay operation and LED on off n for k l k lt 5 k al char Set bypass0 if al char 0x00 goto next normal test printf n n Error 08 Set to Bypass test failed n outportb config VT1211 0xaa exit config mode exit 1 next_normal_test WDT_disableQ delay 800 al char Set normal if al_char 0x00 goto next_bypass_test printf n n Error 09 Set to Normal test failed n outportb config VT1211 Oxaa exit config mode exit 1 next_bypass_test WDT_disableQ delay 800 printf min Set BYPASS amp NORMAL Modes test OKAY _ Press any key for more tests getche goto Main_menu end of if G 0x32 else goto Main_menu end of Main NAR 2090 User s Manual 50 Chapter 3 Operation Guide 3 1 Brief Guide of PPAP 2020 PPAP 2020 is a Communication Appliance computing board based on VIA VT8237R chipset technology PPAP 2020 has four five on board LAN ports to serve communication appliances such as Firewall which needs four Ethernet ports to connect external network internet demilitarized zone and internal network Different I O mana
39. its components peripheral chips memory modules or gold contacts When handling memory modules avoid touching their pins or golden edge fingers Put the value communications appliance system board and peripherals back into the antistatic bag when they are not in use or not installed in the chassis Some circuitry on the system board can continue operating even though the power is switched off Under no circumstances should the Lithium coin cell be used to power the real time clock be allowed to be shorted The coin cell can heat under these conditions and present a burn hazard WARNING 1 CAUTION Danger of explosion if battery is incorrectly replaced Replace only with the same or equivalent type recommended by the manufacturer Discard used batteries according to the manufacturer s instructions 2 This guide is for technically qualified personnel who have experience installing and configuring system boards Disconnect the system board power supply from its power source before you connect disconnect cables or install remove any system board components Failure to do this can result in personnel injury or equipment damage go Avoid short circuiting the lithium battery this can cause it to superheat and cause burns if touched A Do not operate the processor without a thermal solution Damage to the processor can occur in seconds 5 Do not block air vents Minimum 1 2 inch for clearance required NAR 2090 User s Manual 3
40. lTek 8110SC 32 bit Gb Ethernet controller with RJ 45 interface Support on board hardware monitor for CPU fan System fan System voltages Operating Temperature 5 C 40 C Storage Temperature 0 70 C Relative Humidity 5 95 non condensing 214mm L x 225mm W x 52mm H NAR 2090 User s Manual 11 2 12 Hardware Configuration Setting This section gives the definitions and shows the positions of jumpers headers and connectors All of the configuration jumpers on PPAP 2011 are in the proper position The default settings set by factory are marked with a star x Jumpers In general jumpers on PPAP 2020 system board are used to select options for certain features Some of the jumpers are configurable for system enhancement The others are for testing purpose only and should not be altered To select any option cover the jumper cap over Short or remove NC it from the jumper pins according to the following instructions Here NC stands for Not Connected NAR 2090 User s Manual 12 VIA CN 700 Li 10000909 LEGER PPAP 2020 Jumper Table JP1 8 J17 pin Header 2 4 6 1 3 5 Function 1 3 2 4 Short Power on default at Normal mode mode selection is S W programmable NAR 2090 User s Manual 3 5 2 4 Short Power on default at Bypass mode mode selection is S W programmable 4 6 Short Always at normal mode JP2 CMOS Clear J32
41. l_char WDT REFRESH 1K 58 55769 break case 0x48 al_char WDT REFRESH 1K 60 57692 break case 0x68 al_char WDT REFRESH 1K 60 57692 break case 0x49 al_char WDT_REFRESH_1K 62 59615 break case 0x69 al_char WDT_REFRESH_1K 62 59615 break default al_char WDT_REFRESH_1K 1 1 break end of switch if al char 0x1b goto Main menu ESC return printf n n Refresh BP WDT 1000 times gt PASS _ Press any key to do more tests getche0 goto Sub Menu end of if G 0x31 pp Main Menu Selection lt E gt pp NAR 2090 User s Manual 46 else if 1 E ll i e retrigger 1000 times CLEARJ_SYS_WDT_STS_HLHO SYSWDT_Sub_Menu Sub_menu_display OxAA K i getcheQ printf gt n n if i Q Ili q goto Main menu switch 1 case 0x31 al_char WDT RESH 1K 1 989 break case 0x32 al_char WDT_RFSH_1K 2 1978 break case 0x33 al char WDT_RFSH_1K 4 3956 break case 0x34 al_char WDT_RFSH_1K 8 7912 break case 0x35 al char WDT RESH 1K 14 13461 break case 0x36 al_char WDT_RFSH_1K 20 19231 break case 0x37 al char WDT_RFSH_1K 26 25000 break case 0x38 al char WDT RFSH 1K 30 28846 break case 0x39 al char WDT RFSH 1K 34 32692 break case 0x41 al char WDT RFSH 1K 38 36538 break case 0x61 al char WDT_RFSH_1K 38 36538 br
42. m cmp al lbh asm jeesc return if Esc pressed goto esc return for i loop WDT_disableQ return 0x00 esc_return WDT_disableQ return Ox1b end of uc WDT REFRESH 1K ui ui unsigned char WDT_RFSH_1K unsigned int ax twd unsigned int ax idle ms Global Variable GPIOBASE needs to be known first Global constant adopted Called function IO delay SSYSWDT_disableQ fixdelay 15us0 SYSWDT_LOADJ_HLHO inline asm Retuned ESC return Ox1b Normal 1000 times refresh return 0x00 unsigned char al 4 al 5 unsigned int ij al 4 ax twd amp Ox3F Truncate high word Twd load into WDT 5 0 GP15 10 first al 5 inportb GPIOBASE GPIO1X OFFSET amp OxCO al 5 al 5l al 4 IO_delayO outportb GPIOBASE GPIO1X OFFSET al 5 write GP15 10 for i 17 i lt 1000 i NAR 2090 User s Manual 32 SYSWDT_LOADJ_HLHO for j 1 j lt 80 j printf b printf Enable or Refresh SYS WDT d times at I Get time and Date gettime amp t printf 02d 02d 02d 02d t ti hour t ti min t ti sec t ti hund getdate amp d printf d d d Refreshing d da mon d da day d da year I for j 1 J lt 80 printf b if i 1 delay 6 else fixdelay 15us0 if ax idle ms 1 delay ax idle ms else if i 1 delay ax idle ms 6 else delay ax idle ms al 5 inportb GPIOBAS
43. n Reading this chapter will teach you how to set up NAR 2090 Chapter 3 Operation Information This section gives you illustrations and more information on the system architecture and how its performance can be maximized Any updates to this manual technical clarification and answers to frequently asked questions would be posted on the web site http isc portwell com tw 1 3 Technical Support Information Users may find helpful tips or related information on Portwell s web site htip www portwell com tw A direct contact to Portwell s technical person is also available For further support users may also contact Portwell s headquarter in Taipei or your local distributors Taipei Office Phone Number 886 2 27992020 NAR 2090 User s Manual 2 Chapter 2 Get Started This section describes how the hardware installation and system settings should be done 2 1 Included Hardware The following hardware is included in your kit PPAP 2020 Communication Appliance System Board e One null serial port cable 22 Before You Begin To prevent damage to any system board it is important to handle it with care The following measures are generally sufficient to protect your equipment from static electricity discharge When handling the board use a grounded wrist strap designed for static discharge elimination and touch a grounded metal object before removing the board from the antistatic bag Handle the board by its edges only do not touch
44. nit GPIO60 61 polarity outportb config VT1211 OxFO point to GPIO50 57 Non inverse 1 output direction al char inportb config VT1211 1 amp OxFC I 0x04 Bit 2 1 0 P 100 outportb config VT1211 OxF0 outportb config VT1211 1 al char outportb config VT1211 OxF2 outportb config VT1211 1 0x00 init GPO17 direction and polarity outportb config VT1211 OxFO al char inportb config_VT1211 1 amp OxF8 outportb config VT1211 OxFO outportb config_VT1211 1 al char outportb config VT1211 OxF2 Non inverse outportb config VT1211 1 0x00 outportb config VT1211 OxF1 al_char outportb config VT1211 OxF1 outportb config _VT1211 1 al char al char inportb GPIOBASE GPIO1X OFFSET amp Ox7F point to GPIO60 67 Non inverse Bit 2 1 0 P 000 point to GPIO 10 17 inportb config VT1211 1 OxFF 1 output direction GPIT init to 0 al char inportb GPIOBASE GPIO1X OFFSET amp 0x7F 10x7F GP17 init to 0 GP16 gt 1 IO delay0 outportb GPIOBASE GPIO1X OFFSET al char PO Main menu system cls NAR 2090 User s Manual 40 printf n printf PORTWELL PPAP 2020 BP_WDT s All rights reserved n VER DATE al char inportb GPIOBASE GPIO4X OFESET amp 0x08 Check B
45. p kesms LJ RTC lt Figure 3 2 PPAP 2020 Block Diagram NAR 2090 User s Manual 53
46. p Menu Exit current page and return to Main Menu General help on SETUP navigation keys Load the fail safe defaults from BIOS default table Load previous values from CMOS Load the optimized defaults Save all the CMOS changes and exit Yh Main Menu Once you enter NAR 2090 Award BIOS CMOS Setup utility you should start with the Main Menu The Main Menu allows you to select from eleven setup functions and two exit choices Use arrow keys to switch among items and press lt Enter gt to accept or bring up the sub menu NAR 2090 User s Manual 20 Phoenix Award BIOS CMOS Setup Utility CMOS Setup Utility Standard CMOS Features Frequency Voltage Control Advanced BIOS Features Load Fail Safe Defaults Advanced Chipset Features Load Optimized Defaults Integrated Peripherals Set Supervisor Password Power Management Setup Set User Password PnP PCI Configurations Save amp Exit Setup PC Health Status Exit Without Saving ESC Quit Tt lt gt Select Item F10 Save amp Exit Setup Shift F2 Change Color Time Date Hard Disk Type NOTE It is strongly recommended to reload the optimized default setting if CMOS is lost or BIOS is updated Standard CMOS Setup Menu This setup page includes all the items within standard compatible BIOS Use the arrow keys to highlight the item and then use the lt PgUp gt lt PgDn gt or lt gt lt gt keys to select the value or number you want in each item and press
47. rmal state 1 CLEARJ_BP_WDT_STS_HLHO go_on_test_D Twd load into WDT 5 0 GP51 50 47 46 45 44 first al char inportb GPIOBASE GPIOSX OFFSET amp OxFC IO_delayO outportb GPIOBASE GPIOSX OFFSET al char write GP51 50 al char inportb GPIOBASE GPIO4X OFFSET amp 0x0F I 0x10 IO delay0 outportb GPIOBASE GPIO4X_OFFSET al char write GP47 46 45 44 LOADJ_HLHO sleep 2 Pause 2 seconds to wait for BP_WDT expire al_char inportb GPIOBASE GPIO4X_OFFSET amp 0x04 if al char 0x00 goto BP WDT status tl printf n n Error 04 BY WDT status bit error Quit and Return to DOS n n outportb config VT1211 0xaa exit config mode exit 1 BP WDT status tl CLEARJ BP WDT STS HLH al char inportb GPIOBASE GPIO4X_OFFSET amp 0x04 if al char 0x04 goto BP WDT status 12 printf n n Error 05 BY WDT status bit error Quit and Return to DOS n n outportb config VT1211 Oxaa exit config mode exit 1 BP WDT status t2 Set normal printf min BP WDT status bit test gt PASS _ Press any key to continue getche goto Main_menu end of choice D Main Menu Selection lt A gt else if G 0x41 I 0x61 NAR 2090 User s Manual 43 printf n n Set BYPASS amp NORMAL Modes testing gt Sound of Relay operation and LED on off n for k l k lt 5 k
48. sh card drive If the CF is not pre installed you can install it by yourself Follow the steps below to install the CF 3 Fasten the five screws to lock bracket together Fig 2 11a 2 11b EE a Fig 2 11b Push CF into the bracket Fig 2 11a Remove L type base under button case 4 Completion CF to the System Chassis Fig 2 12 NAR 2090 User s Manual 6 Fig 2 12 completion CF in system 2 8 The system has an internal drive bay for one 3 5 hard disk drive If the HDD is not pre installed you can install by yourself You need the parts from the accessory bag as shown on Figure 2 19 Install 3 5 Hard disk Fix all screws back Fig 2 13 They are one HDD bracket several screws from left to right Fig 2 14 Fig 2 15 Fix the Metal Spacers 14mm Fig 2 16 Placement the HDD bracket Fig 2 17 Fix HDD bracket 5 Connect Power Cable and IDE Cable before assemble hard disk After assemble hard disk put IDE Cable and Power cable into board NAR 2090 User s Manual 7 Fig 2 18 Fix the hard disk drive on the HDD Fig 2 19 Completion HDD with bracket bracket with four screws Plug the IDE cable into hard disk drive connector NAR 2090 User s Manual 8 2 9 Add riser card into system 1 Put Riser Card into Metal bracket 2 Put PCI Card Device into riser card assembly Fig
49. tion al char inportb config VT1211 1 10xB5 amp OxFD 1 output direction outportb con outportb con l End fig_VT1211 OxF1 fig VT1211 1 al_char of GPO34 35 37 init GPO40 41 44 47 GPI42 43 direction and polarity outportb config VT1211 OxFO al char inportb config_VT1211 1 amp OxFA I 0x02 Bit 2 1 0 P 010 outportb config _VT1211 OxFO point to GPIO40 47 outportb config_VT1211 1 al char outportb config _VT1211 OxF2 Non inverse NAR 2090 User s Manual 39 outportb config _VT1211 1 0x00 outportb config VT1211 OxF1 al char inportb config VT1211 1 amp 0xF3 I OxF3 1 output direction outportb config VT1211 OxF1 outportb config _VT1211 1 al char Noain End of GPO40 41 44 47 GPI42 43 init GPO50 51 direction and polarity outportb config VT1211 OxFO 0 Input direction al char inportb config VT1211 1 amp OxFB I 0x03 Bit 2 1 0 P 011 outportb config _VT1211 OxFO outportb config _VT1211 1 al char outportb config _VT1211 OxF2 outportb config VT1211 1 0x00 outportb config VT1211 OxF1 al char inportb config _VT1211 1 10x03 outportb config VT1211 OxF1 outportb config _VT1211 1 al char End of GPO50 51 i
50. u display 0x55 K i getche Q printf gt n n if i Q Ili q goto Main menu switch 1 case 0x31 al_char WDT_REFRESH_1K 1 989 break case 0x32 al_char WDT_REFRESH_1K Q 1978 break case 0x33 al_char WDT_REFRESH_1K 4 3956 break case 0x34 al_char WDT_REFRESH_1K 8 7912 break case 0x35 al_char WDT_REFRESH_1K 14 13461 break case 0x36 al_char WDT_REFRESH_1K 20 19231 break case 0x37 al char WDT REFRESH 1K 26 25000 break case 0x38 al_char WDT_REFRESH_1K 30 28846 NAR 2090 User s Manual 45 break case 0x39 al char WDT REFRESH 1K 34 32692 break case 0x41 al_char WDT_REFRESH_1K 38 36538 break case 0x61 al_char WDT REFRESH 1K 38 36538 break case 0x42 al_char WDT REFRESH 1K 42 40385 break case 0x62 al_char WDT REFRESH 1K 42 40385 break case 0x43 al_char WDT_REFRESH_1K 46 44231 break case 0x63 al_char WDT_REFRESH_1K 46 44231 break case 0x44 al char WDT_REFRESH_1K 50 48077 break case 0x64 al_char WDT_REFRESH_1K 50 48077 break case 0x45 al char WDT_REFRESH_1K 54 51923 break case 0x65 al char WDT REFRESH 1K 54 51923 break case 0x46 al_char WDT REFRESH 1K 56 53846 break case 0x66 al char WDT REFRESH 1K 56 53846 break case 0x47 al_char WDT REFRESH 1K 58 55769 break case 0x67 a
51. usQ al char inportb GPIOBASE GPIO3X OFFSET I 0x10 IO_delayO outportb GPIOBASE GPIO3X OFFSET al char P1 Second high pulse fixdelay 15us0 End of LOAD HLHO void SYSWDT LOADJ HLHO Global Variable GPIOBASE needs to be known first Global constant adopted Called function IO_delayQ fixdelay 15us0 unsigned char al_char LOADJ H_L_H pulse al char inportb GPIOBASE GPIO1X OFFSET 1 0x40 GP16 LOAD IO delay0 outportb GPIOBASE GPIO1X OFFSET al char P1 First high pulse fixdelay 15us0 al char inportb GPIOBASE GPIO1X OFFSET amp OxBF IO_delayO outportb GPIOBASE GPIO1X OFFSET al char PO low pulse fixdelay 15us0 al char inportb GPIOBASE GPIO1X OFFSET 0x40 IO delay0 outportb GPIOBASE GPIO1X OFFSET al char P1 Second high pulse fixdelay 15us0 End of SYSWDT LOADJ HLHO void CLEARJ BP WDT STS HLHOQ Global Variable GPIOBASE needs to be known first Global constant adopted Called function IO_delayQ fixdelay 15us0 unsigned char al_char I CLEAR H_L_H pulse al char inportb GPIOBASE GPIO3X OFFSET I 0x20 GP35 CLEARJ IO_delayQ outportb GPIOBASE GPIO3X OFFSET al char P1 First high pulse fixdelay 15us0 al char inportb GPIOBASE GPIO3X OFFSET amp OxDF
52. ypass status GP43 high bypass if al char 0x08 printf Current mode status gt Bypass Mode LED OFF An else printf Current mode status gt Normal Mode LED ONV n printf WW TEST PROGRAM FOR MS DOS ENVIRONMENT n printf For PPAP 2020 By Pass function BP WDT and SYS_WDT test lt lt lt DOS program gt gt gt n printf BP_WDT SYS WDT ZR2 and later n printf Twd SIO_GP44 GP47 GP50 51 SIO GP15 10 An printf LOADJ SIO_GP34 SIO GPI6 n printf BP STS Bit SIO GP43 None Ap printf DIS BP WDT SIO GP41 SIO GP30 An printf WDT Time out STS bit SIO_GP42 SIO GP31 An printf Reset WDT timeout bit SIO GP35 SIO GP32 An printf SW SET NORMAL MODE A SIO GP37 None n printf SW_SET_BY_PASS_MODE _A SIO GP40 None An printf lt 1 gt ENABLE BP_WDT REFRESH BP WDT 1000 TIMES amp DISABLE BP WDT n printf lt 2 gt SET NORMAL and BY_PASS mode test n printf lt A gt BP WDT AUTO TEST M First lt 2 gt SET Mode test then lt 1 gt BP_WDT test n printf lt B gt SET TO BY PASS AND RETURN TO MS DOS An printf lt C gt RUN BP EXT LOOPBACK by connecting GPIO Port J14 to a test fixture n printf lt D Test BP WDT status bit and RESET the status bit after BP WDT timeout An printf lt E gt ENABLE SYS WDT REFRESH SYS WDT 1
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