AN11461 - NXP Semiconductors
Contents
1. Fig 4 Schematics of the PTEV501B analog part Component type Part Nr Value Capacitor C12 C15 C20 1 nF Capacitor C13 C25 220 pF Resistor R16 1 kO Resistor R19 00 Resistor R25 R26 R27 R29 440 s gt ie MATCHING R13 0R i a a C14 ar am ame Laa 470nH ari DETARE CARL R Fig 5 Schematics of the PNEV512B analog part AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 5 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 AN11461 2 2 2 3 PTEV501B Quick Startup Guide Figure 4 and 5 show the analog parts of the PTEV501B and PNEV512B boards DNP do not place means that this components have routed footprints but are not placed on the PCB to show the differences to the PNEV512B Table 2 Unused components of the PNEV512B analog part Component type Part Nr Inductor L2 L3 L4 Resistor R23 Capacitor C7 C8 C14 C16 C17 C18 C21 C22 C23 C24 CE certification of the Blueboard The PTEV501B V1 0 is CE certified LPCXpresso LPC1227 development board The LPC1227 development board integrates a NXP ARM Cortex MO microcontroller LPC1227 with 128 Kbytes of Flash memory and 8 Kbytes of RAM It integrates a lot of hardware parts e 1 Serial UART interface e 1 SPI controller e 1 IPC controller e Serial Wire test2. assnnnnsnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 31 COMEN Sossi enna ee ener neers re nee 32 PTEV501B Quick Startup Guide Please be aware that important notices concerning this document and the product s described herein have been included in the section Legal information NXP N V 2014 All rights reserved For more information visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 6 March 2014 277612 Document identifier AN11461
3. s snassnnnnnnnnnnnnnnnnnn 10 Hardware configuration cccccsseeeeeeeeeeeees 10 Software configuration cecceeseeeeeeeeeeeeeaees 11 LPC1227 LPCXpresso Board as clock source 11 Configure the Main CIOCK cccceeseeeeeeeees 12 Enable the CLKOUT functionality 12 Configure the CLKOUT setup 0 13 Other clock SOUMCE ccccecceeeeceseeeeeeeeeeaneeees 13 Installation of the LPCXpresso Board 14 Managing the PT501 CE solution project with LPCXpresso IDE arisen betes dice te lecesstececiniecet 14 Installation of LPCXpresso IDE 008 15 Extraction of the PT501 CE solution project 19 Start the PrOojecCt cccccceceeecseeeeeeeeeeeeeeeeeeenees 22 Run the project cccscccssesessseeseeeeseeeesseeeens 22 Card Emulation Associated Project 25 Tag Type 2 and Type 4 Card Emulation 25 Configuration of the example project 25 Changing the NDEF messag 000008 26 Program flOW ccccecccceececeececeeeeeseeeseeeesaeees 28 FICTCRENCCS eise n aE 29 Legal information sccccceesseeeseneeseeeseeeeeneenes 30 Definitions exe vac seseee ce score aceeseceoueesreJecseceeecszeece ean 30 DISCIAIMESS cece ceccccececeeeceeeeseeeseeeeaeeeseeeeaees 30 GCS OG E A E E AET 30 Trademarks c cccccecccseecenceceeeceeeccueesseeseeeenes 30 List of figuUresS
4. Please read the following License Agreement You must accept the terms of this agreement before continuing with the installation CODE RED TECHNOLOGIES LIMITED End User Licence Agreement for LPCXpresso Software Development Tools November 7009 THIS END USER LICENCE AGREEMENT LICENCE IS A LEGAL AGREEMENT BETWEEN YOU EITHER A SINGLE INDIVIDUAL OR Fig 22 LPCXpresso installation setup wizard 2 There are numbers of other screens on the setup wizard but generally the default options can be accepted After installation an information file will be displayed Click Next to accomplish the installation Setup LPCXpresso Installing Please wait while Setup installs LPCXpresso on your computer Extracting files Cr pexpresso Tools ibexec gcc arm none eabi 4 5 Iech exe i Fig 23 LPCXpresso installation setup wizard 3 After this installation step one will be asked if he wants to install some required drivers The installation of these drivers should be accepted AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 16 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide Would you like to install this device software Mame Code Red Technologies Publisher Code Red Tec
5. a TEA Cs T EEREN ote A a Fig 9 Connect the two boards AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 7 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide 2 5 Interesting points of measurement On the PTEV501B Evaluation board are test pads for measurement purposes e VCC e GND e D5 e D6 e D7 e ALE e AUX1 e AUX2 e SIGIN e SIGOUT e IRQ e VMID s gt 6 go k gt g A FTA f 3 gt ow gn d d A d A XQ OSoqoqoeqooeoeo0oo0oo0oo0oo0nocnoceceoecs E mc3i i R31 M Bc I2C or L j ofm Ls UMID 211 OR Bow IC2 He ALE Biese cE u o e y Fig 10 Interesting points of measurement 2 6 Preparing the Blueboard for the use with SPI or I C The Blueboard is generally delivered in SPI configuration To change the interface to I C the four appropriate ORO resistors in the interface config section need to be resoldered on the C side of the solder jumpers Also the two ORO resistors at AO and A1 need to be changed Table 3 AO and A1 interface configuration Appropriate solder jumpers ORO resistors for interface configuration Signal Interface type SPI 2C AO R20 R21 A1 R24 R23 AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Applicati
6. Innovatron Technology 8 4 Trademarks Notice All referenced brands product names service names and trademarks are property of their respective owners MIFARE is a trademark of NXP N V DESFire is a trademark of NXP N V MIFARE Ultralight is a trademark of NXP N V MIFARE Plus is a trademark of NXP N V NXP N V 2014 All rights reserved Application note COMPANY PUBLIC Rev 1 2 6 March 2014 2 7612 30 of 32 NXP Semiconductors AN11461 9 List of figures Fig 1 Fig 2 Fig 3 Fig 4 Fig 5 Fig 6 Fig 7 Fig 8 Fig 9 Fig 10 Fig 11 Fig 12 Fig 13 Fig 14 Fig 15 Fig 16 Fig 17 Fig 18 Fig 19 Fig 20 Fig 21 AN11461 Picture of PTEV501B Evaluation board 3 Picture of solder bridges in default configuration ceccceceeeceeeeeeeceeeeeesaeeeeeseeeeeeas 4 Comparison of PTEV501B and PNEV512B 4 Schematics of the PTEV501B analog part 5 Schematics of the PNEV512B analog part 5 Picture of LPCXpresso LPC1227 development DOO eee eee eee oer ae ore eee ee ee 6 Multipoint Connectors we US ccceeeeeees 7 LPCXpresso with the Multipoint Connectors 7 Connect the two boards cccceeceeeeeeeeeeeees 7 Interesting points of measurement 0 8 Blueboard in SPI configuration ccccecee 9 Blueboard in C configuration ccceeeee 9 Crystal oscillator as clock so
7. debug interface e For detailed information see LPC12xx User Manual 5 The LPCXpresso board contains a JTAG SWD debugger called the LPC Link and a target MCU LPC Link is equipped with a 10 pin JTAG header and it seamlessly connects to the target via USB the USB interface and other debug features are provided by NXP s ARM9 based LPC3154 MCU roils C7 a JC 23 a n Toe Tal J v J LPC L ins 6225 a ETP 2 Cc J SO Zai TP RST Fd f O oes J Sy Fig 6 Picture of LPCXpresso LPC1227 development board 2 4 Preparation of the hardware The first step after unpacking the Blue Board and the LPCXpresso is soldering the connectors onto the boards to get them together In our example we use a multipoint connector as one can see on the pictures below All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note COMPANY PUBLIC Rev 1 2 6 March 2014 6 of 32 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide Fig 7 Multipoint Connectors we used One may buy these connectors at any electronic store Here are some examples 7 After soldering the connectors connect the boards as shown on the following figure Fig 8 LPCXpresso with the Multipoint Connectors Now the hardware is ready to use Please connect the LPCXpresso board with the Blueboard gt
8. it won t work because of the missing power File Action View Help al El Hm Pee t Monitors h a Network adapters t I Ports COM amp LPT E B Processors gt le Smart card readers bs li Sound video and game controllers b e Storage controllers b gill System devices a Universal Serial Bus controllers e Generic USB Hub oo Generic USB Hub Generic USB Hub Generic USB Hub a Generic USB Hub 2 g Intel R 6 Series C200 Series Chipset Family USB Enhanced Host Controller 1026 y 2 g Intel R 6 Series C200 Series Chipset Family USB Enhanced Host Controller 1C2D 2 a USB Composite Device S36 Composite Device QE USB Device with DFU Capabilities USE Ta i E Fig 20 Enumeration of the LPCXpresso Board in Device Manager Window 5 Managing the PT501 CE solution project with LPCXpresso IDE The PT501 Card emulation solution project is delivered in a zip package It can be extracted edited compiled and linked with LPCXpresso IDE LPCXpresso is a new low cost development platform available from NXP It supports NXP s ARM based LPC microcontrollers The platform is comprised of a simplified Eclipse based IDE and low cost target boards which include an attached JTAG debugger Use at least the LPCXpresso version 4 2 or higher to benefit a bug free IDE and the up to date features AN11461 All information provided in this document is subject to
9. legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 14 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide This tool can be freely downloaded from the LPCXpresso website 2 Before one can download the software it is necessary to create an account Creating an account is absolutely free 5 1 Installation of LPCXpresso IDE The IDE is installed into a single directory of one s choice Multiple versions cans be installed simultaneously without any issues The installation starts after double clicking the installer file Then click next on the setup wizard Welcome to the LPCXpresso Setup Wizard This will install LPCXpresso 4 1 0 Build 190 on your computer Itis recommended that you close all other applications before Click Next to continue or Cancel to exit Setup Powered by cod e red Fig 21 LPCXpresso installation setup wizard 1 Then read the license agreement then click next AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 15 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide E Setup LPCX presso z License Agreement Please read the following important information before continuing
10. project into the LPCXpresso IDE 21 RUN the PrOjeCt cccececseeeeceeeeeeeeeeaeeesaeeeees 22 RUN the project cccccccssecesssseseeeeseeeeseeeeens 22 RUN the Project cccccccsseceseseeseeeseseesseeeens 23 RUN the project cccccccssecesseseseseeseeeeseeeeens 23 Stop the Project ccccccccccsececeeeeseeeeeseeeeees 24 Debug BUONS vscicii titi oinirciornivdatminecntoin deine 24 Program Flash icon in LPCXpresso IDE 25 Program Flash wizard with Erase flash memory AON ats E EE EE EE E E 26 Change NDEF content for T4T 8 27 Change NDEF content for T2T 08 27 Program flow of the Card Emulation 216 6 er 6 6 eee ener ee nee eee 28 NXP N V 2014 All rights reserved Application note COMPANY PUBLIC Rev 1 2 6 March 2014 2 7612 31 of 32 NXP Semiconductors AN11461 10 Contents PATO GUC LION ass 3 Hardware overview of the PT501 Card Emulation solution 0ccccccseseeeeeeseeeeeneeeeeeneeseees 3 PTEV501B Evaluation board cccccceeeeee es 3 Comparison with the PNEV512B Evaluation ORG PNE E AA E A T 4 CE certification of the Blueboard 06 6 LPCXpresso LPC1227 development board 6 Preparation of the Nardware ccccceeeeeeeeees 6 Interesting points of measurement 005 8 Preparing the Blueboard for the use with SPI or E E E 8 PT501 clock requirements
11. 147 146 149 f lt lt lt end of configuration section gt 150 7 Fig 17 CLKOUT configuration AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 12 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide 3 2 1 3 Configure the CLKOUT setup With the enabled CLKOUTCLK_SETUP in the previous section the i statement for the CLKOUT configuration is true The CLKOUT function is routed to PIOO_ 12 and needs to be configured 0x02 It is very important to update the clock source by toggling the CLKOUTUEN register t main c c system LP C12 23 461 452 if CLEOUTCLE SETUP 463 LPC OcON gt PIOO lz Oxde f CLEOUT function 454 LPO SYSCON gt CLEOUTCLESEL CLEOUTCLESEL Val 455 LPC S YSCON gt CLEOUTUEN 0x01 f update CLEOUT source 456 LPC S YSCON gt CLEOUTUEN 0x00 487 LPC SYSCON gt CLEOUTUEN 0x01 455 LPO AYSCON gt CLEOUTDIV CLEOUTCLEDIV Val 459 endif Fig 18 CLKOUT setup configuration For detailed information about the LPC1227 clock configuration and register settings please refer to the product datasheet and user manual 3 2 2 Other clock source If any other clock source with a frequency between 1 MHz and 23 MHz is used for the PT501 following register settings are mandatory to turn off the frequency che
12. 2 14 06 5 s No card or Tag detected E Project and File wizards No card or Tag detected No card or Tag detected A No card or Tag detected E Build and Settings y card or Tag detected p 5 card or Tag detected E Debug and Run __ MIFARE Classic detected Extras y MIFARE Classic detected Import and Export PN512 Polling Fig 36 Run the project After the software upload the execution of the project starts immediately AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 23 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN11461 AN11461 PTEV501B Quick Startup Guide eh Run Project Help s P N i a EG Ta E BE F e E X Develop F Debug nN i 2 a E PN512 Polling Debug C C MCU Application a MCU GDB Debugger 02 11 12 14 06 p Thread 1 Running po arm none eabi gdb 02 11 12 14 05 Fig 37 Stop the project es are 8 et eee Nee Tee a a Ea ee Ee After the execution has reached the end of the main function please click the Terminate button to stop the execution Otherwise one won t be able to rerun the project One can now do the following with the buttons towards the top of the Debug view Oe Run the program Step over C C line Stop the debugger O0 Pau
13. AN11461 Quick Start Up Guide PTEV501B Board Rev 1 2 6 March 2014 Application note 277612 COMPANY PUBLIC Document information Info Content Keywords PTEV501 PT501 LPCXpresso MCU Code Red eclipse LPC1227 reader library Abstract This application note is related to the installation procedures of the PTEV501B Board It describes the board and the required actions to hand on quickly the Evaluation board NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide Revision history Rev Date Description 1 2 20140306 Updated clock configuration for use with external clock source 1 1 20131212 Added Mass erase description and schematics of PTEV501B analog part 1 0 20131118 First release Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 2 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide 1 Introduction This application note gives a detailed overview of the hardware for operating with the PT501 NFC Card Emulation and NFC Peer to Peer Solution 1 We use the LPCXpresso LPC 1227 4 and the Blueboard Chapter 2 the installation procedures of the Development Environment Chapter 5 1 and the handlin
14. All rights reserved Application note Rev 1 2 6 March 2014 3 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN11461 2 1 1 PTEV501B Quick Startup Guide 7u Q N R31 i 29a Sale t om CONF IG SPI 12C LJ O T L m4 LJ jm Z k xX O lil N W Blueboard PTEV501 Fig 2 Picture of solder bridges in default configuration The default interface configuration of the PTEV501B Evaluation board is SPI The detailed interface configuration is described in section 2 6 Comparison with the PNEV512B Evaluation board The PTEV501B has basically the same board layout as the PNEV512B Evaluation board Since the PT501 acts as passive device in card emulation and P2P mode all parts for the transmitter output are not necessary This is visible if one compares the two boards as in Figure 3 Fig 3 Comparison of PTEV501B and PNEV512B oe 7 A Blueboard PNEVS12B Antenna Sea v4 l m Of C eer Y t J I OF t Om mo u O 3 of Or ON Siji i TS a AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note COMPANY PUBLIC Rev 1 2 6 March 2014 277612 4 of 32 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide The list of necessary components for the receiver part find here Table 1 Necessary components of the PTEV501B analog part
15. ait for card activation phCardEmu_Activate Configure IRQ pin phOsal_Lpci2xx_ConfigIRQ Activation successful Configure Power Sleep Pin phOsal_Lpc12xx_CommDev_Config Initialize Card Emulation component phCardEmu_Init First command after activation was a RATS T2T enabled Start T4 T component Initialize T2T component phCardEmu_T4T_Start phCardEmu_T2T_Init Start T2T component phCardEmu_T2T_Start T4T enabled Initialize T4T component phCardEmu_T4T_Init Fig 43 Program flow of the Card Emulation application The first blocks describe the initialization of the necessary layers and components independent of the card emulation Depending which tag type is used the appropriate component will then be initialized If Tag Type 2 and Tag Type 4 are enabled both are AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 28 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide being initialized After applying the protocol settings the PT501 waits for a successful activation or the card side According to the first command RATS yes or no after the card activation the appropriate tag type component starts 7 References 1 PT501 data sheet http www nxp com documents data_sheet PT501 pdf 2 LPCXpresso website
16. and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary AN11461 All information provided in this document is subject to legal disclaimers PTEV501B Quick Startup Guide testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Evaluation products This product is provided on an as is and with all faults basis for evaluation purposes only NXP Semiconductors its affiliates and their suppliers expressly disclaim all warranties whether express implied or statutory including but not limited to the implied warranties of non infringement merchantability and fitness for a particular purpose The entire risk as to the quality or arising out of the use or performance of this product remains with customer In no event shall NXP Semiconductors its affiliates or their suppliers
17. be liable to customer for any special indirect consequential punitive or incidental damages including without limitation damages for loss of business business interruption loss of use loss of data or information and the like arising out the use of or inability to use the product whether or not based on tort including negligence strict liability breach of contract breach of warranty or any other theory even if advised of the possibility of such damages Notwithstanding any damages that customer might incur for any reason whatsoever including without limitation all damages referenced above and all direct or general damages the entire liability of NXP Semiconductors its affiliates and their suppliers and customer s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars US 5 00 The foregoing limitations exclusions and disclaimers shall apply to the maximum extent permitted by applicable law even if any remedy fails of its essential purpose 8 3 Licenses Purchase of NXP ICs with ISO IEC 14443 type B functionality E This NXP Semiconductors IC is ISO IEC 14443 Type B software enabled and is licensed under Innovatron s F Contactless Card patents license for ISO IEC 14443 B The license includes the right to use the IC in systems and or end user equipment RATP
18. ck 1 Write OxBF to register Ox3C 2 Read from register 0x3C In the Card Emulation software package this register setting can be activated deactivated by the define PT501_EXT_XTAL statement in main c 156 ifdef PT5 1 EXT XTAL 157 t switch off frequency check 158 uint t value 168 status phhalHhw_WriteRegister phhalHhw ReS25 DataParams t jahal x3C xBF 161 CHECK STATUS status 163 status phhalHw ReadRepister phhalHw RceS23 DataParams t jahal x3C amp waluej 164 CHECK STATUS status 165 endif Fig 19 Register settings for the frequency check function in main c AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 13 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide 4 Installation of the LPCXpresso Board The guidelines to install the reader are as follows e Connect the LPCXpresso Board to a real USB2 0 port of the PC for speed reasons using the mini USB connector The PC detects and installs the Board automatically e Once the Board is installed open the Device Manager of the PC to check that the installation is successful The item USB Device with DFU Capabilities is displayed Please be sure to always connect both USB ports to the computer If the USB port of the Blueboard is not connected to an USB port
19. eof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications
20. g of the project using the NXP Reader Library Chapter 5 3 The projects used in this documentation are e Card Emulation 2 Hardware overview of the PT501 Card Emulation solution The PT501 Card Emulation solution is made up of 2 separate boards e A PTEV501B Evaluation board 3 provided by NXP 12NC 9353 029 06699 This board has connectors which are designed to fit exactly to the ones of the companion LPCXpresso LPC 1227 development board e Acommercial LPCXpresso LPC 1227 development board 4 12NC 935294603598 Type OM13008 which can be provided by NXP or bought directly on the market See 2 Once the two boards are put together via the connectors the PT501 Card Emulation solution is ready for use 2 1 PTEV501B Evaluation board Blueboard PT501 Antenna NXO CE Fig 1 Picture of PTEV501B Evaluation board The PTEV501B Evaluation board embeds the PT501 generic 13 56 MHz communication interface with matching network and the antenna The PT501 supports different kind of contactless communication methods and protocols at 13 56 MHz e Passive target device for NFC IP 1 mode communication Peer to Peer e Card operation mode supporting ISO IEC 14443 A and FeliCa compliant protocol Thanks to the relevant solder bridges the host link of PTEV501B Evaluation board can be configured for e C e SPI AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014
21. hive zip E Export projects and references to archive Zip oa i i Ekes p Fig 33 Run the project Choose the desired project and click at the left side the Debug Button like shown at the example picture El Console Ee i Problems Q Memory amp Instruction Trace lt Search 13a Call Hierarchy COT Build Console PTEWSO1B CardEmu_LPC1227 Finished building target PTEYS 16 CardEmu LPC122 axt make no print directory post build Performing post build steps arm none eabl size PTEVS 1B CardEmu LPC1227 axt arm none eabi objcopy O bir PTEWS 16 CardEmu LPcl227 ber text data bss 41685 44 1664 hex filename agg PTEVS 16 CardEmu LPC1227 axt 14 25 28 Build Finished took im 245 556ms Fig 34 Run the project AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 22 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide After the build process one can see the size of the image in the console window 434 PHotetus L SCatTuSs 160 void pHal 8 LPC Link HID 16 16 EAn NAN g i Initializing LPC Link HID 16 1 pa Ss pa Som m om om Fig 35 Run the project The initialization of the LPC Link can take a few seconds p PN512 Polli ain File Edit Refactor Navigate Search Run Projec
22. hnologies Ltd Always trust software from Code Red Technologies Ltd E You should only install driwer software from publishers you trust How can I decide which device software is safe to install Fig 24 Windows Security dialog After the setup wizard has finished one can launch the newly installed IDE Completing the LPCXpresso Setup Wizard Setup has finished installing LPCXpresso on your computer The application may be launched by selecting the installed icons PRESSO Click Finish to exit Setup Launch LPCXpresso v4 1 Powered by Wicode_red Fig 25 LPCXpresso installation setup wizard 4 AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 17 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide r E Develop Welcome page LPCXpresso os ffir les File Edit Navigate Search Project Run Window Help ehi gtr By Eh BEBO CCs Eri sy S E X Develop amp v G Q e e JEENE v v i Project Ex 53 _ stat Core Regi 7a Periphera gt 0 Welcome 52 H vis aS file C nxp LPCXpresso_4 1 0_190 Ipcxpresso pages unregistered htm gt gt License type UNREGISTERED Code 1 sa Debug limit 8k Activation code not available ed i To request an activation code or to activate a license please select
23. inished one can start browsing the code Most interesting might be the main c which is located in src main c in the project Before one can run the project the Evaluation board with the PT501 needs to be connected to the computer Wait until the according drivers have been installed All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note COMPANY PUBLIC Rev 1 2 6 March 2014 277612 21 of 32 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide 5 3 Start the project One can quickly start the reader project by editing the main function in the module main c This function first performs the hardware initializations of the LPC1227 and the PT501 Detailed descriptions of the code in the form of comments are provided in the main c file This should provide a detailed overview of how to initialize certain components 5 3 1 Run the project Before running the project please ensure that the LPCXpresso with the PTEV501B Evaluation board is connected with the computer 1 Start Were P Import project s je New project ao Build all projects Debug F Build PTEWSO1B_CardEmuy_LPC1227 Debug a Clean PTEWSOIB CardErnu LPC1227 Debug EF Debug PTEVSOIB CardEmu_LPCi227 Debug 9 Edit PTEWSOLB CardEmu_LPCl22 project settings FN Import project s from XML Description ga Quick Settings JG Export projects to arc
24. ion included herein and shall have no liability for the consequences of use of such information 8 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication her
25. istered copy of LPCXpresso IDE Just confirm the dialog and follow the instructions on the Welcome Screen to get a registered version without the debug limit of 8k The registration is free and needs one to navigate to the website of Code Red The Link is shown in the menu Help gt Product activation gt Create Serial number and Activate O ci Help Contents TP Search Dynamic Help Key Assist Ctrl Shift L Tips and Tricks Product activation Support About LPCApresso Upgrade your product Fig 27 Product activation AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 18 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide Create Seral number and Activate Select OK to visit the registration website where you can register your product and receive an Activation Code Copy Serial Number to clipboard Fig 28 Product activation If one doesn t already have an account at Code Red please sign up to get an activation code The code will be sent to the provided e mail address Window Help i Cal 7 Help Contents vey te B 6 Qr P Search gt Dynamic Help Key Assist Ctrl Shift L Tips and Tricks Product activation Display license type Supp
26. lay progress log Reopen on completion F Reset target on completion Repeat on completion Run flash command and copy to clipboard P Just copy flash command to clipboard Connection Options Use JTAG interface LPC Link HID Options Speed 250 Flash Oriver Flash driver LPC1L 12 13 128k BK cte Program flash memory Erase flash mi Algorithm W Mass erase Erase by page Fig 40 Program Flash wizard with Erase flash memory tab 6 1 2 Changing the NDEF message The predefined NDEF message can be changed in the following files e T4T src nxprdlib comps phce7816p4T_ Apps phce7816p4T T4T Const c AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 26 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide 1ain c phee Siip4sT_T4T_Constc 53 include lt phce sl6p4T T4T h gt define NORMAL def ine MAX SMGARTPOSTER 1 define BIG MIME IMAGE 2 define MAX _YCARD 3 Go J m A fe w Po detine this te one of the above idef ine T4T_NDEFFILE PREDEF NORMAL DEF predefined content 11 f f This is the data structure returned by the GetData on tag GetVersion 12 const byte TLY_VWERSION 13 Pl GETOATA TAG VERSION P2 GETDATA TAG VERSION bytej xl header version informat 14 foytey l bytel s ff year i
27. n ASCII 15 oytej e byte 1 ff month in ASCII 16 byte 1 fbytei S ff day in ASCII 1 oytey 18 foyte N byte x byte P Fig 41 Change NDEF content for T4T e 72T src nxprdlib comps phceT2TCmdHdl src Sw phceT2T_Const c Le main c le pheeT2T_Constec 23 include phceT T_Sw le define NORMAL define MOM SMARTPOSTER 1 define BIG MIME IMAGE 2 define MAX VCARD 3 ff define this to one of the above for NDEF predefined content define T4T NDE NORMAL Bu oo sy on A P Le ba e const uint t T2T_LOCK_CC_DEF 16 12 axa Axa Ax x internal bytes 13 axa Axa Ax x internal bytes 14 axa Axa Ax AxA internal bytes AND 15 ff static lock bytes 16 ff CE 17 Q xE1 x10 x Ox e 3rd byte data mem 18 ji 19 A Fig 42 Change NDEF content for T2T AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 27 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide 6 1 3 Program flow Initialize BAL Apply Protocol Settings Bus Abstraction Layer for Card Emulation mode phbalReg_Lpc12XXSpi_Init phhalHw_ApplyProtocolSettings Initialize HAL Hardware Abstraction Layer phhalHw_Pn512_Init Initialize OSAL Operating System Abstraction Layer phOsal_Lpc12xx_Init W
28. ne would like to use a different CLK source as described above the external clock signal should be connected to pin OSCIN by connecting to one of the component pads shown in Figure 15b a Fig 15 Schematics of the PTEV501B clock input 27 12MHz C30 15pF R31 GND 3 2 Software configuration 3 2 1 AN11461 This section describes the software configuration for the PTEV501B with an external clock source This can either be the CLKOUT function of the LPC1227 or any stable clock signal in the frequency range of 1 MHz to 33 MHz LPC1227 LPCXpresso Board as clock source Please make sure to change the hardware configuration as defined in section 3 before loading and running the modified software package into the LPC1227 to avoid breaking any hardware All information provided in this document is subject to legal disclaimers Application note COMPANY PUBLIC NXP N V 2014 All rights reserved Rev 1 2 6 March 2014 11 of 32 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide To use the PTEV501B with the LPC1227 LPCXpresso Board as external clock source some modifications need to be done in the system_LPC12xx c file 3 2 1 1 Configure the Main Clock For this example configuration a frequency of 24 MHZ is used To achieve this following settings of the SYSPLLCTRL register are required The SYSPLLCLKSEL_Val 0x01 for System Oscillator defines the clock source for the in
29. ock is assumed to be a disturbance and the card cannot be used This is the case e g if an external clock of 2 MHz is provided on the CLK input pin To use other frequencies than 13 56 MHz the RF clock frequency check can be disabled by register settings See 3 2 Software configuration Note The correct register settings to disable the frequency check are mandatory if a clock below 23 MHz is used between 23 MHz and 33 MHz it can be enabled Hardware configuration The PTEV501B is prepared to be used in conjunction with an on board crystal oscillator or a clock generated by the LPC1227 LPCXpresso Board The following table describes the necessary soldering changes for the different configurations PT501 clock configuration R31 can be placed as 0Q resistor or solder bridge Clock source R31 XT1 C29 C30 Crystal oscillator default Not placed 27 12 MHz 15pF 15pF External clock from LPC1227 LPCXpresso Board 00 Not placed Not placed Not placed Fig 13 Crystal oscillator as clock source default AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 COMPANY PUBLIC 277612 10 of 32 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide 9 0E y o A 231 com E a me Ol i Fig 14 LPC1227 as clock source Figure 15a shows a Snippet of the PTEV501B schematics If o
30. on note Rev 1 2 6 March 2014 8 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide N HI INTERFACE CONFIG SPI e RIO Bi Hrs R12 je amp 00000000000 3 i Blueboard PTEVSO1 Fig 11 Blueboard in SPI configuration a4 e The C address can be configured either by software or by hardware To set the C address by hardware the solder jumpers in the I C config section see Figure 11 has to be connected appropriately R3 R7 and R13 are logically LOW and R4 R8 and R15 logically HIGH spili E il siilj Fig 12 Blueboard in I C configuration AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 9 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide 3 PT501 clock requirements 3 1 Table 4 The PT501 is characterized to a frequency of 27 12 MHZ but it is possible to operate it with a frequency between 1 MHz and 33 MHZ on pin OSZIN As clock source any stable CLK signal in this frequency range can be used To avoid that unwanted noise disturbs the clock the PT501 has an internal frequency check The operating frequency of 13 56 MHz and the expected 13 56 MHz derived from the 27 12MHz clock source are compared If the frequencies differ too much the received RF cl
31. ort H E teate Serial number and Activate Install New Software vid About LPCXpresso W Upgrade your product Fig 29 Product activation Once the activation code arrives please open the activation window by pointing to Help gt Product activation gt Enter Activation code and enter the code The success of the product activation will be confirmed by an info dialog 5 2 Extraction of the PT501 CE solution project Once the LPCXpresso IDE is installed on a Computer the sequence of installing the reference reader project is indicated e Start the LPCXpresso IDE e Select the option Import project s see picture below e Browse the zip archive AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 19 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide e LPCXpresso IDE unzips the software package e The software package is ready for use File Edit Navigate Search Project Run Window Heip SraeS B er amp bh ape oo foes Soe Wx ers iS Proje 3 ME Core Perip E ae gy Import archived projects zip i Import exisiting projects O RO663 NXP LPC1114 301 Fig 30 Importing a project into the LPCXpresso IDE At the Quick Panel on the left side choose Impo
32. pte your product to remove this restriction Help gt Product Activation License Restriction An UNREGISTERED copy of LPCXpresso may only be used for evaluation purposes Register and activate to remove this restriction LPCXpresso website to be able to obtain an W Quick 52 fil RedC 69 Varia 1 Help gt Product activation gt Create Serial number and Activate Your products serial number will be displayed x Write down the serial number or copy it into the clipboard E Start here fej New project Import project s s s Pre e ene Activ F F Build all project fi 2 ress OK and a web browser will be opened on the Activations page i If you are already logged in to the website the serial number will be completed for you a Build If you are not logged in you will need to login navigate to the My Registrations page and enter the products seria Clean number ad g Clean fl m F Debug A i al El Console 3 E Problems J Memory il Red Trace Preview ak ES aps Me ae o 33 Quick Settings v No consoles to display at this time 3 lt Project and File wizards x Import and Export i k Rinld anrd Gettinac workspace ca Fig 26 LPCXpresso IDE Directly after the first start of the Eclipse IDE one will see an info dialog that this is only an unreg
33. rt projects s AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 20 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN11461 AN11461 PTEV501B Quick Startup Guide Import project s Import project s Select the examples archive file to import Projects are contained within archives zip or are unpacked within a directory Select your project archive or root directory and press lt Next gt On the next page select those projects you wish to import and press lt Finish gt Project archive zip Archive C PT501 CardEmu LPC1227 zip Project directory unpacked Root directory Browse for more examples Press Browse for more examples to view the latest examples and download to your local drive Then use press Browse above to import into your workspace Fig 31 Importing a project into the LPCXpresso IDE Browse for more examples Cancel Browse the desired project and click Next Import project s d Select a directory to search for existing Eclipse projects p Projects 7 PTEVS01B_CardEmu_LPC1227 Ei Select All DeselectAll Refresh Copy projects into workspace E ext Finish Cancel Fig 32 Importing a project into the LPCXpresso IDE eT DEE When the import process has f
34. se execution of the running program 1 Instruction stepping mode disassembl Fig 38 Debug Buttons i Step into a function All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note COMPANY PUBLIC Rev 1 2 6 March 2014 277612 24 of 32 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide 6 Card Emulation Associated Project 6 1 Tag Type 2 and Type 4 Card Emulation This example only works with the LPCXpresso LPC1227 development board The PT501 supports 2 different operating modes e Passive target device for NFC IP 1 mode communication Peer to Peer e Card operation mode supporting ISO IEC 14443 A and FeliCa compliant protocol The card operation mode is passive mode in which the PT501 does not generate an RF field but acts as a card that modulates the field for communication with the reader The IC only supports parts of the ISO IEC 14443 A protocol the ISO IEC 14443 4 as well as the ISO IEC 7816 4 commands need to be provided by the Microcontroller A specification to store data for any kind of service and application is specified in the NFC Forum and it is called NFC Data Exchange Format Storing NDEF formatted data inside contactless card products as mapping models as well as the management of NFC forum device as a specific platform such as a NFC Forum Type 4 Tag are defined in 9 The following project shows an e
35. t Window Help Sv i S i aes amp bi CW seo tls Er SW F A SE a vr amp vy Y qa vr X Proj 8 HE Core Z Peri O 2 Debug i Seo ES FS gt 4 E PN512 Polling Debug C C MCU Application ES PNSI2 Polling a E MCU GDB Debugger 02 11 12 14 06 E Binaries p Thread 1 Running ri Includes nS arm none eabi gdb 02 11 12 14 05 amp src E NxpRdLib PublicRelease main c 335 amp phSubBal 153 unsigned int volatile i ec main c 154 uint8_ t reg data G8 startup 5 uint8 t buf 64 G config GS linker 7 for i 0x10007 i gt 05 x gt GS cmsis 9 phStatus t status GS driver bd 160 void pHal m MAb W Quie 33S _6 Varia 9 Brea 7 m uint8 t volatile card or tag_detected Start Xo 3 BFL Basic Function Library data parameter storage Te New project phhalHw Rc523 DataParams t halReader Import project s Build all proj Initialize GPIO sets up clock or Build all projects Debug g GPIOInit amp Build PN512 Polling Debug 170 ifndef TUSA of Clean PNS12 Polling Debug stage Debug PN512 Polling Debug E console 32 E Problems Gj Memory HM Red Trace Preview EBX S G8 8 B ri 5 Quick Settings v PN512 Polling Debug C C MCU Application C Users nxp workspces test PN512 Polling Debug PN512 Polling axf 02 11 1
36. ternal System PLL which must be activated by setting the SYSPLL_SETUP to 1 The SYSPLLCTRL_Val specifies the output frequency of the System PLL This can be configured by the Bits 0 6 of the SYSPLLCTRL register in this case a frequency of 24 MHz Other system clock settings may also be used as long as the LPC1227 generated clock is in the range as defined in section 3 Please refer to the LPC122x User Manual 6 and Data Sheet 5 for detailed description of the supported configurations The MAINCLKSEL_Val sets the clock source for the system Main clock 0x3 for the System PLL output main c c system _LPClie c es lan 1 7 define CLOCK SETUP 1 128 4 define MAINCLE SETUP 1 129 define 3Y505C SETUP 1 130 define SYSOsSccTRL Val OxOOO000000 13 l define SYSPLLCLESEL Val OxOOO000001 132 define SYSPLL SETUP 1 133 define SYSPLLCTRL Val OxOO000041 134 define MAINCLESEL Val OxOOO00003 Fig 16 Main Clock configuration 3 2 1 2 Enable the CLKOUT functionality To use the CLKOUT pin of the LPC1227 the CLKOUTCLK_SETUP has to be enabled The CLKOUTCLKSEL_Val specifies the clock source here 0x3 for the Main clock at 24 MHz so no further division by the CLKOUTCLKDIV_Val is needed 0x01 ic main c Lc system LPCldec E3 142 define PMUCFG SETUP D 143 define FMUCFG Val OxOO000400 144 define CLEOUTCLE SETUP 1 145 define CLEOUTCLESEL Val OxOOO00003 146 define CLEOUTCLEDIV Val OxOOO00001
37. urce default 10 LPC1227 as clock SOUICE ccccceeeeeeeeeeee es 11 Schematics of the PTEV501B clock input 11 Main Clock configuration c ccccccsseeeeeeeees 12 CLKOUT configuration cccccccesseeeeeeeeeees 12 CLKOUT setup configuration cceeeee 13 Register settings for the frequency check function IA MAIN C saree ccsaiensSecretemscabnentsecs janncatness 13 Enumeration of the LPCXpresso Board in Device Manager WIndOW ccs0cceeeeeeeeees 14 LPCXpresso installation setup wizard 1 15 All information provided in this document is subject to legal disclaimers Fig 22 Fig 23 Fig 24 Fig 25 Fig 26 Fig 27 Fig 28 Fig 29 Fig 30 Fig 31 Fig 32 Fig 33 Fig 34 Fig 35 Fig 36 Fig 37 Fig 38 Fig 39 Fig 40 Fig 41 Fig 42 Fig 43 PTEV501B Quick Startup Guide LPCXpresso installation setup wizard 2 16 LPCXpresso installation setup wizard 3 16 Windows Security dialog cccccsseeeeeeeeeees 17 LPCXpresso installation setup wizard 4 17 LPCXpresso IDE cccccecccseeeeceeeeseeeeseeeeees 18 Product Activation ccccccccseceseeeeeeeeeeeeneeees 18 Product activatiOn cccccccseceseeeeeeeeeeeeeeeees 19 Product activation cccccccseceseeeeeeeeeeeeeeeees 19 Importing a project into the LPCXpresso IDE 20 Importing a project into the LPCXpresso IDE 21 Importing a
38. www nxp com redirect lpcware com lpcxpresso downloads older 3 PTEV501 Evaluation board http www nxp com demoboard PTEV501 html 4 LPC1227 LPCXpresso Board www nxp com redirect embeddedartists com products Ipcxpresso lpc1227 xpr php 5 LPC122x family data sheet http www nxp com documents data_sheet LPC122X pdf 6 LPC122X family User Manual http www nxp com documents user_manual UM10441 pdf 7 Multipoint Connectors we used Grid Dimension 2 54mm at least 27 pins www nxp com redirect conrad at ce de product 741119 STIFTLEISTE 1 X 36 POLIG VERGOL RM 254 and www nxp com redirect conrad at ce de product 736427 BUCHSENLEISTE EINREIHIG 36 POLIG RM254 8 Direct link to the NXP Reader Library http www nxp com documents software 200310 zip 9 TYPE 4 TAG NFC Forum Type 4 Tag Operation Specification Version 1 0 March 13 2007 www nxp com redirect nfc forum org specs AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 29 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN11461 8 Legal information 8 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of informat
39. xemplary implementation of a Tag 4 Type Card on the PN501 Therefore one NDEF File and one capability container CC file with ISO file identifier ISO FID equal to E103h are presented to the reader 6 1 1 Configuration of the example project In order to change some of the possible options before compiling the project the file src nxprdlib intfs phCardEmu_Options h should be edited This file contains toggles to enable disable the T2T and T4T functionality memory sizes as well as the pin numbers in which the PT501 chip is connected to the LPC1227 Further options are also indicated on the file Before flashing the modified project it is mandatory to perform a Mass erase on the flash memory of the LPC1227 This can be achieved by clicking the Program Flash icon in the LPCXpresso IDE 7 O Q el e 8 if Gis Program Flash Fig 39 Program Flash icon in LPCXpresso IDE In the Program Flash wizard the Mass erase feature can be found in the Erase flash memory tab After activating the Mass erase algorithm click OK to perform the procedure AN11461 All information provided in this document is subject to legal disclaimers NXP N V 2014 All rights reserved Application note Rev 1 2 6 March 2014 25 of 32 COMPANY PUBLIC 277612 NXP Semiconductors AN1 1 461 PTEV501B Quick Startup Guide Program Flash using LPC Link Probe v1 3 Program target flash LAC ILe NXP LPCL22 7 501 Options Disp
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