PB-TIM2 User`s Manual Preface PB-TIM2
Contents
1. CALI R27 ROR R26 R R30 CA4 pos R32 CAIS CA12 N E a CAIS CA13 Da R58 R54 O 1996 PEP Modular Computers July 30 1997 Page 3 1 Chapter 3 Configuration PB TIM2 User s Manual 3 1 1 Input Electrical Specification The 10 inputs 3 per counter and one common are all optoisolated from the supply with a rating of 1500V Isolation between the inputs is rated at 100V The inputs A B and C all have separated differential inputs while the common clear is referenced to V The inputs are protected against reverse voltage and sink typically 15mA Note For those customers possessing the PB TIM2 without optoisolation for improved speed performance the TTL inputs need to be inverted to maintain the characteristics laid down in this manual The inputs may be configured to cater for different operational voltages and frequency limits 3 1 1 1 Input Voltage Selection The following table shows the association between component values and operational voltages Component Di D3 D5 D8 5V Operation 12V Operation 24V Operation 0 Ohm Resistor 6 8V Zener Diode 18V Zener Diode C2 D19 Clear D22 Page 3 2 1996 PEP Modular Computers July 30 192. Write Only Register Address Bit After Reset Where WDATA This contains the bit that has to be written to the EEPROM CS The status of the EEPROM chip select 0 disabled 1 enabled e CLK Value of the SPI clock pin to access the EEPROM Data is written to the EEPROM at one bit at a time and only then when the EEPROM is chip selected This serial bit transfer is clocked with the SPI clock 4 2 14 Read EEPROM Access Register Read Only Register Address Bit After Reset Where RDATA This shows the current value of the SPIDI SPI data input 4 2 15 Software ID Byte Read Only Register Address Bit After Reset The value is 01 and allows identification of the FPGA program version Changes in the FPGA program will be reflected in this ID byte such that the software can automatically adjust Page 4 8 1996 PEP Modular Computers July 30 1997 PB TIM2 User s Manual Chapter 4 Programming 4 2 16 Hardware ID Byte Read Only Register Bit After Reset The value is always E1 July 30 1997 O 1996 PEP Modular Computers Page 4 9 Chapter 4 Programming PB TIM2 User s Manual This page has been left blank intentionally Page 4 10 O 1996 PEP Modular Computers July 30 1997 PB TIM2 User s Manual Chapter 5 Pinouts 5 5 PINOUTS The PB TIM2 has three sets of connectors ST100 with 15 pins is the left most with reference to the diagram
3. connector and on the front panel of the VMOD 2 or IMOD to indicate connections The connector splits virtually in half pins 1 to 24 and 27 to 50 for connection to the piggybacks B and A respectively For more information on the VMOD 2 IMOD series of PEP MODPACK carrier boards refer to the relevant manual Note July 30 1997 1996 PEP Modular Computers Page 5 5 Chapter 5 Pinouts PB TIM2 User s Manual This page has been left blank intentionally Page 5 6 1996 PEP Modular Computers July 30 1997
4. pz S ps ena ten fa ESG 4 Te SE AA AAA 2 5 2 3 5 Frequency Measurement cccccciciclc eee eee 2 5 2 3 6 Square Wave Generation sita oto aie eed Bee ee a ee es Re ee 2 5 2331 PWM Generation a 245 deda sy l Pa ab ob ws be Ba by Ne oe a das 2 5 2 3 8 Input Signal Edge Sampling 0 0 ee eee 2 5 2 3 9 Event Signal Duration sr daa tora SOR bees BAe BS 2 asua ag pe ee dde 2 5 3 Configuration 13544 Abd pred d foe DAI R ch Ler a cds dop O a O Pa 3 1 3 1 Board OVERVIEW Wise E o at Nab hy Je ee 3 1 3 1 1 Input Electrical Specification lt w ee Eso 3 2 3 1 1 1 Input Voltage Selection lt 3 2 3 1 1 2 Input Frequency Response lt eee 3 3 3113 Input EMI Brotecton n cs za ed dt Ee dep n ne 3 3 3 1 2 Output Electrical Specification lt lt ee eee 3 4 3 1 3 MODPACK Timing Specifications lt lt ee eee 3 4 Z ProsTammno dr a os sd bok 4 1 4 31 VMEbus Interface aca ys bb A pos ny A ee a A odpo 4 1 4 1 T PB TIM2 Address Map seas su a ys E wee ea ee ON tes ae ES A N ES 4 1 4 2 Register Allocation e e a a e a ee 4 2 4 2 1 Channel Control Register semere ketene eea Ea ee Se SUYO Y 4 2 4 2 2 Channel Mode Register 22 say uya A A A S ed Bat ve Sa 4 2 4 2 3 Channel Interrupt Pending Register rss ee eee 4 3 4 2 4 Channel Interrupt Clear Register 22 eee 4 4 4 2 5 Channel Interrupt Authorization Register ee eee 4 4 4 27 6 Prescaler Value z ys
5. the local C clear input or common clear The software allows the prescaler value s to be set enables or clears the timer s defines the edge selection on the trigger input A and whether the B gate input is edge or level sensitive In addition it gives interrupt authorization on comparison zero detect input A or B and identifies clears pending interrupts and configures the timer as a ring counter sets the counter direction up or down and defines when or from which source the timer should be reloaded When accessing the board registers the piggyback will generate a DTACK on each memory location reading a location that is not registered in the address map will produce irrelevant data FF Timer and comparator values are 16 bit and may be accessed as either 3 consecutive bytes or as 2 consecutive words Upon initialization the process should verify the board s hardware and software IDs 2 3 Timer Operating Modes Table 2 3 1 summarizes the timer possibilities indicating the input and output functions the interrupt possibilities the measurement results and the timer modes Table 2 3 1 Timer Characteristics Mode Timer Compare Software A B C Output IRO Result Register Control Hard Count Period Load on Clear Passive On 0 single down edge counter if O shot output stop at 0 load on A Soft Count Software Clear Passive On 0 single down load counter if O shot output st
6. the timer all 0 s and the output Toggle flip flop when this bit is set to 1 e Enable Enable timer operation i e starts the timer or single measurement when this bit 1s set to 1 e Load Loads the timer with the Comparator Preset register value when set to 1 4 2 2 Channel Mode Register Write Only Register Channel Address Bit Function Reload After Reset 0 Where AINOand1 Defines the input mode AIN 1 AINO Mode 0 0 Rising Edge 0 1 Falling Edge 1 X Both Edges BINO Defines input B level or edge 0 active high rising edge 1 active low falling edge BINI Defines input B level or edge 0 level 1 edge operation Page 4 2 1996 PEP Modular Computers PB TIM2 User s Manual Chapter 4 Programming e Mode 0 amp Mode 1 Defines the timer mode Mode Value Function 0 0 Stops on 0 or B event 0 1 Ring Counter 1 0 Counts down input A loads counter 1 1 Counts up input A used as a strobe e Reload Defines timer mode 0 does not reload 1 reloads on 0 Output Defines output operation 0 passive if 0 in timer 1 toggles on timerr 0 detection 4 2 3 Channel Interrupt Pending Register Read Only Register Channel 0 1 2 Address 09 29 49 Bit Function After Reset Where Match A 1 in this location means an interrupt pending o
7. 0 14 11 39 30 12 Piggyback A 38 46 13 37 13 14 36 29 15 35 45 16 34 12 17 33 28 18 32 44 19 31 11 20 30 2 21 29 43 2 Page 5 4 1996 PEP Modular Computers July 30 1997 PB TIM2 User s Manual Chapter 5 Pinouts 28 10 23 27 26 24 Front Front Piggyback Front Front Piggyback Panel Panel ST102 Pin Panel Panel ST102 Pin VMOD 2 VMOD 2D Number VMOD 2 VMOD 2D Number Pin Nr Pin Nr Pin Nr Pin Nr 24 25 1 amp 2 23 41 25 amp 26 22 8 3 21 24 4 20 40 19 7 6 18 23 7 17 39 8 16 6 9 15 22 10 14 38 11 13 5 12 Piggyback B 12 21 13 11 37 14 10 4 15 9 20 16 8 36 17 7 3 18 6 19 19 5 35 20 4 2 21 3 18 22 2 34 23 1 1 24 An optional 50 way header behind the front panel connector has an identical pin out to the front panel connector It is provided for applications where the flat band cable is to be routed internally or where an alternative front panel is to be fitted and used In some cases cables can be routed through the systems interior i e To the back panel from this optional connector and some from the external connector on the front panel In doing so take care not to exceed the fan out ability of the piggyback s driver circuits With systems that have more than one of this type of connector or which use several VMOD 2 or IMODs with various piggybacks it is advisable to put a drop of paint on the back of the mating
8. 97 PB TIM2 User s Manual Chapter 3 Configuration 3 1 1 2 Input Frequency Response The following table shows the association between component values and maximum input frequency response Component C1 C2 C3 C4 C5 30 kHz 300 kHz 1 MHz 10nF Capacitor InF Capacitor 330pF Capacitor C6 C7 Default C8 C9 To reduce the cut off frequency larger capacitor values should be used The values provided in the table are provided as an example and have been simulated over the full operating temperature range 3 1 1 3 Input EMI Protection The design allows for additional enhanced EMI protection by replacing the following components with a suitable SMD coil Component R34 R35 R36 R37 Default R38 0 Ohm Resistor R39 July 30 1997 1996 PEP Modular Computers Page 3 3 Chapter 3 Configuration PB TIM2 User s Manual 3 1 2 Output Electrical Specification The three outputs are all optoisolated from the supply with a rating of 1500V These channels use the common V and V supply rails and are equipped with an open collector circuitry that is capable of sourcing up to 200mA at a voltage difference of 24V between the V and V inputs The outputs are inductive load protected and function correctly within a voltage range between 5V and 30V 3 1 3 MODPACK Timing Specifications DTACK is generated on board and assumin
9. DUCTION 1 1 Product Overview 1 The PB TIN2 is an optoisolated general purpose timer piggyback for the VMOD 2 and CXM IMOD range of PEP boards Three independent timers with 16 8 bit resolution and possessing 9 modes of operation are galvanically isolated from the process Three inputs and an output per counter may be software configured 1 2 Ordering Information Product Description Order Nr PB TIM2 Modpack with 3 independently configurable timers possessing 3 13745 optoisolated 24V DC filtered inputs and 1 optoisolated 24V DC 200mA output per counter PB TIM2 Modpack with 3 independently configurable timers possessing 3 13746 optoisolated 12V DC filtered inputs and 1 optoisolated 24V DC 200mA output per counter PB TIM2 Modpack with 3 independently configurable timers possessing 3 13747 optoisolated 5V DC filtered inputs and 1 optoisolated 24V DC 200mA output per counter July 30 1997 1996 PEP Modular Computers Page 1 1 Chapter 1 Introduction 1 3 Specifications Page 1 2 PB TIM2 User s Manual Timer 16 bit up down synchronous counter 16 bit preset register 16 bit comparator 16 bit zero detection 16 bit last value latch 8 bit prescaler 1 bit toggle register Input Channels Trigger gate and clear together with a common clear All optoisolated and protected against reverse polarity Output Channels 1 digital output per counter 24V DC 200mA with induct
10. PB TIM2 User s Manual Preface PB TIM2 General Purpose 16 8 bit Timer Piggyback Order No 14257 User s Manual Issue 1 Preliminary Unpacking and Special Handling Instructions This PepCard product is carefully designed for a long and fault free life nonetheless its life expectancy can be drastically reduced by improper treatment during unpacking and installation Observe standard anti static precautions when changing piggybacks ROM devices jumper settings etc If the product contains batteries for RTC or memory back up ensure that the board is not placed on conductive surfaces including anti static plastics or sponges These can cause shorts and damage to the batteries or tracks on the board When installing the board switch off the power mains to the chassis Do not disconnect the mains as the ground connection prevents the chassis from static voltages which can damage the board as it is inserted Furthermore do not exceed the specified operational temperature ranges of the board version ordered If batteries are present their temperature restrictions must be taken into account Keep all the original packaging material for future storage or warranty shipments If it is necessary to store or ship the board re pack it as it was originally packed July 30 1997 O 1996 PEP Modular Computer Page 0 1 Preface PB TIM2 User s Manual REVISION HISTORY Revision History Manual Product Title PB TIM2 Publication Numb
11. ange of PEP MODPACK carrier boards The table shown below shows the signals related to this connector Signal Pin No Pin No Signal V 1 2 V Channel 0 A 3 4 Channel 0 A Channel 0 B 5 6 Channel 0 B Channel 0 C 7 8 Channel 0 C Channel 0 MATCH 9 10 Channel 1 A Channel 1 A 11 12 Channel 1 B Channel 1 B 13 14 Channel 1 C Channel 1 C 15 16 Channel 1 MATCH Channel 2 A 17 18 Channel 2 A Channel 2 B 19 20 Channel 2 B Channel 2 C 21 22 Channel 2 C Channel 2 MATCH 23 24 Clear V 25 26 V Note Channelx MATCH is a source signal generated from V Clear is an input signal related to V July 30 1997 1996 PEP Modular Computers Page 5 3 Chapter 5 Pinouts PB TIM2 User s Manual 5 1 4 ST102 VMOD 2 D IMOD Connection Figure 5 1 4 1 VMOD 2 D IMOD Front Panel p Pin 50 Pin 49 o ot Pin 50 ses Pin 23 0 0 e e ese e o 0 e ese ss e o Oo Pin 34 7 Pin 1 Pin 2 Pin 1 VMOD VMOD 2 2D Table 5 1 4 1 Front Panel Connector Pinout Front Front Piggyback Front Front Piggyback Panel Panel ST102 Pin Panel Panel ST102 Pin VMOD 2 VMOD 2D Number VMOD 2 VMOD 2D Number Pin Nr Pin Nr Pin Nr Pin Nr 50 50 142 49 17 25 amp 26 48 33 3 47 49 4 46 16 5 45 32 6 44 48 7 43 15 8 42 31 9 41 47 10 4
12. below ST101 sits to the right with 30 pins and ST102 with 26 pins is on the far right 5 1 Main Board Figure 5 1 0 Board Connectors Pin1 ST100 Pin26 Pin15 Cara CIO CO CO CIO CO CIO Be OJO OO oo CO CIO July 30 1997 O 1996 PEP Modular Computers Page 5 1 Chapter 5 Pinouts PB TIM2 User s Manual 5 1 1 ST100 Connector The ST100 connector fits the BU0A or BUOB sockets on the IMOD or VMOD 2 range of PEP MODPACK carrier boards The table shown below shows the signals related to this connector Pin Number Signal Pin Number Signal 1 GND 9 1D13 2 N C 10 1D12 3 N C 11 ID11 4 N C 12 ID10 5 N C 13 ID9 6 IDS1 14 ID8 7 ID15 15 GND 8 ID14 5 1 2 ST101 Connector The ST101 connector fits the BULA or BU1B sockets on the IMOD or VMOD 2 range of PEP MODPACK carrier boards The table shown below shows the signals related to this connector Signal Pin No Pin No Signal GND 1 2 Vec N C 3 4 N C R W 5 6 CLK RESET 7 8 UDTACK N C 9 10 CS N C 11 12 N C ID7 13 14 IDSO ID6 15 16 N C IDS 17 18 IA6 ID4 19 20 TAS ID3 21 2 N C ID2 23 24 N C ID1 25 26 N C IDO 27 28 IA1 GND 29 30 Vec 1996 PEP Modular Computers July 30 1997 PB TIM2 User s Manual Chapter 5 Pinouts 5 1 3 ST102 Connector The ST102 connector fits the BU2A or BU2B sockets on the IMOD or VMOD 2 r
13. ed of the possibility of such claims prior to the purchase of or during any period since the purchase of the product Please remember that no PEP Modular Computers employee dealer or agent are authorized to make any modification or addition to the above terms either verbally or in any other form written or electronically transmitted without consent July 30 1997 O 1996 PEP Modular Computer Page 0 3 Preface PB TIM2 User s Manual TABLE OF CONTENTS Chapter Section Sub section Page 1 Introduction Xi esta ek ae Abies Bote Rhee E E E pte a Ba se gt Bana Valen de sus 1 1 Vil Product OVEIview 3 tac Sa ate it ds eb ae hed BERS Ae oa he a es 1 1 1 2 Orderme Information css rias aaa a Ae Oe eo Ka ee SSS 1 1 1 3 AS POCIICALIONS A wees Melee gle ee brew edie 1 2 1 4 Board Overview mesa ss vo papas E bee ioe m plan PEE ERS Sl ee Res 1 3 S Features inks Sct Sates Soe Acid th Bs Jda A aw u hires Aare eM dn ON A au Slate R Oe er 1 3 2 Functional Description usas ee A ie Ae St V UE eed ea as 2 1 2 1 Normal Timer Mode u 348 A a s u aka Sa Ra a U 3 Ee 2 2 22 Board Operation otk ea ys ead a ddr ba ee eke gh uq S TOUR obora 2 3 2 3 Timer Operating Mod s usas s bv8 ea Re AROS RU A p BA PRS W SSS a 2 3 2 3 1 Hardware Single Shot Retrigerable lt oro 2 4 2 3 2 Hardware Single Shot lt s ss Sue boa ee AA ES 2 4 2353 JC Generation 3763 4 ts a A ee be il dhe be E pl See 2 4 2 3 4 Period Measurement
14. el interrupt clear register Page 4 6 1996 PEP Modular Computers July 30 1997 PB TIM2 User s Manual Chapter 4 Programming 4 2 11 Common Interrupt Authorization Register Write Only Register Address 69 Bit 7 6 5 4 3 2 1 0 Function CH 2 CH 1 CH 0 After Reset 0 0 0 Where CHx A 1 in this position authorizes interrupts from the corresponding timer 4 2 12 Interrupt Vector Write Only Register Address Bit Function After Reset Where gt V2 V7 Programmable interrupt vector bits Upon receipt of an INTACK signal the interrupt vector register is placed on the data bus e ISO amp IS1 Shows the interrupt source as in the following table IS1 ISO Interrupt Source 0 1 Channel 0 1 0 Channel 1 1 1 Channel 2 If an interrupt is generated a vector is placed on the data bus during the INTACK signal The upper 6 bits of this vector are user definable while the two lower bits define the interrupt source Pending interrupts are latched in a corresponding register and an interrupt may be cleared by writing a bit in the Interrupt Clear Register In the event that several interrupts have been generated the signals will remain active until all have been serviced Note All interrupt sources are edge triggered July 30 1997 O 1996 PEP Modular Computers Page 4 7 Chapter 4 Programming PB TIM2 User s Manual 4 2 13 Write EEPROM Access Register
15. er 14257 Issue Brief Description of Changes Rev Date of issue 1 First release of Issue 1 manual 1 19th Mar 1996 Date of issue the release date of the issue This date does not necessarily reflect the date the improvements were first made This document contains proprietary information of PEP Modular Computers It may not be copied or transmitted by any means passed to others or stored in any retrieval system or media without the prior consent of PEP Modular Computers or its authorized agents The information in this document is to the best of our knowledge entirely correct However PEP Modular Computers cannot accept liability for any inaccuracies or the consequences thereof nor for any liability arising from the use or application of any circuit product or example shown in this document PEP Modular Computers reserve the right to change modify or improve this document or the product described herein as seen fit by PEP Modular Computers without further notice Page 0 2 O 1996 PEP Modular Computers July 30 1997 PB TIM2 User s Manual Preface PEP Modular Computers Two Year Limited Warranty We grant the original purchaser of PEP products the following hardware warranty No other warranties that may be granted or implied by anyone on behalf of PEP are valid unless the consumer has the express written consent of PEP Modular Computers PEP Modular Computers warrants their own p
16. g a 16 MHz system clock and 4 MHz timer clock is generated 5 cycles after Chip Select and Data Strobes This condition is valid for both read and write cycles Page 3 4 O 1996 PEP Modular Computers July 30 1997 PB TIM2 User s Manual Chapter 4 Programmin 4 PROGRAMMING 4 1 VMEbus Interface 4 1 1 PB TIM2 Address Map Address Read Write Counter 0 01 FF Channel Control Register 05 FF Channel Mode Register 09 Channel Interrupt Pending Register Channel Interrupt Clear Register 11 FF Channel Interrupt Authorization Register 15 FF Prescaler Value 18 19 0 1A Counter Value Byte 1 Comparator Value Byte 1 1B Counter Value Byte 0 Comparator Value Byte 0 Counter 1 20 Same as Channel 0 Same as Channel 0 3F Counter 2 40 Same as Channel 0 Same as Channel 0 5F Common Registers 61 FF Common Control Register 65 Common Interrupt Pending Register 69 FF Common Interrupt Authorization Register 6D FF Interrupt Vector 79 Software ID Byte 7E Read EEPROM Access Register Write EEPROM Access Register 7F Hardware Byte July 30 1997 O 1996 PEP Modular Computers Page 4 1 Chapter 4 Programming PB TIM2 User s Manual 4 2 Register Allocation 4 2 1 Channel Control Register Write Only Register Channel Address Bit Function After Reset Where Clear Clears
17. he timer with the preset comparator register 2 3 2 Hardware Single Shot This mode is the same as the one described in 2 3 1 above except that the software starts the period directly by writing the bits ENABLE and LOAD in the Channel Control Register 2 3 3 TIC Generation The period is stored in the preload comparator register and upon zero detection the timer is reloaded and an event IRO is generated IRO plus flag Page 2 4 1996 PEP Modular Computers July 30 1997 PB TIM2 User s Manual Chapter 2 Functional Description 2 3 4 Period Measurement The timer is cleared by the software which also authorizes counting When input B is valid level sensitive gate i e goes high the timer starts counting until input B goes low again at which point an event interrupt is generated IRQ plus flag 2 3 5 Frequency Measurement The mode is the same as the one described in 2 3 4 above except that input B toggles on the rising and falling edges 2 3 6 Square Wave Generation The value of half the square wave period is stored in the comparator preload register with the timer being reloaded and the output toggling on each zero detection 2 3 7 PWM Generation For this mode two of the three timers are required with each providing one part of the signal The timer modes need to be set to single shot with an internal link between the two timers This procedure is explained in more detail in the section on programming 2 3 8 Input S
18. ignal Edge Sampling After a reset the timer operates in free run mode At each edge detection on the A input the current timer value is stored in the counter register and an event interrupt is generated IRQ and flag 2 3 9 Event Signal Duration After a reset the timer operates in free run mode when the B gate input is active A preset value can be placed in the preset comparator register that will react when the gate has been active for a given number of cycles The counter value returns the cumulated time of the active input B and in the event of an overrun an external event interrupt can be generated IRQ and flag July 30 1997 O 1996 PEP Modular Computers Page 2 5 Chapter 2 Functional Description PB TIM2 User s Manual This page has been left blank intentionally Page 2 6 O 1996 PEP Modular Computers July 30 1997 P B TIM2 User s Manual 3 CONFIGURATION 3 1 Board Overview Solder Side O CA1 CAS CA CAS R45 R44 R48 R46 R53 R52 R50 R49 R3 Rl R9 RS R19 R1 R13 R11 R37 R36 R41 R40 R39 R38 R35 R34 R42 R43 R21 R33 R24 R16 R8 cas Component Side CX1 R28 R29 a IC11 CALO x CIO Ici2 CX2 Chapter 3 Configuration
19. ive load protection high side switch Input Voltage SV 12V 15V or 24V Input Current 15mA typically Switching Level 2V 7 4V or 18 6V respectively Input Frequency Up to 300 kHz embedded filter Output Frequency Up to 10 kHz Isolation Voltages 1500V DC VO to system 100V DC between inputs Timer Clock 4 MHz 250 ns derived from 16 MHz System Clk DTACK Generation On board generation Environment Operating Temperature 0 C to 70 C Extended Temperature 40 C to 85 C Storage Temperature 55 C to 85 C Humidity 0 to 95 non condensing Piggyback Size Width 48 mm Length 102 mm Depth 10 mm Modpack Interface 16 Bit data bus 1996 PEP Modular Computers July 30 1997 PB TIM2 User s Manual Chapter 1 Introduction 1 4 Board Overview ptoisolation Stage assasasssaassass seesessseessee 1 5 Features 3 independent timers 16 bit resolution 8 bit prescaler 9 different modes 3 inputs per timer software defined 1 output per timer software defined common clear software defined 1 EEPROM 2 kbit for software driver parameter backup for future use inputs with optoisolation RC filters and configurable thresholds input freguency up to 300 kHz outputs with optoisolation and open collector source circuitry high side switch out
20. ling factor is 256 Page 4 4 1996 PEP Modular Computers July 30 1997 PB TIM2 User s Manual Chapter 4 Programming 4 2 7 Counter Value Read Only Register Bit After Reset Bit After Reset 4 2 8 Comparator Value Write Only Register Bit After Reset Bit After Reset July 30 1997 O 1996 PEP Modular Computers Page 4 5 Chapter 4 Programming PB TIM2 User s Manual 4 2 9 Common Control Register Write Only Register Address 61 Bit Function After Reset Where STx Authorizes common clear function on corresponding channel TIN2 Defines the operation of timer channel 2 A 1 in this location will link the output of channel 0 to the counter clock of channel 2 channel 0 and 2 will also be cascaded PWM 1 Defines the operation of channel 1 A 1 in this location will internally link the output of channel 0 to the A input of channel 1 and the output of channel 1 to the A input of channel 0 With this configuration both channels generate half a Pulse Width Modulation signal 4 2 10 Common Interrupt Pending Register Read Only Register Address Bit Function After Reset Where CH x A 1 in this position means an interrupt pending from the corresponding channel Note If an interrupt is pending from a given channel then the only way to clear it is to use the chann
21. n MATCH Gate A 1 in this location means an interrupt pending on GATE input B Zero A 1 in this location means an interrupt pending on zero crossing Trig A 1 in this location means an interrupt pending on TRIG input A July 30 1997 O 1996 PEP Modular Computers Page 4 3 Chapter 4 Programming PB TIM2 User s Manual 4 2 4 Channel Interrupt Clear Register Write Only Register Channel Address Bit Function After Reset Where Match A 1 in this location will clear an interrupt pending on MATCH Gate A 1 in this location will clear an interrupt pending on GATE input B Zero A 1 in this location will clear an interrupt pending on zero crossing Trig A 1 in this location will clear an interrupt pending on TRIG input A 4 2 5 Channel Interrupt Authorization Register Write Only Register Channel Address Bit Function After Reset Where Match A 1 in this location authorizes an interrupt on MATCH Gate A 1 in this location authorizes an interrupt on GATE input B Zero A 1 in this location authorizes an interrupt on zero crossing Trig A 1 in this location authorizes an interrupt on TRIG input A 4 2 6 Prescaler Value Write Only Register Channel Address Bit After Reset After reset the default value for b0 is 1 if all the bits are cleared 0 then the presca
22. op at 0 Tick Count Period Enable Clear Passive On 0 down counting counter if O output load at 0 Ring Ring counting mode Mode Timter Compare Software A B C Output IRO Result Register Control July 30 1997 1996 PEP Modular Computers Page 2 3 Chapter 2 Functional Description PB TIM2 User s Manual Measure Count up Enable Up Clear Counter period counting count counter register enable output Stop on v stop On Bv B counting Measure Count up Enable lv Clear Counter freg counting count counter register enable output Stop on 2v stop On 2nd B counting Bv Generate Count Half Enable Clear Toggle at freg down period counting counter 0 output Load at 0 Ring Ring counting mode 1 2 Count Half Enable Load on Clear Passive PWM down cycle counting edge counter if O output Stop at 0 load on A Edge Count up Enable Clear On A Counter sampling counting counter edge register output Pulse Count up Thresh Enable Up Clear On Counter duration old counting count counter match register enable output With reference to table 2 3 1 a v on its own represents an edge 1v indicates the first edge and 2v represents the second edge 2 3 1 Hardware Single Shot Retrigerable In this mode the timer always counts down the pulse duration is stored in the comparator register and the output acts as zero detection with input A used to load reload t
23. put frequency up to 10 kHz board ID E1 software ID 01 full interrupt handling July 30 1997 1996 PEP Modular Computers Page 1 3 Chapter 1 Introduction PB TIM2 User s Manual This page has been left blank intentionally Page 1 4 1996 PEP Modular Computers July 30 1997 PB TIM2 User s Manual Chapter 2 Functional Description 2 2 FUNCTIONAL DESCRIPTION In timer mode the PB TIM2 requires that input A be used as a trigger input B as a gate and input C as a clear The block diagram of the piggyback is provided in figure 2 0 1 Figure 2 0 1 Block diagram of the PB TIM2 piggyback VMOD ST FPGA VMOD ST Control ISYSCLK u TM ISYSRES an em IIRW Timing F Schmitt Ez p MY Output IDS0 Logic Status Channel 1 Channel 2 Channel 3 Configuration RC Schmitt OPTO A B C Inputs Output RC OPTO A B C Inputs Output Common OPTO Clear RC Schmitt EEPROM July 30 1997 1996 PEP Modular Computers Page 2 1 Chapter 2 Functional Description 2 1 Normal Timer Mode PB TIM2 User s Manua With reference to the single channel block diagram of figure 2 1 0 below the input line A is used as a trigger input line B functions as a gate that disables the timer when active and the third input C may be used as a clear input An additional clear input is common to all three timers The output line acts as either non
24. roducts excluding software to be free from defects in workmanship and materials for a period of 24 consecutive months from the date of purchase This warranty is not transferable nor extendible to cover any other consumers or long term storage of the product This warranty does not cover products which have been modified altered or repaired by any other party than PEP Modular Computers or their authorized agents Furthermore any product which has been or is suspected of being damaged as a result of negligence misuse incorrect handling servicing or maintenance or has been damaged as a result of excessive current voltage or temperature or has had its serial number s any other markings or parts thereof altered defaced or removed will also be excluded from this warranty A customer who has not excluded his eligibility for this warranty may in the event of any claim return the product at the earliest possible convenience together with a copy of the original proof of purchase a full description of the application it is used on and a description of the defect to the original place of purchase Pack the product in such a way as to ensure safe transportation we recommend the original packing materials whereby PEP undertakes to repair or replace any part assembly or sub assembly at our discretion or to refund the original cost of purchase if appropriate In the event of repair refund or replacement of any part the ownership of the remo
25. ss ba va MU DUO Tapa RE a Mi 4 4 4 27 Counter Valle mret ss custe 54 308 DAS ER S S we AE Be be s 4 5 4 2 8 Comparator Valle 250 tata o ed Be eth Sa AA ee a ee eed 4 5 4 2 9 Common Control Register iii ewe Se FS ees UR See 4 A RB 4 6 4 2 10 Common Interrupt Pending Register 0 0 00 a 4 6 4 2 11 Common Interrupt Authorization Register 2 2 ee eee 4 7 4212 Interrupt Vector etann mirra CA i ua ERS eed a ew ae A 4 7 4 2 13 Write EEPROM Access Register 2 r ra e ae eee 4 8 4 2 14 Read EEPROM Access Register ee eee 4 8 4 2 15 Software ID Byte so msn 8058545865555 Saw Sa bees ee SESE wk wee le sa 4 8 4 2 16 Hardware ID Byte uso ms apaga bye apos A a pa Sle a be See ee oe 4 9 Page 0 4 1996 PEP Modular Computers July 30 1997 PB TIM2 User s Manual Preface 5 Pinouts A IA IS SR A A AA z de Ae o yo ORS LG a n 5 1 S TL Mami Board A WE eh le Seg ene ae baat he Mab te eel oe Brews bisa eee css 5 1 IA LISTO Connectors gas ele 8638 48388 t wu kS SAIS ss A Ah ias 5 2 3 1209T101 Connector A V nk A R V au ss 5 2 52153 ST102 Gonnector reis na es A A A AS A AS Bon w A 5 3 5 1 4 ST102 VMOD 2 D IMOD Connection 5 4 July 30 1997 1996 PEP Modular Computer Page 0 5 Preface PB TIM2 User s Manual This page has been left blank intentionally Page 0 6 1996 PEP Modular Computers July 30 1997 PB TIM2 User s Manual Chapter 1 Introduction 1 INTRO
26. ved or replaced parts reverts to PEP Modular Computers and the remaining part of the original guarantee or any new guarantee to cover the repaired or replaced items will be transferred to cover the new or repaired items Any extensions to the original guarantee are considered gestures of goodwill and will be defined in the Repair Report returned from PEP with the repaired or replaced item Other than the repair replacement or refund specified above PEP Modular Computers will not accept any liability for any further claims which result directly or indirectly from any warranty claim We specifically exclude any claim for damage to any system or process in which the product was employed or any loss incurred as a result of the product not functioning at any given time The extent of PEP Modular Computers liability to the customer shall not be greater than the original purchase price of the item for which any claim exists PEP Modular Computers makes no warranty or representation either express or implied with respect to its products reliability fitness quality marketability or ability to fulfill any particular application or purpose As a result the products are sold as is and the responsibility to ensure their suitability for any given task remains the purchaser s In no event will PEP be liable for direct indirect or consequential damages resulting from the use of our hardware or software products or documentation even 1f we were advis
27. zero detection or as a toggle function on zero detection Figure 2 1 0 Block diagram of a single channel Page 2 2 Last Value Match IRO Compare Val Clock Zero Detector 16 bit Comparator ue 8 bit Prescaler 16 bit Last Value Register 16 bit Timer Register 16 bit Compare Preset Register Zero Logic Toggle Logic Count Enable Logic O 1996 PEP Modular Computers OUTPUT July 30 1997 l PB TIM2 User s Manual Chapter 2 Functional Description 2 2 Board Operation After power up all outputs are passive and all registers are cleared including the interrupt registers Prescalers are set to divide by one and the counters are disabled Input A operates as a trigger responding to a rising edge signal input B operates as a gate that enables the counters when a voltage is applied input C is initialized as a timer clear and the common clear signal is disabled on all three timers Under normal operation the timers are able to be read transparently with continuous comparisons being made between the current timer value and zero or a preset value The timer outputs may be activated if the comparison shows a non zero value or may be toggled when the timer passes through zero The timers may be reloaded with a preset value through the use of the A input timer operation may be blocked by using the B or gate input while the counter s may be reset using
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