DNA/DNR-AO-333 Analog Output Board User Manual
Contents
1. 0 0000 cee eae 7 2 1 3 Configuring the Timing 0 0 0c ee eee 7 2 1 4 Writing DIa a 50 9 ELERE a eee eed Ga a 8 2 1 5 Monitoring the Voltage 1 6 eee 8 2 1 6 Cleaning up the Session 0 0 2 0 c eee eae 9 Chapter 3 Programming with the Low Level API 0 0 c eee eee eee eee 10 3 1 Configuration Settings 0 0 tenes 10 3 3 Data Representation 0000 ccc tees 12 3 5 Using the Board in ACB Mode auaa c eee tet tees 13 3 6 Using the Board in DMap Mode 0 00 cece ete 15 3 7 Example of Code for Monitoring Analog Output Voltages 5 17 Zs Copyright 2009 Tel 508 921 4600 www ueidag com Vers 1 0 b United Electronic Industries Inc Date June 2009 DNA AO 333_ManualTOC fm List of Figures Chapter 1 Introduction 0 0 c ee 1 1 1 DNA AO 333 Board erc cicedert ccneitesawectauesnnt cxacessvevesadessaceawacvsseeswacedetcvavbersien AEEA 4 1 2 Block Diagram of DNx AO 333 Device Architecture ccc ceeeeceeeeeeeeecteeeeeeeeneeeeeeeeaaas 4 1 3 DNx AO 333 DB 62 I O Connector PinOUt c cccccceeeeeeeeeeeeeeeeceaecaeeeeeeeeeeeeeeeeeneeas 5 1 4 Physical Layout of DNA AO 333 Board cccccceeeeceeeeeeeenneeeeeeeeaeeeeeeenaeeeeeeetieeeeeeeaas 6 1 5 Diagram of DNA AO 333 Board Position Jumper SettingS cecceeeeeeeeeeeeeeeeees 6 Chapter 2 Programming with the High Level API 000 eee cece 7 None2. fendif e Ee a ee eee ee Se a k Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 1 0 United Electronic Industries Inc Date June 2009 AO 333 Chap3 fm DNx AO 333 Layer Chapter 3 17 Programming with the Low Level API 3 7 Example of The following code is an example of code written to perform the Guardian Code for diagnostic function of monitoring the analog output voltages The user can write Monitoring additional code to compare the measured readings with the expected values Analog and then take appropriate action Output Voltages portion of Sample333 c showing the readback of the analog output Set up the channel list a list of channels we want in the order we want it for i 0 i lt CHANNELS i cl i i fdata i 10 0 i make channels output 10V to 10V in 1V steps if fdata i gt 10 1 then 5V to 5V in 1V steps fdata i 16 0 ret DgAdv3xxWrite hd0 DEVN CHANNELS cl 0 data fdata if ret DgqAdv3xxWrite hd0 DEVN CHANNELS cl 0 data fdata lt 0 printf nError in DgAdv332Write error d n ret error found 1 goto finish up stop FALSE while stop ifdef WIN32 if _kbhit break fendif datarcvtt Sleep 2800 wait for conversion to occur use same channel list as before because it s already setup for what we need if ret DgAdv333ReadADC hd0 DEVN CHANNELS c
3. Chapter 3 Programming with the Low Level API 0c eee ee eee eee eee 9 None APPendiCes s a6 esbhd eee a eS See a Ate Cae aa eae ek a oe ee 18 None Zs Copyright 2009 Tel 508 921 4600 www ueidag com Vers 1 0 Qy Ve Eectronic Industries ine Date June 2009 DNA AO 333_ManualLOF fm Chapter 1 1 1 Organization Copyright 2009 all rights reserved United Electronic Industries Inc DNx AO 333 Board Chapter 1 Introduction Introduction This document outlines the feature set and use of the DNx AO 333 32 channel 16 bit analog output board s when used with the UEI Cube or RACKtangle I O chassis The DNA version is designed for use with UEI Cubes the DNR version is used with RACKtangle and HalfRACK rack type chassis The DNx AO 333 is a high density high precision analog voltage output board with an output range of 10 V that can drive 10 mA per channel The board has 32 independent DACs one for each channel with per channel digital offset and gain calibration that limits initial gain error to 450 uV and offset error to 305 uV All 32 channels may be configured to update either simultaneously or one at a time A 1024 sample FIFO on each channel allows each DAC to be updated at 10k samples sec without losing any data Double buffered outputs combined with low glitch DACs make the DNA AO 333 board an ideal choice for producing low frequency waveforms or for generating high precision swit
4. board position Power Connector External Circuits Figure 1 4 Physical Layout of DNA AO 333 Board 1 4 1 1 Jumper A diagram of the jumper block is shown in Figure 1 4 To set the board position Settings jumpers place jumpers as shown in Figure 1 5 Note that setting of jumper position is required only for DNA version boards and not for DNR version boards Layer s Position as marked on the Faceplate 1 0 2 1 0 3 1 0 4 1 05 1 0 6 9 10 0 0 oo 11 12 oo oo oo lo o oo 13 14 oo oo oo 15 16 x All I O Layers are sequentially enumerated from top to the bottom of the Cube o Open Closed Figure 1 5 Diagram of DNA AO 333 Board Position Jumper Settings Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 1 0 United Electronic Industries Inc Date June 2009 AO 333 Chap1 fm 6 Chapter 2 2 1 Programming with the UEIDAQ Framework API 2 1 1 Creating a Session 2 1 2 Configuring the Channels 2 1 3 Configuring the Timing Copyright 2009 all rights reserved United Electronic Industries Inc DNx AO 333 Board Chapter 2 Programming with the High Level API Programming with the High Level API This section describes how to program the DNA AO 333 boardr using the UEIDAQ Framework High Level API The UEIDAQ Framework is object oriented Its objects can be manipulated in the same manner within various development environments suc
5. kHz channel 320 kHz max aggregate FIFO Buffer Size 024 samples INL no load 4 LSB 0 012 DNL no load 1 LSB 0 003 Monotonicity 16 bits guaranteed over temperature Gain Calibration Error 450 uV typ Offset Calibration Error 305 pV typ Offset Drift Sppm C Gain Drift Sppm C Output Range 10 V Output Impedance 0 1 Q typ Current Drive 10 mA channel Settling Time 50 us to 16 bits Slew Rate V us Power up state 0 V 10 mV Output Monitoring Accuracy 2 44 mV Sample Update rate All 32 channels read in 2 4 seconds Digital 1 0 digital input 1 digital output logic level Isolation 350Vrms Power Consumption 2 0W 3W not including output loads Operating Temp tested 40 C to 85 C Operating Humidity Vibration IEC 60068 2 6 IEC 60068 2 64 95 non condensing 5 g 10 500 Hz sinusoidal 5 g rms 10 500 Hz broad band random 3 Shock IEC 60068 2 27 50 g 3 ms half sine 18 shocks 6 orientations 30 g 11 ms half sine 18 shocks 6 orientations MTBF 400 000 hours 1 2 1 Features The major features of the DNx AO 333 Analog Output board are as follows e 32 independent DACs e 16 bit resolution e 10 kHz per channel maximum update rate e 10 V output range 10 mA per channel e Low glitch output e Per channel offset and gain calibration e Simultaneous update across all channels if desired e Guardi
6. 21 4600 www ueidaq com Vers 1 0 Date June 2009 AO 333 Chap1 fm 1 DNx AO 333 Board Chapter 1 2 Introduction e Index This is an alphabetical index of topics covered in this manual NOTE A glossary of terms used with the PowerDNA Cube and Boards can be viewed and or downloaded from www ueidaq com Manual Conventions To help you get the most out of this manual and our products please note that we use the following conventions Tips are designed to highlight quick ways to get the job done or reveal good ideas you might not discover on your own NOTE Notes alert you to important information CAUTION Caution advises you of precautions to take to avoid injury data loss and damage to your boards or a system crash Text formatted in bold typeface generally represents text that should be entered verbatim For instance it can represent a command as in the following example You can instruct users how to run setup using a command such as setup exe Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 1 0 United Electronic Industries Inc Date June 2009 AO 333 Chap1 fm DNx AO 333 Board Chapter 1 Introduction 1 2 The Technical specifications for the DNx AO 333 Analog Output Board are listed in DNx AO 333 Table 1 1 Analog Table 1 1 DNx AO 333 Technical Specifications Output Board Technical Specifications Analog Outputs 32 channels Resolution 16 bits Max Update Rate 10
7. AY amp DQRdACfg Receive IOM crucial identification data DqCmdEcho hd0 DQRdCfg Copyright 2009 alll rights reserved Tel 508 921 4600 www ueidaq com Vers 1 0 United Electronic Industries Inc Date June 2009 AO 333 Chap3 fm DNx AO 333 Layer Chapter 3 16 Programming with the Low Level API for i 0 i lt DQ_MAXDEVN i if DQRdCfg gt devmod i printf Model x Option x n DORdCfg gt devmod i DQORdCfg gt option i else break STEP 2 Create and initialize host and IOM sides DqDmapCreate pDge hd0 amp pBcb UPDATE PERIOD amp dmapin amp dmapout STEP 3 Add channels into DMap for i 0 i lt CHANNELS i DqDmapSetEntry pBcb DEVN DQ SSOIN i DQ ACB DATA RAW 1 amp ioffset i DqDmapInitOps pBcb DgeSetEvent pBcb DQ eDataAvailable DQ ePacketLost DQ eBufferError D Q ePacketOOB STEP 4 Start operation DgeEnable TRUE amp pBcbh 1 FALSE STEP 5 Process data while keep looping DgqeWaitForEvent amp pBcbh 1 FALSE timeout amp eventsin if eventsin amp DQ eDataAvailable printf ndata for i 0 i lt CHANNELS i printf s04x uintl6 ioffset i Stop operation DgeEnable FALSE amp pBcb 1 FALSE STEP 6 Clean up DqDmapDestroy pBcb DqStopDQEngine pDqe DqCloseIOM hd0 ifndef WIN32 DqC leanUpDAQLib
8. GE1 1L lt lt 7 start trigger edge MSB define DQ LN STRIGEDGEO 1L lt lt 6 start trigger edge 00 software 01 rising 02 falling define DQ LN CVCKSRC1 1L lt lt 5 CV clock source MSB define DQ LN CVCKSRCO 1L lt lt 4 CV clock source 01 SW 10 HW 11 EXT define DQ LN CLCKSRCI1 1L lt lt 3 CL clock source MSB define DQ LN CLCKSRCO 1L lt lt 2 CL clock source 01 SW 10 HW 11 EXT define DQ LN ACTIVE 1L lt lt 1 STS LED status Tel 508 921 4600 Date June 2009 Vers 1 0 AO 333 Chap3 fm www ueidaq com DNx AO 333 Layer Chapter 3 11 Programming with the Low Level API define DQ LN ENABLED 1L lt lt 0 enable operations For streaming operations with hardware clocking select the following flags DO LN ENABLE DQ LN CVCKSRCO DQ LN STREAMING DQ LN IRQEN DQ_LN ACTIVE DQ _AO3xx_BI10 DNx AO 333 has a range of board specific settings as follows The following modes are reserved for future use define DQ AO3xx MODEFIFO 1L lt lt 19 continuous output with FIFO define DQ AO3xx_MODECONT 2L lt lt 19 waveform mode continuous define DQ AO3xx MODECYCLE xL lt lt 19 waveform mo regenerat define DQ AO3xx_MODEWFGEN 4L lt lt 19 waveform mode hardware DQ LN ENABLE enables all operations with the board DQ LN CVCKSRCO selects the
9. Inc Date June 2009 AO 333 Chap3 fm Board specific Commands and Parameters 3 5 Using the Board in ACB Mode DNx AO 333 Layer Chapter 3 13 Programming with the Low Level API Board specific functions are described in the DaqLibHL h file DqAdv3xxWrite This function works using underlying DqCmdIoct1 It uses the DOCMD_ 1 OCTL command with the DOTOCTL_ CVTCHNL function When this function is called for the first time the firmware terminates any ongoing operation on the device Then the firmware parses the channel list and writes the passed values one by one Therefore you cannot perform this function call when the board is involved in any streaming or data mapping operations Every write to the channel takes approximately 3 3yus Thus execution time for this function depends on the number of channels in the channel list This is a pseudo code example that highlights the sequence of functions needed to use ACB on the 333 board A complete example with error checking can be found in the directory SampleACB333 Note that we use the defines for a 3xx for a DNA AO 333 board STEP 1 Copyright 2009 all rights reserved United Electronic Industries Inc include PDNA h unit configuration word define CFG333 DQ LN ENABLED DQ LN ACTIVE DQ_LN GETRAW DQ LN IRQEN DQ LN _CVCKSRCO DQ LN STREA
10. MING DQ_AO3xx_MODEFIFO DQ AO3xx_BI10 uint32 Config CFG3xx Start DQE engine ifndef WIN32 DqInitDAQLib fendif Start engine DqStartDQEngine 1000 1 amp pDqe NULL IOM Open communication with hd0 DqOpenIOM IOM _IPADDRO TIMEOUT DELAY amp RdC fg Receive IOM crucial DQ_UDP_DAQ PORT identification data DqCmdEcho hd0 DQRdCfg Set up channel list for n 0 CL n n Tel 508 921 4600 Date June 2009 www ueidaq com n lt CHANNELS n Vers 1 0 AO 333 Chap3 fm DNx AO 333 Layer Chapter 3 14 Programming with the Low Level API STEP 2 Create and initialize host and IOM sides Now we are going to test device DqAcbCreate pDge hd0 DEVN DQ SSOIN amp bcb Let s assume that we are dealing with AI 201 device dquser initialize acb_structure Now call the function DqAcbInitOps bcb amp Config 0 TrigSize NULL pDQSETTRIG TrigMode SECT CIR Oy float CVC1k amp CLSize Ch 0 uint32 ScanBlock amp ach printf Actual clock rate f n f CLC1k Now set up events DgeSetEvent bcb DQ eFrameDone DQ ePacketLost DQ eBufferError DQ eP acketOOB Allocate data buffer datta dquser allocatebuffer Pre fill ACB with raw data dquser prefillbuffer data DgAcbPutScansCopy bcb data buffer bufsize buffer size in scan
11. ZN United Electronic wy Industries The High Performance Alternative DNA DNR AO 333 Analog Output Board User Manual Guardian Series 32 channel D A Boards for use with UEI PowerDNA Cubes DNA RACKtangle and HalfRACK DNR Chassis June 2009 Edition PN Man DNx AO 333 0609 Version 1 0 Copyright 1998 2009 United Electronic Industries Inc All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form by any means electronic mechanical by photocopying recording or otherwise without prior written permission Information furnished in this manual is believed to be accurate and reliable However no responsibility is assumed for its use or for any infringement of patents or other rights of third parties that may result from its use All product names listed are trademarks or trade names of their respective companies See the UEI website for complete terms and conditions of sale http www ueidaq com company terms aspx Contacting United Electronic Industries Mailing Address 27 Renmar Avenue Walpole MA 02081 U S A For a list of our distributors and partners in the US and around the world please see http www ueidaq com partners Support Telephone 508 921 4600 Fax 508 668 2350 Also see the FAQs and online Live Help feature on our web site Internet Support Support support ueidag com Web Site www ueidag com FTP Site ftp ftp
12. an diagnostic feature MUX and ADC monitors all analog output voltages to an accuracy of 2 44mV reading all 32 channels in 2 4 seconds Copyright 2009 all rights reserved United Electronic Industries Inc Tel 508 921 4600 Date June 2009 Vers 1 0 AO 333 Chap1 fm www ueidaq com DNx AO 333 Board Chapter 1 4 Introduction Figure 1 1 is a photo of the DNA AO 332 Board 120 pin DNA e bus connector Board Position Jumpers see Figure 1 4 Power eS DB 62 female 62 pin I O connector Figure 1 1 DNA AO 332 Board 1 3 Device The DNA AO 333 Analog Output Board has 32 individual analog output Architecture channels A Block Diagram of the board is shown in Figure 1 2 Control Logic 32 bit 66 MHz bus b e p U Q c f e 1S we 3 a J3 e2 2 c lt Optical Isolation Figure 1 2 Block Diagram of DNA AO 332 Device Architecture As shown in the diagram above the DNA AO 333 board uses an independent 16 bit DAC for each channel Offset and gain calibration data for each channel is stored in a calibration EEPROM which automatically corrects each data sample as needed A single digital input and a single digital output are also provided for general purpose use Note that complete electrical isolation is provided between the system bus logic and the external I O circuits Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 1 0 United Elec
13. ched stimuli A digital input is included for use as a trigger or as a general purpose digital input A single general purpose digital output is also provided Note The DIO function is not currently supported but will be in a later version Software for the board is provided as part of the UEIDAQ Framework package This provides an easy to use API that supports all popular Windows programming languages and most real time operating systems such as QNX RTX RT Linux and others The UEIDAQ Framework is also designed for use with LabVIEW MATLAB Simulink DASYLab and any ActiveX or OPC server application package This DNx AO 333 User Manual is organized as follows e Introduction This chapter provides an overview of DNA AO 333 board features accessories and what you need to get started e DNx AO 333 Board s This chapter provides an overview of the device architecture connectivity logic and accessories for the DNx AO 333 boards e Programming with the High Level API This chapter provides a general overview of procedures that show how to create a session configure the session and generate output on a DNx AO 333 board working with the UEIDAQ Framework High Level API e Programming with the Low Level API This chapter describes the Low Level API commands for configuring and using a DNx AO 333 board e Appendix A Accessories This appendix provides a list of accessories available for use with a DNx AO 333 board Tel 508 9
14. e DNx AO 333 on board clock The following sample shows how to configure the simple mode Please refer to the UEIDAQ Framework User Manual to learn how to use the other timing modes session ConfigureTimingForSimplelI0 Tel 508 921 4600 www ueidag com Vers 1 0 Date June 2009 AO 333 Chap2 fm 7 DNx AO 333 Board Chapter 2 Programming with the High Level API 2 1 4 Writing Data Writing data to the DNx AO 333 board is done with a writer object You can create a writer object that writes raw data straight to the D A converter You can also create a writer object that writes data scaled to volts Framework automatically performs a conversion to binary code before sending the data to the D A converter The following sample code shows how to create a scaled writer object and write a sample Create a reader and link it to the session s stream CueiAnalogScaledWriter writer session GetDataStream write one scan the buffer must contain one value for each channel double data 2 0 0 0 0 writer WriteSingleScan data Similarly you can create a raw writer object by entering the following Create a reader and link it to the session s stream CUeiAnalogRawWriter writer session GetDataStream write one scan the buffer must contain one value for each channel uInt16 data 2 0x1234 0x5678 writer WriteSingleScan data 2 1 5 Monitoring
15. h as Visual C Visual Basic or LabVIEW Although the following section focuses on the C API the concept is the same for any programming language you use Please refer to the UEIDAQ Framework User Manual for more information on using other programming languages Please refer to the examples that come with the UEIDAQ Framework They contain detailed and commented code that can be compiled and executed The Session object controls all operations on your PowerDNA device Therefore the first task is to create a session object by entering CUeiSession session Framework uses resource strings to select which device subsystem and channels you use within a session The resource string syntax is similar to a web URL as lt device class gt lt IP address gt lt Device Id gt lt Subsystem gt lt Channel list gt For PowerDNA the device class is pdna For example the following resource string selects analog output channels 0 1 on device 1 at IP address 192 168 100 2 pdna 192 168 100 2 Dev1 Ao0 1 Configure channels 0 1 with an output range of 10V session CreateAOChannel pdna 192 168 100 2 Dev0 ao0 1 10 0 10 0 You can configure the DNx AO 333 board to run either in simple mode point by point or buffered mode ACB mode In simple mode the delay between samples is determined by software on the host computer In buffered mode the delay between samples is determined by th
16. ing 7 Accesssories Creating a Session 7 DNA CBL 37 18 Data Representation 11 Architecture 4 DMap Mode 14 Low Level API 9 B Writing Data 8 Block Diagram 4 S Screw Terminal Panels 18 C settings clock 10 Cable s 18 Specifications 3 Calibration 18 Support ii Connector DB 37 5 Support email Connectors 5 support ueidaq com ii Support FTP Site F p ftp ueidaq com ii Support Web Site Framework High Level API 7 www ueidaq com ii J Jumper Settings 6 M Manual Conventions 2 Manual Organization 1 P Photo of DNA AO 308 board 4 Physical Layout 6 Programming ACB Mode 12 Channel List Settings 11 Commands and Parameters 12 Zz Copyright 2009 Tel 781 821 2890 www ueidaq com Vers 1 0 eee Date June 2009 File DNA AO 333_ManuallX fm
17. internal channel list clock CL source as a timebase AO 333 supports CV clock DQ _LN ACTIVE is needed to switch on STS LED on the CPU board O d O d You can select either the CL or CV clock as a timebase Because of the parallel architecture of AO 333 board either clock triggers all converters Aggregate rate Per channel rate Number of channels Note that acquisition rate cannot be selected on per channel basis e eee as Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 1 0 United Electronic Industries Inc Date June 2009 AO 333 Chap3 fm DNx AO 333 Layer Chapter 3 12 Programming with the Low Level API 3 2 Channel List The DNx AO 333 board has the following channel list structure Settings Bit Name Purpose Comments 31 LNCL_NEXT Tells firmware that there is a next entry n the channel list 21 DQ_LNCL_UPDALL Check update line to update all Reserved DACs 20 DQ_LNCL_WRITE Write data into the DAC but do Reserved not update 7 0 Channel number 3 3 Data DNxA AO 333 has 16 bit straight binary data representation Represent To convert voltage into an A D representation use the following formula lon atio Raw Volt Offset Span OxFFFF where Volt is the desired level in volts Copyright 2009 all rights reserved Tel 508 921 4600 www ueidag com Vers 1 0 United Electronic Industries
18. ion describes how to program the PowerDNA cube using the low level API The low level API offers direct access to PowerDNA DAQBIOS protocol and also allows you to access device registers directly We recommend that where possible you use the UEIDAQ Framework high level API see Programming with the UEIDAQ Framework API on page 7 which is easier to use than the low level API You need to use the low level API only if you are using an operating system other than Windows or if you are using a UEIPAC Programmable Automation Controller Configuration settings are passed in DgCmdSetCfg and DgAcbInitOps functions Not all configuration bits apply to DNA AO 333 board however The following bits make sense define DQ FIFO MODEFIFO 2L lt lt 16 continuous acquisition with FIFO define DQ LN MAPPED 1L lt lt 15 For WRRD DMAP devices automatically selected define DQ LN STREAMING 1L lt lt 14 For RDFIFO devices stream the FIFO data automatically selected For WRFIFO do NOT send reply to WRFIFO unless needed define DQ LN IRQEN 1L lt lt 10 enable board irqs define DQ LN PTRIGEDGE1 1L lt lt 9 stop trigger edge MSB define DQ LN PTRIGEDGEO 1L lt lt 8 stop trigger edge 00 software 01 rising 02 falling define DQ LN STRIGED
19. l rdata afdata lt 0 printf nError in DgAdv333ReadADC error d n ret error found 1 goto finish up for i 0 i lt CHANNELS i Copyright 2009 all rights reserved Tel 508 921 4600 www ueidag com Vers 1 0 United Electronic Industries Inc Date June 2009 AO 333 Chap3 fm DNx AO 333 Layer Chapter 3 18 Programming with the Low Level API print data and test lsbit of raw data to make indication that data is fresh printf n d fdata 6f Sc i afdatal i rdata i amp Ox1 printf n n limit the number of loops if TOTALSCANS 0 if TOTALSCANS amp amp datarcv gt TOTALSCANS stop 1 Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 1 0 United Electronic Industries Inc Date June 2009 AO 333 Chap3 fm A Accessories B Board Calibration STEP STEP STEP STEP STEP STEP 6 STEP 7 STEP 8 STEP 9 STEP 10 Copyright 2009 all rights reserved United Electronic Industries Inc fel a Ne a DNx AO 333 Layer Appendices The following accessory items are available for use with the DNx AO 333 board DNA CBL 62 This is a 3 ft 62 way flat ribbon cable with one 62 pin male and one 62 pin D sub connector It is used to connect the DNA AO 333 board to a 62 terminal panel such as the DNA STP 62 Calibration should be performed with a microvolt resolution voltmeter To calibrate the boa
20. rd first short circuit all 32 channel signal and return lines at the point of voltage measurement Run a serial terminal program attached to the IOM serial port Use simod 1 command to calibrate the board Please note that once you perform board calibration yourself the factory calibration warranty is void The calibration procedure for the DNA AO 333 Board using a serial port terminal is Type simod 1 Select the device to calibrate from the device table Remove the short circuit from Channel 0 and attach a voltmeter to it Repeat this step for each channel and output 10V to each by entering command a and value 0 Adjust the calibration of DAC 0 by entering command 0 and a hexadecimal value to set this DAC to 0x0 Oxff Adjust the calibration of DAC 0 to see 10 000V on channels 0 through 7 Output 10V on all channels by entering command a and value FFFF Attach voltmeter to channel 0 and adjust calibration to reach 10V on all channels with an error not to exceed 1mV When calibration is complete enter q command and reply y if you want to save calibration values into EEPROM Reset the PowerDNA cube to verify calibration For DNx AO 333 boards we recommend annual factory recalibration at UEI Tel 508 921 4600 www ueidaq com Vers 1 0 Date June 2009 AO 333 AppA fm DNx AO 333 Index A Configuration Settings 9 Configuring Channels 7 Accessories 18 Configuring the Tim
21. s bufsize minimum size amp size actual copied size from user buffer into ACB amp avail available free space in buffer STEP 3 Start operation Start operations DqeEnable TRUE amp bcb 1 FALSE STEP 4 Process data E a a a E U a a a a a a a Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 1 0 United Electronic Industries Inc Date June 2009 AO 333 Chap3 fm DNx AO 333 Layer Chapter 3 15 Programming with the Low Level API We will not use event notification at first just retrieve scans while keep looping DgeWaitForEvent amp bcb 1 FALSE EVENT TIMEOUT amp events if events amp DQ eFrameDone fill buffer with more data dquser prefillbuffer data DgAcbPutScansCopy bcb data buffer bufsize buffer size MINROQ minimum size amp size actual copied size from user buffer into ACB amp avail available free space in buffer STEP 5 Stop operation DgeEnable FALSE amp bcb 1 FALSE STEP 6 Clean up DgAcbDestroy bcb DqStopDQEngine pDge DqCloseIOM hd0 ifndef WIN32 DqCleanUpDAQLib endif 3 6 Using the include PDNA h Board in DMap Mode STEP 1 Start DQE engine ifndef WIN32 DqInitDAQLib fendif Start engine DqStartDQEngine 1000 10 amp pDge NULL open communication with IOM hd0 DqOpenIOM OM_ PADDRO DQ _UDP_DAQ PORT TIMEOUT DEL
22. the You can monitor the voltage measured at each output channel Voltage Use an Analog Input session the same way you would measure voltage from an Analog Input device The following code shows how to measure voltage out of the first 4 analog out put channels CUeiSession aiSs aiSs CreateAIChannel pdna 192 168 100 2 Dev1 Ai0 3 1 0 07 105 0 UeiAIChannelInputModeDifferential aiSs ConfigureTimingForSimplel0 CUeiAnalogScaledReader aiReader aiSs GetDataStream double voltages 8 aiReader ReadSingleScan voltages Copyright 2009 alll rights reserved Tel 508 921 4600 www ueidaq com Vers 1 0 United Electronic Industries Inc Date June 2009 AO 333 Chap2 fm DNx AO 333 Board Chapter 2 9 Programming with the High Level API 2 1 6 Cleaning up The session object cleans itself up when it goes out of scope or when it is the Session destroyed If you want to reuse the object with a different set of channels or parameters you can manually clean up the session with the following session CleanUp ee ee ee a ae Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 1 0 United Electronic Industries Inc Date June 2009 AO 333 Chap2 fm Chapter 3 3 1 Configuration Settings Copyright 2009 all rights reserved United Electronic Industries Inc DNx AO 333 Layer Chapter 3 10 Programming with the Low Level API Programming with the Low Level API This sect
23. tronic Industries Inc Date June 2009 AO 333 Chap1 fm DNx AO 333 Board Chapter 1 Introduction 1 4 Board Since the DNA AO 333 Analog Output board is designed with output buffers Connectors separate force and sense lines are not provided and Wiring 1 4 1 Connectors The pinout of the 62 pin connector for the DNA AO 332 board is shown in Figure 1 3 A physical layout of the board is shown in Figure 1 4 21 1 ELEELE ENAT 2 0202020800088008888 808 OO O27 AE 070 9 91010 020 99 62 43 Pin Signal Pin Signal Pin Signal 1 Gnd 22 AOut0 43 Gnd 2 AOutl 23 Gnd 44 AOut2 3 Gnd 24 AOut 3 45 Gnd 4 AOut4 25 Gnd 46 AOut5 5 Gnd 26 AOut6 47 Gnd 6 AOut7 27 Gnd 48 AOut8 7 Gnd 28 AOut 9 49 Gnd 8 AOut 10 29 Gnd 50 AOut 11 9 Gnd 30 AOut 12 51 Gnd 10 AOut 13 31 Gnd 52 AOut 14 11 Gnd 32 AOut 15 53 Gnd 12 AOut 16 33 Gnd 54 AOut 17 13 Gnd 34 AOut 18 55 Gnd 14 AOut 19 35 Gnd 56 AOut 20 15 Gnd 36 AOut 21 57 Gnd 16 AOut 22 37 Gnd 58 AOut 23 17 Gnd 38 AOut 24 59 Gnd 18 AQOut 25 39 Gnd 60 AOut 26 19 AOut 28 40 AOut 27 61 AOut 29 20 DIn0 41 Gnd 62 AOut 30 21 DOut0 42 AOut31 Figure 1 3 DNx AO 333 DB 62 I O Connector Pinout a a e Copyright 2009 all rights reserved Tel 508 921 4600 www ueidaq com Vers 1 0 United Electronic Industries Inc Date June 2009 AO 333 Chap1 fm DNx AO 333 Board Chapter 1 Introduction DNA 120 pin Bus Connector QOL vb Cb OL Factory Use Only See Figure 1 5 for jumper locations for setting
24. ueidag com Product Disclaimer WARNING DO NOT USE PRODUCTS SOLD BY UNITED ELECTRONIC INDUSTRIES INC AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS Products sold by United Electronic Industries Inc are not authorized for use as critical components in life support devices or systems A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Any attempt to purchase any United Electronic Industries Inc product for that purpose is null and void and United Electronics Industries Inc accepts no liability whatsoever in contract tort or otherwise whether or not resulting from our or our employees negligence or failure to detect an improper purchase Table of Contents Chapter 1 Introduction 0 0 ee 1 1 1 ONZA fc ose avian eed ae chat hh A Mee dats aes eda PA ae 1 1 2 1 Features 255 a24 tk E wide ea nee ake ae ea 3 1 3 Device Architecture eccc0 ee baie dee da bbe ee baa i ene ea bhd ae eda eed 4 1 4 Board Connectors and Wiring 0 0 cette 5 1 4 1 CONNMGCIONS erara ea ee ba nae Da Pe eae eee ee T 5 Chapter 2 Programming with the High Level API 2 00 c cece eee eee eee 7 2 1 Programming with the UEIDAQ Framework API 00 020 c eee eee eee 7 2 1 1 Creating a Session 0 eee eae 7 2 1 2 Configuring the Channels
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